JP2019204156A - Internal clock generation circuit, module for imaging and image processing device - Google Patents

Abstract

To provide an internal clock generation circuit, a module for imaging and an image processing device which enable data communication between own device and another device, even in a period when the frequency of a clock outputted from an internal oscillation circuit is corrected.SOLUTION: An internal oscillator 106 outputs an internal clock signal with accuracy lower than that of a clock signal for serial communication transmitted from a mother board. A frequency measurement unit 104 measures the frequency of the internal clock signal outputted from the internal oscillator 106, based on the clock signal for serial communication transmitted from the mother board. A frequency control unit 105a corrects the frequency of an internal clock outputted from the internal oscillator 106, based on a measured frequency and a target frequency.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an internal clock generation circuit, an imaging module, and an image processing apparatus.

  In order to acquire highly accurate image data in an image processing apparatus, it is required that a difference in brightness does not occur depending on the pixel area when a subject with the same amount of light is captured. It is also required that there is no difference in brightness depending on the elapsed time when subjects with the same amount of light are photographed.

  An imaging apparatus using an image sensor photoelectrically converts light from a subject using a photodiode in the image sensor. Electrons in the silicon are excited by the energy of light incident from the subject. The electrons are accumulated in the junction capacitance of the photodiode, whereby light is converted into an electric signal. The stronger the light intensity, the more electrons are excited. The longer the light is applied, the more electrons accumulate.

  In an imaging apparatus that monitors a change in state by comparing captured images at different times, when the frequency of the clock signal inside the imaging apparatus fluctuates due to a change in the state of the imaging apparatus itself, the light amount measurement time changes. The image becomes brighter when the measurement time of the light amount becomes longer, and the image becomes darker when the measurement time becomes shorter. That is, a difference in brightness occurs in the image due to the imaging device itself. As a result, the imaging apparatus cannot appropriately monitor the state change. Therefore, high accuracy of the clock frequency is required for the purpose of making the light amount measurement time for each captured image uniform.

  Even in a system in which an imaging module as a slave is connected to a mother board as a master, if the measurement time of the amount of light varies due to a temperature change around the imaging module, the captured image is affected. In order to suppress fluctuations in the light amount measurement time, it is necessary to increase the accuracy of the clock signal in the imaging module. In order to obtain a highly accurate clock signal, it is common to mount an oscillation circuit using a crystal resonator. However, the use of the crystal resonator increases the size of the substrate. While the motherboard is placed in a relatively large space inside the product, the imaging module is mounted on the surface of the product, so mounting a crystal unit on the imaging module side reduces the size of the system. The appearance is not good.

  For example, the image forming apparatus described in Patent Document 1 includes a master having a high-accuracy oscillation circuit and a slave having an oscillation circuit whose accuracy is lower than that of the master-side oscillation circuit. The master and the slave are connected by a serial communication signal line. The slave counts the transmission time of the predetermined data transmitted from the master to the slave based on the clock signal generated by the slave oscillation circuit. The slave calculates an error in the clock frequency of the slave oscillation circuit based on the count value and a predetermined time, and corrects the error. In Patent Document 1, since the slave oscillation circuit does not need to use a crystal resonator, downsizing of the image forming apparatus is not hindered.

JP 2011-150310 A

  In the image forming apparatus described in Patent Document 1, it is necessary to provide a correction period in order to correct the frequency of the clock output from the slave internal oscillation circuit. During the correction period, data communication between the master and the slave becomes impossible. In other words, data communication for operating the components on the slave side and correction of the frequency of the clock output from the slave internal oscillation circuit are performed in separate periods. As a result, the amount of payload data transmitted within a certain time is suppressed.

  Therefore, an object of the present invention is to provide an internal clock generation circuit, an imaging module, and image processing that enable data communication with other devices even during a period in which the frequency of the clock output from the internal oscillation circuit is corrected. Is to provide a device.

  In order to solve the above-described problems, the present invention provides an internal clock generation circuit in a first device capable of serial communication with a second device that generates a clock signal for serial communication. The frequency of the internal clock signal output from the internal oscillator is measured on the basis of the internal oscillator that outputs an internal clock signal with a lower accuracy than the clock signal and the serial communication clock signal transmitted from the second device. A frequency measurement unit; and a frequency control unit that corrects the frequency of the internal clock signal output from the internal oscillator based on the measured frequency and the target frequency.

  According to the present invention, data communication with other devices can be performed even during the period of correcting the frequency of the clock output from the internal oscillation circuit.

1 is a diagram illustrating a configuration of an image processing apparatus according to a first embodiment. It is a figure showing the communication system of SPI. 3 is a diagram illustrating a partial configuration included in an imaging module 302 of the image processing apparatus according to Embodiment 1. FIG. 2 is a diagram illustrating an example of an internal oscillator 106. FIG. FIG. 3 is a diagram illustrating a configuration of a frequency control unit 105a according to the first embodiment. 3 is a timing chart of frequency correction of an internal clock signal SCLK in the first embodiment. 6 is a diagram illustrating a configuration of a frequency control unit 105b according to Embodiment 2. FIG. 10 is a timing chart of frequency correction of an internal clock signal SCLK in the second embodiment. 6 is a diagram illustrating a configuration of an image processing apparatus according to Embodiment 3. FIG. 10 is a timing chart of frequency correction of an internal clock signal SCLK in the third embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a diagram illustrating the configuration of the image processing apparatus according to the first embodiment.

The image processing apparatus includes a mother board 301 and an imaging module 302.
A signal is transmitted between the mother board 301 and the imaging module 302 by serial communication.

  In this image processing apparatus, the mother board 301 is a master and the imaging module 302 is a slave. As a communication means between the master and the slave, a communication method conforming to the SPI (Serial Peripheral Interface) communication standard is used.

  The motherboard 301 and the imaging module 302 are connected by a clock signal line CLK, a signal line MOSI, and a signal line MISO.

  The clock signal line CLK transmits a clock signal MCLK for serial communication from the master to the slave.

  The signal line MOSI transmits a data signal DATA_I synchronized with the serial communication clock signal MCLK from the mother board 301 (master) to the imaging module 302 (slave). The data signal DATA_I is data for setting the imaging module 302, for example, data for setting a readout line or various modes.

  The signal line MISO transmits the data signal DATA_O synchronized with the clock signal MCLK for serial communication from the imaging module 302 (slave) to the mother board 301 (master). DATA_O includes image data generated by the imaging module 302.

  The mother board 301 (master) has a crystal oscillator using a crystal resonator. A clock signal MCLK for serial communication is generated by the crystal oscillator. The deviation of the oscillation frequency of the clock signal MCLK for serial communication of the mother board 301 (master) is about ± 0.001%.

  The imaging module 302 (slave) has an internal oscillator that uses a semiconductor integrated circuit instead of a crystal resonator. Therefore, the frequency deviation of the imaging module 302 (slave) is about ± 10%. Therefore, the accuracy of the clock signal MCLK output from the master is higher than that of the slave clock. Data signal DATA_I and data signal DATA_O are exchanged in synchronization with clock signal MCLK for serial communication. The data signal DATA_O including the image data generated by the imaging module 302 is transmitted in synchronization with the serial communication clock signal MCLK.

FIG. 2 is a diagram illustrating an SPI communication method.
The data signal DATA_I and the data signal DATA_O transition at the rising edge of the serial communication clock signal MCLK and are captured at the falling edge. Since serial communication normally handles 8 bits as one unit (1 word), an example using a communication format that outputs a clock signal for 8 cycles each time serial communication is performed will be described.

  As shown in FIG. 2, data in a predetermined bit unit is continuously shifted by shifting the data in the shift register in the SPI communication unit on the master side and the slave side for each cycle of the clock signal MCLK for serial communication. Send and receive. When communication is not performed, serial communication clock signal MCLK is not transmitted. The determined bit unit is one word (8 bits). Since the number of bits of one word is arbitrarily determined according to communication specifications, it may not be 8 bits.

  FIG. 3 is a diagram illustrating a partial configuration included in imaging module 302 of the image processing apparatus according to the first embodiment.

  The imaging module 302 includes an SPI communication unit 107 and an internal clock generation circuit 101.

  The internal clock generation circuit 101 includes a state detection unit 102, a state control unit 103, a frequency measurement unit 104, a frequency control unit 105a, an internal oscillator (OSC) 106, and a switch 108.

  The SPI communication unit 107 receives a high-accuracy clock signal MCLK for serial communication and a data signal DATA_I for serial communication. The SPI communication unit 107 supplies the clock signal MCLK to the internal clock generation circuit 101 and components not shown in the imaging module 302. The SPI communication unit 107 captures the value of the data signal DATA_I in synchronization with the falling edge of the clock signal MCLK, and uses the captured data signal DATA_I as a component (not shown) in the internal clock generation circuit 101 and the imaging module 302. Supply. The SPI communication unit 107 receives a data signal DATA_O from a component (not shown) in the imaging module 302 and holds it in the shift register. The SPI communication unit 107 outputs the data signal DATA_O by shifting the data of the shift register bit by bit in synchronization with the clock signal MCLK for serial communication.

  The state detection unit 102 detects the presence or absence of a rising edge of the clock signal MCLK and outputs the detection result to the state control unit 103.

  The state detection unit 102 sets the detection signal DE to a high level during a period from the falling edge timing of the first clock of the clock signal MCLK during the transmission of one word to the timing of the falling edge of the last (eighth) clock. To do.

  When the state control unit 103 receives the high-level detection signal DE from the state detection unit 102, the state control unit 103 operates the frequency measurement unit 104 and the frequency control unit 105a, and further sets the switch 108 to ON. When the state control unit 103 receives the low-level detection signal DE from the state detection unit 102, the state control unit 103 stops the frequency measurement unit 104 and the frequency control unit 105a, and further sets the switch 108 to OFF.

  The switch 108 receives the serial communication clock signal MCLK sent from the SPI communication unit 107. When the switch 108 is set to ON, the serial communication clock signal MCLK is sent to the frequency measuring unit 104. When the switch 108 is set to OFF, the serial communication clock signal MCLK is not sent to the frequency measurement unit 104.

  The frequency measuring unit 104 measures the frequency of the internal clock signal SCLK output from the internal oscillator 106 based on the clock signal MCLK for serial communication.

  Specifically, the frequency measuring unit 104 outputs the internal oscillator 106 during a period from the falling edge of the first clock of the clock signal MCLK to the falling edge of the last (eighth) clock during one word transmission. The number of pulses of the internal clock signal SCLK is counted. The frequency measurement unit 104 converts the number of pulses as a measurement result into the frequency A of the internal clock signal SCLK based on the frequency of the clock signal MCLK for serial communication.

  The frequency control unit 105a corrects the frequency control value C of the internal oscillator 106 based on the measured frequency A of the internal clock signal SCLK and the target frequency B of the internal clock signal SCLK. Specifically, the frequency control unit 105a is configured to reduce the frequency of the internal clock signal SCLK by a certain value when the measured frequency A is higher than the target frequency B for each transmission of one word of data. When the frequency A is smaller than the target frequency B, the frequency of the internal clock signal SCLK is increased by a certain value.

  The internal oscillator 106 outputs a slave-side internal clock signal SCLK. The internal oscillator 106 corrects the oscillation frequency of the internal oscillator 106 by changing the value of the capacitor in the internal oscillator 106 in accordance with the frequency control value C sent from the frequency control unit 105a. As a result, the frequency of the internal clock signal SCLK generated by the internal oscillator 106 is corrected. Depending on the configuration of the internal oscillator 106, the oscillation frequency of the internal oscillator 106 may be corrected by changing the resistance, the control voltage, and the control current.

FIG. 4 is a diagram illustrating an example of the internal oscillator 106.
As shown in FIG. 4, the internal oscillator 106 does not include a crystal resonator. The internal oscillator 106 is a relaxation type oscillator. Internal oscillator 106 includes a plurality of inverters IV1 to IV10, capacitive elements C1 to C14, NOR circuits NOR1 and NOR2, and N-channel MOS transistors N1 to N14.

  Capacitance elements C7 and C8 have a capacitance of 10C. The capacitances of the capacitive elements C6 and C9 are C. Capacitance elements C5 and C10 have a capacitance of 2C. Capacitance elements C4 and C11 have a capacitance of 4C. Capacitance elements C3 and C12 have a capacity of 8C. Capacitance elements C2, C1, C13, and C14 have a capacitance of 16C.

  Between the node ND1 and the ground, the capacitive element C1 and the NMOS transistor N1 connected in series, the capacitive element C2 and the NMOS transistor N2 connected in series, and the capacitive element C3 and the NMOS transistor N3 connected in series are connected in series. Capacitive element C4 and NMOS transistor N4 connected in series, capacitive element C5 and NMOS transistor N5 connected in series, capacitive element C6 and NMOS transistor N6 connected in series, capacitive element C7 and NMOS transistor N7 connected in series Arranged in parallel.

  Between the node ND2 and the ground, a capacitive element C14 and an NMOS transistor N14 connected in series, a capacitive element C13 and an NMOS transistor N13 connected in series, and a capacitive element C12 and an NMOS transistor N12 connected in series are connected in series. Capacitive element C11 and NMOS transistor N11 connected in series, capacitive element C10 and NMOS transistor N10 connected in series, capacitive element C9 and NMOS transistor N9 connected in series, capacitive element C8 and NMOS transistor N8 connected in series Arranged in parallel.

  Node ND1 is connected to the input of inverter IV5 and the output of inverter IV4. Node ND2 is connected to the input of inverter IV1 and the output of inverter IV7. The output of inverter IV5 is connected to the input of inverter IV6. The output of the inverter IV6 is connected to one input of the NOR circuit NOR2. The output of inverter IV1 is connected to the input of inverter IV2. The output of the inverter IV2 is connected to one input of the NOR circuit NOR1. The other input of the NOR circuit NOR1 is connected to the output of the NOR circuit NOR2. The other input of the NOR circuit NOR2 is connected to the output of the NOR circuit NOR1. The output of the NOR circuit NOR1 is further connected to the input of the inverter IV9 and the input of the inverter IV8. The output of the NOR circuit NOR2 is further connected to the input of the inverter IV10 and the input of the inverter IV3. The output of inverter IV8 is connected to the input of inverter IV7. The output of inverter IV3 is connected to the input of inverter IV4. Inverter IV9 outputs internal clock signal SCLK.

The 6-bit control data D <5: 0> is input to the internal oscillator 106.
The power supply voltage VDD is input to the gate of the NMOS transistor N7 and the gate of the NMOS transistor N8. D0 is input to the gate of the NMOS transistor N6 and the gate of the NMOS transistor N9. D1 is input to the gate of the NMOS transistor N5 and the gate of the NMOS transistor N10. D2 is input to the gate of the NMOS transistor N4 and the gate of the NMOS transistor N11. D3 is input to the gate of the NMOS transistor N3 and the gate of the NMOS transistor N12. D4 is input to the gate of the NMOS transistor N2 and the gate of the NMOS transistor N13. D5 is input to the gate of the NMOS transistor N1 and the gate of the NMOS transistor N14.

  By controlling on / off of the NMOS transistors N1 to N6 and N9 to N14 by the 6-bit control data D <5: 0>, the frequency of the internal clock signal SCLK can be changed.

FIG. 5 is a diagram illustrating the configuration of the frequency control unit 105a according to the first embodiment.
As shown in FIG. 5, the frequency control unit 105 a includes a comparison unit 201, a calculation unit 202, and a DAC 203.

  The comparison unit 201 compares the measurement frequency A of the internal clock signal SCLK sent from the frequency measurement unit 104 with the target frequency B. The comparison unit 201 outputs an UP signal when the measurement frequency A is lower than the target frequency B. When the measurement frequency A is higher than the target frequency B, the comparison unit 201 outputs a DOWN signal. The target frequency B may be determined and stored in advance, or may be specified by the data signal DATA_I transmitted from the motherboard 301.

  The calculation unit 202 performs a calculation on the previous frequency control value C from the comparison result of the comparison unit 201. The calculation unit 202 includes a register that holds a frequency control value C at the time of the previous frequency correction. The arithmetic unit 202 adds “+1” to the previous frequency control value C when the UP signal is input from the comparison unit 201, and “−” with respect to the previous frequency control value C when the DOWN signal is input. The frequency control value C is corrected by adding “1”. Here, “+1” or “−1” is added, but the present invention is not limited to this, and any value such as “+2” or “−2”, “+3” or “−3” is not limited thereto. Adjustment is possible.

  The DAC 203 converts the digital frequency control value C output from the calculation unit 202 into an analog frequency control value C. That is, when the previous frequency control value C is corrected, the frequency control value C is corrected by a fixed amount for each word data communication, and when the correction is not performed, the previous frequency control value C is maintained.

  When the absolute value of the difference between the measurement frequency A and the target frequency B is equal to or less than the threshold value, the comparison unit 201 outputs a STAY signal to the calculation unit 202, and the calculation unit 202 returns to the previous time when the STAY signal is input. It is also possible to add 0 to the frequency control value C.

  FIG. 6 is a timing chart of frequency correction of internal clock signal SCLK in the first embodiment.

  FIG. 6 shows a serial communication clock signal MCLK, a serial communication data signal DATA_I transmitted from the master to the slave, an internal clock signal SCLK output from the slave-side internal oscillator 106, and an internal clock. The frequency of the signal SCLK is shown.

  The first serial communication is started at timing t0. The second serial communication is started at timing t3. The third serial communication is started at timing t6.

  In the first serial communication, the slave imaging module 302 receives the serial communication clock signal MCLK at timing t0.

  At timing t1, the clock signal MCLK first falls. At timing t1, the frequency measuring unit 104 starts counting pulses of the output of the internal oscillator 106. The count operation continues until the timing t2 of the falling edge of the final clock during transmission of one word.

  The frequency measuring unit 104 converts the number of pulses of the internal clock signal SCLK output from the internal oscillator 106 from the timing t1 to the timing t2 into the frequency A and outputs the frequency A to the frequency control unit 105a.

  The frequency control unit 105 a corrects the frequency control value C of the internal oscillator 106 based on the measurement frequency A and the target frequency B sent from the frequency measurement unit 104. The internal oscillator 106 corrects the oscillation frequency based on the frequency control value C. The frequency control value C is corrected in a direction gradually approaching the target frequency B over a plurality of times. Since the serial communication clock signal MCLK is not input to the slave from timing t2 to timing t3 during which serial communication is not performed, the frequency control value C is not corrected.

  Since the frequency correction operation during the second serial communication and the third serial communication is the same, the description thereof is omitted.

  In a period in which serial communication is not performed, that is, a period in which a serial communication signal is not transmitted, the state control unit 103 sets the switch 108 to OFF and stops the frequency measurement unit 104 and the frequency control unit 105a. . As a result, the frequency correction operation of the internal oscillator 106 is not performed. The operation of correcting the frequency intermittently only during communication, instead of always inputting the clock signal to correct the frequency, can reduce the power consumption as compared with the circuit configuration in which the clock signal is always corrected.

  As described above, in the image forming apparatus described in Patent Document 1, it is necessary to provide a correction period during which data communication is not performed in order to correct the clock frequency of the slave oscillation circuit. In the communication system of LIN, which is a communication protocol for in-vehicle devices, a Synch field is provided in the header of the communication frame to correct the frequency of the clock signal, and the clock signal cycle of each slave is adjusted. Therefore, in the LIN communication method, data communication is not possible during the Synch field period.

  On the other hand, in the present embodiment, the slave internal oscillator 106 is corrected by correcting the frequency of the internal oscillator 106 using the serial communication high-accuracy clock signal MCLK transmitted intermittently during serial communication. Correction of the frequency of the internal clock signal SCLK generated in (1) can be performed in parallel with data communication.

  The light amount measurement time of the image sensor mounted on the imaging module 302 varies depending on the frequency of the internal clock signal SCLK generated by the internal oscillator 106. As the amount of correction of the frequency of the internal clock signal SCLK generated by the internal oscillator 106 increases, the difference between the light amount measurement time before and after correction increases. As a result, spots occur in the captured image generated by the imaging module 302. In the present embodiment, the frequency of the internal clock signal SCLK is not corrected to the target frequency B at one time, but the internal clock signal SCLK is corrected so as to gradually approach the target frequency B over a plurality of times, thereby It is possible to suppress plaque.

Embodiment 2
FIG. 7 is a diagram illustrating the configuration of the frequency control unit 105b according to the second embodiment. Here, the description for the same contents as in the first embodiment is omitted, and only the difference is described.

  The frequency control unit 105 b includes an LUT 204, a calculation unit 202, and a DAC 203.

  The LUT 204 receives the measurement frequency A output from the frequency measurement unit 104 every time one word of data is transmitted, and outputs the correction value D of the frequency control value C corresponding to the measurement frequency A to the calculation unit 202. In the LUT 204, a correction value D of the frequency control value C corresponding to the difference between the measurement frequency A and the target frequency B is set.

  When the measurement frequency A is higher than the target frequency B, a correction value D that decreases the frequency control value C is set. When the measurement frequency A is smaller than the target frequency B, a correction value D that increases the frequency control value C is set. The greater the absolute value of the difference between the measurement frequency A and the target frequency B, the greater the correction value D of the frequency control value C. More preferably, the correction value D is determined such that the frequency control value C becomes a target frequency B or a frequency close to the target frequency B by one correction.

  The calculation unit 202 outputs a frequency control value C based on the correction value D sent from the LUT 204. The calculation unit 202 includes a register that holds a frequency control value C at the time of the previous frequency correction. The calculation unit 202 adds the correction value D sent from the LUT 203 to the previous frequency control value C, and updates and outputs the frequency control value C. More preferably, the frequency of the internal clock signal SCLK is corrected to the target frequency B or a frequency close to the target frequency B by one frequency correction.

  The DA converter 203 converts the digital frequency control value C output from the calculation unit 202 into an analog frequency control value C.

  FIG. 8 is a timing chart of frequency correction of internal clock signal SCLK in the second embodiment.

  FIG. 8 shows a serial communication clock signal MCLK, a serial communication data signal DATA_I transmitted from the master to the slave, an internal clock signal SCLK output from the slave-side internal oscillator 106, and an internal clock. The frequency of the signal SCLK is shown.

  Since the start and end of the counting operation of the number of pulses of the internal oscillator 106 are the same as those in the first embodiment, description thereof will not be repeated.

  In the first serial communication, the slave imaging module 302 receives the serial communication clock signal MCLK at timing t0.

  At timing t1, the clock signal MCLK first falls. At timing t1, the frequency measuring unit 104 starts counting pulses of the output of the internal oscillator 106. The count operation continues until the timing t2 of the falling edge of the final clock during transmission of one word.

  The frequency measurement unit 104 converts the number of pulses of the internal clock signal SCLK output from the internal oscillator 106 from timing t1 to timing t2 into the measurement frequency A and outputs the measurement frequency A to the frequency control unit 105b. In the frequency control unit 105b, the LUT 204 outputs a correction value D corresponding to the measurement frequency A to the calculation unit 202. The arithmetic unit 202 and the DAC 203 output the updated frequency control value C to the internal oscillator 106 based on the correction value D. The internal oscillator 106 corrects the oscillation frequency based on the received frequency control value C. As a result, the frequency of the internal clock signal SCLK is corrected.

  In the present embodiment, the frequency of the internal clock signal SCLK is corrected so as to match or be close to the target frequency B by one correction. When the first frequency correction is performed at timing t2, the frequency of the internal clock signal SCLK is corrected to the target frequency B or a frequency close to the target frequency B.

  Since the clock signal MCLK for serial communication is not input from timing t2 to timing t3, which is the time when serial communication is not performed, no correction operation is performed.

  The same applies to the frequency correction operation during the second serial communication and the third serial communication. The frequency is corrected at timings t5 and t8 of the falling edge of the final clock when one word is transmitted in the second and third serial communications.

Next, the effect of Embodiment 2 is demonstrated.
Normally, in an imaging device, transmission and reception of data by serial communication are frequently repeated between the master and the slave. However, the second imaging operation is performed without performing serial communication for a certain period after the first imaging among the two imaging operations. Suppose that That is, in the first imaging operation, assuming that the frequency of the internal clock signal SCLK is captured at the target frequency B, the serial communication is not performed for a certain period after the first imaging. The frequency of the oscillator 106 deviates from the target frequency B, and the difference becomes large. In this state, when the second imaging is performed, if the frequency of the internal clock signal SCLK is corrected stepwise so as to approach the target frequency B, the amount of light that has changed since the first imaging is measured during the second imaging. Since the time is only corrected by one step, the difference in brightness between the captured images at the first and second imaging increases.

  In the present embodiment, the frequency of the internal clock signal SCLK can be corrected to the target frequency B or a frequency close to the target frequency B by one frequency correction. Therefore, in the case where the frequency correction is not performed for a certain period from the time of the first imaging described above and the second imaging is performed, the difference in brightness between the captured images at the first imaging and the second imaging can be reduced.

Embodiment 3
FIG. 9 is a diagram illustrating the configuration of the image processing apparatus according to the third embodiment.

The motherboard 301 is a master and the imaging module 302 is a slave.
In the image processing apparatus according to the third embodiment, the motherboard 301 and the imaging module 302 are connected by a clock signal line CLK, a signal line MOSI for the data signal DATA_I, and a signal line MISO for the data signal DATA_O.

  The imaging module 302 includes an image sensor 304 and an AFE (Analog Front End) 303.

  The AFE 303 includes an amplifier 307, an ADC 306, a digital image processing unit 305, and a timing setting unit 309.

  The timing setting unit 309 includes an internal clock generation circuit 101 and a timing control unit 308.

  Based on the internal clock signal SCLK output from the internal clock generation circuit 101, the timing control unit 308 outputs a timing signal indicating the operation timing of the image sensor 304, ADC 306, and digital image processing unit 305 to the image sensor 304, ADC 306, And sent to the digital image processing unit 305. In addition, the timing control unit 308 sends a timing signal FCAL instructing the timing for correcting the frequency of the internal clock signal SCLK to the frequency control unit 105 a in the internal clock generation circuit 101. The timing control unit 308 sets the timing signal FCAL to high during a period during which the image sensor 304 scans an area outside the effective pixel that does not contribute to imaging (hereinafter referred to as a blanking period) so as not to affect the captured image. Set to level.

  The internal clock generation circuit 101 is the same as that in the first embodiment. The frequency control unit 105a in the internal clock generation circuit 101 corrects the oscillation frequency of the internal oscillator 106 in the internal clock generation circuit 101 when the timing signal FCAL output from the timing control unit 308 is at a high level.

The image sensor 304 converts the amount of light of the subject into an electrical signal in the imaging operation.
The amplifier 307 amplifies the electrical signal output from the image sensor 304.

  The ADC 306 converts the analog signal amplified by the amplifier 307 into a digital signal.

  The digital image processing unit 305 processes the digital signal output from the ADC 306. The image data processed in the digital image processing unit 305 is transmitted to the mother board 301 as a master via the signal line MISO.

  FIG. 10 is a timing chart of frequency correction of internal clock signal SCLK in the third embodiment.

  FIG. 10 shows a serial communication clock signal MCLK, a serial communication data signal DATA_I transmitted from the master to the slave, a timing signal FCAL, and an internal clock signal output from the slave-side internal oscillator 106. SCLK and the frequency of the internal clock signal SCLK are shown.

  Since the start and end of the counting operation of the number of pulses of the internal oscillator 106 are the same as those in the first embodiment, description thereof will not be repeated.

  Here, it is assumed that the first serial communication period is a blanking period. The timing control unit 308 sets the timing signal FCAL to a high level during the first serial communication.

  The frequency correction operation is controlled by a frequency correction timing signal FCAL output from the timing control unit 308 to the internal clock generation circuit 101.

  At timing t1, the first clock of the first serial communication falls. From timing t1, counting of the number of pulses output from the internal oscillator 106 is started. The counting operation is continued until the falling edge of the final clock when one word is transmitted at timing t2.

  Since the timing signal FCAL is set to the high level at the falling timing of the final clock of the first serial communication, the frequency control unit 105a of the internal clock generation circuit 101 is the same method as in the first embodiment. By correcting the oscillation frequency of the internal oscillator 106, the frequency of the internal clock signal SCLK is corrected.

  The timing control unit 308 sets the timing signal FCAL to a low level after the end of the first serial communication period.

  The count operation is similarly performed from the falling edge of the first clock of the second serial communication indicated at the timing t4. The timing signal FCAL is at the low level at the falling timing of the final clock when transmitting one word of the second serial communication at the timing t5. Therefore, the frequency control unit 105 a of the internal clock generation circuit 101 does not correct the oscillation frequency of the internal oscillator 106.

  In this embodiment, the frequency of the internal clock signal SCLK is corrected only during the blanking period, and the frequency of the internal clock signal SCLK is not corrected during the period during which other pixel regions are scanned. Can be suppressed.

(Modification)
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

  (1) In the second embodiment, the frequency of the internal clock signal SCLK is corrected to the target frequency B by one correction using the LUT. However, the present invention is not limited to this. Using the LUT, the frequency of the internal clock signal SCLK may be corrected step by step so as to approach the target frequency B.

  (2) In the third embodiment, the frequency control unit 105a corrects the frequency of the internal clock signal SCLK only during the blanking period, and the first mode corrects the frequency of the internal clock signal SCLK regardless of the blanking period. It is good also as what has 2 modes. An instruction to switch modes may be sent from the master motherboard 301 to the slave imaging module 302 by the data signal DATA_I.

  (3) In this embodiment, the internal clock signal SCLK output from the internal oscillator 106 is directly generated from the internal oscillator, and the oscillation frequency of the internal oscillator 106 and the frequency of the internal clock signal SCLK are the same. However, the present invention is not limited to this.

  The internal clock signal SCLK output from the internal oscillator 106 may be a clock obtained by dividing the clock generated by the internal oscillator 106. In this case, the frequency of the internal clock signal SCLK is (1 / n) times the frequency of the internal oscillator 106. n is an integer.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 101 Internal clock generation circuit, 102 State detection part, 103 State control part, 104 Frequency measurement part, 105a, 105b Frequency control part, 106 Internal oscillator, 107 SPI communication part, 108 Switch, 201 Comparison part, 202 Operation part, 203 DA Converter, 204 LUT, 301 Motherboard, 302 Imaging module, 303 Analog front end, 304 Image sensor, 305 Image processor, 306 AD converter, 307 Amplifier, 308 Timing controller, 309 Timing generator, IV1 to IV10 Inverter, NOR1 , NOR2 NAND circuit, C1-C14 capacitive element, N1-N14 NMOS transistor.

Claims (12)

An internal clock generation circuit in a first device capable of serial communication with a second device that generates a clock signal for serial communication,
An internal oscillator that outputs an internal clock signal with lower accuracy than the clock signal for serial communication;
A frequency measurement unit that measures the frequency of the internal clock signal output from the internal oscillator based on the serial communication clock signal transmitted from the second device;
An internal clock generation circuit comprising: a frequency control unit that corrects the frequency of the internal clock signal output from the internal oscillator based on the measured frequency and the target frequency.   The frequency measurement unit is configured to transmit the serial data supplied last from a falling edge timing of the serial communication clock signal supplied first when transmitting data in bit units determined from the second device. 2. The internal clock generation circuit according to claim 1, wherein the frequency of the internal clock signal is measured by counting the number of pulses of the internal clock signal in a period until a timing of a falling edge of the communication clock signal.   When the measured frequency is larger than the target frequency for each transmission of the determined bit unit data from the second device, the frequency control unit is configured to reduce the frequency of the internal clock signal by a certain value. The internal clock generation circuit according to claim 2, wherein when the measured frequency is smaller than the target frequency, the frequency of the internal clock signal is increased by the constant value.   The frequency control unit has a table that defines a correction value of the frequency of the internal clock signal with respect to the difference between the measured frequency and the target frequency, and the predetermined bit unit from the second device The internal clock generation circuit according to claim 2, wherein the frequency of the internal clock signal is corrected based on the table every time data is transmitted.   5. The internal clock generation circuit according to claim 4, wherein in the table, the correction value increases as the absolute value of the difference between the measured frequency and the target frequency increases.   2. The internal clock generation circuit according to claim 1, wherein the target frequency is designated by a data signal transmitted from the second device in synchronization with the clock signal for serial communication. A switch provided in a front stage of the frequency measurement unit, for receiving the clock signal for serial communication;
The rising edge of the clock signal for serial communication supplied last from the timing of the falling edge of the clock signal for serial communication supplied first at the time of transmission of the predetermined bit unit from the second device. The internal clock generation circuit according to claim 2, further comprising a state control unit that turns on the switch during a period up to a timing of a falling edge. The serial communication clock signal is generated by an oscillator using a crystal resonator,
The internal clock generation circuit according to claim 1, wherein the internal oscillator generates the internal clock signal without using a crystal resonator.   The internal clock generation circuit according to claim 1, wherein the serial communication conforms to an SPI communication standard. An internal clock generation circuit according to any one of claims 1 to 9,
An imaging module comprising: an image sensor that operates based on the internal clock signal.   The imaging module according to claim 10, further comprising: a timing control unit that causes the frequency control unit to correct the frequency of the internal clock signal during a period in which the image sensor scans outside the effective pixel region. A motherboard that is the second device and functions as a master device;
An image processing apparatus comprising the imaging module according to claim 10, wherein the image processing module is the first apparatus and functions as a slave apparatus.

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