JP2019191930A - Neural network circuit - Google Patents

Abstract

To provide a neural network circuit capable of reducing a power consumption.SOLUTION: In an analog product-sum arithmetic circuit 1, a memristor applies a signal voltage and a reference voltage to an input terminal of a crossbar circuit 4 of a storage element via a D/A converter 2 and an amplifier 3. A current flowing through an output terminal of the crossbar circuit 4 is converted into a voltage by an amplifier 7 and then A/D converted. An offset correction unit 30 corrects an offset voltage generated in the amplifier 7. An amplifier 3 (B) applies a reverse polarity bias voltage and a reference voltage in response to an input voltage from a D/A converter 2 (B). During an initial operation, the amplifier 3 (B) outputs a reverse polarity bias voltage, and amplifiers 3 (1) and 3 (2) output the reference voltage, and a subtraction unit 9 latches an A/D converted data. During a normal operation, the amplifier 3 (B) outputs the reference voltage, the amplifiers 3 (1), 3 (2) output the signal voltage, and the subtraction unit latches the A/D converted data and outputs a subtraction result.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a neural network circuit having a storage unit formed by connecting memristors as storage elements in a grid pattern.

  Currently, research is underway to construct a neural network circuit using a non-volatile, two-terminal element that can change the conductance value, called a memristor, as a synapse. Such a neural network circuit is shown in FIG. 14, FIG. As shown in FIG. 2, the memristors are arranged in a grid pattern, and a voltage is applied to the memristors to generate a current. The combined current is converted into a voltage by a transimpedance amplifier and an I / V conversion amplifier, and after a waveform is shaped by an activation function, it is output as a voltage value. A neural network circuit is configured by a memristor operating as a synapse and an I / V conversion amplifier operating as a neuron. The I / V conversion amplifier performs a product-sum operation between the conductance value of the memristor and the applied voltage by an analog operation.

  Here, in the actual circuit, when each of the inputs Vi1 to Vi3 shown in FIG. 14 takes a value of −1 to +1, Vi4 = −1 is always applied as a bias to the threshold.

“A heterogeneous computing system with memristor-based neuromorphic accelerators” High PERFORMANCE Extreme Computing Conference, 2014 IEEE

FIG. 15 shows an example in which a 10-layer CNN (convolutional neural network) is configured using the circuit shown in FIG. FIG. 16 shows a calculation example of the input current ratio of each input terminal in the first layer when image recognition is performed by this CNN. The input consists of 28 terminals Vi1 to Vi28 to which -Vb to + Vb are applied, the output consists of 96 terminals Vo1 to Vo96, and the input bias is
Calculation is performed with Vi28 = −Vb constantly applied.

  In general, since input data has sparsity, the bias current is one digit or more larger than the actual individual input current. In the example shown in FIG. 16, the bias current shows a ratio of less than 40% with respect to the sum of the input currents.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a neural network circuit capable of reducing power consumption based on application of a bias voltage.

  According to the neural network circuit of claim 1, a signal voltage and a reference voltage are connected to a plurality of voltage input terminals of a storage unit formed by connecting memory elements, which are storage elements, in a grid pattern via a D / A converter and a drive amplifier. And apply. When the current flowing through the current output terminal of the storage unit is converted into a voltage by the I / V conversion amplifier, it is A / D converted by the A / D converter. The offset correction unit is disposed on the output side of the A / D converter and corrects an offset voltage generated in the I / V conversion amplifier. A drive amplifier connected to a bias terminal which is one of a plurality of voltage input terminals is a bias application amplifier, and a bias voltage having a reverse polarity and a reference voltage according to a voltage input from a corresponding D / A converter. And apply.

  During the bias setting operation, the control unit of the offset correction unit controls each D / A converter so that the bias applying amplifier outputs a bias voltage having a reverse polarity and the other driving amplifier outputs a reference voltage. At this time, the A / D converted data is latched by the first latch circuit. During normal operation, each D / A converter is controlled so that the reference voltage is output to the bias application amplifier and the signal voltage is output to the other drive amplifiers. The latch circuit latches. The subtracter outputs the result of subtracting the latch data of the second and first latch circuits as signal data.

  For example, assuming that the bias voltage of the reverse polarity to be applied is + Vb, the data latched in the first latch circuit during the bias setting operation is when the bias of the reverse polarity is applied to the offset voltage Voff generated in the I / V conversion amplifier. The output voltage Vbias is added (Voff + Vbias). Further, the data latched by the second latch circuit during normal operation is obtained by adding the offset voltage Voff to the output voltage Vout of the amplifier according to the signal voltage Vin input to the I / V conversion amplifier (Vout + Voff). Equivalent to.

Therefore, the subtraction result of the subtractor is
(Vout + Voff) − (Voff + Vbias) = Vout−Vbias
Thus, the offset voltage is canceled and corresponds to a voltage to which the bias voltage −Vb is added. In other words, since the bias current flows through the storage unit only during the bias setting operation, the energization period of the bias current can be shortened compared to the conventional case, and current consumption can be reduced. The offset voltage can also be corrected.

  According to the neural network circuit of the second aspect, the configuration up to the I / V conversion amplifier is the same as that of the first aspect, but the differential amplifier is differential in the outputs of the two I / V conversion amplifiers forming a pair. The difference is that it is a so-called differential configuration that performs computation. In addition, the conductance value of the differential pair of the memristor to which the bias voltage is applied in the storage unit is changed in advance so that the polarity of the bias voltage is reversed.

  That is, the conductance value of the differential pair of the memristor to which the bias voltage is applied is changed in advance so that the polarity of the bias voltage is reversed. This is equivalent to the operation of outputting a bias voltage of reverse polarity to the amplifier. Therefore, even in the case where the output side of the storage unit has a differential configuration, the current consumption can be reduced as in the first aspect.

  According to the neural network circuit of the third aspect, since the control unit intermittently executes the bias setting operation, the current consumption can be further reduced.

FIG. 2 is a diagram showing the configuration shown in FIG. 2 in more detail according to the first embodiment Functional block diagram showing the analog product-sum operation circuit constituting the neural network circuit The figure which shows the buffer circuit arrange | positioned at the input side of a D / A converter Functional block diagram showing the internal configuration of the subtraction unit Diagram showing an example of an activation function Diagram showing the configuration of the activation function calculator Functional block diagram showing the configuration of the offset correction control unit Timing chart showing operation of offset correction controller Flow chart showing circuit operation of offset correction Functional block diagram showing the configuration of the offset correction control unit according to the second embodiment Timing chart showing operation of temperature sensor Functional block diagram showing in detail the analog product-sum operation circuit constituting the neural network circuit according to the third embodiment Flow chart showing circuit operation of offset correction FIG. Figure showing 2 The figure which shows the example which comprised 10-layer CNN using the circuit shown in FIG. The figure which shows the example of calculation of the input current ratio of each input terminal of the 1st layer at the time of performing image recognition by CNN shown in FIG.

(First embodiment)
The first embodiment will be described below. The analog product-sum operation circuit 1 of the neural network circuit shown in FIG. 2 converts the input data Data_in by the D / A converter 2. The converted voltage is applied to the memristor crossbar circuit 4 via the drive amplifier 3. The drive amplifier 3 corresponds to a drive amplifier. The memristor crossbar circuit 4 uses a memristor as a memory element, and is configured by arranging a plurality of memory elements in a lattice pattern, and corresponds to a memory unit.

A current is output from the crossbar circuit 4 according to the conductance value set for each storage element, and the current is converted into a voltage by the sense amplifier 7. The voltage converted by the sense amplifier 7 is A / D converted by the A / D converter 8 and output as digital data. The sense amplifier 7 corresponds to an I / V conversion amplifier. The data is input to the activation function calculation unit 10 via the subtraction unit 9. In the activation function calculation unit 10, for example, a ramp function f (x) of the following expression shown in FIG. 5 is applied to the input data as an activation function of the neural network circuit.
f (x) = max (0, x) (1)
This ramp function f (x) is positive. Thereafter, the output data Data_out is input to the analog product-sum operation circuit 1 at the next stage.

  The offset correction control unit 11 corrects the offset included in the output data of the A / D converter 8 by controlling the D / A converter 2 and the subtraction unit 9. The subtraction unit 9 and the offset correction control unit 11 constitute an offset correction unit 30. In practice, more D / A converters 2, drive amplifiers 3, sense amplifiers 7, A / D converters 8 and the like are provided. FIG. 1 shows a part related to input / output of the memory stack bar circuit 4 shown in FIG. 2 in more detail according to the actual situation.

  As shown in FIG. 3, a buffer circuit 12 is arranged in the data input section of the D / A converter 2. When the input data DI is n bits, an OR gate 13 is arranged corresponding to the most significant bit DI [n−1], and corresponding to the other lower bits DI [n−2] to DI [0]. AND gates 14 [n-2] to 14 [0] are arranged. Corresponding input data DI is given to one of the input terminals of these logic gates 13 and 14, and an enable signal EN output from the offset correction control unit 11 is given to the other input terminal. However, the enable signal EN is given to the OR gate 13 via the NOT gate 15.

  When the enable signal EN = 0, only DI [n−1], which is the MSB, of the input data of the D / A converter 2 is “1”, and the other lower bits DI [n−2] to DI [0]. All become “0”. As shown in FIG. 1, the enable signal EN input to the D / A converter 2 (B) is a control signal Bias_DAC_select output from the offset correction control unit 11, and the other D / A converter 2 (1). , 2 (2), etc., is the control signal Data_DAC_select.

And about D / A converter 2 (1) and 2 (2), a conversion voltage is output as follows according to the said control signal.
Data_DAC_select Output voltage
0 (initial operation) Reference voltage Vref
1 (normal operation) A signal voltage corresponding to input data. For the D / A converter 2 (B), a conversion voltage is output as follows according to the control signal Bias_DAC_select.
Bias_DAC_select Output voltage
0 (normal operation) Reference voltage Vref
1 (initial operation) Reverse polarity bias voltage + Vb
The “initial operation” and “normal operation” will be described later.

  As shown in FIG. 4, the subtraction unit 9 includes a first latch circuit 16 (1), a second latch circuit 16 (2), a latch control circuit 17, and a subtracter 18. Input data DI is input to the latch circuit 16, and a latch signal is input from the latch control circuit 17. The latch control circuit 17 includes OR gates 19 (1) and 19 (2) and a NOT gate 20. The latch signal; LE is input to one of the input terminals of the OR gates 19 (1) and 19 (2), and the select signal Latch_select; SEL is input to the other input terminal. However, the select signal SEL is input to the OR gate 19 (1) via the NOT gate 20.

  As illustrated in FIG. 6, the activation function calculation unit 10 includes n AND gates 21 [n−1] to 21 [0]. Data D [n−1] to D [0] output from the subtracting unit 9 is given to one input terminal of the AND gate 21, and data D [n−1] is commonly used to the other input terminal. Is given.

  As shown in FIG. 7, the offset correction control unit 11 includes a counter 22. The clock signal Clock is input to the input terminal of the counter 22. The counter 22 receives count value setting data Data_set, and when the count value is counted, the counter 22 sets the output signal Q to a high level for one clock cycle. The inverted signal QN of the output signal Q is set to a low level for one clock cycle.

  A control signal Data_DAC_select and a control signal Latch_select are output from the output terminal QN of the counter 22. A control signal Bias_DAC_select is output from the output terminal Q of the counter 22.

  FIG. 8 is an operation timing chart of the offset correction control unit 11. The offset correction control unit 11 sets the execution frequency of the initial state in which the offset voltage Voff and the bias voltage + Vbias having the opposite polarity are taken in by the count value of the counter 22. This implementation frequency is set such that the influence of the offset voltage Voff of the sense amplifier 7 and the temperature drift of the conductance of the memristor can be allowed as an error in the calculation result.

  In this example, the value of the data Data_set set in the counter 22 is “4”, and Bias_DAC_select becomes high level every 4 counts of the clock signal Clock. Data_DAC_select and Latch_select are inverted from Bias_DAC_select.

  That is, the D / A converters 2 (1) and 2 (2) perform “initial operation” every four clock cycles, and “normal operation” otherwise. The D / A converter 2 (B) performs “initial operation” in synchronization with the D / A converters 2 (1) and 2 (2) every four clock cycles, and “normal operation” otherwise.

  Next, the operation of this embodiment will be described. FIG. 9 shows a circuit operation corresponding to the timing chart of FIG. First, if the bias side operation mode by the offset correction control unit 11 is “initial operation” in step S1 (S2), the D / A converters 2 (1) and 2 (2) output the reference voltage Vref, and D / A The A converter 2 (B) outputs a reverse polarity bias voltage + Vb (S3). The “initial operation” corresponds to a bias setting operation.

Here, the voltage range that can be applied to both ends of the memristor is ± Vb, and the reference potential Vref applied to the sense amplifier 7 is, for example, 0V. "Initial operation" is a state that does not cause a potential difference between both ends of the memristor.
Vin1 = Vin2 = 0V, VinB = + Vb
It becomes. At this time, if the offset voltage Voff is generated in the sense amplifier 7, the output voltage Vout is obtained by adding the offset voltage Voff to the output voltage + Vbais when the reverse polarity bias voltage + Vb is applied, that is,
Vout = Voff + Vbias
become. At this time, since Latch_select = 0, the data corresponding to the output voltage (Voff + Vbias) of the sense amplifier 7 is latched by the latch circuit 16 (2) of the subtraction unit 9 (S4).

  On the other hand, if the bias side operation mode by the offset correction control unit 11 is “normal operation” in step S1 (S5), the D / A converters 2 (1) and 2 (2) output the signal voltages Vin1 and Vin2, respectively. The D / A converter 2 (B) outputs the reference voltage Vref (S6). Therefore, the output of the sense amplifier 7 becomes a voltage (Vout + Voff) obtained by adding the offset voltage Voff to the output voltage Vout corresponding to the signal voltage Vin. At this time, since Latch_select = 1, data corresponding to the output voltage (Vout + Voff) of the sense amplifier 7 is latched by the latch circuit 16 (1) (S7).

Then, the subtracter 18 of the subtraction unit 9 subtracts the data of the latch circuits 16 (2) and 16 (1) (S8). The subtraction result is
(Vout + Voff) − (Voff + Vbias) = Vout−Vbias
It becomes. The data thus obtained corresponds to a voltage obtained by adding the output voltage −Vbias when the positive bias voltage −Vb is applied to the output voltage Vout of the sense amplifier 7. The offset voltage Voff is cancelled.

  As described above, according to the present embodiment, the signal voltage Vin and the reference voltage Vref are supplied to the plurality of voltage input terminals of the crossbar circuit 4 using the memristor as the storage element via the D / A converter 2 and the drive amplifier 3. Apply. The current flowing through the current output terminal of the memristor crossbar circuit 4 is converted into a voltage by the sense amplifier 7 and A / D converted by the A / D converter 8. The offset correction unit 30 is arranged on the output side of the A / D converter 8 and corrects the offset voltage Voff generated in the sense amplifier 7.

  The drive amplifier 3 (B) connected to the bias terminal of the memristor crossbar circuit 4 generates the reverse polarity bias voltage + Vb and the reference voltage Vref according to the voltage input from the D / A converter 2 (B). Apply.

  The offset correction control unit 11 outputs a bias voltage of reverse polarity to the drive amplifier 3 (B) and outputs the reference voltage Vref to the drive amplifiers 3 (1) and 3 (2) during the initial operation. The A converter 2 is controlled, and the A / D converted data is latched by the first latch circuit 16 (1).

  During normal operation, each D / A converter 2 is controlled so that the drive amplifier 3 (B) outputs the reference voltage Vref and the drive amplifiers 3 (1), 3 (2) output the signal voltage Vin. At this time, the A / D converted data is latched by the second latch circuit 16 (2). The subtracter 18 outputs the result of subtracting the latch data of the second and first latch circuits 16 (2) and 16 (1) as signal data DOUT.

  With this configuration, the bias current flows through the memory stack bar circuit 4 only during the initial operation, so that the energization period of the bias current can be made shorter than in the conventional case, and the current consumption can be reduced. The offset voltage Voff can also be corrected. In addition, since the offset correction control unit 11 performs the initial operation intermittently, the energization period of the bias current is further shortened.

  Specifically, the offset correction control unit 11 performs an initial operation every time the clock signal Clock count value by the counter 22 reaches a predetermined value “4”. When the count value reaches a predetermined value, the counter 22 changes the output signal Q to a high level for one clock cycle. The offset correction control unit 11 outputs a control signal Bias_DAC_select from the output terminal Q of the counter 22 to control the D / A converter 2 (B), and outputs a control signal Data_DAC_select from the output terminal QN of the counter 22 to output D / A. The converters 2 (1) and 2 (2) are controlled, and the control signal Latch_select is output from the output terminal QN of the counter 22 to control the latch timing of the latch circuits 16 (1) and 16 (2). Thereby, the energization period of the bias current can be set to one clock cycle every four clock cycles.

  Further, the D / A converter 2 includes a buffer circuit 12 having a control terminal for controlling an input data value, and the buffer circuit 12 corresponds to a drive amplifier corresponding to a change in the binary level of the enable signal EN given to the control terminal. 3 is inputted with data for outputting the reference voltage Vref. Thereby, switching between the initial operation and the normal operation can be easily performed.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. In the second embodiment, an offset correction control unit 31 shown in FIG. 10 is used instead of the offset correction control unit 11. The offset correction control unit 31 includes a D flip-flop 32 that replaces the counter 22 and a temperature sensor unit 33.

  The temperature sensor unit 33 includes a reset terminal and a terminal that outputs a signal DT, and detects the temperature in the vicinity of the memristor crossbar circuit 4, for example. The output terminal of the temperature sensor unit 33 is connected to the input terminal D of the D flip-flop 32, and the reset terminal is connected to the output terminal QN of the D flip-flop 32. The offset correction unit 40 includes an offset correction control unit 31.

  As shown in FIG. 11, the temperature sensor unit 33 sets the signal DT to a high level when the detected temperature changes more than a set value regardless of whether it rises or falls. At this time, the D flip-flop 32 takes in the data value “1” in synchronization with the clock signal Clock and sets the output terminal Q to the high level. Thereby, the initial operation on the bias side is executed. When the output terminal Q becomes high level, the output terminal QN becomes low level, and the temperature sensor unit 33 is reset. Accordingly, the signal DT changes to low level, so that the output terminal QN becomes high level at the next Clock, and the reset of the temperature sensor unit 33 is released.

  As described above, according to the second embodiment, the offset correction control unit 31 executes the bias-side initial setting operation when the temperature fluctuation level detected by the temperature sensor unit 33 exceeds a predetermined level. Specifically, the temperature sensor unit 33 includes a reset terminal for changing the output signal DT to a high level and changing the output signal DT to a low level when the temperature fluctuation level exceeds a predetermined level.

  The output terminal of the temperature sensor unit 33 is connected to the input terminal D of the D flip-flop 32, and the reset terminal is connected to the output terminal QN. The control signals Bias_DAC_select, Data_DAC_select, and Latch_select are output with the same configuration as the offset correction control unit 11 of the first embodiment. According to this configuration, the bias-side initial setting operation is executed only when the temperature fluctuation level exceeds a predetermined level. Therefore, the energization period can be shortened by energizing the bias current at a necessary timing.

(Third embodiment)
The analog product-sum operation circuit 41 of the third embodiment shown in FIG. 12 uses the sense amplifiers 7 (1) and 7 (2) in the first embodiment as sense amplifiers 7 (1p) and 7 (1n), respectively. The output terminals of the sense amplifiers 7 (1p) and 7 (1n) are connected to the input terminals of the differential amplifier 42. The output terminal of the differential amplifier 42 inputs the output voltage Vout1 to the A / D converter 8 (1). That is, the analog product-sum operation circuit 41 has a differential configuration.

  Next, the operation of the third embodiment will be described. When non-linear operation is performed when reverse bias with a large amplitude is applied to the memristor characteristics, a differential configuration is used, and the input signal voltage and bias voltage are single-polarity voltage inputs to reduce computation errors. it can. As with the first embodiment, the analog product-sum calculation circuit 41 applies the bias voltage + Vb having the same reverse polarity as the input signal in the initial operation, and executes the offset correction calculation.

  When a bias voltage is applied during normal operation, the conductance of the memristor is set such that G1B ≧ G2B. Since the third embodiment is a differential output, the polarity of the output voltage can be reversed if the conductance value is changed in advance to satisfy G1B ≦ G2B (S0). As shown in FIG. 13, in step S11 instead of step S3, the D / A converter 2 (B) is made to output a bias voltage + Vb having the same polarity as the input signal. As a result, the same calculation as in the first embodiment is executed.

  As described above, according to the third embodiment, it is possible to cope with the temperature variation of the offset of the sense amplifier 7 and the conductance of the memristor while reducing the energization period of the bias current as in the first embodiment.

(Other embodiments)
In the first embodiment, the value of data set in the counter 22 is not limited to “4”.
A function other than the ramp function may be used as the activation function.
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

  In the drawings, 1 is an analog product-sum operation circuit, 2 is a D / A converter, 3 is a drive amplifier, 4 is a memory stacker bar circuit, 7 is a sense amplifier, 8 is an A / D converter, 9 is a subtracting unit, 11 is An offset correction control unit, 12 is a buffer circuit, 16 (2) and 16 (1) are first and second latch circuits, 18 is a subtractor, 22 is a counter, and 30 is an offset correction unit.

Claims (8)

A memory unit (4) formed by connecting the memory elements in a lattice shape, using the memristor as a variable resistance element as a memory element;
A plurality of D / A converters (2) in which data is input so as to apply a signal voltage and a reference voltage to a plurality of voltage input terminals of the storage unit;
A plurality of drive amplifiers (3) connected between the plurality of D / A converters and the plurality of voltage input terminals;
A plurality of I / V conversion amplifiers (7) connected to a current output terminal of the storage unit and converting a current flowing through the terminal into a voltage and outputting the voltage;
A plurality of A / D converters (8) for A / D converting the signal voltages converted by the plurality of I / V conversion amplifiers;
A plurality of offset correction units (30, 40) that are arranged on the output side of the plurality of A / D converters and correct the offset voltage generated in the I / V conversion amplifier;
One of the plurality of voltage input terminals is a bias terminal for applying a bias voltage;
The drive amplifier (3 (B)) connected to the bias terminal is a bias application amplifier that applies a reverse polarity bias voltage and a reference voltage in accordance with a voltage input from a corresponding D / A converter. Yes,
The offset correction unit
First and second latch circuits (16 (2), 16 (1)) to which output data of the A / D converter is input;
A subtractor (18) for subtracting the latch data of the first latch circuit from the latch data of the second latch circuit;
A controller (11, 31) for controlling the D / A converter and the first and second latch circuits;
The controller is
During the bias setting operation, each D / A converter is controlled so that the bias applying amplifier outputs a bias voltage having a reverse polarity and the other driving amplifier outputs a reference voltage. At that time, the A / D The output data of the converter is latched by the first latch circuit,
During normal operation, each D / A converter is controlled so that the bias application amplifier outputs a reference voltage and the other drive amplifiers output a signal voltage. At that time, output data of the A / D converter is output. Is latched by the second latch circuit,
A neural network circuit for outputting a subtraction result of the subtracter as signal data. A memory unit (4) formed by connecting the memory elements in a lattice shape, using the memristor as a variable resistance element as a memory element;
A plurality of D / A converters (2) in which data is input so as to apply a signal voltage and a reference voltage to a plurality of voltage input terminals of the storage unit;
A plurality of drive amplifiers (3) connected between the plurality of D / A converters and the plurality of voltage input terminals;
A plurality of I / V conversion amplifiers (7) connected to a current output terminal of the storage unit and converting a current flowing through the terminal into a voltage and outputting the voltage;
A differential amplifier (42) for performing a differential operation on the outputs of the two I / V conversion amplifiers forming a pair;
A plurality of A / D converters (8) for A / D converting the output voltage of the differential amplifier;
A plurality of offset correction units (11) disposed on the output side of the plurality of A / D converters, for correcting an offset voltage generated in the I / V conversion amplifier,
One of the plurality of voltage input terminals is a bias terminal for applying a bias voltage;
The drive amplifier connected to the bias terminal is a bias application amplifier (3 (B)) that applies the bias voltage and the reference voltage in accordance with a voltage input from a corresponding D / A converter.
In the storage unit, the conductance value of the differential pair of the memristor to which the bias voltage is applied is switched in advance so that the polarity of the bias voltage is reversed,
The offset correction unit
First and second latch circuits (16 (2), 16 (1)) to which output data of the A / D converter is input;
A subtractor (18) for subtracting the latch data of the first latch circuit from the latch data of the second latch circuit;
A controller (11) for controlling the D / A converter and the first and second latch circuits;
The controller is
During the bias setting operation, each D / A converter is controlled so that the bias application amplifier outputs the bias voltage and the other drive amplifier outputs a reference voltage. At that time, the A / D converter Latching output data in the first latch circuit;
During normal operation, each D / A converter is controlled so that the bias application amplifier outputs a reference voltage and the other drive amplifiers output a signal voltage. At that time, output data of the A / D converter is output. Is latched by the second latch circuit,
A neural network circuit for outputting a subtraction result of the subtracter as signal data.   The neural network circuit according to claim 1, wherein the control unit intermittently executes the bias setting operation.   The neural network circuit according to claim 3, wherein the control unit includes a counter (22) that counts a clock signal, and executes the bias setting operation every time the count value of the clock counter reaches a predetermined value. When the count value reaches a predetermined value, the clock counter changes the output signal to an active level for one clock cycle,
The controller is
A D / A converter corresponding to the bias application amplifier is controlled by an output signal of the clock counter;
5. The neural network circuit according to claim 4, wherein a D / A converter corresponding to the drive amplifier is controlled by inversion of the output signal, and latch timings of the first and second latch circuits are controlled. The D / A converter includes a buffer circuit (12) having a control terminal for controlling an input data value,
6. The neural network circuit according to claim 5, wherein the buffer circuit is configured to input data for causing a corresponding amplifier to output a reference voltage in accordance with a change in a binary level applied to the control terminal.   The neural network circuit according to claim 3, wherein the control unit includes a temperature sensor (31), and executes the bias setting operation when a temperature fluctuation level detected by the temperature sensor exceeds a predetermined level. The temperature sensor includes a reset terminal for changing an output signal to an active level when a fluctuation level of temperature exceeds a predetermined level, and changing the output signal to an inactive level.
The controller is
A D flip-flop (32) in which a clock signal is input to a clock terminal;
The output terminal of the temperature sensor is connected to the input terminal D of the D flip-flop, and the reset terminal is connected to the inverted output terminal QN.
A D / A converter corresponding to the bias applying amplifier is controlled by an output signal of the D flip-flop;
8. The neural network circuit according to claim 7, wherein a D / A converter corresponding to the drive amplifier is controlled by inversion of the output signal, and latch timings of the first and second latch circuits are controlled.

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