JP2019185446A - Image processing device and image processing method - Google Patents

Abstract

To provide an image processing device and an image processing method capable of improving the transmission efficiency of image data.SOLUTION: The image processing device includes: processing means for sequentially outputting each of a plurality of blocks constituting an image; a memory capable of being accessed in a predetermined access unit; and first writing means for writing, to the memory, combined data obtained by combining first data corresponding to a part of a first block of a plurality of blocks with second data not corresponding to the first block and aligned to the access unit.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an image processing apparatus and an image processing method.

  In an image processing apparatus such as a digital camera, various types of image processing such as pixel interpolation, white balance, sharpness, noise reduction, and reduction / enlargement are performed. In these image processes, image data is temporarily stored in a memory such as a DRAM (Dynamic Random Access Memory) that can function as a work area.

  Patent Document 1 discloses an image processing apparatus capable of reducing an increase in access overhead due to a page miss even when an access crossing a boundary between a plurality of pages of a DRAM occurs.

JP 2012-43191 A

  However, when image data having a size that is not aligned with the memory access unit is written to the memory, the writing speed may decrease.

  An object of the present invention is to provide an image processing apparatus and an image processing method capable of suppressing a decrease in writing speed of a memory.

  According to one aspect of the embodiment, a processing unit that sequentially outputs each of a plurality of blocks constituting an image, a memory accessed in a predetermined access unit, and a first block of the plurality of blocks First writing means for writing, into the memory, combined data obtained by combining the second data not corresponding to the first block with the first data corresponding to the first block, and aligned to the access unit An image processing apparatus is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the image processing apparatus and image processing method which can suppress the fall of the writing speed of memory can be provided.

1 is a block diagram illustrating an image processing apparatus according to a first embodiment. It is a block diagram which shows WRDMAC with which the data transfer part of the image processing apparatus by 1st Embodiment was equipped. It is a figure which shows the example of a structure of the data storage area of SRAM with which WRDMAC of the image processing apparatus by 1st Embodiment was equipped. 3 is a timing chart illustrating an operation of the image processing apparatus according to the first embodiment. 3 is a timing chart illustrating an operation of the image processing apparatus according to the first embodiment. It is a figure which shows the virtual address space corresponding to the image of 1 frame. It is a block diagram which shows WRDMAC with which the data transfer part of the image processing apparatus by 2nd Embodiment was equipped. It is a figure which shows the example of a structure of the data storage area | region of SRAM each provided in WRDMAC of the image processing apparatus by 2nd Embodiment. 12 is a flowchart illustrating an example of an operation of the image processing apparatus according to the third embodiment. It is a figure which shows the example of a structure of the data storage area of SRAM with which WRDMAC of the image processing apparatus by 4th Embodiment was equipped. It is a timing chart which shows operation of an image processing device by a 4th embodiment. It is a timing chart which shows operation of an image processing device by a 4th embodiment. It is a figure which shows the virtual address space corresponding to the image of 1 frame. It is a block diagram which shows RDDMAC with which the data transfer part of the image processing apparatus by 5th Embodiment was equipped. It is a figure which shows notionally the block division at the time of writing data in DRAM, and the block division at the time of reading the data written in DRAM. It is a flowchart which shows operation | movement of the image processing apparatus by 5th Embodiment. It is a flowchart which shows operation | movement of the image processing apparatus by 6th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.

[First Embodiment]
The image processing apparatus and the image processing method according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram illustrating the image processing apparatus according to the present embodiment. In the present embodiment, a case where the image processing apparatus 100 is a digital camera will be described as an example, but the present invention is not limited to this.

  The image processing apparatus 100 includes an image sensor 102, an A / D conversion unit 103, an image processing unit 104, a data transfer unit 105, a memory control unit 106, and a DRAM 107. The image processing apparatus 100 further includes a nonvolatile memory control unit 108, a ROM (Read Only Memory) 109, a display control unit 110, and a display unit 111. The image processing apparatus 100 further includes a CPU (Central Processing Unit) 112, an operation unit 113, a system bus (bus line) 114, and a memory bus (bus line) 115. The image processing apparatus 100 includes an imaging optical system 101. The imaging optical system may be removable from the body of the image processing apparatus 100 or may not be removable.

  The imaging optical system (imaging optical unit) 101 includes a lens, a diaphragm, and the like. The imaging optical system 101 performs focus adjustment, exposure adjustment, and the like during shooting. The imaging optical system 101 forms an optical image of a subject on the imaging surface of the image sensor 102.

  The image sensor (solid-state image sensor) 102 has a photoelectric conversion function for converting an optical image into an electrical signal (analog image signal). The image sensor 102 is configured by, for example, a CCD image sensor, a CMOS sensor, or the like.

  The A / D conversion unit 103 converts an analog image signal output from the image sensor 102 into a digital image signal. Here, a case where the A / D conversion unit 103 is provided separately from the image sensor 102 will be described as an example, but the present invention is not limited to this. An A / D conversion unit 103 may be provided in the image sensor 102. For example, the A / D conversion unit 103 outputs a digital image signal indicating a 4K resolution image.

  The CPU 112 governs overall control of the image processing apparatus 100. The CPU 112 includes a microcomputer and the like. The CPU 112 controls each functional block provided in the image processing apparatus 100. The CPU 112 controls each functional block via the system bus 114. Image data is transferred through a memory bus 115 provided separately from the system bus 114.

  A DRAM (volatile memory) 107 is a storage medium (memory) in which data and the like are temporarily stored. For example, still images, moving images, audio data, constants for operating the CPU 112, programs for operating the CPU 112, and the like are stored in the DRAM 107. The DRAM 107 has a storage capacity sufficient to store these. The DRAM 107 is accessed in a predetermined access unit. The burst access unit (access unit, memory access unit) in the DRAM 107 is, for example, 32 bytes. The DRAM 107 is, for example, a DRAM that conforms to the LPDDR4 (Low Power Double-Data-Rate 4) standard. When writing data of a size that is not aligned in burst access units to a DRAM of the LPDDR4 standard, it is necessary to issue a Masked Write command. When the Masked Write command is issued, the Read Modify Write operation is performed. While the Read Modify Write operation is being executed, other commands cannot be processed. Therefore, it takes a long time to write data including data of a size not aligned in burst access units to the DRAM 107. The memory control unit 106 writes and reads data to and from the DRAM 107 based on instructions from the CPU 112 or the data transfer unit 105. The memory control unit 106 issues commands for writing and reading data to the DRAM 107. In the present embodiment, the case where the DRAM 107 of the LPDDR4 standard is used is described as an example, but the present invention is not limited to this. A memory capable of writing and reading at high speed can be used as appropriate.

  The nonvolatile memory control unit 108 reads data from a ROM (nonvolatile memory) 109 based on an instruction from the CPU 112. As the ROM 109, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory) or the like is used. The ROM 109 stores constants for operating the CPU 112, programs for operating the CPU 112, and the like.

  The CPU 112 controls the image processing unit 104, the data transfer unit 105, the memory control unit 106, the nonvolatile memory control unit 108, the display control unit 110, the operation unit 113, the image sensor 102, and the like via the system bus 114. When the program recorded in the ROM 109 is executed by the CPU 112, various processes are performed by the image processing apparatus 100 according to the present embodiment.

  The display unit 111 includes, for example, a liquid crystal display device (liquid crystal monitor). The display unit 111 is controlled by the display control unit 110. Various image data and the like are displayed on the display unit 111. The operation unit 113 includes switches, buttons, and the like operated by the user. Power ON / OFF, shutter ON / OFF, and the like are performed by operating the operation unit 113.

  The image processing unit 104 includes a module (image processing module) that performs various types of image processing, and a buffer memory. The data transfer unit 105 includes a plurality of DMACs (Direct Memory Access Controllers) that perform data transfer.

  FIG. 2 is a block diagram showing the WRDMAC 202 provided in the data transfer unit 105 of the image processing apparatus 100 according to the present embodiment. 2 shows a module 201 provided in the image processing unit 104, a WRDMAC 202 provided in the data transfer unit 105, and a memory bus 115. FIG. 3 is a diagram showing an example of the configuration of the data storage area of the SRAM 207 provided in the WRDMAC 202 of the image processing apparatus 100 according to the present embodiment.

  Module A (MODULE A), that is, module 201 performs predetermined image processing. The module 201 and the WRDMAC 202 are connected by signal lines DATA_A, VALID_A, and STOP_A. Data that has undergone predetermined processing by the module 201 is transmitted to the WRDMAC 202 via the signal line DATA_A. Only in the valid data output period, the signal VALID_A supplied from the module 201 to the WRDMAC 202 is at a high level. When the WRDMAC 202 is in a BUSY state due to some cause and the WRDMAC 202 cannot accept data, the STOP_A signal supplied from the WRDMAC 202 to the module 201 becomes a high level. When the STOP_A signal becomes high level, data transmission from the module 201 to the WRDMAC 202 is stopped. The module 201 can function as a processing unit that sequentially outputs each of a plurality of blocks constituting an image.

  The WRDMAC (WRDMAC — 0) 202 includes an address calculation unit 203, a write control unit 204, an SRAM 207, a read control unit 208, and a bus I / F unit 209.

  The address calculation unit 203 calculates an address value when writing data to the DRAM 107 or the like. The address calculation unit 203 manages and controls the start address when image data is written in the DRAM 107, that is, the start address. The address calculation unit 203 can increment the address. The address calculation unit 203 manages and controls the data transfer length and the like. In the control of the data transfer length, the transfer burst length is set so as to correspond to the number of words that can be continuously accessed by one addressing. Here, a case where one word is 32 bytes, that is, 256 bits (bits) will be described as an example, but the present invention is not limited to this. Here, the transfer burst length can be set to 32, 64, or 128, for example. Note that the transfer burst length is not limited to these. The address calculation unit 203 can also update the address value by adding the offset value.

  The write control unit 204 performs control for writing the data received from the module (MODULE A) 201 to the SRAM 207. The SRAM 207 includes a memory bank 207a, a memory bank 207b, and a fractional data storage area 207c (see FIG. 3). For example, when data is being written to the memory bank 207a, that is, BANK0, it is possible to read data from the memory bank 207b, that is, BANK1. When data is being read from the memory bank 207a, that is, BANK0, data can be written to the memory bank 207b, that is, BANK1.

  The write controller 204 and the SRAM 207 are connected by signal lines WR_ADDR_0, WEN_0, and DIN_0. The write control unit 204 supplies a write address to the SRAM 207 via the signal line WR_ADDR_0. The write control unit 204 supplies data to the SRAM 207 via the signal line DIN_0. The write control unit 204 supplies a write enable signal to the SRAM 207 via the signal line WEN_0. When the write enable signal WEN_0 is at a high level, data supplied from the write control unit 204 is written into the SRAM 207.

  The read control unit 208 reads data from the SRAM 207 and supplies the read data to the bus I / F unit 209. The read control unit 208 and the SRAM 207 are connected by signal lines RD_ADDR_0, REN_0, and DOUT_0. The read control unit 208 supplies a read address to the SRAM 207 via the signal line RD_ADDR_0. The read control unit 208 reads data from the SRAM 207 via the signal line DOUT_0. When the signal REN_0 is at a high level, the data output from the SRAM 207 is read by the read control unit 208.

  The bus I / F unit 209 is an interface for exchanging signals with each functional block via the memory bus 115. The bus I / F unit 209 and the address calculation unit 203 are connected via a signal line MEM_ADDR_0. A write start address, which is an address when writing to the DRAM 107 is started, is supplied from the address arithmetic unit 203 to the bus I / F unit 209 via the signal line MEM_ADDR_0. Also, information indicating the transfer burst length is supplied from the address calculation unit 203 to the bus I / F unit 209 via the signal line MEM_ADDR_0.

  Data writing to the DRAM 107 is performed as follows. That is, data is supplied from the module (MODULE A) 201 to the WRDMAC (WRDMAC — 0) 202. The address calculation unit 203 supplies a write start address, which is an address when starting writing to the DRAM 107, and information indicating the transfer burst length to the bus I / F unit 209 via the signal line MEM_ADDR_0. The write control unit 204 writes the data supplied from the module 201 to the SRAM 207. When writing to the memory bank 207a of the SRAM 207, that is, BANK0, is completed, the bus I / F unit 209 transmits a request signal REQ_0, which is a signal for requesting permission to transfer data, via the memory bus 115. The bus I / F unit 209 transmits the write start address and information indicating the transfer burst length via the memory bus 115. When the DRAM 107 is in a writable state, a high-level permission signal ACK_ 0 indicating that writing is permitted is supplied to the bus I / F unit 209 via the memory bus 115. The read control unit 208 reads data from the memory bank 207 a of the SRAM 207, that is, BANK 0 through the signal line DOUT_ 0, and transmits the read data through the signal line WDATA_ 0 and the memory bus 115. In parallel with the reading of data from the memory bank 207a of the SRAM 207, data is written to the memory bank 207b of the SRAM 207. Data (image data) supplied from the module 201 is written to the DRAM 107 via the memory bus 115 by alternately and continuously writing to and reading from the memory bank 207a and the memory bank 207b.

  The WRDMAC 202 can function as a writing unit that writes the combined data aligned with the access unit of the DRAM 107 to the memory. The combined data is obtained, for example, by combining the second data that does not correspond to the first block with the first data that corresponds to a part of the first block among the plurality of blocks.

  FIG. 5 is a diagram illustrating a virtual address space corresponding to an image of one frame. As shown in FIG. 5, rectangular divided blocks (divided areas) 501a to 501l are defined by dividing one frame of image data into four in the horizontal direction and three in the vertical direction. From the module 201 to the WRDMAC 202, data transmission is executed in units of divided blocks 501a to 501l. Also, data transmission is performed from WRDMAC 202 to DRAM 107 in units of divided blocks 501a to 501l. In this specification, reference numerals 501a to 501l are used when describing individual divided blocks, and reference numerals 501 are used when general divided blocks are described. Each divided block 501 includes a plurality of lines (blocks) 503. The arrows in FIG. 5 conceptually indicate the access order. Note that the address at which the pixel data at the upper left corner of the image of one frame is written becomes the head address of the address area in which the image data is written. The address at which the head of the image data is written is, for example, address 0x1000 of the DRAM 107. The first line to the last line of the image are sequentially written at consecutive addresses. The data of the pixel located at the head of the (n + 1) th line of the image is written at the address next to the address where the data of the pixel located at the tail of the nth line of the image is written. The address to which the data of the pixel located at the lower right corner of the image is written is the last address in the address area to which the image data is written.

  First, the image data of the divided block 501a located at the upper left of FIG. 5 is transmitted. After the transmission of the image data of the divided block 501a is completed, the image data of the divided block 501b located on the right side of the divided block 501a is transmitted. After the transmission of the image data of the divided block 501b is completed, the image data of the divided block 501c located on the right side of the divided block 501b is transmitted. After the transmission of the image data of the divided block 501c is completed, the transmission of the image data of the divided block 501d located on the right side of the divided block 501c is performed. As described above, the image data of the divided blocks 501a to 501d positioned on the first block line 502a is sequentially transmitted. After the transmission of the image data of the divided blocks 501a to 501d positioned on the first block line 502a is completed, the transmission of the image data of the divided blocks 501e to 501h positioned on the second block line 502b is sequentially performed. . After the transmission of the image data of the divided blocks 501e to 501h positioned on the second block line 502b is completed, the transmission of the image data of the divided blocks 501i to 501l positioned on the third block line 502c is sequentially performed. . As described above, transmission of image data is performed in units of divided blocks 501. On the other hand, as described above, in the DRAM 107, it is necessary that the first line to the last line of the image are written in continuous addresses. The data size in the horizontal direction of the divided block 501 is, for example, 502 bytes. The number of lines in the vertical direction of the divided block 501 is 64, for example.

  Since transmission is performed with a transfer burst length corresponding to the size of a line included in the divided block 501, the following event may occur when processing described later is not performed. That is, as described above, the data size in the horizontal direction of the divided block 501 is, for example, 502 bytes. On the other hand, the burst access unit in the DRAM 107 is, for example, 32 bytes. For this reason, for example, 22 bytes of fractional data write access occurs at the right end of the first line of the divided block 501a. Such fraction data is not aligned with the burst access unit in the DRAM 107. When such fraction data that does not align with the burst access unit in the DRAM 107 is generated, the command overhead becomes larger than when data is aligned with the burst access unit in the DRAM 107.

  The SRAM 207 has a capacity of, for example, 512 words, that is, 16384 bytes. The addresses from the address 0x000 to the address 0x07F in the SRAM 207 are assigned to BANK0, that is, the memory bank 207a. The addresses from the address 0x080 to the address 0x0FF of the SRAM 207 are assigned to BANK1, that is, the memory bank 207b. The addresses from the address 0x100 to the address 0x1FF of the SRAM 207 are assigned to an area for storing fraction data 504LR, which will be described later, that is, a fraction data storage area 207c.

  4A and 4B are timing charts showing the operation of the image processing apparatus 100 according to the present embodiment. 4A and 4B show the operation of the SRAM 207 when data is written to the DRAM 107. FIG. 4A and 4B show signals WR_ADDR_0, WEN_0, DIN_0, RD_ADDR_0, REN_0, and DOUT_0. FIG. 4A shows the operation from timing t401 to timing t406, and FIG. 4B shows the operation from timing t405 to timing t410.

  A period 411 from timing t 401 to timing t 403 is a period in which the image data of the divided block 501 a output from the module 201 is written in the SRAM 207. In the period 411, the following processing is performed.

  First, data 504a1C (see FIG. 5) other than the fraction data 504a1R (see FIG. 5) located at the right end of the data of the first line of the divided block 501a is written into the SRAM 207. The size of the data 504a1C is, for example, 480 bytes. The data 504a1C is written into, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the data 504a1C is written to the SRAM 207 is, for example, 0x000. Note that reference numeral 504C is used when general data excluding fractional data included in the line 503 is described. Further, when the general fraction data located at the right end of the line 503 is described, reference numeral 504R is used.

  Next, fraction data 504a1R located at the right end of the data of the first line of the divided block 501a is written into the SRAM 207. The size of the data 504a1R is, for example, 22 bytes. The data 504a1R is written into the fraction data storage area 207c of the SRAM 207. The address when writing the data 504a1R to the SRAM 207 is, for example, 0x100.

  Next, data 504a2C other than the fraction data 504a2R located at the right end of the data of the second line of the divided block 501a is written into the SRAM 207. The size of the data 504a2C is, for example, 480 bytes. The data 504a2C is written into, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504a2C is written to the SRAM 207 is, for example, 0x080.

  Next, fraction data 504a2R located at the right end of the data of the second line of the divided block 501a is written into the SRAM 207. The size of the data 504a2R is, for example, 22 bytes. The data 504a2R is written to the fraction data storage area 207c of the SRAM 207. An address when the data 504a2R is written to the SRAM 207 is, for example, 0x101.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501a. As described above, the number of lines included in the divided block 501a is 64, for example. The data of the 64th line of the divided block 501a is processed as follows. That is, data 504a64C other than the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is written into the SRAM 207. The size of the data 504a64C is, for example, 480 bytes. The data 504a64C is written into the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504a64C is written to the SRAM 207 is, for example, 0x080. Thereafter, fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is written into the SRAM 207. The size of the data 504a64R is, for example, 22 bytes. The data 504a64R is written into the fraction data storage area 207c of the SRAM 207. The address when writing the data 504a64R to the SRAM 207 is, for example, address 0x13F.

  A period 412 from timing t402 to timing t404 is a period in which the image data of the divided block 501a is read from the SRAM 207. A part of the period 412 overlaps with a part of the period 411 described above. In the period 412, the following processing is performed.

  First, data 504a1C other than the fraction data 504a1R located at the right end of the data of the first line of the divided block 501a is read from the SRAM 207. The size of the data 504a1C is, for example, 480 bytes as described above. The data 504a1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504a1C from the SRAM 207 is, for example, 0x000. Data 504a1C read from the SRAM 207 is transmitted via the memory bus 151. As described above, the start address for writing image data to the DRAM 107, that is, the start address of the DRAM 107 is, for example, 0x1000. Therefore, the address calculation unit 203 sets the write start address when writing the data 504a1C to the DRAM 107 as the address 0x1000. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504a1C other than the fraction data 504a1R located at the right end of the data of the first line of the divided block 501a is written to the DRAM 107. The data 504a1C for 480 bytes is aligned in units of burst access in the DRAM 107. Note that the burst access unit in the DRAM 107 is, for example, 32 bytes as described above.

  Next, data 504a2C other than the fraction data 504a2R located at the right end of the data of the second line of the divided block 501a is read from the SRAM 207. The size of the data 504a2C is, for example, 480 bytes as described above. The data 504a2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when reading the data 504a2C from the SRAM 207 is, for example, address 0x080. Data 504a2C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504a2C by adding the offset value to the address 0x1000 that is the write start address of the data 504a1C. The offset value is determined as follows. As described above, the data size in the horizontal direction of the divided block 501 is, for example, 502 bytes. The number of divided blocks 501 in the horizontal direction is four. The size of dummy data to be described later for adjusting the alignment is 8 bytes. Therefore, the offset value is 502 × 4 + 8 = 2016 bytes. The write start address thus obtained is, for example, address 0x17E0. Thus, data 504a2C other than the fraction data 504a2R located at the right end of the data of the second line of the divided block 501a is written to the DRAM 107. The data 504a2C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501a. As described above, the number of lines included in the divided block 501a is 64, for example. The data of the 64th line of the divided block 501a is processed as follows. That is, data 504a64C other than the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is read from the SRAM 207. The size of the data 504a64C is, for example, 480 bytes. The data 504a64C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The head address when reading the data 504a64C from the SRAM 207 is, for example, address 0x080. Data 504a64C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504a64C by adding the offset value to the write start address of the data 504C other than the fraction data 504R located at the right end of the 63rd line of the divided block 501a. Thus, data 504a64C other than the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is written to the DRAM 107. The data 504a64C for 480 bytes is aligned in units of burst access in the DRAM 107.

  A period 413 from timing t403 to timing t405 is a period in which the image data of the divided block 501b output from the module 201 is written in the SRAM 207. A part of the period 413 overlaps with a part of the period 412 described above. In the period 413, the following processing is performed.

  First, fraction data 504b1L located at the left end of the data of the first line of the divided block 501b is written into the SRAM 207. The size of the data 504b1L is, for example, 10 bytes. The data 504b1L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504b1L to the SRAM 207 is, for example, 0x100. The fraction data 504a1R located at the right end of the first line of the divided block 501a has already been written at address 0x100. The fraction data 504b1L is written so as to follow the fraction data 504a1R. The size of the fraction data 504a1R is 22 bytes. The size of the fraction data 504b1L is 10 bytes. Accordingly, a total of 32 bytes of data are written at address 0x100 in the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107. It should be noted that reference numeral 504L is used when general fraction data located at the left end of the line 503 is described. In addition, when the general fraction data included in the line 503 is described, reference numeral 504LR is used.

  Next, data 504b1C among the data of the first line of the divided block 501b is written into the SRAM 207. Data 504b1C is data obtained by removing the fraction data 504b1L located at the left end of the line and the fraction data 504b1R located at the right end of the line from the data of the first line of the divided block 501b. The size of the data 504b1C is, for example, 480 bytes. The data 504b1C is written into, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the data 504b1C is written to the SRAM 207 is, for example, 0x000.

  Next, fraction data 504b1R located at the right end of the data of the first line of the divided block 501b is written into the SRAM 207. The size of the data 504b1R is, for example, 12 bytes. The data 504b1R is written to the fraction data storage area 207c of the SRAM 207. The address when the data 504b1R is written to the SRAM 207 is, for example, 0x180.

  Next, fraction data 504b2L located at the left end of the data of the second line of the divided block 501b is written into the SRAM 207. The size of the data 504b2L is, for example, 10 bytes. The data 504b2L is written to the fraction data storage area 207c of the SRAM 207. An address when the data 504b2L is written to the SRAM 207 is, for example, 0x101. The fraction data 504a2R located at the right end of the second line of the divided block 501a has already been written at address 0x101. The fraction data 504b2L is written so as to follow the fraction data 504a2R. The size of the fraction data 504a2R is 22 bytes. The size of the fraction data 504b2L is 10 bytes. Accordingly, a total of 32 bytes of data are written in the address 0x101 of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  Next, data 504b2C among the data of the second line of the divided block 501b is written into the SRAM 207. Data 504b2C is data obtained by removing the fraction data 504b2L located at the left end of the line and the fraction data 504b2R located at the right end of the line from the data of the second line of the divided block 501b. The size of the data 504b2C is, for example, 480 bytes. The data 504b2C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The start address when writing the data 504b2C to the SRAM 207 is, for example, address 0x080.

  Next, fraction data 504b2R located at the right end of the data of the second line of the divided block 501b is written into the SRAM 207. The size of 504b2R is, for example, 12 bytes. 504b2R is written in the fraction data storage area 207c of the SRAM 207. The address when writing 504b2R to the SRAM 207 is, for example, address 0x181.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501b. For example, the 10-byte fraction data 504b3L located at the left end of the third line data of the divided block 501b is written to, for example, 0x102 in the fraction data storage area 207c of the SRAM 207. As described above, the number of lines included in the divided block 501b is 64, for example. The fraction data 504b64L (see FIG. 5) located at the left end of the data of the 64th line of the divided block 501b is written to the SRAM 207. The size of the data 504b64L is, for example, 10 bytes. The data 504b64L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504b64L to the SRAM 207 is, for example, address 0x13F. The fraction data 504a64R located at the right end of the 64th line of the divided block 501b has already been written at address 0x13F. The fraction data 504b64L is written so as to follow the fraction data 504a64R. The size of the fraction data 504a64R is 22 bytes. The size of the fraction data 504b64L is 10 bytes. Accordingly, a total of 32 bytes of data are written in the address 0x13F of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107. Thereafter, data 504b64C among the data of the 64th line of the divided block 501b is written into the SRAM 207. Data 504b64C is data obtained by removing the fraction data 504b64L located at the left end of the line and the fraction data 504b64R located at the right end of the line from the data of the 64th line of the divided block 501b. The size of the data 504b64C is, for example, 480 bytes. The data 504b64C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when writing the data 504b64C to the SRAM 207 is, for example, address 0x080. Thereafter, the fraction data 504b64R located at the right end of the data of the 64th line of the divided block 501b is written into the SRAM 207. The size of the data 504b64R is, for example, 12 bytes. The data 504b64R is written into the fraction data storage area 207c of the SRAM 207. The address when writing the data 504b64R to the SRAM 207 is, for example, address 0x1BF.

  A period 414 from timing t404 to timing t406 is a period in which the image data of the divided block 501b is read from the SRAM 207. A part of the period 414 overlaps with a part of the period 413 described above. In the period 414, the following processing is performed.

  First, the fraction data 504a1R and 504b1L stored at address 0x100 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504a1R is located at the right end of the first line of the divided block 501a. As described above, the fraction data 504b1L is located at the left end of the first line of the divided block 501b.

  Next, data 504b1C among the data of the first line of the divided block 501b is read from the SRAM 207. As described above, the data 504b1C is data obtained by removing the fraction data 504b1L located at the left end of the line and the fraction data 504b1R located at the right end of the line from the data of the first line of the divided block 501b. It is. The size of the data 504b1C is, for example, 480 bytes as described above. The data 504b1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504b1C from the SRAM 207 is, for example, 0x000.

  These data read from the SRAM 207, that is, the fraction data 504a1R, 504b1L and the data 504b1C are transmitted via the memory bus 151. The write start address of the fraction data 504a1R and 504b1L is, for example, address 0x11E0. The write address of the data 504b1C is, for example, 0x1200 address. As described above, the size of the fraction data 504a1R is 22 bytes. Further, as described above, the size of the fraction data 504b1L is 10 bytes. As described above, the size of the data 504b1C is 480 bytes. Therefore, the total size of these data 504a1R, 504b1L, and 504b1C read from the SRAM 207 is 512 bytes. These data 504a1R, 504b1L, and 504b1C whose total size is 512 bytes are aligned in burst access units in the DRAM 107. Thus, the fraction data 504a1R, 504b1L and the data 504b1C are written to the address immediately after the address in the DRAM 107 where the data 504a1C is written. In other words, the combined data obtained by combining the fraction data 504b1L and the fraction data 504b1L and the data 504b1C are sequentially written to the address immediately after the address where the data 504a1C is written in the DRAM 107.

  Next, the fraction data 504a2R and 504b2L stored at address 0x101 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504a2R is located at the right end of the second line of the divided block 501a. As described above, the fraction data 504b2L is located at the left end of the second line of the divided block 501b.

  Next, data 504b2C among the data of the second line of the divided block 501b is read from the SRAM 207. As described above, the data 504b2C is data obtained by removing the fraction data 504b2L located at the left end of the line and the fraction data 504b2R located at the right end of the line from the data of the second line of the divided block 501b. It is. The size of the data 504b2C is, for example, 480 bytes as described above. The data 504b2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The head address when reading the data 504b2C from the SRAM 207 is, for example, 0x080.

  These data read from the SRAM 207, that is, the fraction data 504a2R, 504b2L and the data 504b2C are transmitted via the memory bus 151. The address calculation unit 203 adds the offset values to generate write start addresses for these data 504a2R, 504b2L, and 504b2C. As described above, the offset value is, for example, 2016 bytes. Thus, the fraction data 504a2R, 504b2L and the data 504b2C are written to the address immediately after the address where the data 504a2C is written in the DRAM 107. In other words, the combined data obtained by combining the fraction data 504b2L and the fraction data 504b2L and the data 504b2C are sequentially written to the address immediately after the address where the data 504a2C is written in the DRAM 107. These 512-byte data 504a2R, 504b2L, and 504b2C are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501b. As described above, the number of lines included in the divided block 501b is 64, for example. Accordingly, the same processing as described above is repeatedly performed up to the 64th line of the divided block 501b.

  A period 415 from timing t405 to timing t407 is a period in which the image data of the divided block 501c output from the module 201 is written in the SRAM 207. A part of the period 415 overlaps with a part of the period 414 described above. In the period 415, the following processing is performed.

  First, fraction data 504c1L located at the left end of the data of the first line of the divided block 501c is written into the SRAM 207. The size of the data 504c1L is, for example, 20 bytes. The data 504c1L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504c1L to the SRAM 207 is, for example, address 0x180. The fraction data 504b1R located at the right end of the first line of the divided block 501b has already been written at address 0x180. The fraction data 504c1L is written so as to follow the fraction data 504b1R. The size of the fraction data 504b1R is 12 bytes. The size of the fraction data 504c1L is 20 bytes. Accordingly, a total of 32 bytes of data is written at address 0x180 of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  Next, data 504c1C of the data of the first line of the divided block 501c is written into the SRAM 207. Data 504c1C is data obtained by removing the fraction data 504c1L located at the left end of the line and the fraction data 504c1R located at the right end of the line from the data of the first line of the divided block 501c. The size of the data 504c1C is, for example, 480 bytes. The data 504c1C is written to, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the data 504c1C is written to the SRAM 207 is, for example, 0x000.

  Next, fraction data 504c1R located at the right end of the data of the first line of the divided block 501c is written into the SRAM 207. The size of the data 504c1R is, for example, 2 bytes. The data 504c1R is written into the fraction data storage area 207c of the SRAM 207. An address when the data 504c1R is written to the SRAM 207 is, for example, 0x100.

  Next, fraction data 504c2L located at the left end of the data of the second line of the divided block 501c is written into the SRAM 207. The size of the data 504c2L is, for example, 20 bytes. The data 504c2L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504c2L to the SRAM 207 is, for example, 0x181. The fraction data 504b2R located at the right end of the second line of the divided block 501b has already been written at address 0x181. The fraction data 504c2L is written to follow the fraction data 504b2R. The size of the fraction data 504b2R is 12 bytes. The size of the fraction data 504c2L is 20 bytes. Accordingly, a total of 32 bytes of data are written to address 0x181 of SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  Next, data 504c2C of the data of the second line of the divided block 501c is written into the SRAM 207. Data 504c2C is data obtained by removing the fraction data 504c2L located at the left end of the line and the fraction data 504c2R located at the right end of the line from the data of the second line of the divided block 501c. The size of the data 504c2C is, for example, 480 bytes. The data 504c2C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504c2C is written to the SRAM 207 is, for example, 0x080.

  Next, fraction data 504c2R located at the right end of the data of the second line of the divided block 501c is written into the SRAM 207. The size of the fraction data 504c2R is, for example, 2 bytes. The data 504c2R is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504c2R to the SRAM 207 is, for example, 0x101.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501c. For example, for example, 20-byte fraction data 504c3L located at the left end of the data of the third line of the divided block 501c is written to, for example, address 0x182 in the fraction data storage area 207c of the SRAM 207. The fraction data 504c64L (see FIG. 5) located at the left end of the data of the 64th line of the divided block 501c is written into the SRAM 207. The size of the data 504c64L is, for example, 20 bytes. The data 504c64L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504c64L to the SRAM 207 is, for example, address 0x1BF. The fraction data 504b64R located at the right end of the 64th line of the divided block 501b has already been written in the address 0x1BF. The fraction data 504c64L is written so as to follow the fraction data 504b64R. The size of the fraction data 504b64R is 12 bytes. The size of the fraction data 504c64L is 20 bytes. Accordingly, a total of 32 bytes of data are written in the address 0x1BF of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107. Thereafter, data 504c64C among the data of the 64th line of the divided block 501c is written into the SRAM 207. The data 504c64C is data obtained by removing the fraction data 504c64L located at the left end of the line and the fraction data 504c64R located at the right end of the line from the data of the 64th line of the divided block 501c. The size of the data 504c64C is, for example, 480 bytes. The data 504c64C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504c64C is written to the SRAM 207 is, for example, 0x080. Thereafter, fraction data 504c64R located at the right end of the data of the 64th line of the divided block 501c is written into the SRAM 207. The size of the data 504c64R is, for example, 2 bytes. The data 504c64R is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504c64R to the SRAM 207 is, for example, address 0x13F.

  A period 416 from timing t406 to timing t408 is a period in which the image data of the divided block 501c is read from the SRAM 207. A part of the period 416 overlaps with a part of the period 415 described above. In the period 416, the following processing is performed.

  First, the fraction data 504b1R and 504c1L stored at address 0x180 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504b1R is located at the right end of the first line of the divided block 501b. As described above, the fraction data 504c1L is located at the left end of the first line of the divided block 501c.

  Next, data 504c1C of the data of the first line of the divided block 501c is read from the SRAM 207. As described above, the data 504c1C is data obtained by removing the fraction data 504c1L located at the left end of the line and the fraction data 504c1R located at the right end of the line from the data of the first line of the divided block 501c. It is. The size of the data 504c1C is, for example, 480 bytes as described above. The data 504c1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504c1C from the SRAM 207 is, for example, 0x000.

  These data read from the SRAM 207, that is, the fraction data 504b1R, 504c1L and the data 504c1C are transmitted via the memory bus 151. The write start address of the fraction data 504b1R and 504c1L is, for example, address 0x13E0. The write address of the data 504c1C is, for example, address 0x1400. As described above, the size of the fraction data 504b1R is 12 bytes. Further, as described above, the size of the fraction data 504c1L is 20 bytes. As described above, the size of the data 504c1C is 480 bytes. Therefore, the total size of these data 504b1R, 504c1L, and 504c1C read from the SRAM 207 is 512 bytes. These data 504b1R, 504c1L, and 504c1C having a total size of 512 bytes are aligned in burst access units in the DRAM 107. In this way, the fraction data 504b1R, 504c1L and the data 504c1C are written to the address immediately after the address where the data 504b1C is written in the DRAM 107. In other words, the combined data obtained by combining the fraction data 504c1L and the fraction data 504c1L and the data 504c1C are sequentially written to the address immediately after the address where the data 504b1C is written in the DRAM 107.

  Next, the fraction data 504b2R and 504c2L stored at address 0x181 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504b2R is located at the right end of the second line of the divided block 501b. As described above, the fraction data 504c2L is located at the left end of the second line of the divided block 501c.

  Next, data 504c2C among the data of the second line of the divided block 501c is read from the SRAM 207. As described above, the data 504c2C is data obtained by removing the fraction data 504c2L located at the left end of the line and the fraction data 504c2R located at the right end of the line from the data of the second line of the divided block 501c. It is. The size of the data 504c2C is, for example, 480 bytes as described above. The data 504c2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when reading the data 504c2C from the SRAM 207 is, for example, 0x080.

  These data read from the SRAM 207, that is, the fraction data 504b2R, 504c2L and the data 504c2C are transmitted via the memory bus 151. The address calculation unit 203 adds the offset values to generate write start addresses for these data 504b2R, 504c2L, and 504c2C. As described above, the offset value is, for example, 2016 bytes. Thus, the fraction data 504b2R, 504c2L and the data 504c2C are written to the address immediately after the address in the DRAM 107 where the data 504b2C is written. In other words, the combined data obtained by combining the fraction data 504c2L and the fraction data 504c2L and the data 504c2C are sequentially written to the address immediately after the address where the data 504b2C is written in the DRAM 107. These 512 bytes of data 504b2R, 504c2L, and 504c2C are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501c. As described above, the number of lines included in the divided block 501c is 64, for example. Accordingly, the same processing as described above is repeatedly performed up to the 64th line of the divided block 501c.

  A period 417 from timing t407 to timing t409 is a period in which the image data of the divided block 501b output from the module 201 is written in the SRAM 207. A part of the period 417 overlaps with a part of the period 416 described above. In the period 417, the following processing is performed.

  First, fraction data 504d1L located at the left end of the data of the first line of the divided block 501d is written to the SRAM 207. The size of the data 504d1L is, for example, 30 bytes. The data 504d1L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504d1L to the SRAM 207 is, for example, 0x100. The fraction data 504c1R located at the right end of the first line of the divided block 501c is already written at address 0x100. The fraction data 504d1L is written to follow the fraction data 504c1R. The size of the fraction data 504c1R is 2 bytes. The size of the fraction data 504d1L is 30 bytes. Accordingly, a total of 32 bytes of data are written at address 0x100 in the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  Next, data 504d1C of the data of the first line of the divided block 501d is written into the SRAM 207. Data 504d1C is data obtained by removing the fraction data 504d1L located at the left end of the line and the fraction data 504d1R located at the right end of the line from the data of the first line of the divided block 501d. The size of the data 504d1C is, for example, 448 bytes. The data 504d1C is written to, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The start address when writing the data 504d1C to the SRAM 207 is, for example, 0x000.

  Next, the fraction data 504d1R located at the right end of the data of the first line of the divided block 501d and the dummy data 504d1D are written into the SRAM 207. The size of the data 504d1R is, for example, 24 bytes. The size of the dummy data 504d1D is, for example, 8 bytes. The fraction data 504d1R and the dummy data 504d1D are written in the fraction data storage area 207c of the SRAM 207. The address when the fraction data 504d1R and the dummy data 504d1D are written to the SRAM 207 is, for example, 0x180. The size of the fraction data 504d1R is 24 bytes as described above. The size of the dummy data 504d1D is 8 bytes. Accordingly, a total of 32 bytes of data is written at address 0x180 of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107. Note that reference numeral 504D is used when general dummy data is described. As the dummy data 504D, data that can be distinguished from normal data is used. For example, data having a value of 0 can be used as the dummy data 504D.

  Next, fraction data 504d2L located at the left end of the data of the second line of the divided block 501c is written into the SRAM 207. The size of the data 504d2L is, for example, 30 bytes. The data 504d2L is written to the fraction data storage area 207c of the SRAM 207. The address when writing the data 504d2L to the SRAM 207 is, for example, 0x101. The fraction data 504c2R located at the right end of the second line of the divided block 501c has already been written at address 0x101. The fraction data 504d2L is written to follow the fraction data 504c2R. The size of the fraction data 504c2R is 2 bytes. The size of the fraction data 504d2L is 30 bytes. Accordingly, a total of 32 bytes of data are written in the address 0x101 of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  Next, data 504d2C of the data on the second line of the divided block 501d is written into the SRAM 207. Data 504d2C is data obtained by removing the fraction data 504d2L located at the left end of the line and the fraction data 504d2R located at the right end of the line from the data of the second line of the divided block 501d. The size of the data 504d2C is, for example, 448 bytes. The data 504d2C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504d2C is written to the SRAM 207 is, for example, 0x080.

  Next, the fraction data 504d2R located at the right end of the data of the second line of the divided block 501d and the dummy data 504d2D are written into the SRAM 207. The size of the data 504d2R is, for example, 24 bytes. The size of the dummy data 504d2D is, for example, 8 bytes. The fraction data 504d2R and the dummy data 504d2D are written in the fraction data storage area 207c of the SRAM 207. The address when the fraction data 504d2R and the dummy data 504d2D are written to the SRAM 207 is, for example, address 0x181. The size of the fraction data 504d2R is 24 bytes as described above. The size of the dummy data 504d2D is 8 bytes. Accordingly, a total of 32 bytes of data are written to address 0x181 of SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501d. For example, for example, 30-byte fraction data 504d3L located at the left end of the data of the third line of the divided block 501b is written to, for example, 0x102 in the fraction data storage area 207c of the SRAM 207. As described above, the number of lines included in the divided block 501d is 64, for example. The fraction data 504d64L (see FIG. 5) located at the left end of the data of the 64th line of the divided block 501d is written to the SRAM 207. The size of the data 504d64L is, for example, 30 bytes. The data 504d64L is written in the fraction data storage area 207c of the SRAM 207. The address when writing the data 504d64L to the SRAM 207 is, for example, address 0x13F. The fraction data 504c64R located at the right end of the 64th line of the divided block 501c is already written at the address 0x13F. The fraction data 504d64L is written so as to follow the fraction data 504c64R. The size of the fraction data 504c64R is 2 bytes. The size of the fraction data 504d64L is 30 bytes. Accordingly, a total of 32 bytes of data are written in the address 0x13F of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107. Thereafter, data 504d64C among the data of the 64th line of the divided block 501d is written into the SRAM 207. Data 504d64C is data obtained by removing the fraction data 504d64L located at the left end of the line and the fraction data 504d64R located at the right end of the line from the data of the 64th line of the divided block 501d. The size of the data 504d64C is, for example, 448 bytes. The data 504d64C is written in, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504d64C is written to the SRAM 207 is, for example, 0x080. Thereafter, the fraction data 504d64R located at the right end of the data of the 64th line of the divided block 501d and the dummy data 504d64D are written into the SRAM 207. The size of the data 504d64R is, for example, 24 bytes. The size of the dummy data 504d64D is, for example, 8 bytes. The fraction data 504d64R and the dummy data 504d64D are written in the fraction data storage area 207c of the SRAM 207. The address when writing the fraction data 504d64R and the dummy data 504d64D into the SRAM 207 is, for example, address 0x1BF. The size of the fraction data 504d64R is 24 bytes as described above. The size of the dummy data 504d64D is 8 bytes. Accordingly, a total of 32 bytes of data are written in the address 0x1BF of the SRAM 207. The 32-byte data is aligned in burst access units in the DRAM 107.

  A period 418 from timing t408 to timing t410 is a period in which the image data of the divided block 501d is read from the SRAM 207. Part of the period 418 overlaps with part of the period 417 described above. In the period 418, the following processing is performed.

  First, fraction data 504c1R and data 504d1L stored at address 0x100 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504c1R is located at the right end of the first line of the divided block 501c. As described above, the fraction data 504d1L is located at the left end of the first line of the divided block 501d.

  Next, data 504d1C of the data of the first line of the divided block 501d is read from the SRAM 207. As described above, the data 504d1C is data obtained by removing the fraction data 504d1L located at the left end of the line and the fraction data 504d1R located at the right end of the line from the data of the first line of the divided block 501d. It is. As described above, the size of the data 504d1C is, for example, 448 bytes. The data 504d1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504d1C from the SRAM 207 is, for example, 0x000.

  Next, the fraction data 504d1R and the dummy data 504d1D stored at address 0x180 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504d1R is located at the right end of the first line of the divided block 501d.

  These data read from the SRAM 207, that is, the fraction data 504c1R, the data 504d1L, the data 504d1C, the fraction data 504d1R, and the dummy data 504d1D are transmitted via the memory bus 151. The write start address of the fraction data 504c1R and data 504d1L is, for example, 0x15E0. The write address of the data 504d1C is, for example, address 0x1600. Write addresses of the fraction data 504d1R and the dummy data 504d1D are, for example, address 0x17C0. As described above, the size of the fraction data 504c1R is 2 bytes. Further, as described above, the size of the fraction data 504d1L is 30 bytes. As described above, the size of the data 504d1C is 448 bytes. Further, as described above, the size of the fraction data 504d1R is 24 bytes. Further, as described above, the size of the dummy data 504d1D is 8 bytes. Therefore, the total size of these data 504c1R, 504d1L, 504d1C, 504d1R, and 504d1D read from the SRAM 207 is 512 bytes. These data 504 c 1 R, 504 d 1 L, 504 d 1 C, 504 d 1 R, and 504 d 1 D having a total size of 512 bytes are aligned in burst access units in the DRAM 107. Thus, the fraction data 504c1R, the data 504d1L, the data 504d1C, the fraction data 504d1R, and the dummy data 504d1D are written to the address immediately after the address where the data 504c1C is written in the DRAM 107. In other words, the following data is sequentially written in the address immediately after the address where the data 504c1C is written in the DRAM 107. That is, the combined data obtained by combining the fraction data 504c1R with the fraction data 504d1L, the data 504d1C, and the combined data obtained by combining the dummy data 504d1D with the fraction data 504d1R are sequentially written.

  Next, the fraction data 504c2R and 504d2L stored at address 0x101 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504c2R is located at the right end of the second line of the divided block 501c. As described above, the fraction data 504d2L is located at the left end of the second line of the divided block 501d.

  Next, data 504d2C of the data of the second line of the divided block 501c is read from the SRAM 207. As described above, the data 504d2C is data obtained by removing the fraction data 504d2L located at the left end of the line and the fraction data 504d2R located at the right end of the line from the data of the second line of the divided block 501c. It is. As described above, the size of the data 504d2C is, for example, 448 bytes. The data 504d2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The head address when reading the data 504d2C from the SRAM 207 is, for example, address 0x080.

  Next, the fraction data 504d2R and the dummy data 504d2D stored at address 0x181 in the fraction data storage area 207c of the SRAM 207 are read. As described above, the fraction data 504d2R is located at the right end of the second line of the divided block 501d.

  These data read from the SRAM 207, that is, fraction data 504c2R, 504d2L, data 504d2C, fraction data 504d2R, and dummy data 504d2D are transmitted via the memory bus 151. The address calculation unit 203 adds the offset values to generate write start addresses for these data 504c2R, 504d2L, 504d2C, 504d2R, and 504d2D. As described above, the offset value is, for example, 2016 bytes. As described above, the size of the fraction data 504c2R is 2 bytes. Further, as described above, the size of the fraction data 504d2L is 30 bytes. As described above, the size of the data 504d2C is 448 bytes. Further, as described above, the size of the fraction data 504d2R is 24 bytes. Further, as described above, the size of the dummy data 504d2D is 8 bytes. Therefore, the total size of these data 504c2R, 504d2L, 504d2C, 504d2R, and 504d2D read from the SRAM 207 is 512 bytes. These data 504c2R, 504d2L, 504d2C, 504d2R, and 504d2D having a total size of 512 bytes are aligned in burst access units in the DRAM 107. Thus, the fractional data 504c2R, 504d2L, the data 504d2C, the fractional data 504d2R, and the dummy data 504d2D are written to the address immediately after the address where the data 504c2C is written in the DRAM 107. In other words, the following data is sequentially written in the address immediately after the address where the data 504c2C is written in the DRAM 107. That is, the combined data obtained by combining the fraction data 504d2L with the fraction data 504c2R, the data 504d2C, and the combined data obtained by combining the dummy data 504d2D with the fraction data 504d2R are sequentially written.

Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501d. As described above, the number of lines included in the divided block 501d is 64, for example. Accordingly, the same processing as described above is repeatedly performed up to the 64th line of the divided block 501c.
Thereafter, the processing for the divided blocks 501e to 501l is performed in the same manner as described above.

  It should be noted that the fraction data located at the right end of each line of the divided block 501d and the fraction data located at the left end of each line of the divided block 501a are combined and written into the fraction data storage area 207c of the SRAM 207. Good. In this case, such data is written at the end of each line of the divided block 501d. Data obtained by combining the fraction data located at the right end of each line of the divided block 501d and the fraction data located at the left end of each line of the divided block 501a can also be aligned in the burst access unit of the DRAM 107.

  As described above, according to the present embodiment, the size of the fraction data is adjusted so as to align with the burst access unit in the DRAM 107. For this reason, according to this embodiment, command overhead can be reduced and a decrease in writing speed can be suppressed.

[Second Embodiment]
An image processing apparatus and an image processing method according to the second embodiment will be described with reference to FIGS. The same components as those of the image processing apparatus according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The image processing apparatus 100 according to the present embodiment temporarily stores fraction data 504LR and dummy data 504D in an SRAM 237 provided in a WRDMAC 232 different from the WRDMAC 202.

  FIG. 6 is a block diagram showing the WRDMACs 202, 212, 222, and 232 provided in the data transfer unit 105 of the image processing apparatus 100 according to the present embodiment. FIG. 6 shows modules 201, 211, 221, a selector 251, WRDMACs 202, 212, 222, 232, and a memory bus 115. The module 201, that is, the module A (MODULE A) is provided in the image processing unit 104 as described above in the first embodiment. The module B (MODULE B), that is, the module 211 is also provided in the image processing unit 104. The module C (MODULE C), that is, the module 221 is also provided in the image processing unit 104. FIG. 7 is a diagram illustrating an example of the configuration of the data storage areas of the SRAMs 207 and 237 provided in the WRDMACs 202 and 232 of the image processing apparatus 100 according to the present embodiment, respectively.

  Modules 201, 211, and 221 perform predetermined image processing, respectively. Modules 201, 211, 221 and WRDMAC 202, 212, 222, 232 can be connected via a selector 251. Data output from the modules 201, 211, and 221 is transmitted through signal lines DATA_A, DATA_B, and DATA_C, respectively. Data is supplied to WRDMACs 202, 212, 222, and 232 through signal lines DATA_0, DATA_1, DATA_2, and DATA_3, respectively. Signals indicating the valid data output period are output from the modules 201, 211, and 221 via the signal lines VALID_A, VALID_B, and VALID_C, respectively. A signal indicating that it is a valid data output period is supplied to WRDMACs 202, 212, 222, and 232 through signal lines VALID_0, VALID_1, VALID_2, and VALID_3, respectively. Signals indicating that the WRDMACs 202, 212, 222, and 232 cannot accept data are output from the WRDMACs 202, 212, 222, and 232 through the signal lines STOP_0, STOP_1, STOP_2, and STOP_3, respectively. A signal indicating that the WRDMAC 202, 212, 222, 232 cannot accept data is supplied to the modules 201, 211, 221 via the signal lines STOP_A, STOP_B, STOP_C, respectively. The selector 251 appropriately selects the supply destination of these signals.

  As described above in the first embodiment, the WRDMAC (WRDMAC — 0) 202 includes the address calculation unit 203, the write control unit 204, the SRAM 207, the read control unit 208, and the bus I / F unit 209. The WRDMAC (WRDMAC_1) 212 includes an address calculation unit 213, a write control unit 214, an SRAM 217, a read control unit 218, and a bus I / F unit 219. The WRDMAC (WRDMAC_2) 222 includes an address calculation unit 223, a write control unit 224, an SRAM 227, a read control unit 228, and a bus I / F unit 229. The WRDMAC (WRDMAC — 3) 232 includes an address calculation unit 233, a write control unit 234, an SRAM 237, a read control unit 238, and a bus I / F unit 239. The SRAM 207 includes two memory banks 207a and 207b as described above in the first embodiment. The SRAM 217 includes two memory banks 217a and 217b. The SRAM 227 includes two memory banks 227a and 227b. The SRAM 237 includes two memory banks 237a and 237b.

  The address calculation units 213, 223, and 233 have the same functions as the address calculation unit 203. The write control units 214, 224, and 234 have the same functions as the write control unit 204. The SRAMs 217, 227, and 237 have the same functions as the SRAM 207. The read control units 218, 228, and 238 have the same functions as the read control unit 208. The bus I / F units 219, 229, and 239 have the same functions as the bus I / F unit 209.

  A write memory bus 260 is provided between the write controllers 204, 214, 224, and 234 and the SRAMs 207, 217, 227, and 237. A memory bus 261 for reading is provided between the SRAMs 207, 217, 227, and 237 and the reading control units 208, 218, 228, and 238. The write controllers 204, 214, 224, and 234 access the SRAMs 207, 217, 227, and 237 provided in the WRDMAC different from the WRDMACs 202, 212, 222, and 232 provided with the write controller via the memory bus 260. Can do. For example, the SRAM write control unit 204 provided in the WRDMAC 202 can perform a write process on the SRAM 237 provided in the WRDMAC 232 via the memory bus 260.

  Here, a case where the modules 201, 211, 221 and the WRDMAC 202, 212, 222, 232 are connected as described below will be described as an example. That is, the module 201 is connected to the WRDMAC 202 via the selector 251. The module 211 is connected to the WRDMAC 212 via the selector 251. The module 221 is connected to the WRDMAC 222 via the selector 251. The WRDMAC 232 is not connected to any of the modules 201, 211, and 221 and is in an unused state. Here, a case where the SRAM 207 provided in the WRDMAC 202 is used to store data 504C that is neither the fraction data 504LR nor the dummy data 504D will be described as an example. Here, a case where the SRAM 237 provided in the WRDMAC 232 which is an unused WRDMAC is used to store the fraction data 504LR and the dummy data 504D will be described as an example.

  Write addresses output from the write controllers 204, 214, 224, and 234 are supplied via signal lines WR_ADDR_0_IBUS, WR_ADDR_1_IBUS, WR_ADDR_2_IBUS, and WR_ADDR_3_IBUS. Write addresses are supplied to the SRAMs 207, 217, 227, and 237 through signal lines WR_ADDR_0_OBUS, WR_ADDR_1_OBUS, WR_ADDR_2_OBUS, and WR_ADDR_3_OBUS, respectively.

  Write enable signals output from the write controllers 204, 214, 224, and 234 are supplied via signal lines WEN_0_IBUS, WEN_1_IBUS, WEN_2_IBUS, and WEN_3_IBUS, respectively. Write enable signals are supplied to the SRAMs 207, 217, 227, and 237 through signal lines WEN_0_OBUS, WEN_1_OBUS, WEN_2_OBUS, and WEN_3_OBUS, respectively.

  Data output from the write control units 204, 214, 224, and 234 is supplied via signal lines DIN_0_IBUS, DIN_1_IBUS, DIN_2_IBUS, and DIN_3_IBUS, respectively. Data is supplied to the SRAMs 207, 217, 227, and 237 through the signal lines DIN_0_OBUS, DIN_1_OBUS, DIN_2_OBUS, and DIN_3_OBUS, respectively.

  The read control units 208, 218, 228, and 238 supply read addresses via signal lines RD_ADDR_0_IBUS, RD_ADDR_1_IBUS, RD_ADDR_2_IBUS, and RD_ADDR_3_IBUS. Read addresses are supplied to the SRAMs 207, 217, 227, and 237 through the signal lines RD_ADDR_0_OBUS, RD_ADDR_1_OBUS, RD_ADDR_2_OBUS, and RD_ADDR_3_OBUS, respectively.

  The read control units 208, 218, 228, and 238 supply read enable signals via the signal lines REN_0_IBUS, REN_1_IBUS, REN_2_IBUS, and REN_3_IBUS. Read enable signals are supplied to the SRAMs 207, 217, 227, and 237 through the signal lines REN_0_OBUS, REN_1_OBUS, REN_2_OBUS, and REN_3_OBUS, respectively.

  The SRAMs 207, 217, 227, and 237 supply data via signal lines DOUT_0_OBUS, DOUT_1_OBUS, DOUT_2_OBUS, and DOUT_3_OBUS. Data is supplied to the read controllers 208, 218, 228, and 238 through the signal lines DOUT_0_IBUS, DOUT_1_IBUS, DOUT_2_IBUS, and DOUT_3_IBUS.

  The address calculation units 203, 213, 223, and 233 supply the following signals to the bus I / F units 209, 219, 229, and 239 through the signal lines MEM_ADDR_0, MEM_ADDR_1, MEM_ADDR_2, and MEM_ADDR_3, respectively. The address calculation units 203, 213, 223, and 233 supply the write start address when writing to the DRAM 107 via the signal lines MEM_ADDR_0, MEM_ADDR_1, MEM_ADDR_2, and MEM_ADDR_3, respectively. Further, the address arithmetic units 203, 213, 223, and 233 supply information indicating the transfer burst length via the signal lines MEM_ADDR_0, MEM_ADDR_1, MEM_ADDR_2, and MEM_ADDR_3, respectively.

  The bus I / F units 209, 219, 229, and 239 transmit request signals REQ_0, REQ_1, REQ_2, and REQ_3 via the memory bus 115, respectively. Permission signals ACK_0, ACK_1, ACK_2, and ACK_3 indicating that writing is permitted are supplied to the bus I / F units 209, 219, 229, and 239 via the memory bus 115, respectively. Data read from each of the SRAMs 207, 217, 227, and 237 is transmitted via the signal lines WDATA_0, WDATA_1, WDATA_2, and WDATA_3, respectively, and further via the memory bus 115.

  The data 504C that is neither the fraction data 504LR nor the dummy data 504D is temporarily stored in the SRAM 207 provided in the WRDMAC 202, as in the first embodiment. On the other hand, the fraction data 504LR and the dummy data 504D are temporarily stored in, for example, an SRAM 237 provided in the WRDMAC 232, which is a WRDMAC different from the WRDMAC 202.

  Specifically, the data 504C that is neither the fraction data 504LR nor the dummy data 504D is written into the SRAM 207 as follows. The write control unit 204 supplies a write address to the SRAM 207 via the signal line WR_ADDR_0_IBUS, the memory bus 260, and the signal line WR_ADDR_0_OBUS. Further, the write control unit 204 supplies a write enable signal to the SRAM 207 via the signal line WEN_0_IBUS, the memory bus 260, and the signal line WEN_0_OBUS. Further, the write control unit 204 supplies data to the SRAM 207 via the signal line DIN_0_IBUS, the memory bus 260, and the signal line DIN_0_OBUS. In this way, data 504C that is neither the fraction data 504LR nor the dummy data 504D is written to the SRAM 207.

  Data 504C that is neither the fraction data 504LR nor the dummy data 504D is read from the SRAM 207 as follows. The read control unit 208 supplies a read address to the SRAM 207 via the signal line RD_ADDR_0_IBUS, the memory bus 261, and the signal line RD_ADDR_0_OBUS. Further, the read control unit 208 supplies a read enable signal to the SRAM 207 via the signal line REN_0_IBUS, the memory bus 261, and the signal line REN_0_OBUS. The SRAM 207 supplies data to the read control unit 208 via the signal line DOUT_0_OBUS, the memory bus 261, and the signal line DOUT_0_IBUS. In this way, data 504C that is neither the fraction data 504LR nor the dummy data 504D is read from the SRAM 207. Data 504C read from the SRAM 207 is transmitted via the memory bus 115.

  The fraction data 504LR is written in the SRAM 237 as follows. The dummy data 504D is also written in the SRAM 237 as follows, as in the case of the fraction data 504LR. The write control unit 204 supplies a write address to the SRAM 237 via the signal line WR_ADDR_0_IBUS, the memory bus 260, and the signal line WR_ADDR_3_OBUS. Further, the write control unit 204 supplies a write enable signal to the SRAM 237 via the signal line WEN_0_IBUS, the memory bus 260, and the signal line WEN_3_OBUS. Further, the write control unit 204 supplies data to the SRAM 237 via the signal line DIN_0_IBUS, the memory bus 260, and the signal line DIN_3_OBUS. Thus, the fraction data 504LR and the dummy data 504D are written into the SRAM 237.

  The fraction data 504LR is read from the SRAM 237 as follows. The dummy data 504D is also read from the SRAM 237 as follows, like the fraction data 504LR. The read control unit 208 supplies a read address to the SRAM 237 via the signal line RD_ADDR_0_IBUS, the memory bus 261, and the signal line RD_ADDR_3_OBUS. Further, the read control unit 208 supplies a read enable signal to the SRAM 237 via the signal line REN_0_IBUS, the memory bus 261, and the signal line REN_3_OBUS. The SRAM 237 supplies data to the read control unit 208 via the signal line DOUT_3_OBUS, the memory bus 261, and the signal line DOUT_0_IBUS. Thus, the fraction data 504LR and the dummy data 504D are read from the SRAM 237. The fraction data 504LR and the dummy data 504D read from the SRAM 237 are transmitted via the memory bus 115.

  The operation timing is the same as that in the first embodiment described above with reference to FIGS.

  As described above, the fraction data 504LR and the dummy data 504D may be temporarily stored in the SRAM 237 provided in the WRDMAC 232 different from the WRDMAC 202.

[Third Embodiment]
An image processing apparatus and an image processing method according to the third embodiment will be described with reference to FIG. The same components as those in the image processing apparatus according to the first or second embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 8 is a flowchart illustrating an example of the operation of the image processing apparatus 100 according to the present embodiment. The image processing apparatus 100 according to the present embodiment includes, for example, a WRDMAC 202 as shown in FIG.

  In step S801, transfer parameters are set in the WRDMAC 202. Examples of the transfer parameter include the data size in the horizontal direction of the divided block 501 and the number of divisions. Thereafter, the process proceeds to step S802.

  In step S802, it is determined whether the data size in the horizontal direction of the divided block 501 is less than a predetermined size. The predetermined size is, for example, 512 bytes, but is not limited thereto. If the data size in the horizontal direction of the divided block 501 is less than the predetermined size (YES in step S802), the process proceeds to step S804. If the data size in the horizontal direction of the divided block 501 is equal to or larger than the predetermined size (NO in step S802), the process proceeds to step S803.

  In step S803, it is determined whether or not the number of divisions in the horizontal direction of the divided block 501 is greater than or equal to a predetermined number. In other words, it is determined whether or not the size of the divided block 501 is less than a predetermined value. The predetermined number is, for example, 16, but is not limited thereto. If the number of divisions of the divided block 501 in the horizontal direction is equal to or greater than the predetermined number (YES in step S803), the process proceeds to step S804. If the number of divisions in the horizontal direction of the divided block 501 is a predetermined number (NO in step S803), the process proceeds to step S805.

In step S804, the data is written to the DRAM 107 while the data size is aligned in units of burst access in the DRAM 107. Specifically, the fraction data 504LR of each line 503 of the divided blocks 501 adjacent to each other are combined with each other. As described above in the first and second embodiments, the fraction data 504LR is coupled to each other so as to align with the burst access unit in the DRAM 107. The combined fraction data 504LR is written into the fraction data storage area 207c of the SRAM 207. The fraction data 504LR written in the fraction data storage area 207c of the SRAM 207 is read from the SRAM 207. The fraction data 504LR read from the SRAM 207 is written to the DRAM 107.
In step S805, data is written to the DRAM 107 without performing processing for aligning the data size in units of burst access in the DRAM 107.
Thus, the process shown in FIG. 8 is completed.

  As described above, when the horizontal data size of the divided block 501 is less than the predetermined size or when the horizontal division number of the divided block 501 is larger than the predetermined number, the data size is aligned with the burst access unit of the DRAM 107. It may be. In cases other than these cases, the process of aligning the data size in the burst access unit of the DRAM 107 may not be performed. In these cases, it is because the frequency that the data size is not aligned with the burst access unit in the DRAM 107 is low, and no significant command overhead occurs.

[Fourth Embodiment]
An image processing apparatus and an image processing method according to the fourth embodiment will be described with reference to FIGS. The same components as those of the image processing apparatus according to the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The image processing apparatus 100 according to the present embodiment attaches dummy data 504D to each fraction data 504R.

  The basic configuration of the image processing apparatus 100 according to the present embodiment is the same as the basic configuration of the image processing apparatus 100 according to the first embodiment described above with reference to FIG.

FIG. 9 is a diagram showing an example of the configuration of the data storage area of the SRAM 207 provided in the WRDMAC 202 of the image processing apparatus 100 according to the present embodiment.
As shown in FIG. 9, the SRAM 207 provided in the WRDMAC 202 of the image processing apparatus 100 according to the present embodiment includes a memory bank 207a and a memory bank 207b.

  FIG. 11 is a diagram illustrating a virtual address space corresponding to an image of one frame. As in the first embodiment, rectangular divided blocks 501a to 501l are defined by dividing one frame of image data into four parts in the horizontal direction and three parts in the vertical direction. Similar to the first embodiment, data transmission in units of divided blocks 501a to 501l is executed from the module 201 to the WRDMAC 202. Similarly to the first embodiment, data is transmitted from the WRDMAC 202 to the DRAM 107 in units of the divided blocks 501a to 501l. As in the first embodiment, the address at which the data of the upper left pixel of the image of one frame is written becomes the head address of the address area where the image data is written. As in the first embodiment, the address at which the head of the image data is written is, for example, address 0x1000 of the DRAM 107. Similar to the first embodiment, the first line to the last line of the image are sequentially written to consecutive addresses. As in the first embodiment, the pixel located at the head of the (n + 1) th line of the image has an address next to the address where the data of the pixel located at the tail of the nth line of the image is written. Data is written. As in the first embodiment, the address to which the data of the pixel located at the lower right corner of the image is written is the last address in the address area to which the image data is written.

  Similar to the first embodiment, the image data of the divided blocks 501a to 501d located on the first block line 502a is sequentially transmitted. Similarly to the first embodiment, after the transmission of the image data of the divided blocks 501a to 501d located in the first block line 502a is completed, the divided blocks 501e to 501h located in the second block line 502b are completed. Transmission of image data is performed sequentially. Similar to the first embodiment, after the transmission of the image data of the divided blocks 501e to 501h located in the second block line 502b is completed, the divided blocks 501i to 501l located in the third block line 502c are completed. Transmission of image data is performed sequentially. Similar to the first embodiment, in the DRAM 107, it is necessary that the first line to the last line of the image are written in continuous addresses.

  The data size in the horizontal direction of the divided blocks 501a, 501e, and 501i is, for example, 502 bytes. The data size in the horizontal direction of the divided blocks 501b, 501f, and 501j is, for example, 490 bytes. The data size in the horizontal direction of the divided blocks 501c, 501g, and 501k is, for example, 510 bytes. The data size in the horizontal direction of the divided blocks 501d, 501h, and 501l is, for example, 500 bytes. The number of lines in the vertical direction of the divided block 501 is 64, for example.

  Since transmission is performed with a transfer burst length corresponding to the size of a line included in the divided block 501, the following event may occur when processing described later is not performed. That is, as described above, the data size in the horizontal direction of the divided blocks 501a, 501e, and 501i is, for example, 502 bytes. On the other hand, the burst access unit in the DRAM 107 is, for example, 32 bytes. Therefore, for example, 22 bytes of fractional data write access occurs at the right end of the lines of the divided blocks 501a, 501e, and 501i. As described above, the data size in the horizontal direction of the divided blocks 501b, 501f, and 501j is, for example, 490 bytes. On the other hand, the burst access unit in the DRAM 107 is, for example, 32 bytes. For this reason, for example, a write access of 10-byte fraction data occurs at the right end of the lines of the divided blocks 501b, 501f, and 501j. Further, as described above, the data size in the horizontal direction of the divided blocks 501c, 501g, and 501k is, for example, 510 bytes. On the other hand, the burst access unit in the DRAM 107 is, for example, 32 bytes. For this reason, for example, 30 bytes of fractional data write access occurs at the right end of the lines of the divided blocks 501c, 501g, and 501k. Further, as described above, the data size in the horizontal direction of the divided blocks 501d, 501h, and 501l is, for example, 500 bytes. On the other hand, the burst access unit in the DRAM 107 is, for example, 32 bytes. For this reason, for example, 20 bytes of fractional data write access occurs at the right end of the lines of the divided blocks 501d, 501h, and 501l. As described above, such fraction data is not aligned with the burst access unit in the DRAM 107. As described above, when such fractional data that does not align with the burst access unit in the DRAM 107 occurs, the command overhead becomes larger than when data aligns with the burst access unit in the DRAM 107.

  The SRAM 207 has a capacity of, for example, 512 words, that is, 16384 bytes. The addresses from the address 0x000 to the address 0x07F in the SRAM 207 are assigned to BANK0, that is, the memory bank 207a. The addresses from the address 0x080 to the address 0x0FF of the SRAM 207 are assigned to BANK1, that is, the memory bank 207b.

  10A and 10B are timing charts showing the operation of the image processing apparatus 100 according to the present embodiment. 10A and 10B show the operation of the SRAM 207 when data is written to the DRAM 107. 10A and 10B show signals WR_ADDR_0, WEN_0, DIN_0, RD_ADDR_0, REN_0, and DOUT_0. FIG. 10A shows an operation from timing t1001 to timing t1006, and FIG. 10B shows an operation from timing t1005 to timing t1010.

  A period 1011 from timing t1001 to timing t1003 is a period in which the image data of the divided block 501a output from the module 201 is written in the SRAM 207. In the period 1011, the following processing is performed.

  First, data 504a1C other than the fraction data 504a1R located at the right end of the first line of the divided block 501a is written into the SRAM 207. The data 504a1C is written into, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the data 504a1C is written to the SRAM 207 is, for example, 0x000. The size of the data 504a1C is, for example, 480 bytes. Therefore, the data 504a1C is aligned in units of burst access in the DRAM 107.

  Next, fraction data 504a1R located at the right end of the first line of the divided block 501a and dummy data 504a1D are written into the SRAM 207. The fraction data 504a1R and the dummy data 504a1D are written to, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the fraction data 504a1R and the dummy data 504a1D are written to the SRAM 207 is, for example, address 0x00F. The size of the data 504a1R is, for example, 22 bytes. The size of the dummy data 504a1D is, for example, 10 bytes. These data 504a1R and 504a1D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504a2C other than the fraction data 504a2R located at the right end of the second line of the divided block 501a is written into the SRAM 207. The data 504a2C is written into, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504a2C is written to the SRAM 207 is, for example, 0x080. The size of the data 504a2C is, for example, 480 bytes. Therefore, the data 504a2C is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504a2R located at the right end of the second line of the divided block 501a and the dummy data 504a2D are written into the SRAM 207. The fraction data 504a2R and the dummy data 504a2D are written into, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when writing the fraction data 504a2R and the dummy data 504a2D into the SRAM 207 is, for example, address 0x08F. The size of the data 504a2R is, for example, 22 bytes. The size of the dummy data 504a2D is, for example, 10 bytes. These data 504a2R and 504a2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501a. As described above, the number of lines included in the divided block 501a is 64, for example. The data of the 64th line of the divided block 501a is processed as follows. That is, data 504a64C other than the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is written into the SRAM 207. The data 504a64C is written into the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504a64C is written to the SRAM 207 is, for example, 0x080. The size of the data 504a64C is, for example, 480 bytes. Therefore, the data 504a64C is aligned in burst access units in the DRAM 107. Thereafter, the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a and the dummy data 504a64D are written into the SRAM 207. The fraction data 504a64R and the dummy data 504a64D are written into the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when writing the fraction data 504a64R and the dummy data 504a64D into the SRAM 207 is, for example, address 0x08F. The size of the data 504a64R is, for example, 22 bytes. The size of the dummy data 504a64D is, for example, 10 bytes. These data 504a64R and 504a64D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  A period 1012 from timing t1002 to timing t1004 is a period in which the image data of the divided block 501a is read from the SRAM 207. A part of the period 1012 overlaps with a part of the period 1011 described above. In the period 1012, the following processing is performed.

  First, data 504a1C other than the fraction data 504a1R located at the right end of the data of the first line of the divided block 501a is read from the SRAM 207. The size of the data 504a1C is, for example, 480 bytes as described above. The data 504a1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504a1C from the SRAM 207 is, for example, 0x000. Data 504a1C read from the SRAM 207 is transmitted via the memory bus 151. As described above, the start address for writing image data to the DRAM 107, that is, the start address of the DRAM 107 is, for example, 0x1000. Therefore, the address calculation unit 203 sets the write start address when writing the data 504a1C to the DRAM 107 as the address 0x1000. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504a1C other than the fraction data 504a1R located at the right end of the data of the first line of the divided block 501a is written to the DRAM 107. The data 504a1C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504a1R located at the right end of the data of the first line of the divided block 501a and the dummy data 504a1D are read from the SRAM 207. The leading address when reading the fraction data 504a1R and the dummy data 504a1D from the SRAM 207 is, for example, address 0x00F. The fraction data 504a1R and the dummy data 504a1D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504a1R is, for example, 22 bytes. The size of the dummy data 504a1D is, for example, 10 bytes as described above. These data 504a1R and 504a1D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504a2C other than the fraction data 504a2R located at the right end of the data of the second line of the divided block 501a is read from the SRAM 207. The size of the data 504a2C is, for example, 480 bytes as described above. The data 504a2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when reading the data 504a2C from the SRAM 207 is, for example, address 0x080. Data 504a2C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504a2C by adding the offset value to the address 0x1000 that is the write start address of the data 504a1C. The offset value is, for example, 2048 bytes. The write start address thus obtained is, for example, address 0x1800. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504a2C other than the fraction data 504a2R located at the right end of the data of the second line of the divided block 501a is written to the DRAM 107. The data 504a2C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504a2R located at the right end of the data of the second line of the divided block 501a and the dummy data 504a2D are read from the SRAM 207. The leading address when reading the fraction data 504a2R and the dummy data 504a2D from the SRAM 207 is, for example, address 0x08F. The fraction data 504a2R and the dummy data 504a2D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504a2R is, for example, 22 bytes. The size of the dummy data 504a2D is, for example, 10 bytes as described above. These data 504a2R and 504a2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501a. As described above, the number of lines included in the divided block 501a is 64, for example. The data of the 64th line of the divided block 501a is processed as follows. That is, data 504a64C other than the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is read from the SRAM 207. Data 504a64C read from the SRAM 207 is transmitted via the memory bus 151. Thus, data 504a64C other than the fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a is written to the DRAM 107. The size of the data 504a64C is, for example, 480 bytes as described above. The data 504a64C for 480 bytes is aligned in units of burst access in the DRAM 107. The fraction data 504a64R located at the right end of the data of the 64th line of the divided block 501a and the dummy data 504a64D are read from the SRAM 207. The fraction data 504a64R and the dummy data 504a64D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504a64R is, for example, 22 bytes. The size of the dummy data 504a64D is, for example, 10 bytes as described above. These data 504a64R and 504a64D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  A period 1013 from timing t1003 to timing t1005 is a period in which the image data of the divided block 501b output from the module 201 is written in the SRAM 207. In the period 1013, the following processing is performed.

  First, data 504b1C other than the fraction data 504b1R located at the right end of the first line of the divided block 501b is written into the SRAM 207. The data 504b1C is written into, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the data 504b1C is written to the SRAM 207 is, for example, 0x000. The size of the data 504b1C is, for example, 480 bytes. Therefore, the data 504b1C is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504b1R located at the right end of the first line of the divided block 501b and the dummy data 504b1D are written into the SRAM 207. The fraction data 504b1R and the dummy data 504b1D are written into, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when writing the fraction data 504b1R and the dummy data 504b1D to the SRAM 207 is, for example, address 0x00F. The size of the data 504b1R is, for example, 10 bytes. The size of the dummy data 504b1D is, for example, 22 bytes. These data 504b1R and 504b1D whose total size is 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504b2C other than the fraction data 504b2R located at the right end of the second line of the divided block 501b is written into the SRAM 207. The data 504b2C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The start address when writing the data 504b2C to the SRAM 207 is, for example, address 0x080. The size of the data 504b2C is, for example, 480 bytes. Therefore, the data 504b2C is aligned in burst access units in the DRAM 107.

  Next, the fraction data 504b2R located at the right end of the second line of the divided block 501b and the dummy data 504b2D are written into the SRAM 207. The fraction data 504b2R and the dummy data 504b2D are written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the fraction data 504b2R and the dummy data 504b2D are written to the SRAM 207 is, for example, address 0x08F. The size of the data 504b2R is, for example, 10 bytes. The size of the dummy data 504b2D is, for example, 22 bytes. These data 504b2R and 504b2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501b. As described above, the number of lines included in the divided block 501b is 64, for example. The data of the 64th line of the divided block 501b is processed as follows. That is, data 504b64C other than the fraction data 504b64R located at the right end of the 64th line of the divided block 501b is written into the SRAM 207. The data 504b64C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when writing the data 504b64C to the SRAM 207 is, for example, address 0x080. The size of the data 504b64C is, for example, 480 bytes. Therefore, the data 504b64C is aligned in burst access units in the DRAM 107. Thereafter, the fraction data 504b64R located at the right end of the 64th line of the divided block 501b and the dummy data 504b64D are written into the SRAM 207. The fraction data 504b64R and the dummy data 504b64D are written in, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the fraction data 504b64R and the dummy data 504b64D are written to the SRAM 207 is, for example, address 0x08F. The size of the data 504b64R is, for example, 10 bytes. The size of the dummy data 504b64D is, for example, 22 bytes. These data 504b64R and 504b64D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  A period 1014 from timing t1004 to timing t1006 is a period in which the image data of the divided block 501b is read from the SRAM 207. A part of the period 1014 overlaps with a part of the period 1013 described above. In the period 1014, the following processing is performed.

  First, data 504b1C other than the fraction data 504b1R located at the right end of the data of the first line of the divided block 501b is read from the SRAM 207. The size of the data 504b1C is, for example, 480 bytes as described above. The data 504b1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504b1C from the SRAM 207 is, for example, 0x000. Data 504b1C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504b1C by adding the offset value to the address 0x1000 that is the write start address of the data 504a1C. The offset value is set so that the data of the first line of the divided block 501b is located immediately after the data of the first line of the divided block 501a. The write start address thus obtained is, for example, 0x1200. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504b1C other than the fraction data 504b1R located at the right end of the data of the first line of the divided block 501b is written into the DRAM 107. The data 504b1C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504b1R located at the right end of the data of the first line of the divided block 501b and the dummy data 504b1D are read from the SRAM 207. The fraction data 504b1R and the dummy data 504b1D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504b1R is, for example, 10 bytes. The size of the dummy data 504b1D is, for example, 22 bytes as described above. These data 504b1R and 504b1D whose total size is 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504b2C other than the fraction data 504b2R located at the right end of the data of the second line of the divided block 501b is read from the SRAM 207. The size of the data 504b2C is, for example, 480 bytes as described above. The data 504b2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The head address when reading the data 504b2C from the SRAM 207 is, for example, 0x080. Data 504b2C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504b2C by adding the offset value to the address 0x1200 that is the write start address of the data 504b1C. The offset value is, for example, 2048 bytes. The write start address thus obtained is, for example, address 0x1A00. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504b2C other than the fraction data 504b2R located at the right end of the data of the second line of the divided block 501b is written to the DRAM 107. The data 504b2C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504b2R located at the right end of the data of the second line of the divided block 501b and the dummy data 504b2D are read from the SRAM 207. The fraction data 504b2R and the dummy data 504b2D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504b2R is, for example, 10 bytes. The size of the dummy data 504b2D is, for example, 22 bytes as described above. These data 504b2R and 504b2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501b. As described above, the number of lines included in the divided block 501b is 64, for example. The data of the 64th line of the divided block 501b is processed as follows. That is, data 504b64C other than the fraction data 504b64R located at the right end of the data of the 64th line of the divided block 501b is read from the SRAM 207. Data 504b64C read from the SRAM 207 is transmitted via the memory bus 151. Thus, data 504b64C other than the fraction data 504b64R located at the right end of the data of the 64th line of the divided block 501b is written to the DRAM 107. The size of the data 504b64C is, for example, 480 bytes as described above. The data 504b64C for 480 bytes is aligned in units of burst access in the DRAM 107. The fraction data 504b64R located at the right end of the data of the 64th line of the divided block 501b and the dummy data 504b64D are read from the SRAM 207. The fraction data 504b64R and the dummy data 504b64D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504b64R is, for example, 10 bytes. As described above, the size of the dummy data 504b64D is, for example, 22 bytes. These data 504b64R and 504b64D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  A period 1015 from timing t1005 to timing t1007 is a period in which the image data of the divided block 501c output from the module 201 is written in the SRAM 207. In the period 1015, the following processing is performed.

  First, data 504c1C other than the fraction data 504c1R located at the right end of the first line of the divided block 501c is written into the SRAM 207. The data 504c1C is written to, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the data 504c1C is written to the SRAM 207 is, for example, 0x000. The size of the data 504c1C is, for example, 480 bytes. Therefore, the data 504c1C is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504c1R located at the right end of the first line of the divided block 501c and the dummy data 504c1D are written into the SRAM 207. The fraction data 504c1R and the dummy data 504c1D are written to, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when writing the fraction data 504c1R and the dummy data 504c1D to the SRAM 207 is, for example, address 0x00F. The size of the data 504c1R is, for example, 30 bytes. The size of the dummy data 504c1D is, for example, 2 bytes. These data 504c1R and 504c1D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504c2C other than the fraction data 504c2R located at the right end of the second line of the divided block 501c is written into the SRAM 207. The data 504c2C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504c2C is written to the SRAM 207 is, for example, 0x080. The size of the data 504c2C is, for example, 480 bytes. Therefore, the data 504c2C is aligned in units of burst access in the DRAM 107.

  Next, fraction data 504c2R located at the right end of the second line of the divided block 501c and dummy data 504c2D are written into the SRAM 207. The fraction data 504c2R and the dummy data 504c2D are written in, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the fraction data 504c2R and the dummy data 504c2D are written to the SRAM 207 is, for example, address 0x08F. The size of the data 504c2R is, for example, 30 bytes. The size of the dummy data 504c2D is, for example, 2 bytes. These data 504c2R and 504c2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501c. As described above, the number of lines included in the divided block 501c is 64, for example. The data of the 64th line of the divided block 501c is processed as follows. That is, data 504c64C other than the fraction data 504c64R located at the right end of the 64th line of the divided block 501c is written into the SRAM 207. The data 504c64C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504c64C is written to the SRAM 207 is, for example, 0x080. The size of the data 504c64C is, for example, 480 bytes. Therefore, the data 504c64C is aligned in units of burst access in the DRAM 107. Thereafter, the fraction data 504c64R located at the right end of the 64th line of the divided block 501c and the dummy data 504c64D are written into the SRAM 207. The fraction data 504c64R and the dummy data 504c64D are written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when writing the fraction data 504c64R and the dummy data 504c64D into the SRAM 207 is, for example, address 0x08F. The size of the data 504c64R is, for example, 30 bytes. The size of the dummy data 504c64D is, for example, 2 bytes. These data 504c64R and 504c64D having a total size of 32 bytes are aligned in a burst access unit in the DRAM 107.

  A period 1016 from timing t1006 to timing t1008 is a period in which the image data of the divided block 501c is read from the SRAM 207. A part of the period 1016 overlaps with a part of the period 1015 described above. In the period 1016, the following processing is performed.

  First, data 504c1C other than the fraction data 504c1R located at the right end of the data of the first line of the divided block 501c is read from the SRAM 207. The size of the data 504c1C is, for example, 480 bytes as described above. The data 504c1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504c1C from the SRAM 207 is, for example, 0x000. Data 504c1C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504c1C by adding the offset value to the address 0x1200 which is the write start address of the data 504b1C. The offset value is set so that the data of the first line of the divided block 501c is located immediately after the data of the first line of the divided block 501b. The write start address thus obtained is, for example, address 0x1400. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504c1C other than the fraction data 504c1R located at the right end of the data of the first line of the divided block 501c is written into the DRAM 107. The data 504c1C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504c1R located at the right end of the data of the first line of the divided block 501c and the dummy data 504c1D are read from the SRAM 207. The fraction data 504c1R and the dummy data 504c1D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504c1R is, for example, 30 bytes. The size of the dummy data 504c1D is, for example, 2 bytes as described above. These data 504c1R and 504c1D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504c2C other than the fraction data 504c2R located at the right end of the data of the second line of the divided block 501c is read from the SRAM 207. The size of the data 504c2C is, for example, 480 bytes as described above. The data 504c2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when reading the data 504c2C from the SRAM 207 is, for example, 0x080. Data 504c2C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates a write start address for the data 504c2C by adding an offset value to the address 0x1400 that is the write start address for the data 504c1C. The offset value is, for example, 2048 bytes. The write start address thus obtained is, for example, address 0x1C00. The write start address thus obtained is transmitted through the signal line REQ_0. In this way, data 504c2C other than the fraction data 504c2R located at the right end of the data of the second line of the divided block 501c is written into the DRAM 107. The data 504c2C for 480 bytes is aligned in units of burst access in the DRAM 107.

  Next, the fraction data 504c2R located at the right end of the data of the second line of the divided block 501c and the dummy data 504c2D are read from the SRAM 207. The fraction data 504c2R and the dummy data 504c2D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504c2R is, for example, 30 bytes. The size of the dummy data 504c2D is, for example, 2 bytes as described above. These data 504c2R and 504c2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501c. As described above, the number of lines included in the divided block 501c is 64, for example. The data of the 64th line of the divided block 501c is processed as follows. That is, data 504c64C other than the fraction data 504c64R located at the right end of the data of the 64th line of the divided block 501c is read from the SRAM 207. Data 504c64C read from the SRAM 207 is transmitted via the memory bus 151. Thus, data 504c64C other than the fraction data 504c64R located at the right end of the data of the 64th line of the divided block 501c is written into the DRAM 107. The size of the data 504c64C is, for example, 480 bytes as described above. The data 504c64C for 480 bytes is aligned in a burst access unit in the DRAM 107. The fraction data 504c64R located at the right end of the data of the 64th line in the divided block 501c and the dummy data 504c64D are read from the SRAM 207. The fraction data 504c64R and the dummy data 504c64D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504c64R is, for example, 30 bytes. As described above, the size of the dummy data 504c64D is, for example, 2 bytes. These data 504c64R and 504c64D having a total size of 32 bytes are aligned in a burst access unit in the DRAM 107.

  A period 1017 from timing t1007 to timing t1009 is a period in which the image data of the divided block 501d output from the module 201 is written in the SRAM 207. In the period 1017, the following processing is performed.

  First, data 504d1C other than the fraction data 504d1R located at the right end of the first line of the divided block 501d is written into the SRAM 207. The data 504d1C is written to, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The start address when writing the data 504d1C to the SRAM 207 is, for example, 0x000. The size of the data 504d1C is, for example, 480 bytes. Therefore, the data 504d1C is aligned in burst access units in the DRAM 107.

  Next, the fraction data 504d1R located at the right end of the first line of the divided block 501c and the dummy data 504d1D are written into the SRAM 207. The fraction data 504d1R and the dummy data 504d1D are written in, for example, the memory bank 207a of the SRAM 207, that is, BANK0. The leading address when the fraction data 504d1R and the dummy data 504d1D are written to the SRAM 207 is, for example, address 0x00F. The size of the data 504d1R is, for example, 20 bytes. The size of the dummy data 504d1D is, for example, 12 bytes. These data 504d1R and 504d1D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504d2C other than the fraction data 504d2R located at the right end of the second line of the divided block 501d is written into the SRAM 207. The data 504d2C is written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504d2C is written to the SRAM 207 is, for example, 0x080. The size of the data 504d2C is, for example, 480 bytes. Therefore, the data 504d2C is aligned with the burst access unit in the DRAM 107.

  Next, fraction data 504d2R located at the right end of the second line of the divided block 501d and dummy data 504d2D are written into the SRAM 207. The fraction data 504d2R and the dummy data 504d2D are written in, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when writing the fraction data 504c2R and the dummy data 504d2D into the SRAM 207 is, for example, address 0x08F. The size of the data 504d2R is, for example, 20 bytes. The size of the dummy data 504d2D is, for example, 12 bytes. These data 504d2R and 504d2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501d. As described above, the number of lines included in the divided block 501d is 64, for example. The data of the 64th line of the divided block 501d is processed as follows. That is, data 504d64C other than the fraction data 504d64R located at the right end of the 64th line of the divided block 501d is written into the SRAM 207. The data 504d64C is written in, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the data 504d64C is written to the SRAM 207 is, for example, 0x080. The size of the data 504d64C is, for example, 480 bytes. Therefore, the data 504d64C is aligned in burst access units in the DRAM 107. Thereafter, the fraction data 504d64R located at the right end of the 64th line of the divided block 501d and the dummy data 504d64D are written into the SRAM 207. The fraction data 504d64R and the dummy data 504d64D are written to, for example, the memory bank 207b of the SRAM 207, that is, BANK1. The leading address when the fraction data 504d64R and the dummy data 504d64D are written to the SRAM 207 is, for example, address 0x08F. The size of the data 504d64R is, for example, 20 bytes. The size of the dummy data 504d64D is, for example, 12 bytes. These data 504d64R and 504d64D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  A period 1018 from timing t1008 to timing t1010 is a period in which the image data of the divided block 501d is read from the SRAM 207. A part of the period 1018 overlaps with a part of the period 1017 described above. In the period 1018, the following processing is performed.

  First, data 504d1C other than the fraction data 504d1R located at the right end of the data of the first line of the divided block 501d is read from the SRAM 207. The size of the data 504d1C is, for example, 480 bytes as described above. The data 504d1C is read from the memory bank 207a of the SRAM 207, that is, BANK0. The head address when reading the data 504d1C from the SRAM 207 is, for example, 0x000. Data 504 d 1 C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates the write start address of the data 504d1C by adding the offset value to the address 0x1400 that is the write start address of the data 504c1C. The offset value is set so that the data of the first line of the divided block 501d is located immediately after the data of the first line of the divided block 501c. The write start address thus obtained is, for example, address 0x1600. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504d1C other than the fraction data 504d1R located at the right end of the data of the first line of the divided block 501d is written to the DRAM 107. The data 504d1C for 480 bytes is aligned in burst access units in the DRAM 107.

  Next, fraction data 504d1R and dummy data 504d1D located at the right end of the data of the first line of the divided block 501d and the dummy data 504d1D are read from the SRAM 207. The fraction data 504d1R and the dummy data 504d1D read from the SRAM 207 are transmitted via the memory bus 151. The size of the data 504d1R is, for example, 20 bytes as described above. The size of the dummy data 504d1D is, for example, 12 bytes as described above. These data 504d1R and 504d1D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

  Next, data 504d2C other than the fraction data 504d2R located at the right end of the data of the second line of the divided block 501d is read from the SRAM 207. The size of the data 504d2C is, for example, 480 bytes as described above. The data 504d2C is read from the memory bank 207b of the SRAM 207, that is, BANK1. The head address when reading the data 504d2C from the SRAM 207 is, for example, address 0x080. Data 504d2C read from the SRAM 207 is transmitted via the memory bus 151. The address calculation unit 203 generates a write start address for the data 504d2C by adding an offset value to the address 0x1600, which is the write start address for the data 504d1C. The offset value is, for example, 2048 bytes. The write start address thus obtained is, for example, address 0x1E00. The write start address thus obtained is transmitted through the signal line REQ_0. Thus, data 504d2C other than the fraction data 504d2R located at the right end of the data of the second line of the divided block 501d is written to the DRAM 107. The data 504d2C for 480 bytes is aligned in burst access units in the DRAM 107.

  Next, the fraction data 504d2R located at the right end of the data of the second line of the divided block 501d and the dummy data 504d2D are read from the SRAM 207. The fraction data 504d2R and the dummy data 504d2D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504d2R is, for example, 30 bytes. The size of the dummy data 504d2D is, for example, 2 bytes as described above. These data 504d2R and 504d2D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.

Thereafter, the same processing as described above is sequentially performed on the third and subsequent lines of the divided block 501d. As described above, the number of lines included in the divided block 501d is 64, for example. The data of the 64th line of the divided block 501d is processed as follows. That is, data 504d64C other than the fraction data 504d64R located at the right end of the data of the 64th line of the divided block 501d is read from the SRAM 207. Data 504d64C read from the SRAM 207 is transmitted via the memory bus 151. Thus, data 504d64C other than the fraction data 504d64R located at the right end of the data of the 64th line of the divided block 501d is written to the DRAM 107. The size of the data 504d64C is, for example, 480 bytes as described above. The data 504d64C for 480 bytes is aligned in units of burst access in the DRAM 107. The fraction data 504d64R located at the right end of the data of the 64th line of the divided block 501d and the dummy data 504d64D are read from the SRAM 207. The fraction data 504d64R and the dummy data 504d64D read from the SRAM 207 are transmitted via the memory bus 151. As described above, the size of the data 504d64R is, for example, 20 bytes. As described above, the size of the dummy data 504d64D is, for example, 12 bytes. These data 504d64R and 504d64D having a total size of 32 bytes are aligned in burst access units in the DRAM 107.
Thereafter, the processing for the divided blocks 501e to 501l is performed in the same manner as described above.

  As described above, according to the present embodiment, the fraction data 504LR is added to the data of each line 503 so as to align with the burst access unit in the DRAM 107. For this reason, also in this embodiment, command overhead can be reduced and a decrease in writing speed can be suppressed.

[Fifth Embodiment]
An image processing apparatus and an image processing method according to the fifth embodiment will be described with reference to FIGS. The same components as those of the image processing apparatus according to the first to fourth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The basic configuration of the image processing apparatus 100 according to the present embodiment is the same as the basic configuration of the image processing apparatus 100 according to the first embodiment described above with reference to FIG.

  FIG. 12 is a block diagram showing the RDDMAC provided in the data transfer unit 105 of the image processing apparatus 100 according to the present embodiment. FIG. 12 shows a module 1201 provided in the image processing unit 104, an RDDMAC 1202 provided in the data transfer unit 105, and a memory bus 115.

  The module D (MODULE D), that is, the module 1201 performs predetermined image processing. The module 1201 and the RDDMAC 1202 are connected by signal lines DATA_A, VALID_A, and STOP_A. Data read from the DRAM 107 by the RDDMAC 1202 is supplied to the module 1201 through the signal line DATA_A. Only in the valid data output period, the signal VALID_A supplied from the RDDMAC 1202 to the module 1201 becomes High level. When the module 1201 enters the BUSY state due to some cause and the module 1201 cannot accept data, the STOP_A signal supplied from the module 1201 to the RDDMAC 1202 becomes High level. When the STOP_A signal becomes high level, data transmission from the RDDMAC 1202 to the module 1201 is stopped.

  The RDDMAC (RDDMAC_0) 1202 includes an address calculation unit 1203, a read control unit 1204, an SRAM 1207, a write control unit 1208, and a bus I / F unit 1209.

  The address calculation unit 1203 calculates an address value when data is read from the DRAM 107. The address calculation unit 1203 manages and controls the start address when reading image data from the DRAM 107, that is, the start address. The address calculation unit 1203 can increment the address. The address calculation unit 1203 manages and controls the data transfer length and the like. In the control of the data transfer length, the transfer burst length is set so as to correspond to the number of words that can be continuously accessed by one addressing. Here, a case where one word is 32 bytes, that is, 256 bits (bits) will be described as an example, but the present invention is not limited to this. Here, the transfer burst length can be set to 32, 64, or 128, for example. Note that the transfer burst length is not limited to these. The address calculation unit 203 can also update the address value by adding the offset value.

  The bus I / F unit 1209 is an interface for exchanging signals with each functional block via the memory bus 115. The bus I / F unit 1209 and the address calculation unit 1203 are connected via a signal line MEM_ADDR_0. A read start address, which is an address for starting reading from the DRAM 107, is supplied from the address calculation unit 1203 to the bus I / F unit 1209 via the signal line MEM_ADDR_0. Also, information indicating the transfer burst length is supplied from the address calculation unit 1203 to the bus I / F unit 1209 via the signal line MEM_ADDR_0.

  The write control unit 1208 performs control for writing data received from the DRAM 107 to the SRAM 1207. The SRAM 1207 includes a memory bank 1207a and a memory bank 1207b. For example, when data is being written to the memory bank 1207a, ie, BANK0, it is possible to read data from the memory bank 1207b, ie, BANK1. When data is being read from the memory bank 1207a, that is, BANK0, data can be written to the memory bank 1207b, that is, BANK1.

  The write controller 1208 and the SRAM 1207 are connected by signal lines WR_ADDR_0, WEN_0, and DIN_0. The write control unit 1208 supplies a write address to the SRAM 1207 via the signal line WR_ADDR_0. The write control unit 1208 supplies data to the SRAM 1207 via the signal line DIN_0. The write control unit 1208 supplies a write enable signal to the SRAM 1207 via the signal line WEN_0. When the write enable signal WEN_0 is at a high level, data supplied from the write control unit 1208 is written into the SRAM 1207.

  The read control unit 1204 reads data from the SRAM 1207 and supplies the read data to the module 1201. The read control unit 1204 and the SRAM 1207 are connected by signal lines RD_ADDR_0, REN_0, and DOUT_0. The read control unit 1204 supplies a read address to the SRAM 1207 via the signal line RD_ADDR_0. The read control unit 1204 reads data from the SRAM 1207 via the signal line DOUT_0. The read control unit 1204 supplies a read enable signal to the SRAM 1207 via the signal line REN_0. When the read enable signal REN_0 is at a high level, the data output from the SRAM 1207 is read by the read control unit 1204.

  Data is read from the DRAM 107 as follows. That is, the address calculation unit 1203 supplies a read start address, which is an address when starting reading to the DRAM 107, and information indicating the transfer burst length to the bus I / F unit 1209 via the signal line MEM_ADDR_0. . The bus I / F unit 1209 transmits a request signal REQ_0, which is a signal for requesting data transfer, via the memory bus 115. The bus I / F unit 1209 transmits the read start address and information indicating the transfer burst length via the memory bus 115. When the DRAM 107 is ready to be read, a high-level permission signal ACK_0 indicating that reading is permitted is supplied to the bus I / F unit 1209 via the memory bus 115. Data is transmitted from the DRAM 107 to the bus I / F unit 1209 via the memory bus 115 and the signal line RDATA0. The write control unit 1208 writes the data supplied from the DRAM 107 to the SRAM 1207. The read control unit 1204 reads data from the SRAM 1207. The read control unit 1204 supplies the data read from the SRAM 1207 to the module 1201 via the signal line DATA_A. Data read from the SRAM 1207 by the read control unit 1204 is appended with dummy data 504D. The read control unit 1204 deletes the dummy data 504D attached to the data read from the SRAM 1207. The read control unit 1204 supplies data obtained by removing the dummy data 504D from the data read from the SRAM 1207 to the module 1201. In parallel with the reading of data from the memory bank 1207a of the SRAM 1207, data is written to the memory bank 1207b of the SRAM 1207. Data (image data) read from the DRAM 107 is supplied to the module 1201 by alternately and continuously writing to and reading from the memory bank 1207a and the memory bank 1207b.

  FIG. 13 is a diagram conceptually showing block division when data is written to the DRAM 107 and block division when data written to the DRAM 107 is read. FIG. 13 shows a virtual address space corresponding to an image of one frame. As in the case of the fourth embodiment described above with reference to FIG. 11, rectangular divided blocks 501a to 501l are defined by dividing image data of one frame into four in the horizontal direction and three in the vertical direction. . Also, rectangular divided blocks 1301a to 1301o are determined by dividing a part of one frame of image data into 5 parts in the horizontal direction and 3 parts in the vertical direction. The divided blocks 1301a to 1301o are shown using thick solid lines. In this specification, reference numerals 1301a to 1301o are used when describing individual divided blocks, and reference numeral 1301 is used when general divided blocks are described. When data is written to the DRAM 107, data transmission is performed in units of divided blocks 501a to 501l. When data is read from the DRAM 107, for example, data transmission is executed in units of divided blocks 1301a to 1301o. On the right side of each divided block 501, there is dummy data 504 D added so as to align with the burst access unit in the DRAM 107.

FIG. 14 is a flowchart showing the operation of the image processing apparatus 100 according to the present embodiment.
In step S1401, transfer parameters are set in the RDDMAC 1202. The transfer parameters include the data size in the horizontal direction of the divided block 1301, the number of divisions, and the like. Then, the process proceeds to step S1402.

  In step S1402, the data of the first line of the divided block 1301 is read. The data size when reading the data of the first line of the divided block 1301 is the maximum burst length. When reading the first line of the divided block 1301, the size of the dummy data included in each line of the divided block 1301 is unknown. For this reason, when reading is performed on the first line of the divided block 1301, reading with the maximum burst length is performed. Since reading is performed with the maximum burst length, extra data can also be read. Then, the process proceeds to step S1403.

  In step S1403, it is determined whether or not the size of the data of the read data excluding the dummy data has reached the size of the divided block 1301 in the horizontal direction. If the size of the data other than the dummy data in the read data has reached the horizontal size of the divided block 1301 (YES in step S1403), the process proceeds to step S1404. When the data size of the read data excluding the dummy data does not reach the horizontal size of the divided block 1301 (NO in step S1403), step S1402 is repeated.

  In step S1404, the size of the dummy data included in the read data is determined. The total size of the first line of the divided block 1301 in the horizontal direction and the size of the dummy data attached to the line is the read size when the second and subsequent lines of the divided block 1301 are read. Set as As a result, when reading is performed on the second and subsequent lines, unnecessary data is not read, and efficient reading can be performed. Then, the process proceeds to step S1405.

  In step S1405, data of the second and subsequent lines of the divided block 1301 is read. The data size when reading the data of the second and subsequent lines of the divided block 1301 is the maximum burst length. Then, the process proceeds to step S1406.

  In step S1406, it is determined whether or not the total size of the read data reaches the read size set in step S1404 by reading the data only once again. If the total size of the read data does not reach the read size set in step S1404 (NO in step S1406) simply by reading data once again, the process returns to step S1405. If the total size of the read data reaches the read size set in step S1404 (YES in step S1406) by performing the data read only once again, the process proceeds to step S1407.

  In step S1407, data is read. At this time, fraction data can also be read. Then, the process proceeds to step S1408.

In step S1408, it is determined whether reading of all lines included in the divided block 1301 has been completed. If reading of all the lines included in the divided block 1301 has not been completed (NO in step S1408), the process proceeds to step S1410.
In step S1410, the line to be read is changed to the next line. Thereafter, the process returns to step S1405.

  If reading of all the lines included in divided block 1301 has been completed (YES in step S1408), the process proceeds to step S1409.

In step S1409, it is determined whether reading from all the divided blocks 1301 has been completed. If reading from all the divided blocks 1301 has not been completed (NO in step S1409), the process proceeds to step S1411.
In step S1411, the divided block 1301 to be read is changed to the next divided block 1301. Thereafter, the process returns to step S1402.

  When reading from all the divided blocks 1301 is completed (YES in step S1409), the reading process shown in FIG. 14 is completed.

  Thus, according to the present embodiment, the read size is set based on the data read from the first line of the divided block 1301. For this reason, when data is read from the second and subsequent lines of the divided block 1302, extra reading is not performed. For this reason, according to the present embodiment, data can be read efficiently.

[Sixth Embodiment]
An image processing apparatus and an image processing method according to the sixth embodiment will be described with reference to FIG. The same components as those of the image processing apparatus according to the first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The basic configuration of the image processing apparatus 100 according to the present embodiment is the same as the basic configuration of the image processing apparatus 100 according to the first embodiment described above with reference to FIG.

  The data transfer unit 105 provided in the image processing apparatus 100 according to the present embodiment includes the WRDMAC 202 described above with reference to FIG.

  In addition, the memory control unit 106 provided in the image processing apparatus 100 according to the present embodiment has a band detection function capable of measuring the band (bandwidth usage rate) of the memory bus 115. Based on the number of data transfer requests, which is the number of data transfer requests issued from the data transfer unit 105, and the requested data transfer length, which is the data transfer length requested by the data transfer unit 105, the memory control unit 106 Measure the bandwidth. The memory control unit 106 notifies the CPU 112 of the measurement result of the bandwidth of the memory bus 115.

FIG. 15 is a flowchart showing the operation of the image processing apparatus according to the present embodiment.
In step S1501, transfer parameters are set in the WRDMAC 202. The transfer parameters include the data size in the horizontal direction of the divided block 501, the data size in the vertical direction of the divided block 501, the number of divisions, and the like. Then, the process proceeds to step S1502.

  In step S1502, it is determined whether the capacity of the DRAM 107 has a margin. Specifically, the work area required when dummy data is added is calculated based on the transfer parameter set in step S1501. Then, it is determined whether or not an area required when dummy data is added exists in the DRAM 107. If it is determined that the capacity of DRAM 107 has a margin equal to or greater than the predetermined value (YES in step S1502), the process proceeds to step S1503. On the other hand, if it is determined that the capacity of DRAM 107 does not have a margin greater than the predetermined value (NO in step S1502), the process proceeds to step S1505.

  In step S1503, it is determined whether there is a margin in the bandwidth of the memory bus 115. Whether or not there is a margin in the bandwidth of the memory bus 115 can be determined using a bandwidth detection function provided in the memory control unit 106. The memory control unit 106 measures the bandwidth usage rate. If the bandwidth usage rate is greater than or equal to a predetermined value, it is determined that there is no room in the bandwidth of the memory bus 115. If there is no room in the bandwidth of memory bus 115 (NO in step S1503), the process proceeds to step S1504. The predetermined value may be 60%, for example, but is not limited thereto. If the bandwidth usage rate is less than the predetermined value, it is determined that there is a margin in the bandwidth of the memory bus 115. If there is a margin in the bandwidth of memory bus 115 (YES in step S1503), the process proceeds to step S1505.

  In step S1504, as described above with reference to FIG. 11, the data to which the dummy data 504D is added is written into the DRAM 107. In this case, the capacity of the DRAM 107 needs a margin, but the command overhead can be reduced.

  In step S1505, data is written to the DRAM 107 without adding dummy data 504D. In this case, the command overhead is increased, but the capacity of the DRAM 107 does not require a large margin.

  As described above, whether to add dummy data may be switched depending on whether or not there is a capacity margin in the DRAM 107 and whether or not there is a band margin in the memory bus 115.

[Modified Embodiment]
As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a recording medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

115 ... Memory bus 201 ... Module 202 ... WRDMAC

Claims (15)

Processing means for sequentially outputting each of a plurality of blocks constituting the image;
A memory accessed in a predetermined access unit;
Obtained by combining the second data not corresponding to the first block with the first data corresponding to a part of the first block of the plurality of blocks, and aligning to the access unit An image processing apparatus comprising: first writing means for writing combined data into the memory. Both the size of the first data and the size of the second data are smaller than the size of the access unit,
The image processing apparatus according to claim 1, wherein the size of the combined data is a size of the access unit.   The image processing apparatus according to claim 1, wherein the second data is included in a second block adjacent to the first block. The first block is a first line included in a first divided region among a plurality of divided regions defined by dividing the image into a plurality of regions;
The image processing apparatus according to claim 3, wherein the second block is a second line included in a second divided region adjacent to the first divided region.   The image processing apparatus according to claim 1, wherein the second data is dummy data.   The image processing apparatus according to claim 5, wherein the dummy data is data that can be distinguished from other data. It further has a reading means for reading the image written in the memory,
The image processing apparatus according to claim 5, wherein the reading unit removes the dummy data from the combined data read from the memory.   8. The image processing apparatus according to claim 5, wherein the second data is combined with the first data when the capacity of the memory has a margin equal to or greater than a predetermined value. 9. .   9. The second data is combined with the first data when a bandwidth usage rate of a bus line used when writing the image to the memory is a predetermined value or more. The image processing apparatus according to any one of the above. A second writing means different from the first writing means;
The image processing apparatus according to claim 1, wherein the second data is combined with the first data by the second writing unit.   The image according to any one of claims 1 to 10, wherein when the size of the first block is less than a predetermined value, the second data is combined with the first data. Processing equipment.   The image processing apparatus according to claim 1, wherein the second data is combined with the first data when the number of divisions of the image is equal to or greater than a predetermined value. .   The image processing apparatus according to claim 1, wherein the memory conforms to the LPDDR4 standard. Sequentially outputting each of a plurality of blocks constituting the image;
Obtained by combining the second data not corresponding to the first block with the first data corresponding to a part of the first block of the plurality of blocks, and aligned to the memory access unit Generating combined data to be
Writing the combined data into the memory. On the computer,
Sequentially outputting each of a plurality of blocks constituting the image;
Obtained by combining the second data not corresponding to the first block with the first data corresponding to a part of the first block of the plurality of blocks, and aligned to the memory access unit Generating combined data to be
A program for executing the step of writing the combined data in the memory.

Images