JP2019176606A - Switching power supply device - Google Patents

Abstract

To provide a switching power supply device that can easily add multi-phase and current balancing functions, without changing a basic control circuit of a control circuit.SOLUTION: A switching power supply device includes: a main circuit in which a plurality of power conversion portions (converter portion CH) having switching elements (switching elements Q) are connected to each other in parallel, a control circuit 2 that outputs a reference pulse signal based on output of the entire main circuit; an entire current detection circuit CTthat detects the output current of the entire main circuit as entire current; a plurality of individual current detection circuits CTthat are provided corresponding to the plurality of power conversion portions and detect the output currents for each of the plurality of power conversion portions as individual currents; and a pulse corrector 3 that respectively generates individual pulse signals for each of the plurality of power conversion portions based on the entire current, the individual current, and the reference pulse signal, and respectively outputs the individual pulse signals for each of the plurality of power conversion portions to the plurality of power conversion portions as drive signals for the switching elements.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a switching power supply device that converts an input voltage into an output voltage using a plurality of converter units connected in parallel.

  In recent years, there have been known multi-phase type switching power supply devices that drive each operation phase by shifting the number of phases in order to realize a large current and low ripple as the output load increases. Yes. In such a switching power supply device, it is necessary to operate the current supplied to the load while equally sharing the operation phase. Therefore, by detecting the current deviation of each operation phase and adding the correction signal that makes this deviation zero to the flow rate command value, the operation phase is equalized without increasing the size and complexity of the device. Has been proposed (see, for example, Patent Document 1).

JP 09-215322 A

  However, since the prior art performs multiphase processing based on the value obtained by adding the current correction value to the conduction ratio command value, the control circuit itself must be modified, and a microcomputer or a dedicated analog control IC is installed. The switching power supply used has a problem that it is difficult to apply. For example, when a microcomputer is used, the current control calculation for each phase needs to be performed inside the microcomputer, so the existing control program must be significantly changed. In addition, it is necessary to use a plurality of PWM counters inside the microcomputer when performing multiphase, but the number of counters is limited. Therefore, in order to increase the number of phases, a highly functional microcomputer is required, leading to an increase in cost. When a dedicated analog control IC is used, application circuits are often determined, and it is difficult to incorporate a current correction circuit or phase shift conversion circuit for calculating current correction for each phase. was there.

  An object of the present invention is to solve the above-mentioned problems of the prior art and provide a switching power supply device that can easily add multi-phase and current balancing functions without changing the basic control circuit portion of the control circuit. It is in.

  A switching power supply device of the present invention includes a main circuit in which a plurality of power conversion units having switching elements are connected in parallel to each other, a control circuit that outputs a reference pulse signal based on the output of the entire main circuit, and the entire main circuit And a plurality of individual currents that are provided corresponding to the plurality of power conversion units and that detect the output currents of the plurality of power conversion units as individual currents. The individual pulse signal for each of the plurality of power conversion units is generated based on the detection circuit, the entire current, the individual current, and the reference pulse signal, and the individual pulse signal for each of the plurality of power conversion units And a pulse compensator that outputs the signal as a drive signal for the switching element to each of the plurality of power converters.

  According to the present invention, since the current correction and the multi-phase can be performed by the pulse corrector based on the gate pulse signal output from the control circuit, the control circuit has a multi-phase (interleave) function. However, it is possible to easily provide an interleave (multiphase) function only by adding a pulse corrector.

It is a circuit block diagram which shows the circuit structure of 1st Embodiment of the switching power supply device which concerns on this invention. It is a wave form diagram which shows the example of an operation waveform of the pulse correction device shown in FIG. It is a wave form diagram which shows the other example of operation waveform of the pulse correction device shown in FIG. It is a circuit block diagram which shows the circuit structure of 2nd Embodiment of the switching power supply device which concerns on this invention. It is a circuit block diagram which shows the circuit structure of 3rd Embodiment of the switching power supply device which concerns on this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that in the following embodiments, the same reference numerals are given to configurations showing similar functions, and description thereof will be omitted as appropriate.

(First embodiment)
The switching power supply device 1 according to the first embodiment is a multi-phase DC / DC converter. Switching power supply device 1, with reference to FIG. 1, a control circuit 2, the pulse corrector 3, a total current detecting circuit CT _0, and N of the converter unit CH ₁ to CH _N which is the main circuit .

The switching power supply device 1 has a power supply Vin connected to the input side and a load L connected to the output side. Then, between the power source Vin and the load L, N converter units CH _{1 to} CH _N are driven in parallel with each other as first to N-th operation phases.

The N converter units CH _{1 to} CH _N are power conversion units having switching elements that are on / off controlled by pulse signals. Then, N pieces of the converter unit _CH 1 to CH _N have respective same configurations. Therefore, it is assumed that n is an integer from 1 to N, and the converter unit CH _n will be described in detail. Converter CH _n is a reactor _{S n,} includes a diode _{D n,} a switching element _{Q n,} and the capacitor _{C n,} and a separate current detector circuit CT _n, constitute a step-up chopper circuit of the non-insulated. In this embodiment, the converter unit has an example of the step-up chopper circuit as CH _n, PWM control converter other than the step-up chopper circuit (step-down chopper circuit, buck chopper circuit and the like), an insulating-type DC / A DC converter may be used.

A series circuit is formed by the reactor S _n and the diode D _n, and one end of the reactor S _n in this series circuit is connected to the power source Vin and the cathode of the diode D _n is connected to the load L. The capacitor C _n is connected in parallel with the load L on the output side between the connection point between the cathode of the diode D _n and the load L and the ground terminal.

In this embodiment, the switching element _Q n is composed of MOS-FET. The switching element Q _n has a drain connected to a connection point between the reactor S _n and the diode D _n, and a source connected to the ground terminal. Thus, the switching operation of the switching element Q _n is controlled by a drive signal applied to the gate, the voltage of the power supply Vin is supplied to be boosted load L.

The individual current detection circuit CT _n detects a current flowing through the reactor S _n, that is, an output current of the converter unit CH _n (for example, an average value in the period Ts of the gate pulse signal). Individual current detection circuit CT _n is composed of, for example, a current transformer or sense resistor.

The total current detection circuit CT ₀ detects an input current (for example, an average value in the period Ts of the gate pulse signal) input from the power source Vin to the entire main circuit (converter units CH _{1 to} CH _N ). Input current detected by the entire current detecting circuit CT ₀ is a main circuit (converter _CH 1 to CH _N) overall output current which is the sum of output current flowing through the converter unit _CH 1 to CH _N respectively. Overall current detecting circuit CT ₀ is composed of, for example, a current transformer or sense resistor.

The control circuit 2 is a circuit for generating a gate pulse signal for turning on and off the switching element Q _n of the converter unit CH _n. The control circuit 2 is a gate pulse signal whose duty ratio (pulse width) is controlled so that the outputs (input current, output current, output voltage) of the entire main circuit (converter units CH _{1 to} CH _N ) become target values. Is output to the pulse corrector 3.

Based on the gate pulse signal input from the control circuit 2, the pulse corrector 3 generates drive signals for turning on / off the switching elements Q _{1 to} Q _N of the _N converter units CH _{1 to} CH _N. To do. That is, the control circuit 2 only needs to have a function of controlling a single-phase converter, and does not need to support multi-phase.

The pulse corrector 3 includes a field programmable gate array (FPGA), and functions as a divider 4 and drive signal generators 5 _{1 to} 5 _N.

Divider 4 by dividing the input current detected by the entire current detector CT ₀ at a number operational phase N to calculate the average current, respectively the calculated average current to the drive signal generating unit 5 ₁ to 5 _n Output.

The drive signal generators 5 _{1 to} 5 _N have the same configuration. Therefore, it is assumed that n is an integer from 1 to N, and the drive signal generation unit 5 _n will be described in detail. The drive signal generator 5 _n includes a current deviation calculator 6 _n , a compensator 7 _n , a duty adder 8 _n, and a phase shifter 9 _n .

The current deviation calculator 6 _n is a subtractor that calculates the difference between the average current input from the divider 4 and the output current of the converter unit CH _n detected by the individual current detection circuit CT _n as a current deviation.

The compensator 7 _n determines a correction duty value ΔD _n that compensates for the current deviation calculated by the current deviation calculator 6 _n . As the compensator 7 _n, proportional controller (P controller), proportional integral controller (PI controller), proportional-integral-derivative controller (PID controller) can be used.

The duty adder 8 _n adds D + ΔD _n obtained by adding the correction duty value ΔD _n determined by the compensator 7 _n to the duty value (pulse width) D of the gate pulse signal input from the control circuit 2 as the gate pulse width. A driving signal is generated. Thus, the direction in which the output current of the average current converter CH _n approaches inputted from the divider 4 will be generating a drive signal obtained by correcting the duty value of the gate pulse signal.

If the period of the gate pulse signal output from the control circuit 2 is Ts, the phase shifter 9 _n delays the drive signal generated by the duty adder 8 _n by Ts × (n−1) / N and Output to the unit CH _n . As a result, the drive signals of each operation phase are output at phase angles that are equally shifted by 360 ° / N.

Next, the current correction and multiphase method in the pulse corrector 3 will be described in detail with reference to FIG.
In the pulse corrector 3, the duty adder 8 _n of the drive signal generator 5 _n calculates the time (pulse width) from the rising edge to the falling edge of the gate pulse signal input from the control circuit 2 at time t ₀ as the duty value Dt. Measured as _zero . The period Ts of the gate pulse signal output from the control circuit 2, a switching period of the converter unit CH _n.

In parallel with the measurement of the duty value Dt ₀ , the calculation of the current deviation by the current deviation calculator 6 _n and the determination of the correction duty value ΔD _n t ₀ by the duty adder 8 _n are executed.

The duty adder 8 _n outputs a drive signal having a gate pulse width of Dt ₀ + ΔD _n t ₀ obtained by adding the correction duty value ΔD _n t ₀ determined by the compensator 7 _n to the measured duty value Dt _0. Generate. Thereby, the gate pulse widths Dt ₀ + ΔD ₁ t ₀ , Dt ₀ + ΔD ₂ t ₀ ,..., Dt ₀ + ΔD _N t ₀ of the drive signals in the first to N-th operation phases are determined.

Next, the phase shifter 9 _n receives the drive signal generated by the duty adder 8 _n from time t ₁ , that is, the timing when the next gate pulse signal rises from the control circuit 2, Ts × (n−1) / N Only after a delay, the signal is output to the converter CH _n . As a result, a pulse having a gate pulse width Dt ₀ + ΔD ₁ t ₀ that rises at time t1 is output to the converter unit CH ₁ as a first-phase drive signal. Then, a pulse of gate pulse width Dt ₀ + ΔD ₂ t ₀ that rises with a delay of time Ts / N corresponding to a phase of 360 ° / N with respect to the driving signal of the first phase is input to the converter unit CH ₂ in the second phase. A drive signal is output. Similarly, the third to N-th phase drive signals generated by the duty adder 8 _n are output to the converter units CH _{2 to} CH _N by shifting the phase at time Ts / N intervals.

The gate pulse signal input from the control circuit 2 at time t ₁ after the pulse corrector 3 be made the same current correction and multi-phased, and output to the next switching period of time t ₂ later.

As described above, in the first embodiment, the gate pulse signal output from the control circuit 2 is input to the pulse corrector 3, the current correction is calculated and the phase shift operation is performed in the pulse corrector 3, and N The respective drive signals of the converter units CH _{1 to} CH _N are output. As a result, even if a microcomputer for a single-phase switching power supply device or a dedicated analog control IC is used, it is possible to easily realize multiphase and current balancing simply by adding the pulse corrector 3.

In the first embodiment, the multi-phase and current balancing are executed with a control delay of one switching cycle. However, the multi-phase and current balancing are executed without causing a control delay. You can also In this case, as shown in FIG. 3, the pulse corrector 3, the drive signal generation unit 5 of the _first phase, without performing calculation of the correction duty value [Delta] D _1, are output from the control circuit 2 the gate pulse signal is output as it is as the drive signal of the converter unit CH _1. Then, run the current balancing performs calculation of the correction duty value [Delta] D ₂ ～DerutaD _N respectively in the second phase, second N-phase driving signal generation unit 5 ₂ to 5 _N.

Referring to FIG. 3, the phase shifter 9 ₁ time t ₀ to the control circuit 2 and a drive signal generation unit 5 ₁ a gate pulse signal is inputted, a driving signal of the first phase to be output to the converter unit CH ₁ At the same time, the drive signal generators 5 _{2 to} 5 _N calculate the correction duty value ΔD _n t ₀ .

Next, the phase shifter 9 ₂ of the drive signal generation unit 5 ₂ raises the driving signal of the second phase at intervals of time Ts / N from the rise of the drive signal of the first phase. The phase shifters 9 _{3 to} 9 _{N of} the drive signal generation units 5 _{3 to} 5 _N also raise the second to N-phase drive signals at the same interval.

Next, the phase shifter 9 ₁ of the drive signal generation unit 5 _1, lowers the drive signal falling at the same time as the first phase of a gate pulse signal at time t _{0 +} DT _0. In the drive signal generators 5 _{2 to} 5 _N , as soon as the duty value DT ₀ of the gate pulse signal output from the control circuit 2 is determined, the duty value Dt ₀ and the correction duty value ΔD _n t calculated in advance are calculated. by adding ₀ to determine the gate pulse width DT ₀ + ΔD _n t ₀ to a driving signal of the first phase to n-th phase, the second phase to n-th phase in response to the gate pulse width DT ₀ + ΔD _n t ₀ determined The drive signal is lowered.

The gate pulse signal input from the control circuit 2 at time t ₁ after the pulse corrector 3 be made the same current correction and multi-phased, are output to the same switching period.

  As a result, multiphase and current balancing can be realized without causing a control delay. In the first phase operation phase, current balancing current correction is not performed, but in other phase operation phases, current balancing current correction is performed, so the first phase operation phase is also automatically current balanced. It is like that.

(Second Embodiment)
The switching power supply device 1a according to the second embodiment is a multi-phase inverter. Switching power supply unit 1a, referring to FIG. 4, a control circuit 2, the pulse corrector 3, a total current detecting circuit CT _0, and N of the inverter _INV 1 INV _N is the main circuit . Hereinafter, the description of the same configuration as that of the first embodiment will be omitted as appropriate.

In the switching power supply device 1a, a power source Vin is connected to the input side, and a load L is connected to the output side. In addition, between the power source Vin and the load L, N inverter units INV _{1 to} INV _N are connected and driven in parallel as the first to N-th operation phases.

The N inverter units INV _{1 to} INV _N are power conversion units having switching elements that are on / off controlled by pulse signals. The N inverter units INV _{1 to} INV _N have the same configuration. Therefore, it is assumed that n = 1 to N, and the inverter unit INV _n will be described in detail. Inverter unit INV _n includes a capacitor _{C n,} and inverting buffer NOT _n, a reactor _{S n,} and four switching elements _{Q n-1 to 4,} and a separate current detecting circuit CT _n, single-phase full-bridge It constitutes an inverter.

The capacitor C _n is connected in parallel with the power source Vin.

In the present embodiment, the four switching elements Qn _{-1 to 4} are configured by MOS-FETs. A series circuit including a switching element Q _n-1 and a switching element Q _n-2 is connected between the positive terminal and the negative terminal of the capacitor C _n , and the switching element Q _n-3 and the switching element Q _n are connected. _-4 is connected.

Connection point of the switching element _{Q n-1} and the switching element _{Q n-2} is connected to one end of the load L via a reactor _{S n,} a connection point between the switching elements _{Q n-3} and the switching element _{Q n-4} Is connected to the other end of the load L. A capacitor C ₀ that functions as a filter circuit that removes high-frequency components is connected between both ends of the load L together with the reactor S _n of the inverter unit INV _n .

The drive signal from the pulse corrector 3 is directly input to the gates of the switching element Q _n-1 and the switching element Q _n-4 , and the inverting buffer NOT _{n is} input to the gates of the switching element Q _n-2 and the switching element Q _n-3. Is input through. Thereby, on / off of switching element Qn _-1-4 is switched by a drive signal, and a DC voltage is converted into a desired AC voltage.

In the second embodiment, the individual current detection circuit CT _n detects the current flowing through the reactor S _n, that is, the output current of the inverter unit INV _n . Individual current detection circuit CT _n is composed of, for example, a current transformer or sense resistor. In the second embodiment, the current deviation calculator 6 _n of the pulse corrector 3 outputs the average current input from the divider 4 and the output of the inverter unit INV _n detected by the individual current detection circuit CT _n . The difference from the current (for example, the average value in the period Ts of the gate pulse signal) is calculated as the current deviation.

In the second embodiment, the total current detection circuit CT ₀ detects the output current output from the entire main circuit (inverter units INV _{1 to} INV _N ). Output current detected by the entire current detecting circuit CT ₀ is a inverter unit _INV 1 INV _N mainly the sum of the output currents flowing through the circuit (inverter _INV 1 INV _N) overall output current. Overall current detecting circuit CT ₀ is composed of, for example, a current transformer or sense resistor. In the second embodiment, the divider 4 of the pulse corrector 3 calculates the output current (for example, the average value in the period Ts of the gate pulse signal) detected by the total current detection circuit CT ₀ by the number of operation phases. The average current is calculated by dividing by N, and the calculated average current is output to the drive signal generation units 5 _{1 to} 5 _n , respectively.

As described above, in the second embodiment, the gate pulse signal output from the control circuit 2 is input to the pulse corrector 3, the current correction is calculated and the phase shift operation is performed in the pulse corrector 3, and N Each drive signal of the inverter units INV _{1 to} INV _N is output. As a result, even if a microcomputer for a single-phase switching power supply device or a dedicated analog control IC is used, it is possible to easily realize multiphase and current balancing simply by adding the pulse corrector 3.

(Third embodiment)
Referring to FIG. 5, the switching power supply device 1 b of the third embodiment includes an abnormal operation signal input from the converter units CH _{1 to} CH _N in addition to the configuration of the first embodiment. Is provided with a phase control unit 10 for controlling the number of operation phases to be driven.

The converter unit CH _n includes an abnormal operation detection unit 11 _n . When the abnormal operation detection unit 11 _n detects an operation abnormality such as overheating, short circuit, or failure of the converter unit CH _n , the abnormal operation detection unit 11 _n outputs an operation abnormality signal to the phase control unit 10 of the pulse corrector 3 a.

Based on the input abnormal operation signal, the phase control unit 10 sets the converter unit CH _n in which the operation abnormality is detected as an abnormal phase and sets the normal operation of the converter unit CH _n as the normal phase. N ′ (≦ N) is calculated. Then, the phase control unit 10, the phase shifter 9a _n abnormal operation is detected abnormal phase stops the output of the drive signal, the phase shifter 9a _n of normal phase operating normally 360 ° / A phase angle command shifted by N ′ is output. As a result, even if some converter units CH _n fail, N ′ converter units CH _n that are operating normally operate at equal phase angles with drive signals whose phases are shifted by 360 ° / N ′. The ripple component of the entire current can be minimized.

Further, the phase control unit 10 outputs the calculated normal phase number N ′ to the divider 4a. Then, divider 4a is by dividing the input current detected by the entire current detector CT ₀ at operation phase number N 'to calculate the average current, the calculated average current to the drive signal generating unit 5a ₁ to 5 A _n Output each. Thereby, in the second embodiment, the divider 4a is changed from 1 / N to 1 / N ′. Since the average current obtained by dividing the total input current by the number of operation phases N ′ becomes the target current value of each phase, the current balancing function of each phase works even when the number of operation phases to be driven changes.

Further, the phase control unit 10 outputs the calculated normal phase number N ′ to the control circuit 2a. The control circuit 2a determines the control gain of the entire main circuit (converters CH _{1 to} CH _N ) based on the normal phase number N ′. That is, since the transfer function to be controlled varies depending on the number of operating phases to be driven, the control circuit 2a decreases the control gain as the normal phase number N ′ decreases based on the normal phase number N ′. Thereby, the switching power supply device 1a can be controlled with an optimal control gain regardless of the number of operation phases to be driven.

  The control circuit 2a also determines a set value for overload protection based on the normal phase number N '. Specifically, the threshold for overload protection is lowered as the number of operation phases N ′ decreases by processing such as multiplying the threshold for overload protection by N ′ / N. Thereby, even when a failure occurs in a part of the operation phases, it is possible to operate safely with a reduced load.

  In the third embodiment, the example applied to the configuration of the first embodiment has been described. However, the third embodiment may be applied to the second embodiment.

As described above, in the third embodiment, even when one converter unit CH _n cannot be used due to abnormal operation, the remaining normal converter unit CH _n maintains the phase angle evenly and maintains each phase. It is possible to perform an operation while maintaining the current balance. Furthermore, it can operate safely with an optimal control gain.

As described above, according to the present embodiment, a plurality of power conversion units (converter unit CH _n , inverter unit INV _n ) having switching elements (switching elements Q _n , switching elements Q _n-1 to ₄ ) are provided. A main circuit connected in parallel to each other; a control circuit 2 that outputs a reference pulse signal based on the output of the entire main circuit; an overall current detection circuit CT ₀ that detects an output current of the entire main circuit as an overall current; multiple provided corresponding to the power conversion unit, and, on the basis of a plurality of individual current detection circuit CT _n for detecting an output current of a plurality of power converting unit each as a separate current, the total current and the individual current and the reference pulse signal Generating individual pulse signals for each of the power converters, and using the individual pulse signals for the plurality of power converters as drive signals for the switching elements And a pulse corrector 3 for outputting to each.
With this configuration, since the pulse corrector 3 can perform current correction and multi-phase based on the gate pulse signal output from the control circuit 2, the control circuit 2 has a multi-phase function. There is no need, and the main circuit can be multiphased only by adding the pulse corrector 3.

Further, according to the present embodiment, the pulse corrector 3 sets the individual pulse signal for each of the plurality of power conversion units to the duty value of the reference pulse signal so that the individual current for each of the plurality of power conversion units becomes equal. It corrects and generates each.
With this configuration, the current balancing of the plurality of power converters constituting the main circuit can be realized only by adding the pulse corrector 3.

Furthermore, according to the present embodiment, the pulse corrector 3 operates a plurality of power conversion units in multiphase.
With this configuration, an interleave (multi-phase) function can be easily provided simply by adding the pulse corrector 3.

Furthermore, according to the present embodiment, the pulse corrector 3 outputs the reference pulse signal as the switching element drive signal as it is for the first phase operation phase, and for the operation phases other than the first phase. The generated individual pulse signals are output with the phase shift angles shifted from the reference pulse signal evenly.
With this configuration, the gate pulse signal duty value D determined when the first-phase drive signal is output can be reflected in the second and subsequent phases, so that multiphase and current balancing can be achieved without causing a control delay. realizable.

Furthermore, according to the present embodiment, the abnormal operation detection unit 11 _n that detects each abnormal operation for each of the plurality of power conversion units is provided, and the pulse corrector 3 a includes the power conversion unit in which the abnormal operation is detected. Is the abnormal phase, the output of the individual pulse signal is stopped, and the power conversion unit where no abnormal operation is detected is set to the normal phase, and the duty value of the reference pulse signal is corrected so that the individual current for each normal phase is equal Respectively.
With this configuration, even when a part of the power converter constituting the main circuit cannot be used due to abnormal operation, the remaining normal power converter maintains the current balance of each phase while keeping the phase angle uniform. Operation can be performed. Moreover, since it drives except an abnormal power converter, redundant operation is attained.

Furthermore, according to the present embodiment, the pulse corrector 3a outputs the number of normal phases to the control circuit 2a, and the control circuit 2a determines the control gain of the entire main circuit and the overload detection based on the number of normal phases. Either or both of the threshold values are changed.
With this configuration, it is possible to operate safely with an optimum control gain.

Furthermore, according to the present embodiment, the pulse corrector 3 is configured by an FPGA (Field Programmable Gate Array).
With this configuration, the pulse corrector 3 can be easily configured by using an FPGA, and a switching power supply circuit having an interleave (multiphase) function can be easily constructed using a single-phase control circuit. be able to.

  As mentioned above, although this invention was demonstrated by specific embodiment, the said embodiment is an example and it cannot be overemphasized that it can change and implement in the range which does not deviate from the meaning of this invention.

1, 1a, 1b switching power supply Vin power _CH 1 to CH _N converter section _S 1 to S _N reactor _D 1 to D _N diode _{Q 1 ~Q N, Q 1-1~4 ~Q} N-1~4 switching element C _{0, 1} ~C _N capacitor CT ₀ total current detector _CT 1 to CT _N individual current detection circuit _INV 1 INV _N inverter _NOT 1 _{~NOT N-inverting} buffer L load 2,2a control circuit 3,3a pulse corrector 4, 4a Dividers 5 _{1 to} 5 _N , 5a _{1 to} 5a _N Drive signal generators 6 _{1 to} 6 _N Current deviation calculators 7 _{1 to} 7 _N Compensators 8 ₁ to 8 _N Duty adders 9 _{1 to} 9 _N , 9 _{a1 to} 9 _aN phase shifter 10 phase controller 11 _{1 to} 11 _N abnormal operation detector

Claims (6)

A main circuit in which a plurality of power conversion units having switching elements are connected in parallel to each other;
A control circuit that outputs a reference pulse signal based on the output of the entire main circuit;
An overall current detection circuit for detecting an output current of the entire main circuit as an overall current;
A plurality of individual current detection circuits that are provided corresponding to the plurality of power conversion units and detect output currents for the plurality of power conversion units as individual currents;
Based on the total current, the individual current, and the reference pulse signal, the individual pulse signal for each of the plurality of power conversion units is generated, and the individual pulse signal for each of the plurality of power conversion units is generated as the switching element. And a pulse corrector that outputs to each of the plurality of power converters as a drive signal for the switching power supply.   The pulse corrector generates the individual pulse signal for each of the plurality of power converters by correcting the duty value of the reference pulse signal so that the individual currents for the plurality of power converters are equalized. The switching power supply device according to claim 1.   The switching power supply device according to claim 1, wherein the pulse corrector operates a plurality of the power conversion units in multiphase.   The pulse corrector outputs the reference pulse signal as it is as a drive signal of the switching element for the first phase operation phase, and generates the individual pulse signal generated for each operation phase other than the first phase. 4. The switching power supply device according to claim 3, wherein the phase shift angle is shifted equally from the reference pulse signal, respectively. Comprising an abnormal operation detector for detecting each abnormal operation for each of the plurality of power converters;
The pulse corrector sets the power conversion unit in which an abnormal operation is detected as an abnormal phase, stops the output of the individual pulse signal, sets the power conversion unit in which no abnormal operation is detected as a normal phase, and performs the normal operation. 5. The switching power supply device according to claim 3, wherein a duty value of the reference pulse signal is corrected and generated so that the individual current for each phase becomes equal. The pulse corrector outputs the number of normal phases to the control circuit,
6. The switching power supply device according to claim 5, wherein the control circuit changes either or both of a control gain of the entire main circuit and an overload detection threshold based on the number of normal phases. .

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