JP2019176382A - Gate drive circuit and switching device using the same - Google Patents

Abstract

To secure a sufficient withstand voltage and achieve miniaturization.SOLUTION: A gate drive circuit 1 includes: a transmitter unit 10 which generates a power signal to be used to drive the gate of a semiconductor switching element 60; an isolation element 3 which transmits a power signal in an electrically isolated state; a plurality of rectifier circuits 2 which rectify the output of isolation element 3 to output as a rectification signal; and a plurality of drive transistors 5 connected in cascade between a power source and the gate of the semiconductor switching element 60. To the gate of each drive transistor 5, the output of each rectifier circuit 2 is given, whereas to the source, the ground terminal of the rectifier circuit 2 provided in association therewith is connected.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a gate driving circuit of a power semiconductor device.

  With power electronics technology, electric appliances are being downsized regardless of consumer or industrial use. In an inverter circuit used in such a device, large power is switched at a frequency of about several kHz to several MHz using a semiconductor switching element (for example, an IGBT (Insulated Gate Bipolar Transistor)). The gate drive circuit is a circuit that drives the gate of the semiconductor switching element.

  In the inverter circuit as described above, the difference between the control signal of the gate drive circuit and the operating voltage of the semiconductor switching element is large. Therefore, it is necessary to electrically insulate the input side (hereinafter referred to as the primary side) and the output side (hereinafter referred to as the secondary side) of the gate drive circuit.

  In Patent Document 1, an insulated gate drive circuit is realized by using a plurality of electromagnetic resonance couplers.

  Patent Document 2 discloses a circuit that separates signals by using multiple stages of transistors and using the same number of transformers as the transistors in order to individually drive the multistage transistors.

JP 2004-294420 A Japanese Patent No. 6157625

  By the way, an element (hereinafter referred to as a high frequency device) having a relatively low breakdown voltage generated by a high frequency process of a compound semiconductor (for example, SiGe or GaAs) is used on the secondary side (for example, rectifier circuit) of the gate drive circuit. If possible, the conversion efficiency of the rectifier circuit can be improved. Further, the high-frequency device has an advantage that the degree of freedom of design is increased because there are many choices of elements as compared with a semiconductor element of a high breakdown voltage process (hereinafter referred to as a high breakdown voltage device).

  However, in the gate drive circuit, it is necessary to apply a pulsed drive voltage having an amplitude of about 20 V between the gate and the source of the semiconductor switching element. As a result, the high-frequency device has a problem that the withstand voltage cannot be sufficiently secured and is difficult to apply to the gate drive circuit.

  As a method for avoiding such a problem, it is conceivable to increase the number of transistors as in Patent Document 2. However, the technique of Patent Document 2 uses the same number of insulating transformers as multistaged transistors, and there is a problem that the size of the device increases.

  The present invention has been made in view of the above points, and an object of the present invention is to ensure a sufficient withstand voltage and realize miniaturization even when a high-frequency device is used for a gate drive circuit.

  A gate driving circuit according to an aspect of the present invention includes a transmission unit that generates a power signal that is a basis of gate driving of the semiconductor switching element, and an isolation element that transmits the power signal in an electrically insulated state. A plurality of rectifier circuits that receive the outputs of the isolation elements at respective input terminals separated from each other in a direct current, rectify and output as rectified signals, and corresponding to the rectifier circuits, And a plurality of drive transistors connected in cascode between the power source and the gate of the semiconductor switching element. The drive transistor is characterized in that the output of the rectifier circuit is supplied to the gate and the ground terminal of the rectifier circuit is connected to the source.

  According to this configuration, the output of the isolation element is branched, and the cascode-connected driving transistor is driven through the plurality of rectifier circuits in which the input terminals are separated from each other in a direct current manner. Thereby, an excessive breakdown voltage is not required for DC separation of the rectifier circuit, and an element having a relatively low breakdown voltage (for example, a capacitor element formed on a semiconductor) can be used. As a result, the gate drive circuit can be downsized while ensuring a sufficient breakdown voltage for driving the semiconductor switching element.

  According to the gate drive circuit according to the present disclosure, even when a semiconductor process with a low breakdown voltage is used, the gate drive circuit can be downsized while ensuring a sufficient breakdown voltage for driving the semiconductor switching element.

Block diagram showing the configuration of the gate drive circuit of the first embodiment Layout diagram showing the configuration of the receiving part of the gate drive circuit 2 is an exploded perspective view of the inductor portion of FIG. Timing chart showing the operation of the gate drive circuit of the first embodiment The figure for demonstrating operation | movement of the receiving unit of a gate drive circuit The figure for demonstrating operation | movement of the receiving unit of a gate drive circuit The block diagram which shows the structure of the gate drive circuit of 2nd Embodiment. Timing chart showing the operation of the gate drive circuit of the second embodiment The block diagram which shows the structure of the gate drive circuit of 3rd Embodiment. The block diagram which shows the structure of the gate drive circuit of a comparative example Timing chart showing operation of gate drive circuit of comparative example Circuit diagram showing another configuration example of rectifier circuit

  Hereinafter, embodiments will be specifically described with reference to the drawings.

  It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements.

<First Embodiment>
-Configuration of gate drive circuit-
FIG. 1 is a schematic diagram illustrating a configuration of a switching device A according to the present embodiment. As shown in FIG. 1, the switching device A includes a semiconductor switching element 60 and a gate drive circuit 1 that drives the semiconductor switching element 60.

  The gate drive circuit 1 includes a transmission unit 10, an isolation unit 11, and a reception unit 12 including a plurality of reception units 13. FIG. 1 illustrates an example in which the reception unit 12 includes a power supply rectifier circuit 20 and two reception units 13 that are cascode-connected. A connection node N <b> 1 that connects the two receiving units 13 is connected to the gate of the semiconductor switching element 60. In the following description, the receiving unit 13 connected to the high potential side may be referred to as a first receiving unit 13a, and the receiving unit 13 connected to the low potential side may be referred to as a second receiving unit 13b.

  The gate driving circuit 1 generates the output pulse voltage by alternately switching the first and second receiving units 13a and 13b, and drives the gate of the semiconductor switching element 60. Thereby, the gate drive circuit 1 performs switching of the voltage supplied by the load power supply 102, for example.

  The transmitter 10 has a function of generating PWM (Pulse Width Modulation) control signals S11 and S12 as power signals that are the basis for driving the semiconductor switching element 60. Specifically, the transmission unit 10 includes an oscillator 50 that oscillates upon receiving a power supply voltage Vi from the power supply 100, and a mixer 52 that receives an output of the oscillator 50. The mixer 52 modulates the output of the oscillator 50 in accordance with the PWM voltage Vm from the PWM power supply 101 and outputs it to the isolation unit 11 as the first and second PWM control signals S11 and S12. Further, the transmission unit 10 includes an amplifier 51 provided in a path for supplying driving power for the gate driving circuit 1. The amplifier 51 receives an output from an oscillator 50 of the transmitter 10 described later, amplifies it, and outputs it as a high-frequency signal S13.

  The isolation unit 11 includes a power supply isolation element 3, a first isolation element 3a, and a second isolation element 3b. For example, a conventionally known electromagnetic resonance coupler can be applied to the power source isolation element 3, the first isolation element 3a, and the second isolation element 3b. The power supply isolation element 3 and the first and second isolation elements 3a and 3b can adopt the same configuration. In the present embodiment, these are collectively referred to as “isolation element 3”. There is.

  The power supply isolation element 3 is provided in a path for supplying the drive power of the gate drive circuit 1, receives the high frequency signal S13 output from the amplifier 51, and is electrically insulated in the subsequent power supply element. Transmit to the rectifier circuit 20.

  The first isolation element 3a receives the first PWM control signal S11 and transmits this signal in an electrically insulated state. The second isolation element 3b receives the second PWM control signal S12 and transmits this signal in an electrically insulated state. Receiving units 13a and 13b are connected to the outputs of the first and second isolation elements 3a and 3b, respectively.

  FIG. 1 shows an example in which the first receiving unit 13a connected to the first isolation element 3a and the second receiving unit 13b connected to the second isolation element 3b have the same configuration. In the present embodiment, the first receiving unit 13a and the second receiving unit 13b may be collectively referred to simply as “receiving unit 13”.

  The power supply rectifier circuit 20 converts the output of the power supply isolation element 3 into a positive voltage and charges the capacitor 74. Although the magnitude | size of the capacity | capacitance of the capacitor | condenser 74 is not specifically limited, For example, it is about several micro F.

  The receiving unit 13 includes a plurality of rectifier circuits 2 and a plurality of drive transistors 5 provided corresponding to the rectifier circuits 2. FIG. 1 shows an example in which the reception unit 13 includes two rectifier circuits 2 and two drive transistors 5.

  The two drive transistors 5 are cascode-connected between a high potential side node (hereinafter referred to as a high potential node) and a low potential side node (hereinafter referred to as a low potential node).

  In the following description, the driving transistors 5 connected to the high potential nodes of the first receiving unit 13a and the second receiving unit 13b may be referred to as first driving transistors 5a and 5c, respectively. In addition, the drive transistors 5 connected to the low potential nodes of the first reception unit 13a and the second reception unit 13b may be referred to as second drive transistors 5b and 5d, respectively.

  As described above, the drive transistor 5 and the rectifier circuit 2 have a corresponding relationship, and the rectifier circuit 2 corresponding to the first drive transistors 5a and 5c may be referred to as first rectifier circuits 2a and 2c, respectively. The rectifier circuit 2 corresponding to the second drive transistors 5b and 5d may be referred to as second rectifier circuits 2b and 2d. Note that a circuit having the same configuration can be applied to the power supply rectifier circuit 20 and the plurality of rectifier circuits 2 (2a to 2d), and these may be collectively referred to simply as “rectifier circuit 2”. is there.

  Each rectifier circuit 2 has an input terminal, an output terminal, and a ground terminal. An input capacitor 21 and an inductor 22 are connected in series between the input terminal and the output terminal. The intermediate node between the input capacitor 21 and the inductor 22 is connected to the ground terminal via the forward diode 23. Further, an output capacitor 24 is provided between the output terminal and the ground terminal. With such a configuration, the input terminals of the rectifier circuit 2 connected to the common power supply isolation element 3 are separated from each other in a direct current manner.

  The first rectifier circuit 2a of the first receiver unit 13a rectifies the first PWM control signal S11 received from the transmitter 10 via the first isolation element 3a, and outputs it as a voltage pulse signal to the gate of the first drive transistor 5a. To do. The ground terminal of the first rectifier circuit 2a is connected to the source of the first drive transistor 5a (the drain of the second drive transistor 5b), and the resistance element 4a is provided between the gate and the source of the first drive transistor 5a.

  Similarly, in the first rectification circuit 2c of the second reception unit 13b, the second PWM control signal S12 received from the transmission unit 10 via the second isolation element 3b is rectified and used as a voltage pulse signal of the first drive transistor 5c. Output to the gate. The ground terminal of the first rectifier circuit 2c is connected to the source of the first drive transistor 5c (the drain of the second drive transistor 5d), and the resistance element 4c is provided between the gate and the source of the first drive transistor 5c.

  The second rectification circuit 2b of the first reception unit 13a rectifies the first PWM control signal S11 received from the transmission unit 10 via the first isolation element 3a, and outputs it as a voltage pulse signal to the gate of the second drive transistor 5b. To do. The ground terminal of the second rectifier circuit 2b is connected to the source of the second drive transistor 5b (the drain of the second drive transistor 5d), and the resistance element 4b is provided between the gate and source of the second drive transistor 5b.

  Similarly, the second rectification circuit 2d of the second reception unit 13b rectifies the second PWM control signal S12 received from the transmission unit 10 via the second isolation element 3b, and outputs a voltage pulse signal of the second drive transistor 5d. Output to the gate. The ground terminal of the second rectifier circuit 2d is connected to the source (secondary ground 201) of the second drive transistor 5d, and the resistance element 4d is provided between the gate and source of the second drive transistor 5d.

  FIG. 2 shows an example of a layout configuration related to the front stage portion (including the rectifier circuit 2) of the receiving unit 13. In the following description of FIG. 2, the first receiving unit 13a will be described as an example.

  The input terminal 120 of the receiving unit 13 is connected to the output end (not shown) of the isolation element 3 by wire bonding. The high frequency signal input from the input terminal 120 is branched and supplied to the two input capacitors 21. That is, each path is DC separated.

  In FIG. 2, 121 is a ground terminal connected to the ground terminal of the rectifier circuit 2b. An intermediate terminal 122 is connected to the ground terminal of the first rectifier circuit 2a, and serves as a connection point between the first and second drive transistors 5a and 5b that are cascode-connected. Reference numeral 22 denotes a diode, which can be configured, for example, by short-circuiting the source and drain of a GaAs-FET having a gate width of 20 μm and using the gate and drain / source. For example, the diode 22 may be used by connecting three diodes (using GaAs-FETs) connected in parallel in three stages from the viewpoint of securing a withstand voltage and a driving current (not shown).

  Further, in the layout of FIG. 2, two spiral inductors corresponding to the inductor 22 are configured. More specifically, as shown in FIG. 3, the inductor 22 included on the first rectifier circuit 2a side is configured with a third layer, and the inductor 22 included on the second rectifier circuit 2b side is configured with a second layer. FIG. 3 shows an example in which the output of each inductor 22 is drawn in the first layer. The output of the inductor 22 is connected to the gates of the first and second drive transistors 5a and 5b, respectively. 2 and 3, X1 and Y2 are an input terminal and an output terminal of the inductor 22 of the first rectifier circuit 2a, respectively. Similarly, X2 and Y2 are an input terminal and an output terminal of the inductor 22 of the second rectifier circuit 2b, respectively.

  As described above, according to this aspect, the spiral inductors occupying a large area on the semiconductor chip can be arranged one above the other so that the chip area can be greatly reduced. The winding direction of the inductor 22 is preferably the same direction. Since the in-phase signal is input to each inductor 22, the signal level can be prevented from being attenuated. However, the arrangement is not limited to such an arrangement, and the upper and lower inductors 22 may be arranged so as to be shifted from front to back and from side to side. Further, the inductors 22 may be wired by being wound in opposite directions.

  With the above configuration, even when the gate drive circuit 1 is driven under the condition of a capacitive load of 47 [nF] at a PWM frequency of 10 [kHz], good switching characteristics can be obtained without breaking. It was.

  The primary side grounding 200 and the secondary side grounding 201 are electrically separated from each other by the isolation unit 11. The same applies to the following second and third embodiments.

-Operation of gate drive circuit-
Next, the operation of the gate drive circuit 1 according to the present embodiment will be specifically described with reference to FIGS.

  First, the operation of the receiving unit 13 of the gate drive circuit 1 will be described with reference to FIGS. FIG. 5 shows an example in which the receiving unit 13 switches the voltage generated in the load resistor 62 by the power source 102 in accordance with the on / off of the high-frequency signal source 200 (corresponding to the oscillator 50). As shown in FIG. 1 described above, in the actual gate driving circuit 1, a plurality of receiving units 13 (two in FIG. 1) are cascode-connected, and these are alternately switched, whereby the output pulses of the gate driving circuit 1 are displayed. Generate voltage.

  In FIG. 5, the high-frequency signal S0 output from the high-frequency signal source 200 passes through the isolation element 3, branches, and is input to the first and second rectifier circuits 2a and 2b.

  In the ON period (for example, high level period) of the high-frequency signal S0, the first and second rectifier circuits 2a and 2b convert the high-frequency signal S0 to DC and generate negative voltages in the resistance elements 4a and 4b, respectively. Accordingly, Vgs of the first and second drive transistors 5a and 5b becomes a negative voltage, and the first and second drive transistors 5a and 5b are turned off.

  On the other hand, in the off period (for example, low level period) of the high-frequency signal S0, the voltages of the resistance elements 4a and 4b are substantially 0 [V], respectively. That is, Vgs of the first and second drive transistors 5a and 5b is substantially 0 [V], and the first and second drive transistors 5a and 5b are turned on.

  In the present embodiment, the first and second rectifier circuits 2a and 2b are connected with reference to the sources of the first and second drive transistors 5a and 5b corresponding thereto. Thereby, the first and second drive transistors 5a and 5b can be driven uniformly. That is, even in the pulse driving state, it is possible to evenly divide the voltage applied between the drain and source of each of the driving transistors 5a and 5b in the off state of the first and second driving transistors 5a and 5b.

  FIG. 6 is a simulation result of the switching characteristics of the receiving unit 13 shown in FIG. In the simulation of FIG. 6, the frequency of the high-frequency signal source 200 is 2.4 [GHz], and the voltage of the power source 102 is 20 [V]. FIG. 6A shows changes in Vgs and Vds of the first and second drive transistors 5a and 5b when the signal level of the high-frequency signal source 200 is in the range of 0 to 25 [dBm]. Note that the above specific numerical values are merely examples, and other numerical values (for example, frequencies other than 2.4 [GHz]) may be applied.

  In FIG. 6A, the region T1 indicates the on period of the first and second drive transistors 5a and 5b, and the region T2 indicates the off period of the first and second drive transistors 5a and 5b. A region T3 shows a transition period from the on period to the off period of the first and second drive transistors 5a and 5b. 6B and 6C show the result of enlarging the area around the region T3 with respect to the change in Vds of the first and second drive transistors 5a and 5b. In the following description, T1 is referred to as an on region, T2 is referred to as an off region, and T3 is referred to as a transition region.

  As shown in the lower part of FIG. 6A, Vgs of the first and second drive transistors 5a and 5b show substantially the same locus with respect to changes in signal level. Further, as shown in the upper part of FIG. 6A, in the off region T2, the Vds of each of the drive transistors 5a and 5b is 10 V that is ½ of the power supply voltage, and the two drive transistors 5a and 5b. It can be seen that operates almost equally.

  On the other hand, in the transition region T3, although the first and second rectifier circuits 2a and 2b, the first and second drive transistors 5a and 5b, and the resistance elements 4a and 4b have an equivalent circuit configuration, An asymmetric operation is triggered by the on / off transition of one of the drive transistors 5a and 5b. In the example of FIG. 6, as shown by thin lines in FIGS. 6B and 6C, a transient region where the voltage is concentrated only on the first drive transistor 5a is seen.

  However, in the actual gate drive circuit 1 configured as shown in FIG. 1, the rise time and the fall time of the high frequency signal with respect to the PWM signal are as high as about 10 [ns] at most. Therefore, in the design of the transmitter 10, the power output from the high-frequency signal source 200 is set as follows, so that the influence of the region T3 on the switching characteristics of the drive transistors 5a and 5b can be almost eliminated. For example, the output power of the high-frequency signal source 200 is such that the power defining the off state of the first and second drive transistors 5a and 5b is about −20 [dBm] and the power defining the on state is about 20 [dBm]. It is good to.

  In the receiving unit 13, as described below, the range of the transition region T3 can be adjusted by setting the magnitude relationship between the resistance elements 4a and 4b. By making such an adjustment, for example, it is possible to cope with faster driving conditions and to reduce power consumption in the transmission unit 10.

  Specifically, FIG. 6B shows an example in which the resistance value of the resistance element 4a is increased from the state of FIG. Specifically, it is a simulation result in which the resistance value of the resistance element 4a is increased by 15%.

  As shown in FIG. 6B, when the resistance value of the resistance element 4a serving as the load of the rectifier circuit 2a increases, the voltage level generated in the resistance element 4a increases. Then, the first driving transistor 5a is easily turned off with respect to an increase in the input level of the high-frequency signal source 200. Therefore, in this example, as shown by the thick line in FIG. 6B, the asymmetry of the first and second drive transistors 5a and 5b is increased, and the transition region T3 is expanded.

  On the other hand, FIG. 6C shows an example in which the resistance value of the resistance element 4a is reduced from the state of FIG. Specifically, it is a simulation result in which the resistance value of the resistance element 4a is reduced by 15%.

  As shown in FIG. 6C, when the resistance value of the resistance element 4a serving as the load of the rectifier circuit 2a is decreased, the voltage level generated in the resistance element 4a is decreased. As a result, the first drive transistor 5a is less likely to be turned off as the input level of the high-frequency signal source 200 increases. Therefore, in this example, as shown by the thick line in FIG. 6C, the asymmetry of the first and second drive transistors 5a and 5b is weakened, and the transition region T3 is narrowed.

  Next, the operation of the gate drive circuit 1 will be specifically described with reference to FIG.

  The high frequency signal generated by the oscillator 50 is modulated by the mixer 52 in accordance with the PWM voltage Vm, and is divided into first and second PWM control signals S11 and S12.

  The first PWM control signal S11 passes through the first isolation element 3a, branches, and is input to the first and second rectifier circuits 2a and 2b of the first receiving unit 13a, respectively. The first receiving unit 13a can uniformly drive the first and second drive transistors 5a and 5b and can equally divide the voltage applied to the off state.

  Similarly, the second PWM control signal S12 passes through the second isolation element 3b, branches, and is input to the first and second rectifier circuits 2c and 2d of the second reception unit 13b, respectively. Then, the second receiving unit 13b uniformly drives the drive transistors 5c and 5d and equally divides the voltage applied to the off state.

  The specific operations of the first and second receiving units 13a and 13b are the same as those described above with reference to FIG. 5, and a detailed description thereof is omitted here.

  As shown in FIG. 4, the first PWM control signal S11 and the second PWM control signal S12 are complementary to each other during the on / off period. Therefore, the gate signals S21a and S21b of the first and second driving transistors 5a and 5b of the first receiving unit 13a and the gate signals S21c and S21d of the first and second driving transistors 5c and 5d of the second receiving unit 13b are as follows. , It becomes a complementary pulse signal.

  As a result, the voltage of the capacitor 74 serving as the output voltage of the gate driving circuit is changed between the first and second driving transistors 5a and 5b of the first receiving unit 13a and the first and second driving transistors 5c and 5b of the second receiving unit 13b. The switching is alternately performed by 5d and applied to the gate of the semiconductor switching element 60.

  At this time, in the off period T11 of the first and second drive transistors 5a and 5b of the first receiving unit 13a, the voltage applied to each of the first and second drive transistors 5a and 5b is 1 of the output voltage of the gate drive circuit. / 2. Similarly, in the off period T12 of the first and second drive transistors 5c and 5d of the second receiving unit 13b, the voltage applied to each of the first and second drive transistors 5c and 5d is 1 of the output voltage of the gate drive circuit. / 2.

-Comparative example-
FIG. 10 shows a comparative example of the switching device created based on FIG.

  FIG. 11 shows potential changes of the gate drive circuit 9 and the semiconductor switching element 99 during the operation of the gate drive circuit 9 of the comparative example. In FIG. 11, a voltage having the same amplitude as the output voltage Vo is applied between the drain and source of the drive transistors 95a and 95b. On the other hand, in the switching device A of the present embodiment, the voltage between the drain and source of the first and second drive transistors 5a to 5d can be made almost half of the output voltage Vo. Therefore, it is possible to use a semiconductor process with a low breakdown voltage.

  In the above embodiment, an example in which two (two stages) drive transistors 5 are cascode-connected has been shown, but three or more stages of drive transistors 5 may be cascode-connected. By doing so, the voltage applied per drive transistor 5 can be further reduced. Even in this case, the number of branches of the output of the isolation element 3 may be increased and the rectifier circuit 2 corresponding to the number of the drive transistors 5 may be provided.

  Further, for example, in the above embodiment, the PWM control signal S11 is opposite in phase to the PWM voltage Vm (pulse waveform signal) of the PWM power supply 101, and the PWM control signal S12 is in phase, but this The relationship may be reversed, and the operation can be performed in the same manner as in the above embodiment.

  In the above embodiment, instead of the mixer 52, an amplifier that amplifies the output of the oscillator 50, and an SPDT (Single) that outputs the first and second PWM control signals S11 and S12 to the isolation unit 11 by switching the output of the amplifier. -Pole Double-Throw) switch.

<Second Embodiment>
FIG. 7 is a schematic diagram showing the configuration of the switching device A of the present embodiment. In FIG. 7, the same reference numerals are given to components common to FIG. 1 (having the same or similar functions). In the following description, the gate drive circuit 1 that is different from FIG. 1 will be described in detail, and the description of the common part with FIG. 1 may be omitted.

  The gate drive circuit 1 shown in FIG. 7 includes a transmission unit 10, an isolation unit 11, and a reception unit 12 including first and second reception units 13a and 13b. In FIG. 7, as in FIG. 1, the first and second receiving units 13 a and 13 b are connected in cascode, and the connection node N <b> 1 connecting the receiving units 13 a and 13 b is connected to the gate of the semiconductor switching element 60. Yes. The gate driving circuit 1 generates the output pulse voltage by alternately switching the first and second receiving units 13a and 13b, and drives the gate of the semiconductor switching element 60. Thereby, the gate drive circuit 1 performs switching of the voltage supplied by the load power supply 102, for example.

  The transmission unit 10 has a function of generating the PWM control signal S15. Specifically, the transmitter 10 includes an oscillator 50 that receives and transmits a power supply voltage Vi from the power supply 100, and an amplifier 55 that receives the output of the oscillator 50. The amplifier 55 amplitude-modulates the output of the oscillator 50 according to the PWM voltage Vm from the PWM power supply 101, and outputs it to the isolation unit 11 as a PWM control signal S15.

  The configuration of the amplifier 55 is not particularly limited. For example, a method of changing the bias state by changing the potential of the base or gate of the transistor constituting the amplifier 55, or a method of changing the power supply supplied to the collector or drain of the transistor. is there. Further, a similar function may be realized by switching the attenuation amount of the attenuator or SW provided on the input side or output side of the amplifier 55. The same applies to an amplifier 55 (see FIG. 9) provided in the transmission unit 10 of the third embodiment to be described later.

  The isolation unit 11 receives the PWM control signal S15 and the isolation element 3c provided in the path for supplying the driving power of the gate drive circuit 1, and transmits this signal in an electrically insulated state. 3d.

  The output of the isolation element 3c is branched into two, with one branch destination connected to the input node of the power supply rectifier circuit 20 and the other branch destination connected to an input node of the rectifier circuit 2f described later. .

  The output of the isolation element 3d is branched into two, with one branch destination connected to the input node of the first receiving unit 13a and the other branch destination connected to the input node of the second receiving unit 13b.

  The first receiving unit 13a includes two rectifier circuits 2f and 2g, an inverter unit 70, and a drive transistor 5g as an inverting drive transistor. Note that the rectifier circuits 2f and 2g can apply a circuit configuration common to the rectifier circuit 2 of FIG. 1, and description of the specific circuit configuration is omitted here.

  One rectifier circuit 2 f is a rectifier circuit for generating power for the inverter unit 70, rectifies the high-frequency signal S 13 output from the isolation element 3 c, and supplies the rectified circuit to the power node of the inverter unit 70. The other rectifier circuit 2g is a drive signal generating rectifier circuit that drives the inverter unit 70, rectifies the PWM control signal S15 received from the isolation element 3d, and supplies it to the drive node of the inverter unit 70.

  The inverter unit 70 has a function of inverting and outputting the rectified signal S31 received from the rectifier circuit 2g for generating the drive signal. FIG. 7 shows an example in which an NPN bipolar transistor and a resistor are used as the inverter unit 70. The output of the inverter unit 70 is given to the gate of the drive transistor 5g. Note that the configuration of the inverter unit 70 is not limited to the configuration of FIG. 7, and other semiconductor elements or circuit configurations that function as an inverter may be used.

  The second receiving unit 13b includes a rectifier circuit 2h that rectifies the PWM control signal S15 output from the isolation element 3d, and a drive transistor 5h provided corresponding to the rectifier circuit 2h.

-Operation of gate drive circuit-
Next, the operation of the gate drive circuit 1 according to the present embodiment will be specifically described with reference to FIG. FIG. 8 shows potential changes in the gate drive circuit 1 and the semiconductor switching element 60 during the operation of the gate drive circuit.

  The PWM control signal S15 generated by the oscillator 50 is amplitude-modulated in the amplifier 55 according to the PWM voltage Vm, and is output as the PWM control signal S15.

  The PWM control signal S15 passes through the isolation element 3d, branches, and is input to the rectification circuit 2g of the first reception unit 13a and the rectification circuit 2h of the second reception unit 13b, respectively.

  In the ON period (for example, high level period) of the PWM control signal S15, the PWM control signal S15 is DC-converted in the rectifier circuit 2g of the first receiving unit 13a to generate a negative voltage. Since the output of the rectifier circuit 2g is inverted by the inverter unit 70, the gate signal S32 of the drive transistor 5g (Vgs of the drive transistor 5g) becomes approximately 0 [V]. That is, the driving transistor 5g of the first receiving unit 13a is turned on.

  At this time, in the second receiving unit 13b, the PWM control signal S15 is DC-converted in the rectifier circuit 2h and is directly applied to the gate of the drive transistor 5h. That is, a negative voltage is applied as the gate signal S33 of the drive transistor 5h, and the drive transistor 5h is turned off.

  In the off period (for example, low level period) of the PWM control signal S15, in the first receiving unit 13a, the gate signal S32 of the drive transistor 5g (Vgs of the drive transistor 5g) becomes a negative voltage. On the other hand, the gate signal S33 of the drive transistor 5h is substantially 0 [V]. That is, the driving transistor 5g of the first receiving unit 13a is turned off, and the driving transistor 5h of the second receiving unit 13b is turned on.

  That is, in the first receiving unit 13a, the rectified signal S31 (pulse voltage signal) having the same phase as the PWM voltage Vm is inverted by the inverter unit 70 and applied to Vgs of the driving transistor 5g. On the other hand, in the second receiving unit 13b, a pulse voltage having the same phase as the PWM voltage Vm is generated and applied to the drive transistor 5h. As a result, the drive transistors 5g and 5h are alternately turned on and off. Then, the voltage of the capacitor 74, which is the output voltage of the gate drive circuit 1, is alternately switched by the drive transistors 5g and 5h and applied to the gate of the semiconductor switching element 60.

  Here, in the comparative example shown in FIG. 10 described above, two paths for transmitting the PWM control signal of the gate drive circuit 9 are necessary, and it is necessary to provide the isolation element 93 in each path. On the other hand, in this embodiment, since the isolation element 3 can be reduced to one, the size of the transmission unit 10 and the isolation unit 11 can be reduced. Thereby, the size of the entire gate drive circuit 1 can be reduced.

  In the above-described embodiment, the example in which the power supply of the inverter unit 70 of the first receiving unit 13a is received from the path for supplying the driving power of the gate driving circuit 1 is shown, but the present invention is not limited to this. For example, power may be supplied to the inverter unit 70 from the outside of the gate drive circuit 1.

<Third Embodiment>
FIG. 9 is a schematic diagram showing the configuration of the switching device A of the present embodiment. The switching device A shown in FIG. 9 has a configuration combining the configuration of the first embodiment and the configuration of the second embodiment. In FIG. 9, the same reference numerals are given to the components common (having the same or similar functions) as those in FIG. 1 and / or FIG. 7. In the following description, the gate drive circuit 1 that is different from FIG. 1 and / or FIG. 7 will be described in detail, and description of common parts with FIG. 1 and / or FIG. 7 may be omitted. .

  The gate drive circuit 1 shown in FIG. 9 includes a transmission unit 10, an isolation unit 11, and a reception unit 12 including first and second reception units 13a and 13b. In FIG. 9, as in the first and second embodiments, the first and second receiving units 13a and 13b are cascode-connected, and the connection node N1 connecting the receiving units 13a and 13b is connected to the semiconductor switching element 60. Connected to the gate.

  The gate driving circuit 1 generates the output pulse voltage by alternately switching the first and second receiving units 13a and 13b, and drives the gate of the semiconductor switching element 60. Thereby, the gate drive circuit 1 performs switching of the voltage supplied by the load power supply 102, for example.

  The configurations of the transmission unit 10 and the isolation unit 11 are the same as those in FIG.

  Specifically, the transmission unit includes an oscillator 50 and an amplifier 55 that receives the output of the oscillator 50 and performs amplitude modulation, and has a function of generating the PWM control signal S15.

  The isolation unit 11 includes isolation elements 3c and 3d.

  The isolation element 3c receives the high frequency signal S13 from the amplifier 51 of the transmission unit 10, and transmits this signal in an electrically insulated state. The output of the isolation element 3c is branched into three and connected to the input node of the power supply rectifier circuit 20 and the input nodes of rectifier circuits 2fa and 2fb described later.

  The isolation element 3d receives the PWM control signal S15 from the amplifier 55 of the transmission unit 10, and transmits this signal in an electrically insulated state. The output of the isolation element 3d is branched into four and connected to the input nodes of the first and second receiving units 13a and 13b.

  The first receiving unit 13a has a configuration in which a circuit configuration common to the first receiving unit 13a of FIG. This cascode connection method is the same as in FIG. In FIG. 9, 2ga is a rectifier circuit provided on the high potential side of the drive signal generating rectifier circuit provided in the first receiving unit 13a, and 2gb is a rectifier provided on the low potential side. Circuit.

  Specifically, the rectifier circuit 2ga receives the high-frequency signal S15 branched from the isolation element 3, rectifies the high-frequency signal S15, and supplies it to the drive node of the inverter unit 70a. The ground terminal of the rectifier circuit 2ga is connected to the source of the first drive transistor 5ga provided on the high potential side. In addition, a resistance element 4ga is provided between the gate and the source of the first drive transistor 5ga.

  The rectifier circuit 2gb receives the high-frequency signal S15 branched from the isolation element 3, rectifies the high-frequency signal S15, and supplies it to the drive node of the inverter unit 70b. The ground terminal of the rectifier circuit 2gb is connected to the source of the second drive transistor 5gb provided on the low potential side. In addition, a resistance element 4gb is provided between the gate and the source of the second drive transistor 5gb.

  With this configuration, it is possible to evenly divide the voltage applied between the drain and source of the two drive transistors 5ga and 5gb in the off state of the first and second drive transistors 5ga and 5gb.

  The second receiving unit 13b has a circuit configuration common to the second receiving unit 13b in FIG. 1, and detailed description thereof is omitted here. By adopting the same configuration as that of FIG. 1, it is possible to evenly divide the voltage applied between the drain and source of the first and second drive transistors 5c and 5d in the second receiving unit 13b.

  The operation of the switching device A is also the same as the configuration of FIG. Specifically, in the ON period of the PWM control signal S15, in the first receiving unit 13a, the outputs of the rectifier circuits 2ga and 2gb on both the high potential side and the low potential side are inverted by the inverter units 70a and 70b, respectively. The Vgs of the first and second drive transistors 5ga and 5gb are substantially 0 [V] and are turned on. On the other hand, a negative voltage is applied to the gates of the first and second drive transistors 5c and 5d of the second reception unit 13b, and the second reception unit 13b is turned off.

  On the contrary, in the OFF period of the PWM control signal S15, a negative voltage is applied to the gates of the first and second drive transistors 5ga and 5gb in the first receiving unit 13a to turn them off. On the other hand, in the second receiving unit 13b, Vgs of the first and second drive transistors 5c and 5d becomes almost 0 [V] and is turned on.

  The first and second drive transistors 5ga and 5gb and the first and second drive transistors 5c and 5d are alternately turned on and off by repeating the on period and the off period. Then, the voltage of the capacitor 9 serving as the output voltage of the gate drive circuit 1 is alternately switched by the drive transistors 5 a and 5 b and applied to the gate of the semiconductor switching element 60.

  As described above, according to the present embodiment, as in the first embodiment, the voltage between the drain and source of the first and second drive transistors 5ga and 5gb of the first receiving unit 13a and the second receiving unit 13b The voltage between the drain and source of the first and second drive transistors 5c and 5d can be made almost half of the output voltage Vo. This makes it possible to use a semiconductor process with a low breakdown voltage.

  Further, since the number of isolation elements 3 having a relatively large size can be reduced, the size of the transmission unit 10 and the isolation unit 11 can be reduced, and the size of the entire gate drive circuit 1 can be reduced. can do.

  In the above embodiment, the power supply unit 7 receives power from the inverter units 70a and 70b of the first receiving unit 13a. However, the present invention is not limited to this, and the inverter unit 70a is externally connected to the gate drive circuit 1. , 70b may be supplied with power.

<Other embodiments>
As described above, the embodiment has been described as an example of the technique disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed. Moreover, it is also possible to make a new embodiment by appropriately combining the components described in the above embodiment and the modifications described below.

  For example, in the first to third embodiments, the drive transistor 5 is a so-called normally-on type FET in which Vgs is 0 [V], the transistor is turned on, Vgs is a negative voltage, and the transistor is turned off. Although an example of using is shown, a configuration using a normally-off type FET or a bipolar transistor is also possible.

  Moreover, in the said 1st-3rd embodiment, although the single shunt type | mold circuit was illustrated as a structure of the rectifier circuit 2 of the receiving unit 13, it is not limited to this. For example, since a positive voltage can be generated by connecting the anode and cathode of the diode in the opposite direction, a rectifier circuit having such a configuration may be applied. Also, other rectification methods such as a voltage doubler type and a bridge type may be applied.

  FIGS. 12A to 12E show other configuration examples of the rectifier circuit 2. FIG. 12 illustrates a circuit that generates a negative potential with respect to the ground terminal in all the circuits. A positive potential can be generated by reversing the direction of the diode.

  In the above embodiment, as the configuration of the rectifier circuit 2, the (a) single shunt type shown in FIG. 12 (a) is used, but is not limited to this. For example, from different circuit topologies such as a single series type shown in FIG. 12B, a double voltage type shown in FIG. 12C, a double current type shown in FIG. 12D, and a bridge type shown in FIG. It is also possible to configure using a rectifier circuit.

  Further, with respect to the L and C elements other than the diode, in order to maximize the voltage generated in the rectifier circuit 2 with respect to the frequency of the input signal, a new element is added to the circuit topology shown in FIG. Alternatively, a part may be deleted.

  The bridge type in FIG. 12E shows a circuit in the case of a single-end type signal input, and the lower left capacitive element can be eliminated. When the input signal is a differential signal, the installation connection portion may be used as one of the differential signal input terminals.

  In the example of FIG. 12, the topology of each rectifier circuit is shown as a lumped constant element, but it is also possible to obtain the same effect by using a distributed constant element such as a microstrip line.

  In addition, as shown in FIG. 2, when the inductor portion is constituted by a spiral inductor, the chip layout area can be reduced by arranging the inductor portions so as to overlap each other.

  In the first to third embodiments, an example in which an electromagnetic resonance coupler is used as the isolation element 3 has been described. However, a capacitive element, a transformer, or the like may be used.

  In addition to the configuration of FIG. 1, a resistor may be inserted between the drain and source of each drive transistor 5 in order to stabilize the potential of the drive transistor 5.

  The gate drive circuit according to the present disclosure can be used for an inverter, a power converter, a power system, and the like.

1 Gate Drive Circuit 2, 2a, 2b, 2c, 2d, 2g, 2ga, 2gb, 2h Rectifier Circuit 2f Rectifier Circuit (Second Power Supply Rectifier Circuit)
3, 3a, 3b, 3d Isolation element 3 Power supply isolation element 5 Drive transistor 5a, 5ga, 5c First drive transistor (inverted drive transistor)
5b, 5gb, 5d Second drive transistor 10 Transmitter 20 Power supply rectifier circuit (first power supply rectifier circuit)
60 Semiconductor switching element 70 Inverter part S11 1st PWM control signal (high frequency power signal)
S12 Second PWM control signal (high frequency power signal)
S15 PWM control signal (high frequency power signal)

Claims (11)

A gate drive circuit for driving a semiconductor switching element,
A transmitter for generating a power signal that is a basis for gate driving of the semiconductor switching element;
An isolation element for transmitting the power signal in an electrically insulated state;
A plurality of rectifier circuits connected in parallel to the output of the isolation element;
A plurality of drive transistors having a gate receiving an output of the rectifier circuit and a source connected to a ground terminal of the rectifier circuit;
The gate driving circuit, wherein the plurality of driving transistors are cascode-connected to drive a gate of the semiconductor switching element. The gate drive circuit according to claim 1,
An inverter unit is provided between a first rectifier circuit that is at least one of the plurality of rectifier circuits and a first drive transistor connected to an output of the first rectifier circuit. Gate drive circuit. The gate drive circuit according to claim 2,
The plurality of rectifier circuits include the first rectifier circuit and a plurality of second rectifier circuits,
The plurality of driving transistors include the first driving transistor and a plurality of second driving transistors whose gates receive the output of the second rectifier circuit and whose sources are connected to the ground terminal of the second rectifier circuit,
A first drive unit including the first rectifier circuit, the inverter unit, and the first drive transistor connected to each other; and a second drive unit including the second rectifier circuit and the second drive transistor connected to each other. A gate drive circuit comprising a plurality of first drive units and a plurality of first drive units and a plurality of second drive units connected in cascode. The gate drive circuit according to claim 2 or 3,
The transmission unit generates a high frequency power signal as the power signal,
The gate drive circuit, wherein the high-frequency power signal is supplied as a pulse signal to the drive transistor through the isolation element and the rectifier circuit. In the gate drive circuit according to any one of claims 2 to 4,
The isolation element includes a power supply isolation element,
A power rectifier circuit that receives the power signal generated by the transmitter via the power isolation element;
An output of the power supply rectifier circuit is used as a power supply for the inverter unit, and a ground terminal of the power supply rectifier circuit and a corresponding ground terminal of the inverter unit are connected. The gate drive circuit according to claim 5, wherein
The power supply rectifier circuit includes at least one first power supply rectifier circuit and a second power supply rectifier circuit that generate different voltages.
Using the output of the first power supply rectifier circuit as a power supply for the inverter unit,
An output of the second power supply rectifier circuit is used as an output voltage of the gate drive circuit. The gate drive circuit according to any one of claims 1 to 6,
An output of a part of the plurality of rectifier circuits has a positive polarity, and an output of the remaining rectifier circuit has a negative polarity. In the gate drive circuit according to any one of claims 1 to 7,
A gate driving circuit, wherein resistance elements having different resistance values are provided between a gate and a source of each driving transistor. The gate drive circuit according to any one of claims 1 to 8,
The rectifier circuit includes an inductor formed by a spiral pattern wiring,
A gate driving circuit, wherein inductors of different rectifier circuits are arranged to overlap each other. The gate drive circuit according to any one of claims 1 to 9,
The gate drive circuit, wherein the isolation element is an electromagnetic resonance coupling element. A gate drive circuit according to any one of claims 1 to 10,
A switching device comprising: a semiconductor switching element driven by the gate drive circuit.

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