JP2019176176A - Multilayer ceramic capacitor - Google Patents

Abstract

To secure both moisture resistance and capacitance.SOLUTION: A multilayer ceramic capacitor 10 includes a laminate 14, an external dielectric 11, a first external electrode 12, and a second external electrode 13. In the laminate, a first internal electrode layer and a second internal electrode layer are alternately stacked, via an internal dielectric 16 formed of a ceramic dielectric containing sintering aids such as manganese or magnesium. The laminate has a first surface 14a, a second surface 14b, a third surface 14c, a fourth surface 14d, a fifth surface 14e, and a sixth surface 14f. An external dielectric is formed of a ceramic dielectric containing more sintering aid than the internal dielectric, and covers the first surface, the second surface, the third surface and the fourth surface of the laminate. The first external electrode covers the fifth surface and is electrically connected to the first internal electrode layer. The second external electrode covers the sixth surface and is electrically connected to the second internal electrode layer.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a multilayer ceramic capacitor that can be reduced in size and performance, and a method for manufacturing the same.

  In recent years, with the downsizing of electronic devices such as smartphones and mobile phones, there is an increasing demand for downsizing and increasing the capacity of, for example, multilayer ceramic capacitors as electronic components mounted on electronic devices.

  In such a multilayer ceramic capacitor, how to ensure the moisture resistance of the ceramic layer becomes a problem. Therefore, conventionally, in order to ensure moisture resistance, an additive that enhances sinterability is added to the ceramic material, or the diameter of the dielectric particles constituting the ceramic layer is reduced to control the sinterability of the ceramic layer. , And densification (for example, refer to Patent Documents 1 to 4).

Japanese Patent No. 4135443 JP 2012-227260 A JP 2003-017356 A JP 2010-103566 A

  In order to promote the densification of the ceramic layer, it is effective to add a sintering aid such as manganese or magnesium. However, the addition of a sintering aid reduces the dielectric constant of the dielectric, making it difficult to ensure the desired capacitance. For this reason, it has been very difficult to achieve both moisture resistance and capacitance.

  In view of the circumstances as described above, an object of the present invention is to provide a multilayer ceramic capacitor capable of achieving both moisture resistance and securing of capacitance and a method for manufacturing the same.

In order to achieve the above object, a multilayer ceramic capacitor according to one embodiment of the present invention includes a multilayer body, an external dielectric, a first external electrode, and a second external electrode.
In the laminated body, the first internal electrode layer and the second internal electrode layer are alternately laminated through an internal dielectric formed of a ceramic dielectric containing a sintering aid such as manganese or magnesium. , A first surface that is a surface in the stacking direction, a second surface that is a surface opposite to the first surface, and the first interior that is orthogonal to the first surface and the second surface. A third surface from which the electrode layer and the second internal electrode layer are drawn, and a surface opposite to the third surface, and the first internal electrode layer and the second internal electrode layer are drawn out. A fourth surface that is perpendicular to the first surface, the second surface, the third surface, and the fourth surface and from which the first internal electrode is drawn out And a sixth surface which is the surface opposite to the fifth surface and from which the second internal electrode is drawn out.
The external dielectric is formed of a ceramic dielectric containing more sintering aid than the internal dielectric, and the first surface, the second surface, the third surface, and the first surface of the laminate. 4 side is covered.
The first external electrode covers the fifth surface and is electrically connected to the first internal electrode layer.
The second external electrode covers the sixth surface and is electrically connected to the second internal electrode layer.
Of the external dielectric, at least a portion covering the third surface and the fourth surface is composed of an outer layer portion and an intermediate portion provided between the outer layer portion and the laminated body. The outer layer portion has a higher concentration of sintering aid than the intermediate portion.

  As the content of manganese or magnesium, which is a sintering aid, decreases as the content increases, securing the capacitance is facilitated by reducing the content of the sintering aid in the internal dielectric. On the other hand, a decrease in the amount of sintering aid causes a decrease in sinterability, but at this time, even if the amount of sintering aid in the internal dielectric is small, the external dielectric has more sintering aid than the internal dielectric. By containing, the sinterability of the external dielectric improves more than the sinterability of the internal dielectric, and a multilayer ceramic capacitor having a dense surface can be realized. This densely sintered external dielectric prevents moisture from entering the internal dielectric region from the external atmosphere.

  On the other hand, since a concentration difference of the sintering aid occurs between the internal dielectric and the external dielectric, there is a possibility that the sintering aid derived from the external dielectric may diffuse into the internal dielectric. In particular, the third surface and the fourth surface are likely to be diffused because the inner dielectric and the outer dielectric are in direct contact with each other. Therefore, as shown in the above configuration, the outer dielectric is composed of the outer layer portion and the intermediate portion provided between the laminate and the outer layer portion, so that the outer layer portion and the layer having a high concentration of the sintering aid are laminated. It is possible to take a distance from the body. Therefore, the sintering aid derived from the outer layer portion diffuses to the intermediate portion without being directly diffused and mixed into the inner dielectric constituting the laminate. Therefore, not only a decrease in capacitance due to the diffusion and mixing of the sintering aid into the internal dielectric is suppressed, but also a decrease in denseness is suppressed. Therefore, according to the multilayer ceramic capacitor, it is possible to ensure moisture resistance and capacitance.

  The sintering aid contained in the intermediate portion is increased in concentration by a first concentration gradient from the laminate side toward the outer layer portion side, and the sintering aid contained in the outer layer portion is the intermediate portion. The concentration may be increased by a second concentration gradient that is smaller than the first concentration gradient from the portion side toward the surface of the outer layer portion.

  The inner dielectric and the outer dielectric may contain at least one of silicon and vanadium.

  The entire outer dielectric may be composed of the outer layer portion and the intermediate portion.

  The external dielectric includes a cover portion on the first surface and the second surface, a side margin portion on the third surface and the fourth surface, and the cover portion and the side margin portion. The Vickers hardness of the cover part may be 1.00 or more with respect to the Vickers hardness of the side margin part.

  By designing the Vickers hardness of the cover part and the side margin part as described above, the denseness of the external dielectric composed of the cover part and the side margin part is improved, so that the moisture resistance of the multilayer ceramic capacitor is ensured. It becomes possible.

  The external dielectric may contain more manganese or magnesium in the range of 0.3 to 4.5 mol relative to 100 mol of Ti (titanium) than the internal dielectric.

  When the external dielectric contains more Mn (manganese) or Mg (magnesium) than the internal dielectric in the range of 0.3 mol to 4.5 mol with respect to 100 mol of Ti, the connection between the internal electrode layer and the internal dielectric is achieved. Not only is the difference in shrinkage behavior alleviated, but also a decrease in capacitance due to diffusion of Mn (manganese) or Mg (magnesium) into the internal dielectric is suppressed.

  The internal dielectric and the external dielectric contain silicon and boron, and the external dielectric contains more silicon in a range of 2.8 mol or less with respect to 100 mol of Ti than the internal dielectric, and 0 with respect to 100 mol of Ti. A large amount of boron may be contained within a range of 0.8 mol or less.

  The outer dielectric contains more silicon in the range of 2.8 mol or less with respect to 100 mol of Ti than the inner dielectric, and contains more boron in the range of 0.8 mol or less with respect to 100 mol of Ti, thereby configuring the outer dielectric. Since the grain growth of the dielectric particles is suppressed, a decrease in strength due to the fact that the product surface is not completely densified is suppressed.

In order to achieve the above object, a method for manufacturing a multilayer ceramic capacitor according to an aspect of the present invention includes:
An internal dielectric containing a sintering aid and internal electrode layers are alternately laminated to form a first laminate,
On the first surface of the first laminate and the second surface opposite to the first surface, a first inner layer having a concentration of sintering aid equal to or lower than the inner dielectric is laminated, On the first inner layer, a second outer layer is formed by laminating a first outer layer in which the concentration of the sintering aid is higher than that of the inner dielectric,
The second laminated body is cut into a chip size, a second inner layer made of the same material as the first inner layer is laminated on both sides of the second laminated body of the chip size, and the second Forming a third laminate by laminating a second outer layer made of the same material as the first outer layer on the inner layer;
An outer dielectric comprising a middle portion having a higher sintering aid concentration than the inner dielectric and an outer layer portion having a higher sintering aid concentration than the middle portion by firing the third laminate. Form.

  Since the concentration of the sintering aid in the first inner layer and the second inner layer is lower than the inner dielectric and lower than the first outer layer and the second outer layer, the third laminate is fired. The sintering aid derived from the inner dielectric, the first outer layer and the second outer layer diffuses and penetrates into the first inner layer and the second inner layer. As a result, not only a decrease in capacitance due to diffusion and mixing of the sintering aid into the internal dielectric is suppressed, but also a decrease in denseness can be suppressed.

In order to achieve the above object, another method for manufacturing a multilayer ceramic capacitor according to an aspect of the present invention includes:
The internal dielectric containing the sintering aid, the internal electrode layer, the first relaxation layer having a concentration of the sintering aid equal to or lower than that of the internal dielectric, and the second concentration of the sintering aid being higher than that of the internal dielectric. A plurality of first inner layers made of relaxation layers are stacked to form a first stacked body;
A second inner layer made of the same material as the first relaxation layer is stacked on the first surface of the first stacked body and the second surface opposite to the first surface, An outer layer made of the same material as the second relaxation layer is laminated on the inner layer of 2 to form a second laminate,
The second laminate is cut into a chip size, the second laminate having a chip size is fired, and an intermediate portion having a higher concentration of sintering aid than the internal dielectric, and the intermediate portion An external dielectric including an outer layer portion having a high concentration of sintering aid is formed.

  As described above, according to the present invention, it is possible to provide a multilayer ceramic capacitor capable of ensuring moisture resistance and capacitance and a method for manufacturing the same.

1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. It is sectional drawing in AA of FIG. It is sectional drawing in BB of FIG. FIG. 3 is a schematic diagram showing the external dielectric shown in FIG. 2 for each element. It is a figure which shows the concentration curve (concentration gradient) of Mn (manganese) contained in the internal dielectric and the external dielectric according to the same embodiment. It is a schematic diagram which shows the manufacturing process of the same multilayer ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the same multilayer ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the same multilayer ceramic capacitor. It is a figure which shows the density | concentration change of the sintering auxiliary agent which concerns on the 3rd laminated body of the same embodiment. It is a density | concentration curve of the sintering aid which concerns on the 4th laminated body of the embodiment. It is a schematic diagram which shows the other manufacturing process of the same multilayer ceramic capacitor. It is a schematic diagram which shows the other manufacturing process of the same multilayer ceramic capacitor. It is a schematic diagram which shows the other manufacturing process of the same multilayer ceramic capacitor. It is a perspective view of the multilayer ceramic capacitor which concerns on the 2nd Embodiment of this invention. It is sectional drawing in AA of FIG. It is a table | surface which shows the result of the characteristic test which concerns on Example 1 of this invention. It is a table | surface which shows the result of the characteristic test which concerns on Example 2 of this invention. It is a table | surface which shows the result of the characteristic test which concerns on Example 2 of this invention. It is a table | surface which shows the result of the characteristic test which concerns on Example 2 of this invention. The ratio of the sintering aid contained in the inner dielectric and the outer dielectric of the multilayer ceramic capacitors according to Examples 3 and 4 of the present invention and Comparative Examples 1 to 3 and the results of the characteristic test of each multilayer ceramic capacitor are shown. It is a table.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, embodiment described below is an example and is not limited to this.

<First Embodiment>
[Overall structure of multilayer ceramic capacitor]
FIG. 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG. In the following drawings, the X, Y, and Z axis directions indicate the three axis directions orthogonal to each other. In this embodiment, the X axis direction is the length direction of the multilayer ceramic capacitor, and the Y axis direction is the width direction. The Z-axis direction corresponds to the height direction.

  As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 10 of this embodiment includes an external dielectric 11, a first external electrode 12, a second external electrode 13, and a multilayer body 14.

  As will be described later, the multilayer body 14 is configured by alternately laminating internal electrode layers and internal dielectrics in the Z-axis direction. The first external electrode 12 and the second external electrode 13 are formed on terminal surfaces facing each other in the X-axis direction of the multilayer body 14 and are electrically connected to the internal electrode layers of the multilayer body 14. The external dielectric 11 is formed on the outer periphery of the multilayer body 14 as shown in FIG. Specifically, as illustrated in FIG. 2, the surfaces of the stacked body 14 that face each other in the Y-axis direction and the surfaces that face each other in the Z-axis direction are covered. Details of each part of the multilayer ceramic capacitor 10 will be described below.

(Laminate)
As shown in FIG. 2, the laminated body 14 includes a first surface 14a, a second surface 14b opposite to the first surface 14a, and a first surface 14a orthogonal to the first surface 14a and the second surface 14b. 3 surface 14c and a fourth surface 14d opposite to the third surface 14c, the first surface 14a, the second surface 14b, the third surface 14c and the fourth surface 14d are external. The dielectric 11 is covered.

  As shown in FIG. 3, the multilayer body 14 includes a first internal electrode layer 15, a second internal electrode layer 17, and an internal dielectric 16. A first internal electrode layer 15 and a second internal electrode layer 17 are drawn out from the third surface 14 c and the fourth surface 14 d of the multilayer body 14.

  As illustrated in FIG. 3, the multilayer body 14 is configured by sequentially laminating a first internal electrode layer 15, an internal dielectric 16, and a second internal electrode layer 17 in the Z-axis direction, and the first internal electrode layer 15. And the second internal electrode layer 17 have an internal structure arranged so as to face each other with the internal dielectric 16 interposed therebetween. In addition, the number of layers of the first internal electrode layer 15 and the second internal electrode layer 17 is not limited to the illustrated example, and each layer may be composed of several tens of layers.

  Further, as shown in FIG. 3, the laminate 14 includes a first surface 14a, a second surface 14b, a third surface 14c, a fifth surface 14e orthogonal to the fourth surface 14d, and a fifth surface 14e. A sixth surface 14f opposite to the surface 14e is provided. A first internal electrode layer 15 is drawn out on the fifth surface 14e, and a first external electrode 12 is provided so as to be electrically connected to the first internal electrode layer 15, and a sixth surface 14f is provided on the sixth surface 14f. The second internal electrode layer 17 is drawn out, and the second external electrode 13 is provided so as to be electrically connected to the second internal electrode layer 17.

  The 1st internal electrode layer 15 and the 2nd internal electrode layer 17 are comprised by the rectangular-shaped metal thin film which sintered the electrically conductive paste containing base metal powders, such as Ni and Cu, for example.

The internal dielectric 16 is formed with dielectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ) as a main component. It is composed of a sintered body of rectangular green sheets and has an insulating property. In the present embodiment, the internal dielectric 16 is composed of a slurry whose main component is a barium titanate (BaTiO ₃ ) -based ceramic material.

(External dielectric)
As shown in FIG. 2, the external dielectric 11 according to the present embodiment includes an intermediate portion 18 and an outer layer portion 19.

  As shown in FIG. 2, the intermediate portion 18 covers the first surface 14 a, the second surface 14 b, the third surface 14 c, and the fourth surface 14 d of the stacked body 14, and the stacked body 14 and the outer layer portion 19. It intervenes between. The thickness of the intermediate portion 18 is appropriately changed according to the chip size, and is preferably 2 μm or more, for example.

The intermediate portion 18 is formed using, for example, dielectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ) as a main component. It is a sintered body and has insulating properties. In the present embodiment, the intermediate portion 18 is composed of a slurry containing a barium titanate (BaTiO ₃ ) ceramic material as a main component, like the internal dielectric 16.

  As shown in FIG. 2, the outer layer portion 19 covers the outer side of the intermediate portion 18 and constitutes the outer wall of the multilayer ceramic capacitor 10. The thickness of the outer layer portion 19 is appropriately set according to the chip size, and is preferably 10 μm or more, for example, and more preferably 20 μm or more.

The outer layer portion 19 is formed with dielectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ) as a main component, for example. It is composed of a sintered body and has insulating properties. In the present embodiment, the outer layer portion 19 is made of a slurry containing a barium titanate (BaTiO ₃ ) -based ceramic material as a main component, like the inner dielectric 16 and the intermediate portion 18.

  FIG. 4 is a schematic diagram showing the external dielectric 11 shown in FIG. 2 for each element. As shown in FIG. 4, the external dielectric 11 according to this embodiment includes a side margin portion 20 and a cover portion 21.

  As shown in FIG. 4, the side margin portion 20 includes a first coating layer 11c that covers the third surface 14c and the fourth surface 14d of the stacked body 14, and a second coating that is stacked on the first coating layer 11c. Layer 11d.

  As shown in FIG. 4, the cover portion 21 includes a third coating layer 11 e that covers a plane parallel to the Y-axis direction of the first surface 14 a, the second surface 14 b, and the first coating layer 11 c of the stacked body 14. The fourth coating layer 11f covers the plane parallel to the Y-axis direction of the third coating layer 11e and the second coating layer 11d. Here, the intermediate portion 18 is composed of the first covering layer 11c and the third covering layer 11e, and the outer layer portion 19 is composed of the second covering layer 11d and the fourth covering layer 11f.

(External electrode)
The first external electrode 12 is an external terminal of the multilayer ceramic capacitor 10. As shown in FIG. 3, the first external electrode 12 is provided on the fifth surface 14 e and partially covers the external dielectric 11. As shown in FIG. 3, the first external electrode 12 is electrically connected to the first internal electrode layer 15 through the first lead-out end portion 15a.

  The second external electrode 13 is an external terminal of the multilayer ceramic capacitor 10. As shown in FIG. 3, the second external electrode 13 is provided on the sixth surface 14 f and partially covers the external dielectric 11. As shown in FIG. 3, the second external electrode 13 is electrically connected to the second internal electrode layer 17 via the second lead-out end portion 17a.

  The first external electrode 12 and the second external electrode 13 are conductive materials containing base metal powder such as Ni, Cu, Cr, Ag, Pd, Fe, Sn, Pb, Pt, Ir, Rh, Ru, Al, Ti, etc. It is composed of a metal thin film obtained by sintering a paste. The surfaces of the first external electrode 12 and the second external electrode 13 may be subjected to solder plating in order to improve solder wettability when mounted on a circuit board.

[Sintering aid]
The inner dielectric 16, the intermediate portion 18, and the outer layer portion 19 of the present embodiment contain a sintering aid used for promoting and stabilizing the sintering in manufacturing the multilayer ceramic capacitor 10. The Here, the sintering aid contains at least Mn (manganese) or Mg (magnesium). The intermediate portion 18 according to the present embodiment contains more sintering aid than the internal dielectric 16, and the outer layer portion 19 contains more sintering aid than the intermediate portion 18.

  In addition to Mn (manganese) and Mg (magnesium), sintering aids include Si (silicon), B (boron), Ho (holmium), Ca (calcium), V (vanadium) and oxides thereof, Li A glass containing Si (silicon) as a main component and containing any of (lithium), K (potassium), Na (sodium), and B (boron) can be included. Moreover, these may be individual and multiple types may be mixed.

  FIG. 5 is a schematic diagram of the main part of the EPMA (Electron Probe Micro Analyzer) spectrum of Mn (manganese) contained in the inner dielectric 16 and the outer dielectric 11 of the present embodiment. The concentration curve (concentration gradient) of Mn (manganese) contained in the body 11 is shown.

  Here, in FIG. 5, a curve in the region La is a concentration curve of Mn (manganese) in the region L1 related to the end portion of the multilayer body 14 (internal dielectric 16) shown in FIG. The curve in the region Lb is a concentration curve of Mn (manganese) in the region L2 related to the intermediate portion 18 shown in FIG. 2, and the curve in the region Lc is the region L3 related to the outer layer portion 19 shown in FIG. It is a density | concentration curve of Mn (manganese) in the inside.

  As shown in FIG. 5, the multilayer ceramic capacitor 10 of the present embodiment has a configuration in which the concentration of Mn increases from the multilayer body 14 toward the outer layer portion 19. Specifically, as shown in FIG. 5, the concentration of manganese contained in the region L2 of the intermediate portion 18 increases with a first concentration gradient from the laminated body 14 side toward the outer layer portion 19 side, and the outer layer The concentration of manganese contained in the region L3 of the part 19 increases from the intermediate part 18 side toward the surface of the outer layer part 19 with a second concentration gradient that is smaller than the first concentration gradient.

  Here, the outer dielectric 11 preferably contains more Mn (manganese) or Mg (magnesium) than the inner dielectric 16 in the range of 0.30 mol to 4.5 mol with respect to 100 mol of Ti. If it is less than 0.30 mol, the surface of the outer layer portion 19 cannot be sufficiently densified, and if it exceeds 4.5 mol, Mn (manganese) or Mg (magnesium) diffuses into the internal dielectric 16, and the capacitance This is because a decrease in the above becomes apparent.

  The outer dielectric 11 preferably contains more Si (silicon) than the inner dielectric 16 in the range of 0.00 mol to 2.8 mol with respect to 100 mol of Ti. When it exceeds 2.8 mol, the dielectric particles constituting the external dielectric 11 are likely to grow, and the product surface cannot be sufficiently densified, and the strength may not be ensured.

  Furthermore, the outer dielectric 11 preferably contains more B (boron) than the inner dielectric 16 in the range of 0.00 mol to 0.8 mol with respect to 100 mol of Ti. When the amount exceeds 0.8 mol, the dielectric particles constituting the external dielectric 11 are likely to grow and the product surface cannot be sufficiently densified, and the strength may not be ensured.

  By making Mn (manganese), Mg (magnesium), Si (silicon), and B (boron) within the above ranges as sintering aids, the internal electrode layer and the internal dielectric 16 are uniformly shrunk during firing. (Sintered simultaneously). As a result, it is possible to suppress moisture resistance failure due to the difference in sintering shrinkage behavior between the internal electrode layer and the internal dielectric 16.

  For example, in a thin-layer product in which the thickness of the internal dielectric 16 is less than 1 μm, such as a multilayer ceramic capacitor having a 0603 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm), the internal dielectric 16, oversintering is suppressed, and this makes it possible to suppress a decrease in dielectric constant and secure a desired capacitance.

  Furthermore, since the sintering aid contains more of the outer dielectric 11 than the inner dielectric 16, the sinterability of the outer dielectric 11 can be increased more than the sinterability of the inner dielectric 16. it can. Thereby, since oversintering of the internal dielectric 16 is suppressed, a decrease in dielectric constant can be suppressed, and a capacitance can be ensured.

  Further, the multilayer ceramic capacitor 10 of the present embodiment is configured such that the external dielectric 11 contains more sintering aid than the internal dielectric 16, so that the external dielectric 11 is more than the internal dielectric 16. , Hardness increases. Thereby, the surface of the external dielectric 11 can be sufficiently densified, and the moisture resistance of the multilayer ceramic capacitor 10 can be ensured.

  Specifically, when the hardness index of the surface of the external dielectric 11 is Vickers hardness, the Vickers hardness of the surface 20a of the side margin part 20 and the surface 21a of the cover part 21 shown in FIG. The ratio of the Vickers hardness of the surface 21a to the Vickers hardness of the surface 20a is configured to be 1.00 or more. With such a configuration, when mounted on a circuit board, even if stress due to the deflection of the board is applied to the multilayer ceramic capacitor, cracks can be hardly generated.

  The method for adjusting the Vickers hardness of the surface 20a and the surface 21a is not particularly limited. For example, the hardness can be adjusted by adjusting the concentration of the sintering aid contained in the cover portion 21 and the side margin portion 20, the firing conditions, and the like.

  From these facts, according to the present embodiment, when the outer dielectric 11 contains more sintering aid than the inner dielectric 16, the sinterability of the outer dielectric 11 than the sinterability of the inner dielectric 16. Will improve. Therefore, according to the multilayer ceramic capacitor 10 of the present embodiment, both moisture resistance and capacitance securing can be achieved.

[Operation of multilayer ceramic capacitor]
In the multilayer ceramic capacitor 10 of the present embodiment configured as described above, the first external electrode 12 and the second external electrode 13 are soldered to the connection lands on the circuit board, respectively, so that a capacitance element having a predetermined capacity is obtained. Configure.

  Furthermore, according to the present embodiment, since the outer dielectric 11 contains more sintering aid than the inner dielectric 16, the sinterability of the outer dielectric 11 is improved over the sinterability of the inner dielectric 16. Therefore, according to the multilayer ceramic capacitor 10 of the present embodiment, both moisture resistance and capacitance securing can be achieved.

[Manufacturing method of multilayer ceramic capacitor]
(First manufacturing method)
A first manufacturing method of the multilayer ceramic capacitor 10 according to the present embodiment will be described. In addition, the manufacturing method shown below is an example, and the manufacturing method of the multilayer ceramic capacitor 10 is not limited to the method shown below. 6 to 8 are schematic views showing a manufacturing process of the multilayer ceramic capacitor 10.

  FIG. 6A shows an internal dielectric 16 that is a ceramic green sheet formed from a slurry containing a ceramic material as a main component. The thickness of the internal dielectric 16 is not particularly limited, and can be, for example, about several μm.

  As shown in FIG. 6B, a strip-like first internal electrode layer 15 extending in the width direction is printed (laminated) on the internal dielectric 16 by a method such as screen printing. As a result, a pattern of the first internal electrode layer 15 is formed on the internal dielectric 16.

  Subsequently, as shown in FIG. 6C, the internal dielectric 16 is laminated on the first internal electrode layer 15, and the second internal electrode layer 17 is laminated on the internal dielectric 16. And the 1st internal electrode layer 15, the internal dielectric material 16, and the 2nd internal electrode layer 17 are laminated | stacked alternately, and a laminated body is formed. Hereinafter, as illustrated in FIG. 6C, a stacked body in which the first internal electrode layers 15, the internal dielectrics 16, and the second internal electrode layers 17 are alternately stacked is referred to as a first stacked body 30.

  Subsequently, as shown in FIG. 7 (a), the concentration of the sintering aid is lower or equivalent to the ceramic slurry forming the internal dielectric 16 on the front surface 30a and the back surface 30b of the first laminated body 30. The formed first inner layer 18a is laminated. Next, as shown in the figure, a first outer layer 19a formed from a ceramic slurry having a higher sintering aid concentration than the ceramic slurry forming the inner dielectric 16 is laminated on the first inner layer 18a. Hereinafter, a laminated body in which the first inner layer 18 a and the first outer layer 19 a are laminated on the first laminated body 30 is referred to as a second laminated body 40.

  Subsequently, as shown in FIG. 7B, the second stacked body 40 is cut to obtain the chip 50. Next, as shown in FIG. 7C, the second inner layer 18 b is laminated on the first side cut surface 50 a and the second side cut surface 50 b of the chip 50. The second inner layer 18b is formed from a ceramic slurry of the same material as the first inner layer 18a.

  Next, as shown in FIG. 7C, the second outer layer 19b is laminated on the second inner layer 18b. The second outer layer 19b is formed from a ceramic slurry made of the same material as the first outer layer 19a.

  The second inner layer 18b and the second outer layer 19b can be formed by applying or spraying ceramic slurry on the first side cut surface 50a and the second side cut surface 50b. Or later. A stacked body in which the second inner layer 18 b and the second outer layer 19 b are stacked on the chip 50 is referred to as a third stacked body 60.

  Subsequently, the third stacked body 60 is fired at a few hundreds of degrees Celsius in a reducing atmosphere. In the third laminated body 60 after firing, the sintering aid is diffused, and as shown in FIG. 8A, the laminated body 14, the intermediate portion 18, and the outer layer portion 19 are formed. Hereinafter, as shown in FIG. 8A, the chip on which the stacked body 14, the intermediate portion 18, and the outer layer portion 19 are formed is referred to as a fourth stacked body 70.

  Finally, as shown in FIG. 8B, the first external electrode 12 and the second external electrode 13 are formed on the fourth laminate 70, respectively. Typically, the first external electrode 12 and the second external electrode 13 are made of the same kind of material as the first internal electrode layer 15 and the second internal electrode layer 17, for example, a paste body of a base metal material such as Ni. It forms by baking after apply | coating to each edge part containing the surface which opposes the X-axis direction of the laminated body 70. FIG. Thereafter, if necessary, solder plating is applied to the surfaces of the first external electrode 12 and the second external electrode 13. The first external electrode 12 and the second external electrode 13 can also be formed by firing at the same time as the fourth stacked body 70. The multilayer body in which the first external electrode 12 and the second external electrode 13 are formed on the fourth multilayer body 70 corresponds to the multilayer ceramic capacitor 10 as shown in FIG.

[Action of inner layer]
Addition of a sintering aid is effective for promoting densification of the ceramic layer. However, the addition of a sintering aid reduces the dielectric constant of the dielectric, making it difficult to ensure the desired capacitance. In addition, when the auxiliary component of the margin (cover layer, side margin layer) that protects the electrode intersection is increased and sintered, the margin portion is more effective than the dielectric auxiliary component at the electrode intersection that is effective as a capacitor. In some cases, the auxiliary component diffuses from the electrode crossing portion to the electrode crossing portion and the dielectric constant of the dielectric at the electrode crossing portion is lowered. For this reason, it was very difficult to achieve both moisture resistance and capacitance securing.

  On the other hand, the intermediate portion 18 of the present embodiment is mainly composed of a first inner layer 18a and a second inner layer 18b, and the outer layer portion 19 is mainly composed of a first outer layer 19a and a second outer layer 19b. Is done. Here, in the third stacked body 60 immediately before the intermediate portion 18 and the outer layer portion 19 are formed, the first outer layer 19 a and the second outer layer 19 b are configured to be spaced from the inner dielectric 16.

  Specifically, as shown in FIG. 7C, the first inner layer 18a is interposed between the first outer layer 19a and the inner dielectric 16, and the second outer layer 19b and the inner dielectric 16 are separated. The second inner layer 18b is interposed therebetween.

  Here, since the first inner layer 18a and the second inner layer 18b have a sintering aid concentration of the inner dielectric 16 or lower and lower than the first outer layer 19a and the second outer layer 19b, the third laminated body. When firing 60, the sintering aid derived from the inner dielectric 16, the first outer layer 19a and the second outer layer 19b diffuses and penetrates into the first inner layer 18a and the second inner layer 18b. On the other hand, the first inner layer 18a and the second inner layer 18b are interposed between the first outer layer 19a and the inner dielectric 16, and between the second outer layer 19b and the inner dielectric 16, respectively. Therefore, the first inner layer 18 a and the second inner layer 18 b function as a buffer layer that suppresses the sintering aid derived from the first outer layer 19 a and the second outer layer 19 b from entering the inner dielectric 16.

  This not only suppresses a decrease in capacitance due to diffusion and mixing of the sintering aid into the internal dielectric 16, but also suppresses a decrease in denseness of the intermediate portion 18 and the outer layer portion 19. . Therefore, the multilayer ceramic capacitor 10 manufactured by the above-described method ensures the desired capacitance and moisture resistance at the same time.

[Concentration change of sintering aid]
FIG. 9 is a diagram showing a change in the concentration of the sintering aid according to the third laminate 60, and FIG. 10 is a concentration curve of the sintering aid according to the fourth laminate 70. In these drawings, the curves in the regions Ld and Lg are the regions L4 (see FIGS. 7C and 8A) of the third stacked body 60 and the fourth stacked body 70, respectively. The same applies to L6.), And the curves in the regions Le and Lh are concentration curves in the region L5 of the third stacked body 60 and the fourth stacked body 70, respectively. The curves in the regions Lf and Li are curves in the region L6 of the third stacked body 60 and the fourth stacked body 70, respectively.

  In the third laminated body 60 after firing, the sintering aid diffuses as described above. At this time, the sintering aid in the regions L4 and L6 of the third stacked body 60 diffuses and enters the region L5. Thereby, the density | concentration of the sintering aid in the area | region L4 and the area | region L6 reduces, and the density | concentration of the sintering aid in the area | region L5 increases. Thereby, the sintering aid in the region L4 to the region L6 of the third stacked body 60 temporarily forms a concentration curve as shown in FIG. In addition, the dotted line in the area | regions Ld-Lf shown in FIG. 9 shows the density | concentration of the sintering aid in the area | regions L4-L6 which concern on the 3rd laminated body 60 before baking, respectively.

  As described above, the third laminated body 60 after the diffusion of the sintering aid is formed with the intermediate portion 18 and the outer layer portion 19 to form the fourth laminated body 70. Here, the sintering aid in the region L4 to the region L6 of the fourth laminated body 70 forms a concentration curve as shown in FIG. The region L4 of the fourth stacked body 70 is a region related to the end portion of the stacked body 14, and the region L5 is a region related to the intermediate portion 18. The region L6 is a region related to the outer layer portion 19.

  That is, when the fourth laminated body 70 having the intermediate portion 18 and the outer layer portion 19 is formed by firing the third laminated body 60, the sintering aid contained in the regions L4 to L6 of each laminated body is From the straight line shown in FIG. 9, the concentration curve shown in the same figure is formed. Then, finally, a concentration curve in which the concentration of the sintering aid increases with a predetermined gradient is formed from the end of the laminated body 14 toward the outer layer portion 19 as shown in FIG. Thus, the first inner layer 18a and the second inner layer 18b function as a buffer layer that suppresses the sintering aid derived from the first outer layer 19a and the second outer layer 19b from entering the inner dielectric 16. To do.

(Second manufacturing method)
The multilayer ceramic capacitor 10 according to the present embodiment can be manufactured by a method different from the first manufacturing method described above. FIGS. 11 to 13 are schematic views showing another manufacturing process of the multilayer ceramic capacitor 10.

  FIG. 11A shows an internal dielectric 16 that is a ceramic green sheet formed from a slurry containing a ceramic material as a main component. The thickness of the internal dielectric 16 is not particularly limited, and can be, for example, about several μm.

  As shown in FIG. 11B, a plurality of strip-shaped first internal electrode layers 15 are printed on the internal dielectric 16 by a method such as screen printing, spaced apart from each other in the Y-axis direction. As a result, a pattern of the first internal electrode layer 15 is formed on the internal dielectric 16. The width direction of each first internal electrode layer 15 is formed parallel to the Y-axis direction, and the length direction thereof is formed parallel to the X-axis direction.

  Next, as shown in FIG. 11C, a plurality of first relaxing layers 18 c having a predetermined width, which are ceramic green sheets, are formed on the internal dielectric 16 in the width direction (Y-axis direction) of each first internal electrode layer 15. Laminate each so as to be adjacent to both sides. The first relaxing layer 18 c is formed from a ceramic slurry having a sintering aid concentration lower than or equivalent to that of the ceramic slurry forming the internal dielectric 16.

  Subsequently, as shown in FIG. 12A, a plurality of second relaxing layers 19c, which are ceramic green sheets, are laminated on the internal dielectric 16 next to each first relaxing layer 18c. The second relaxing layer 19 c is formed from a ceramic slurry having a higher concentration of sintering aid than the ceramic slurry forming the internal dielectric 16. The surface of the internal dielectric 16 is covered with the first internal electrode layer 15, the first relaxation layer 18c, and the second relaxation layer 19c. Hereinafter, as shown in FIG. 12A, the internal dielectric 16, the first internal electrode layer 15, the first relaxation layer 18 c and the second relaxation layer 19 c are referred to as a third internal layer 22. Similarly, the internal dielectric 16, the second internal electrode layer 17, the first relaxation layer 18 c and the second relaxation layer 19 c are referred to as a fourth internal layer 23.

  Subsequently, as shown in FIG. 12B, the fourth inner layer 23 is laminated on the third inner layer 22. Next, as illustrated in FIG. 12C, the third inner layer 22 and the fourth inner layer 23 are alternately stacked to form a stacked body. Hereinafter, as illustrated in FIG. 12C, a stacked body in which the third inner layers 22 and the fourth inner layers 23 are alternately stacked is referred to as a fifth stacked body 80.

  Subsequently, as illustrated in FIG. 13A, the fifth inner layer 18 d made of the same material as the first relaxing layer 18 c is stacked on the entire surface 80 a and the back surface 80 b of the fifth stacked body 80. Next, as shown in the figure, a third outer layer 19d made of the same material as the second relaxing layer 19c is laminated on the fifth inner layer 18d. Hereinafter, as illustrated in FIG. 13A, a stacked body in which the fifth inner layer 18 d and the third outer layer 19 d are stacked on the fifth stacked body 80 is referred to as a sixth stacked body 90.

  Subsequently, as illustrated in FIG. 13B, the sixth stacked body 90 is cut to obtain the chip 100. At this time, the sixth stacked body 90 is cut along a dotted line P passing through the center in the Y-axis direction (width direction) of the second relaxing layer 19c shown in FIG.

  Next, the chip 100 is fired at a few hundreds of degrees Celsius in a reducing atmosphere. After firing, the sintering aid diffuses to form the intermediate portion 18 and the outer layer portion 19, and a fourth laminate 70 shown in FIG. 8A is obtained. Finally, the first external electrode 12 and the second external electrode 13 are formed by the same method as described above, and the multilayer ceramic capacitor 10 is obtained. That is, even if this method is used, the multilayer ceramic capacitor 10 having the intermediate portion 18 (having a buffer function) shown in FIG. 2 can be obtained as in the first manufacturing method. That is, the same effect as the above-mentioned 1st manufacturing method can be acquired also by the said method (2nd manufacturing method).

<Second Embodiment>
FIG. 14 is a perspective view of the multilayer ceramic capacitor 200 of the present embodiment, and FIG. 15 is a cross-sectional view taken along line AA of FIG. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.

  As shown in FIGS. 14 and 15, the multilayer ceramic capacitor 200 according to the present embodiment includes a first external electrode 12, a second external electrode 13, a multilayer body 14, and an external dielectric 110. The 1st external electrode 12, the 2nd external electrode 13, and the laminated body 14 have the structure similar to the above-mentioned 1st Embodiment.

  Differences from the first embodiment described above are as follows. That is, in the first embodiment, the cover portion 21 of the outer dielectric 11 is composed of the third coating layer 11e and the fourth coating layer 11f (see FIG. 4). On the other hand, in the multilayer ceramic capacitor 200 of the present embodiment, as shown in FIG. 15, the cover part 210 constituting the external dielectric 110 is composed of a single layer and is composed of the same material as the second coating layer 11d. Is done. That is, the multilayer ceramic capacitor 200 is configured such that the first coating layer 11c is an intermediate portion and the second coating layer 11d and the cover portion 210 are outer layer portions.

  Also in the multilayer ceramic capacitor 200 of the present embodiment configured as described above, it is possible to achieve the same effect as the first embodiment, that is, both moisture resistance and capacitance securing. In the cover part 210 of the external dielectric 110, an internal electrode layer is interposed between the internal dielectric 16. As a result, the phenomenon that the sintering aid derived from the external dielectric 110 diffuses into the laminate 14 is relatively unlikely to occur. However, the side margin portion 20 is in direct contact with the outer dielectric 110 and the inner dielectric 16. Therefore, the phenomenon that the sintering aid derived from the external dielectric 110 diffuses into the laminate 14 is relatively likely to occur. Therefore, if the 1st coating layer 11c used as an intermediate part at least in a side margin part is formed, the spreading | diffusion to the laminated body 14 of a sintering aid can be suppressed.

  Examples of the present invention will be described below.

[Example 1]
A 1005-shaped chip was fabricated and evaluated.

(Production of ceramic slurry)
Barium titanate (BaTiO ₃ ) as a main component, and sintering aids: Si (silicon): 0.5 mol per 100 mol of Ti, Mg (magnesium): 0.5 mol per 100 mol of Ti, Mn (manganese): 100 mol of Ti On the other hand, 0.5 mol, V (vanadium): A first ceramic slurry containing 0.1 mol with respect to 100 mol of Ti was prepared. Next, a second ceramic slurry containing barium titanate as a main component and containing 0.1 mol of Si (silicon): 100 mol of Ti and Mg (magnesium): 0.1 mol of 100 mol of Ti as a sintering aid, Si (silicon): 1.0 mol per 100 mol of Ti, Mg (magnesium): 1.0 mol per 100 mol of Ti, Mn (manganese): 1.0 mol per 100 mol of Ti, V (vanadium): 0.1 mol per 100 mol of Ti. A third ceramic slurry containing 2 mol was prepared.

(Production of 1005-shaped chip)
A first ceramic green sheet having a thickness of 1.0 μm was prepared from the first ceramic slurry, and an internal electrode layer was laminated on the first ceramic green sheet (see FIG. 6B).

  Subsequently, the first ceramic green sheets and the internal electrode layers were alternately laminated to form a laminate A (see FIG. 6C). At this time, the internal electrode layers were alternately changed in polarity for each layer.

  Subsequently, the second ceramic green sheet formed from the second ceramic slurry is laminated on the front and back surfaces of the laminate A, and the third ceramic green sheet formed from the third ceramic slurry on the second ceramic green sheet. And a cover part having a thickness of 50 μm was formed on the laminate A (see FIG. 7A).

  Subsequently, the laminated body A on which the cover portion was laminated was diced (cut) to obtain an unfired chip (see FIG. 7B). Subsequently, the second ceramic slurry whose viscosity was adjusted with a predetermined solvent was dipped on the side cut surface of the green chip and dried to form a second slurry layer.

  Subsequently, a third slurry layer made of a third ceramic slurry whose viscosity is adjusted with a predetermined solvent is laminated on the second slurry layer to form a side margin portion having a thickness of 50 μm on the green chip. And the laminated body B was obtained (refer FIG.7 (c)).

  Next, the laminate B was fired at 1280 ° C. in a reducing atmosphere. After firing, the sintering aid was diffused to obtain a 1005-shaped chip (hereinafter referred to as the first chip) in which an intermediate part made of the second ceramic slurry and an outer layer part made of the third ceramic slurry were formed. (See FIG. 8 (a)). In Example 1, the thicknesses of the second slurry layer and the third slurry layer were changed to produce first chips having different thicknesses of the intermediate portion and the outer layer portion.

(Production of laminated body C and laminated body D)
Except for laminating the third slurry layer directly on the side cut surface of the unfired chip, a laminate C having no intermediate part was produced by the same method as described above. Furthermore, the laminated body D which does not have an outer layer part was produced by the method similar to the above-mentioned method except not laminating | stacking a 3rd slurry layer on a 2nd slurry layer.

(Characteristic test of first chip, laminate C, and laminate D)
The characteristics (humidity resistance, electrostatic capacity) of the first chip, the laminated body C, and the laminated body D, which were obtained by the above-described method, and the thicknesses of the intermediate portion and the outer layer portion were evaluated. FIG. 16 is a table showing the results.

  Specifically, after performing a moisture resistance load test under the conditions of number = 500, test temperature = 125 ° C., relative humidity = 95% RH, applied voltage = 5 Vdc (direct current), time = 100 h, a moisture resistant tank immediately And the resistance value was measured when the temperature returned to room temperature. And the resistance value of less than 1 MΩ was determined as moisture resistance failure, and the failure rate was examined. In this test, it was determined that the defect rate was 0%, and that it had moisture resistance.

  Sample number 1 shown in FIG. 16 is a laminate C in which no intermediate part is formed. As shown in the figure, it was confirmed that the laminated body C has moisture resistance and capacitance.

  Further, as shown in FIG. 16, the first chips of Sample Nos. 2 to 5 having an intermediate part had a capacitance of 10 μF or more and a defect rate of 0%. However, since the capacitance of the first chip of sample number 2 is lower than that of sample number 3, it was confirmed that the thickness of the intermediate portion is preferably 2 μm or more. .

  Moreover, as shown in FIG. 16, the moisture resistance defect was confirmed by the 1st chip | tip of the sample number 6 which thickened the thickness of the intermediate part. This is presumably because the sinterability deteriorated as the thickness of the outer layer portion decreased. Sample number 7 shown in FIG. 16 is a laminate D in which the outer layer portion is not formed. As shown in the figure, the layered product D had a defect rate of 80%. Therefore, from these results, it was confirmed that the thickness of the intermediate part is preferably 30 μm at the maximum.

[Example 2]
A 1608-shaped chip was fabricated and evaluated.

(Production of ceramic slurry)
Barium titanate (BaTiO ₃ ) as the main component, Si (silicon): 0.56 mol per 100 mol of Ti as a sintering aid, Mn (manganese): 0.15 mol per 100 mol of Ti, V (vanadium): 100 mol of Ti On the other hand, 0.1 mol, Ho (holmium): A fourth ceramic slurry containing 0.4 mol with respect to 100 mol of Ti was produced. Next, barium titanate is also the main component, and Si (silicon): 1.0 mol per 100 mol of Ti, Mg (magnesium): 0.95 mol per 100 mol of Ti, and Mn (manganese): 100 mol of Ti as sintering aids. 0.375 mol, V (vanadium): 0.2 mol with respect to Ti 100 mol, Ho (holmium): 0.8 mol with respect to Ti 100 mol, Ca (calcium): 0.3 mol with respect to Ti 100 mol, B (boron): Ti 100 mol A fifth ceramic slurry containing 0.155 mol relative to Si, silicon (Si): 0.135 mol relative to Ti 100 mol, Mg (magnesium): 0.5 mol relative to Ti 100 mol, and Mn (manganese): relative to 100 mol Ti 0.037 mol, V (vanadium): 0.1 mol relative Ti100mol, Ho (holmium): to prepare a sixth ceramic slurry containing 0.4mol against Ti100mol.

(Production of 1608-shaped chip)
A fourth ceramic green sheet is produced from the fourth ceramic slurry to a thickness of 1 μm after sintering, and the thickness after sintering is 0.5 μm by screen printing on the fourth ceramic green sheet. The internal electrode layer was formed with a sufficient thickness (see FIG. 6B).

  Subsequently, 400 pieces of the fourth ceramic green sheets on which the internal electrode layers were formed were laminated to form a laminate E (see FIG. 6C). At this time, the internal electrode layers were alternately changed in polarity for each layer.

  Then, the 5th ceramic green sheet which consists of a 6th ceramic slurry was laminated | stacked on the surface and the back surface of the laminated body E, and the cover part with a thickness of 50 micrometers was formed in the laminated body E. As shown in FIG.

  Subsequently, the laminated body E on which the cover portion was formed was diced (cut) to obtain an unfired chip. Subsequently, the fifth ceramic slurry was dipped on the side cut surface of the green chip and dried to form a BT paste.

  Subsequently, a fifth slurry layer made of the sixth ceramic slurry was laminated on the BT paste to form a side margin portion having a thickness of 50 μm on the unsintered chip, whereby a laminate F was obtained.

  Next, the laminate F was fired at a predetermined temperature in a reducing atmosphere with a hydrogen concentration of 0.06%. After firing, the sintering aid diffused to obtain a 1608-shaped chip (hereinafter referred to as a second chip) in which an intermediate part made of the fifth ceramic slurry and an outer layer part made of the sixth ceramic slurry were formed. (See FIG. 15). In this example, second chips having different Mn concentrations in the cover part and the side margin part and different firing temperatures were produced.

(Characteristic test of 2nd chip)
In the second chip obtained by the above-described method, the Vickers hardness of the surface of the cover part (A surface) and the surface of the side margin part (B surface) and the moisture resistance defect rate of the chip were examined. The moisture resistance load test was performed under the conditions of number = 500, test temperature = 85 ° C., relative humidity = 85% RH, applied voltage = 6.3 Vdc, and time = 14 hr. Evaluation of the defect rate and the like was performed in the same manner as in the first example.

  First, the characteristics of the second chip in which the content of Mn (manganese) in the side margin portion was fixed to 0.075 mol with respect to 100 mol of Ti and the contents of Mn (manganese) in the cover portion were different from each other were examined. FIG. 17 is a table showing the results.

  Next, the characteristics of the second chip in which the content of Mn (manganese) contained in the cover portion is fixed to 1.125 mol with respect to 100 mol of Ti and the contents of Mn (manganese) contained in the side margin portions are different from each other. I investigated. FIG. 18 is a table showing the results.

As shown in FIG. 17 and FIG. 18, it is possible to produce a product with no moisture resistance when the Vickers hardness is 650 or more on both the A surface and the B surface and the ratio of the Vickers hardness of the A surface to the B surface is 1.00 or more. It was confirmed that it was possible. Therefore, from this result, it was confirmed that the moisture resistance of the second chip is ensured when the cover portion and the side margin portion have a predetermined hardness.

  Next, the characteristics of chips having different Mn concentrations contained in the BT paste and different firing temperatures were examined. FIG. 19 is a table showing the results. From this result, it was confirmed that the method of controlling the Vickers hardness by changing the firing temperature has an influence on the entire product, and therefore the product life is reduced. For this reason, for example, it is desirable to adjust the sinterability by including a manganese compound such as manganese oxide in the cover portion and the side margin portion.

  In this embodiment, a 1608-shaped chip has been described as an example, but the chip size is not limited to this, and products of other shapes (or sizes) such as a 1005 shape are also evaluated with the same index. Is possible.

[Example 3]
A multilayer ceramic capacitor (MLCC) according to Example 3 was produced.

(Production of ceramic slurry)
First, barium titanate (BaTiO ₃ ) powder having an average particle size of 100 nm was prepared as a raw material powder for the inner dielectric and the outer dielectric (cover portion and side margin portion).

  Next, a seventh ceramic slurry having this barium titanate as a main component and serving as a base for the internal dielectric was prepared. In the seventh ceramic slurry, Si (silicon) as a sintering aid is 1.15 mol per 100 mol of Ti, Mn (manganese) is 0.08 mol per 100 mol of Ti, and B (boron) is 0.13 mol per 100 mol of Ti. V (vanadium) is contained in an amount of 0.1 mol per 100 mol of Ti, and Ho (holmium) is contained in an amount of 1.0 mol per 100 mol of Ti. Further, Ba / Ti and A / B were set to 1.0100 and 1.0050, respectively.

  Further, an eighth ceramic slurry that is also composed mainly of barium titanate and serves as a base for the external dielectric was prepared. In the eighth ceramic slurry, Si (silicon) as a sintering aid is 2.00 mol per 100 mol of Ti, Mn (manganese) is 2.25 mol per 100 mol of Ti, and B (boron) is 0.26 mol per 100 mol of Ti. V (vanadium) is contained in an amount of 0.1 mol per 100 mol of Ti, and Ho (holmium) is contained in an amount of 1.0 mol per 100 mol of Ti. Further, Ba / Ti and A / B were set to 1.0100 and 1.0075, respectively.

(Production of MLCC molding)
Then, the MLCC molded object was produced using the 7th ceramic slurry and the 8th ceramic slurry. A detailed manufacturing method is described below.

  First, a seventh ceramic green sheet having a thickness of 1.0 μm was prepared from the seventh ceramic slurry by a doctor blade method. Then, a conductive paste film containing Ni was formed on the seventh ceramic green sheet by screen printing in a predetermined pattern.

  Subsequently, an eighth slurry layer made of the eighth ceramic slurry and having the same thickness as the conductive paste film was formed by screen printing on the seventh ceramic green sheet on which the conductive paste film was formed. At this time, a gap of 5 μm was formed between the conductive paste film and the eighth slurry layer.

  Subsequently, 201 sheets of the seventh slurry layer on which the conductive paste film and the eighth slurry layer were formed were stacked so that the side from which the conductive paste film was drawn was alternated, and a layered product G was obtained. Next, a plurality of ninth slurry layers made of the eighth ceramic slurry were laminated on the upper and lower surfaces of the laminate G to form a cover portion having a thickness of 20 μm.

  Then, the laminated body G in which the cover part was formed was cut into predetermined size, and the rectangular parallelepiped laminated body H was obtained. Next, a plurality of ninth slurry layers are stacked on both side surfaces of the stacked body H to form side margin portions having a thickness of 40 μm, so that the length direction, the width direction, and the height direction are 0. MLCC moldings of 6 mm, 0.3 mm and 0.3 mm were obtained.

(Production of multilayer ceramic capacitor)
A multilayer ceramic capacitor was produced using the MLCC molded body obtained by the above-described method. Specifically, after the binder was debindered at 300 ° C. in a nitrogen atmosphere, the MLCC molded body was heated from 1150 ° C. to 1250 ° C. at a heating rate of 600 ° C./hr in a reducing atmosphere containing H ₂ (hydrogen). Baked for 10 minutes to 2 hours. After lowering the temperature, the temperature was raised from 800 ° C. to 1050 ° C. in a nitrogen atmosphere, and re-oxidation treatment was performed while maintaining 1050 ° C. to obtain an MLCC sintered body.

  Next, Ni paste containing glass frit was applied to both end faces where the internal electrode layer of the MLCC sintered body was exposed. And the baking process was performed in nitrogen atmosphere, the external electrode was formed, and the multilayer ceramic capacitor was obtained (refer FIG.8 (b)).

[Example 4]
A multilayer ceramic capacitor (MLCC) according to Example 4 was produced.

First, using a barium titanate (BaTiO ₃ ) obtained by the same method as in Example 3, a ninth ceramic slurry serving as a base for the internal dielectric was prepared. In the ninth ceramic slurry, Si (silicon) as a sintering aid is 1.15 mol per 100 mol of Ti, Mn (manganese) is 0.08 mol per 100 mol of Ti, and B (boron) is 0.13 mol per 100 mol of Ti. , V (vanadium) is contained in 0.093 mol with respect to 100 mol of Ti, and Ho (holmium) is contained in 0.75 mol with respect to 100 mol of Ti.

  Next, a tenth ceramic slurry, which is also composed mainly of barium titanate and serves as a base for the external dielectric, was prepared. In the tenth ceramic slurry, Si (silicon) as a sintering aid is 1.15 mol per 100 mol of Ti, Mn (manganese) is 0.08 mol per 100 mol of Ti, and B (boron) is 0.13 mol per 100 mol of Ti. , V (vanadium) is contained in 0.093 mol with respect to 100 mol of Ti, Ho (holmium) is contained in 0.75 mol with respect to 100 mol of Ti, and Mg (magnesium) is contained in 1.00 mol with respect to 100 mol of Ti.

  Subsequently, an MLCC molded body was produced using the ninth ceramic slurry and the tenth ceramic slurry by the same method as in Example 3, and then a multilayer ceramic capacitor was obtained.

[Comparative Examples 1 to 3]
Multilayer ceramic capacitors according to Comparative Examples 1 to 3 were produced.

  The multilayer ceramic capacitor according to Comparative Example 1 was produced by the same method as in Example 3 except that the outer dielectric contained only Si (silicon) more than the inner dielectric.

  The multilayer ceramic capacitor according to Comparative Example 2 was manufactured by the same method as in Example 3 except that the outer dielectric contained more Si (silicon) and B (boron) than the inner dielectric.

  The multilayer ceramic capacitor according to Comparative Example 3 was produced by the same method as in Example 3 except that the content of each sintering aid contained in the outer dielectric and the inner dielectric was the same.

[Characteristic test of multilayer ceramic capacitor]
The characteristics (capacitance, capacity ratio, moisture resistance failure rate) of the multilayer ceramic capacitor obtained by the above-described method were examined. FIG. 20 shows the ratio of the sintering aid contained in the inner dielectric and the outer dielectric of the multilayer ceramic capacitors according to Examples 3 and 4 and Comparative Examples 1 to 3, and the result of the characteristic test of each multilayer ceramic capacitor. It is a table | surface which shows.

  When Example 3 and Comparative Example 3 were compared, it was confirmed that the moisture resistance failure was improved when the outer dielectric contained more sintering aid than the inner dielectric.

  Further, as shown in Example 4 of FIG. 20, it can be seen that even when the outer dielectric contains only magnesium more than the inner dielectric, the moisture resistance defect is improved and the capacity and the capacity ratio are maintained.

  Further, comparing Example 3 with Comparative Examples 1 and 2, it can be seen that the configuration of Example 3 improves not only the moisture resistance failure but also the capacity and capacity ratio. As a result, the configuration in which the outer dielectric material contains more than one kind of sintering aids including Mn (manganese) as in Example 3 is more resistant to moisture than the configuration in which the outer dielectric material contains only Mg more than the inner dielectric material. It was confirmed that not only the defects but also the capacity and capacity ratio could be improved.

DESCRIPTION OF SYMBOLS 10,200 ... Multilayer ceramic capacitor 11, 110 ... External dielectric 12 ... 1st external electrode 13 ... 2nd external electrode 14 ... Laminate 15 ... 1st internal electrode layer 16 ... Internal dielectric 17 ... Second internal electrode layer 18 ... Intermediate part 19 ... Outer layer part 20 ... Side margin part 21, 210 ... Cover part

Claims (6)

The first internal electrode layer and the second internal electrode layer are alternately stacked via an internal dielectric formed of a ceramic dielectric containing manganese, and the first surface, which is a surface in the stacking direction, A second surface which is the surface opposite to the first surface; and the first internal electrode layer and the second internal electrode layer are drawn out perpendicular to the first surface and the second surface. A third surface that is opposite to the third surface, the fourth surface from which the first internal electrode layer and the second internal electrode layer are drawn, and the first surface A fifth surface perpendicular to the second surface, the third surface, and the fourth surface and from which the first internal electrode layer is drawn, and a surface opposite to the fifth surface. A laminated body having a sixth surface from which the second internal electrode layer is drawn;
An outer dielectric formed of a ceramic dielectric containing more manganese than the inner dielectric and covering the first surface, the second surface, the third surface, and the fourth surface of the laminate. Body,
A first external electrode covering the fifth surface and electrically connected to the first internal electrode layer;
A second external electrode that covers the sixth surface and is electrically connected to the second internal electrode layer;
The external dielectric contains a larger amount of manganese than the internal dielectric in a range of 0.3 mol to 4.5 mol with respect to 100 mol of Ti. First internal electrode layers and second internal electrode layers are alternately stacked via an internal dielectric formed of a ceramic dielectric containing magnesium, and the first surface, which is a surface in the stacking direction, A second surface which is the surface opposite to the first surface; and the first internal electrode layer and the second internal electrode layer are drawn out perpendicular to the first surface and the second surface. A third surface that is opposite to the third surface, the fourth surface from which the first internal electrode layer and the second internal electrode layer are drawn, and the first surface A fifth surface perpendicular to the second surface, the third surface, and the fourth surface and from which the first internal electrode layer is drawn, and a surface opposite to the fifth surface. A laminated body having a sixth surface from which the second internal electrode layer is drawn;
An outer dielectric formed of a ceramic dielectric containing more magnesium than the inner dielectric and covering the first surface, the second surface, the third surface, and the fourth surface of the laminate. Body,
A first external electrode covering the fifth surface and electrically connected to the first internal electrode layer;
A second external electrode that covers the sixth surface and is electrically connected to the second internal electrode layer;
The external dielectric contains a larger amount of magnesium than the internal dielectric in a range of 0.3 mol to 4.5 mol with respect to 100 mol of Ti. The multilayer ceramic capacitor according to claim 1 or 2,
The outer dielectric and the inner dielectric comprise silicon;
A multilayer ceramic capacitor in which the outer dielectric contains more silicon than the inner dielectric. The multilayer ceramic capacitor according to claim 3,
The external dielectric contains a larger amount of silicon than the internal dielectric in a range of 2.8 mol or less with respect to 100 mol of Ti. A multilayer ceramic capacitor according to any one of claims 1 to 4,
The outer dielectric and the inner dielectric include boron;
The multilayer ceramic capacitor wherein the external dielectric contains more boron than the internal dielectric. The multilayer ceramic capacitor according to claim 5,
The multilayer ceramic capacitor, wherein the external dielectric contains more boron than the internal dielectric in a range of 0.8 mol or less with respect to 100 mol of Ti.

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