JP2019175431A - Information processing apparatus and control method thereof - Google Patents

Abstract

To provide an information processing apparatus efficiently performing power control in accordance with a job to be processed.SOLUTION: The information processing apparatus includes a scanner image processing part including a color space conversion part that comprise: a data processing means performing data processing; a first SRAM 404 storing a parameter for performing data processing of data input to the data processing means; a second SRAM 405 temporarily storing the data processed by the data processing means; data control means controlling an output of the data stored in the second SRAM; and data control means performing power control to supply power to a storage area in which the parameter of the first SRAM is stored, stop power supply to a control area for writing the data to the first SRAM and a storage area in which the data of the second SRAM is stored, and stop power supply to a control area for writing the data in a case where a job that uses the first SRAM and the second SRAM is not performed.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a power saving technique for a semiconductor integrated circuit included in an information processing apparatus.

  A semiconductor integrated circuit in the information processing apparatus includes a logic circuit that executes arithmetic processing and a static memory (SRAM) circuit that is used as a data storage area. As a conventional SRAM power saving technique, an SRAM circuit having two power saving modes, a resume standby mode and a shutdown mode, is disclosed in addition to a normal operation mode for reading and writing data (see Patent Document 1). ). This resume standby mode (hereinafter referred to as “RS mode”) of the SRAM is an operation mode in which power consumption is reduced while the written data is retained. The shutdown mode (hereinafter referred to as “SD mode”) is an operation mode for stopping the function without holding the written data. By operating in these modes, leakage currents in peripheral circuits for accessing SRAM cells and SRAMs are reduced.

International Publication No. 2016/157412

  An image forming apparatus on which the above-described semiconductor integrated circuit is mounted has a normal power mode for performing operations such as scanning and printing, and a power saving mode for reducing standby power without performing operations, and switches the power mode. It is working. In the image forming apparatus, the power supply to the semiconductor integrated circuit is controlled according to the power mode, so that the power consumption of the entire image forming apparatus is reduced. For example, it is configured such that a clock gate and power supply can be shut off for the logic circuit and SRAM of the semiconductor integrated circuit.

  However, in a semiconductor integrated circuit mounted on the image forming apparatus, even if a job using the SRAM is not executed, the power supply to the SRAM is cut off and the stored data is erased. May affect subsequent job operations. For example, if the SRAM for holding image processing parameters is turned off and the data is deleted during a period when the job using the SRAM is not executed, it is necessary to reset the parameters when executing the job using the SRAM. Occurs, and the recovery time becomes longer.

  In the technique disclosed in Patent Document 1, in the RS mode, even when there is no need to hold data, power is supplied to the storage area of the SRAM circuit. I couldn't plan.

  Therefore, there is a possibility that power control cannot be performed efficiently according to the job to be processed.

  An information processing apparatus according to an aspect of the present invention that solves the above-described problem includes a data processing unit that executes data processing, and a parameter for executing the data processing on data input to the data processing unit. A first SRAM for storing; a second SRAM for temporarily storing data processed by the data processing means; a data control means for controlling the output of the data stored in the second SRAM; When a job that uses the first SRAM and the second SRAM is not executed, power is supplied to a storage area in which the parameters of the first SRAM are stored, and the data is stored in the first SRAM. The power supply to the control area for writing is stopped, and the storage area in which the data of the second SRAM is stored and the data are written. Characterized in that it comprises a control means for performing power control for stopping the power supply to fit the control area.

  According to the present invention, in the power saving control of the SRAM, the SRAM that needs to hold data is set to the RS mode, and the SRAM that does not need to hold the data is set to the SD mode according to the job to be processed. Control can be performed.

1 is a block diagram illustrating an example of the overall configuration of an image forming apparatus according to an exemplary embodiment. It is a block diagram which shows the example of schematic structure of a main controller. It is a block diagram which shows the schematic structural example of a scanner image processing part. It is a block diagram which shows the schematic structural example of a color space conversion part. It is a block diagram which shows the detailed structural example of SRAM. 4 is a flowchart illustrating a flow of SRAM power control when a copy job is input to the image forming apparatus. It is a flowchart which shows the detail of the flow of SRAM power control. It is a timing chart explaining the example of SRAM power control.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments do not limit the present invention, and all the combinations of features described in the present embodiment are not necessarily essential to the solution means of the present invention.

[Embodiment]
<Image forming apparatus>
FIG. 1 is a block diagram illustrating an example of the overall configuration of an image forming apparatus according to the present embodiment. The image forming apparatus 100 includes a print function that can print an image on a recording medium such as paper. Further, the image forming apparatus 100 includes a scan function that can scan a document and transmit an input image via a network. In the present embodiment, an example in which the image forming apparatus 100 is a multi-function printer (Multi Function Printer: hereinafter referred to as “MFP”) will be described.

  The image forming apparatus 100 includes a main controller 101, an operation unit 102, a scanner 103, and a printer 104. The operation unit 102, the scanner 103, and the printer 104 are communicably connected to the main controller 101, and are controlled by instructions from the main controller 101.

  The main controller 101 is connected to a LAN (Local Area Network) 106 and is connected to the PC 105 or the like via the LAN 106. The operation unit 102 includes a liquid crystal display touch panel and the like, and receives an instruction input from a user. The scanner 103 illuminates an image formed on a sheet and scans a CCD (Charge Coupled Device) provided with R (red), G (green), and B (blue) color filters. The scanner 103 converts the charge amount acquired by the CCD into an electrical signal indicating RGB color image data or gray scale image data. The printer 104 prints raster image data on a recording medium such as paper.

  FIG. 2 is a block diagram illustrating a schematic configuration example of the main controller 101 in the present embodiment. The main controller 101 functions as an image processing apparatus, and each functional block of the main controller 101 is mounted on a semiconductor integrated circuit such as an ASIC. In the present embodiment, a plurality of functional blocks are mounted on one ASIC, but each functional block may be mounted on a separate ASIC. The main controller 101 controls the scanner 103 connected via a scanner interface (hereinafter referred to as “I / F”) 212 and the printer 104 connected via a printer I / F 213. The main controller 101 is connected to the LAN 106 via the LAN I / F 206 and the public line 107 via the modem unit 207. The main controller 101 can send and receive files and the like to and from external devices such as the PC 105 through the LAN 106 and the public line 107.

  The main controller 101 includes a CPU 201 that is a main control unit. The CPU 201 is connected to the DRAM 202, the ROM 203, the image bus I / F 204, the operation unit I / F 205, the LAN I / F 206, the modem unit 207, and the HDD (Hard Disk Drive) 208 via the system bus 209. Is done. The CPU 201 is further connected to the clock control unit 220 and the SRAM power saving control unit 221 via the system bus 209.

  The DRAM 202 is a main storage device in the main controller 101 and provides a work area to the CPU 201. The DRAM 202 of this embodiment is also used as an image memory for temporarily storing image data. The ROM 203 stores a system boot program. The operation unit I / F 205 performs transmission between the main controller 101 and the operation unit 102. For example, the operation unit I / F 205 transmits image data for display to the operation unit 102 and transmits information received through the operation unit 102 to the CPU 201. The LAN I / F 206 performs transmission between the CPU 201 and the LAN 106. The modem unit 207 performs transmission between the CPU 201 and the public line 107. The HDD 208 is an auxiliary storage device and holds various data used in the image forming apparatus 100 such as image data, address book data, log data, and user data.

  The clock control unit 220 controls a clock signal (CLK) supplied to each image processing unit described later in detail. Although not shown in FIG. 2, the main controller 101 is operated by a clock signal, and the scanner image processing unit (data processing unit) 300 is also operated by the clock signal. The SRAM power saving control unit 221 performs power saving shift control and power saving return control (normal power return control) on the SRAM included in each image processing unit, which will be described later in detail. The CPU 201 controls the clock control unit 220 and the SRAM power saving control unit 221 to execute SRAM power saving transition control and SRAM power saving return control (SRAM normal power return control) described later in detail.

  The image bus I / F 204 is an interface for transmitting image data at a high speed between the system bus 209 and the image bus 210, and converts the data structure of the image data before and after the transmission of the image data. That is, the image bus I / F 204 of the present embodiment functions as a bus bridge.

  A RIP (Raster Image Processor) 211, a scanner image processing unit 300, a printer image processing unit 900, an image rotation unit 214, and an image compression unit 215 are connected to the image bus 210. The RIP 211 develops, for example, PDL (Page Description Language) data transmitted from the PC 105 and received via the LAN 106 into a bitmap image.

  A scanner I / F 212 is an interface for transmitting image data between the scanner 103 and the main controller 101 (scanner image processing unit 300). The image I / F 212 is a synchronous / asynchronous system for image data before and after transmission of the image data. Perform conversion. The scanner image processing unit 300 performs image processing such as color space conversion processing and filter processing on image data input from the scanner 103 via the scanner I / F 212.

  The printer I / F 213 is an interface for transmitting image data between the printer 104 and the main controller 101 (printer image processing unit 900). The image I / F 213 is a synchronous / asynchronous system of image data before and after transmission of image data. Perform conversion. The printer image processing unit 900 performs image processing such as color space conversion processing, filter processing, and gamma correction processing on image data output to the printer 104 via the printer I / F 213.

  The image rotation unit 214 executes processing for rotating image data. The image compression unit 215 performs compression / decompression processing on various image data. Specifically, the image compression unit 215 executes JPEG compression / decompression processing for multi-valued image data, and performs compression / decompression processing such as JBIG, MMR, and MH for binary image data.

  The power control unit 216 performs power control of the image forming apparatus 100 based on control signals from the operation unit 102, the CPU 201, and the LAN I / F 206. The power control unit 216 according to the present embodiment performs power control so that the image forming apparatus 100 is operated by switching between the normal power mode and the power saving mode. In the present embodiment, the normal power mode refers to a state in which power is supplied to each functional block of the image forming apparatus 100 and an operation such as printing can be performed according to a job that has received an input. The power saving mode is a state in which power to each functional block in the image forming apparatus 100 is cut off and power consumption is smaller than that in the normal power mode.

  The main functional blocks of the image forming apparatus 100 are, for example, the printer image processing unit 900, the RIP 211, and the CPU 201 necessary for causing the printer 104 to execute a printing operation according to a job that has received an input in the normal power mode. And so on. On the other hand, for example, in the power saving mode, the LAN I / F 206 that detects job reception from the PC 105, the power control unit 216, and the like do not correspond to main functional blocks.

  FIG. 3 is a block diagram illustrating a schematic configuration example of the scanner image processing unit 300. The scanner image processing unit 300 according to the present embodiment constitutes an image processing module group that performs image processing necessary for the image forming apparatus 100 to operate the scanner 103 and read an image. The scanner image processing unit 300 is mounted on, for example, a semiconductor integrated circuit such as an ASIC, and the semiconductor integrated circuit includes a logic circuit that performs an operation necessary for image processing and an SRAM circuit that is used as a data storage area.

  The sub-scanning color misregistration correction unit 311 is an image processing module that corrects color misregistration in the sub-scanning direction of image data input by the scanner 103. For example, the sub-scanning color misregistration correction unit 311 performs a matrix operation on the 8-bit pixel data of each RGB color of the image data using a 1 × 3 pixel size filter centered on the target pixel. The sub-scanning color misregistration correction unit 311 scans the target pixel pixel by pixel in the main scanning direction, and performs matrix calculation on the image data. At this time, the sub-scanning color misregistration correction unit 311 stores pixel data continuous in the main scanning direction in a line buffer SRAM (not shown) in accordance with the scanning of the target pixel.

  The main scanning color misregistration correction unit 312 is an image processing module that corrects color misregistration in the main scanning direction of image data. For example, the main scanning color misregistration correction unit 312 performs a matrix operation on the 8-bit pixel data of each RGB color of the image data using a filter of 5 pixels × 1 pixel size centered on the target pixel.

  The color space conversion unit 313 is an image processing module that converts image data depending on the characteristics of the scanner 103 into image data in a device-independent color space. In this embodiment, the color space conversion unit 313 refers to a look-up table (hereinafter referred to as “LUT”) held in an SRAM 404 (see FIG. 4) described later, and converts image data depending on the characteristics of the scanner 103 into Convert to device-independent color space image data. The color space conversion unit 313 also includes an SRAM 405 (see FIG. 4) for temporarily storing image data to which the above-described color space conversion processing is added. The SRAM (second SRAM) 405 has a larger number of hardware processing steps in the image area determination process of the image area determination unit 314 than in the image processing in the color space conversion unit 313. It is provided. That is, the SRAM 405 functions as a delay buffer in a transmission path for transmitting image data from the main scanning color misregistration correction unit 312 to the filter processing unit 315 via the color space conversion unit 313. As a result, the color space conversion unit 313 can input pixel data at the same position as the attribute flag data to the subsequent filter processing unit 315 simultaneously with the attribute flag data output from the image area determination unit 314. The detailed configuration of the color space conversion unit 313 will be described later.

  The image area determination unit 314 determines whether the pixel of interest in the image data is included in a character portion, a photograph portion, a chromatic color portion, or an achromatic color portion, and sets attribute flag data indicating the portion in units of pixels. An image processing module to be generated.

  The filter processing unit 315 is an image processing module that corrects image data to image data having desired spatial frequency characteristics. The filter processing unit 315 performs a matrix operation on the 8-bit pixel data of each RGB color of the image data, using a 5 pixel × 5 pixel size filter centered on the target pixel.

  The histogram processing unit 316 is an image processing module that creates a distribution from pixel data constituting the image data, and further corrects the image data by changing the created distribution.

  Note that the processing in the scanner image processing unit 300 described above is not limited to the processing from the sub-scanning color misregistration correction unit 311 to the histogram processing unit 316, and includes functional blocks that perform other types of image processing. Also good. Also, some of the processing from the sub-scanning color misregistration correction unit 311 to the histogram processing unit 316 may be omitted. Further, the processing order from the sub-scanning color misregistration correction unit 311 to the histogram processing unit 316 is not limited to the above-described order.

  The scanner image processing unit 300 is supplied with a clock signal (CLK) 320. The clock signal 320 supplied to the scanner image processing unit 300 is supplied to each of the image processing units 311 to 316 described above. Whether the clock signal 320 is supplied to each of the image processing units 311 to 316 is controlled by an instruction from the CPU 201 to the clock control unit 220. The RS signal 321 input / output from the SRAM power saving control unit 221 to the scanner image processing unit 300 is a signal for performing power saving control of the SRAM included in each of the image processing units 311 to 316. The transmission path of the RS signal 321 is indicated by a broken line in FIG. 3, and the sub-scanning color misregistration correction unit 311, main scanning color misregistration correction unit 312, color space conversion unit 313, image area determination unit 314, filter processing unit 315, The histogram processing unit 316 is serially connected. The RS signal 321 output from the histogram processing unit 316 that is the image processing unit at the final stage returns to the SRAM power saving control unit 221, and a so-called loopback method is adopted. In other words, the SRAM power saving control unit 221 functions as an output unit that outputs a control signal for shifting the SRAMs 404 and 405 to the power saving mode to the serially connected SRAMs 404 and 405.

  FIG. 4 is a block diagram illustrating a schematic configuration example of the color space conversion unit 313. The color space conversion processing unit 401 is a logic unit that converts RGB pixels input from the main scanning color misregistration correction unit 312 into device-independent sRGB pixels. The color space conversion processing unit 401 is connected to an SRAM (first SRAM) 404. The SRAM 404 is connected to the LUT setting unit 403. Based on an instruction from the CPU 201, the LUT setting unit 403 sets an LUT that is a conversion table referred to in the color conversion process, and stores the set LUT in the SRAM 404. The color space conversion processing unit 401 performs color space conversion processing based on the LUT stored in the SRAM 404. The color space conversion processing unit 401 functions as data processing means for executing data processing.

  The output delay control unit 402 once accumulates the pixel data processed by the color space conversion processing unit 401 in the SRAM 405, and combines it with the image area determination data output from the image area determination unit 314 operating in parallel, and performs subsequent filtering processing. The delay amount is controlled in order to perform image processing in the unit 315. That is, the output delay control unit 402 outputs the device-independent color space image data to the filter processing unit 315 at the same timing as the image area determination data. Controls the amount of delay to delay the output. The output delay control unit 402 functions as data control means for controlling output of data stored in the SRAM 405.

  The clock signal 320 supplied to the color space conversion unit 313 is supplied to each of the sub modules 401 to 405. In addition, the SRAM 404 and the SRAM 405 are serially connected so that the transmission path of the RS signal 321 input to and output from the color space conversion unit 313 is indicated by a broken line. The mode signals 420 and 421 are input to setting ports for setting the power saving modes of the SRAMs 404 and 405, respectively. When the setting ports of the SRAMs 404 and 405 are connected to Vdd as in the mode signal 420 and become high level, the SRAM shifts to the RS mode during power saving control. When the setting ports of the SRAMs 404 and 405 are connected to the GND as in the mode signal 421 and become low level, the SRAM shifts to the SD mode during power saving control. The mode signals 420 and 421 may be fixed to Vdd / GND according to the configuration of the main controller 101. For example, the connection destination is configured by a register so that the setting can be changed from the CPU 201. Also good.

  FIG. 5A is a block diagram illustrating a detailed configuration example of the SRAM 500 according to the present embodiment. FIGS. 5B to 5D are explanatory diagrams of an example of the operation state of the SRAM 500. FIG. 5B shows the case of the normal power mode, and FIG. 5C is the power saving mode (RS mode). FIG. 5D shows a case of the power saving mode (SD mode). That is, the SRAM 500 is a power-saving SRAM that can shift to the RS mode or the SD mode and return to the normal mode, and has a lower power consumption than the normal mode when shifting to the RS mode or the SD mode. . In the present embodiment, an SRAM having a configuration like the SRAM 500 is applied to the SRAM 405, and adaptive power saving control is executed. Further, it is assumed that the SRAM 500 is a 2-port SRAM that allows simultaneous read access and write access. In FIGS. 5B to 5D, the submodules for which power supply is performed are displayed in white, and the submodules for which power supply is interrupted are displayed in hatching.

  As shown in FIG. 5A, a plurality of types of signals are input to the SRAM 500. The CS signal, the WE signal, and the RE signal are input signals for controlling the operation timing of the SRAM 500, as are signals used for general memory control. The wraddr signal, the rdaddr signal, the data_in signal, and the clock signal (CLK) 320 are input signals for write / read address control, input data control, and clock control as well as signals used for general memory control. is there. The RS signal 321 is a signal for controlling the transition to the power saving mode such as the RS mode or the SD mode and the return to the normal power mode. The mode signal is an input signal for selecting whether the power saving mode shifted by the RS signal is to be the RS mode or the SD mode. Transition. This is connected to the mode signals 420 and 421 in FIG.

  Also, as shown in FIG. 5A, the SRAM 500 outputs a plurality of types of signals. The data_out signal is an output signal for controlling output data, similarly to a signal used for general memory control. The RSO signal is a signal for delaying the input RS signal for a predetermined time by the buffer 505 and then outputting it to the SRAM or SRAM power saving control unit 221 of the subsequent module. The SRAM or SRAM power saving control unit 221 of the subsequent module can know from the assertion of this signal and the negation timing that the SRAM 500 has completed the transition to the RS mode or the SD mode or the return to the normal power mode.

  The control unit 501 includes a timing control circuit (not shown) that generates an operation timing signal from a CS signal or a WE signal. The control unit 501 controls power supply to the word driver unit 502, the column unit 503, and the memory array unit 504 according to the RS signal, and selectively cuts off power supply to these when the RS signal is at a high level. A circuit is provided.

  Here, two power saving modes of the SRAM 500, that is, the RS mode (520) and the SD mode (530) will be described. The RS mode is a mode for implementing power saving while retaining the data of the SRAM 500. When the RS signal is instructed by the mode signal, the control unit 501 maintains (continues) power supply to the control unit 501 and the memory array unit 504 as illustrated in FIG. Only the power supply to the column unit 503 is cut off. On the other hand, the SD mode is a mode that does not hold the data of the SRAM 500 but realizes higher power saving than the RS mode. When the SD mode is instructed by the mode signal, the control unit 501 cuts off the power supply to the memory array unit 504 in addition to the word driver unit 502 and the column unit 503 as shown in FIG. In addition, when not shifting to the two power saving modes of the RS mode and the SD mode, the SRAM 500 operates as a normal mode. That is, the SRAM 500 operates as a normal mode (510) in which power is supplied to the control unit 501, the word driver unit 502, the column unit 503, and the memory array unit 504, as shown in FIG. Further, when the SRAM is shifted to the power saving mode such as the RS mode or the SD mode, it is necessary to turn off the clock signal supplied to the SRAM in advance as shown in FIGS.

  Returning to the description of FIG. 5A, the word driver unit 502 is a functional block that determines which column (row) of the memory array unit 504 is activated by decoding the addr signal. When the SRAM 500 receives the RS mode or the SD mode, the word driver unit 502 is powered off by the control unit 501.

  The column unit 503 is a functional block that determines which row (column) of the memory array unit 504 is activated by decoding the addr signal. The column unit 503 is powered off by the control unit 501 when the SRAM 500 accepts the RS mode or the SD mode.

  In this embodiment, the voltage fluctuation in the memory array unit 504 is suppressed by preventing the power supply interruption of the word driver unit 502 and the column unit 503 and the oscillation of the clock signal from overlapping when shifting to the RS mode. It is done. The control unit 501, word driver unit 502, and column unit 503 in the SRAM 500 can be said to be control regions for writing data to the memory array unit 504.

  In the memory array portion 504, static memory cells are arranged in a matrix, and data is held in memory cells determined by the word driver portion 502 and the column portion 503. The memory array unit 504 maintains power supply in the RS mode in addition to the normal operation, and thus can hold data in the RS mode. On the other hand, in the memory array unit 504, when the SRAM 500 receives the SD mode, the power supply is interrupted by the control unit 501, and the data held in the memory array unit 504 is lost. The memory array unit 504 in the SRAM 500 can be said to be a storage area for storing image data for executing image processing.

  In the present embodiment, the power consumption when the scanner image processing unit 300 is not used is obtained by gating the clock signal 320 from the CPU 201 via the clock control unit 220 to the scanner image processing unit 300 (see FIG. 3). Can be suppressed. In addition, by controlling the RS signal 321 from the CPU 201 via the SRAM power saving control unit 221, the power consumption of the SRAM in the scanner image processing unit 300 can be further suppressed.

  Like the LUT SRAM 404, the SRAM that holds parameters that need to be reset before executing scanner image processing uses the RS mode that does not erase the data if the data held inside disappears. To perform power saving control. This eliminates the need for resetting parameters in the SRAM 404 after returning from the power saving mode, and shortens the time required to start job execution after returning from the power saving mode. On the other hand, for an SRAM that can complete the retention and reuse of SRAM internal data for each job of the image forming apparatus 100, such as the delay buffer SRAM 405, the data disappears, but the SD has a higher power saving effect than the RS mode. Use the mode to perform power saving control. As a result, it is possible to construct a system that achieves both power saving and return time from the power saving mode.

  A method of switching the normal mode, the RS mode, and the SD mode of the SRAM will be described in detail with reference to FIGS. 6, 7, and 8. FIG. The following symbols S mean steps in the flowchart.

  FIG. 6 is a flowchart showing the flow of power saving return control and power saving shift control of the SRAMs 404 and 405 when a copy job is input to the image forming apparatus 100. Unless otherwise specified, each process is executed by the CPU 201. It is assumed that the SRAM 404 is held in the RS mode and the SRAM 405 is held in the SD mode before the processing illustrated in FIG. 6 is started. Furthermore, it is assumed that the SRAM in the printer image processing unit 900 is also set to the RS mode and the SD mode according to the application before the process illustrated in FIG.

  First, the CPU 201 determines whether a copy job has been started (S601). When a copy job is input to the image forming apparatus 100 via the operation unit 102 by a user input operation, the copy job is started under the control of the main controller 101 or the like. In other words, the image forming apparatus 100 determines whether or not the copy job has been started until the copy job is input. When the copy job is input, the image forming apparatus 100 executes the copy job. When the CPU 201 determines that the copy job has started (YES in S601), the CPU 201 instructs the SRAM power saving control unit 221 to perform the SRAM power saving return control of the scanner image processing unit 300 (S602). The SRAM power saving control unit 221 executes power saving return control on the SRAMs 404 and 405 of the scanner image processing unit 300 based on an instruction from the CPU 201. Details of the power saving return control will be described later.

  Subsequently, the CPU 201 executes power saving return control of the SRAM of the printer image processing unit 900 (S603). That is, the CPU 201 instructs the SRAM power saving control unit 221 to return the printer image processing unit 900 from the power saving state to the normal power state. Based on an instruction from the CPU 201, the SRAM power saving control unit 221 outputs a signal instructing the SRAM of the printer image processing unit 900 to return from the RS mode and the SD mode to the normal mode. The SRAM of the printer image processing unit 900 returns from the power saving state to the normal power state based on the return signal from the SRAM power saving control unit 221.

  Next, the CPU 201 determines whether it is necessary to set image processing parameters for the scanner image processing unit 300 and the printer image processing unit 900 used in the copy job (S604). The case where the setting of the image processing parameter is necessary is a case where the parameter or LUT is not set in the SRAM 404 or a case where the setting of the copy job is changed and the parameter or LUT needs to be set again in the SRAM 404. . When the CPU 201 completes the parameter and LUT settings, the CPU 201 sets in the register that the setting to the SRAM is complete. In step S604, the CPU 201 refers to the register and determines whether the parameter and LUT settings have been completed. Further, the CPU 201 refers to the setting of the previous copy job stored in a memory such as the DRAM 202 different from the SRAM 404. The settings of the previous copy job and the settings of the current copy job are compared. If the settings are different, the CPU 201 determines that the parameter and LUT settings are necessary. In other words, when the CPU 201 determines that image processing parameters need to be set for the scanner image processing unit 300 and the printer image processing unit 900 used in the copy job (YES in S604), the process proceeds to S605. If the CPU 201 determines that it is not necessary to set image processing parameters for the scanner image processing unit 300 and the printer image processing unit 900 used in the copy job (NO in S604), the process skips S605 and proceeds to S606. Transition.

  The CPU 201 executes parameter and LUT settings for the SRAM 404 (S605). The CPU 201 sets parameters and LUTs suitable for setting a copy job in the SRAM 404 of the scanner image processing unit 300 and the SRAM of the printer image processing unit 900. When no parameter or LUT is set in the SRAM, the CPU 201 sets the LUT or parameter corresponding to the current job setting in the SRAM. If parameters and LUTs have already been set in the SRAM, the CPU 201 compares the previous job settings stored in the DRAM 202 and the current job settings, and sets only the parameters and LUTs corresponding to the differences in the SRAM. To do.

  When the image processing parameter setting to the SRAM 404 of the scanner image processing unit 300 and the SRAM of the printer image processing unit 900 is completed, transfer of image data to the scanner 103 and the printer 104 is started.

  The CPU 201 determines whether or not the copy job is completed (S606). The CPU 201 determines that the copy job is completed based on the completion of reading all pages of the document and the completion of printing. Specifically, the CPU 201 determines that the copy job has been completed based on a copy job completion notification that is output when the printer 104 has completed printing all pages.

  If the CPU 201 determines that the copy job is not completed (NO in S606), the CPU 201 shifts the processing to S607. If the CPU 201 determines that the copy job is completed (YES in S606), the CPU 201 shifts the process to S609.

  In S607, the CPU 201 receives a page image from the scanner 103 and stores it in the DRAM 202 or the like. In the process of reception, the scanner image processing unit 300 executes predetermined image processing on the page image. If the scanning process is completed, for example, reading of all pages set on an ADF (Auto Document Feeder) document table is completed, the process of S608 is performed without performing the process of S607.

  In step S <b> 608, the CPU 201 inputs the page image stored in the DRAM 202 to the printer image processing unit 900 and transmits it as copy data to the printer 104 via the printer IF 213. The printer 104 outputs (prints) the input copy data on a recording medium. In the transmission process, the printer image processing unit 900 performs page image processing, which is predetermined image processing, on the page image. When the processing for the page image is completed for one page, the processing is returned to S606. The CPU 201 determines whether or not the copy job has been completed. Here, S607 and S608 do not necessarily have to be executed sequentially, and S607 and S608 can be executed in parallel to speed up the copy job operation.

  In step S <b> 609, the CPU 201 instructs the SRAM power saving control unit 221 to perform power saving shift control of the scanner image processing unit 300. The SRAM power saving control unit 221 executes power saving transition control on the SRAMs 404 and 405 of the scanner image processing unit 300 based on an instruction from the CPU 201. Details of the power saving shift control will also be described later.

  In step S610, the CPU 201 executes SRAM power saving transition control of the printer image processing unit 900. That is, the CPU 201 instructs the SRAM power saving control unit 221 to shift the printer image processing unit 900 from the normal power state to the power saving state. Based on an instruction from the CPU 201, the SRAM power saving control unit 221 outputs a signal that instructs the SRAM of the printer image processing unit 900 to shift from the normal power state to the power saving state. The SRAM of the printer image processing unit 900 shifts from the normal power state to the power saving state based on the shift signal from the SRAM power saving control unit 221.

  As described above, when the power saving transition control (S609) of the scanner image processing unit 300 and the power saving transition control of the printer image processing unit 900 are completed, a series of power control processing accompanying the input of the copy job to the image forming apparatus 100 is completed. To do.

  In the present embodiment, a processing example in which the SRAMs 404 and 405 included in the scanner image processing unit 300 are shifted to the RS mode and the SD mode, respectively, after the copy job is completed has been described. Even if the printing by the printer 104 has not been completed, the CPU 201 may execute the processing of S609 based on a document reading completion notification that is output when the scanner 103 has read all the pages of the document.

  In the present embodiment, the case where the process of S609 is executed based on the copy job completion notification has been described. When the job that uses the scanner 103 for a predetermined time is not executed after the printing by the printer 104 is completed, the process of S609 may be executed. Further, the processing of S609 may be executed when a job for using the printer for a predetermined time is not executed after printing by the printer 104 is completed.

  In addition, a job other than a copy job using the scanner 103 may be started, such as a data storage function for storing an input image from the scanner 103 in the HDD 208 or a transmission function for transmitting the image to another PC 105 via the LAN 106. When starting a job other than the copy job using the scanner 103, the SRAMs 404 and 405 in the scanner image processing unit 300 are returned from the power saving state to the normal power state, and are again set to the power saving state after the job is completed. You may migrate.

  Furthermore, when executing a job that does not use the scanner image processing unit 300 such as PDL printing, power saving return control and power saving transition control after completion of the job are performed only for the SRAM in the printer image processing unit 900. May be. That is, when executing a job that does not use the scanner image processing unit 300, the SRAM in the scanner image processing unit 300 may be held in a power saving state.

  By performing power control according to the job, when executing a job that does not use the scanner image processing unit 300, the SRAMs 404 and 405 in the scanner image processing unit 300 are maintained in the power saving state, and the printer image processing unit 900 has the power saving state. The SRAM can be operated.

  FIG. 7A is a flowchart showing details of S609 in FIG. Specifically, FIG. 7A is a flowchart showing a flow of power saving transition control of the SRAMs 404 and 405 of the scanner image processing unit 300. FIG. 7B is a flowchart showing details of S602 in FIG. Specifically, FIG. 7B is a flowchart showing a flow of power saving return control (normal power return control) of the SRAMs 404 and 405 of the scanner image processing unit 300. FIG. 8A is a timing chart for explaining the operation of the power saving transition control example of the SRAMs 404 and 405 of the scanner image processing unit 300. FIG. 8B is a timing chart for explaining the operation of the normal power return control example of the SRAMs 404 and 405 of the scanner image processing unit 300. In FIG. 8A, N is an integer of 89 or more, and in FIG. 8B, M is an integer of 86 or more.

  CLK 800 is the same clock signal as the clock signal (CLK) 320 supplied to each of the sub modules 401 to 405 in the color space conversion unit 313 and the image processing units 311 to 316 that are peripheral circuits thereof.

  The mode_0 signal 810, the RS_0 signal 811, the RSO_0 signal 812, and the SRAM State_0 signal 813 represent the movement of the control signal in the power saving state of the SRAM 404 for LUT. The mode_1 signal 820, the RS_1 signal 821, the RSO_1 signal 822, and the SRAM State_1 signal 823 represent the movement of the control signal in the power saving state of the SRAM 405 for the delay buffer.

  The mode_0 / 1 signals 810 and 820 are signals for instructing whether to shift to the RS mode or the SD mode when each SRAM shifts to the power saving state. In this embodiment, the mode signals of the SRAMs 404 and 405 are fixed to Vdd with respect to the SRAM 404 and fixed to GND with respect to the SRAM 405 as shown in FIG. 4, so the mode_0 signal 810 is at the high level and the mode_1 signal 820 is at the low level. . The RS_0 / 1 signals 811 and 821 are signals for controlling the transition of the SRAMs 404 and 405 to the RS / SD mode and the power saving return (normal power return). When the CLK 800 is in a gated state and the RS_0 / 1 signals 811 and 821 are asserted to a high level, the SRAMs 404 and 405 are in a state of shifting to the RS / SD mode. The RSO_0 / 1 signals 812 and 822 are signals output from the RS signals 811 and 821 with a delay added by the buffer 505 in the SRAM 500. SRAM State_0 / 1 813 and 823 are SRAM power status information indicating whether the power status of the SRAM 404 or 405 is in the normal mode, normal mode (clock gate), RS mode, or SD mode. . The RSO_n signal 830 is output from the histogram processing unit 316 at the final stage of the RS signal 321 that is transmitted by serial connection in the scanner image processing unit 300 including the SRAMs 404 and 405 and is output to the SRAM power saving control unit 221. Indicates the return timing.

  Hereinafter, unless otherwise specified, each signal name indicates a signal timing in the timing chart of FIG. 8, and the notation CLKXXX or CLKXXX to YYY (XXX and YYY are integers) indicate the clock timing in FIG. . Further, CLKA0 to N + 3 are clock timings in the timing chart of FIG. 8A, and CLKB0 to M + 5 are clock timings in the timing chart of FIG.

  Returning to the description of the flowcharts of FIGS. The processing of each flow in FIGS. 7A and 7B is executed by the CPU 201 unless otherwise specified. In the present embodiment, when execution of a job that uses the scanner image processing unit 300 is completed, the CPU 201 starts power saving transition control of the scanner image processing unit 300. Hereinafter, an example of power saving shift control of the scanner image processing unit 300 will be described with reference to FIG.

  First, the CPU 201 instructs the clock control unit 220 to clock the clock signal 320 (CLK800) supplied to the scanner image processing unit 300 (S701). As a result, the clock signal 320 (CLK800) supplied to the SRAMs 404 and 405 is also stopped as in CLKA3 to N + 3 in FIG. Accordingly, as shown in SRAM State_0 / 1 signals 813 and 823, the power state of each SRAM is in the normal mode but is clock gated.

  Next, the CPU 201 instructs the SRAM power saving control unit 221 to perform power saving transition control (S702). Specifically, this corresponds to the signal control of the timing of CLKA5 in FIG. 8 in which the RS_0 signal 811 is asserted. In the SRAM 404, since the mode_0 signal 810 is at a high level, the control unit 501 of the SRAM 404 turns off (shuts off) power supply to the word driver unit 502 and the column unit 503 in accordance with the input RS_0 signal 811. Further, as the power supply to these submodules 502 and 503 is cut off (stopped), the power state of the SRAM 404 shifts to the RS mode as in the SRAM State_0 signal 813.

  In the present embodiment, the RS_0 signal 811 is delayed by 40 clocks by the buffer 505, and is output as the RSO_0 signal 812 at the timing of the CLKA 45 in FIG. The RSO_0 signal 812 output at the timing of CLKA45 is delayed by one clock depending on the wiring length, and is input to the SRAM 405 as the RS_1 signal 821 at the timing of CLKA46 in FIG.

  In the SRAM 405, since the mode_1 signal 820 is at the low level, the control unit 501 of the SRAM 405 turns off (cuts off) the power supply to the word driver unit 502, the column unit 503, and the memory array unit 504 in accordance with the input RS_1 signal 821. ) Further, as the power supply to these submodules 502, 503, and 504 is interrupted (stopped), the power state of the SRAM 405 shifts to the SD mode as in the SRAM State_1 signal 823.

  In the present embodiment, the RS_1 signal 822 is delayed by 40 clocks by the buffer 505 and is output as the RSO_1 signal 822 at the timing of the CLKA 86 in FIG. After that, after N-1 SRAMs that perform the same control are routed in total, the RSO_n signal 830 is returned to the SRAM power saving control unit 221 at the timing of CLKA N in FIG.

  The SRAM power saving control unit 221 that asserted the RS_0 signal 811 in S702 determines whether or not the SRAM power saving transition control of the scanner image processing unit 300 has been completed by waiting for the assert timing of the RSO_n signal 830 (S703). . When it is confirmed (detected) that the RSO_n signal 830 is asserted (YES in S703), the CPU 201 completes the power saving transition control of the scanner image processing unit 300.

  Next, a power saving return control example (normal power return control example) of the scanner image processing unit 300 will be described with reference to FIG. In this embodiment, when the execution of a job using the scanner image processing unit 300 is instructed by the user, the CPU 201 starts the normal power return control of the scanner image processing unit 300.

  First, the CPU 201 instructs the SRAM power saving control unit 221 to perform power saving return control (normal power return control) for performing normal power control (S711). Specifically, this corresponds to the signal control of the timing of CLKB1 in FIG. 8B in which the RS_0 signal 811 is negated. The control unit 501 of the SRAM 404 turns on (starts) power supply to the word driver unit 502 and the column unit 503 in accordance with the input RS_0 signal 811. Further, with the power supply to these submodules 502 and 503, the power state of the SRAM 404 returns to the normal mode (clock gate) state as in the SRAM State_0 signal 813.

  Further, as described above, the RS_0 signal 811 is delayed by 40 clocks by the buffer 505 and is output as the RSO_0 signal 812 at the timing of the CLKB 41 in FIG. The RSO_0 signal 812 output at the timing of CLKB41 is delayed by one clock depending on the wiring length, and is input to the SRAM 405 as the RS_1 signal 821 at the timing of CLKB42 in FIG.

  The control unit 501 of the SRAM 405 supplies power to the word driver unit 502, the column unit 503, and the memory array unit 504 in accordance with the input RS_1 signal 821. Like the SRAM State_1 signal 823, the power state of the SRAM 405 returns to the normal mode (clock gate) state.

  Further, as described above, the RS_1 signal 822 is delayed by 40 clocks by the buffer 505 and is output as the RSO_1 signal 822 at the timing of the CLKB 82 in FIG. After that, after passing through M−1 SRAMs that perform the same control, the RSO_n signal 830 is returned to the SRAM power saving control unit 221 at the timing of CLKBM in FIG.

  The SRAM power saving control unit 221 negating the RS_0 signal 811 in S711 determines whether or not the SRAM normal power return control of the scanner image processing unit 300 is completed by waiting for the negation timing of the RSO_n signal 830 (S712). . When it is confirmed (detected) that the RSO_n signal 830 has been negated (YES in S712), the CPU 201 instructs the clock control unit 220 to cancel the clock gate of the clock signal 320 supplied to the scanner image processing unit 300 ( S713). As a result, the clock is restarted and transmitted to the SRAMs 404 and 405 as CLKB M + 1 to M + 5 in FIG. Accordingly, as in SRAM State_0 / 1, the power state of each SRAM returns to the normal mode state in which no clock gate is performed. As described above, the scanner image processing unit 300 returns to a state in which scanner image processing can be executed, and the power saving return control (normal power return control) is completed.

  As described above, in this embodiment, the LUT SRAM 404 of the color space conversion unit 313 is controlled to shift to the RS mode as the power saving mode at the idle time, and the delay buffer SRAM 405 is shifted to the SD mode. Executed. Thereby, since the power control of the SRAM 500 during the image processing operation can be adaptively performed, more effective power saving control during the operation of the image processing module can be realized. In other words, according to the job to be processed, the SRAM that needs to hold data is set to the RS mode and the SRAM that does not need to hold the data is set to the SD mode during the power saving control of the SRAM. Power control can be performed.

[Modification]
A modification of the present embodiment will be described below.

  In the above description, the case where the present invention is applied to the color space conversion unit 313 of the scanner image processing unit 300 has been described. However, other image processing units in the scanner image processing unit 300, other image processing units other than the scanner image processing unit 300, etc. It is also possible to apply to. Even in such a case, the SRAM that needs to hold data is set to the RS mode and the SRAM that does not need to hold the data is set to the SD mode during the power saving control of the SRAM according to the job to be processed. By doing so, power control can be performed efficiently.

[Other Embodiments]
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program. It can also be realized by processing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

320 Clock signal 321 RS signal 404 SRAM (SRAM for LUT)
405 SRAM (SRAM for delay buffer)
420 mode signal 421 mode signal 500 SRAM
505 buffer

Claims (16)

Data processing means for performing data processing;
A first SRAM for storing parameters for executing the data processing on the data input to the data processing means;
A second SRAM for temporarily storing data processed by the data processing means;
Data control means for controlling the output of the data stored in the second SRAM;
When a job that uses the first SRAM and the second SRAM is not executed, power is supplied to a storage area in which the parameters of the first SRAM are stored, and the data is stored in the first SRAM. Control means for stopping power supply to the control area for writing, and performing power control for stopping power supply to the storage area for storing the data of the second SRAM and the control area for writing the data An information processing apparatus comprising:   The control means supplies power to the storage area and the control area of the first SRAM and executes the second SRAM when executing a job using the first SRAM and the second SRAM. The information processing apparatus according to claim 1, wherein power is supplied to the storage area and the control area. The data input to the data processing means is image data,
The information processing apparatus according to claim 1, wherein the parameter is a lookup table referred to by the data processing unit.   The information processing apparatus according to claim 3, wherein the lookup table is a conversion table referred to in a color space conversion process of the image data.   5. The information processing apparatus according to claim 1, wherein the second SRAM delays output of data processed by the data processing unit. 6.   An output means for outputting a control signal for shifting the first SRAM and the second SRAM to a power saving mode to the first SRAM and the second SRAM connected in series. Item 6. The information processing device according to any one of Items 1 to 5. In an information processing apparatus having a plurality of memory devices having a memory area, a control area for controlling writing to the memory area, and a power control circuit for controlling power supply to the memory area and the control area.
Power control means for instructing the plurality of memory devices to shift to a power saving state;
The power control circuit of at least one memory device among the plurality of memory devices is configured to continue the power supply to the memory area based on an instruction to shift to the power saving state from the power control unit. Power supply to
A power control circuit of another memory device among the plurality of memory devices stops power supply to the memory area and the control area based on an instruction to shift to the power saving state from the power control means. An information processing apparatus characterized by the above.   The information processing apparatus according to claim 7, wherein power is supplied to the power control circuit of the memory device even after shifting to the power saving state. A data processing means for processing the input data;
The information processing apparatus according to claim 7, wherein the at least one memory device stores a parameter used in processing by the data processing unit.   The information processing apparatus according to claim 9, wherein the parameter stored in the at least one memory device is a lookup table.   8. The information processing according to claim 7, wherein the at least one memory device delays an instruction to shift to the power saving state from the power control unit and outputs the delayed instruction to the other memory device. apparatus.   The information processing apparatus according to claim 7, wherein the power control circuit determines an area in which power supply is stopped based on a voltage applied to a predetermined pin among the memory area and the control area. .   The information processing apparatus according to claim 7, wherein the power control unit instructs to shift to the power saving state in accordance with completion of a job for accessing the memory device.   The information processing apparatus according to claim 7, wherein the memory device is an SRAM. The information processing apparatus according to claim 13, wherein the power control unit instructs the memory device to return from the power saving state in accordance with a job input. A method for controlling an information processing apparatus,
A data processing step for performing data processing;
Storing in the first storage means a parameter for executing the data processing on the data input in the data processing step;
Temporarily storing the data processed by the data processing step in a second storage means;
A data control step for controlling the output of the data stored in the second storage means;
When the job using the first storage unit and the second storage unit is not executed, the first storage unit supplies power to the storage area in which the parameter of the first storage unit is stored and the first storage unit The power for stopping the power supply to the control area for writing the data to the storage area and for stopping the power supply to the storage area for storing the data and the control area for writing the data of the second storage means And a control step for controlling the information processing apparatus.

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