JP2019169600A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor device with high reliability and a method for manufacturing the same.SOLUTION: A semiconductor device comprises a circuit part, an insulation part provided around the circuit part, a protection member provided in the insulation part and provided so as to surround the circuit part, and a stress relaxation part provided along the protection member in the insulation part.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof.

  A semiconductor memory device having a three-dimensional structure has a structure in which a memory cell array including a plurality of memory cells and a peripheral circuit are integrated. A dicing line is provided around the memory cell array and the peripheral circuit, and a plurality of chips each having the memory cell array and the peripheral circuit are separated into pieces by cutting along the dicing line. In such a semiconductor memory device, a groove for protecting the memory cell array is formed between the memory cell array and the peripheral circuit and the dicing line, and the groove is deformed by an insulating film on the memory cell array and the peripheral circuit. There is a problem of doing.

JP 2009-021528 A

  An object of the embodiment is to provide a highly reliable semiconductor device and a manufacturing method thereof.

  The semiconductor device according to the embodiment includes a circuit unit, an insulating unit provided around the circuit unit, a protective member provided in the insulating unit and provided to surround the circuit unit, and the insulating unit. A stress relieving portion provided along the protection member.

It is a top view showing a semiconductor device concerning an embodiment. It is a top view of the area | region A of FIG. 3A is an enlarged plan view of the region B in FIG. 2, and FIG. 3B is a cross-sectional view of the columnar portion. 4A is an enlarged plan view of a region C in FIG. 2, and FIG. 4B is a cross-sectional view taken along line D1-D2 in FIG. 4A. It is a top view which shows a part of semiconductor device which concerns on a reference example. 6A and 6B are diagrams showing the relationship between the position and width of the groove. FIG. 7A and FIG. 7B are diagrams showing the relationship between the position and width of the groove. It is a figure which shows the relationship between the position of a groove | channel, and a width | variety. It is a figure which shows the displacement amount of an element. It is a figure which shows the displacement amount of an element. FIG. 11A and FIG. 11B are plan views showing the method for manufacturing a semiconductor device according to the embodiment. FIG. 12A and FIG. 12B are plan views showing the method for manufacturing a semiconductor device according to the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
As an example, a case where the semiconductor device is a three-dimensional semiconductor memory device will be described.

(This embodiment)
FIG. 1 is a plan view showing the semiconductor device 1.
In the semiconductor device 1, a substrate 10 containing silicon (Si) or the like is provided (see FIG. 3A). Hereinafter, in this specification, for convenience of explanation, an XYZ orthogonal coordinate system is adopted. Two directions parallel to and orthogonal to the upper surface 10a of the substrate 10 are defined as “X direction” and “Y direction”, and a direction perpendicular to the upper surface 10a is defined as “Z direction”.

As shown in FIG. 1, the semiconductor device 1 is provided with a cell region (circuit portion) Rmc, a peripheral region Rs, and a dividing region Rd.
In the cell region Rmc, a memory cell array (MCA in FIG. 2) including a plurality of memory cells is provided. When viewed from the Z direction, the shape of the cell region Rmc is, for example, a rectangle.

  The peripheral region Rs is located around the cell region Rmc. In the peripheral region Rs, peripheral circuits (PC in FIG. 2) such as a row decoder and a sense amplifier are provided. For example, the peripheral circuit may be located near both ends of the memory cell array in the X direction and the Y direction, or may be located near at least one end of the memory cell array in the X direction and the Y direction.

  In the example illustrated in FIG. 1, the cell regions Rmc are arranged along the X direction and the Y direction, and the peripheral region Rs is positioned around each cell region Rmc. The cell region Rmc and the peripheral region Rs are separated by the slit ST1 in the Y direction and separated by the slit ST2 in the X direction.

  The divided region Rd is located around the peripheral region Rs. For example, the divided region Rd is located between the peripheral regions Rs adjacent in the X direction and the Y direction. In the dividing region Rd, a dicing line DL as shown by a broken line is formed so as to extend in the X direction and the Y direction.

  In the example shown in FIG. 1, a chip 1A (semiconductor device) is configured by two cell regions Rmc (memory cell array) and a peripheral region Rs (peripheral circuit) located around each cell region Rmc. Note that the number of cell regions Rmc and peripheral regions Rs in the chip 1A is arbitrary. In the divided region Rd, the plurality of chips 1A each having the cell region Rmc and the peripheral region Rs are separated into pieces by cutting along the dicing line DL.

  A groove (protective member) T is provided between the peripheral region Rs and the dividing region Rd. The trench T is located between the memory cell array and the peripheral circuit and the dicing line DL. For example, the groove part T is located in the outer peripheral part of each chip | tip 1A. Elements located in and around the groove T will be described in detail later.

FIG. 2 is a plan view of region A in FIG.
3A is an enlarged plan view of the region B in FIG. 2, and FIG. 3B is a cross-sectional view of the columnar portion CL.
4A is an enlarged plan view of a region C in FIG. 2, and FIG. 4B is a cross-sectional view taken along line D1-D2 in FIG. 4A.
In FIG. 2, the dicing line DL in the dividing region Rd is not shown.
As shown in FIG. 2, a memory cell array MCA including a plurality of memory cells is provided in the cell region Rmc.

  As shown in FIG. 3A, in the cell region Rmc, the memory cell array MCA is provided with a stacked body 15, a columnar portion CL, an insulating member 55A, and an insulating member 55B. The stacked body 15 is provided with a plurality of insulating films 22 and a plurality of electrode films 21, and the insulating films 22 and the electrode films 21 are alternately stacked one by one in the Z direction (see FIG. 3B). . The number of laminated insulating films 22 and electrode films 21 is arbitrary. The insulating film 22 includes, for example, silicon oxide (SiO). The electrode film 21 includes, for example, tungsten (W). The insulating film 22 functions as an interlayer insulating film of the electrode film 21, and the electrode film 21 functions as a source side selection gate, a drain side selection gate, and a word line.

The columnar portion CL is provided in the stacked body 15. When a plurality of columnar portions CL are provided, for example, the plurality of columnar portions CL are arranged in a lattice shape in the X direction and the Y direction.
As shown in FIG. 3B, the columnar part CL is located in the memory hole MH formed in the stacked body 15. The columnar portion CL includes a core insulating film 31, a channel 32, a tunnel insulating film 41, a charge storage film 42, and a block insulating film 43.

The core insulating film 31 includes, for example, silicon oxide. For example, the core insulating film 31 extends in the Z direction in a columnar shape. The core insulating film 31 may not be included in the columnar part CL.
The channel 32 is provided around the core insulating film 31. The channel 32 is a semiconductor part and includes, for example, polysilicon obtained by crystallizing amorphous silicon. The channel 32 extends in the Z direction in a cylindrical shape, and the lower end thereof is in contact with the substrate 10.

The tunnel insulating film 41 is provided around the channel 32. The tunnel insulating film 41 includes, for example, silicon oxide.
The charge storage film 42 is provided around the tunnel insulating film 41. The charge storage film 42 is a film for storing charges, and includes, for example, silicon nitride (SiN).
The block insulating film 43 is provided around the charge storage film 42. The block insulating film 43 includes, for example, silicon oxide.
The upper end of the columnar part CL is connected to a bit line (not shown) via a contact or the like.

  As shown in FIG. 3A, the shape of the end 15 t in the X direction of the stacked body 15 is a stepped shape in which a terrace 21 </ b> T and a step 21 </ b> S are formed on the electrode film 21. Here, the step-like structure means a structure in which the horizontal terraces 21T and the vertical steps 21S are alternately arranged. A contact 21C is provided on the terrace 21T of the end 15t. The contact 21 </ b> C extends in the Z direction, and the lower end of the contact 21 </ b> C is connected to the electrode film 21. The contact 21C includes a conductive material such as tungsten, for example. The upper end of the contact 21C is connected to an upper layer wiring (not shown). For example, the electrode film 21 is connected to a peripheral circuit located in the vicinity of the end 15t of the stacked body 15 via the contact 21C and the upper layer wiring.

  The insulating member 55A is positioned in the slit ST1 that extends the stacked body 15 in the X direction and the Z direction. The insulating member 55B is positioned in the slit ST2 that extends the stacked body 15 in the Y direction and the Z direction. A plurality of insulating members 55 </ b> A are provided, and extend in the X direction and the Z direction within the stacked body 15. The insulating member 55B extends in the Y direction and the Z direction in the stacked body 15, and for example, intersects the plurality of insulating members 55A. The insulating members 55A and 55B include, for example, silicon oxide. The elements (for example, the columnar portion CL) in the stacked body 15 are separated in the Y direction and the X direction by the insulating member 55A in the slit ST1 and the insulating member 55B in the slit ST2.

  As shown in FIG. 2, a peripheral circuit (circuit unit) PC is provided in the peripheral region Rs. For example, the peripheral circuit PC includes a plurality of transistors each formed by a channel region, a source region, a drain region, a gate electrode, and a gate insulating film. The cell region Rmc and the peripheral circuit PC are collectively referred to as a “circuit portion”.

  In the cell region Rmc, a large number of memory cells are arranged in a three-dimensional matrix along the X, Y, and Z directions to form a memory cell array MCA, and data can be stored in each memory cell. . In the peripheral region Rs, the memory cell array MCA is connected to the peripheral circuit PC through contacts and wiring.

In the peripheral region Rs, an insulating film (insulating portion) 50 is provided around the peripheral circuit PC. For example, a contact connected to the gate electrode is provided on the peripheral circuit PC so as to penetrate the insulating film.
The insulating film is also located on the end 15t of the stacked body 15 of the memory cell array MCA in the cell region Rmc. In other words, the contact 21 </ b> C connected to the electrode film 21 is provided on the end portion 15 t of the stacked body 15 so as to penetrate the insulating film. The insulating film 50 is located in the dividing region Rd. The insulating film 50 includes, for example, silicon oxide. The insulating film 50 is formed of, for example, TEOS (tetraethoxysilane).
In the peripheral region Rs, the insulating film 50 outside the peripheral circuit PC and the insulating film 50 in the dividing region Rd are referred to as “insulating portions”.

As shown in FIG. 2, the trench T surrounds the memory cell array MCA and the peripheral circuit PC. However, the trench T is not necessarily formed so as to continuously surround the memory cell array MCA and the peripheral circuit PC, and may be formed intermittently by being divided into a plurality of parts so as to surround the memory cell array MCA and the peripheral circuit PC. Good.
As shown in FIG. 4A, the groove T is constituted by a groove T1, a groove T2, a groove T3, a groove T4, and a groove T5. In the example of FIG. 4A, the trench T1, the trench T2, the trench T3, the trench T4, and the trench T5 are spaced apart from each other in this order from the memory cell array MCA1 in FIG. That is, in the trench portion T, the trench T1, the trench T2, the trench T3, the trench T4, and the trench T5 have a predetermined distance from each other, and in this order from the memory cell array MCA and the peripheral circuit PC in the chip divided by the dicing line DL. It will be located away. As viewed from the Z direction, the shapes of the groove T1, the groove T2, the groove T3, the groove T4, and the groove T5 are, for example, annular.

  For example, each of the five grooves T1 to T5 (for example, the width W1 of the groove T1) is about 200 nanometers, and the distance between the grooves in the grooves T1 to T5 (for example, between the grooves T1 and T2). The distance dt) is about 1000 nanometers. Here, the widths of the grooves T1 to T5 correspond to the width in the direction perpendicular to the Z direction and perpendicular to the direction in which the grooves T1 to T5 extend. Further, the distance between the grooves in the grooves T1 to T5 is a distance between adjacent grooves, and corresponds to a distance in a direction perpendicular to the Z direction and the direction in which the grooves T1 to T5 extend.

  In the trench part T, the trenches T1 to T5 function as trenches for protecting the memory cell array MCA. The grooves T1 to T5 are, for example, chip seal grooves. An embedding member 70 is provided in the grooves T1 to T5. For example, the embedding member 70 includes a metal material such as tungsten. Since the embedded member 70 is formed in the grooves T1 to T5, moisture and the like are prevented from entering the memory cell array MCA from the periphery of the memory cell array MCA. In addition, when dicing along the dicing line DL in the dividing region Rd, a crack may occur from the dividing region Rd toward the cell region Rmc. When the embedded member 70 is formed in the trench T1 to the trench T5, it is possible to prevent the memory cell array MCA in the cell region Rmc from being damaged when a crack occurs from the dividing region Rd to the cell region Rmc. In addition, although the groove part T is comprised by five groove | channels T1-groove T5, the number of the grooves which comprise the groove part T is arbitrary.

  As shown in FIGS. 2 and 4A, a support member (stress relaxation part) 60 is provided in the insulating film 50. For example, a plurality of support members 60 are provided, and the plurality of support members 60 are arranged along the groove T. For example, the plurality of support members 60 are desirably disposed along the groove T1 at a predetermined distance from the groove T1 of the groove portion T. Further, for example, the plurality of support members 60 are desirably arranged along the groove T5 at a predetermined distance from the groove T5 of the groove portion T. As will be described later, the groove T1 and the groove T5 of the groove portion T are more easily deformed than the grooves T2 to T4 due to the compressive stress of the insulating film 50 (TEOS film). Then, the width of the grooves T1 and T5 is prevented from being reduced and deformed by the compressive stress of the insulating film 50.

The support member 60 is desirably located in the vicinity of the corner portion Tp of the groove portion T, for example. For example, in the case where the corner portion Tp of the groove portion T has a shape as shown in FIG. 4A, the distance d1 is separated from the one end Tp1 of the corner portion Tp of the groove portion T in the X direction, and It is desirable that the support member 60A is located in a region 50R surrounded by the position point 50Rt positioned at a distance d1 in the Y direction and one end Tp1 and the other end Tp2 of the corner portion Tp. When viewed from the Z direction, the shape of the region 50R is a triangle, and the distance d1 is about 20 micrometers. The support member 60A is located outside the groove portion T (groove T5), but the support member 60B located inside the groove portion T (groove T1) also has a region such as the region 50R set by the support member 60A. It is desirable to be located in When the support members 60 </ b> A and 60 </ b> B are arranged in this way, the widths of the grooves T <b> 1 and T <b> 5 are prevented from being reduced and deformed by the compressive stress of the insulating film 50.
When viewed from the Z direction, the shape of the support member 60 is, for example, a circle or an ellipse. When viewed from the Z direction, the shape of the support member 60 may be a rectangle. Alternatively, when viewed from the Z direction, the shape of the support member 60 may be a ring shape.

  As shown in FIG. 4B, the support member 60 is positioned in the hole H that extends through the insulating film 50 in the Z direction. Instead of forming the hole H, a slit along the groove T may be formed in the insulating film 50, and the support member 60 may be formed in the slit.

  In the cross section between the Z direction and a direction perpendicular to the Z direction (for example, the X direction or the Y direction), the shape of the support member 60 is, for example, a rectangle. In the example of FIG. 4B, the shape of the support member 60 in the cross sections in the Z direction and the X direction is shown.

  The insulating film 50 is located on the side surface of the support member 60. An insulating film 50 is located on the upper end of the support member 60. For example, the lower end of the support member 60 is located on the substrate 10. The support member 60 may be formed so as to have a recess in the insulating film 50, and in this case, the lower end of the support member 60 is located on the insulating film 50. Further, for example, when the peripheral circuit PC in the peripheral region Rs is located immediately below the support member 60, the lower end of the support member 60 is connected to the elements of the peripheral circuit PC in the Z direction so as not to be electrically connected to the elements of the peripheral circuit PC. It is desirable to have a predetermined distance between them.

  The support member 60 includes a material having a stress opposite to that of the insulating film 50. When the insulating film 50 includes a material having compressive stress (for example, silicon oxide), the support member 60 includes, for example, a material having tensile stress. As a material having a tensile stress, the support member 60 includes, for example, silicon nitride (SiN) and aluminum oxide (AlO).

  As a material having a tensile stress, the support member 60 includes, for example, a metal such as tungsten (W) or titanium (Ti). The support member 60 may include a metal compound such as titanium nitride (TiN), for example. The support member 60 may be formed of a single layer, or may be formed of a stacked body in which layers including at least one of the materials described above are stacked.

By providing the support member 60 having a tensile stress in the insulating film 50, the internal stress (compressive stress) due to the insulating film 50 is relieved. In the following, the case where the insulating film 50 includes a material having a compressive stress and the support member 60 includes a material having a tensile stress will be described. However, the insulating film 50 includes a material having a tensile stress, and the support member 60 includes A material having a compressive stress may be included.
Alternatively, the support member 60 may be a simple cavity. That is, the support member 60 may be a hole or a slit formed in the insulating film 50, and the inside of the support member 60 may be a cavity or a void without being filled. By providing such a cavity or void as the support member 60, the compressive stress or tensile stress of the insulating film 50 can be relaxed.
Alternatively, the support member 60 may be formed of a highly rigid material. That is, if the support member 60 is formed of a highly rigid (hard) material that does not easily expand or contract, deformation in the groove T described later can be suppressed.

  In the semiconductor device 1 of the present embodiment, a support member 60 including a material having tensile stress is provided in the insulating film 50 between the memory cell array MCA and the peripheral circuit PC and the dicing line DL. For example, a plurality of support members 60 are provided, and the plurality of support members 60 are arranged along the groove T. By such a support member 60, deformation of the grooves T1 to T5 of the groove T is suppressed.

Hereinafter, the deformation of the grooves T1 to T5 of the groove T will be described.
FIG. 5 is a plan view showing a part of the semiconductor device 100 according to the reference example.
FIG. 6A, FIG. 6B, FIG. 7A, FIG. 7B, and FIG. 8 are diagrams showing the relationship between the position and width of the groove.
The region shown in FIG. 5 corresponds to the region shown in FIG. 5 corresponds to a configuration in which the supporting member 60 is not provided in the semiconductor device 1 of FIG.

  6A, FIG. 6B, FIG. 7A, FIG. 7B, and FIG. 8 show the upper ends of the grooves T1 to T5 in the regions E1 to E5 in the semiconductor device 100 of FIG. The width values at are respectively shown. 6 (a), 6 (b), 7 (a), 7 (b), and 8, the vertical axis indicates the value of the width of the groove. Nanometer. 6A, FIG. 6B, FIG. 7A, FIG. 7B, and FIG. 8, the horizontal axis indicates the grooves T1 to T5. In each figure, the width value at the upper end of the groove T1 to the groove T5 before deformation (before reduction) is indicated by a broken line.

FIG. 6A shows the widths of the upper ends of the grooves T1 to T5 in the region E1 indicating the vicinity of the center in the Y direction of the memory cell array MCA. In the region E1, in the X direction, the trench T1 is located on the peripheral region Rs (cell region Rmc) side, and the trench T5 is located on the dividing region Rd side. Comparing the widths of the grooves T1 to T5, the width values of the grooves T1 and T5 are smaller than the width values of the grooves T2 to T4. Therefore, it can be seen that in the region E1, the widths of the grooves T1 and T5 are reduced and the grooves T1 and T5 are deformed.
Note that such deformation (change in width) of the groove does not occur uniformly along the depth direction of the groove, and the deformation tends to be maximum at the upper end of the groove. That is, the deformation of the groove tends to increase as it goes from the lower side of the groove toward the upper end.
Thus, as the width decreases toward the upper end of the groove, the upper end of the groove is blocked, and in the subsequent process, the filling may not be sufficiently performed, and a cavity may remain inside the groove.

  FIG. 6B shows the widths of the upper ends of the grooves T1 to T5 in the region E2 indicating the vicinity of the center in the Y direction of the peripheral circuit PC. In the region E2, in the X direction, the groove T1 is located on the peripheral region Rs side, and the groove T5 is located on the dividing region Rd side. Comparing the widths of the grooves T1 to T5, the width values of the grooves T1 and T5 are smaller than the width values of the grooves T2 to T4. Therefore, it can be seen that in the region E2, the widths of the upper ends of the grooves T1 and T5 are reduced and the grooves T1 and T5 are deformed.

  FIG. 7A shows the widths of the upper ends of the grooves T1 to T5 in the region E3 indicating the vicinity of the center in the X direction of the peripheral circuit PC. In the region E3, in the Y direction, the groove T1 is located on the peripheral region Rs side, and the groove T5 is located on the dividing region Rd side. Comparing the widths of the grooves T1 to T5, the width values of the grooves T1 and T5 are smaller than the width values of the grooves T2 to T4. Therefore, it can be seen that in the region E3, the upper end widths of the grooves T1 and T5 are reduced and the grooves T1 and T5 are deformed.

  FIG. 7B shows the width of the upper ends of the trenches T1 to T5 in the region E4 indicating the vicinity of the center in the X direction of the memory cell array MCA (MCA1). In the region E4, in the Y direction, the trench T1 is located on the peripheral region Rs (cell region Rmc) side, and the trench T5 is located on the dividing region Rd side. Comparing the widths of the grooves T1 to T5, the width values of the grooves T1 and T5 are smaller than the width values of the grooves T2 to T4. Therefore, it can be seen that in the region E4, the widths of the upper ends of the grooves T1 and T5 are reduced and the grooves T1 and T5 are deformed.

  FIG. 8 shows the widths of the upper ends of the grooves T1 to T5 in the region E5 indicating the corner portion Tp of the groove T. In the region E5, the trench T1 is located on the peripheral region Rs (cell region Rmc) side, and the trench T5 is located on the dividing region Rd side. When the widths of the grooves T1 to T5 are compared, the width value of the groove T5 is smaller than the width values of the grooves T1 to T4. Therefore, it can be seen that in the region E5, the width of the upper end of the groove T5 is reduced and the groove T5 is deformed.

From FIG. 6A, FIG. 6B, FIG. 7A, and FIG. 7B 8, in the regions E1 to E4, the widths of the upper ends of the grooves T1 and T5 become smaller, and the grooves T1 and G It can be seen that T5 is deformed. Further, it can be seen from FIG. 8 that in the region E5, the width of the upper end of the groove T5 is reduced and deformed.
This is a direction perpendicular to the Z direction and perpendicular to the direction in which the trenches T1 and T5 extend due to the compressive stress of the insulating film 50 (TEOS film) located in the cell region Rmc, the peripheral region Rs, and the dividing region Rd. This is because the grooves T1 and T5 are deformed so that the widths of the grooves T1 and T5 in the direction (for example, the X direction and the Y direction) are reduced.
This is considered to be because the compressive stress applied to the outer grooves T1 and T5 is larger than the inner grooves T2 to T4 among the grooves T1 to T5. That is, the volume of the insulating film 50 existing outside the grooves T1 and T5 is larger than the volume of the insulating film 50 existing on both sides of the inner grooves T2 to T4. For this reason, it is considered that the outer grooves T1 and T5 are subjected to a larger compressive stress and the deformation becomes remarkable.

Next, the amount of element displacement will be described.
FIG. 9 is a diagram illustrating the amount of displacement of the element in the X direction on the top surface of the grooves T1 to T5.
FIG. 9 shows the amount of displacement in the X direction of the element at the position point moved in the direction of the arrow a1 (X direction) from the position point b1 in the peripheral region Rs in the semiconductor device 100 of FIG. The vertical axis | shaft of FIG. 9 has shown the value of the displacement amount of a X direction, and a scale is 1 nanometer, for example. The horizontal axis in FIG. 9 indicates the relative position P from the position point b1.

  Here, the amount of displacement in the X direction corresponds to the amount of deformation from the reference position in the + X direction or the −X direction, with the value of the reference position when the element is not deformed being zero. In FIG. 9, when the displacement amount is larger than 0, it is shown that the element is deformed in the + X direction from the reference position. The larger the displacement amount (positive value), the more the element is deformed. It has been shown that In addition, when the displacement amount is smaller than 0, it is indicated that the element is deformed in the −X direction from the reference position. The smaller the displacement amount (negative value), the larger the element is deformed. It has been shown.

  As shown in FIG. 9, the displacement amount value (positive value) is large at position P1, and the displacement amount value (negative value) is small at position P2. At the position P1 and the position P2, the groove T1 and the groove T5 of the groove portion Ta1 as shown in FIG. 5 are located, respectively. A portion between the position P1 and the position P2 (a portion between the broken lines) corresponds to a portion where the groove portion Ta1 (the groove T1 to the groove T5) is located.

  Therefore, the groove T1 of the groove portion Ta1 is greatly deformed in the + X direction. That is, the groove T1 of the groove portion Ta1 is greatly deformed toward the dividing region Rd side. On the other hand, the groove T5 of the groove portion Ta1 is greatly deformed in the −X direction. That is, the groove T5 of the groove portion Ta1 is greatly deformed toward the peripheral region Rs side. The groove T1 and the groove T5 of the groove portion Ta1 are deformed so that the width becomes smaller at the upper end.

FIG. 10 is a diagram illustrating the amount of displacement of the element in the Y direction on the top surface of the grooves T1 to T5.
FIG. 10 shows the amount of displacement in the Y direction of the element at the position point moved in the direction of the arrow a2 (Y direction) from the position point b2 in the cell region Rmc in the semiconductor device 100 of FIG. The vertical axis in FIG. 10 indicates the value of the displacement amount in the Y direction, and one scale is, for example, 1 nanometer. The horizontal axis in FIG. 10 indicates the relative position P from the position point b2.

  Here, the amount of displacement in the Y direction corresponds to the amount of deformation from the reference position in the + Y direction or the −Y direction, with the value of the reference position when the element is not deformed being zero. In FIG. 10, when the displacement amount is larger than 0, it is shown that the element is deformed in the + Y direction from the reference position. The larger the displacement amount (positive value), the more the element is deformed. It has been shown that Further, when the displacement amount is smaller than 0, it is indicated that the element is deformed in the −Y direction from the reference position. The smaller the displacement amount (negative value), the larger the element is deformed. It has been shown.

  As shown in FIG. 10, the displacement value (negative value) is small at the position Ps1, and the displacement value (positive value) is large at the position Ps2. At positions Ps1 and Ps2, slits ST1a and ST1b as shown in FIG. 5 are located, respectively.

  The displacement value (positive value) is large at the position P3, and the displacement value (negative value) is small at the position P4. At positions P3 and P4, as shown in FIG. 5, grooves T1 and T5 of the groove portion Ta2 are positioned, respectively. A portion between the positions P3 and P4 (a portion between the broken lines) corresponds to a portion where the groove portion Ta2 (grooves T1 to T5) is located.

  Therefore, the groove T1 of the groove portion Ta2 is greatly deformed in the + Y direction. That is, the groove T1 of the groove portion Ta2 is greatly deformed toward the dividing region Rd side. On the other hand, the groove T5 of the groove portion Ta2 is greatly deformed in the -Y direction. That is, the groove T5 of the groove portion Ta2 is greatly deformed toward the peripheral region Rs (cell region Rmc) side. The groove T1 and the groove T5 of the groove portion Ta2 are deformed so that the width becomes small.

  Further, the displacement value (positive value) is large at the position P5, and the displacement value (negative value) is small at the position P6. At the position P5 and the position P6, as shown in FIG. 5, the groove T5 and the groove T1 of the groove portion Ta3 are respectively located. A portion between the positions P5 and P6 (a portion between the broken lines) corresponds to a portion where the groove portion Ta3 (grooves T1 to T5) is located.

  Therefore, the groove T1 of the groove portion Ta3 is greatly deformed in the −Y direction. That is, the groove T1 of the groove portion Ta3 is greatly deformed toward the dividing region Rd side. On the other hand, the groove T5 of the groove portion Ta3 is greatly deformed in the + Y direction. That is, the groove T5 of the groove portion Ta3 is greatly deformed toward the peripheral region Rs (cell region Rmc) side. As a result, the groove T1 and the groove T5 of the groove portion Ta3 are deformed so that the width becomes smaller at the upper end.

  9 and 10, it can be seen that the grooves Ta1, Ta2, and Ta3 are greatly deformed in the X direction or the Y direction at the upper end. This is a direction perpendicular to the Z direction and perpendicular to the direction in which the grooves Ta1, Ta2, and Ta3 extend due to the compressive stress of the insulating film 50 (TEOS film) located in the cell region Rmc, the peripheral region Rs, and the dividing region Rd. This is because the widths of the grooves T1 and T5 of the groove portions Ta1, Ta2, and Ta3 are reduced in a certain direction (for example, the X direction and the Y direction).

Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.
FIG. 11A, FIG. 11B, FIG. 12A, and FIG. 12B are plan views showing a method for manufacturing the semiconductor device 1.
The area shown in FIG. 11A, FIG. 11B, FIG. 12A, and FIG. 12B corresponds to the area shown in FIG.

First, as shown in FIG. 11A, the peripheral circuit PC is formed on the substrate 10. The peripheral circuit PC is located in the peripheral region Rs.
Subsequently, a stacked body in which the insulating films 22 and the sacrificial films are alternately stacked is formed on the substrate 10, and then a memory hole MH that penetrates the stacked body and reaches the substrate 10 is formed. In the memory hole MH, the block insulating film 43, the charge storage film 42, the tunnel insulating film 41, the channel 32, and the core insulating film 31 are sequentially formed to form the columnar portion CL (FIG. 3B). reference).

Subsequently, the end portion of the stacked body is processed into a step shape, and the insulating film 50 is formed so as to cover the peripheral circuit PC and the stacked body. The insulating film 50 is formed by, for example, TEOS.
Subsequently, slits ST1 and ST2 are formed in the laminate. After removing the sacrificial film through the slits ST1 and ST2, the electrode film 21 is formed in the cavity from which the sacrificial film has been removed, thereby forming the stacked body 15 having the insulating film 22 and the electrode film 21 (FIG. 3 (a)). Thereafter, insulating members 55A and 55B are formed in the slits ST1 and ST2. As a result, the memory cell array MCA is formed on the substrate 10. Memory cell array MCA is located in cell region Rmc.

  Next, as shown in FIG. 11B, a plurality of holes H are formed in the insulating film 50 by photolithography and etching such as RIE (Reactive Ion Etching). For example, a plurality of holes H are formed so as to penetrate the insulating film 50 and have the bottom surface reaching the substrate 10. In the cross section between the Z direction and a direction perpendicular to the Z direction (for example, the X direction or the Y direction), the shape of the hole H is rectangular. The plurality of holes H are arranged along the groove T.

Next, as shown in FIG. 12A, a support member 60 is formed in the hole H by, for example, a CVD (Chemical Vapor Deposition) method. The plurality of support members 60 are arranged along the groove T. When the insulating film 50 is formed of a material having compressive stress, the support member 60 is formed of a material having tensile stress. The support member 60 is made of, for example, silicon nitride or aluminum oxide. The support member 60 is formed of, for example, a metal material such as tungsten or titanium.
Next, as shown in FIG. 12B, a groove portion is formed between the memory cell array MCA and the peripheral circuit PC and the dicing line DL (see FIG. 1) by, for example, photolithography and etching processing such as RIE. T is formed. The groove portion T is located between the peripheral region Rs and the dividing region Rd. The trench T is formed so as to surround the memory cell array MCA and the peripheral circuit PC. The groove part T is comprised by the groove | channel T1, the groove | channel T2, the groove | channel T3, the groove | channel T4, and the groove | channel T5 (refer Fig.4 (a)).
Subsequently, the embedded member 70 (see FIG. 4A) is formed in the grooves T1 to T5 of the groove T by, for example, the CVD method. For example, the embedded member 70 is formed of a metal material such as tungsten or titanium.
Thereafter, cutting is performed along the dicing line DL in the dividing region Rd, and a plurality of chips 1A each having a cell region Rmc (memory cell array MCA) and a peripheral region Rs (peripheral circuit PC) are separated into pieces (see FIG. 1). ).
In this way, the semiconductor device 1 is manufactured.

In the specific example described above, the groove portion T is formed after the plurality of holes H are formed. However, the hole H and the groove portion T may be formed at the same time. Alternatively, the hole H may be formed after the groove portion T is formed. For example, the hole H may be formed when a contact hole penetrating the insulating film 50 is formed on the peripheral circuit PC in the peripheral region Rs. In the contact hole, for example, a contact connected to the gate electrode is formed by embedding a metal material. Further, the plurality of holes H may be formed when the memory hole MH is formed.
Similarly, the order of the steps of forming the support member 60 and the embedded member 70 can be changed as appropriate.

Hereinafter, the effect of this embodiment will be described.
In a semiconductor memory device having a three-dimensional structure, a groove is formed between a memory cell array and peripheral circuits and a dicing line, and the memory cell array is protected by embedding a metal material or the like in the groove. Such a groove may be deformed by an insulating film on the memory cell array and the peripheral circuit.

  For example, as shown in FIG. 6A, FIG. 6B, FIG. 7A, FIG. 7B, and FIG. 8 to FIG. 10, the cell region Rmc, the peripheral region Rs, and the divided region Rd are located. Due to the compressive stress of the insulating film 50 (TEOS film), in the direction perpendicular to the Z direction and perpendicular to the direction in which the groove T extends (for example, the X direction and the Y direction), the grooves T1 and T5 of the groove T The width of becomes smaller. That is, the width of the groove T1 and the groove T5 is reduced and the groove T is deformed.

  For example, if the widths of the upper ends of the grooves T1 and T5 of the groove T are reduced, voids are likely to be generated in the grooves T1 and T5 when the embedded member 70 is embedded in the grooves T1 to T5. When cutting along the dicing line DL to divide the plurality of chips 1A into individual pieces, there is a possibility that cracks may occur in the chips 1A due to gaps and the chips 1A may be damaged.

  In the semiconductor device 1 of this embodiment, a support member 60 including a material having a tensile stress is provided in the insulating film 50. For example, a plurality of support members 60 are provided, and the plurality of support members 60 are arranged along the groove T. By providing such a support member 60, the internal stress (compressive stress) due to the insulating film 50 is relieved by the tensile stress of the support member 60, and deformation of the groove T is suppressed. This makes it difficult for voids to be generated in the grooves T1 and T5 of the groove portion T, and the chip 1A is prevented from being damaged due to cracks generated in the chip 1A due to the voids.

For example, as in the steps of FIGS. 11B, 12A, and 12B, the hole H is formed after the groove portion T is formed, and the support member 60 is formed in the hole H. Thereby, it is possible to prevent the grooves T1 and T5 of the groove portion T from being deformed and the air gap from being generated in the grooves T1 and T5. In the step of FIG. 12B, since it is difficult for voids to be generated in the grooves T1 and T5, the embedded member 70 is easily formed in the grooves T1 to T5 of the groove portion T. That is, the embedding property in the groove T1 to the groove T5 of the groove part T is improved. Moreover, since it becomes difficult to generate | occur | produce a space | gap in the groove | channel T1 and the groove | channel T5, a crack generate | occur | produces in the chip | tip 1A and the chip | tip 1A is prevented from being damaged by the space | gap.
According to the present embodiment, a highly reliable semiconductor device and a manufacturing method thereof are provided.

  In the present embodiment, the support member 60 is formed in the hole H, but the support member 60 may not be formed in the hole H. That is, by forming the holes H in the insulating film 50, the internal stress (compressive stress) due to the insulating film 50 is relieved, and the deformation of the trench T is suppressed. This makes it difficult for voids to be generated in the grooves T1 and T5 of the groove portion T, and the chip 1A is prevented from being damaged due to cracks generated in the chip 1A due to the voids.

  As described above, the case where the semiconductor device according to the present embodiment is a three-dimensional semiconductor memory device has been described as an example, but the semiconductor device according to the present embodiment is limited to a three-dimensional semiconductor memory device. I don't mean.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1,100 ... Semiconductor device, 1A ... Chip, 10 ... Board | substrate, 10a ... Upper surface, 15 ... Laminated body, 15t ... End part, 21 ... Electrode film, 21C ... Contact, 21S ... Step, 21T ... Terrace, 22, 50 ... Insulating film, 31 ... Core insulating film, 32 ... Channel, 41 ... Tunnel insulating film, 42 ... Charge storage film, 43 ... Block insulating film, 50R ... Region, 50Rt ... Position point, 55A, 55B ... Insulating member, 60, 60A , 60B ... support member, 70 ... embedding member, CL ... columnar part, DL ... dicing line, H ... hole, MCA, MCA1 ... memory cell array, MH ... memory hole, PC ... peripheral circuit, Rd ... divided region, Rmc ... Cell region, Rs ... peripheral region, ST1, ST1a, ST1b, ST2 ... slit, T, Ta1, Ta2, Ta ... groove, T1T5 ... groove, Tp ... corners, Tp1 ... one end, Tp2 ... the other end, W1 ... width, a1, a2 ... an arrow, b1, b2 ... location points, d1, dt ... distance

Claims (11)

A circuit section;
An insulating portion provided around the circuit portion;
A protective member provided in the insulating portion and provided to surround the circuit portion;
A stress relieving part provided along the protective member in the insulating part;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the stress relieving part includes a material that relieves stress of the insulating part. The insulating part includes silicon oxide,
The semiconductor device according to claim 1, wherein the stress relaxation portion includes at least one of silicon nitride, aluminum oxide, and metal.   The semiconductor device according to claim 1, wherein the circuit unit includes a stacked body having a plurality of electrode films stacked apart from each other.   The semiconductor device according to claim 1, wherein the stress relaxation portion is provided between the circuit portion and the protection member.   The semiconductor device according to claim 1, wherein the stress relaxation portion is provided on both sides of the protection member.   The semiconductor device according to claim 1, wherein the circuit unit includes a memory cell array having a plurality of memory cells and a peripheral circuit. Forming a circuit portion on the substrate;
Forming an insulating portion around the circuit portion;
Forming a stress relaxation portion in the insulating portion;
Forming a protective member in the insulating portion so as to surround the circuit portion;
With
A method for manufacturing a semiconductor device, wherein the stress relaxation portion is formed along the protective member.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the stress relaxation portion includes a step of forming a hole in the insulating portion, and a step of embedding a material for relaxing stress in the insulating portion in the hole. .   The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the protection member includes a step of forming a groove in the insulating portion and a step of embedding the groove. The insulating part includes silicon oxide,
The method of manufacturing a semiconductor device according to claim 8, wherein the stress relaxation part includes at least one of silicon nitride, aluminum oxide, and metal.

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