JP2019166287A - Game machine - Google Patents

Abstract

To provide a game machine capable of executing a preset operation even when a rotation speed of a reel is made to increase or decrease at an optional timing, and stopping a specific pattern at specific timing.SOLUTION: A game machine comprises: pattern position detection means S1604 for detecting a pattern position; pattern position calculation means S1605 for calculating a calculation pattern position; pattern position difference calculation means S1605 for calculating a difference between the pattern position detected by the pattern position detection means and a calculation pattern position calculated by the pattern position calculation means; and rotary speed adjustment means S1606 for adjusting rotation speeds of the plurality of reels according to the difference calculated by the difference calculation means, the rotary speed adjustment means adjusting the rotary speeds of the plurality of reels in a cycle shorter than a cycle in which the plurality of reels rotate one round.SELECTED DRAWING: Figure 128

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachi-slot, comprising a plurality of reels each having a plurality of symbols provided on the surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as “start operation”) after a game medium such as a medal or coin has been inserted into the gaming machine, and the rotation of all reels is detected. Outputs a signal requesting start. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and a symbol combination (display combination) related to the winning of the winning is displayed, a privilege corresponding to the symbol combination is given to the player. As an example of a privilege granted to a player, a replay (hereinafter also referred to as “replay”) in which an internal lottery process is performed again without paying out game media (medals, etc.) or consuming the game media. An operation of a bonus game in which a game medium payout opportunity increases can be cited.

  Conventionally, in the gaming machine having the above-described configuration, a function of navigating the establishment of a specific small role (a role related to payout of game media) with a lamp, that is, an assist time (hereinafter referred to as “AT”) Equipped with a game machine. Conventionally, a game machine having a function of operating a gaming state in which a replay winning probability is higher than normal when a specific symbol combination is displayed, that is, a replay time (hereinafter referred to as “RT”) function has also been developed. Has been. Further, a pachislot having a function of assist replay time (hereinafter referred to as “ART”) in which AT and RT operate simultaneously has been developed.

  The above-mentioned gaming machine is usually equipped with a main control circuit in which a circuit (main control circuit) for controlling the main gaming operation of the gaming machine such as determination of an internal winning combination, rotation and stop of each reel, determination of presence / absence of winning is implemented. A board and a sub-control board on which a circuit (sub-control circuit) for controlling a rendering operation by displaying an image or the like is mounted. The game operation is controlled by a CPU (Central Processing Unit) mounted on the main control circuit. At this time, under the control of the CPU, the program and various table data stored in the ROM (Read Only Memory) of the main control circuit are expanded in the RAM (Random Access Memory) of the main control circuit, and processing related to various game operations is executed. Is done.

JP 2005-342055 A

  By the way, in the above-described conventional gaming machines, advanced effects are performed using reels, display devices, speakers, lamps, etc., and the reels move accurately in synchronization with effects such as images, sounds, and lights. This is extremely important and indispensable for the production to be effective. However, as a reel rotation control process, the reel signal is controlled by the index signal in the conventional gaming machine in which the reel index signal is determined and the motor control of acceleration, constant speed, deceleration, and stop is controlled for each reel. Since control is performed every time (about 0.8 seconds), there is a problem that it takes time to adjust all reel speeds to be synchronized. In addition, since the speed adjustment during the lap cannot be performed, there is a problem that the operation of stopping the designated symbol at an arbitrary timing cannot be performed.

  The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to execute an operation as designed in advance even if the rotation speed of the reel is increased or decreased at an arbitrary timing. It is possible to provide a gaming machine that can stop a specific symbol at a specific timing.

  In order to solve the above problems, the present invention provides a gaming machine having the following configuration.

A plurality of reels (3L, 3C, 3R) arranged with a plurality of symbols,
A symbol changing means (stepping motor) for changing the plurality of symbols by rotating the plurality of reels;
A symbol position detecting means (reel position detector) for detecting a symbol position;
A symbol position calculating means for calculating a calculated symbol position (reel rotation speed calculation process executed by the main CPU 101);
Symbol position difference calculation means (reel rotation speed calculation processing executed by the main CPU 101) for calculating a difference between the symbol position detected by the symbol position detection means and the calculated symbol position calculated by the symbol position calculation means; ,
Rotation speed adjustment means (reel rotation speed calculation processing executed by the main CPU 101) for adjusting the rotation speed of the plurality of reels according to the difference calculated by the symbol position difference calculation means;
The gaming machine characterized in that the rotation speed adjusting means adjusts the rotation speed of the plurality of reels in a cycle shorter than a cycle in which the plurality of reels make one rotation.

  With this configuration, the virtual reel is operated by a program separately from the actual reel, the deviation (difference) from the operation state of the virtual reel is calculated when the reel is stopped, and the rotation speed of the reel is adjusted according to the calculated deviation. However, since it is performed every cycle that is shorter than the cycle in which the reel makes one rotation, it is possible to execute an operation as designed in advance even if the rotational speed of the reel is increased or decreased at an arbitrary timing. In addition, the object of the present invention of “stopping a specific symbol at a specific timing” can be achieved.

  In the gaming machine of the present invention, the rotation speed adjusting means may adjust the rotation speeds of the plurality of reels with a period of less than a predetermined time (for example, 1.1172 milliseconds).

  With this configuration, the rotation speed of the reel is adjusted at a high frequency of 10 times or more per second, so that the accuracy of adjusting the rotation speed of the reel can be improved and the effectiveness thereof can be better secured.

In the gaming machine of the present invention,
The symbol position calculation means may calculate the calculation symbol position by simulating the reel with software.

  With this configuration, the virtual reel of the symbol position calculating means can be realized by software, so that no additional hardware parts are required for the gaming machine, and therefore the gaming machine can be downsized and the manufacturing cost can be reduced. Furthermore, it is possible to respond flexibly to changes in specifications.

  According to the gaming machine of the present invention configured as described above, it is possible to execute an operation as designed in advance even if the reel rotation speed is increased or decreased at an arbitrary timing, and at a specific timing. A gaming machine capable of stopping a specific symbol can be provided.

It is a figure for demonstrating the function flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a block diagram which shows the whole circuit structure with which the game machine of one Embodiment of this invention is provided. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub control circuit in one Embodiment of this invention. It is a block diagram of the various registers | resistors which the main CPU in one Embodiment of this invention has. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the bonus state and non-bonus state of a pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the ART game state of a pachislot in one Embodiment of this invention, a non-ART game state, and a bonus state. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and stop symbol combination in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and stop symbol combination in one Embodiment of this invention. It is a figure which shows an example of the reel stop initial setting table in one Embodiment of this invention. It is a figure which shows an example of the drawing priority order table in one Embodiment of this invention. It is a figure which shows the structure (the 1) of the winning request flag storage area | region and winning operation flag storage area | region in one Embodiment of this invention. It is a figure which shows the structure (the 2) of the winning request flag storage area | region and winning operation flag storage area | region in one Embodiment of this invention. It is a figure which shows (the 3) of the winning request flag storage area | region and the winning action flag storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the carryover combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation | movement stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the corresponding table (the 1) with the internal winning combination and subflag in one Embodiment of this invention. It is a figure which shows the corresponding table (the 2) with the internal winning combination and subflag in one Embodiment of this invention. It is a figure for demonstrating alerting | reporting operation | movement when subflag EX "triple chili lip" or "reach eye lip" wins in the gaming machine of one embodiment of the present invention. It is a figure for demonstrating the flow of the game in the general game state in one Embodiment of this invention. It is a figure which shows an example of the normal medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ lottery table in one Embodiment of this invention. It is a figure which shows an example of the mode up lottery table in CZ1 in one Embodiment of this invention. It is a figure which shows an example of the point lottery table in CZ2 in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ1, CZ2) in CZ in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ3) in CZ in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in normal ART in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table during ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART medium high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of CT lottery table during ART in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table during normal ART in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in CT state in one Embodiment of this invention. It is a figure which shows an example of the table lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table during CT in one Embodiment of this invention. It is a figure which shows an example of the lot number table on the number of sets in CT in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the bonus state in one Embodiment of this invention. It is a figure which shows an example of the bonus classification lottery table in one Embodiment of this invention. It is a figure which shows an example of the lottery table on the number of bonus ART games in one Embodiment of this invention. It is a figure which shows an example of CT lottery table at the time of bonus end in one Embodiment of this invention. It is a figure for demonstrating the flow of the game (others) in the general game state in one Embodiment of this invention. It is a figure which shows an example of the non-ART flag conversion lottery table in one Embodiment of this invention. It is a figure which shows the correspondence of the main side navigation data and sub side navigation data in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of power-on (reset interruption) performed by the main control circuit of the gaming machine in one embodiment of the present invention. It is a flowchart which shows the example of the game return process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command production | generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of a power failure (external) in one Embodiment of this invention. It is a flowchart which shows the example of the checksum production | generation process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a flowchart which shows the example of the main process (main operation process) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error process in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compression data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the control process classified by state in one Embodiment of this invention. It is a flowchart which shows the example of the subflag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the navigation set process in one Embodiment of this invention. It is a flowchart which shows the example of the flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of a normal start in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the start in CZ in one Embodiment of this invention. It is a flowchart which shows the example of the process in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the process in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the process in CZ3 in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of start in normal ART in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of CT start in one Embodiment of this invention. It is a flowchart which shows the example of CT lottery processing in CT in one Embodiment of this invention. It is a flowchart which shows the example of the table data acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the 1 byte lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of BB start in one Embodiment of this invention. It is a flowchart which shows the example of the attraction | saving priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the AND operation process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control process in one Embodiment of this invention. It is a flowchart which shows the example of the winning search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of a prize check and medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the BB check process in one Embodiment of this invention. It is a flowchart which shows the example of the RT check process in one Embodiment of this invention. It is a flowchart which shows the example of the RT check process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of CZ * ART completion | finish in one Embodiment of this invention. It is a flowchart which shows the example of the interruption process performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment LED drive processing in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment display data generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is the schematic explaining the concept of the data decompression | decompression process performed in FIG. 115 in one Embodiment of this invention. It is a flowchart which shows the procedure of the data decompression | decompression process in one Embodiment of this invention. It is the schematic which shows the example which applied the data decompression process performed in FIG. 115 in one Embodiment of this invention to the symbol arrangement | positioning table. It is a figure which shows the reel control data storage area in one Embodiment of this invention. It is a table | surface which shows the judgment criteria of the detection of the off edge of an index sensor in one Embodiment of this invention, or an on edge. It is a figure which shows an example of the sequence data selection table (a), sequence data table (b), and excitation data table (c) in one Embodiment of this invention. It is an example of the flowchart of the virtual reel control process performed in the interruption process (1.1172 ms) in one Embodiment of this invention. It is an example of the flowchart of the reel control process performed in the interruption process (1.1172 ms) in one Embodiment of this invention. It is an example of the flowchart of the acceleration preparation 1 process in one Embodiment of this invention. It is an example of the flowchart of the acceleration preparation 2 process in one Embodiment of this invention. It is an example of the flowchart of the process during a stop in acceleration in one Embodiment of this invention. It is an example of the flowchart of the end code process in one Embodiment of this invention. It is an example of the flowchart of the stop code process in one Embodiment of this invention. It is an example of the flowchart of the reel rotational speed calculation process in one Embodiment of this invention. It is an example of the flowchart of the constant speed waiting and constant speed processing in one embodiment of the present invention. It is an example of the flowchart of the symbol position update process in one Embodiment of this invention. It is an example of the flowchart of the stop start position waiting process in one Embodiment of this invention. It is an example of the flowchart of the all-phase OFF process in one Embodiment of this invention. It is an example of the flowchart of the excitation output process in one Embodiment of this invention.

  Hereinafter, a pachislot machine is taken as an example of a gaming machine according to an embodiment of the present invention, and the configuration and operation thereof will be described with reference to the drawings. In the present embodiment, a pachislot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot will be described with reference to FIG. In the pachislot machine of this embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as game media.

  When a player inserts a medal into the pachislot and operates the start lever, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is one of various processing means (processing functions) provided in a main control circuit described later. By determining the internal winning combination, a combination of symbols that permits display along an after-mentioned effective line (winning determination line) is determined. The types of symbol combinations include those related to “winning” in which benefits such as payout of medals, replay (replay) operation, bonus operation, etc. are given to the player, and so-called “out of” other than that. Such a thing is provided. In the following, a combination relating to the payout of medals is referred to as a “small combination”, and a combination relating to replay (replay) operation is referred to as a “replay combination”. In addition, a combination related to a bonus operation (bonus game) is also referred to as a “bonus combination”.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is one of various processing means (processing functions) provided in a main control circuit described later.

  In the pachi-slot, basically, control for stopping the rotation of the corresponding reel is performed within a specified time (190 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. In the present embodiment, when the specified period is 190 msec, the maximum number of sliding symbols (maximum number of sliding symbols) is determined for four symbols.

  The reel stop control means, when the internal winning combination permitting the symbol combination display related to the winning is determined, normally, the symbol combination is placed on the active line within a specified time of 190 msec (four symbols). The rotation of the reel is stopped so as to display as much as possible. In addition, the reel stop control means stops the rotation of the reel using a specified time so that the combination of symbols that are not permitted to be displayed by the internal winning combination is not displayed along the active line.

  In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the active line relates to winning. This winning determination means is also one of various processing means (processing functions) provided in the main control circuit described later. Then, when the combination of the displayed symbols is determined to be related to winning by the winning determination means, a bonus such as a medal payout is given to the player. In the pachislot, a series of flows as described above is performed as one game (unit game).

  Also, in the pachislot, in the series of gaming operations described above, various effects can be achieved by displaying images on a display device, outputting light from various lamps, outputting sound from a speaker, or a combination thereof. Is done.

  Specifically, when the start lever is operated, a random number value for presentation is extracted separately from the random number value used for determining the internal winning combination described above. When the effect random number is extracted, the effect content determination means determines the effect to be executed this time from lots of effect contents associated with the internal winning combination by lottery. This effect content determination means is one of various processing means (processing functions) provided in a sub-control circuit described later.

  Next, when the content of the effect is determined by the effect content determination means, the effect execution means responds in conjunction with each opportunity such as when the rotation of the reel starts, when the rotation of each reel stops, or when the presence or absence of a prize is determined. Execute. In this way, in the pachislot, for example, by executing the production contents associated with the internal winning combination, there is an opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) It is provided to the player and the player's interest can be improved.

<Pachislot structure>
Next, the structure of a pachislot machine according to an embodiment of the present invention will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachislot 1 includes an exterior body (game machine main body) 2. The exterior body 2 includes a cabinet 2a that houses a reel, a circuit board, and the like, and a front door 2b that is attached so that the opening of the cabinet 2a can be opened and closed.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display columns) are provided in a horizontal row. Hereinafter, the reels 3L, 3C, and 3R (main reels) are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (reel rotation direction).

  The front door 2 b includes a door body 9, a front panel 10, a waist panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachi-slot 1.

  The front panel 10 is provided on the upper portion of the door body 9. The front panel 10 is constituted by a frame-like member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is disposed to face a display device 11 described later disposed inside the cabinet 2a.

  The display device cover 30 is formed of a black translucent synthetic resin. Therefore, the player can visually recognize the video (image) displayed on the display device 11 described later via the display device cover 30. In the present embodiment, the display device cover 30 is formed of a black translucent synthetic resin, thereby suppressing the entry of external light into the cabinet 2a and the image (image) displayed by the display device 11. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21 a and 21 b provided on the upper portion of the front panel 10 when viewed from the player side. Each of the lamps constituting the lamp group 21 is composed of an LED (Light Emitting Diode) or the like (see LED group 85 in FIG. 5 described later), and turns on and off the light in a pattern corresponding to the content of the effect.

  The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 includes a decorative panel on which an arbitrary image is drawn, and a light source (LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal portion 13 is provided between the front panel 10 and the waist panel 12. The pedestal 13 includes a symbol display area 4 and various devices (medal slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, three stop buttons 17L, 17C, and the like to be operated by the player. 17R, a settlement button (not shown), and the like.

  The symbol display area 4 is an area that overlaps with the three reels 3L, 3C, and 3R when viewed from the front, and is arranged at a position closer to the player than the three reels 3L, 3C, and 3R. 3L, 3C, 3R has a size that enables visual recognition. The symbol display area 4 functions as a display window, and is configured so that each reel 3L, 3C, 3R provided behind the display window 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped, the reel display window 4 is continuously arranged among a plurality of symbols provided on the peripheral surface of each reel. Two symbols are displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, one symbol (three in total) is placed in each of the upper, middle, and lower regions for each reel within the frame of the reel display window 4. ) Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). In the present embodiment, a pseudo line (center line) connecting the middle stage area of the left reel 3L, the middle stage area of the middle reel 3C, and the middle stage area of the right reel 3R within the frame of the reel display window 4, It is defined as an effective line for determining whether or not a prize is won.

  The reel display window 4 is formed by an opening of a frame member 31 provided on the pedestal portion 13. A substantially horizontal plane base region is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, a medal slot 14 is provided on the right side of the pedestal area, and a MAX bet button 15a and a 1 bet button 15b are provided on the left side.

  The medal slot 14 is provided to accept a medal dropped on the pachislot 1 from the outside by the player. The medals accepted from the medal slot 14 are used for one game up to a predetermined number (for example, three) set in advance, and the number of medals exceeding the predetermined number are deposited inside the pachislot 1. (So-called credit function (game medium storage means)).

  The MAX bet button 15a and the 1 bet button 15b are provided for determining the number of coins used for one game from medals deposited in the cabinet 2a. Note that a bet button LED (not shown) that is lit when a medal can be inserted is provided inside the MAX bet button 15a. The checkout button is provided to draw out (discharge) medals deposited inside the pachislot machine 1 to the outside.

  When the player depresses the MAX bet button 15a, medals corresponding to the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, each time the 1-bet button 15b is pressed, one medal is inserted. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the active line is activated.

  Hereinafter, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting a medal into the medal insertion slot 14 (operation of inserting a medal for playing a game) are all referred to as “insertion operation”.

  The start lever 16 is provided to start rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  In addition, an information display 6 is provided in the approximate center of the pedestal region on a substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

  The information display 6 has a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player as a privilege (hereinafter referred to as “paid-out number”). (Hereinafter referred to as “7-segment LED”) and information such as the number of medals deposited inside the pachislot machine 1 (hereinafter referred to as “credit number”) for digital display (notification) to the player A 2-digit 7-segment LED is provided. In this embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) information about the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of paid-out medals is switched from the display mode of the paid-out number to the display mode of the error type information.

  Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on a stop operation necessary for displaying a symbol combination corresponding to the combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a two-digit 7-segment LED. The instruction monitor informs the player of necessary stop operation information by turning on, blinking, or turning off the 2-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. To do.

  Note that the aspect uniquely corresponding to the information of the stop operation to be notified here is, for example, in the case of informing the pressing order “1st (perform the first stop operation on the left reel 3L)”. When the numerical value “1” is displayed on the instruction monitor and the push order “2nd (perform the first stop operation on the middle reel 3C)” is notified, the numerical value “2” is displayed on the instruction monitor and the push order In a case where “3rd (perform the first stop operation on the right reel 3R)” is notified, a numerical value “3” is displayed on the instruction monitor. In addition, the notification mode (navigation data determined on the main side described later) of the stop operation information on the instruction monitor will be described in detail later with reference to FIG. 61 described later.

  The information display 6 is electrically connected to the main control board 71 via a door relay board 68 and a game operation display board 81 as shown in FIG. 5 described later. The display operation of the information display 6 is controlled by the main control board. It is controlled by a later-described main control circuit 90 in the substrate 71. Moreover, the control method of the various 7-segment LEDs described above is dynamic lighting control.

  In the pachislot machine 1 of this embodiment, in addition to the instruction monitor controlled by the main control board 71, a configuration for notifying the stop operation information using other means controlled by the sub control board 72 is provided. Specifically, information on a stop operation is notified by a display device 11 described later configured by a projector mechanism 211 and a display unit 212 (see FIG. 3 and FIG. 5 described later).

  When such a configuration is applied, the notification mode in the instruction monitor and the notification mode in other means controlled by the sub-control board 72 may be different from each other. That is, the instruction monitor may be notified in a manner that uniquely corresponds to the information on the stop operation to be notified, and does not necessarily need to notify the information on the stop operation directly (for example, the numerical value “1” in the instruction monitor). Even if is displayed, there is a possibility that the notification content cannot be specified depending on the player, which is not a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, information on the stop operation may be directly notified. For example, when the push order “1st” is notified, the instruction monitor displays a numerical value “1” that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11) displays the left reel 3L. The instruction information for performing the first stop operation may be directly notified.

  In the pachislot machine 1 configured as described above, not only the control of the sub-control board 72 but also the control of the main control board 71 can notify information on necessary stop operation according to the internal winning combination. In addition, the presence / absence of notification of such stop operation information may be controlled according to the gaming state. For example, in a general gaming state (non-ART gaming state) described later, stop operation information may be notified in a later-described ART gaming state (see FIG. 12 described later) without notifying the stop operation information.

  Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand substantially vertically from a pedestal region in a substantially horizontal plane of the pedestal portion 13 in the front surface portion of the door body 9. The sub display device 18 includes a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various types of information.

  Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 5 described later). The touch sensor 19 operates in accordance with a predetermined operation principle such as a capacitance method, and when a player's operation is accepted, outputs a signal corresponding to the operation as touch input information. The pachislot machine 1 according to the present embodiment has a function that allows the display of the sub display device 18 to be switched in accordance with the player's operation received via the touch sensor 19 (touch input information output from the touch sensor 19). Have The sub display device 18 is controlled by a later-described sub control board 72 (see FIG. 5 described later) based on touch input information output from the touch sensor 19.

  In the lower part of the door body 9, a medal payout opening 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout port 24 guides medals discharged by driving a medal payout device 51 described later to the outside. The medal tray 25 stores medals discharged from the medal payout opening 24. Sounds such as sound effects and music corresponding to the contents of the effects are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the back side of the front door 2b.

  As shown in FIG. 3, the cabinet 2a includes a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. And the display apparatus 11 is arrange | positioned in the upper part in the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection member 212a onto which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, in the display device 11, image light is generated based on the position (projection distance, angle, etc.) and shape of the projection member 212a that is a three-dimensional object, and the image light is projected by the projector mechanism 211 to the projection member. Projected onto the surface of 212a. By providing such an effect function, an advanced and powerful effect can be performed. Although not shown in FIG. 3, another projected member with a curved display surface is provided on the back side of the box-shaped projected member 212 a, and either one of the projected members is provided depending on the gaming state. Used as a screen on which image light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the projection target member in accordance with the gaming state.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are disposed in the lower part of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 can store a large amount of medals and can discharge them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds 50, for example, or when the settlement button is pressed and settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

  The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 includes a power switch 53a and a power supply board 53b (power supply means) (see FIG. 5 described later). The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device (not shown) into the power of the DC voltage necessary for each part, and supplies the converted power to each part.

  Further, a sub control board case 57 for accommodating a sub control board 72 (see FIG. 5 described later) is disposed above the power supply device 53 in the cabinet 2a. A sub control circuit 72 (see FIG. 8 described later), which will be described later, is mounted on the sub control board 72 housed in the sub control board case 57. The sub-control circuit 200 is a circuit that controls the execution of effects by displaying images. A specific configuration of the sub control circuit 200 will be described later.

  A sub-relay board 61 is disposed above the sub-control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which wiring for connecting the sub control board 72 and a main control board 71 described later is mounted. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72, a board disposed around the sub-control board 72, various devices (units), and the like is mounted.

  Although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 5 described later) is disposed in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 5 described later), a hopper device 51, a game medal auxiliary storage switch 77 (see FIG. 5 described later), and a medal payout count switch (not shown). Is a relay board on which wiring for connecting is mounted.

  As shown in FIG. 4, a middle door 41 is disposed at the center of the rear side of the front door 2b, and the reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, and 3R are attached to the reel display window 4 side of the middle door 41, and main control is performed on the opposite side of the middle door 41 from the reel display window 4 side. A main control board case 55 in which a board 71 (see FIG. 5 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R through gears having a predetermined reduction ratio.

  The main control board 71 accommodated in the main control board case 55 has a main control circuit 90 (see FIG. 7 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of each of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. . In the present embodiment, the main control circuit 90 also performs control such as lottery processing for determining whether ART is determined, processing for displaying navigation information on an instruction monitor, and processing for transmitting various test signals. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back side of the front door 2b. The speakers 65L and 65R are disposed at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

  A selector 66 and a door open / close monitoring switch 67 are disposed above the speaker 65L. The selector 66 is a device for selecting whether or not the medal material and shape are appropriate, and guides the appropriate medal inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that an appropriate medal has passed is provided on the path through which the medal passes in the selector 66.

  The door open / close monitoring switch 67 is disposed diagonally to the left of the selector 66 when the front door 2b is viewed from the back side. The door opening / closing monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachislot 1.

  Although not shown in FIG. 4, a door relay terminal plate 68 is disposed in the area where the front door 2 b is opened and closed by the middle door 41 on the back surface and below the reel display window 4 (see below). 5). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub-relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, This is a relay board on which wiring for connecting each of the second interface boards 302 for the testing machine is mounted. Examples of the various buttons and switches include a MAX bet button 15a, a 1 bet button 15b, a door open / close monitoring switch 67, a BET switch 77 described later, a start switch 79, and the like.

<Control system for pachislot>
Next, a control system provided in the pachislo 1 will be described with reference to FIG. FIG. 5 is a circuit block diagram showing the configuration of the control system of the pachi-slot 1.

  The pachi-slot 1 includes a main control board 71 provided on the middle door 41 and a sub-control board 72 provided on the front door 2b. The pachi-slot 1 includes a reel relay terminal board 74, a setting key switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot 1 includes an external concentration terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via the cabinet-side relay board 44. In addition, since the structure of the hopper apparatus 51 was mentioned above, the description is abbreviate | omitted here.

  The reel relay terminal plate 74 is disposed inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal board 74 is electrically connected to stepping motors (not shown) of the reels 3L, 3C, 3R, and relays signals output from the main control board 71 to the stepping motors.

  The setting key type switch 54 is provided on the main control board case 55. The setting key switch 54 is used when changing the setting (setting 1 to setting 6) of the pachi-slot 1 or when checking the setting of the pachi-slot 1.

  The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external concentration terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. It is. The external concentration terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52 and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot 1.

  The power supply device 53 includes a power supply board 53b and a power switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot 1. The power supply board 53 b is connected to the main control board 71 via the cabinet side relay board 44 and also connected to the sub control board 72 via the sub relay board 61.

  The pachislot machine 1 includes a door relay terminal plate 68, a selector 66, a door open / close monitoring switch 67, a BET switch 77, a checkout switch 78, which are connected to the main control board 71 via the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub-relay board 61, a first testing machine interface board 301, and a second testing machine interface board 302. Since the selector 66, the door opening / closing monitoring switch 67, and the sub relay board 61 have been described above, the description thereof is omitted here.

  The BET switch 77 (insertion operation detecting means) detects that the MAX bet button 15a or the 1 bet button 15b has been pressed by the player. The settlement switch 78 detects that a settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

  The stop switch substrate 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stopable main reel by an LED or the like. The stop switch substrate 80 is provided with a stop switch (not shown). The stop switch detects that each stop button 17L, 17C, 17R has been pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 includes, for example, three LEDs for displaying the number of inserted medals (hereinafter referred to as “first LED” to “first LED”) that are turned on in correspondence with the number of medals inserted in the current game (hereinafter referred to as “inserted number”). LED for lighting a medal insertion mark, a game start mark, a replay mark, etc. based on a signal input from the game operation display board 81) Etc. are included. In the first to third LEDs (display means), when one medal is inserted, the first LED is turned on, and when two medals are inserted, the first and second LEDs are turned on, and three medals (game) When the startable number of sheets is inserted, the first to third LEDs are turned on. Since the information display device 6 has been described above, the description thereof is omitted here.

  Both the first interface board 301 for testing machine and the second interface board 302 for testing machine are relay boards used when various signals relating to games are output to the testing machine in the pachislot 1 certification test (trial test) ( Since these relay boards are not mounted on the pachislot machine 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for testing machine and the testing machine. Various electronic components necessary for connecting to the second interface board 302 are also not mounted). For example, a test signal for controlling a main operation related to the game (for example, internal lottery, reel stop control, etc.) is output via the first interface board 301 for testing machine, and is determined by the main control board 71, for example. A test signal or the like related to the pushed push navigation is output via the second interface board 302 for the testing machine.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. The pachislot machine 1 includes a speaker group 84, LED groups 85, a 24h door opening / closing monitoring unit 63, a touch sensor 19, and a display unit 212, which are connected to the sub control board 72 via the sub relay board 61. Since the touch sensor 19 has been described above, the description thereof is omitted here.

  The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10 and a light source that emits light for illuminating the decorative panel of the waist panel 12 from the back side. The 24h door opening / closing monitoring unit 63 stores opening / closing history information of the middle door 41. Further, the 24h door opening / closing monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projection target 212a constituting the display device 11, and another projection target with a curved display surface provided on the back side of the projection target 212a.

  The pachi-slot 1 also includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub control substrate 72. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are housed in the sub control board case 57 together with the sub control board 72.

  The ROM cartridge substrate 86 is a substrate for managing various control programs executed by the sub CPU 102, production images (videos), sound (speaker groups 84), light (LED groups 85), and communication data. . The liquid crystal relay substrate 87 is a substrate that relays connection wiring between the sub control substrate 72, the projector mechanism 211 constituting the display device 11, and the sub display device 18. Since the projector mechanism 211 and the sub display device 18 have been described above, the description thereof is omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 6 is a block diagram illustrating a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

  The microprocessor 91 is a microprocessor with a security function for gaming machines.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

  The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 5). The power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the startup voltage value (10V) from 0V). When a power interruption occurs (when the power supply voltage falls below the power failure voltage value (10.5 V) from 12 V), a power interruption detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (start signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means to output (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (DC power supply voltage of 5 V DC) for the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 7 is a block diagram showing the internal configuration of the microprocessor 91.

  The microprocessor 91 includes a main CPU 101, a main ROM 102 (control data storage means, first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 105, The arithmetic circuit 107, random number circuit 110, parallel port 111, interrupt controller 112, timer circuit 113, first serial communication circuit 114, and second serial communication circuit 115 are included. These units constituting the microprocessor 91 are connected to each other via a signal bus 116.

  The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 and performs control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  The main CPU 101 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, 3L (main reel) after detecting the reel index. Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. The reel index includes, for example, an optical sensor having a light emitting unit and a light receiving unit, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting unit and the light receiving unit by the rotation of each main reel. It is detected by a provided reel position detector (not shown).

  Here, management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Each time the output of a predetermined number of pulses necessary for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is incremented by one. A symbol counter is provided for each reel. The value of the symbol counter is cleared when a reel index is detected by a reel position detector (not shown). The reel position detector constitutes “symbol position detecting means”.

  In other words, in the present embodiment, by managing the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG.

  The external bus interface 104 is for electrically connecting an external signal bus (not shown) to which various components (for example, each reel) provided outside the microprocessor 91 are connected to the microprocessor 91. It is an interface circuit. The clock circuit 105 includes, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is received by other components (for example, the timer circuit 113). Convert to a clock pulse signal of the frequency used. Note that the clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or WDT (watchdog timer) based on the reset signal input from the power management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit.

  The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 generates a random number register 0 for obtaining a 2-byte hard latch random number, random number registers 1 to 3 for obtaining a 2-byte soft latch random number, and a 1-byte soft latch random number. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from a predetermined range of random numbers generated by the random number circuit 110, for example, as a random value for internal lottery. The parallel port 111 is a port (memory map I / O) for signals input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93) provided outside the microprocessor 91. . The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to one of the input ports PI0 to PI4 of the parallel port 111, and the latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110 at a timing (on edge) when the start switch 79 is turned on. Is output. In the random number circuit 110, when the latch signal is input, the random number register 0 is latched, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs an interrupt process by the main CPU 101 based on a power interruption detection signal input from the power management circuit 93 via the parallel port 111 or a time-out signal input from the timer circuit 113 at a cycle of 1.1172 ms. Control the execution timing of. When a power failure detection signal is input from the power management circuit 93 or a time-out signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. Based on the interrupt request signal input from the interrupt controller 112 in response to the time-out signal from the timer circuit 103, the main CPU 101 performs input port check processing, reel control processing, communication data transmission processing, 7-segment LED drive processing, timer Various interrupt processing such as update processing (see FIG. 110 described later) is performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (clock pulse signal having a frequency obtained by dividing a clock pulse signal for operating the main CPU by a frequency divider (not shown)). Count elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) is transmitted from the main control board 71 to the sub-control board 72. The second serial communication circuit 115 is a circuit that controls a serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Sub control circuit>
Next, the configuration of the sub control circuit 200 (sub control means) mounted on the sub control board 72 will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration example of the sub control circuit 200 of the pachislot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 90. The sub control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge substrate 86. The driver 205 is connected to the liquid crystal relay substrate 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  In the program storage area, a control program executed by the sub CPU 201 is stored. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random number value for production are extracted, and production registration for determining and registering production contents (production data). Various programs for executing tasks are included. In addition, the control program includes a drawing control task for controlling the display of video by the display device 11 based on the determined content of the presentation, a lamp control task for controlling the output of light from a light source such as the LED group 85, and a sound by the speaker group 84. Various programs for executing a voice control task or the like for controlling the output of the program are also included.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to creation of video. Further, the data storage area includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a light on / off pattern, and the like.

  The sub RAM 202 is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create a video according to the animation data designated by the contents of the presentation, and display the created video on the display device 11 (projector mechanism 211) and / or Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the contents of the effect. Further, the sub CPU 201 controls lighting and extinguishing of the LED group 85 according to the lamp data designated by the contents of the effect.

<Various registers of main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. FIG. 9 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 includes, as main registers, an accumulator A (hereinafter referred to as “A register”), a flag register F (flag register), a general purpose register B (hereinafter referred to as “B register”), and a general purpose register C (hereinafter referred to as “register A”). General purpose register D (hereinafter referred to as “D register”), general purpose register E (hereinafter referred to as “E register”), general purpose register H (hereinafter referred to as “H register”) and general purpose register L (hereinafter referred to as “C register”). , Referred to as “L register”). Further, the main CPU 101 includes, as sub registers, an accumulator A ′, a flag register F ′, a general purpose register B ′, a general purpose register C ′, a general purpose register D ′, a general purpose register E ′, a general purpose register H ′, and a general purpose register L ′. As a general purpose register. Each register is composed of a 1-byte register.

  In this embodiment, the B register and the C register are used as a pair register (hereinafter referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter referred to as “DE register”). Furthermore, in this embodiment, the H register and the L register are used as a pair register (hereinafter referred to as “HL register”).

  As shown in FIG. 9, predetermined flag information indicating the result of the arithmetic processing is set in each bit of the flag registers F and F ′. For example, in bit 6 (D6), data (zero flag) indicating whether or not the calculation result is “0” in the calculation result determination process is set. Specifically, when the operation result is “0”, data “1” is set in bit 6, and when the operation result is not “0”, data “0” is set in bit 6. In the calculation result determination process, the main CPU 101 performs determination (YES / NO) with reference to the data “0” / “1” of bit 6.

  The main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is composed of a 1-byte register. In the present embodiment, in various instruction codes dedicated to the main CPU 101 that specify an address using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. In the Q register, “F0H” is set as an initial value immediately after the main CPU 101 is reset.

  Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R configured by 1-byte registers, and an index register IX and an index register IY configured by 2-byte registers. The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configuration of the main ROM 102 and the main RAM 103 (hereinafter referred to as “memory map”) included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 10A to 10C. 10A is a diagram showing a memory map of the entire memory, FIG. 10B is a diagram showing a memory map of the main ROM 102, and FIG. 10C is a diagram showing a memory map of the main RAM 103.

  In the memory map of the entire memory provided in the main control circuit 90 (microprocessor 91), as shown in FIG. 10A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, The XCS decode areas are arranged at predetermined addresses in this order with an unused area in between.

  In the memory map of the main ROM 102, as shown in FIG. 10B, from the head (0000H) side of the address of the main ROM 102, there are a program area, a data area, an unspecified area, a trademark recording area, a program management area, and a security setting area. In order, they are arranged at predetermined addresses.

  In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to game playability performed by the player are stored. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, various sub-control circuits 42, etc.) in various control processes related to game playability performed by the player. Data for transmitting a control command (command), etc.) are stored. In other words, the game ROM area (game storage area) composed of a program area and a data area is necessary for control processing (game-related processing) related to game playability actually performed by the player at the game store. Various programs and various data are stored.

  The non-regulated area stores control programs and data for various processes (processes that do not affect the game characteristics) that are not directly related to the game performance of the game executed by the player. For example, a program and data used in a pachislot 1 certification test (trial test), a control program and data used in checksum generation processing at power interruption or sum check processing at power recovery, and a fraud countermeasure program In addition, data necessary for the data and the like are stored in an unspecified area.

  In the memory map of the main RAM 103, as shown in FIG. 10C, from the head (F000H) side of the address of the main RAM 103, a gaming RAM area (predetermined storage area, gaming temporary storage area) and an unspecified RAM area (unspecified temporary area). Storage areas) are arranged at predetermined addresses in this order.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the game performance of the game executed by the player. . Each of the various data is stored in a work area at a predetermined address in the game RAM area.

  In addition, the non-specified RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the game performance of the game executed by the player, and a non-standard stack. In the present embodiment, various processes that are not directly related to the game playability of the game executed by the player, such as a sum check process, are executed using the non-regulated RAM area.

  As described above, in the pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes that are not directly related to the game performance of the game performed by the player are stored in the main ROM 102. The data is stored in a non-standard ROM area (non-standard storage area) arranged at an address different from the ROM area. In addition, various processes that are not directly related to game playability performed by such a player are performed in the main RAM 103 using an unspecified RAM area that is arranged at an address different from the game RAM area. .

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually played by the player are placed in the ROM area (non-specified ROM area) where it is impossible to place a program or the like according to the conventional rules. can do. Therefore, in this embodiment, compression of the capacity of the game ROM area can be avoided.

<Game state transition flow>
Next, various game states managed by the main control circuit 90 (main CPU 101) of the pachi-slot 1 of this embodiment and the transition flow thereof will be described with reference to FIGS. FIG. 11A is a transition flow diagram of the basic gaming state of the pachislot 1, and FIG. 11B is a table summarizing the transition conditions of the gaming state. FIG. 12A is a game state transition flow diagram in consideration of whether or not the notification (ART) function is activated, and FIG. 12B is a table summarizing the game state transition conditions.

[Basic game state transition flow]
In the pachi-slot 1 of the present embodiment, a big bonus (hereinafter referred to as “BB”) is provided as a type of bonus game. BB is an accessory continuous operation device related to a regular bonus (hereinafter referred to as “RB”) called a first type special accessory, and continuously operates the RB.

  Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on whether or not the bonus combination is won / actuated (winning). Specifically, as shown in FIG. 11A, the main control circuit 90 determines whether or not a bonus combination (internal winning combination of names “F_BB1” and “F_BB2” described later) is won / actuated (winning). Three types of gaming states called “bonus non-winning state”, “inter-flag state” and “bonus state” are managed.

  Note that the bonus non-winning state is a state where the bonus is non-winning and the bonus is not activated (winning), and the bonus state is a state where the bonus is activated. In this embodiment, when a bonus combination is determined as an internal winning combination, a state in which the bonus combination is carried over as an internal winning combination over a plurality of games until the bonus is won is generated. The inter-flag state is a state where the bonus combination is carried over as an internal winning combination, that is, a state where the bonus combination is won and the bonus is not activated.

  Whether or not the bonus combination is won is determined by the data stored in the later-described hit request flag storage area (see FIGS. 26 to 28 described later) and the carryover combination storage area (see FIG. 29 described later) provided in the main RAM 103. Managed based on. Further, whether or not a bonus is activated (winning) is managed based on data stored in a game state flag storage area (described later in FIG. 30) provided in the main RAM 103.

  Further, in the present embodiment, as shown in FIG. 11A, in the gaming state where the bonus is not activated (bonus non-winning state and inter-flag state), the type of internal winning combination related to replay and the winning probability thereof are different from each other. Six types of states, RT0 gaming state to RT5 gaming state (hereinafter referred to as “RT0 state” to “RT5 state”, respectively), are provided. The RT0 state, the RT2 state, and the RT5 state are gaming states in which the probability that a replay role is determined as an internal winning combination is low, and the RT1 state has a medium probability that a replay role is determined as an internal winning combination. It is a gaming state with a medium probability. The RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is one of the RT0 state to the RT4 state, and the RT state in the inter-flag state is the RT5 state.

  Therefore, in this embodiment, the main control circuit 90 is further based on the type of internal winning combination related to replay and its winning probability in a gaming state where the bonus is not activated (bonus non-winning state and inter-flag state). Thus, six types of states from the RT1 state to the RT5 state are also managed.

  The RT0 state to the RT5 state are managed based on data stored in a game state flag storage area (described later in FIG. 30) provided in the main RAM 103. Specifically, in the pachislot machine 1 of the present embodiment, five flags indicating the RT state of the RT1 state flag to the RT5 state flag are provided, and the on / off state of these flags is managed by the main RAM 103, thereby the RT state. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag that is in the on state as the current RT state. When all the RT state flags are in the off state, the main control circuit 90 specifies that the current RT state is the RT0 state.

  As shown in FIGS. 11A and 13B, when a bonus combination (an internal winning combination with names “F_BB1” and “F_BB2” described later) is determined as an internal winning combination in the bonus non-winning state (when the transition condition (1) is satisfied). ), The main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. When the bonus combination wins in the inter-flag state (when the transition condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

  Further, when medals exceeding the prescribed number (216) are paid out in the bonus state and the bonus state is terminated (when the transition condition (3) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the RT1 state ( Shift to bonus non-winning state).

  When 20 games have elapsed in the RT1 state (when the transition condition (4) is satisfied), the main control circuit 90 shifts the gaming state from the RT1 state to the RT0 state. Further, in the RT1 state, when the symbol combination (see FIG. 26 described later) related to the abbreviation “bell spilled eyes” is displayed on the active line before 20 games have elapsed (when the transition condition (5) is satisfied). The main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

  In the RT0 state, when the symbol combination related to the abbreviation “bell spill” is displayed on the active line (when the transition condition (5) is satisfied), the main control circuit 90 shifts the gaming state from the RT0 state to the RT2 state. Let In the RT2 state, when the symbol combination related to the abbreviation “RT3 transition lip” (see FIG. 26 described later) is displayed on the active line (when the transition condition (6) is satisfied), the main control circuit 90 changes the gaming state. Transition from the RT2 state to the RT3 state.

  In the RT3 state, when the symbol combination related to the abbreviation “RT4 transition lip” (see FIG. 26 described later) is displayed on the active line (when the transition condition (7) is satisfied), the main control circuit 90 changes the gaming state. Transition from the RT3 state to the RT4 state. In the RT3 state, when the symbol combination (see FIG. 26 described later) relating to the abbreviation “bell spilled eyes” or “RT2 transition lip” is displayed on the active line (when transition condition (8) is satisfied), The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Furthermore, in the RT4 state, when the symbol combination related to the abbreviation “bell spill” or “RT2 transition lip” is displayed on the active line (when the transition condition (8) is satisfied), the main control circuit 90 The gaming state is shifted from the RT4 state to the RT2 state.

  As for the symbol combination related to the abbreviation “bell spilled eyes”, an internal winning combination (small role) related to the name “F_3 selection bell_1st”, “F_3 selection bell_2nd” or “F_3 selection bell_2rd” described later is determined, And it is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the pressing order determined for each type of the small role (see FIG. 22 described later). For the symbol combination related to the abbreviation “RT2 transition lip”, an internal winning combination (replay combination) related to a name “F_maintenance lip_1st”, “F_maintenance lip_2nd” or “F_maintenance lip_3rd” described later is determined, and This is a combination of symbols displayed when the order of the stop operation is incorrect for the pressing order determined for each type of the replay combination.

  For the symbol combination related to the abbreviation “RT3 transition Lip”, an internal winning combination (replay combination) related to the names “F_RT3 Lip_1st”, “F_RT3 Lip_213”, “F_RT3 Lip_231” or “F_RT3 Lip_3rd” described later is determined. And the combination of symbols displayed when the order of the stop operation is correct with respect to the pressing order determined for each type of the replay combination. In addition, the symbol combination related to the abbreviation “RT4 transition Lip” has an internal winning combination (replay combination) related to the names “F_RT4 Lip_123”, “F_RT4 Lip_132”, “F_RT4 Lip_2nd”, or “F_RT4 Lip_3rd” described later. This is a combination of symbols that is displayed when the order of stop operations is determined and is correct with respect to the pressing order determined for each type of replay combination.

[Game State Transition Flow Considering Operation of Notification (ART) Function]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not to activate a function (ART function) that notifies a stop operation that is advantageous to the player. Therefore, in this embodiment, in the bonus inactive state, the operating / inactive state of the ART function is also managed as a gaming state.

  In the pachi-slot 1 of the present embodiment, as shown in FIG. 12A, the main control circuit 90 separates the “general gaming state” and the “ART gaming state” based on the presence or absence of notification (ART) in the non-bonus operating state. To manage as a gaming state. That is, in the management of the gaming state in consideration of the presence / absence of notification (ART), as shown in FIG. 12A, the main control circuit 90 categorizes the “bonus state”, “general gaming state”, and “ART gaming state” as broad categories. 3 types of gaming state are managed.

  Note that the general game state is basically a game state (non-ART) in which information on a stop operation advantageous to the player is not notified, and is a disadvantageous game state for the player. Further, the general gaming state is one of the RT0 to RT4 states, and is an ART non-winning gaming state.

  On the other hand, the ART gaming state is a gaming state in which information on a stop operation advantageous to the player is notified, and is a gaming state advantageous to the player. Further, the ART gaming state is basically a RT4 state and a gaming state in which the ART is won. In this embodiment, when the RT state transitions to the RT4 state after winning the ART, the ART game is started.

  In the present embodiment, as shown in FIG. 12A, two types of states called “normal game state” and “CZ (chance zone)” are provided as the general game state.

  The normal game state is the most unfavorable game state for the player, but in the game in the normal game state, a lottery to shift to CZ is performed. Then, as shown in FIGS. 12A and 12B, in the game in the normal game state, when winning the lottery to CZ (when the transition condition (A) is satisfied), the main control circuit 90 changes the game state to the normal game. Transition from state to CZ.

  CZ is a gaming state (chance zone) with high expectation for the transition to the ART gaming state, and a lottery for transitioning to the ART is performed in the game in the CZ. Then, as shown in FIGS. 12A and 12B, in the game in CZ, when the lottery for shifting to ART is not won (when the transition condition (B) is satisfied), the main control circuit 90 is in the gaming state. Is shifted from CZ to the normal gaming state. On the other hand, in a game during CZ, when winning a lottery for shifting to ART (when the transition condition (C) is satisfied), the main control circuit 90 shifts the gaming state from CZ to the ART gaming state. At this time, although not shown in FIG. 12A, the main control circuit 90 shifts the gaming state from CZ to the ART gaming state (described later, normal ART or CT) via the ART preparation state described later.

  As described above, the ART gaming state is started when the RT state shifts to the RT4 state after winning the ART. As shown in FIG. 11A, since the RT4 state shifts from the RT0 to RT2 state via the RT3 state, the ART gaming state is not started immediately even after the ART is won. Therefore, in the pachi-slot 1 of the present embodiment, the gaming state during the period from the winning of the ART to the transition of the RT state to the RT4 state is set to the ART ready state. In this ART ready state game, information on a stop operation necessary to shift the RT state to the RT4 state is notified.

  Further, in the present embodiment, as shown in FIG. 12A, two types of states called “normal ART” and “CT (additional chance)”, which are different from each other, are provided as the ART gaming state.

  The normal ART is a stop operation that is advantageous to the player for a predetermined number of games (for example, a stop operation for displaying a symbol combination with a large number of medals to be paid out or a stop operation necessary for maintaining the RT4 state). Is a gaming state in which is notified. Further, in a game during normal ART, a lottery for transition to CT is performed.

  CT is a gaming state in which a stop operation that is advantageous to the player is notified, and it is possible to add a normal ART continuation period for a specific period (one set of eight games), and functions as an extra chance zone It is a gaming state to be Also, during CT, a game is usually played without digesting the duration of ART. Note that the game playability during CT will be described in detail later with reference to FIGS. 50A to 50C described later.

  As shown in FIG. 12A and FIG. 12B, in the game during the normal ART, when the winning lottery to the CT is won (when the transfer condition (D) is satisfied), the main control circuit 90 changes the game state from the normal ART to the CT. The game state is transferred to. In the normal ART, when the duration of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the game state from the normal ART to the general game state (normal game state or CZ). Transition. In this embodiment, the duration of the normal ART is managed by the number of games. However, the present invention is not limited to this, and the management method of the duration of the normal ART is arbitrary. For example, the duration of normal ART may be managed based on the number of medals paid out during normal ART or the number of differences, or depending on the number of times of notification (number of navigations) affecting medal payout during normal ART. May be managed.

  As shown in FIGS. 12A and 12B, in the game during CT, when the duration of CT (one set of 8 games) ends (when the transition condition (F) is satisfied), the main control circuit 90 changes the gaming state to CT. To normal ART.

  Also, as shown in FIG. 12A, when a bonus combination is won in the general gaming state (normal gaming state or CZ) or the ART gaming state (normal ART or CT) (the transition condition (2) described in FIGS. 11A and 13B). When established, the main control circuit 90 shifts the gaming state from the general gaming state or the ART gaming state to the bonus state.

  In the game in the bonus state, as described above, the lottery for the transition to ART is performed. In the game in the bonus state, when the lottery for transition to the ART is non-winning (when the transition condition (G) is satisfied) The main control circuit 90 shifts the gaming state from the bonus state to the general gaming state (normal gaming state or CZ). However, if the ART game state (normal ART or CT) has shifted to the bonus state, the main control circuit 90 will change the game state, Transition from the bonus state to the ART gaming state (normal ART or CT). On the other hand, in the bonus state game, when the lottery for transition to ART is won (when the transition condition (H) is satisfied), the main control circuit 90 changes the game state from the bonus state to the ART game state (normal ART or CT). Transition. As described above, since the RT state shifts to the RT1 state at the end of the bonus state, when the gaming state is shifted from the bonus state to the ART gaming state, the main control circuit 90 changes the gaming state to the ART state. A transition is made to the ART gaming state via the preparation state.

<Configuration of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 102 will be described with reference to FIGS. Various data tables used in various lotteries relating to the gameability (CZ, normal ART, CT gameability) in the general gaming state and the ART gaming state will be described later together with the description of each gaming property. .

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table of FIG. 13 will be described with reference to FIGS. The compressed symbol arrangement table (see FIG. 116 (2)) stored in the main ROM 102 is decompressed to the main RAM 103 (see FIG. 116 (3)). The symbol arrangement table is data (hereinafter referred to as symbol code (in FIG. 13) that specifies the position of each symbol in the rotation direction of each of the left reel 3L, the middle reel 3C, and the right reel 3R and the type of symbol arranged at each position. )))).

  In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle area of each reel within the frame of the reel display window 4 is defined as “0”. Then, in each reel, the symbol counter value “0” corresponds to the value of the symbol counter in the order of advance in the reel rotation direction (the direction from symbol position “19” in FIG. 13 toward symbol position “0”). “0” to “19” are assigned to the symbols as symbol positions.

  That is, by referring to the symbol counter values (“0” to “19”) and the symbol arrangement table, the symbols are displayed in the upper, middle, and lower regions of each reel within the frame of the reel display window 4. It is possible to specify the type of design. In this embodiment, the symbols “white 7”, “blue 7”, “top 1”, “top 2”, “bottom”, “replay”, “hat”, “cactus 1”, 10 types of symbols “Cactus 2” and “Cactus 3” are used 35.

  In this embodiment, as shown in the symbol code table, symbol “white 7” (symbol code 1) is assigned “00000001” as data, and symbol “blue 7” (symbol code 2) “00000010” is assigned as data. The symbol “Chile top 1” (symbol code 3) is assigned “00000011” as data, and the symbol “Chile above 2” (symbol code 4) is assigned “00000100” as data.

  The symbol “Chile under” (symbol code 5) is assigned “00000101” as data, and the symbol “Replay” (symbol code 6) is assigned “00000110” as data. The symbol “hat” (symbol code 7) is assigned “0000011” as data, and the symbol “cactus 1” (symbol code 8) is assigned “00001000” as data. In addition, the symbol “cactus 2” (symbol code 9) is assigned “00000101” as data, and the symbol “cactus 3” (symbol code 10) is assigned “00001010” as data.

[Internal lottery table]
Next, with reference to FIG. 14 and FIG. 15, an internal lottery table referred to when determining an internal winning combination will be described. FIG. 14 is an internal lottery table referred to in each of the RT0 state to the RT4 state. 15A is an internal lottery table referred to in the RT5 state, and FIG. 15B is an internal lottery table referred to in the bonus state.

  The internal lottery table is provided for each gaming state, and defines the correspondence between various internal winning combinations and lottery values when each internal winning combination is determined. Note that the lottery value is defined for each setting (settings 1 to 6) for adjusting the expected value of internal winnings such as a bonus combination and a small combination set in advance. This setting is changed using, for example, the reset switch 76 and the setting key switch 54 (see FIG. 5).

  In the internal lottery process of this embodiment, first, a random number value extracted from a predetermined numerical range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 is assigned to each internal winning combination. Sequentially add with the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result has overflowed). When the lottery result exceeds 65535 in a predetermined internal winning combination, it is determined that the internal winning combination is won. In the internal lottery process of the present embodiment, an example of performing lottery by adding a lottery value to an extracted random number value has been described, but the present invention is not limited thereto, and the lottery value is subtracted from the random number value, It may be determined whether the subtraction result (lottery result) has fallen below “0” (whether the lottery result has underflowed) or not to determine whether the internal lottery is won or not.

  Therefore, in the internal lottery process of the present embodiment, the probability of being determined is higher for an internal winning combination having a larger numerical value defined as a lottery value. The winning probability of each internal winning combination can be expressed by “the lottery value specified for each winning number / the number of all random numbers that may be extracted (random number denominator: 65536)”.

  In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 14, basically, the type of replay combination and the winning probability determined as the internal winning combination according to the type of the RT state. Changes. For example, the replay combination relating to the names “F_Chill Lip (No. 25)” to “F_Reach Eye Lip D (No. 31)” is not determined as an internal winning combination in the RT0 state to the RT3 state, but in the RT4 state. Only determined as an internal winning combination. In the pachi-slot 1 of the present embodiment, the replay roles relating to the names “F_Chilelip (No. 25)” to “F_Leach Eye Lip D (No. 31)” are determined as internal winning combinations during the RT4 state. In this case, peculiar control (flag conversion described later) is performed. This flag conversion will be described in detail later.

  Further, as shown in FIG. 14, in the RT0 state to the RT3 state, the internal winning combinations of the names “F_reach eye lip A” to “F_reach eye lip D” are related to the names “F_BB1” or “F_BB2”. Although it may be determined to overlap with the bonus combination (see Nos. 3-6, 15-18), each of the internal winning combinations (replays) of the names “F_reach eye lip A” to “F_reach eye lip D” Is not determined as an internal winning combination alone. Therefore, in the present embodiment, when the replay combination relating to the names “F_reach eye lip A” to “F_reach eye lip D” is determined as the internal winning combination during the RT0 state to the RT3 state (name from the player's point of view) A bonus combination (named “F_BB1” or “F_BB2”) and an internal winning combination are simultaneously determined when a symbol combination corresponding to a replay combination related to “F_reach lip A” to “F_reach lip D” is displayed. Will be.

  The RT5 state, which is an inter-flag state, is a gaming state in which a bonus combination is carried over as an internal winning combination as described above. Therefore, as shown in FIG. 15A, in the internal lottery table referred to in the RT5 state, the bonus combination carried over is always determined as the internal winning combination. Further, as shown in FIG. 15B, the internal lottery table referred to in the bonus state is configured such that an internal winning combination corresponding to any of the names “F_RB winning 1” to “F_RB winning 4” is always won ( "Out of the box" will not win.)

[Correspondence table between internal winning combination and symbol combination (winning combination) (design combination determination table)]
Next, a correspondence table (symbol combination determination table) between internal winning combinations and symbol combinations will be described with reference to FIGS. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line (center line) associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the active line (the type of display combination that can win a prize) is uniquely determined.

  Various data described in the symbol combination column in each symbol combination determination table is for identifying symbol combinations that are allowed to be displayed along the effective lines set over the left reel 3L, the middle reel 3C, and the right reel 3R. It is data. In addition, the relationship between each name described in the symbol combination (display combination) column and a specific symbol combination is shown in a winning action flag storage area of FIGS.

  The symbol “◯” described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the active line in the determined internal winning combination, that is, a display combination that can be won. For example, when the internal winning combination “F_Chilli Lip” is determined, as shown in FIG. 16 and FIG. 17, the combination names “C_Keep Lip A_01” to “C_Keep Lip G_01”, “C_Chilli Lip A_01” to “C_Chilli Lip” The symbol combination related to “D_01” can be stopped and displayed. In the symbol combination determination table, the case where the “internal winning combination” is “out of” is not defined, but this is all the symbols defined by the symbol combination tables shown in FIGS. Indicates that combination display is not allowed.

  In the pachi-slot 1 of the present embodiment, the main control circuit 90 (main CPU 101) changes the stop control according to the internal winning combination and the gaming state, and when the predetermined winning combination is determined as the internal winning combination, FIG. The rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the corresponding symbol combination (combination) shown in FIG. 21 can be displayed. In the correspondence tables shown in FIGS. 16 to 21, all symbol combinations that can be displayed for the determined internal winning combination are listed with “◯” marks, but symbols with “○” marks are attached. Even a combination may not be displayed.

  In the present embodiment, there is a function of changing stop control (for example, a drawing to be drawn preferentially) according to a combination of symbols that can be stopped and the current gaming state. Even symbol combinations with marks may not be displayed. The correspondence between the internal winning combination and the symbol combination actually displayed will be described with reference to FIGS. 22 and 23 described later.

[Correspondence between winning combination in non-flag state and symbol combination to be stopped]
Here, with reference to FIG. 22, the correspondence relationship between the internal winning combination and the symbol combination to be stopped and displayed in the gaming state (non-flag state) excluding the inter-flag state will be described. FIG. 22 shows the correspondence between various internal winning combinations that can be determined in the non-flag state and symbol combinations (abbreviated) that are stopped when each internal winning combination is determined (some combinations are omitted). FIG. Note that the names of the symbol combinations described in FIG. 22 are “abbreviations” described in the contents column shown in the winning action flag storage area of FIGS.

  In the pachi-slot 1 of the present embodiment, a so-called “push order” is provided in which the symbol combinations displayed differ according to the order (push order) of the player's stop operation. Note that the symbol combination associated with the “push order correct answer” shown in FIG. 22 is a symbol combination advantageous to the player among the symbol combinations displayed in accordance with the push order, and the “push order incorrect answer” The associated symbol combinations are symbol combinations that are disadvantageous to the player among the symbol combinations displayed according to the pressing order. When notifying a stop operation that is advantageous to the player, the correct push order is notified, and if the stop operation is performed in accordance with the notification, the symbol combination associated with the “push order correct answer” is displayed. In addition, even in the ART gaming state, the push order that becomes an incorrect answer may be notified, but the contents will be described in detail later.

  In the present embodiment, for some of the push order combinations, the correct push order is shown at the end of the name. Specifically, the end “1st” of the name of the internal winning combination means that the correct pressing order is that the first stop operation (first stop operation) is for the left reel 3L, The end of the name of the internal winning combination “2nd” means that the correct pushing order is that the first stop operation is for the middle reel 3C, and the end of the name of the internal winning combination “3rd” is the correct answer. This pressing order means that the first stop operation is for the right reel 3R. In addition, the last “123” of the name of the internal winning combination means that the pressing order of the correct answer is “left, middle, right”, and the last “132” of the name of the internal winning combination is the correct answer. Means that the order of pressing is “left, right, middle”, and the last “213” of the name of the internal winning combination is the order of “middle, left, right”. And “231” at the end of the name of the internal winning combination means that the correct pressing order is “left, right, middle”.

  In the following, the stop operation sequence when the first stop operation is performed on the left reel 3L, specifically, the pressing order of “left, middle, right” and “left, right, middle” is “ It is also called “pressing forward”. Furthermore, in the following, the stop operation sequence when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, “middle, left, right”, “middle, right, left”, The pressing order of “right, middle, left” and “right, left, middle” is also referred to as “anomalous pressing”.

  In the present embodiment, as shown in FIG. 22, the internal winning combination “F_Chillilip” is a pressing combination with different symbol combinations displayed according to the pressing order, and the abbreviation “ One of the displayable symbol combinations shown in FIGS. 16 to 21 among the symbol combinations (see FIG. 26 to be described later) related to “Chilelip” is displayed along the active line. On the other hand, when the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 16 to 21 among the symbol combinations related to the abbreviation “Replay” (see FIG. 26 described later) is along the active line. Displayed. When the internal winning combination “F_Chilli Lip” is determined, as shown in FIGS. 16 to 21, the combination names “C_Chilli Lip A_01”, “C_Chilli Lip B_01” or “C_Chilli Lip C_01” (abbreviated “Single Chilli Lip”) Or, the symbol combination corresponding to the abbreviation “Chilelip (no triple)” in FIG. 26 to be described later) can be displayed, but the combination names “C_Chillilip D_01” to “C_1 correct Chilelip D_01” (abbreviation) “Triple Chile Lip”: Corresponding to the abbreviation “Chile Lip (Triple)” in FIG. That is, the internal winning combination “F_Chillilip” is a combination that cannot display the symbol combination related to the abbreviation “Triple Chilelip”.

  In addition, the internal winning combination “F_Challenging Lip” and “F_1 Challenging Lip” are both pushing orders with different symbol combinations displayed according to the pressing order. When the pressing order is correct, the abbreviation “Chile Lip” Of the symbol combinations (see FIG. 26 described later), any of the displayable symbol combinations shown in FIGS. 16 to 21 is displayed along the effective line. On the other hand, when the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 16 to 21 among the symbol combinations related to the abbreviation “Replay” (see FIG. 26 described later) is along the active line. Displayed. In addition, when the internal winning combination “F_acceptable dust” or “F_1 accurate dust” is determined, the symbol combination related to the abbreviation “triple dust” can be displayed as shown in FIGS. In other words, the internal winning combination “F_accurate lip” and “F_1 accurate dip” are roles that can display the symbol combination related to the abbreviation “triple dip”.

  In addition, the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” are push combinations with different symbol combinations displayed according to the push order, and are abbreviated when the push order is correct. Of the symbol combinations related to “reach eye lip” (see FIGS. 26 and 27 described later), any one of the displayable symbol combinations shown in FIGS. 16 to 21 is displayed along the active line. On the other hand, when the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 16 to 21 among the symbol combinations related to the abbreviation “Replay” (see FIG. 26 described later) is along the active line. Displayed.

  In the present embodiment, the correct answer push order at the time of winning the internal winning combination “F_Chile Lip”, “F_Challeng Lip”, “F_1 Chilli Lip” and “F_Reach Eye Lip A” to “F_Reach Eye Lip D” Performs a first stop operation on the left reel 3L. Therefore, for example, in a game in which the internal winning combination “F_reach eye lip A” is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation “reach eye lip” is given. Such a symbol combination is stopped and displayed. Note that the present invention is not limited to this, and at the time of winning the internal winning combination "F_Chile Lip", "F_Challenging Lip", "F_1 Chick Lip" and "F_Reach Eye Lip A" to "F_Reach Eye Lip D" The pushing order of correct answers can be arbitrarily set.

  In addition, the internal winning combination “F_maintenance lip A” and “F_maintenance lip B” are not push order combinations, and are diagrams of symbol combinations related to the abbreviation “replay” regardless of the press order (see FIG. 26 described later). Any of the displayable symbol combinations shown in FIGS. 16 to 21 is displayed along the effective line.

  Also, all of the internal winning combinations “F_Maintenance Lip_1st” to “F_Maintenance Lip_3rd” are pressing combinations with different symbol combinations displayed according to the pressing order, and are abbreviated when the pressing order is correct. Of the symbol combinations related to “Replay” (see FIG. 26 described later), any of the displayable symbol combinations shown in FIGS. 16 to 21 is displayed along the active line. On the other hand, when the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 16 to 21 in the symbol combination (see FIG. 26 described later) related to the abbreviation “RT2 transition lip” is an effective line. It is displayed along.

  Also, all of the internal winning combinations “F_RT3 Lip_1st” to “F_RT3 Lip_1rd” are push combinations having different symbol combinations displayed according to the push order. When the push order is correct, the abbreviation “RT3 The symbol combination related to “transition lip” (see FIG. 26 described later) is displayed along the active line. On the other hand, when the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 16 to 21 among the symbol combinations related to the abbreviation “Replay” (see FIG. 26 described later) is along the active line. Displayed.

  Also, the internal winning combinations “F_RT4 Lip_123” to “F_RT4 Lip_3rd” are push combinations with different symbol combinations displayed according to the push order. When the push order is correct, the abbreviation “RT4 The symbol combination related to “transition lip” (see FIG. 26 described later) is displayed along the active line. On the other hand, when the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 16 to 21 among the symbol combinations related to the abbreviation “Replay” (see FIG. 26 described later) is along the active line. Displayed.

  In addition, the internal winning combinations “F_3 selection bell_1st” to “F_3 selection bell_3rd” are all pressing combinations with different symbol combinations displayed according to the pressing order, and are abbreviated when the pressing order is correct. The symbol combination related to “Bell” (see FIG. 17 described later) is displayed along the active line. On the other hand, if the pressing order is not correct, the symbol combination related to the abbreviation “Bell spilling eyes” (see FIG. 26 described later) or the symbol combination related to the abbreviation “one-shot appearance” (refer to FIG. 28 described later). Is displayed.

  In addition, the internal winning combination “F_common bell” is not a push order, and can be displayed as shown in FIGS. 16 to 21 in the symbol combination (see FIG. 27 described later) related to the abbreviation “bell” regardless of the push order. One of the various symbol combinations is displayed along the active line. In addition, the internal winning combination “F_Sabo 1” and “F_Sabo 2” are not push order combinations, and FIG. 16 of the symbol combinations related to the abbreviation “Cactus” regardless of the push order (see FIG. 28 described later). Any one of the displayable symbol combinations shown in FIG. 21 is displayed along the effective line.

  In addition, the internal winning combination “weak cherry” is not a push order, and can be displayed as shown in FIGS. 16 to 21 in the symbol combination related to the abbreviation “weak cherry” regardless of the push order (see FIG. 28 described later). One of the various symbol combinations is displayed along the active line. In addition, the internal winning combination “F_Strong Chile 1” and “F_Strong Chile 2” are not the push order, and are included in the symbol combination related to the abbreviation “Strong Cherry” regardless of the push order (see FIG. 28 described later). Any one of the displayable symbol combinations shown in FIGS. 16 to 21 is displayed along the effective line.

[Correspondence relationship between winning combination in inter-flag state and symbol combination to be stopped]
Next, with reference to FIG. 23, the correspondence relationship between the internal winning combination and the symbol combination that is stopped and displayed in the inter-flag state will be described. FIG. 23 is a diagram showing the correspondence between the internal winning combination and the symbol combination that is displayed in a stopped state in the inter-flag state (some of the combinations are omitted). In particular, the bonus combination ( It is a figure which shows whether the symbol combination (combination name "C_BB1" or "C_BB2") which concerns on BB role can be displayed.

  In the correspondence table of FIG. 23, “○” mark in the “BB establishment possibility” column indicates that the symbol combination related to the BB role can be displayed, and “X” mark indicates the symbol combination related to the BB role. Indicates that it cannot be displayed. When the symbol combination related to the BB combination cannot be displayed, the symbol combination related to the combination determined to overlap with the bonus combination as the internal winning combination is displayed. For example, when the internal winning combination “F_BB1 + F_Chillilip” is won (when the internal winning combination “F_BB1” and the internal winning combination “F_Chillilip” are duplicated), as shown in FIG. 23, the internal winning combination “F_BB1” The symbol combination related to the internal symbol combination “F_Chillilip” can be stopped and displayed.

  Also, in the inter-flag state, when the symbol combination related to the BB combination cannot be displayed and the symbol combination related to the combination determined to overlap with the bonus combination is displayed, the push described in FIG. Only the symbol combination at the time of the correct answer may be displayed, or only the symbol combination at the time of the incorrect push order may be displayed.

  For example, when the internal winning combination “F_BB1 + F_3 selection bell_1st” is won, as shown in FIG. 23, the symbol combination related to the internal winning combination “F_BB1” cannot be stopped, so the internal winning combination “F_3 selection bell_1st” The symbol combination related to "" is stopped and displayed, but at this time, only the symbol combination related to the abbreviation "Bell" displayed at the correct answer in the pressing order can be displayed, and the abbreviation "Bell spilled" displayed at the incorrect answer in the pressing order. Alternatively, the symbol combination relating to “one-shot” may be disabled (see FIG. 22). Also, for example, when the internal winning combination “F_BB1 + F_RT3 Lip_1st” is won, only the symbol combination related to the abbreviation “Replay” displayed when the pressing order is incorrect can be displayed, and the abbreviation “RT3 displayed when the pressing order is correct The symbol combination related to “transition lip” may be disabled (see FIG. 22).

  In the inter-flag state, as shown in FIG. 23, a bonus combination (BB combination) and any of the internal winning combinations “out”, “F_special 1”, “F_special 2”, and “F_special 3” When it is determined redundantly, the symbol combination relating to the BB combination can be stopped and displayed.

[Reel stop initial setting table]
Next, the reel stop initial setting table will be described with reference to FIG. The reel stop initial setting table defines the correspondence between the internal winning combination and various data used in the reel stop control process described later.

  The reel stop initial setting table shown in FIG. 24 defines the correspondence relationship between the internal winning combination (small winning combination number), the drawing priority table selection table number, the drawing priority table number, and the stop table number. In FIG. 24, the gaming state to be referred to and the name of the internal winning combination are also described.

  The pull-in priority table selection table number and the pull-in priority table number are data used in the pull-in priority table selection process. For example, in the reel stop initial setting table, if a pull-in priority table number corresponding to the stop table number is defined, it corresponds to the pull-in priority table number defined in the pull-in priority table (see FIG. 25 described later). Data relating to the priority order of the display combination can be acquired. On the other hand, if the pull-in priority table number corresponding to the stop table number is not defined in the reel stop initial setting table, the pull-in priority table selection table number is referred to by referring to a pull-in priority table selection table (not shown). A corresponding pull-in priority table number is determined.

  Here, the stop control (determination method of the stop symbol position) of the reel in the pachi-slot 1 of the present embodiment will be briefly described. In this embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel stops within 190 msec. Specifically, one of the number of sliding symbols “0” to “4” is added to the value of the symbol counter corresponding to the reel when the stop operation is detected, and the value obtained corresponds to the value obtained. The symbol position is determined as the symbol position where the reel rotation stops (hereinafter referred to as “scheduled stop position”). The symbol position corresponding to the value of the symbol counter corresponding to the reel when the stop operation is detected is the symbol position at which the rotation of the reel starts to be stopped (hereinafter referred to as “stop start position”).

  That is, the number of sliding pieces is the amount of rotation of the reel from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. In other words, the number of symbols passing through the middle area of the corresponding reel in the reel display window 4 in the period from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  Referring to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is a tentative one, and the acquired number of sliding pieces does not immediately determine the planned stop position of the reel. In the present embodiment, when there is an appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), a pull-in priority table (described later) The number of sliding pieces is changed with reference to FIG. Then, the sliding piece number determination data is referred to in order to determine the search order when the priorities are compared for each of the symbols from the stop start position to the 4th symbol position that is the maximum number of sliding symbols.

[Pull-in priority table]
Next, the drawing priority table will be described with reference to FIG. The pull-in priority table is a pull-in data (winning operation flag data) for each type of a later-described winning operation flag storage area (see FIGS. 26 to 28 described later) in each of the drawing priority table numbers “00” to “05”. ) And a predetermined priority order.

  The pull-in priority order table is used for searching whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols obtained based on a stop table (not shown). The priority order is data that defines the order of priority stop display (drawn) among the types of symbol combinations (winning operation flag) related to winning. In FIG. 25, for convenience of explanation, the combination data of the winning action flag is described in the drawing data (winning action flag data) column. However, in the actual drawing priority order table, each drawing data is a prize to be described later. As shown in the operation flag storage area (see FIGS. 26 to 28 described later), it is represented by 1-byte data, and a unique symbol combination (winning operation flag) is assigned to each bit in the 1-byte data. .

  In the reel stop control of this embodiment, first, the number of sliding pieces is acquired based on a stop table (not shown). However, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces based on the priority, the number is changed to the appropriate number of sliding pieces. That is, in the present embodiment, a more appropriate number of sliding symbols is determined based on the priority order of symbol combinations that allow stop display by an internal winning combination regardless of the number of sliding symbols acquired from the stop table.

  In the present embodiment, the stop display (withdrawal) of the symbol combination having the higher priority is performed in preference to the stop display of the symbol combination having the lower priority.

  In the present embodiment, as shown in FIG. 25, not only does the priority of the symbol combination (winning operation flag) differ according to the drawing priority table number, but also the number of priority divisions differs. Specifically, when the pull-in priority table number is “00”, the number of priority categories is set to 5, and when the pull-in priority table number is “01” or “04”, the priority is The number of divisions is 4. Further, when the pull-in priority table number is “02” or “03”, the number of priority divisions is 2, and when the pull-in priority table number is “05”, the number of priority divisions Is 3.

  Here, the priority when the pull-in priority table number is “00” will be described, and description of priorities in other pull-in priority table numbers will be omitted. The priority order “1” (highest priority order) when the pull-in priority order table number is “00” includes the combination names “C_9 sheets A_01”, “C_1 correct dust C_01”, “C_1 correct dust D_01”, and The pull-in data corresponding to “C_RT3 Lip_01” is defined.

  The priority order “2” when the pull-in priority table number is “00” includes combination names “C_high 2 sheets C_01” to “C_high 2 sheets C_09”, “C_weak 2 sheets B_01” to “C_weak”. Corresponding to “2 sheets B_03”, “C_3 sheets E_01”, “C_3 sheets E_02”, “C_9 sheets F_01” to “C_9 sheets F_03”, “C_1 exact dust lip B_01”, “C_chili lip D_01” and “C_chili lip C_01” Withdrawal data is specified.

  The priority order “3” when the pull-in priority table number is “00” includes the combination names “C_1 correct chili lip A_01”, “C_chili lip A_01”, “C_chili lip B_01”, and “C_maintenance lip E_01” to “ Pull-in data corresponding to “C_maintenance lip E_04” is defined.

  The priority order “4” when the pull-in priority table number is “00” includes combination names “C_SP1_01”, “C_SP2_01”, “C_reach eye lip P_01”, “C_reach eye lip P_02”, “C_reach”. Eye Lip O_01 "," C_Reach Eye Lip O_02 "," C_Reach Eye Lip N_01 "," C_Reach Eye Lip N_02 "," C_Reach Eye Lip M_01 "," C_Reach Eye Lip M_02 "," C_Reach Eye Lip " L_01 ”to“ C_reach eye lip L_03 ”,“ C_reach eye lip K_01 ”to“ C_reach eye lip K_03 ”,“ C_reach eye lip J_01 ”,“ C_reach eye lip I_01 ”to“ C_reach eye lip I_09 ” , “C_reach eye lip H_01” to “C_reach eye lip H_03”, “C_reach eye lip H_01” , “C_reach eye lip F_01”, “C_reach eye lip F_02”, “C_reach eye lip E_01”, “C_reach eye lip D_01”, “C_reach eye lip D_02”, “C_reach eye lip C_01” ˜ “ C_reach eye lip C_03, “C_reach eye lip B_01”, “C_reach eye lip B_02”, “C_reach eye lip A_01”, “C_maintenance lip F_01”, “C_maintenance lip F_02”, “C_maintenance lip D_01” To “C_maintenance lip D_04”, “C_maintenance lip C_01” to “C_maintenance lip C_03”, “C_maintenance lip B_01”, “C_maintenance lip B_02” and “C_maintenance lip A_01” are defined. Is done.

  Further, in the priority order “5” (lowest priority order) when the drawing priority order table number is “00”, the pull-in data corresponding to the combination names “C_BB1” and “C_BB2” are defined.

<Configuration of storage area provided in main RAM>
Next, the configuration of various storage areas provided in the main RAM 103 will be described with reference to FIGS.

[Hit request flag storage area and winning action flag storage area]
First, the configuration of the winning request flag storage area (internal winning combination storage area) and the winning action flag storage area (display combination storage area) will be described with reference to FIGS. In the present embodiment, the winning request flag storage area (flag data storage area, winning flag data storage area) and the winning action flag storage area (winning flag data storage area) have the same configuration.

  In this embodiment, the winning request flag storage area is composed of winning request storing areas 0 to 11 each represented by 1-byte data, and the winning action flag storing area is each winning operation represented by 1-byte data. It consists of storage areas 0-11. The data stored in the storage areas of the winning request flag storage area and the winning action flag storage area is only 1-byte data in the “data” column in FIGS. 26 to 28, but in FIGS. For convenience of explanation, the symbol combinations of the reels associated with the bits of each storage area (in the drawing, the symbols of the left reel 3L, the symbols of the middle reel 3C and the symbols of the right reel 3R are described in this order), The name (combination name) and abbreviation, and the number of medals to be paid out are also described.

  In each of the hit request flag storage areas 0 to 11, when “1” is stored in a predetermined bit, it indicates that the internal winning combination corresponding to the predetermined bit has been won internally. In each of the winning action storage areas 0 to 11, when “1” is stored in a predetermined bit, it indicates that a display combination (winning action flag) corresponding to the predetermined bit has won. That is, when “1” is stored in a predetermined bit, it indicates that various symbol combinations of the internal winning combination corresponding to the predetermined bit are displayed on the active line.

  In the winning request flag storage area and the winning action flag storage area, as shown in FIGS. 26 to 28, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. Some have. That is, for such a flag, it means that there are a plurality of symbol combinations (combination that can be awarded) that can be stopped and displayed.

  For example, in the bit 5 of the winning request storage area 5 and the winning action storage area 5, the symbol combination “cactus 2” − “white 7” − “hat” (combination name “C_maintenance lip C_01”), the symbol combination “cactus 2” -"Chile top 1"-"hat" (combination name "C_maintenance lip C_02") and symbol combination "cactus 2"-"cactus 2"-"hat" (combination name "C_maintenance lip C_03") Three symbol combinations are assigned. Therefore, when “1” is stored in bit 5 of the hit request storage area 5, it indicates that these three symbol combinations can be stopped and displayed on the effective line. When “1” is stored in bit 5 of the winning action storage area 5, it indicates that any one of the three symbol combinations is displayed on the active line.

[Coverage storage area]
Next, the structure of the carryover combination storage area will be described with reference to FIG. In the present embodiment, the carryover combination storage area is composed of a 1-byte data storage area.

  When the internal winning combination “F_BB1” or “F_BB2” is determined as a result of the internal lottery, the internal winning combination (BB combination) is stored in the carryover combination storage area as a carryover combination. The carryover combination stored in the carryover combination storage area is held without being cleared until the corresponding symbol combination is displayed on the active line. Further, while the carryover combination is stored in the carryover combination storage area, the carryover combination is stored in the hit request storage area in addition to the internal winning combination determined by the internal lottery.

[Game state flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. The gaming state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 30, a unique bonus type or RT type is assigned to each bit of the gaming state flag storage area.

  When “1” is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when “1” is stored in bit 0 of the game state flag storage area, it indicates that the big bonus “BB” is activated and the game state is the BB game state. For example, when “1” is stored in bit 3 of the gaming state flag storage area, it indicates that the gaming state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is composed of a 1-byte data storage area and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

  For example, if the left stop button 17L is a stop button that has been pressed this time, that is, an operation stop button, “1” is stored in bit 0 of the operation stop button storage area. Also, for example, if the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, “1” is stored in bit 4. Based on the data stored in the operation stop button storage area, the main CPU 101 identifies a stop button that has been pressed this time and a stop button that has not yet been pressed.

[Push order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The pressing order storage area is composed of a 1-byte data storage area and stores a pressing order flag consisting of 1 byte.

  In the pressing order flag, the type of stop button pressing order is assigned to each bit. For example, when the stop button pressing order is “left, middle, right”, “1” is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. In this embodiment, the symbol code storage area is composed of symbol code storage areas 0 to 11 each represented by 1-byte data. The symbol code storage area has the same configuration as the winning request flag storage area and the winning action flag storage area (see FIGS. 26 to 28).

  In the symbol code storage area, “1” is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the active line. After all the reels are stopped, the symbol codes corresponding to the display combination (winning operation flag) are stored in the symbol code storage areas 0 to 11.

[Relationship between internal winning combination and various subflags]
In the general gaming state and the ART gaming state, various data tables are referred to in various lotteries by the main control circuit 90. As parameters used at this time, in the present embodiment, not only the internal winning combination but also the internal winning combination is supported. Various parameters with different names (hereinafter referred to as “sub-flag (first sub-flag)”, “sub-flag EX (second sub-flag)”, and “sub-flag D”)) are also used. Therefore, in the present embodiment, the main control circuit 90 performs processing for converting the internal winning combination into various subflags (refer to subflag conversion processing, flag conversion processing, and subflag compression processing in FIG. 83 described later). In the present embodiment, as information (communication parameter) regarding the internal winning combination, a sub flag is set in the start command and transmitted from the main control circuit 90 to the sub control circuit 200.

  Here, with reference to FIG. 34 and FIG. 35, the correspondence between the internal winning combination and various subflags will be described. FIG. 34 is a diagram showing a correspondence relationship between an internal winning combination (small winning combination number) and various subflags, and FIG. 35 is a diagram showing a correspondence relationship between an internal winning combination (special prize winning number) and a subflag.

  In the flag conversion process of the present embodiment, first, a plurality of internal winning combinations belonging to the same type are combined into one subflag. In the present embodiment, by this flag conversion process, as shown in FIG. 34, 32 types of internal winning combinations (small combination winning numbers) related to the small combination and replay combination are converted into 18 types of sub-flags (“01” to “18”). : Flag data). For example, the internal winning combination “F_maintenance lip — 1st (10: small combination winning number)” to “F_maintenance lip — 3rd (12)” are collected into the sub flag “push order lip 1 (09: flag data)”. Note that the sub-flag “losing (00)” is assigned to the internal winning combination “out”.

  In the flag conversion process of the present embodiment, as shown in FIG. 34, 19 types of subflags (“00” to “18”) including the subflag “losing (00)” are converted into 9 types of subflags EX (“00 To “08”: flag data). Therefore, in this conversion process, the subflag data can be further compressed. At this time, in this embodiment, the sub flag is converted into the sub flag EX by lottery (flag conversion lottery). Specifically, it is converted as follows.

  The sub-flag “losing (00)” is converted into the sub-flag EX “losing (00)” regardless of the result of the flag conversion lottery, and the sub-flag “double chili (01)” is irrespective of the result of the flag converting lottery. Sub-flag EX is converted to “Replay (01)”.

  When the sub-flag “Triple Chile Lip A (02)” and the sub-flag “Triple Chile Lip B (03)” win the flag conversion lottery (in the case of “with conversion” described later), the sub-flag EX “determined role (06)” Or, when it is converted to “triple dust lip (07)” and the flag conversion lottery is non-winning (in the case of “no conversion” described later), it is converted to the sub flag EX “replay (01)”.

  When the sub-flag “reach eye lip 1 (04)” to “reach eye lip 4 (07)” wins the flag conversion lottery, it is converted into the sub flag EX “determined combination (06)” or “reach eye lip (08)”. If the flag conversion lottery is not won, it is converted to the sub flag EX “Replay (01)”.

  The subflags “Replay (08)” and “Push Order Lip 1 (09)” to “Push Order Lip 3 (11)” are converted to the subflag EX “Replay (01)” regardless of the result of the flag conversion lottery, The subflags “push order bell (12)” and “common bell (13)” are converted into the subflag EX “bell (02)” regardless of the result of the flag conversion lottery.

  The sub-flags “cactus (14)”, “weak cherry (15)”, and “strong cherry (16)” are sub-flags EX “cactus (03)” and “weak cherry (04)” regardless of the result of the flag conversion lottery. And “strong cherry (05)”. Further, the sub-flags “reach eyes 1 (17)” and “reach eyes 2 (18)” are converted into the sub-flag EX “losing (00)” regardless of the result of the flag conversion lottery.

  As described above, in the present embodiment, the sub-flags “triple lip A (02)”, “triple lip B (03)” and “reach eye lip 1 (04)” to “reach eye lip 4 (07) ) ”Only becomes the target of flag conversion lottery. The lottery table used for the flag conversion lottery described above will be described in detail later.

  Furthermore, in the flag conversion process of the present embodiment, as shown in FIG. 34, nine types of subflags EX (“00” to “08”) are converted into seven types of subflags D (“00” to “06”). The Therefore, in this conversion process, the subflag data can be further compressed. In this conversion process, lottery is not performed, and conversion is performed in association with the subflag EX and the subflag D as follows.

  The subflags EX “losing (00)”, “replay (01)”, and “bell (02)” are converted into subflags D “losing (00)”. Sub flag EX “cactus (03)” is converted to sub flag D “cactus (01)”, sub flag EX “weak cherry (04)” is converted to sub flag D “weak cherry (02)”, and sub flag EX “strong” Cherry (05) "is converted to sub-flag D" strong cherry (03) ".

  Further, the subflag EX “determined combination (06)” is converted into a subflag D “determined combination (04)”, and the subflag EX “triple-tilt (07)” is converted into sub-flag D “triple-tilt (05)”. Then, the sub flag EX “reach eye lip (08)” is converted into a sub flag D “reach eye lip (06)”.

  In the flag conversion process according to the present embodiment, as shown in FIG. 35, both the internal winning combination “F_BB1 (01: special prize winning number)” and “F_BB2 (02)” are converted into the sub flag “BB”. .

[Gameability during sub-flag EX conversion]
Here, an example of the process of converting the above internal winning combination into the sub flag and the sub flag EX and an example of the game at the time of the sub flag EX conversion will be described with reference to FIGS. 36A and 36B. FIG. 36A is a diagram showing a flag conversion process when the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is determined, and FIG. 36B shows the internal winning combinations “F_Reach Eye Lip A” to “F_ It is a figure which shows the flag conversion process in case one of "reach eyes lip D" is determined.

  In the pachi-slot 1 of the present embodiment, any one of the internal winning combination “F_Challenging Lip”, “F_1 Chanting Lip”, and “F_Reach Eye Lip A” to “F_Reach Eye Lip D” is alone during the RT4 gaming state. If it is determined as an internal winning combination, a flag conversion lottery is performed. In the present embodiment, when this flag conversion lottery is won, a special privilege (for example, an additional number of ART games or CT winning) is given.

  For example, when the internal winning combination “F_Challenging Lip” or “F_1 Chanting Lip” is determined, as shown in FIG. 36A, the internal winning combination “F_Challenging Lip” and “F_1 Chick Lip” are sub-flags “Three consecutive”, respectively. Converted to “Chilli Lip A (02)” and “Triple Chili Lip B (03)”.

  Next, when the sub-flag “triple dust lip A (02)” and “triple dust lip B (03)” win the flag conversion lottery, the sub-flag EX “triple dust lip (07)” or “determined role (06)” Converted. On the other hand, if the flag conversion lottery is non-winning, both the sub-flags “triple chilli lip A (02)” and “triple chilli lip B (03)” are converted to the sub-flag EX “replay (01)”. .

  As described with reference to FIG. 22, when the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is won, the symbol combination related to the abbreviation “Triple Chilli Lip” is displayed at the correct push order, and the push order is not correct. When the answer is correct, the symbol combination related to the abbreviation “Replay” is displayed. Therefore, in the present embodiment, when the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is determined and the flag conversion lottery is won, the internal winning combination “F_Challenging Lip” and “F_1 Chanting Lip” Are both treated as a combination of the sub flag EX “Triple Chile Lip (07)” or “Determined Combination (06)”.

  When the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is converted to the sub-flag EX “Triple Chilelip (07)” or “Determining Role (06)” by this flag conversion process, the abbreviation “Triple” Information for displaying the symbol combination related to “Chilelip” is notified (for example, information indicating that the Chile symbol is aimed at the player by pushing forward) is notified. On the other hand, when the flag conversion lottery becomes non-winning in this flag conversion process and the internal winning combination “F_acceptance lip” or “F_1 accuracy dip” is converted to the sub flag EX “Replay (01)”, the abbreviation “Replay” is obtained. Information for displaying such a symbol combination is notified (for example, a pressing order other than forward pressing (anomalous pressing) is notified).

  Further, for example, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined, as shown in FIG. 36B, the internal winning combinations “F_reach eye lip A” to “ F_reach eye lip D "is converted into sub-flags" reach eye lip 1 (04) "to" reach eye lip 4 (07) ", respectively.

  Next, when the sub-flags “reach eye lip 1 (04)” to “reach eye lip 4 (07)” win the flag conversion lottery, the sub flag EX “reach eye lip (08)” or “determined role (06)” Converted. On the other hand, if the flag conversion lottery is not won, the subflags “reach eye lip 1 (04)” to “reach eye lip 4 (07)” are converted to the subflag EX “replay (01)”.

  Note that, as described with reference to FIG. 22, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is won, the symbol combination related to the abbreviation “reach eye lip” in the correct push order Is displayed, and the symbol combination related to the abbreviation “Replay” is displayed when the pressing order is incorrect. Therefore, in this embodiment, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined and the flag conversion lottery is won, the internal winning combination “F_reach eye” Any of “Lip A” to “F_reach eye lip D” is treated as a role of the sub flag EX “reach eye lip (08)” or “determined role (06)”.

  When the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is converted into, for example, the sub flag EX “reach eye lip (08)” or “determining role (06)” by this flag conversion process. , Information for displaying the symbol combination related to the abbreviation “reach eye lip” is notified (for example, information indicating that the symbol “white 7” is aimed by being pushed forward is notified to the player). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is converted to the sub flag EX “replay (01)”, the abbreviation Information for displaying the symbol combination related to “Replay” is notified (for example, a pressing order other than forward pressing (anomalous pressing) is notified).

  In the present embodiment, in the flag conversion process shown in FIG. 36A or FIG. 36B, when the player performs a stop operation according to the notification after winning the flag conversion lottery, the abbreviation “triple lip” or “reach eye lip” is displayed. Such a symbol combination is stopped and displayed on the active line, and a special privilege is given. This granting process substantially gives a special privilege to the player in response to the fact that the pachislot 1 wins the flag conversion lottery, but for the player, the abbreviation “3 By displaying the symbol combination related to “ream chililip”, it can be felt that a special privilege has been given.

  In order to improve the gameability of the pachislot, it may be preferable that the appearance frequency of the symbol combination to which a privilege is given is different depending on the state. Stop control (displayed symbol combination) varies depending on the type of internal winning combination. Therefore, as a method of varying the appearance frequency of the symbol combination to which a privilege is given depending on the state, the winning probability of the internal winning combination is varied. (In Pachislot 1, the winning probability of the internal winning combination can be varied depending on whether the bonus is activated or depending on the RT state. For example, as the RT state corresponding to the ART gaming state, only the RT4 state is possible. In addition, a method of providing another RT state such as the RT6 state or the RT7 state is also conceivable). However, since the opportunity to change the winning probability of the internal winning combination (RT state transition opportunity) is limited, this method lacks flexibility in terms of improving game play (amusement).

  On the other hand, in the pachislot machine 1 of the present embodiment, in addition to the internal lottery for determining the internal winning combination without changing the winning probability of the internal winning combination, the flag conversion lottery and the notification based on the lottery result are performed. The appearance frequency of the symbol combination to which the privilege is given can be flexibly changed according to the state. That is, in a state where it is easy to win the flag conversion lottery, the appearance frequency of the symbol combination to which the privilege is given can be increased, and conversely, in a state where it is difficult to win the flag conversion lottery, the appearance of the symbol combination to which the privilege is given is given. The frequency can be lowered.

<Gameability in general gaming state>
Next, with reference to FIG. 37A to FIG. 37C, the flow of the game during the general gaming state will be described. In the pachi-slot 1 of the present embodiment, in the general gaming state, the gaming state transitions from the normal gaming state to the CZ, and then the gaming state transitions from the CZ to the ART gaming state, so that the general gaming state (non-ART gaming state) ) To the ART gaming state (see FIGS. 12A and 12B).

  FIG. 37A is a diagram illustrating a game flow when the game state shifts from the normal game state to the CZ during the general game state. As shown in FIG. 37A, the normal gaming state has a low-probability state and a high-probability state as CZ lottery states. The low-probability state and the high-probability state are states in which expectations for winning a CZ lottery performed during the normal gaming state are different from each other. The low-probability state is a state in which it is difficult to win a CZ lottery. It is in a state where it is easy to win a lottery. When the CZ lottery performed in the game in the normal game state is won, the game state shifts from the normal game state to the CZ.

  In the pachislot machine 1 of the present embodiment, a plurality of chance zones “CZ1”, “CZ2”, and “CZ3” are provided as CZ (chance zone). CZ1 to CZ3 are chance zones with different expectations for winning an ART lottery performed in a game in CZ, CZ3 is a chance zone that must win an ART lottery, and CZ1 and CZ2 have a predetermined probability. This is a chance zone to win the ART lottery. In CZ lottery performed in a game in the normal gaming state, not only CZ winning / non-winning but also the type of CZ (any one of CZ1 to CZ3) to be transferred at the time of winning is determined (see FIG. 39 described later).

  FIG. 37B is a diagram illustrating a game flow when the gaming state shifts from the general gaming state CZ1 and CZ2 to the ART gaming state. CZ1 and CZ2 are both composed of a first half and a second half. The first half is a period in which the rank of expectation for winning an ART lottery performed in a game in CZ is promoted, and the second half is a result of a lottery result of an ART lottery based on the rank (in this embodiment, a character It is a period to notify by (battle production).

  In CZ1, six stages of modes (modes 1 to 6) are prepared as ranks, and the higher the mode, the higher the degree of expectation for winning an ART lottery. In the first half of CZ1, a game is continuously performed for a period of a first predetermined number of games (for example, a maximum of 12 games), and a mode promotion lottery is performed based on an internal winning combination. Then, in the first game of the second half of CZ1, ART lottery is performed based on the mode promoted in the first half (mode at the end of the first half).

  In CZ2, 10 stages of points are prepared as ranks, and the higher the points, the higher the degree of expectation for winning an ART lottery. In the first half of CZ2, a game is continuously performed for a period of a second predetermined number of games (for example, a maximum of 15 games), and a point lottery is performed based on an internal winning combination. Then, in the first game in the second half of CZ2, ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

  In the second half of CZ1, a battle effect is played in which the teammate character and the enemy character A battle each other. In the second half of CZ2, a battle effect is played in which the teammate character and the enemy character B battle each other. This battle effect is performed over a game for a period of a third predetermined number of games (for example, a maximum of 4 games). In addition, the victory or defeat of the battle effect is managed (determined) based on the result of the ART lottery. When the player wins the ART lottery, the battle character wins the battle effect, and when the player wins the battle, Enemy character wins by directing.

  In each latter half of CZ1 and CZ2 (during battle production), ART lottery is performed based on each game and internal winning combination. Then, when the ART lottery is won, the result of the battle effect is rewritten. For example, when a so-called “rare” combination is determined as an internal winning combination during a battle presentation, an ART lottery is performed, and the result of the battle presentation is rewritten based on the result.

  In CZ1 and CZ2, if the ART is not won, the player loses the battle in the latter half, and basically the gaming state shifts to the normal gaming state. On the other hand, in CZ1 and CZ2, when the player wins ART, the player wins in the second half battle effect, and then the gaming state shifts from CZ to normal ART via the ART preparation state. In this embodiment, a freeze may occur in the game in the first half of CZ1 and CZ2, and in this case, the game state passes from the CZ via the ART ready state and is not a normal ART but a CT (addition). (Chance zone).

  FIG. 37C is a diagram showing a game flow when the gaming state shifts from the general gaming state CZ3 to the ART gaming state. In CZ3, a game is continuously performed for a period of a fourth predetermined number of games (for example, a maximum of 17 games). In CZ3, an ART lottery is performed based on each game and an internal winning combination.

  CZ3 ends when the ART lottery is won, and after the next game, the gaming state shifts from CZ3 to the CT (additional chance zone) via the ART preparation state. In CZ3, a freeze may occur. In this case, the game state is transferred from CZ3 to the CT (additional chance zone) via the ART preparation state after the next game. On the other hand, in CZ3, when the game period (fourth predetermined number of games) of CZ3 has passed without winning the ART lottery, the game state shifts from CZ3 to the normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state is confirmed.

<Various data tables used during the general gaming state>
Next, with reference to FIG. 38 to FIG. 43, various data tables used in lottery processing relating to game play performed in the general game state will be described. Various data tables described below are stored in the main ROM 102.

  Also, in the various data tables shown below, lottery value information is conceptually shown. “0” in the data table means that a lottery value corresponding to the winning probability “0%” is defined, and “extremely low” means a lottery corresponding to the winning probability “0% to less than 1%”. It means that a value is defined, and “extremely low” means that a lottery value corresponding to a winning probability “less than 1% to 10%” is defined. “Low” in the data table means that a lottery value corresponding to the winning probability “10% to less than 30%” is defined, and “medium” means the winning probability “30% to less than 60%”. ”Means that a lottery value corresponding to the winning probability“ 60% to less than 80% ”is prescribed. Furthermore, “extremely high” in the data table means that a lottery value corresponding to the winning probability “80% to less than 99%” is defined, and “extremely high” means that the winning probability is “99% to 100%”. A lottery value corresponding to “less than%” is defined, and “confirmed” means that a lottery value corresponding to the winning probability “100%” is defined.

  In the various data tables shown below, the random number register 1 of the random number circuit 110 sequentially subtracts the random numbers for lottery extracted from the predetermined numerical range (0 to 65535) by the prescribed lottery value. The internal lottery is performed by determining whether the result of the subtraction is negative (whether a so-called “digit” has occurred). In the present embodiment, the example in which the winning / non-winning is determined by subtracting the lottery value from the random number for lottery in the lottery processing related to the game performance performed in the general gaming state is described, but the present invention is not limited to this. The lottery value is added to the extracted random number for lottery, and whether or not the addition result exceeds 65536 (whether or not so-called “digit overflow” has occurred) is determined, and the winning / non-winning is determined. Also good.

[Normal high probability lottery table]
First, with reference to FIGS. 38A and 38B, the normal medium / high probability lottery table used in the transition lottery in the CZ lottery state (low probability and high probability) will be described. In the pachi-slot 1 of the present embodiment, not only the lottery of the CZ lottery state is performed based on each game and the internal winning combination, but also at the end of the bonus or at the end of CZ, ART, etc. A lottery transition lottery is performed. FIG. 38A is a configuration diagram of a normal medium / high probability random determination table that is referred to every game during the normal gaming state, and FIG. 38B is a normal medium / high probability that is referred to when, for example, setting change, bonus end or CZ, ART end, etc. It is a block diagram of a probability lottery table. Note that the names of the internal winning combinations shown in FIG. 38A correspond to the names of the subflags described above.

  The normal medium-high probability lottery table shown in FIG. 38A shows each combination of the current CZ lottery state and internal winning combination, lottery result (low probability / high probability) of the CZ lottery state after transition, and each lottery result. A correspondence relation with the information of the lottery value associated with the prescription is defined.

  As is clear from the normal medium-high probability lottery table shown in FIG. 38A, when the current CZ lottery state has a low probability, when the internal winning combination is a combination corresponding to the sub-flag “weak cherry”, The lottery state easily shifts with high probability. On the other hand, when the current CZ lottery state has a high probability, the internal winning combination is a combination corresponding to any of the sub-flags “common bell”, “cactus”, “weak cherry”, and “strong cherry” In addition, the lottery state of CZ is maintained with high probability.

  The normal medium / high probability lottery table shown in FIG. 38B is a lottery associated with each lottery result, each situation when referring to the table, lottery result (low probability / high probability) of the CZ lottery state after the transition. Specifies the correspondence with value information. As is apparent from the normal medium-high probability lottery table shown in FIG. 38B, the CZ lottery state always shifts to a high probability at the end of the bonus.

[CZ lottery table]
Next, the CZ lottery table used in the CZ lottery will be described with reference to FIGS. 39A and 39B. FIG. 39A is a configuration diagram of a CZ lottery table used when a CZ lottery is performed based on an internal winning combination during a normal gaming state, and FIG. 39B is a CZ pullback when, for example, CZ fails or ART ends. It is a block diagram of the CZ lottery table used when performing CZ lottery of whether to perform. Note that the names of the internal winning combinations shown in FIG. 39A correspond to the names of the subflags described above.

  The CZ lottery table shown in FIG. 39A is a lottery associated with each combination of the current CZ lottery state and internal winning combination, CZ1, CZ2, CZ3 winning / non-winning (lottery result), and each lottery result. Specifies the correspondence with value information. As is clear from the CZ lottery table shown in FIG. 39A, when the current CZ lottery state has a high probability, the CZ lottery is won more than when the current CZ lottery state has a low probability. Probability increases.

  The CZ lottery table shown in FIG. 39B is a correspondence relationship between winning / non-winning (lottery results) of CZ1, CZ2, and CZ3 and lottery value information associated with each lottery result when CZ fails or ART ends. Is specified. At the time of CZ failure (when the ART lottery in CZ1 and CZ2 is not won) or at the end of the ART gaming state, the CZ pullback lottery is performed using this CZ lottery table.

[Mode up lottery table during CZ1]
Next, with reference to FIG. 40, the CZ1 medium-up lottery table used in the CZ1 mode-up lottery performed in the first half of the CZ1 will be described. FIG. 40 is a configuration diagram of the mode-up lottery table during CZ1. Note that the names of the internal winning combinations shown in FIG. 40 correspond to the names of the subflags described above.

  The mode-up lottery table during CZ1 shows the correspondence between each combination of the current mode and the internal winning combination, the result of mode-up lottery (winning / non-winning), and lottery value information associated with each lottery result. Is specified. As shown in FIG. 42A described later, in CZ1, the probability of winning an ART lottery increases as the mode increases (the mode value increases), and when the mode increases to mode 6, the ART lottery is always won.

  Note that the lottery result “mode 1 UP” in FIG. 40 means that the mode of CZ1 goes up by one step, and the lottery result “mode 2 UP” means that the mode of CZ1 goes up by two steps. Therefore, for example, in the situation where the current mode is mode 2, if the lottery result “mode 2 UP” is won, the mode of CZ1 is raised from mode 2 to mode 4. Further, for example, when a lottery result “Mode 6 UP_Freeze” is won, a freezing occurs, and the determination of the ART lottery and the grant of CT are determined.

[CZ2 medium point lottery table]
Next, a CZ2 point lottery table used in the CZ2 point-up lottery performed in the first half of CZ2 will be described with reference to FIG. FIG. 41 is a block diagram of the point lottery table in CZ2. Note that the names of the internal winning combinations shown in FIG. 41 correspond to the names of the subflags described above.

  The point lottery table in CZ2 shows the correspondence between each combination of the current point and the internal winning combination, the result of the point-up lottery (winning / non-winning), and lottery value information associated with each lottery result. Stipulate. As shown in FIG. 42B, which will be described later, in CZ2, the probability of winning an ART lottery increases as the point increases, and when the point increases to “point 10”, the ART lottery is always won. The lottery result “point 2 UP” in FIG. 41 means that “2” is added to the current CZ2 point. For example, in the situation where the current point is “2”, the lottery result “ If you win "Point 2UP", the point of CZ2 will rise from "2" to "4". Further, for example, when a lottery result “point 10 UP_freeze occurrence” is won, a freeze occurs, and the determination of the ART lottery and the grant of CT are determined.

[CZ ART lottery table]
Next, with reference to FIG. 42A to FIG. 42C and FIG. 43, the ART lottery table during CZ used in the ART lottery executed during CZ will be described. 42A is a configuration diagram of an ART lottery table in CZ (for CZ1) used in the first game of the second half of CZ1, and FIG. 42B is an ART in CZ used in the first game of the second half of CZ2. 42C is a configuration diagram of a lottery table (for CZ2), and FIG. 42C is a configuration diagram of an ART lottery table in CZ (for CZ1 and CZ2 common use in the latter half battle) used in the latter half of CZ1 and CZ2. FIG. 43 is a configuration diagram of an ART lottery table for CZ (for CZ3) used in an ART lottery executed during CZ3. Note that the names of the internal winning combinations shown in FIGS. 42C and 43 correspond to the names of the subflags described above.

  The ART lottery table in CZ (for CZ1) shown in FIG. 42A defines the correspondence between the current mode, the ART lottery result (presence / absence of winning), and lottery value information associated with each lottery result. . Further, the ART lottery table in CZ (for CZ2) shown in FIG. 42B shows the correspondence between the current point, the ART lottery result (presence / absence of winning), and lottery value information associated with each lottery result. Stipulate.

  As is clear from the ART lottery table during CZ (for CZ1) and the ART lottery table during CZ (for CZ2), the higher the rank (mode or point) of the first half of CZ1 and CZ2, the easier it is to win the ART lottery.

  42C shows an ART lottery table in CZ (common for CZ1 and CZ2 during the second half battle), an internal winning combination, an ART lottery result (presence / absence of winning), and lottery value information associated with each lottery result. Specify the correspondence of. As is clear from the CZ ART lottery table (common for CZ1 and CZ2 during the latter half of the battle), in the latter half of CZ1 and CZ2, the role corresponding to the sub flag “weak cherry”, “cactus” or “strong cherry” ) Is determined as an internal winning combination, the ART lottery is won with a predetermined probability.

  The ART lottery table in CZ (for CZ3) shown in FIG. 43 includes combinations of the number of CZ3 digest games and internal winning combinations, ART lottery results (presence / absence of winning), and lotteries associated with the lottery results. Specifies the correspondence with value information. As is clear from the ART lottery table during CZ (for CZ3), in the present embodiment, when the ART lottery is won in CZ3, the CT is always won.

<Gameability during normal ART>
Next, with reference to FIG. 44A and FIG. 44B, the flow of the game during the game ART will be described. In the pachi-slot 1 of the present embodiment, as described above, the ART gaming state is normally provided with ART and CT (see FIGS. 12A and 12B), and the inside of CT is added as a chance zone. Therefore, in this embodiment, the player plays a game aiming at the transition to CT in a game during normal ART.

[Transition mode from normal ART to CT]
FIG. 44A is a diagram showing a transition state of the gaming state from normal ART to CT. In the pachislot machine 1 of the present embodiment, as shown in FIG. 44A, when a CT lottery performed during normal ART is won, the gaming state shifts from normal ART to CT. As shown in FIG. 44A, the pachi-slot 1 of this embodiment is provided with an ART level and a CT lottery state as parameters that affect various lotteries performed during normal ART.

  As the ART level, four levels of level 1 to level 4 are provided, and this ART level is controlled (determined) mainly based on the number of continuous (digestion) games in normal ART. The ART level affects the determination of the CT lottery state and the flag conversion lottery during normal ART described later.

  As the CT lottery state, there are four stages of low probability, normal, high probability, and ultra-high probability. The CT lottery state is controlled mainly based on the ART level or the internal winning combination during normal ART ( It is determined. The CT lottery state affects a CT lottery performed during normal ART, a flag conversion lottery during normal ART, which will be described later, and the like.

[Flag conversion during normal ART]
As described above, in the pachislot machine 1 of the present embodiment, during the RT4 state, that is, during the ART gaming state, the internal winning combination “F_Challenging Lip”, “F_1 Challenging Lip” and “F_Leaching Lip A” to “F_” When any one of the “reach eyes lip D” is determined as an internal winning combination alone, a flag conversion lottery is performed, and a special privilege (for example, an additional number of ART games or CT winning) is given according to the lottery result. . FIG. 44B is a diagram showing an outline of a flag conversion lottery method performed during normal ART.

  In the present embodiment, as shown in FIG. 44B, flag conversion lottery is performed with reference to the ART level and the CT lottery state during normal ART. As a result, when a flag conversion lottery is won, a special privilege is given and a symbol combination related to the abbreviation “triple chili lip” or a symbol combination related to the abbreviation “reach eye lip” is stopped and displayed on the active line. Navigation (for example, notification of information indicating that a predetermined symbol is aimed by forward pressing) is performed. On the other hand, when the flag conversion lottery is not won, navigation for displaying the symbol combination related to the abbreviation “Replay” on the active line (for example, notification of the pressing order other than the forward pressing) is performed.

  And if a player performs stop operation according to this alerting | reporting (navigation), the symbol combination according to the alerting | reporting content will be stopped and displayed on an effective line. Specifically, when winning the flag conversion lottery, the symbol combination related to the abbreviation “triple lip” or the symbol combination related to the abbreviation “reach eye lip” is stopped on the active line, and the flag conversion lottery is not displayed. In the case of winning, the symbol combination related to the abbreviation “Replay” is stopped and displayed on the active line.

<Various data tables used during normal ART>
Next, with reference to FIGS. 45 to 49, various data tables used in lottery processing during normal ART will be described. Various data tables described below are stored in the main ROM 102.

[ART flag conversion lottery table]
45A and 45B are configuration diagrams of an ART flag conversion lottery table used in flag conversion lottery performed during normal ART.

  In the pachi-slot 1 according to the present embodiment, flag conversion lottery during normal ART is performed in two stages. More specifically, when the internal winning combination “F_Challenging Lip” or “F_1 Challenging Lip” is won, the first stage flag conversion lottery is performed. A second stage flag conversion lottery is performed. Then, when the second stage flag conversion lottery is won, the internal winning combination “F_accurate lip” or “F_1 credible lip” is converted to the sub flag EX “triple dip”. On the other hand, if the first-stage flag conversion lottery or the second-stage flag conversion lottery is non-winning, the internal winning combination “F_acceptance lip” or “F_1 accuracy dip” is converted to the sub-flag EX “replay”. (Handles as a normal replay role). When any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” wins, only the second-stage flag conversion lottery is performed.

  45A is a configuration diagram of an ART flag conversion lottery table used in the first-stage flag conversion lottery, and FIG. 45B is a configuration diagram of an ART flag conversion lottery table used in the second-stage flag conversion lottery. is there.

  The flag conversion lottery table during ART shown in FIG. 45A is an internal winning combination (“F_accurate lipper” or “F_1 accurate lipper”) and the lottery result of the first stage flag conversion lottery (no conversion / with conversion (provisional)) And the correspondence between lottery value information associated with each lottery result.

  The flag conversion lottery table during ART shown in FIG. 45B includes combinations of internal winning combinations, ART levels, and CT lottery states, lottery results (no conversion / with conversion) of the second stage flag conversion lottery, and lottery results. A correspondence relationship with lottery value information associated with is defined. Note that in the game until winning CT once in normal ART, the table in the “first time (until once winning CT)” column of the item “ART level” in FIG. 45B is referred.

  In this embodiment, as shown in FIGS. 45A and 45B, in the stage and second stage flag conversion lottery using each of the ART flag conversion lottery tables, a random value (0) whose probability denominator is “256”. ˜255), the lottery is performed. Therefore, in the present embodiment, the above-described two-stage flag conversion lottery can be regarded as a lottery that is substantially the same as a lottery performed once using a random number with a probability denominator “65536”.

  In recent pachislot machines, a lottery (ART lottery, etc.) related to a ball that was conventionally performed on the sub-control board 72 side (hereinafter referred to as “sub-side”) is performed on the main control board 71 side (hereinafter referred to as “main-side”). There is a need to do. However, since the capacity of the main storage means (main ROM 102) is limited to a small capacity, there is a demand for a mechanism that enables lottery without reducing the game capacity while suppressing an increase in processing capacity.

  In this regard, in the pachislot machine 1 of the present embodiment, the lottery with the probability denominator “256” can be performed in two stages, so that the lottery with the probability denominator “65536” can be performed. Side capacity increase can be suppressed. Also, in the second lottery, the ART level, CT lottery status, etc. are referred to, so that it is possible to perform flag conversion lottery according to the current state as well as the internal winning combination. A flag conversion lottery can be performed.

[ART level determination table]
46A and 46B are configuration diagrams of an ART level determination table used when determining the ART level. The ART level determination process is performed when the ART is determined to shift to the ART gaming state and during normal ART. FIG. 46A is a configuration diagram of an ART level determination table used when winning an ART, and FIG. 46B is a configuration diagram of an ART level determination table used during normal ART.

  The ART level determination table shown in FIG. 46A defines the correspondence between ART levels 1 to 4 (lottery results) and lottery value information associated with each ART level. In the present embodiment, ART level 2 is determined as the ART level when freezing occurs when the ART is won.

  The ART level determination table shown in FIG. 46B is a lottery associated with each combination of the current ART level and the number of elapsed (digested) games of the normal ART, the various ART levels of the transfer destination, and each ART level of the transfer destination. Specifies the correspondence with value information. In addition, the ART level determination table shown in FIG. 46B is associated with each combination of the current ART level and the number of elapsed games of the normal ART at the time of CT entry, various transition ART levels, and each transition destination ART level. The correspondence relationship with the information of the lottery value obtained is defined. In other words, during normal ART, the ART level can be shifted not only when the number of elapsed (digested) games of normal ART reaches a predetermined number of games, but also when the level of CT enters normal ART. Can be migrated.

[Normal ART medium-high probability lottery table]
FIG. 47 is a configuration diagram of a normal ART medium high probability lottery table used when determining the CT lottery state during normal ART.

  The normal ART medium / high probability lottery table shows the correspondence between each combination of the current CT lottery state and the internal winning combination, various CT lottery states at the transition destination, and lottery value information associated with each CT lottery state. Stipulate. Note that the names of the internal winning combinations shown in FIG. 47 correspond to the names of the subflags described above.

  As is clear from the normal ART medium / high probability lottery table, the internal winning combination corresponding to the sub-flag “triple chilli lip (triple chilli lip A and triple chilli lip B)” and the sub-flag “reach lip (reach lip 1 to 4)” When is won, the CT lottery state easily shifts (falls) to “low probability”. However, as shown in FIG. 48 to be described later, when the internal winning combination corresponding to the sub-flag “triple lip” or “reach eye lip” is won, even if the CT lottery state falls, The lottery must be won.

[CT lottery table during ART]
FIG. 48 is a configuration diagram of a CT lottery table during ART used in CT lottery performed during normal ART.

  In the ART CT lottery table, each combination of the current CT lottery state and the internal winning combination, various lottery results of CT lottery (non-winning / normal CT / high probability CT), and lottery associated with each lottery result Specifies the correspondence with value information. Note that the names of the internal winning combinations shown in FIG. 48 correspond to the names of the subflags described above.

  In this embodiment, the sub-flag “cactus”, “weak cherry”, “strong cherry”, “triple chilli lip (triple chilli lip A and triple chilli lip B)”, “reach lip (reach lip) 1 to 4) ”or“ BB ”is determined, in the CT lottery process using the CT lottery table during ART, the CT lottery using random numbers in the range where the probability denominator is“ 256 ” Is done. If an internal winning combination other than these combinations is determined as an internal winning combination (for example, a combination corresponding to the sub-flag “replay”, “common bell”, “push order bell”, etc.), the CT during ART In the CT lottery process using the lottery table, a CT lottery using a random number value in a range where the probability denominator is “65536” is performed.

  In the pachislot machine 1 of the present embodiment, two types of CT called “normal CT” and “high probability CT” are provided as CT. The normal CT and the high probability CT have different expectations of the number of ART games added in the CT (additional chance zone), and the high probability CT is more likely to add a larger number of ART games than the normal CT. (See FIG. 53 described later).

[Normal lottery table during ART]
FIG. 49 is a configuration diagram of the extra lottery table during normal ART used in the extra lottery for the number of ART games performed during normal ART. Note that the names of the internal winning combinations shown in FIG. 49 correspond to the names of the subflags described above.

  The extra lottery table during the normal ART defines a correspondence relationship between the internal winning combination, various lottery results of the extra lottery (non-winning / additional 10G to 300G), and lottery value information associated with each lottery result.

<Gameability during CT>
Next, with reference to FIG. 50A to FIG. 50C, the flow of games during CT will be described. 50A and 50B are diagrams showing an outline of the game flow during the CT when the sub flag EX “Triple Chile Lip” is won, and FIG. 50C shows an outline of the flag conversion process performed during the CT. FIG.

[Game contents during CT]
In the pachislot machine 1 of the present embodiment, one set of 8 games (8 games) is played in CT. During the CT period, the number of ART games is added and lottery is performed based on each game and internal winning combination. If the extra lottery is won, the number of CT game unit games (number of games) is not subtracted. On the other hand, if the extra lottery is non-winning, the number of CT game unit games (game) Number) is subtracted. Therefore, CT does not end for games with the number of ART games added during the CT period, and CT ends when a game in which the number of ART games is not added is executed eight times in the same set. .

  Further, in the present embodiment, as shown in FIGS. 50A and 50B, when the sub flag EX “Triple Chile Lip” is won during the CT period, that is, the internal winning combination “F_Probable Chile Lip” or “F_1 Probable Chile Lip” When winning and winning the flag conversion lottery, one set of 8 CT games is reset (stocked). Then, the reset (stocked) CT game set is started after the CT game set is completed.

  For example, after a unit game that is non-winning for the number of ART games in the same set is played 7 times, if a CT game in which the number of ART games is not added is performed once, CT ends. If the sub-flag EX “Triple Chile Lip” is won, the CT game is reset. As a result, after the CT game is reset, the CT does not end until the number of ART games is increased and the unit game that is not won by lottery is performed eight times. Therefore, the CT game period becomes longer as the sub-flag EX “Triple Chile Lip” is won.

[Flag conversion during CT]
Next, a flag conversion lottery method performed during CT will be described with reference to FIG. 50C. As described above, in the present embodiment, when the sub-flag EX “Triple Chile Lip” is won during the CT period (internal winning combination “F_Challenging Lip” or “F_1 Chilli Lip” is won and the flag conversion lottery is won. Then, the CT is reset (stocked). Also, as shown in the CT flag conversion lottery table of FIG. 52 described later, if an internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is won during CT, the flag conversion lottery is always won (sub flag EX “ It is always converted to “Triple Chilelip”). In other words, in the present embodiment, when the internal winning combination “F_accurate lip” or “F_1 accurate lip” is won during CT, CT is always reset.

  Further, in the flag conversion lottery when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is won, the flag is based on three types of flag conversion tables (tables 0 to 2). The winning probability of the conversion lottery is controlled. Specifically, as shown in FIG. 50C, table 0 is a flag conversion table having the lowest probability of being converted to subflag EX “reach eye lip”, and table 1 is converted to subflag EX “reach eye lip”. The flag conversion table with the next lowest probability, and Table 2 is the flag conversion table with the highest probability of being converted to the subflag EX “reach eye lip”. When the sub flag EX “reach eye lip” is won during CT, CT is newly given as shown in the lottery table with the number of sets in CT of FIG. 54 described later.

  In this embodiment, in normal CT, as shown in FIG. 50C, the flag conversion table is determined based on the ART level. On the other hand, in high probability CT, table 0 is always determined as the flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, with reference to FIGS. 51 to 54, various data tables used in lottery processing performed during CT will be described. Various data tables described below are stored in the main ROM 102.

[Table lottery table during CT]
FIG. 51 is a block diagram of a CT table lottery table used when determining a table to be used for flag conversion lottery out of three stages of flag conversion tables (tables 0 to 2).

  The CT table lottery table shows the correspondence between each state such as the ART level and the type of CT to be executed, the type of the flag conversion table (tables 0 to 2), and lottery value information associated with each type. Stipulate. The CT table lottery table is referred to when the CT lottery is determined to shift to CT or when CT starts.

[CT flag lottery table]
FIG. 52 is a configuration diagram of a CT flag conversion lottery table used in flag conversion lottery performed during CT.

  The CT flag conversion lottery table includes an internal winning combination (any one of “F_Correct Lip”, “F_1 Correct Chilli Lip” and “F_Reach Eye Lip A” to “F_Reach Eye Lip D”) and each flag conversion table ( The correspondence relationship between the lottery result (no conversion / with conversion) of the flag conversion lottery in the tables 0 to 2) and lottery value information associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, if the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is won during CT, the flag conversion lottery is always won (the sub flag EX “Triple Chile Lip” must be won). Converted).

[Lottery table during CT]
FIG. 53 is a configuration diagram of the extra lottery table during CT used in the extra lottery for the number of ART games performed during CT.

  The extra lottery table during CT corresponds to each combination of the current CT state and the internal winning combination, various lottery results of extra lottery (non-winning / additional 10 games /.../ over 300 games), and lottery results The correspondence relationship with the information on the attached lottery value is defined. Note that the names of the internal winning combinations shown in FIG. 53 correspond to the names of the sub-flags described above, and if a combination other than the internal winning combination (sub flag) shown in FIG. 53 is won internally, the winning lottery in CT will be won. Never do.

  In addition, in the extra lottery during the normal CT according to the present embodiment, the number of added games is changed according to the number of wins of the sub-flag “triple chilli lip” (internal winning combination “F_Challenging Lip” or “F_1 Challenging Lip”). To do.

  Specifically, when the number of wins of the sub-flag “Triple Chile Lip” in the same CT set is 1 to 8, the lottery results “addition_10G” and “addition_20G” shown in FIG. 53 are given. The number of additional games is 10 games and 20 games, respectively. Therefore, in this case, 10 games are easily determined as the number of additional games of ART. Further, when the number of wins of the sub-flag “triple chilli lip” in the same CT set is 9 to 16, the extra game given by the lottery results “addition_10G” and “addition_20G” shown in FIG. Both numbers are 20 games. That is, the number of added games (lottery result) corresponding to the lottery value “extremely high” of the sub flag “triple chililip” in FIG. 53 is promoted to 20 games. Therefore, in this case, 20 games are easily determined as the number of additional games of ART.

  In addition, when the number of wins of the sub flag “triple chililip” in the same CT set is 17 to 24, the extra game given by the lottery results “addition_10G” and “addition_20G” shown in FIG. Both numbers are 30 games. That is, the number of extra games (lottery results) corresponding to the lottery values “extremely high” and “extremely low” of the subflag “triple chilli lip” in FIG. 53 is promoted to 30 games. Therefore, in this case, “30 games” is easily determined as the number of additional games of ART. Further, when the number of wins of the sub-flag “triple chililip” in the same CT set is 25 times or more, the number of extra games given by the lottery results “addition_10G” and “addition_20G” shown in FIG. Both will be 50 games. That is, the number of extra games (lottery results) corresponding to the lottery values “extremely high” and “extremely low” of the sub-flag “triple chilli lip” in FIG. 53 is promoted to 50 games. Therefore, in this case, “50 games” is easily determined as the number of additional games of ART.

  As described above, in the pachi-slot 1 of the present embodiment, it is possible to increase the number of ART games that can be added by one extra lottery according to the number of wins of the sub-flag “triple chilli lip” in CT. Further, as described above, in this embodiment, as long as the number of ART games is added, CT does not end, and if the sub flag EX “triple chili lip” is won, CT is reset (stock). Is done. Therefore, in the present embodiment, as the CT continues, the player can be expected to increase the additional amount per game, and the interest during CT can be improved. In addition, since the number of wins of the sub-flag “triple chili lip”, which is an opportunity to increase the additional amount per game, is greater than the number of basic games (8 times) for CT 1 set (9 times or more), the player It is possible to prevent an excessive profit from being given to the player and to balance the profits between the player and the game store.

  In the present embodiment, the number of wins of the above-mentioned sub-flag “triple lip” (internal winning combination “F_accurate lip” or “F_1 credible lip”) is the number counted in the same CT set. The present invention is not limited to this. For example, a new CT that is given when a lottery is won by adding the number of sets performed during CT may also be included in “in the same CT set”.

[Number of sets in CT, lottery table]
FIG. 54 is a configuration diagram of the CT lot number addition lottery table used in the CT lot addition lottery performed during CT.

  The set lottery table for the number of sets during CT includes each combination of the current CT state and the internal winning combination (sub-flag “reach eye lip (reach eye lip 1 to 4)”), and various lottery results of the extra lottery (non-win / normal) CT winning / high probability CT winning) and the lottery value information associated with each lottery result are defined.

  As is clear from the lottery table for the number of sets during CT, if you win any of the “F_reach eye lip A” to “F_reach eye lip D” during CT, you will win the extra lottery of the CT set. (CT sets are always stocked). The set of stocked CT is started after the currently set CT is finished.

<Gameability in bonus state>
Next, with reference to FIG. 55A to FIG. 55C, the flow of the game during the bonus state will be described. FIG. 55A is a diagram showing a game flow when the gaming state shifts to the bonus state during the general gaming state (ART non-winning), and FIG. 55B shows a case where the gaming state shifts to the bonus state during the normal ART. FIG. 55C is a diagram showing a game flow when the game state shifts to a bonus state during CT.

  In the pachislot machine 1 of the present embodiment, as shown in FIGS. 55A to 55C, in terms of game play, a normal BB and a special BB are provided as bonus types, and the type of bonus is set when shifting to the bonus state. It is determined. At this time, if the special BB is determined, after the bonus state is ended, the gaming state shifts to CT via the ART preparation state. On the other hand, when the normal BB is determined, the game state of the transfer destination varies depending on the state before the shift to the bonus state.

  When the gaming state shifts from the general gaming state to the normal BB, as shown in FIG. 55A, in the game in the normal BB, the ART lottery is performed based on the internal winning combination. When this ART lottery is won, after the bonus state is over, the gaming state shifts to the normal ART via the ART preparation state. In this case, in the game in the bonus state after winning the ART lottery, the number of ART games is added and lottery is performed.

  When the gaming state shifts from normal ART to normal BB, CT lottery is performed at the end of normal BB, as shown in FIG. 55B. The winning probability of this CT lottery is 50%. After winning, the gaming state shifts to CT via the ART preparation state after the bonus state ends. On the other hand, if the CT lottery is not won, after the bonus state is over, the gaming state shifts to the normal ART via the ART ready state. In addition, in the game in the bonus state transferred from the normal ART, the number of ART games is added and lottery is also performed.

  When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 55C, the gaming state shifts to CT via the ART preparation state after the bonus state ends. In addition, in the game in the bonus state transferred from the CT, the number of ART games is added and lottery is also performed.

<Various data tables used in games in bonus state>
Next, with reference to FIGS. 56 to 58, various data tables used in the lottery process performed in the game in the bonus state will be described. Various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 56 is a configuration diagram of a bonus type lottery table used when determining the bonus type (normal BB, special BB).

  The bonus type lottery table includes game states (CT and other) before the transition to the bonus state, various lottery results (bonus type: normal BB / special BB), and lottery values associated with the lottery results. Define the correspondence with information. Note that the bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[A lottery table with bonus ART games]
FIG. 57 is a configuration diagram of the bonus lottery table used in the bonus lottery used in the lottery and ART game lottery performed in the game in the bonus state.

  The bonus lottery table for the number of bonus ART games includes each combination of the current bonus type and internal winning combination, various lottery results for the extra lottery (non-winning / 5 games /... / 300 games), and each lottery result. A correspondence relation with the information of the lottery value associated with the prescription is defined.

  In the present embodiment, in the ART non-winning state (the state up to winning an ART lottery in the normal BB shifted from the general gaming state), the bonus ART game number adding lottery table is used for the ART lottery. Specifically, when the number of extra games is determined by lottery using the bonus lottery table in the state of ART non-winning, the number of extra games is determined when the number of extra games is determined (one in the example shown in FIG. 57 is 50 games or more). While winning the lottery, the corresponding number of games is given as the number of ART games. On the other hand, in the state after the ART win, the bonus ART game number addition lottery table is used only for the ART game number addition lottery.

[CT lottery table at the end of bonus]
FIG. 58 is a configuration diagram of the bonus end CT lottery table used in the CT lottery performed at the end of the bonus state.

  The CT lottery table at the end of the bonus shows each combination of the bonus type (normal BB, special BB) and the game state before transitioning to the bonus state (during normal CT, high probability CT), and various lottery results of CT lottery ( Non-winning / normal CT winning / high probability CT winning) and a lottery value information associated with each lottery result are defined. As is apparent from the bonus end CT lottery table, for example, when a normal BB is performed during a normal ART, a CT is won with a probability of 50% at the end of the bonus state.

<Exceptional gameplay in general gaming state>
Next, with reference to FIG. 59, an exceptional game flow during the general game state will be described.

  In the basic game state flow in the pachislot machine 1 of the present embodiment, the game state shifts from the normal game state to the CZ during the general game state, and the game state shifts to the ART game state by winning the ART lottery in the CZ. To do. In this embodiment, the ART gaming state is realized by performing notification in the RT4 state. In the present embodiment, as shown in FIG. 59, RT state transition control is performed in accordance with the symbol combination to be stopped and displayed.

  In addition, since the symbol combination for shifting the RT state is one that is stopped and displayed according to the order (pushing order) of the player's stop operation (see FIG. 22), the notification is not performed. Coincidentally, the RT state may shift to the RT4 state. Further, in the RT4 state, any of the internal winning combination "F_reach eye lip A" to "F_reach eye lip D" may be determined, so even during the general gaming state (non-ART) Reach eyes to which a special privilege is given (a symbol combination related to the abbreviation “reach eye lip”) can be displayed.

  Therefore, in the pachi-slot 1 of this embodiment, as shown in FIG. 59, the RT state accidentally shifts to the RT4 state during the general gaming state (non-ART), and the symbol combination related to the abbreviation “reach eye lip” can be displayed. When the game state is changed, the game state can be shifted to the ART game state (normal ART) without going through the CZ.

  More specifically, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined in the general gaming state and in the RT4 state, a flag conversion lottery is performed, When the flag conversion lottery is won, a notification (navigation) for displaying a symbol combination related to the abbreviation “reach eye lip” is performed, and an ART right is granted. On the other hand, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined in the general gaming state and in the RT4 state, if the flag conversion lottery is not won, A notification for displaying the symbol combination related to the abbreviation “Replay” is performed, and control is performed so that the symbol combination related to the abbreviation “Reach Eye Lip” is not displayed.

<Various data tables used in exceptional game control during the general game state>
Next, with reference to FIG. 60, a data table used in the lottery process performed in the above-described exceptional game control during the general gaming state will be described. Note that a data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 60 is a configuration diagram of a non-ART flag conversion lottery table used in a flag conversion lottery performed in a game in the general gaming state and in the RT4 state.

  The non-ART flag conversion lottery table includes an internal winning combination (“F_reach eye lip A” to “F_reach eye lip D”), a flag conversion lottery result (no conversion / with conversion), and each lottery result. A correspondence relation with the information of the lottery value associated with the prescription is defined.

<Notification function by main side control>
In the conventional pachislot, information (navigation) of reel stop operation information (push order, etc.) is performed under the control of the sub (sub control board 72) side during ART. However, since the presence / absence of the notification affects the player's profit (so-called “out of ball”), in recent years, it is required to perform notification on the main (main control board 71) side that manages the player's profit. Yes. Therefore, in the pachi-slot 1 of the present embodiment, as described above, an instruction monitor (not shown) for notifying information of the stop operation is provided on the information display 6 controlled on the main side, and by the control on the main side, A function of notifying information on the reel stop operation is provided.

  Here, in FIG. 61A to FIG. 61D, in the pachislot machine 1 of the present embodiment, a correspondence relationship between notification (navigation) performed on the main side and notification (navigation) performed on the sub side is shown. FIG. 61A is a diagram showing a correspondence relationship between notification (navigation) performed on the main side and notification (navigation) performed on the sub side in the ART preparation state, and FIG. 61B is during ART (normal ART or CT). It is a figure which shows the correspondence of alerting | reporting (navigation) performed on the main side and alerting | reporting (navigation) performed on the sub side. FIG. 61C is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flag), and FIG. It is a figure which shows the correspondence of alerting | reporting (navigation) performed on the main side, and alerting | reporting (navigation) performed on the sub side (between BB2 flags).

  In this embodiment, as shown in FIGS. 61A to 61D, the main (main control board 71) side displays information on the reel stop operation by displaying numerical values “1” to “11” on the instruction monitor. Inform. The numerical values “1” to “11” displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

  Specifically, each of the numerical values “1” to “3” indicates the type of the reel that performs the first stop operation, and the numerical value “1” means that the first stop operation is performed on the left reel 3L. The numerical value “2” means that the first stop operation is performed on the middle reel 3C, and the numerical value “3” indicates that the first stop operation is performed on the right reel 3R.

  The numerical values “4” to “9” indicate the pressing order to be notified, and the numerical value “4” means that the pressing order is “left, middle, right”, and the numerical value “5”. Means push order is “left, right, middle”, numerical value “6” means push order is “middle, left, right”, numeric value “7” is push This means that the order is “middle, right, left”, the numerical value “8” means that the pressing order is “right, left, middle”, and the numerical value “9” means that the pressing order is It means the order of “right, middle, left”.

  The numerical values “10” and “11” respectively notify the bonus combination, and the numerical value “10” is a symbol combination (symbol “white 7” −symbol “white 7” −) associated with the combination name “C_BB1”. Symbol “white 7”), and the numerical value “11” means the symbol combination (symbol “blue 7” -design “blue 7” -design “blue 7”) associated with the combination name “C_BB2”.

  In addition, although the numerical values “1” to “11” notified on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be notified, all the players are clearly based on the numerical values. It is not always possible to grasp the contents of notification. For example, there is a possibility that the notification content cannot be grasped by some players just by displaying the numerical value “6” on the instruction monitor on the main side.

  Therefore, in the pachi-slot 1 of the present embodiment, information related to the stop operation of the stop button is also notified on the sub side together with the notification on the main side. Specifically, the display unit 11 (projector mechanism 211 and display unit 212) controlled on the sub side is used to notify information related to the stop operation by the control on the sub side.

  For example, when notifying the pressing order of performing the first stop operation on the left reel 3L, the main side displays a numerical value “1” on the instruction monitor, and on the sub side, the left reel in the display screen of the display device 11 is displayed. A numerical value “1” is displayed above 3L to notify that the left reel 3L is the target of the first stop operation. When notifying the push order “middle, left, right”, the main side displays the numerical value “6” on the instruction monitor, and the sub-side displays a numerical value above the middle reel 3C in the display screen of the display device 11. “1” is displayed, a numerical value “2” is displayed above the left reel 3L, a numerical value “3” is displayed above the right reel 3R, and the order of pressing is “middle, left, right”. Notify that. When the internal winning combination “F_BB1” is determined, the main side displays the numerical value “10” on the instruction monitor, and the sub-side displays “white 7” − “white 7” on the display screen of the display device 11. -Display information on the symbol combination of "White 7" and notify the player of the symbol to be aimed at.

  Note that the timing of notification on the main side can be set to any timing as long as it is at least a period of one game in which notification is performed. For example, the main-side notification may be performed at the timing when the player's start operation is detected (accepted), the main-side notification may be performed when the reel starts rotating, or the first stop operation to the third stop operation. The main-side notification may be performed at the timing when any one of the stop operations is detected. On the other hand, it is preferable that the notification timing on the sub side is at least a timing before the first stop operation. Therefore, in the pachi-slot 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or the timing at the start of reel rotation. Thereby, before the player performs the stop operation, information on the stop operation is notified on both the main-side instruction monitor and the sub-side display device 11.

  In the ART ready state, as shown in FIG. 61A, notification (navigation) called “bell navigation”, “maintenance return navigation”, “RT3 transition return navigation”, and “RT4 transition return navigation” is performed under the control of the main side. In “Bell Navi”, when the internal winning combination “F_3 selection bell_1st” to “F_3 selection bell_3rd” is determined, the symbol combination related to the abbreviation “Bell” (see FIG. 27) is stopped and displayed on the active line. The order of pressing is notified. In “Maintenance Lip Navi”, when the internal winning combination “F_Maintenance Lip_1st” to “F_Maintenance Lip_3rd” is determined, the symbol combination related to the abbreviation “Replay” (see FIG. 26) is stopped and displayed on the active line. The order of pressing is notified. In the “RT3 transition Lip navigator”, when the internal winning combinations “F_RT3 transition Lip_1st” to “F_RT3 transition Lip_3rd” are determined, the symbol combination (see FIG. 26) related to the abbreviation “RT3 transition Lip” is placed on the effective line. The order of pressing for stop display is notified. In addition, in the “RT4 transition Lip navigator”, when the internal winning combination “F_RT4 transition Lip_123” to “F_RT4 transition Lip_3rd” is determined, the symbol combination (see FIG. 26) related to the abbreviation “RT4 transition Lip” is activated. The order of pressing for stop display is informed.

  Also, in the ART gaming state (normal ART or CT), as shown in FIG. 61B, notifications referred to as “Bell Navi”, “Maintenance Lip Navi”, “RT 3 Transition Lip Navi”, and “RT 4 Transition Lip Navi” as shown in FIG. 61B. (Navigation) is performed. The game in the ART game state (RT4 state) is subjected to flag conversion lottery, and based on the lottery result, a symbol combination related to the abbreviation “triple chili lip”, “reach eye lip” or “replay” is displayed. However, this notification is performed only on the sub side and not on the main side.

  As mentioned above, the symbol combination related to the abbreviation “triple chili lip” or “reach eye lip” is related to the provision of a special privilege, so the presence or absence of notification affects the player's profit (out of play). Although it seems to give, in fact, in the pachislot 1 of this embodiment, since the special privilege is given based on the lottery result of the flag conversion lottery, the displayed symbol combination is given to the privilege to be given. It has no effect on it. Therefore, for example, in the state of winning the flag conversion lottery, even if the symbol combination related to the abbreviation “Replay” is stopped and displayed, a special privilege is given. On the other hand, even if the symbol combination related to the abbreviation “triple chilli lip” or “reach eye lip” can be stopped and displayed in a state where the flag conversion lottery is not won, no special privilege is given. In the pachi-slot 1 of this embodiment, when the symbol combination displayed in this way does not affect the player's profit (out), it is controlled on the sub-side without performing notification on the main-side instruction monitor. Notification is performed only on the display device 11.

  Also, in the RT5 state (inter-flag state), as shown in FIGS. 61C and 61D, information indicating that the player is aimed at the symbol combination related to the bonus combination carried over as the internal winning combination is notified. For example, when the internal winning combination “F_BB1” is carried over, as shown in FIG. 61C, notification (navigation) called “White 7 Navi” is performed under the control of the main side, and the internal winning combination “F_BB2” is performed. ”Is carried over, as shown in FIG. 61D, a notification (navigation) called“ blue 7 navigation ”is performed under the control of the main side.

  In “White 7 Navi”, the symbol combination corresponding to the internal winning combination “F_BB1”, that is, the symbol combination related to the combination name “C_BB1” (“White 7”-“White 7”-“White 7”: see FIG. 26) Information on stop operation for stopping and displaying on the active line is notified. In “Blue 7 Navi”, the symbol combination corresponding to the internal winning combination “F_BB2”, that is, the symbol combination related to the combination name “C_BB2” (“Blue 7”-“Blue 7”-“Blue 7”: FIG. 26) Information on stop operation for stopping display on the active line is notified.

  In the inter-flag state, when the bonus combination and any of the internal winning combination “out”, “F_special 1”, “F_special 2” and “F_special 3” are determined, as described with reference to FIG. The symbol combination relating to the bonus combination (BB combination) can be stopped and displayed on the active line. However, if an internal winning combination other than the internal winning combination “Out of”, “F_Special 1”, “F_Special 2” and “F_Special 3” and a bonus combination are won, the symbol combination related to the bonus combination Cannot be stopped on the active line. Therefore, in this embodiment, as shown in FIGS. 61C and 61D, the bonus combination carried over and the internal winning combination “out of”, “F_special combination 1”, “F_special combination 2” and “F_special” are displayed. Only when one of the “combination 3” is won, a notification called “white 7 navigation” or “blue 7 navigation” is performed by the control on the main side. Therefore, in the present embodiment, notification (navigation) called “white 7 navigation” or “blue 7 navigation” by the control on the main side can be performed at an appropriate timing at which the bonus combination can be won.

  Note that the pachi-slot 1 of the present embodiment is also provided with a function of giving a bonus notification by, for example, displaying a bonus confirmation screen or lighting a bonus confirmation lamp. Therefore, the main side may perform navigation called “white 7 navigation” or “blue 7 navigation” only after notifying (bonus notification) that the bonus combination is determined as the internal winning combination.

  As a bonus notification, for example, an effect that is performed over a plurality of game periods (a so-called continuous effect) and an effect of displaying a bonus confirmation screen according to the result of this continuous effect is generally performed. Yes. If “white 7 navigation” or the like is performed on the main side during such a continuous production, the result of the continuous production is known on the way, which may impair interest. Therefore, in the present embodiment, after the bonus notification is made, the main control board 71 performs notification (navigation) called “white 7 navigation” or “blue 7 navigation” under the control of the main side.

  It should be noted that any method for enabling the main side to grasp the timing at which the bonus notification is made is arbitrary. As one method, when the bonus combination is determined as an internal winning combination, the main control board 71 determines the number of games required until the bonus notification is completed, and after digesting the game of this number of games, A method of performing notification (navigation) called “blue 7 navigation” is conceivable. More specifically, when determining the number of games required until the bonus notification is completed, the main control board 71 notifies the sub control board 72 of the number of games. The sub-control board 72 controls the effect according to the number of games, and displays the bonus confirmation screen at the timing when the game of the number of games is consumed, thereby grasping the timing when the bonus notification is performed on the main side. Can do. That is, the main control board 71 counts the number of unit games since the bonus combination is determined as the internal winning combination in a state where the bonus combination is not carried over, and after the count result reaches a predetermined number, If any of the internal winning combination “Out of”, “F_Special combination 1”, “F_Special combination 2” and “F_Special combination 3” is determined as the internal winning combination “White 7 Navi” or “ Perform "Blue 7 Navigation".

  As another method, a method of controlling the bonus notification on the main side instead of the sub side is conceivable. More specifically, when the bonus combination is determined as an internal winning combination when the bonus combination is not carried over, the main control board 71 determines an effect (at least the number of games required for the effect) to be executed on the display device 11, The sub control board 72 is notified. The sub-control board 72 executes the notified effect and displays the bonus confirmation screen, whereby the timing at which the bonus notification is made on the main side can be grasped.

  Note that the main side may be able to grasp the timing at which the bonus notification is performed by a method other than the two methods described above. In this case, since the main control board 71 cannot accept a signal from the sub-control board 72 or the like, it is necessary to grasp the timing when the bonus notification is made based on the signal that can be accepted by the main control board 71. For example, since the signal accompanying the stop operation can be received by the main control board 71, when a predetermined stop operation (for example, other than forward pressing) is performed in a state where the bonus combination is determined as the internal winning combination In addition, a technique for giving a bonus notification is also conceivable. Specifically, the sub-control board 72 acquires information on the internal winning combination and information on the stop operation from the main control board 71, and performs bonus notification when the combination of these information is a predetermined combination. By adopting such a bonus notification method, the main control board 71 can grasp the trigger of the bonus notification, so that the timing at which the bonus notification is performed on the main side can be grasped.

<Description of main control circuit operation>
Next, the contents of various processes executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS.

[Processing at power-on (reset interrupt)]
First, the process at the time of power-on (reset interrupt) of the pachislot 1 performed under the control of the main CPU 101 will be described with reference to FIG. FIG. 62 is a diagram illustrating an example of a flowchart showing a procedure of processing at power-on (reset interrupt). 62, when the power supply management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 is started, the reset signal is sent to the “91” of the microprocessor 91. This is executed based on an interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 determines whether or not the power monitoring port (power monitoring means) is in an on state (S1).

  In S1, when the main CPU 101 determines that the power monitoring port is on (when S1 is YES), the main CPU 101 repeats the process of S1. Here, the power monitoring port being in the ON state is a state where the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

  On the other hand, when the main CPU 101 determines in S1 that the power monitoring port is not in the ON state (when S1 is NO), the main CPU 101 performs initialization processing of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 performs initial setting of the timer circuit 113. Specifically, the main CPU 101 sets a division ratio in a timer prescaler register (not shown), sets an interrupt enable setting in the timer control register (not shown), and sets a timer counter (not shown). Set the initial count value.

  Next, the main CPU 101 initializes the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. An initialization process is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test on the main RAM 103 (S5).

  Next, the main CPU 101 determines whether or not writing to the main RAM 103 has been normally performed as a result of the writing test (S6).

  In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S6 that the writing to the main RAM 103 has been performed normally (when S6 is YES), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. Is acquired (S7).

  Next, the main CPU 101 determines whether or not the current state is the generation timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether 1.1172 ms has elapsed since the start of the timer count based on the acquired state of the timer control register.

  In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. Thereafter, the status of the timer circuit 113 can be acquired by reading information in a timer control register (not shown). In this embodiment, a bit (determination bit) that can determine (refer to) whether or not the current state is the generation timing of an interrupt process (whether or not it is a timer interrupt state) in the timer control register. ) Is provided.

  Therefore, in the process of S7, the main CPU 101 reads information in the timer control register (not shown), and in the process of S8, the main CPU 101 turns on / off the discrimination bit in the timer control register ( By referring to “1” / “0”), it is determined whether or not the current state is the generation timing of the interrupt process. When 1.1172 ms elapses from the count start by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the determination bit is turned on.

  In S8, when the main CPU 101 determines that the current state is not the generation timing of the interrupt process (when S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

  On the other hand, when the main CPU 101 determines in S8 that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 performs a sum check process (not specified) (S9). . In this process, the main CPU 101 performs a sum check process of the main RAM 103, and the work of this process is performed in an unspecified work area (see FIG. 10C) in the main RAM 103. The program used in the sum check process is stored in an unspecified area in the main ROM 102 (see FIG. 10B). The details of the sum check process will be described later with reference to FIGS. 70 and 71 described later.

  In S8, when the main CPU 101 determines that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 determines the below-described interrupt before the process of S9. (See FIG. 110 described later). As a result of this interrupt processing, a no-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

  After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in an on state (S10).

  In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, when the main CPU 101 determines in S10 that the setting key switch 54 is not in the ON state (when S10 is NO), the main CPU 101 determines the sum check based on the result of the sum check process in S9. It is determined whether or not the result is normal (S11).

  In S11, when the main CPU 101 determines that the sum check determination result is not normal (when S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S11 that the sum check determination result is normal (when S11 is YES), the main CPU 101 performs a game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power interruption detection. The details of the game return process will be described later with reference to FIG. 63 described later.

  When S6 or S11 is NO, the main CPU 101 displays a character string “rr” indicating an error occurrence on the information display 6 (7-segment LED display) (S13). Thereafter, the main CPU 101 repeats the WDT clear process (S14).

  Here, returning to the process of S10 again, if S10 is YES, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation and storage process at the start of setting change. The details of the setting change confirmation process will be described later with reference to FIG.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets an address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 10C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared). Then, after the process of S16, the main CPU 101 starts a main process described later (see FIG. 72 described later).

[Game return processing]
Next, with reference to FIG. 63, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 62) will be described. FIG. 63 is a diagram showing an example of a flowchart showing the procedure of the game return process.

  First, the main CPU 101 sets the stack pointer at the time of power interruption to the stack pointer (SP) (S21). Next, the main CPU 101 clears (turns off) the on-edge data before the interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port to the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the data storage area of the current input port and before the one interrupt process (S24).

  Next, the main CPU 101 sets the address of the spinning cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

  Next, the main CPU 101 acquires reel control management information (data relating to display row fluctuation control when power interruption occurs) based on the address of the set spinning cylinder control data storage area (S27). Note that the reel control management information (display row variation control management information) is information related to the control state (rotation state) of each reel, and is backed up and stored when power is interrupted.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation state during the reel acceleration, the constant speed waiting, or the constant speed (S28).

  In S28, when the main CPU 101 determines that the condition of S28 is not satisfied (when S28 is NO), the main CPU 101 performs a process of S31 described later. On the other hand, when the main CPU 101 determines in S28 that the condition of S28 is satisfied (when S28 is YES), the main CPU 101 clears the spinning control data (reel control management information) (S29). With this process, after the game returns, the reel rotation control is started from the acceleration process. Next, the main CPU 101 sets a reel operation timing value (rotation control data execution start timing “1”) (S30). Note that when “1” is set as the reel operation timing, the main CPU 101 controls the rotation of the reel since the excitation change timing is reached in the reel control process (see S905 to S909 in FIG. 110 described later). Start with accelerated processing.

  After the process of S30 or when S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is “0” (S32).

  In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not “0” (when S32 is NO), the main CPU 101 changes the reel to be checked and changes the process to the process of S27. Return and repeat the processing from S27.

  On the other hand, when the main CPU 101 determines in S32 that the value of the number of reels after subtraction is “0” (when S32 is YES), the main CPU 101 performs a RAM initialization process (S33). In this process, the main CPU 101 sets the address at the time of “power recovery” in the game RAM area of the main RAM 103 shown in FIG. 10C as the start address of the start of initialization, and starts from the start address to the end of the game RAM area. Erase (clear) information up to the address.

  Next, the main CPU 101 restores all the register data saved at the time of detecting power interruption to all the registers (S34). After the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of detecting the power interruption.

  In the present embodiment, the game return process is performed as described above. In the game return process of the present embodiment, as described above, the input / output state of each port at the time of power failure is ensured at the time of power recovery, and when the reel is rotating at the time of power failure, the reel control management is performed at the time of power recovery. The processing necessary for acquiring the information and starting the reel re-rotation is also performed (refer to the processing of S25 to S32). Therefore, in the present embodiment, even when the power is restored from the power interruption during the rotation of the spinning cylinder, the reel re-rotation control can be stably performed, and the player does not feel uncomfortable.

[Setting change confirmation process]
Next, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 62) will be described with reference to FIG. FIG. 64 is a diagram showing an example of a flowchart showing the procedure of the setting change confirmation process.

  First, the main CPU 101 performs an initialization process for an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt waiting process (S42). In this process, the main CPU 101 stands by until the transmission process of the no-operation command to the sub control circuit 200 by the interrupt process is completed.

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets an address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 10C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared).

  Next, the main CPU 101 determines whether or not the setting key type switch 54 is on (S44). A setting key (not shown) inserted into the setting key switch 54 is an operation key for operating the settings (settings 1 to 6) of the pachislot 1. When the setting key is turned on, the setting key (not shown) is set. The key type switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (in the case where S44 is NO), the main CPU 101 ends the setting change confirmation processing and turns on the power (reset interrupt). ) The process proceeds to S16 in the time process (see FIG. 62). On the other hand, when the main CPU 101 determines in S44 that the setting key type switch 54 is in the ON state (when S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this processing, the solenoid of the selector 66 (see FIG. 5) is not driven, and the inserted medal is discharged from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets setting change start or setting check start information (005H: first value) in the L register, and generates and stores a setting change command (setting change / setting check start) (S46). . In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. 66 described later. Also, the setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Sent to.

  Next, the main CPU 101 sets the error count relay to an on state (S47). Next, the main CPU 101 determines which setting change or setting confirmation has been performed (S48).

  In S48, when the main CPU 101 determines that the setting has not been changed (setting has been confirmed) (when S48 is NO), the main CPU 101 performs the process of S55 described later.

  On the other hand, when the main CPU 101 determines in S48 that the setting has been changed (the setting has not been confirmed) (when S48 is YES), the main CPU 101 performs a setting value update process (S49). ). Next, the main CPU 101 performs setting value 7-segment display setting processing (S50). By this processing, the updated set value can be displayed by the 7-segment LED in the information display 6.

  Next, the main CPU 101 determines whether or not the reset switch 76 is on (S51).

  When the main CPU 101 determines in S51 that the reset switch 76 is in the on state (when S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, when the main CPU 101 determines in S51 that the reset switch 76 is not in the on state (when S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the on state (S52). .

  In S52, when the main CPU 101 determines that the start switch 79 is not on (when S52 is NO), the main CPU 101 returns the process to the process of S51 and repeats the processes after S51. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is on (when S52 is YES), the main CPU 101 sets a setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  Next, the main CPU 101 determines whether or not the setting key switch 54 is in an OFF state (S54).

  In S54, when the main CPU 101 determines that the setting key switch 54 is not in the OFF state (when S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (when S54 is YES), the main CPU 101 performs the process of S55 described later.

  When S48 is NO or S54 is YES, the main CPU 101 determines whether setting change or setting confirmation has been performed (S55).

  When the main CPU 101 determines in S55 that the setting has not been changed (setting confirmation has been performed) (when S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, when the main CPU 101 determines in S55 that the setting has been changed (the setting has not been confirmed) (when S55 is YES), the main CPU 101 performs a RAM initialization process (S56). . In this process, the main CPU 101 uses, as a start address for starting initialization, an address (at the end of setting change) (not shown) in the game RAM area of the main RAM 103 shown in FIG. 10C. The information from the head address to the last address of the game RAM area is erased (cleared).

  After the process of S56 or when S55 is NO, the main CPU 101 sets setting change end information or setting check end information (004H: second value) in the L register, and a setting change command (setting change / setting check end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. Also, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Sent to. After the process of S57, the main CPU 101 ends the setting change confirmation process, and moves the process to the process of S16 of the power-on (reset interrupt) process (see FIG. 62).

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 64) will be described with reference to FIG. FIG. 65 is a diagram showing an example of a flowchart showing the procedure of the setting change command generation / storage process.

  First, the main CPU 101 sets information of setting values (1 to 6) in the E register (S61). Next, the main CPU 101 sets RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 performs communication data storage processing (S64). In this process, the main CPU 101 determines the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 64) (setting change start / setting change end / setting status). The setting change command data is generated using the setting confirmation start / setting confirmation end), and the generated command data is stored in the communication data storage area. Details of the communication data storage processing will be described later with reference to FIG. 66 described later.

  After the process of S64, the main CPU 101 ends the setting change command generation / storage process. When ending the setting change command generation / storage process performed in S46 during the setting change confirmation process (see FIG. 64), the main CPU 101 performs the process of the setting change confirmation process (see FIG. 64) after the process in S64. The process proceeds to S47. When the setting change command generation / storage process performed in S57 during the setting change confirmation process (see FIG. 64) is to be ended, the main CPU 101 ends the setting change command generation / storage process after the process of S64. The change confirmation process (see FIG. 64) is also terminated.

  As described above, in the setting change command generation / storage process, the setting status is stored in the D register as the communication parameter 4 immediately before the setting change command generation / storage process is executed, and the setting value is set during the execution of the setting change command generation / storage process. Is stored in the E register as communication parameter 3, and RT information is stored in the C register as communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. Therefore, the values stored in the L register and the H register at the present time are set, respectively. Therefore, the values of the communication parameters 1 and 2 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Communication data storage processing]
Next, with reference to FIG. 66, for example, the communication data storage process performed in S64 in the setting change command generation / storage process (see FIG. 65) will be described. Note that the communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 66 is a diagram showing an example of a flowchart showing a procedure of communication data storage processing.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as communication command parameters 1 and 2, respectively (S72). .

  Next, the main CPU 101 stores the data set in the D register and E register as communication command parameters 3 and 4 in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register in the communication data temporary storage area in the main RAM 103 as the communication command parameter 5 and the RT state data, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in a communication data temporary storage area in the main RAM 103 (S76).

  After the process of S76, the main CPU 101 determines whether or not there is an empty communication data storage area in the main RAM 103 (S77).

  In S77, when the main CPU 101 determines that there is no free space in the communication data storage area (when S77 is NO), the main CPU 101 ends the communication data storage process and, for example, a setting change command generation storage process ( The process also ends (see FIG. 65).

  On the other hand, when the main CPU 101 determines in S77 that the communication data storage area is free (when S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the processes of S71 to S76 described above. The communication data is stored in the communication data storage area as communication command data (S78).

  Next, the main CPU 101 performs communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating a communication data pointer indicating a storage address of communication data in the communication data storage area. Details of the communication data pointer update process will be described later with reference to FIG. 67 described later.

  Then, after the process of S79, the main CPU 101 ends the communication data storage process and also ends the setting change command generation / storage process (see FIG. 65), for example.

[Communication data pointer update processing]
Next, with reference to FIG. 67, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 68) will be described. FIG. 67 is a diagram showing an example of a flowchart showing the procedure of the communication data pointer update process.

  First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer for one packet (8 bytes) (S82). In this process, when the updated communication data pointer value is equal to or larger than the upper limit size of the communication data storage area, the main CPU 101 sets the updated communication data pointer value to “0”. As a result, all command data stored in the communication data storage area are invalidated (similar to the discarded state).

  In the present embodiment, the amount of data (one packet) transmitted in one transmission operation is 8 bytes. That is, in this embodiment, one command data can be transmitted by one transmission operation. In the present embodiment, since a maximum of nine command data can be stored in the communication data storage area, the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). Therefore, in this embodiment, the range of the communication data pointer is set to “0” to “71”, and the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is “71 ( If the value exceeds the upper limit value), set the updated communication data pointer value to “0” (return the communication data storage destination address to the top address) and store the communication data. Invalidate all command data stored in the area (similar to the discarded state). If the value of the communication data pointer is set to “0”, the next time command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area. The command data is overwritten with new command data. Therefore, in this embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds “71 (upper limit value)”.

  After the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 66).

[Power failure (external) processing]
Next, the process at the time of power failure of pachislot 1 performed by the control of the main CPU 101 (external) will be described with reference to FIG. FIG. 68 is a flowchart showing a procedure of processing at the time of power interruption (external). 68, the power interruption (external) process is performed when the power management circuit 93 detects a drop (power interruption) in the power supply voltage supplied to the microprocessor 91. And is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 saves data set in all registers (S91). Next, the main CPU 101 reads data set in the power interruption detection port (S92).

  Next, the main CPU 101 determines whether or not the power failure detection port is on (S93).

  In S93, when the main CPU 101 determines that the power interruption detection port is not in the on state (when S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 terminates the power interruption (external) processing. It should be noted that these processes performed when S93 is NO corresponds to the instantaneous power failure countermeasure process that occurs when the power management circuit 93 instantaneously detects a power interruption.

  On the other hand, when the main CPU 101 determines in S93 that the power failure detection port is in the ON state (when S93 is YES), the main CPU 101 sets the medal insertion impossible and sets the stop of the hopper device 51. (S95).

  Next, the main CPU 101 stores the value of the currently set stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 performs checksum generation processing of the main RAM 103 (S97). This process is performed in an unspecified work area in the main RAM 103 (see FIG. 10C). The program used in the checksum generation process is stored in an unspecified area in the main ROM 102 (see FIG. 10B). Details of the checksum generation process will be described later with reference to FIG. 69 described later.

  Next, the main CPU 101 sets prohibition of access to the main RAM 103 (S98). Then, after the process of S98, an infinite loop process is performed until the power supply stops (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation processing (not specified)]
Next, with reference to FIG. 69, the checksum generation processing performed in S97 during power interruption (external) processing (see FIG. 68) will be described. FIG. 69 is a diagram showing an example of a flowchart showing the procedure of checksum generation processing.

  First, the main CPU 101 stores the current stack pointer (SP) value (the in-use address of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets an upper address value (F0H) of the RAM address (non-standard stack area address) in the Q register (S103). Next, the main CPU 101 sets a power interruption occurrence flag (S104).

  Next, the main CPU 101 sets the calculation start address of the sum value in the game RAM area to the stack pointer, and sets the sum calculation counter to the value obtained by dividing the number of bytes in the storage area for the sum value calculation by “2”. Set (S105). The sum calculation counter is a counter for determining the end timing of the sum value calculation, and is provided in the main RAM 103. When the sum calculation counter set in S105 becomes “0”, the game RAM area sum value calculation process of the main RAM 103 ends.

  Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value “0” of the sum value is set.

  Next, the main CPU 101 executes an instruction code called a “POP instruction” (specific instruction), and stores data (stored value) for 2 bytes from the storage area address of the main RAM 103 set in the stack pointer (SP). ) Is read into the DE register (S107). When the “POP” instruction is executed, the data (memory contents) stored in the 1-byte area at the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address obtained by updating the updated address by 1 is loaded into the upper register of the pair register. When the “POP” instruction is executed, an address update process for 2 bytes (a process of adding “2” to the address) is performed on the address set in the stack pointer (SP). Therefore, in the process of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and stored at the address obtained by adding “1” to the address specified by the stack pointer. Data (memory contents) is loaded into the D register.

  After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (in the case where S110 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standardized thumb count value is the number of bytes in the non-standardized storage area. Therefore, when the sum calculation counter set in S111 becomes “0”, the sum value calculation process for the non-standard RAM area of the main RAM 103, that is, the sum value calculation process for the entire main RAM 103 is completed.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S112). Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value in the HL register as a sum value. Next, the main CPU 101 adds 1 to the address stored in the DE register, and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S115).

  In S115, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S115 is NO), the main CPU 101 returns the process to the process of S112 and repeats the processes after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the unspecified RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

  On the other hand, when the main CPU 101 determines in S115 that the value of the sum calculation counter is “0” (in the case where S115 is YES), the main CPU 101 uses the value stored in the HL register when the power interruption occurs. Is stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S101 to the stack pointer (S117). After the process of S117, the main CPU 101 ends the checksum generation process, and moves the process to the process of S98 of the power interruption (external) process (see FIG. 68).

[Sum check processing (not specified)]
Next, the sum check process performed in S9 during the power-on process (see FIG. 62) will be described with reference to FIGS. 70 and 71 are diagrams showing an example of a flowchart showing the procedure of the sum check process.

  First, the main CPU 101 stores the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets a value obtained by dividing the number of bytes in the sum value calculation target storage area by “2” in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end timing of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 obtains a sum value (check sum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power interruption occurs is stored in the HL register.

  Next, the main CPU 101 executes a “POP” instruction, and reads data (stored value) of 2 bytes from the storage area address of the main RAM 103 set in the stack pointer (SP) to the DE register (S124). . At this time, by executing the “POP” instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is set. Data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register. When the “POP” instruction is executed, an address update process for two bytes (a process for adding two addresses) is performed on the address set in the stack pointer (SP). Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial value of the sum value or the sum value after the previous subtraction process). The value is stored in the HL register as a sum value. Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S127 is NO), the main CPU 101 returns the process to the process of S124 and repeats the processes after S124. That is, the processes of S124 to S127 are repeated until the sum value subtraction process is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is “0” (in the case where S127 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard thumb count value is the number of bytes in the non-standard RAM area.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S129). Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value. Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S132).

  In S132, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S132 is NO), the main CPU 101 returns the process to the process of S129 and repeats the processes after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire non-standard RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is “0” (when S132 is YES), the main CPU 101 sets “sum abnormality” in the determination result of the sum check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134). In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value is “0” when the value of the sum calculation counter set in S128 becomes “0”, that is, when the sum value subtraction process is completed over the entire area of the main RAM 103. In the case of “0”, “1” is set in the zero flag of the flag register F, and “0” is set in the zero flag of the flag register F when the sum value is not “0”. Therefore, if “1 (ON state)” is set in the zero flag of the flag register F at the time of the processing of S134, the main CPU 101 determines that the sum value is “0”.

  In S134, when the main CPU 101 determines that the calculated sum value is not “0” (when S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, when the main CPU 101 determines in S134 that the calculated sum value is “0” (when S134 is YES), the main CPU 101 sets “power failure abnormality” as the determination result (S135). ).

  Next, the main CPU 101 acquires a power interruption occurrence flag (S136). Next, the main CPU 101 determines whether or not the power interruption occurrence flag is in a state without power interruption (off state) (S137).

  In S137, when the main CPU 101 determines that the power interruption occurrence flag is in a state where there is no power interruption (when S137 is YES), the main CPU 101 performs a process of S139 described later. On the other hand, when the main CPU 101 determines in S137 that the power interruption occurrence flag is not in the state without power interruption (when S137 is NO), the main CPU 101 sets “normal” as the determination result (S138).

  After S138, if S134 is NO or S137 is YES, the main CPU 101 stores the determination result in the sum check determination result and clears (turns off) the power interruption occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S121 to the stack pointer (S140). After the process of S140, the main CPU 101 ends the sum check process, and moves the process to the process of S10 of the power-on process (see FIG. 62).

[Main processing of pachislot by control of main CPU]
Next, with reference to FIG. 72, the main process (main operation process) of the pachi-slot 1 executed under the control of the main CPU 101 will be described. FIG. 72 is a flowchart (hereinafter, referred to as main flow) showing a procedure of main processing.

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address at the end of one game in the game RAM area of the main RAM 103 shown in FIG. Erase (clear) information up to the last address. The storage area in this range is a storage area that needs to be erased for each unit game (game) such as an internal winning combination storage area or a display combination storage area.

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this processing, the main CPU 101 performs input check processing such as a medal sensor (not shown) and the start switch 79. The details of the medal acceptance / start check process will be described later with reference to FIG. 73 described later.

  Next, the main CPU 101 performs random number acquisition processing (S203). In this processing, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: the value of the random number register 0 of the random number circuit 110 to be a hard latch random number) or a random number value for effects used in various lotteries related to ART ( 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 serving as a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 serving as a soft latch random number) The various random numbers extracted are stored in a random value storage area (not shown) provided in the main RAM 103. Details of the random number acquisition process will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. Details of the internal lottery process will be described later with reference to FIG. 78 described later.

  Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. Etc. Details of the symbol setting process will be described later with reference to FIG. 79 described later.

  Next, the main CPU 101 performs a start command generation / storage process (S206). In this processing, the main CPU 101 generates start command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. Note that the start command includes a parameter (such as a subflag) that identifies an internal winning combination.

  Next, the main CPU 101 performs a second interface board control process (S207). Note that the second interface board control process is executed in a non-standard work area of the main RAM 103.

  Next, the main CPU 101 performs state-specific control processing (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-specific control processing will be described later with reference to FIG. 81 described later.

  Next, the main CPU 101 performs reel stop initial setting processing (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (see FIG. 24), and sets the drawing priority table selection table number, the drawing priority table number, and the stopping table number based on the internal winning combination and the gaming state. Processing to acquire, processing to store “3” in the stop button non-operation counter, and the like are performed.

  Next, the main CPU 101 performs reel rotation start processing (S210). In this process, the main CPU 101 requests the start of rotation of all reels. Then, when the start of rotation of all reels is requested, driving of three stepping motors (not shown) is performed by an interrupt process (see FIG. 110, which will be described later) executed at a constant cycle (1.1172 msec). Is controlled, and rotation of the left reel 3L, the middle reel 3C, and the right reel 3R is started. Next, each reel is controlled to be accelerated until its rotational speed reaches a constant speed, and then controlled so as to maintain the constant speed.

  Next, the main CPU 101 performs reel rotation start command generation / storage processing (S211). In this processing, the main CPU 101 generates reel rotation start command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. The reel rotation start command includes a parameter indicating that the reel rotation start operation has started.

  Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the pull-in priority data and stores it in the pull-in priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 96 described later.

  Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 performs stop control of rotation of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C, and the right stop button 17R are respectively pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG.

  Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 33) in the winning action flag storage area (see FIGS. 26 to 28). In this process, the main CPU 101 determines whether or not a display combination is displayed on the active line, and sets the number of medals to be paid out based on the determination result. Details of the winning search process will be described later with reference to FIG.

  Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 combines a winning request flag (internal winning combination) and a winning action flag (display combination), and determines the presence or absence of an illegal hit error based on the combined result. The details of the illegal hit check process will be described later with reference to FIG. 103 described later.

  Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a winning operation command generation process. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of display combination payouts determined in S214, and performs a medal payout process. Details of the winning check / medal payout process will be described later with reference to FIG.

  Next, the main CPU 101 performs a BB check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. Details of the BB check process will be described later with reference to FIG.

  Next, the main CPU 101 performs RT check processing (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination that is stopped and displayed on the active line. Details of the RT check process will be described later with reference to FIGS. 107 and 108 described later.

  Next, the main CPU 101 performs CZ / ART termination processing (S219). In this process, the main CPU 101 mainly performs a CZ pull-back lottery process. Details of the CZ / ART termination process will be described later with reference to FIG. 109 described later. After the process of S219 (after the end of one game), the main CPU 101 returns the process to the process of S201.

[Medal reception / start check processing]
Next, with reference to FIG. 73, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 72) will be described. FIG. 73 is a diagram showing an example of a flowchart showing the procedure of medal acceptance / start check processing.

  First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is “1” or more, the main CPU 101 determines that there is an automatic insertion request. The automatic insertion medal counter is data for identifying whether or not a display combination relating to replay (replay) has been established in the previous unit game. When the display combination related to the re-game is established, the medals for the number of coins inserted in the previous unit game are automatically inserted into the automatic insertion medal counter.

  In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is “0” (when S221 is YES), the main CPU 101 performs the process of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not “0” (when S221 is NO), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, a medal insertion number LED lighting control process, and the like. Details of the medal insertion process will be described later with reference to FIG. 74 described later.

  Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is “0” (S224).

  In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not “0” (when S224 is NO), the main CPU 101 returns the process to S222 and repeats the processes after S222.

  On the other hand, when the main CPU 101 determines in S224 that the value of the automatic insertion medal counter is “0” (when S224 is YES), or when S221 is YES, the main CPU 101 stores the medal auxiliary storage. A warehouse switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not a medal can be inserted based on the result of the medal insertion state check process (S227).

  When the main CPU 101 determines in S227 that the medal cannot be inserted (when S227 is NO), the main CPU 101 performs a process of S231 described later.

  On the other hand, when the main CPU 101 determines in S227 that the medal can be inserted (when S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, for example, based on the medal sensor input state, the main CPU 101 determines whether or not a medal has passed normally, and credits the medal when a medal is inserted beyond a prescribed number. Perform processing. Details of the medal insertion check process will be described later with reference to FIG. 75 described later.

  Next, based on the result of the medal insertion check process, the main CPU 101 determines whether or not a medal can be inserted or credited (S229).

  When the main CPU 101 determines in S229 that the medal can be inserted or credited (YES in S229), the main CPU 101 performs a process of S231 described later. On the other hand, when the main CPU 101 determines in S229 that the medal cannot be inserted or credited (NO in S229), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24.

  After S230, when S227 is NO or when S229 is YES, the main CPU 101 determines whether or not the current number of inserted medals is the game start possible number (S231). In the present embodiment, the number of games that can be started is three (see FIGS. 26 to 28).

  In S231, when the main CPU 101 determines that the current number of inserted medals is the game start number (when S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of inserted medals is not the game start possible number (when S231 is NO), the main CPU 101 determines whether or not there are medals inserted (S232). ).

  When the main CPU 101 determines in S232 that a medal has been inserted (when S232 is YES), the main CPU101 returns the process to S226 and repeats the processes after S226. On the other hand, when the main CPU 101 determines in S232 that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described with reference to FIG. 64 (S233). In this processing, the main CPU 101 performs processing for generating and storing a setting change command at the start of setting confirmation.

  After the processing of S233 or when S231 is YES, the main CPU 51 determines whether or not the start switch 79 is on (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the ON state (when S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines in S234 that the start switch 79 is on (when S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24. After the process of S235, the main CPU 101 ends the medal acceptance / start check process, and moves the process to S203 of the main flow (see FIG. 72).

[Medal insertion processing]
Next, with reference to FIG. 74, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 73) will be described. FIG. 74 is a diagram showing an example of a flowchart showing the procedure of medal insertion processing.

  First, the main CPU 101 adds “1” to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 performs medal insertion command generation / storage processing (S242). In this process, the main CPU 101 generates medal insertion command data to be transmitted to the sub control circuit 200 and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub-control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 every time a medal is inserted. The medal insertion command includes a parameter for specifying the number of inserted coins.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 5) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the medal insertion number based on the medal insertion number (medal counter value) (S244). In this process, for example, when the number of inserted medals is 1, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated. For example, the number of inserted medals is 3. LED lighting data for lighting all the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 uses the calculated LED lighting data to light up the corresponding medal insertion number display LED (S245). After the process of S245, the main CPU 101 ends the medal insertion process, and moves the process to S223 of the medal acceptance / start check process (see FIG. 73).

[Medal insertion check process]
Next, with reference to FIG. 75, the medal insertion check process performed in S228 during the medal acceptance / start check process (see FIG. 73) will be described. FIG. 75 is a diagram showing an example of a flowchart showing the procedure of the medal insertion check process.

  First, the main CPU 101 determines whether or not replaying is in progress (S251).

  When the main CPU 101 determines in S251 that the game is being replayed (when S251 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 73). To S229.

  On the other hand, when the main CPU 101 determines in S251 that the game is not being replayed (when S251 is NO), the main CPU 101 permits medal acceptance (S252). In this processing, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 24 are accepted. The received medals are counted and guided to the hopper device 51.

  Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1 bet button 15b) has been operated based on the on / off state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the bet button check process in S253 (S254).

  When the main CPU 101 determines in S254 that the betting operation has been completed (when S254 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 73). To S229.

  On the other hand, when the main CPU 101 determines in S254 that the betting operation has not been completed (in the case where S254 is NO), the main CPU 101 determines the medal sensor input state (game medium acceptance state) during the current process, The medal sensor input state at the time of the previous process is acquired (S255). The medal sensor input state is information indicating the passage status of medals received in the medal insertion slot 24 in the selector 66, and the detection results of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by

  In this embodiment, the medal sensor input state is represented by 1-byte (8-bit) data, and the first medal sensor (not shown) on the upstream side provided side by side in the medal passage direction at the exit of the selector 66. The detection result corresponds to the information of bit 0 (“0” or “1”), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the information of bit 1 (“0” or “1”). To do. When the passage of the medal is detected by the first medal sensor, “1” is set to the bit 0, and when the passage of the medal is detected by the second medal sensor, “1” is set to the bit 1. Is done. Therefore, the medal sensor input state “00000000B” indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state “00000001B” indicates the state when the medal passage starts, and the medal sensor input state “ “00000011B” indicates a state in which a medal is passing, and a medal sensor input state “00000010B” indicates a state immediately before completion of medal passing.

  Next, the main CPU 101 determines whether or not the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (S256).

  In S256, when the main CPU 101 determines that the medal sensor input state during the current process has not changed from the medal sensor input state during the previous process (when S256 is NO), the main CPU 101 proceeds to S261 described below. Process.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (when S256 is YES), the main CPU 101 Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained in the current process is generated by arithmetic processing (S257).

  In this process, when the medal sensor input state at the time of the previous process is “00000000B” (when both the first and second medal sensors are not detected), the normal change value of the medal sensor input state is used. When “00000001B” (when the first medal sensor is medal detection and the second medal sensor is not medal detection) is generated, and the medal sensor input state at the previous processing is “00000001B”, the medal sensor As a normal change value of the input state, “00000011B” (when both the first and second medal sensors are medal detection) is generated. In this process, if the medal sensor input state at the previous process is “00000011B”, the normal change value of the medal sensor input state is “00000010B” (the first medal sensor is not detected, the second When the medal sensor is medal detection) and the medal sensor input state at the time of the previous process is “00000010B”, the normal change value of the medal sensor input state is “00000000B” (first and second medals). When both medals have not been detected yet). The method for generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current process is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition in S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

  In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not the same as the normal change value generated in S257 (when S258 is NO), the main CPU 101 performs the process of S262 described later. Do.

  On the other hand, when the main CPU 101 determines in S258 that the medal sensor input state at the current process is the same as the normal change value generated at S257 (when S258 is YES), the main CPU 101 It is determined whether or not the medal sensor input state is a medal passing state (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is a state when the medal passes (when S259 is YES), the main CPU 101 performs the process of S263 described later.

  In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not a medal passage state (when S259 is NO), the main CPU 101 sets a medal passage check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to the medal sensor input state at the time of the current process, for example.

  After the processing of S260 or when S256 is NO, the main CPU 101 determines whether the medal sensor input state at the time of the current processing is a state in which a medal is passing (“00000011B”) and the medal passing check timer is stopped. Is determined (S261). In this determination process, it is determined whether or not a medal passage error (inserted medal passage time error) has occurred, and when the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passage error has occurred.

  In S261, when the main CPU 101 determines that the determination condition of S261 is not satisfied (when S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is YES), or when S258 is NO, that is, a medal passing error or a medal retrograde error has occurred. When it is determined that the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation / storage process. Details of error processing will be described later with reference to FIG. 76 described later. After the process of S262, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  Here, returning to the process of S259 again, if S259 is YES, the main CPU 101 determines whether or not a prescribed number (three in this embodiment) of medals has been inserted (S263). .

  In S263, when the main CPU 101 determines that the prescribed number of medals has not been inserted (when S263 is NO), the main CPU 101 performs the medal insertion process described with reference to FIG. 74 (S264). After the process of S264, the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines in S263 that the specified number of medals has been inserted (when S263 is YES), the main CPU 101 adds “1” to the value of the credit counter (S265). ). Next, the main CPU 101 performs medal insertion command generation storage processing (S266). In this process, the main CPU 101 generates medal insertion command data to be transmitted to the sub control circuit 200 and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub-control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the credit number of medals is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

  When the main CPU 101 determines that the medal credit number is not the upper limit value in S267 (when S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, when the main CPU 101 determines in S267 that the credit number of medals is the upper limit value (when S267 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check. The process proceeds to S229 in the process (see FIG. 73).

[Error handling]
Next, with reference to FIG. 76, for example, the error process performed in S262 during the medal insertion check process (see FIG. 75) will be described. FIG. 76 is a diagram showing an example of a flowchart showing a procedure of error processing.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 5). Next, the main CPU 101 performs evacuation processing of medal payout number display data (S272).

  Next, the main CPU 101 performs error table setting processing (S273).

  Next, the main CPU 101 acquires an error factor (S274). Note that the error factor acquired in this process varies depending on the process from which the currently processed error process is read. Note that error factors to be targeted in the present embodiment include “hopper empty error”, “hopper jam error”, “inserted medal passage count error”, “inserted medal passage check error”, “inserted medal passage check error”, The “inserted medal passage time error”, “inserted medal retrograde error”, “inserted medal auxiliary storage full error”, and “illegal hit error” are defined.

  Next, the main CPU 101 acquires error display data from the error table and error factors (S275). For example, when the error factor is “inserted medal retrograde error (Cr)”, two characters “Cr” are displayed as error information on the two-digit 7-segment LED.

  Next, the main CPU 101 performs error command (occurrence) generation and storage processing (S276). In this process, the main CPU 101 generates error command data to be transmitted to the sub control circuit 200 when an error occurs, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of occurrence of an error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The error command when an error occurs includes a parameter indicating the error occurrence.

  Next, the main CPU 101 performs standby processing for one interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been canceled (S278).

  When the main CPU 101 determines in S278 that the error has not been canceled (when S278 is NO), the main CPU 101 returns the process to the process of S277 and repeats the processes after S277.

  On the other hand, when the main CPU 101 determines in S278 that the error has been canceled (in the case where S278 is YES), the main CPU 101 performs error factor clear processing (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a return process of the payout number display data of medals saved in S272 (S280).

  Next, the main CPU 101 performs error command (cancellation) generation and storage processing (S281). In this process, the main CPU 101 generates error command data to be transmitted to the sub-control circuit 200 at the time of error cancellation, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The error command at the time of error cancellation includes a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing and shifts the processing to S253 in the medal insertion check processing (see FIG. 75), for example. In the error cancellation, the error factor that has occurred is canceled, and the error state is canceled by pressing the reset switch 76.

[Random number acquisition processing]
Next, the random number acquisition process performed in S203 in the main flow (see FIG. 72) will be described with reference to FIG. FIG. 77 is a flowchart showing the procedure of random number acquisition processing.

  First, the main CPU 101 acquires the hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as the random number value for the internal winning combination lottery in the random value storage area (invalid) in the main RAM 103. (S291).

  Next, the main CPU 101 generates soft latch random numbers (0 to 65535: production random numbers used in ART-related lottery processing, and 0 to 255: 1 byte random processing). To set the soft latch random number acquisition register (S292). Next, the main CPU 101 sets the number of acquired soft latch random numbers (for example, 7) (S293).

  Next, the main CPU 101 obtains the acquired number of soft latch random numbers at once and stores the acquired number of soft latch random numbers in the random number storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random value storage area. It is stored in an area different from the area where the latch random number (random number value for internal winning combination lottery) is stored. Then, after the process of S294, the main CPU 101 ends the random number acquisition process, and moves the process to S204 of the main flow (see FIG. 72). In this embodiment, in order to store four 2-byte random numbers and four 1-byte random numbers, a 12-byte storage area is allocated as a random number storage area in the main RAM 103.

[Internal lottery processing]
Next, with reference to FIG. 78, the internal lottery process performed in S204 in the main flow (see FIG. 72) will be described. In addition, FIG. 78 is a figure which shows an example of the flowchart which shows the procedure of an internal lottery process.

  First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 performs a check process for the current game setting value (any one of 1 to 6) and the number of inserted medals (three in this embodiment).

  Next, the main CPU 101 sets the internal lottery table for general games and the number of lotteries (53 times in this embodiment) (S302).

  Next, the main CPU 101 determines whether or not the RB is operating (S303). In S303, when the main CPU 101 determines that the RB is not operating (when S303 is NO), the main CPU 101 performs a process of S305 described later.

  On the other hand, when the main CPU 101 determines in S303 that the RB is operating (when S303 is YES), the main CPU 101 determines the internal lottery table for RB and the number of lotteries (in this embodiment, five times). Set (S304). In this process, the internal lottery table and the number of lotteries for the general game set in S302 are overwritten with the internal lottery table for the RB and the number of lotteries.

  After the process of S304 or when S303 is NO, the main CPU 101 acquires the determination data (data relating to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether the determination data is RT state data (S306). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the RT state.

  In S306, when the main CPU 101 determines that the determination data is not RT state data (when S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, when the main CPU 101 determines in S306 that the determination data is the RT state data (when S306 is YES), the main CPU 101 selects the selected data from the RT state lottery value selection table based on the determination data. And the acquired selection data is set as determination data (S307).

  After the processing of S307 or when S306 is NO, the main CPU 101 determines whether the determination data of the lottery target combination is data by setting (S308). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the set value.

  In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, when the main CPU 101 determines in S308 that the determination data is data by setting (when S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is data associated with the set value. However, the set value data “0” to “5” is not “the set value itself” but “ Data corresponding to “Setting 1” to “Setting 6”.

  After the processing of S309 or when S308 is NO, the main CPU 101 calculates the address of the area where the lottery value of the lottery target role is stored based on the set determination data (address data), and sets the address The stored lottery value is acquired (S310).

  In the present embodiment, when the lottery value depends on both the RT state and the set value, such as the internal winning combination “F_Maintenance Lip A”, for example, the internal lottery value table and the internal lottery classified by setting are used. The lottery value is acquired with reference to both of the value tables.

  Next, the main CPU 101 acquires a random number value (any one of 0 to 65535) for internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 performs lottery execution processing (S312). In this process, the main CPU 101 adds the random number acquired in S311 to the lottery value acquired in S310, and sets the addition result as a lottery result (winning / non-winning for the lottery target role). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (when overflowing), it is determined that the lottery target combination is won (the lottery target combination is determined as an internal winning combination). The

  Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not a lottery execution process has been won (whether or not an overflow has occurred) (S314).

  In S314, when the main CPU 101 determines that the lottery execution process has been won (when S314 is YES), the main CPU 101 refers to the internal lottery table, and the winning request flag status (corresponding to the internal winning combination won) “Value of special prize winning number + small role winning number”) is acquired (S315). For example, in a general game, when winning the lottery execution process when the lottery target role is “F_definite chip”, the winning request flag status “(00H * 25H) + 02H” (special prize winning number = 0, small winning number = 2) is acquired. Then, after the process of S315, the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 72).

  On the other hand, when it is determined in S314 that the main CPU 101 has not won the lottery execution process (when S314 is NO), the main CPU 101 updates the lottery object combination to the next combination in the internal lottery table, and lottery is performed. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the number of lotteries after subtraction is not “0” (when S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

  On the other hand, when the main CPU 101 determines in S317 that the number of lotteries after subtraction is “0” (when S317 is YES), that is, when the internal winning combination is “out”, the main CPU 101 The lose status is set (S318). Note that the “losing status” corresponds to a hit request flag status in which both the special prize winning number and the small bonus winning number are “0”. Then, after the process of S318, the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 72).

[Design setting process]
Next, with reference to FIG. 79, the symbol setting process performed in S205 in the main flow (see FIG. 72) will be described. FIG. 79 is a flowchart showing the procedure of the symbol setting process.

  First, the main CPU 101 extracts a special prize winning number and a small bonus winning number based on the winning request flag status acquired in the internal lottery process, and the extracted special winning prize number and small bonus winning number are stored in the main RAM 103. It is stored in a winning number storage area (not shown) (S321).

  Next, the main CPU 101 determines whether or not a small combination is won based on the extracted small combination winning number (S322). In this process, when the small combination winning number is any one of 1 to 36, the main CPU 101 determines that the small combination winning number has been won, and when the small combination winning number is 0, the main CPU 101 It is determined that the small role did not win.

  In S322, when the main CPU 101 determines that a small role is not won (when S322 is NO), the main CPU 101 performs processing of S331 described later. On the other hand, when the main CPU 101 determines in S322 that the small combination has been won (when S322 is YES), the main CPU 101 sets the small combination winning number as an initial value of the subtraction result (S323).

  Next, the main CPU 101 sets a hit request flag table (S324). Next, the main CPU 101 subtracts 1 from the subtraction result and updates the subtraction result (S325). Next, the main CPU 101 determines whether or not the subtraction result is less than “0” (S326).

  When the main CPU 101 determines in S326 that the subtraction result is not less than “0” (when S326 is NO), the main CPU 101 performs a bit number calculation process (S327). In the bit number calculation process of S327, the number of blocks in the storage area of the hit request flag data corresponding to the small combination winning number specified in the hit request flag table is acquired.

  In the present embodiment, in the hit request flag storage area (internal winning combination storage area), blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11 are provided. Therefore, the maximum value of the number of blocks in the storage area for the hit request flag data acquired in the bit number calculation process of S327 is “2”. For example, when the internal winning combination is “F_definite chip”, as shown in the hit request flag table, the storage area 7 included in the block of the hit request storage areas 0 to 7 and the hit request storage areas 8 to 11 Since the hit request flag data is defined for each storage area 9 included in each block, the number of blocks in the hit request flag data storage area acquired in the bit number calculation process of S327 is “2”.

  Next, the main CPU 101 performs a bit number calculation process (S328). In the bit number calculation process in S328, the number of bytes of hit request flag data in block units defined in the hit request flag table is calculated. For example, when the internal winning combination is “F_definite chip”, since 1-byte hit request flag data is stored in the storage area 7 and the storage area 9 as shown in the hit request flag table, the bit of S328 The number of bytes of request flag data per block acquired in the number calculation process is 1 byte.

  In addition, the process of S325-S328 mentioned above is repeated by the frequency | count of a small winning number. For example, when the internal winning combination is “F_Challenging Lip” (the small winning combination number is “2”), the above-described processing of S325 to S328 is repeated twice. In addition, when the processes of S325 to S328 are repeated a plurality of times, the number of blocks and the number of bytes of the per-block hit request flag data respectively obtained in the bit number calculation processes of S327 and S328 are stored in separate storage areas. Is done. Further, the number of blocks and the number of bytes of hit request flag data in units of blocks obtained by the above-described processing of S325 to S328 are information (on-bit information) for specifying the storage destination of the hit request flag data.

  Here, returning to the process of S326 again, when the main CPU 101 determines in S326 that the subtraction result is less than “0” (when S326 is YES), the main CPU 101 determines the hit request flag storage area ( The internal winning combination storage area) is set (S329).

  Next, the main CPU 101 performs compressed data storage processing (S330). In this process, the main CPU 101 mainly performs a process of transferring (developing) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). Details of the compressed data storage processing will be described later with reference to FIG.

  After the process of S330 or when S322 is NO, the main CPU 101 refers to the carryover combination storage area (see FIG. 29) and determines whether there is a carryover combination (S331). When the main CPU 101 determines in S331 that there is a carryover combination (when S331 is YES), the main CPU 101 performs a process of S334 described later.

  On the other hand, when the main CPU 101 determines in S331 that there is no carryover combination (when S331 is NO), the main CPU 101 determines the bonus combination (BB1 or BB2) based on the special prize winning number extracted in the process of S321. ) Is determined whether or not (S332).

  In S332, when the main CPU 101 determines that the bonus combination is not won (when S332 is NO), the main CPU 101 ends the symbol determination process, and the process proceeds to S206 of the main flow (see FIG. 72). Transfer.

  On the other hand, when the main CPU 101 determines that the bonus combination is won in S332 (when S332 is YES), the main CPU 101 stores the winning prize winning number in the carryover combination storage area (S333).

  After the processing of S333 or when S331 is NO, the main CPU 101 sets the special prize winning number in the winning number storage area (not shown), sets the winning request flag data in the winning request flag storing area, and sets the RT state to RT5. The state is set, and the RT game number (the number of digest games in the RT1 state) is cleared (“0”) (S334). After the process of S334, the main CPU 101 ends the symbol setting process, and moves the process to S206 of the main flow (see FIG. 72).

[Compressed data storage processing]
Next, with reference to FIG. 80, for example, the compressed data process performed in S330 during the symbol setting process (see FIG. 79) will be described. FIG. 80 is a flowchart showing a procedure of compressed data storage processing.

  The compressed data storage process shown in FIG. 80 is executed not only in S330 during the symbol setting process (see FIG. 79) but also in S652 during the symbol code acquisition process (see FIG. 97 described later). In the compressed data storage process executed in S330 during the symbol setting process (see FIG. 79), the flag data to be processed is the hit request flag data (the flag data related to the winning combination). In the compressed data storage process executed in S652 (see FIG. 97 described later), the flag data to be processed is winning action flag data (flag data relating to a winning combination). The two processes are the same except that the types of flag data to be processed are different.

  Therefore, in the flowchart of FIG. 80, flag data to be processed is referred to as “processing target flag data”, and a flag table to be processed is referred to as “processing target flag table”. In accordance with this description, in the following explanation of the compressed data storage process, the winning request flag data or the winning action flag data is referred to as “processing target flag data”, and the winning request flag table or a symbol corresponding winning action table described later is used. Is referred to as a “processing target flag table”.

  First, the main CPU 101 sets a storage location check bit (S341). In this processing, the storage destination check bit is stored in a register other than the A register.

  The storage destination check bit is 1-byte data for designating a block that is a storage destination (transfer destination) of processing target flag data. In the present embodiment, the winning request flag storage area and the winning action flag storage area are both composed of two blocks (a storage area 0-7 block and a storage area 8-11 block).

  Next, the main CPU 101 sets the value of the transfer counter in bytes to “8” (S342). In this embodiment, since the number of bytes in each block is “8”, “8” is set as the initial value of the transfer counter.

  Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the process of S343, the storage destination check bit stored in the 1-byte register is right-shifted once (one bit). As a result, the transfer instruction bit is extracted. Specifically, when a 1-byte register (register other than the A register) storing the storage destination check bit is right-shifted once, the data stored in bits 7 to 1 is changed to bits 6 to 0, respectively. While moving, the data of bit 0 before the shift is output. The data output by this shift process becomes the value of the transfer instruction bit.

  Next, the main CPU 101 determines whether there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when “00000011B” is set as the storage destination check bit, transfer processing is performed in the determination process of S344 for the first time (corresponding to the first block of the storage area) and for the second time (corresponding to the second block of the storage area). Although it is determined that there is an instruction, it is determined that there is no transfer instruction in the determination process of S344 after the third time.

  In S344, when the main CPU 101 determines that there is no transfer instruction (when S344 is NO), the main CPU 101 performs the process of S354 described later.

  On the other hand, when the main CPU 101 determines in S344 that there is a transfer instruction (YES in S344), the main CPU 101 acquires byte unit storage location designation information from the processing target flag table (S345). In this processing, 1 indicating the transfer destination, which is stored at the start address of the area in which the flag data of the processing target combination (winning combination or winning combination) in the processing target flag table is stored as the byte unit storage location designation information. Byte data is obtained.

  Next, the main CPU 101 performs an update process of an address referred to in the process target flag table (a process of adding 1 to the address) (S346). In this process, the main CPU 101 sets an address that designates the head storage area of the block that is the storage (transfer) destination of the processing target flag data as an initial address. For example, in the process of the first block, the address of the storage area 0 is set as the initial address in the process of S346, and in the process of the second block, the address of the storage area 8 is set as the initial address in the process of S346. .

  Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage location designation information (S347). Note that the transfer instruction bit here corresponds to bit 0 of the byte unit storage location designation information, and in the process of S347, the byte unit storage location designation information stored in the 1 byte register is shifted once to the right. Thus, the value of the transfer instruction bit is extracted (bit 0 data is output).

  Next, the main CPU 101 determines whether there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when “00000010B” is set as the byte unit storage location designation information, the data “1” of bit 1 in the processing of S347 for the second time (storage area 1 of the first block or storage area 9 of the second block). Is output as the value of the transfer instruction bit, and it is determined that there is a transfer instruction, but in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

  When the main CPU 101 determines in S348 that there is no transfer instruction (when S348 is NO), the main CPU 101 performs the process of S351 described later.

  On the other hand, when the main CPU 101 determines that there is a transfer instruction in S348 (when S348 is YES), the main CPU 101 determines the processing target flag stored at the address in the currently set processing target flag table. Data (winning request flag data or winning action flag data) is transferred (copied) to the designated storage area (S349).

  Next, the main CPU 101 performs an update process of an address referred to in the process target flag table (a process of adding 1 to the address) (S350).

  After the process of S350 or when S348 is NO, the main CPU 101 performs an address update process (a process of adding 1 address) that specifies a storage area that is a storage destination of the processing target flag data (S351). Next, the main CPU 101 subtracts 1 from the value of the transfer counter (S352).

  Next, the main CPU 101 determines whether or not the value of the transfer counter is “0” (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not “0” (when S353 is NO), the main CPU 101 returns the process to the process of S347 and repeats the processes after S347.

  On the other hand, in S353, when the main CPU 101 determines that the value of the transfer counter is “0” (in the case of YES determination in S353), the main CPU 101 determines whether the transfer instruction target remains in the current storage destination check bit. It is determined whether or not (S354). In this process, the main CPU 101 determines whether or not there remains a bit storing “1” in the storage destination check bit at the time of the current process. Then, the main CPU 101 instructs to transfer to the current storage destination check bit when there is a bit storing “1” in the storage destination check bit, that is, when there is a block to be processed. It is determined that the target remains.

  When the main CPU 101 determines in S354 that the transfer instruction target remains in the current storage location check bit (when S354 is YES), the main CPU 101 returns the process to the process of S342, and the processes after S342 repeat. On the other hand, when the main CPU 101 determines in S354 that there is no transfer instruction target remaining in the current storage destination check bit (when S354 is NO), the main CPU 101 ends the compressed data storage process and performs the process. For example, the process proceeds to S331 in the symbol setting process (see FIG. 79).

[Control processing by status]
Next, with reference to FIG. 81, the state-specific control process performed in S208 in the main flow (see FIG. 72) will be described. FIG. 81 is a flowchart showing the procedure of the state-specific control process.

  First, the main CPU 101 performs sub-flag conversion processing (S401). In this process, the main CPU 101 performs a process of converting the internal winning combination into a sub flag (see FIGS. 34 and 35). The details of the subflag conversion process will be described later with reference to FIG.

  Next, the main CPU 101 performs a navigation set process (S402). In this process, the main CPU 101 acquires navigation data based on the RT state, the gaming state, and the small combination winning number. The details of the navigation set process will be described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the current RT state is the RT4 state (S403). In S403, when the main CPU 101 determines that the current RT state is not the RT4 state (when S403 is NO), the main CPU 101 performs a process of S406 described later.

  On the other hand, when the main CPU 101 determines in S403 that the current RT state is the RT4 state (when S403 is YES), the main CPU 101 performs flag conversion processing (S404). In this process, the main CPU 101 performs a flag conversion lottery process (sub-flag data compression process) for converting the sub-flag into the sub-flag EX (see FIG. 34). By this flag conversion process, 19 types (including loss) of sub-flags are converted (compressed) into 9 types (including loss) of sub-flags EX. The details of the flag conversion process will be described later with reference to FIG. 109 described later.

  Next, the main CPU 101 performs sub-flag compression processing (S405). In this process, the main CPU 101 converts the sub flag EX into a sub flag D (see FIG. 34), and further compresses the sub flag data. By this sub-flag compression processing, nine types (including loss) of sub-flags EX are converted (compressed) into seven types (including loss) of sub-flags D.

  After the processing of S405 or when S403 is NO, the main CPU 101 determines whether or not the current gaming state is the normal gaming state (S406).

  In S406, when the main CPU 101 determines that the current gaming state is the normal gaming state (when S406 is YES), the main CPU 101 performs normal start processing (S407). Details of the normal start process will be described later with reference to FIG. Then, after the processing of S407, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S406 that the current gaming state is not the normal gaming state (when S406 is NO), the main CPU 101 determines whether or not the current gaming state is CZ ( S408).

  In S408, when the main CPU 101 determines that the current gaming state is CZ (when S408 is YES), the main CPU 101 performs start processing during CZ (S409). The details of the start process during CZ will be described later with reference to FIG. 86 described later. Then, after the processing of S409, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S408 that the current gaming state is not CZ (when S408 is NO), the main CPU 101 determines whether or not the current gaming state is normal ART (S410). ).

  In S410, when the main CPU 101 determines that the current gaming state is the normal ART (when S410 is YES), the main CPU 101 performs a start process during the normal ART (S411). Details of the start processing during normal ART will be described later with reference to FIG. 90 described later. Then, after the processing of S411, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S410 that the current gaming state is not the normal ART (when S410 is NO), the main CPU 101 determines whether or not the current gaming state is CT (S412). ).

  In S412, when the main CPU 101 determines that the current gaming state is CT (when S412 is YES), the main CPU 101 performs start processing during CT (S413). Details of the start process during CT will be described later with reference to FIG. 91 described later. Then, after the processing of S413, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S412 that the current gaming state is not CT (when S412 is NO), the main CPU 101 determines whether or not the current gaming state is a bonus state (S414). ).

  In S414, when the main CPU 101 determines that the current gaming state is a bonus state (when S414 is YES), the main CPU 101 performs a start-time process during BB (S415). The details of the processing at the time of starting during BB will be described later with reference to FIG. 95 described later. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines that the current gaming state is not the bonus state in S414 (when S414 is NO), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a gaming state other than the gaming state targeted by the various determination processes. For example, when the current gaming state is the ART ready state, processing corresponding to the ART ready state is performed. Then, after the processing of S416, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 72).

[Sub flag conversion processing]
Next, with reference to FIG. 82, the subflag conversion process performed in S401 in the state-specific control process (see FIG. 81) will be described. FIG. 82 is a diagram showing an example of a flowchart showing the procedure of the subflag change process.

  First, the main CPU 101 acquires a small combination winning number (0 to 36) (S421). Next, the main CPU 101 determines whether or not a bonus is currently being operated (S422).

  In S422, when the main CPU 101 determines that the bonus operation is currently being performed (in the case where S422 is YES), the main CPU 101 converts the small role winning number into a bonus operating sub-flag and saves it (S423). . After the process of S423, the main CPU 101 ends the subflag conversion process, and moves the process to S402 of the control process for each state (see FIG. 81).

  On the other hand, when it is determined in S422 that the main CPU 101 is not currently operating the bonus (when S422 is NO), the main CPU 101 sets a sub-flag conversion table (S424).

  Next, the main CPU 101 determines whether the data of the small role winning number specified in the block in the subflag conversion table currently being referred to is data corresponding to the small bonus winning number acquired in the current game. It is determined whether or not (S425).

  In S425, the main CPU 101 determines that the data of the small role winning number specified in the block in the subflag conversion table to be referred to is not data corresponding to the small bonus winning number acquired in the current game. When (NO in S425), the main CPU 101 updates the block in the subflag conversion table to be referenced to the block of the next address (S426). Next, the main CPU 101 adds “1” to the value of the subflag (S427). After the process of S427, the main CPU 101 returns the process to the process of S425, and repeats the processes after S425.

  On the other hand, in S425, the data of the small combination winning number specified in the block in the sub flag conversion table that is the reference target of the main CPU 101 is data corresponding to the small combination winning number acquired in the current game. Is determined (when S425 is YES), the main CPU 101 refers to the sub-flag conversion table and sets the sub-flag conversion control data associated with the small role winning number (the address next to the address of the small bonus winning number). (Stored 1-byte data) is acquired, and the sub-flag conversion control data is stored in a sub-flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). After the process of S428, the main CPU 101 ends the subflag conversion process, and moves the process to S402 of the control process for each state (see FIG. 81).

[Naviset processing]
Next, with reference to FIG. 83, the navigation set process performed in S402 in the state-specific control process (see FIG. 81) will be described. FIG. 83 is a diagram showing an example of a flowchart showing the procedure of the navigation set process.

  First, the main CPU 101 determines whether or not a navigation set flag is set in a sub-flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub-flag conversion control data storage area, and the set sub-flag conversion control data is data corresponding to the small combination winning numbers (10 to 23) that generate the push order navigation. It is determined whether or not. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub-flag conversion control data storage area (when S431 is NO), the main CPU 101 ends the navigation set process, and the process is classified by state. The process proceeds to S403 of the control process (see FIG. 81).

  On the other hand, when the main CPU 101 determines in S431 that the navigation set flag is set in the sub-flag conversion control data storage area (when S431 is YES), the main CPU 101 is in the RT0 or RT1 state. Whether or not (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (when S432 is NO), the main CPU 101 ends the navigation set process, and the process is controlled according to the state (see FIG. 81). To S403.

  On the other hand, in S432, when the main CPU 101 determines that the RT state is the RT0 or RT1 state (when S432 is YES), the main CPU 101 determines whether or not the gaming state is the general gaming state ( S433). In S433, when the main CPU 101 determines that the gaming state is the general gaming state (when S433 is YES), the main CPU 101 ends the navigation set process, and the process is controlled according to the state (see FIG. 81). To S403.

  On the other hand, when the main CPU 101 determines in S433 that the gaming state is not the general gaming state (when S433 is NO), the main CPU 101 acquires the small role winning number (S434). Next, the main CPU 101 refers to the navigation data table and acquires navigation data (any one of 1 to 9) based on the small combination winning number (S435).

  Next, the main CPU 101 stores the acquired navigation data (information related to the stop operation of the variable display of the plurality of display columns) in a navigation data storage area (stop operation instruction information storage area) (not shown) in the main RAM 103 (S436). After the process of S436, the main CPU 101 ends the navigation set process, and moves the process to S403 of the control process for each state (see FIG. 81).

[Flag conversion process]
Next, with reference to FIG. 84, the flag conversion process performed in S404 in the state-specific control process (see FIG. 81) will be described. FIG. 84 is a flowchart showing the procedure of flag conversion processing.

  First, the main CPU 101 determines whether or not it is the CT start time (S441).

  In S441, when the main CPU 101 determines that it is not the CT start time (when S441 is NO), the main CPU 101 performs the process of S443 described later. On the other hand, when it is determined in S441 that the main CPU 101 is at the start of CT (when S441 is YES), the main CPU 101 determines the table number of the flag conversion lottery table used for the flag conversion lottery during CT by lottery. And set (S442).

  After the processing of S442 or when S441 is NO, the main CPU 101 sets a flag conversion lottery table corresponding to the current state (S443). For example, when the current state is a non-ART RT4 state, a non-ART flag conversion lottery table (see FIG. 60) is set, and when the current state is a normal ART RT4 state, An ART flag conversion lottery table (see FIGS. 45A and 45B) is set. If the current state is the RT4 state during CT, a CT flag conversion lottery table (see FIG. 52) is set.

  Next, the main CPU 101 refers to the set flag conversion lottery table and performs flag conversion lottery processing based on the internal winning combination (S444). In fact, in this process, the main CPU 101 performs the flag conversion lottery process using the subflag conversion control data acquired from the subflag conversion table based on the subflag corresponding to the internal winning combination.

  Next, the main CPU 101 determines whether or not the flag conversion lottery of S444 has been won (S445).

  When the main CPU 101 determines in S445 that the flag conversion lottery has been won (when S445 is YES), the main CPU 101 performs sub-flag conversion processing (S446). In this process, for example, when the internal winning combination is “F_1 correct Chile Lip”, that is, when the sub flag is “Triple Chile Lip B (03)”, when the flag conversion lottery process is won, the sub flag conversion process of S446 is performed. Then, the subflag “triple dust B (03)” is converted to the subflag EX “determined combination (06)” or subflag EX “triple dust (07)” (see FIG. 34).

  After the processing of S446, the main CPU 101 determines whether or not the current gaming state is a non-ART state (S447). In S447, when the main CPU 101 determines that the current gaming state is not the non-ART state (when S447 is NO), the main CPU 101 ends the flag conversion process, and the process is controlled according to the state (see FIG. 81). ) To S405.

  On the other hand, when the main CPU 101 determines in S447 that the current gaming state is the non-ART state (when S447 is YES), the main CPU 101 adds “1” to the number of ART sets (S448). Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S449). Then, after the process of S449, the main CPU 101 ends the flag conversion process, and moves the process to S405 of the state-specific control process (see FIG. 81).

  Here, returning to the process of S445 again, when it is determined in S445 that the main CPU 101 has not won the flag conversion lottery (when S445 is NO), the main CPU 101 performs the sub flag maintaining process (S450). . In this process, for example, when the internal winning combination is “F_1 exact Chile Lip”, that is, when the sub flag is “Triple Chile Lip B (03)”, if the flag conversion lottery is non-winning, the sub flag is maintained in S450. Through the processing, the subflag “triple lip B (03)” is converted (maintained) into the subflag EX “replay (01)”. Then, after the process of S450, the main CPU 101 ends the flag conversion process, and moves the process to S405 of the control process for each state (see FIG. 81).

[Normal start processing]
Next, with reference to FIG. 85, the normal start process performed in S407 in the state-specific control process (see FIG. 81) will be described. FIG. 85 is a flowchart showing the procedure of normal start processing.

  First, the main CPU 101 refers to the CZ lottery table (see FIG. 39A), and performs CZ lottery processing based on the current CZ lottery state and internal winning combination (sub flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery of S461 has been won (S462).

  In S462, when the main CPU 101 determines that the CZ lottery has not been won (when S462 is NO), the main CPU 101 performs a process of S465 described later.

  On the other hand, when it is determined in S462 that the main CPU 101 has won the CZ lottery (when S462 is YES), the main CPU 101 sets the type of CZ that has won the game state of the next game (S463). Next, the main CPU 101 sets the number of CZ games of the winning type in the CZ game number counter (S464). The CZ game number counter is a counter that counts the duration of CZ and is provided in the main RAM 103. In the process of S464, for example, when CZ1 is won, the first predetermined game number (for example, “12”) is set in the CZ game number counter (first half), and CZ2 is won. When the second predetermined game number (for example, “15”) is set in the CZ game number counter (first half) and CZ3 is won, the fourth predetermined game number is displayed in the CZ game number counter. (For example, “17”) is set.

  After the processing of S464 or when S462 is NO, the main CPU 101 refers to the normal medium / high probability lottery table (see FIG. 38A) and performs the lottery of the CZ lottery state based on the internal winning combination (sub flag) (S465). ). Next, the main CPU 101 updates the lottery state of the CZ based on the result of the transfer lottery (S466). Then, after the process of S466, the main CPU 101 ends the normal start process and also ends the state-specific control process (see FIG. 81).

[Process during start during CZ]
Next, with reference to FIG. 86, a description will be given of the start process during CZ performed in S409 in the control process by state (see FIG. 81). FIG. 86 is a flowchart showing the procedure of the start time process during CZ.

  First, the main CPU 101 determines whether or not the current gaming state is CZ1 (S471).

  In S471, when the main CPU 101 determines that the current gaming state is CZ1 (when S471 is YES), the main CPU 101 performs processing during CZ1 (CZ2) (S472). The details of the middle processing in CZ1 (CZ2) will be described later with reference to FIGS. 87 and 88 described later. Then, after the process of S472, the main CPU 101 ends the start-time process during CZ and also ends the control process by state (see FIG. 81).

  On the other hand, when the main CPU 101 determines in S471 that the current gaming state is not CZ1 (when S471 is NO), the main CPU 101 determines whether or not the current gaming state is CZ2 (S473). .

  In S473, when the main CPU 101 determines that the current gaming state is CZ2 (when S473 is YES), the main CPU 101 performs processing during CZ1 (CZ2) (S474). Details of the intermediate processing in CZ1 (CZ2) will be described later with reference to FIGS. 87 and 88 described later. Then, after the process of S474, the main CPU 101 ends the start-time process during CZ and also ends the control process for each state (see FIG. 81). In the present embodiment, only the rank (mode or point) indicating the degree of expectation for winning the ART lottery is different between the CZ1 middle processing and the CZ2 middle processing, and the basic processing content is the same. Therefore, in the present embodiment, the CZ1 mid-process and the CZ2 mid-process are described as one process as CZ1 (CZ2) mid-process.

  On the other hand, when the main CPU 101 determines in S473 that the current gaming state is not CZ2 (when S473 is NO), the main CPU 101 performs CZ3 mid-process (S475). The details of the CZ3 intermediate process will be described later with reference to FIG. 89 described later. Then, after the processing of S475, the main CPU 101 ends the start-time processing during CZ and also ends the state-specific control processing (see FIG. 81).

[CZ1 (CZ2) medium processing]
Next, with reference to FIG. 87 and FIG. 88, the process during CZ1 (CZ2) performed in S472 or S474 during the start time process during CZ (see FIG. 86) will be described. 87 and 88 are flowcharts showing the procedure of the process during CZ1 (CZ2).

  First, the main CPU 101 determines whether or not the current game is a game in the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not a game in the first half of CZ1 (or CZ2) (when S481 is NO), the main CPU 101 performs the process of S490 described later.

  On the other hand, when the main CPU 101 determines in S481 that the current game is a game in the first half of CZ1 (when S481 is YES), the main CPU 101 refers to the CZ1 mode-up lottery table (see FIG. 40). Then, a mode-up lottery process is performed based on the internal winning combination (sub flag) (S482). In S481, when the main CPU 101 determines that the current game is a game in the first half of CZ2 (when S481 is YES), the main CPU 101 refers to the point lottery table during CZ2 (see FIG. 41). Then, point-up lottery is performed based on the internal winning combination (sub flag) (S482).

  Next, the main CPU 101 updates the rank (mode or point) based on the lottery result in S482 (S483). Next, the main CPU 101 determines whether or not the freezing is won in the lottery of S482 (S484).

  When it is determined in S484 that the main CPU 101 has won the freeze (when S484 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game, and also includes the number of ART sets and the number of CT sets. "1" is added to (S485). In this process, the main CPU 101 determines and sets the ART level with reference to the ART level determination table (see FIG. 46A). When freeze occurs, “ART level 2” is determined as the ART level.

  Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S486). Then, after the processing of S486, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing at start during CZ (see FIG. 86).

  Here, returning to the processing of S484 again, when it is determined in S484 that the main CPU 101 has not won the freeze (when S484 is NO), the main CPU 101 determines the value of the CZ game number counter (first half). 1 is subtracted (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half) is “0” (S488).

  In S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is not “0” (when S488 is NO), the main CPU 101 ends the processing in CZ1 (CZ2). The start time process during CZ (see FIG. 86) is also terminated.

  On the other hand, in S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is “0” (when S488 is YES), the main CPU 101 determines that the game state of the next game is CZ1 or The latter half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing at start during CZ (see FIG. 86).

  Here, returning to the processing of S481 again, if S481 is NO, the main CPU 101 determines whether or not the current game is the first game in the second half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game in the second half of CZ1 or CZ2 (when S490 is NO), the main CPU 101 performs the process of S495 described later.

  On the other hand, when the main CPU 101 determines in S490 that the current game is the first game of the second half of CZ1 or CZ2 (when S490 is YES), the main CPU 101 determines that the ART lottery table during CZ (FIG. 42A and FIG. 42). Referring to FIG. 42B), the ART lottery process is performed based on the rank (mode or point) of the first half (S491).

  Next, the main CPU 101 determines whether or not the ART lottery has been won (S492). In S492, when the main CPU 101 determines that the ART lottery has not been won (when S492 is NO), the main CPU 101 performs a process of S494 described later.

  On the other hand, when it is determined in S492 that the main CPU 101 has won the ART lottery (when S492 is YES), the main CPU 101 adds “1” to the number of ART sets and determines the ART level determination table (see FIG. 46A). ) To perform ART level lottery and set the lottery result (S493).

  After the processing of S493 or when S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half) (S494). In the process of S494, for example, when the ART lottery is won, “4” is set in the CZ game number counter (second half), and when the ART lottery is not won, the number of CZ games is set. “3” is set in the counter (second half).

  After the processing of S494 or when S490 is NO, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 42C) and performs the ART lottery processing based on the internal winning combination (sub flag) (S495).

  Next, the main CPU 101 determines whether or not the ART lottery has been won (S496). When the main CPU 101 determines in S496 that the ART lottery has not been won (when S496 is NO), the main CPU 101 performs a process of S498 described later.

  On the other hand, when it is determined in S496 that the main CPU 101 has won the ART lottery (when S496 is YES), the main CPU 101 adds “1” to the number of ART sets and determines the ART level determination table (see FIG. 46A). ), The ART level lottery is performed, and the lottery result is set (S497).

  After the processing of S497 or when S496 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (second half) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is “0” (S499).

  In S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is not “0” (when S499 is NO), the main CPU 101 ends the CZ1 (CZ2) process, The start time process during CZ (see FIG. 86) is also terminated.

  On the other hand, when the main CPU 101 determines in S499 that the value of the CZ game number counter (second half) is “0” (when S499 is YES), the main CPU 101 determines that the number of ART sets is “1” or more. It is determined whether or not (S500).

  In S500, when the main CPU 101 determines that the number of ART sets is “1” or more (when S500 is YES), the main CPU 101 sets the ART ready state to the game state of the next game (S501). Then, after the processing of S501, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing during start during CZ (see FIG. 86).

  On the other hand, when the main CPU 101 determines in S500 that the number of ART sets is not “1” or more (when S500 is NO), the main CPU 101 sets the CZ failure state to the gaming state of the next game ( S502). Then, after the process of S502, the main CPU 101 ends the process during CZ1 (CZ2) and also ends the process during start during CZ (see FIG. 86).

[CZ3 medium processing]
Next, with reference to FIG. 89, the process during CZ3 performed in S475 during the process during start during CZ (see FIG. 86) will be described. Note that FIG. 89 is a flowchart showing the procedure of the processing in CZ3.

  First, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 43) and performs ART lottery processing based on the internal winning combination (sub flag) (S511).

  Next, the main CPU 101 determines whether or not the ART lottery has been won (S512). When the main CPU 101 determines in S512 that the ART lottery has not been won (when S512 is NO), the main CPU 101 performs a process of S518 described later.

  On the other hand, when it is determined in S512 that the main CPU 101 has won the ART lottery (when S512 is YES), the main CPU 101 adds “1” to the number of ART sets and “1” to the number of CT sets. Addition is performed (S513). Next, the main CPU 101 determines whether or not the freezing is won in the ART lottery of S512 (S514).

  In S514, when the main CPU 101 determines that it has not won the freeze (when S514 is NO), the main CPU 101 performs a process of S516 described later. On the other hand, when it is determined in S514 that the main CPU 101 has won the freeze (when S514 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game (S515).

  After the processing of S515 or when S514 is NO, the main CPU 101 performs ART level lottery processing with reference to the ART level determination table (see FIG. 46A), and sets the lottery result (ART level) (S516). . Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S517). Then, after the processing of S517, the main CPU 101 ends the processing during CZ3 and also ends the processing during start during CZ (see FIG. 86).

  Here, returning to the processing of S512 again, if S512 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether or not the value of the CZ game number counter is “0” (S519).

  In S519, when the main CPU 101 determines that the value of the CZ game number counter is not “0” (in the case of NO determination in S519), the main CPU 101 ends the processing during CZ3 and starts the processing during CZ (FIG. 86) also ends.

  On the other hand, when the main CPU 101 determines in S519 that the value of the CZ game number counter is “0” (when S519 is YES), the main CPU 101 adds “1” to the number of ART sets, and ART The ART level lottery is performed with reference to the level determination table (see FIG. 46A), and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S521). Then, after the processing of S521, the main CPU 101 ends the processing during CZ3 and also ends the processing during start during CZ (see FIG. 86).

[Normal start processing during ART]
Next, with reference to FIG. 90, the normal ART start process performed in S411 in the state-based control process (see FIG. 81) will be described. Note that FIG. 90 is a flowchart showing a procedure of processing at the start during normal ART.

  First, the main CPU 101 adds “1” to the value of the ART continuing game number counter (S531). The ART continued game number counter is a counter that counts the number of games (the number of digested games) that the normal ART has continued. In the present embodiment, in addition to the ART continuing game number counter, an ART end game number counter that counts the number of games that the normal ART can continue is provided. Then, in the pachi-slot 1 of this embodiment, the value of the ART continuing game number counter is compared with the value of the ART ending game number counter, and when the value of the ART continuing game number counter reaches the value of the ART ending game number counter, The gaming state ends.

  Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 48), and performs CT lottery processing based on the current CT lottery state and the internal winning combination (subflag) (S532). Next, the main CPU 101 determines whether or not a CT lottery has been won (S533). In S533, when the main CPU 101 determines that the CT lottery has not been won (when S533 is NO), the main CPU 101 performs the process of S536 described later.

  On the other hand, when it is determined in S533 that the main CPU 101 has won the CT lottery (when S533 is YES), the main CPU 101 adds “1” to the number of CT sets and sets the value of the CT game number counter to “ 8 ”is set (S534). Next, the main CPU 101 sets the type of CT that won the gaming state of the next game (S535).

  After the processing of S535 or when S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 46B), lotteries the ART level based on the value of the ART continuing game number counter, and sets the lottery result. (S536). Next, the main CPU 101 refers to the normal ART medium / high probability lottery table (see FIG. 47), lottery the destination CT lottery state based on the current CT lottery state and the internal winning combination (subflag), and the lottery result. Is set (S537).

  Next, the main CPU 101 refers to the normal ART extra lottery table (see FIG. 49), and performs an extra lottery process for the number of ART games based on the internal winning combination (subflag) (S538). Next, the main CPU 101 determines whether or not the extra lottery is won (S539).

  When the main CPU 101 determines in S539 that the winning lottery has not been won (when S539 is NO), the main CPU 101 performs the process of S541 described later. On the other hand, when the main CPU 101 determines in S539 that the winning lottery has been won (when S539 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S540).

  After the processing of S540 or when S539 is NO, the main CPU 101 determines whether or not the value of the ART continuing game number counter has reached the value of the ART end game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continued game number counter has not reached the value of the ART end game number counter (when S541 is NO), the main CPU 101 performs normal start processing during ART. And the state-specific control process (see FIG. 81) also ends.

  On the other hand, when the main CPU 101 determines in S541 that the value of the ART continued game number counter has reached the value of the ART end game number counter (when S541 is YES), the main CPU 101 sets the ART set number to 1. Subtraction is performed (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 ends the start processing during normal ART, and also ends the state-specific control processing (see FIG. 81).

[Processing at start during CT]
Next, with reference to FIG. 91, the start process during CT performed in S413 in the control process by state (see FIG. 81) will be described. FIG. 91 is a flowchart showing the procedure of the start time process during CT.

  First, the main CPU 101 refers to the extra lottery table during CT (see FIG. 53), and performs extra lottery on the number of ART games based on the internal winning combination (sub flag) (S551). Next, the main CPU 101 determines whether or not the extra lottery is won (S552).

  When the main CPU 101 determines in S552 that the winning lottery has not been won (when S552 is NO), the main CPU 101 performs the process of S556 described later. On the other hand, when the main CPU 101 determines in S552 that the winning lottery has been won (when S552 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S553). As described above, in the pachislot machine 1 of this embodiment, as the number of wins for the sub-flag “triple chilli lip (triple chilli lip A or triple chilli lip B)” increases during the same CT, The amount of addition increases.

  After the processing of S553, the main CPU 101 determines whether or not the internal winning combination is a combination corresponding to the sub flag EX “triple combination” (or “determined combination”), that is, the internal winning combination “F_acceptance combination” or “F_1”. It is determined whether or not it is “CHILI CHIP” and the flag conversion lottery process of S444 in FIG. 84 has been won (S554).

  When the main CPU 101 determines in S554 that the internal winning combination is not a combination corresponding to the sub flag EX “triple chip” (when S554 is NO), the main CPU 101 ends the start processing during CT, The state-specific control process (see FIG. 81) is also terminated.

  On the other hand, when the main CPU 101 determines in S554 that the internal winning combination is a combination corresponding to the sub flag EX “triple chip” (when S554 is YES), the main CPU 101 sets the value of the CT game number counter to “1” is added (S555). Then, after the process of S555, the main CPU 101 ends the start-time process during CT and also ends the state-specific control process (see FIG. 81).

  Here, returning to the processing of S552 again, when S552 is NO, the main CPU 101 performs CT lottery processing during CT (S556). In this process, the main CPU 101 mainly performs lottery by adding the number of CT sets. Details of the CT lottery process during CT will be described later with reference to FIG. 92 described later.

  Next, the main CPU 101 subtracts 1 from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether or not the value of the CT game number counter is “0” (S558).

  In S558, when the main CPU 101 determines that the value of the CT game number counter is not “0” (when S558 is NO), the main CPU 101 ends the start-up process during CT and also controls each state ( 81) also ends. On the other hand, when the main CPU 101 determines in S558 that the value of the CT game number counter is “0” (when S558 is YES), the main CPU 101 determines whether or not the number of CT sets is “1” or more. Is discriminated (S559).

  In S559, when the main CPU 101 determines that the number of CT sets is “1” or more (when S559 is YES), the main CPU 101 subtracts 1 from the number of CT sets (S560). Next, the main CPU 101 sets “8” to the value of the CT game number counter (S561). After the process of S561, the main CPU 101 ends the start-time process during CT and also ends the control process for each state (see FIG. 81).

  On the other hand, when the main CPU 101 determines in S559 that the number of CT sets is not “1” or more (when S559 is NO), the main CPU 101 sets the normal ART in the gaming state of the next game (S562). After the process of S562, the main CPU 101 ends the start process during CT and also ends the control process for each state (see FIG. 81).

[CT lottery processing during CT]
Next, with reference to FIG. 92, the CT lottery process during CT performed in S556 during the start process during CT (see FIG. 91) will be described. FIG. 92 is a flowchart showing the CT lottery process during CT.

  First, the main CPU 101 sets a CT lottery table during CT (S571).

  Next, the main CPU 101 performs table data acquisition processing (S572). In this process, the main CPU 101 acquires the address of the lottery table to be referred to in the CT lottery process during CT. Details of the table data acquisition process will be described later with reference to FIG. 93 described later.

  Next, the main CPU 101 performs a 1-byte lottery process (S573). In this process, the main CPU 101 performs lottery addition on the CT set. Details of the 1-byte lottery process will be described later with reference to FIG. 94 described later.

  Next, the main CPU 101 determines whether or not a 1-byte lottery process has been won (S574). When the main CPU 101 determines in S574 that the 1-byte lottery process has not been won (when S574 is NO), the main CPU 101 ends the CT lottery process during CT, and the process is started during CT (FIG. 91).

  On the other hand, when it is determined in S574 that the main CPU 101 has won the 1-byte lottery process (when S574 is YES), the main CPU 101 adds “1” to the number of CT sets (S575). After the process of S575, the main CPU 101 ends the CT lottery process during CT, and moves the process to S557 of the start time process during CT (see FIG. 91).

[Table data acquisition processing]
Next, with reference to FIG. 93, the table data acquisition process performed in S572 during the CT lottery process during CT (see FIG. 92) will be described. FIG. 93 is a flowchart showing the procedure of the table data acquisition process.

  In this embodiment, when acquiring lottery values to be referred to in CT CT lottery processing during CT, lottery values are stored through two-stage address calculation processing (first and second stage table data acquisition processing). The current address is calculated. First, in the first-stage table data acquisition process (the processes of S582 and S583 described later), the “selection value (1 byte)” associated with the internal winning combination (actually the subflag D) is acquired. In addition, the selection value is provided for each type of internal winning combination, it is possible to determine whether the internal winning combination is a lottery target, and can specify the location of the lottery table associated with the internal winning combination Value (relative value) is specified. In the present embodiment, a selection value “0” is defined in advance for internal winning combinations (actually, subflag D) in which the lottery result of CT lottery processing during CT is non-winning, and those internal winning combinations are set to 1. Treated as “lost” at the stage of the table data acquisition process. In the second-stage table data acquisition process (the processes of S585 to S587 described later), the address storing the lottery value of the internal winning combination in which the selection value other than “0” is defined is calculated (the lottery table). The address obtained by adding the relative value (selection value) from the reference address (2 bytes) of the above is calculated.

  First, the main CPU 101 refers to a CT lottery selection table during CT (not shown), calculates the addresses of the CT lottery table during CT, the addresses of the first stage and second stage addition selection data, and CT The number of lotteries for lottery (in this embodiment, twice) is acquired (S581). Next, the main CPU 101 adds the address of the first stage addition selection data to the address of the CT lottery table during CT to calculate the first stage selection address (S582).

  Next, the main CPU 101 acquires the selection value stored in the calculated first stage selection address (S583). Next, the main CPU 101 determines whether or not the selection value is “0” (S584).

  In S584, when the main CPU 101 determines that the selection value is “0” (in the case where S584 is YES), the main CPU 101 ends the table data acquisition process, and the CT lottery process during CT (FIG. 92). (See step S573).

  On the other hand, when the main CPU 101 determines that the selection value is not “0” in S584 (when S584 is NO), the main CPU 101 adds the selection value to the selection address and sets the second-stage selection address. Calculate (S585). Next, the main CPU 101 adds the address of the second stage addition selection data to the second stage selection address to calculate the selection address (S586).

  Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates an address to be referred to in the CT lottery table during CT (S587). . After the process of S587, the main CPU 101 ends the table data acquisition process, and moves the process to S573 of the CT lottery process during CT (see FIG. 92).

[1-byte lottery processing]
Next, the 1-byte lottery process performed in S573 during the CT lottery process during CT (see FIG. 92) will be described with reference to FIG. FIG. 94 is a flowchart showing the procedure of 1-byte lottery processing.

  First, the main CPU 101 stores a 1-byte random number value (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110) for CT lottery in CT stored in a random number storage area (not shown) in the main RAM 103. Set (S591). Next, the main CPU 101 acquires lottery determination data from the CT lottery table during CT based on the address calculated in S587 during the table data acquisition process (S592). Further, in this process, the main CPU 101 sets the number of determination bits “8” as the initial value of the number of lotteries.

  Next, the main CPU 101 determines whether the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to bit data in a determination bit associated with the current number of lotteries, and determines that the bit data is “1” if the bit data is “1”. In this embodiment, bits 0 to 7 in the determination bits are associated with the number of lotteries “8” to “1”, respectively.

  In S593, when the main CPU 101 determines that the lottery determination data is not a lottery target (when S593 is NO), the main CPU 101 performs a process of S599 described later. On the other hand, in S593, when the main CPU 101 determines that the lottery determination data is a lottery target (when S593 is YES), the main CPU 101 acquires a lottery value from the CT CT lottery table during CT (S594).

  Next, the main CPU 101 determines whether or not the lottery value is “0” (winning determination data) (S595).

  In S595, when the main CPU 101 determines that the lottery value is “0” (when S595 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is performed during the CT lottery process during CT (FIG. 92). (See step S574). On the other hand, when the main CPU 101 determines that the lottery value is not “0” in S595 (when S595 is NO), the main CPU 101 performs a CT lottery (an addition lottery for the number of CT sets) (S596). Specifically, the main CPU 101 subtracts the lottery value from the random value (1-byte random value) and sets the subtraction result as the random value.

  Next, the main CPU 101 determines whether or not the CT lottery of S596 has been won (S597). In the CT lottery in S596, the main CPU 101 determines that the winning is made when the subtraction result in S596 is equal to or less than “0” (so-called “digit” occurs).

  When the main CPU 101 determines in S597 that the CT lottery has been won (in the case where S597 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is a CT lottery process during CT (see FIG. 92). Move to S574. On the other hand, when the main CPU 101 determines in S597 that the CT lottery has not been won (when S597 is NO), the main CPU 101 stores the lottery value storage address (lottery address) referred to in the CT lottery table during CT. Is updated to the next lottery address (S598).

  After the processing of S598 or when S593 is NO, the main CPU 101 subtracts 1 from the number of lotteries (S599). Next, the main CPU 101 determines whether or not the number of lotteries is “0” (S600).

  In S600, when the main CPU 101 determines that the number of lotteries is not “0” (when S600 is NO), the main CPU 101 returns the process to S593 and repeats the processes after S593. On the other hand, when the main CPU 101 determines in S600 that the number of lotteries is “0” (when S600 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is a CT lottery process during CT ( The process proceeds to S574 in FIG.

[Process during start during BB]
Next, with reference to FIG. 95, the BB start-time process performed in S415 in the state-specific control process (see FIG. 81) will be described. FIG. 95 is a flowchart showing the procedure of processing at the start during BB.

  First, the main CPU 101 refers to the bonus ART game number addition lottery table (see FIG. 57), and performs an ART game number addition lottery process based on the internal winning combination (S611). Next, the main CPU 101 determines whether or not the extra lottery is won (S612).

  When the main CPU 101 determines in S612 that the winning lottery has not been won (when S612 is NO), the main CPU 101 ends the start processing during BB and also performs control processing by state (see FIG. 81). finish. On the other hand, when it is determined in S612 that the main CPU 101 has won the extra lottery (when S612 is YES), the main CPU 101 adds the winning result (the number of added games) to the ART end game number counter (S613). .

  Next, the main CPU 101 determines whether or not the number of ART sets is “0” (S614). In S614, when the main CPU 101 determines that the number of ART sets is not “0” (when S614 is NO), the main CPU 101 ends the BB start-time processing and also controls by state (see FIG. 81). ) Also ends.

  On the other hand, when the main CPU 101 determines in S614 that the number of ART sets is “0” (when S614 is YES), the main CPU 101 adds “1” to the number of ART sets (S615). Then, after the processing of S615, the main CPU 101 ends the start-time processing during BB and also ends the state-specific control processing (see FIG. 81).

[Retrieve priority storage processing]
Next, with reference to FIG. 96, the drawing priority order storing process performed in S212 in the main flow (see FIG. 72) will be described. FIG. 96 is a flowchart showing the sequence of the pull-in priority storage process.

  First, the main CPU 101 sets “3” as the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, the pull-in priority table (see FIG. 25) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the search target reel is selected. Next, the main CPU 101 sets “20” as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs symbol code acquisition processing (S625). In this process, a symbol code is acquired with reference to a winning action flag storage region and a symbol code storage region corresponding to the number of symbol checks. Details of the symbol code acquisition process will be described later with reference to FIG. 97 described later.

  Next, the main CPU 101 performs a logical product operation process (S626). In this processing, the main CPU 101 performs winning operation flag data generation processing. Details of the logical product operation processing will be described later with reference to FIG.

  Next, the main CPU 101 performs a drawing priority order acquisition process (S627). In this process, the main CPU 101 sets the bit to “1” in the winning action flag (winning combination) storage area (see FIGS. 26 to 28), and sets the bit to “1” in the winning request flag storage area. With respect to the combination indicated by “”, the drawing priority order data is obtained with reference to the drawing priority order table (see FIG. 25). The details of the pull-in priority acquisition process will be described later with reference to FIGS. 99 and 100 described later.

  Next, the main CPU 101 stores the acquired pull-in priority data in a pull-in priority data storage area (not shown) in the main RAM 103 (S628). At this time, the pull-in priority data is stored in the pull-in priority data storage area so that each priority value corresponds to a bit in the storage area.

  The pull-in priority data storage area is provided with a priority data storage area for each main reel type. Each drawing priority data storage area stores drawing priority data determined according to the symbol positions “0” to “19” of the corresponding main reel. In the present embodiment, by referring to this pull-in priority data storage area, it is searched whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols determined based on the stop table.

  The contents of the priority pull-in data stored in the pull-in priority data storage area differ depending on the type of the pull-in priority table number in the pull-in priority table referenced when determining the pull-in priority data. The pull-in priority data indicates that the higher the value, the higher the priority. By referring to the drawing priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol for which the largest value is determined as the pull-in priority data becomes the symbol with the highest priority. Therefore, it can be said that the pull-in priority data indicates the rank between the symbols arranged on the peripheral surface of the main reel. When there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

  Next, the main CPU 101 performs an update process of the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is “0” (S631).

  In S631, when the main CPU 101 determines that the number of symbol checks is not “0” (when S631 is NO), the main CPU 101 returns the process to the process of S625, and repeats the processes after S625. On the other hand, when the main CPU 101 determines in S631 that the number of symbol checks is “0” (when S631 is YES), the main CPU 101 performs a search target reel changing process (S632).

  Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the above-described series of processing has been performed on all main reels (S634).

  In S634, when the main CPU 101 determines that the number of search reels is not “0” (when S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (in the case where S634 is YES), the main CPU 101 terminates the pull-in priority storage process, and the process proceeds to the main flow (FIG. 72).

[Design code acquisition processing]
Next, with reference to FIG. 97, the symbol code acquisition process performed in S625 during the pull-in priority storage process (see FIG. 96) will be described. FIG. 97 is a diagram showing an example of a flowchart showing the procedure of the symbol code acquisition process.

  First, the main CPU 101 performs clear processing of the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all the storage areas in the winning action flag storage area (see FIGS. 26 to 28) provided in the main RAM 103.

  Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S642).

  In S642, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when S642 is YES), the main CPU 101 executes the data decompression process described later with reference to FIG. The compressed data of the read first reel symbol arrangement table is decompressed (S643), and the first reel symbol arrangement table is set in the symbol arrangement table provided in the main RAM 103 (S644). On the other hand, when the main CPU 101 determines in S642 that the first reel (left reel 3L) is not stopped (when S642 is NO), the main CPU 101 determines that the main CPU 101 is the second reel (middle reel 3C). It is determined whether or not it is at a stop (S645).

  In S645, when the main CPU 101 determines that the second reel (medium reel 3C) is stopped (when S645 is YES), the main CPU 101 executes the data decompression process described later with reference to FIG. The compressed data of the read second reel symbol arrangement table is decompressed (S646), the second reel symbol arrangement table is set in the symbol arrangement table provided in the main RAM 103 (S647), and subsequently S650 (from symbol check to symbol correspondence) Proceed to the subsequent processing. On the other hand, when the main CPU 101 determines in S645 that it is not when the second reel (the middle reel 3C) is stopped (when S645 is NO), the main CPU 101 performs the main ROM 102 by data decompression processing to be described later with reference to FIG. The compressed data of the third reel symbol arrangement table read from (3) is decompressed (S648), and the third reel symbol arrangement table is set in the symbol arrangement table provided in the main RAM 103 (S649).

  After the process of S649, or when S642 or S645 is YES, the main CPU 101 performs a symbol check process when the stop operation is performed on the reel to be stopped, and corresponds to the symbol corresponding to the symbol acquired by the symbol check process. A winning action table is acquired (S650).

  Next, the main CPU 101 sets a winning operation flag storage area (S651). Next, the main CPU 81 performs the compressed data storage process described with reference to FIG. 80 (S652). In this process, the main CPU 101 mainly transfers (develops) the winable winning action flag data stored in the symbol corresponding winning action table to the corresponding storage area in the winning action flag storage area provided in the main RAM 103. ) Is performed.

  For example, when the first reel (left reel 3L) is stopped and the symbol positioned on the active line at the time of the stop operation is “white 7”, the symbol combinations (combinations) that can be won are shown in FIGS. 28, combination names “C_2nd_A_01”, “C_2nd_A_01” and “C_SP1_01” defined in the second storage area, combination names “C_9 sheets C_01” to “C_9 sheets C_03” defined in the third storage area, “C_9 sheets C_07” to “C_9 sheets C_09” and “C_9 sheets E_01”, combination names “C_RB role A_01”, “C_RB role A_02”, “C_RB role B_01” to “C_RB role B_04” defined in the fourth storage area ”,“ C_RB combination C_01 ”and“ C_RB combination C_02 ”, and the sixth storage area Combination names “C_reach eye lip C_01” to “C_reach eye lip C_03”, “C_reach eye lip D_01”, “C_reach eye lip D_02” and “C_reach eye lip D_01”, and the tenth storage area Is a combination name “C_BB1”.

  Note that the reel symbol arrangement table decompression process commonly executed in S643 (first reel symbol arrangement table decompression), S646 (second reel symbol arrangement table decompression), and S648 (third reel symbol arrangement table decompression). Will be described later with reference to FIGS. 114 to 116.

[AND operation]
Next, with reference to FIG. 98, for example, the AND operation process performed in S626 in the pull-in priority order storage process (see FIG. 96) will be described. FIG. 98 is a flowchart showing a procedure of logical product operation processing. The logical product calculation process shown in FIG. 98 is performed not only in S626 in the pull-in priority storage process (see FIG. 96), but also in S687 in the pull-in priority acquisition process (see FIGS. 99 and 100 described later). Is also executed.

  In the logical product operation process executed in S626 in the pull-in priority storage process (see FIG. 96), the two data subjected to the logical product operation are stored in the winning action flag set in S650 during the above-described symbol code acquisition process. Area data and symbol code storage area data. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “12” of the data length (12 bytes) set in S650 during the above-described symbol code acquisition process corresponds to “number of logical products” described later.

  On the other hand, in the AND operation executed in S687 in the pull-in priority acquisition process described later (see FIG. 99 and FIG. 100 described later), the two data subjected to the logical AND operation are the hit (withdrawal) request flag storage area. And data of a winning action flag storage area. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later.

  First, the main CPU 101 acquires logical product source data (for example, data in a symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation on the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and stores the calculation result as the logical product destination data (S662).

  Next, the main CPU 101 adds 1 to the address of the logical product data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

  Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is “0” (S666).

  In S666, when the main CPU 101 determines that the number of logical products is not “0” (when S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is “0” (in the case where S666 is YES), the main CPU 101 ends the logical product operation processing and stores the processing, for example, the drawing priority order storage. The process proceeds to S627 in the process (see FIG. 96).

[Withdrawal priority acquisition processing]
Next, with reference to FIGS. 99 and 100, a description will be given of the pull-in priority acquisition process performed in S627 in the pull-in priority storage process (see FIG. 96). 99 and 100 are flowcharts showing the procedure of the acquisition priority order acquisition process.

  First, the main CPU 101 determines whether or not the right reel 3R (specific display column) is being checked (S671).

  In S671, when the main CPU 101 determines that it is not at the time of checking the right reel 3R (when S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, when the main CPU 101 determines in S671 that the right reel 3R is being checked (when S671 is YES), the main CPU 101 determines “ANY combination” as the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (predetermined symbol combination) is included (S672). Here, the “ANY combination” refers to a combination in which a winning is determined regardless of at least the stop design of the right reel 3R (a winning combination in which at least the stop design of the right reel 3R is an arbitrary design).

  In S672, when the main CPU 101 determines that “ANY combination” is not included in the symbol combination related to the internal winning combination (when S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that “ANY combination” is included in the symbol combination related to the internal winning combination (when S672 is YES), the main CPU 101 determines “ANY combination” in the winning action flag storage area. The storage area corresponding to “comb” is masked (S673). Specifically, the main CPU 101 sets “1” to a bit corresponding to “ANY combination” in the winning action flag storage area.

  After the process of S673, or when S671 or S672 is NO, the main CPU 101 sets “1” to the address of the last storage area as the address of the winning action flag storage area (see FIGS. 26 to 28). The added address is set, stop prohibition data is set, and a winning action flag data length (data length of the winning action flag storage area: 12 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation has been detected. Further, the stop button operation state is acquired by referring to the operation stop button storage area (see FIG. 31).

  Next, the main CPU 101 subtracts 1 (-1 update) the address of the set winning operation flag storage area (S676). Next, the main CPU 101 generates winning request flag data from the set winning operation flag storage area and the corresponding winning request flag storage area (see FIGS. 26 to 28), and the generated winning request flag data. The prohibited winning action position is generated based on (S677).

  Next, the main CPU 101 determines whether or not the stop operation position is a prohibited winning action position (S678).

  In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning action position (when S678 is NO), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (when S678 is YES), the main CPU 101 has the value of the stop button operation counter being the value of the third stop. Whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when S679 is YES), the main CPU 101 performs a process of S705 described later. On the other hand, when the main CPU 101 determines in S679 that the value of the stop button operation counter is not the value of the third stop (when S679 is NO), the main CPU 101 determines that the value of the stop button operation counter is the second stop. Whether it is a value or not is discriminated (S680).

  In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the second stop value (when S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, when the main CPU 101 determines in S680 that the value of the stop button operation counter is the second stop value (when S680 is YES), the main CPU 101 determines whether or not the right reel 3R has stopped. Is determined (S681).

  When the main CPU 101 determines in S681 that the right reel 3R has been stopped (when S681 is YES), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S681 that the right reel 3R has not been stopped (NO in S681), the main CPU 101 determines that the hit request flag may be subject to interference “ANY role”. Or not (whether or not “ANY combination” is included in the symbol combination (winning combination) related to the internal winning combination) (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may receive the “ANY role” interference (YES in S682), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be subject to interference of “ANY role” (when S682 is NO), the main CPU 101 determines that the current check is “ANY”. It is determined whether or not it is time to check the hit request flag including “combination” (S683).

  In S683, when the main CPU 101 determines that the current check is a check of the hit request flag including “ANY role” (when S683 is YES), the main CPU 101 performs a process of S705 described later.

  On the other hand, when the main CPU 101 determines in S683 that the current check is not at the time of checking the hit request flag including “ANY role” (when S683 is NO), S678 or S680 is NO, or S681. Alternatively, when S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning action flag data length is “0” (S685).

  In S685, when the main CPU 101 determines that the winning action flag data length is not “0” (when S685 is NO), the main CPU 101 returns the process to the process of S676 and repeats the processes after S676.

  On the other hand, when the main CPU 101 determines in S685 that the winning action flag data length is “0” (when S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). . In the logical product calculation process executed in the process of S686, as described above, the data in the winning (withdrawal) request flag storage area is set to “logical product destination data”, and the data in the winning action flag storage area is In the “logical product source data”, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag is set in the “logical product number”. The RT action combination display flag is a storage area in which a symbol combination related to RT transition is defined in the winning action flag storage area. In the present embodiment, only the storage area 11 as shown in FIGS. Become.

  Next, the main CPU 101 refers to the pull-in priority table address storage area and acquires the pull-in priority table (S687).

  Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is an end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data in the pull-in priority order table stored at the currently set address is an end code (when S688 is YES), the main CPU 101 determines that S705 to be described later. Perform the process. On the other hand, when the main CPU 101 determines in S688 that the data in the drawing priority table stored at the currently set address is not an end code (when S688 is NO), the main CPU 101 A flag storage area is set (S689).

  Next, the main CPU 101 acquires pull-in priority data from the pull-in priority table based on the currently set address (S690). Next, the main CPU 101 sets a block counter in the pull-in priority table (S691). In this embodiment, in this process, the main CPU 101 sets “2” to the value of the block counter in the pull-in priority table.

  Next, the main CPU 101 sets the number of checks in the pull-in priority table, and adds 1 (+1 update) to the address of the pull-in priority table to be referred to (S692). In this embodiment, in this process, the main CPU 101 sets “8” (the number of bits of check data defined in the pull-in priority table) to the number of checks in the pull-in priority table.

  Next, the main CPU 101 acquires check data based on the updated address of the drawing priority table, and extracts a check bit from the check data (S693).

  Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

  In S694, when the main CPU 101 determines that the value of the extracted check bit is not “1” (when S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is “1” (when S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced. (+1 update), and based on the updated address, determination data is acquired from the pull-in priority table (S695).

  Next, the main CPU 101 determines based on the determination data acquired in S695 whether or not the currently acquired winning action flag data is a determination target (S696). In this process, the main CPU 101 compares the currently acquired winning action flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently acquired winning action flag data is a determination target.

  In S696, when the main CPU 101 determines that the winning action flag data is not a determination target (when S696 is NO), the main CPU 101 performs a process of S699 described later. On the other hand, when the main CPU 101 determines in S696 that the winning operation flag data is the determination target (when S696 is YES), the main CPU 101 performs the update processing of the drawing priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set pull-in priority data with the pull-in priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 performs check data update processing (S698). In this process, the main CPU 101 shifts the check data rightward by 1 bit (in the direction from bit 7 to bit 0). In this process, “0” is set in bit 7 of the check data after the shift.

  After the processing of S698, or when S694 or S696 is NO, the main CPU 101 determines whether or not there is a bit to be checked (bit in which “1” is set) in the check data (S699).

  In S699, when the main CPU 101 determines that there is no check target bit in the check data (when S699 is NO), the main CPU 101 performs a process of S702 described later. On the other hand, when the main CPU 101 determines in S699 that there is a bit to be checked in the check data (when S699 is YES), the main CPU 101 adds 1 to the address of the winning action flag storage area to be checked (+1 update) And 1 is subtracted from the number of checks (S700).

  Next, the main CPU 101 determines whether or not the number of checks is “0” (S701). In S701, when the main CPU 101 determines that the number of checks is not “0” (when S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

  On the other hand, when the main CPU 101 determines in S701 that the number of checks is “0” (in the case where S701 is YES), the main CPU 101 sets the number of checks in the address of the winning action flag storage area that is currently referenced. The initial value “8” is added to update the address of the winning action flag storage area, and the value of the block counter is decremented by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is “0” (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (when S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

  On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is “0” (when S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced (+1 update). (S704). For example, when the pull-in priority table currently referred to is the pull-in priority table specified in the first block, the pull-in priority table referred to in the next block is determined by this process. Change to table. After the process of S704, the main CPU 101 returns the process to the process of S688, and repeats the processes after S688.

  Here, returning to the processing of S679, S683, or S688 again, if S679, S683, or S688 is YES, the main CPU 101 uses the pulling order data set at this time as the final pulling priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets “0 (00H)” as final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data “0 (00H)”, no pull-in data (stop prohibition) is set. After the process of S705, the main CPU 101 ends the pull-in priority order acquisition process, and moves the process to S628 in the pull-in priority order storing process (see FIG. 96).

[Reel stop control process]
Next, with reference to FIG. 101, the reel stop control process performed in S213 in the main flow (see FIG. 72) will be described. FIG. 101 is a flowchart showing a procedure of reel stop control processing.

  First, the main CPU 101 performs a reel stop possible signal OFF process (S711). In this process, the main CPU 101 mainly performs a port output process of the reel stop possible signal OFF data. Further, this process is performed using an unspecified work area in the main RAM 103.

  Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not it has become “constant speed”) (S712). In S712, when the main CPU 101 determines that the rotation speeds of all the reels are not “constant speed” (when S712 is NO), the main CPU 101 repeats the process of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotation speeds of all the reels have become “constant speed” (when S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal ON data. Further, this process is performed using an unspecified work area in the main RAM 103.

  Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

  When the main CPU 101 determines in S714 that a valid stop button has not been pressed (in the case where S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, when the main CPU 101 determines in S714 that a valid stop button has been pressed (in the case where S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 31), and the stop button has not been pressed. The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines a search target reel from the operation stop button (S716). Further, in this process, an address (start address) setting process of the spinning cylinder control data storage area in which the reel control management information of the search target reel is stored is also performed.

  Next, the main CPU 101 performs a reel stop possible signal OFF process (S717). This process is performed using an unspecified work area of the main RAM 103, as in S711. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 performs reel stop selection processing (S719). Although a detailed description is omitted, in this process, the main CPU 101 performs the number of sliding pieces selection process.

  Next, the main CPU 101 determines a planned stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined planned stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding frames to the stop start position, and sets the addition result as the planned stop position.

  Next, the main CPU 101 executes symbol code storage processing (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button non-operating counter. When it is “0”, it is determined that the reel to be controlled is the final stop reel.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stop reel (when S722 is NO), the main CPU 101 performs a control change process (S723). In this process, the stop information group used for stopping the reel is updated when the stop position is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 124 (S724).

  Next, the main CPU 101 performs standby interval remaining time standby processing (S725). In this process, the main CPU 101 performs a standby process until a predetermined reel stop interval time has elapsed. After the process of S725, the main CPU 101 returns the process to the process of S711, and repeats the processes after S711.

  Here, the process returns to S722 again, and when the main CPU 101 determines in S722 that the reel to be controlled is the final stop reel (when S722 is YES), the main CPU 101 energizes all reels. It is determined whether or not is in a stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all the reels is not stopped (when S726 is NO), the main CPU 101 repeats the process of S726.

  On the other hand, when the main CPU 101 determines in S726 that the excitation of all the reels is in a stopped state (when S726 is YES), the main CPU 101 remains in the on state in which the stop button operated for the third stop is on. It is determined whether or not (the stop button has not been released) (S727). In S727, when the main CPU 101 determines that the stop button subjected to the third stop operation remains on (when S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, when the main CPU 101 determines in S727 that the stop button for which the third stop operation has been performed is not in the on state (when S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. The process proceeds to S214 in the main flow (see FIG. 72).

[Winning Search Process]
Next, with reference to FIG. 102, the winning search process performed in S214 in the main flow (see FIG. 72) will be described. FIG. 102 is a flowchart showing the winning search processing procedure.

  First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 33) to the corresponding storage area in the winning action flag storage area (see FIGS. 26 to 28). (S761). At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets the address of the payout number data table in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables (“5” in this embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

  Next, based on the address set in the HL register, the main CPU 101 sets data on the number of medals to be paid out (in this embodiment, one, two, three, or nine) in the C register. The determination target data is set in the A register, and “2” is added (+2 update) to the address set in the HL register (S764).

  Next, the main CPU 101 extracts the value of the determination bit from the medal payout number data set in the C register (S765). Next, the main CPU 101 determines whether the block is a determination target block based on the extracted determination bit value (S766).

  In S766, when the main CPU 101 determines that the block is not a determination target block (when S766 is NO), the main CPU 101 performs a process of S768 described later. On the other hand, when the main CPU 101 determines in S766 that the block is a determination target block (when S766 is YES), the main CPU 101 subtracts 1 from the address of the winning action flag storage area set in the DE register (- 1 update) (S767).

  After the process of S767 or when S766 is NO, the main CPU 101 extracts the data in the storage area specified by the address of the winning action flag storage area set in the DE register as the determination data (S768).

  Next, the main CPU 101 determines whether or not the determination result is a win based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a win.

  In S769, when the main CPU 101 determines that the result of the determination is not a win (when S769 is NO), the main CPU 101 performs a process of S776 described later. On the other hand, when the main CPU 101 determines in S769 that the result of the determination is a win (when S769 is YES), the main CPU 101 determines that the current game is three games (the number of medals bet is three). ) Is determined (S770).

  In S770, when the main CPU 101 determines that the current game is a three-game game (when S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, when the main CPU 101 determines in S770 that the current game is not a three-game (when S770 is NO), the main CPU 101 pays out a two-game (a game in which the number of medals bet is two). The number of sheets (2 sheets) is set in the C register (S771).

  After the processing of S771 or when S770 is YES, the main CPU 101 performs payout number update processing (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current value of the winning number counter, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether or not the value of the payout number is less than the maximum payout number “10” (S773).

  In S773, when the main CPU 101 determines that the value of the payout number is less than the maximum payout number “10” (when S773 is YES), the main CPU 101 performs a process of S775 described later. On the other hand, when the main CPU 101 determines in S773 that the value of the payout number is not less than the maximum payout number “10” (when S773 is NO), the main CPU 101 sets the maximum payout number “10” as the payout number. (S774).

  After the processing of S774 or if S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

  After the processing of S775 or when S769 is NO, the main CPU 101 determines whether or not there is another winning (S776). When the main CPU 101 determines that there is another winning in S776 (when S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

  On the other hand, when the main CPU 101 determines in S776 that there are no other winnings (when S776 is NO), the main CPU 101 subtracts 1 from the winning search counter (-1 update) (S777). Note that when there is one active line as in the present embodiment, a plurality of small roles will not be won in duplicate, so the determination process in S776 is always NO.

  Next, the main CPU 101 determines whether or not the value of the winning search counter is “0” (S778).

  In S778, when the main CPU 101 determines that the value of the winning search counter is not “0” (when S778 is NO), the main CPU 101 returns the process to the process of S764 and repeats the processes after S764. On the other hand, when the main CPU 101 determines in S778 that the value of the winning search counter is “0” (in the case where S778 is YES), the main CPU 101 ends the winning search process, and the process proceeds to the main flow (FIG. 72), the process proceeds to S215.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 72) will be described with reference to FIG. FIG. 103 is a flowchart showing the procedure of the illegal hit check process. The illegal hit is a lottery in an internal lottery process (see FIG. 78), and a BB winning number and a small bonus winning number (internal winning combination) stored in the winning number storage area in the symbol setting process (see FIG. 79). This is a term indicating that the left reel 3L, the middle reel 3C, and the right reel 3R are stopped on a valid line with a combination of symbols that cannot be established (design combination is not established).

  First, the main CPU 101 sets the address of the winning action flag storage area (see FIGS. 26 to 28) (S781). Next, the main CPU 101 sets the size (number of bytes, “12” in the present embodiment) of the winning action flag storage area to the value of the check counter (S782).

  Next, the main CPU 101, based on the address of the currently set winning action flag storage area, stores the internal winning combination stored in the storage area in the winning request flag storage area (internal winning combination storage area) corresponding to the address. (Hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored at the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

  In this synthesis process, first, the main CPU 101 obtains an exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data). Next, the main CPU 101 obtains the logical product of the obtained exclusive OR calculation result and the winning combination data (winning operation flag data), and uses the logical product calculation result as the combined result. If an illegal hit error has not occurred, the value of the synthesis result is “0”.

  Next, the main CPU 101 determines whether an illegal hit error has occurred based on the result of the synthesis process in S784 (S785).

  In S785, when the main CPU 101 determines that an illegal hit error has not occurred (when S785 is NO), the main CPU 101 updates the address of the winning action flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is “0” (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (when S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is “0” (when S788 is YES), the main CPU 101 ends the illegal hit check process, and the process proceeds to the main flow (FIG. 72), the process proceeds to S216.

  Here, returning to the processing of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (when S785 is YES), the main CPU 101 determines that the error processing described with reference to FIG. (S789). By this process, the two characters “EE” indicating the occurrence of the illegal hit error are displayed as error information on the 2-digit 7-segment LED (used for displaying the number of payouts and for error display) included in the information display 6. Error display data is output. The occurrence state (error state) of the illegal hit error is canceled by pressing the reset switch 76 (see FIG. 5).

  Next, the main CPU 101 clears the value of the winning number counter and the data in the winning request flag storage area (S790). After the process of S790, the main CPU 101 ends the illegal hit check process, and moves the process to the process of S216 in the main flow (see FIG. 72).

  In the present embodiment, as shown in FIGS. 26 to 28, the configuration of the winning action flag storage area (display combination storage area) is the same as that of the winning request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning action flag storage area arranged in the main RAM 103 during the combination processing of the combination of the winning action flag storage area and the internal winning combination can be configured identically.

[Winning check / medal payout processing]
Next, with reference to FIG. 104, the winning check / medal payout process performed in S216 in the main flow (see FIG. 72) will be described. FIG. 104 is a flowchart showing the procedure of the winning check / medal payout process.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning action command transmitted to the sub control circuit 200. The winning action command includes a parameter for specifying a winning action flag (display combination) and the like.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 66 (S802). Note that the winning operation command is transmitted from the main control circuit 90 to the sub-control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is “0” (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (in the case of YES determination in S803), the main CPU 101 ends the winning check / medal payout process, and the process proceeds to the main flow ( The process proceeds to S217 in FIG.

  On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not “0” (NO in S803), the main CPU 101 determines that the number of credits (stored number) of medals is the upper limit number (the number of books). It is determined whether or not the number is 50 or more in the embodiment (S804).

  In S804, when the main CPU 101 determines that the number of credits of the medal is not equal to or greater than the upper limit (when S804 is NO), the main CPU 101 adds “1” to the value of the credit counter (+1 update) ( S805). The added credit counter value is displayed by a two-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). The details of the medal payout number check process will be described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the medals have been paid out (S807). When the main CPU 101 determines in S807 that the payout of medals has ended (when S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 72). The process proceeds to S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not ended (when S807 is NO), the main CPU 101 performs payout interval waiting processing (S808). In this process, the main CPU 101 waits until a preset medal payout interval time (in this embodiment, 60.33 msec: 54 cycles of an interrupt process (1.1172 msec cycle) described in FIG. 110 described later). Wait. After the process of S808, the main CPU 101 returns the process to the process of S803 and repeats the processes after S803.

  Here, returning to the processing of S804 again, when the main CPU 101 determines in S804 that the number of credits of medals is equal to or greater than the upper limit number (50) (when S804 is YES), the main CPU 101 A medal payout process is performed (S809). Through this process, one medal is paid out. Then, after the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and shifts the processing to S217 in the main flow (see FIG. 72).

[Medal payout number check process]
Next, with reference to FIG. 105, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 104) will be described. FIG. 105 is a flowchart showing the procedure of the medal payout number check process.

  First, the main CPU 101 adds “1” to the value of the medal OUT counter (+1 update) (S811). The medal OUT counter is a counter for counting the number of medals paid out. Next, the main CPU 101 adds “1” to the value of the payout number counter (+1 update) (S812). The payout number counter is a counter for counting the number of medals to be paid out.

  Next, the main CPU 101 performs a payout number 7 SEG display process (S813). In this process, the main CPU 101 performs a control process for displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

  Next, the main CPU 101 performs update processing of the combination end number counter (S814). The consecutive end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the consecutive end number counter with its lower limit “0”, and when the value of the end of consecutive number counter is greater than the lower limit “0”, The counter value is decremented by 1 (-1 is updated), and when the value of the combination end number counter is equal to or lower than the lower limit “0”, the value of the combination end number counter is held at “0”.

  Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

  Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub control circuit 200. The credit information command includes a parameter for specifying the number of medals for credit.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 66 (S817). By this processing, the credit information command data is stored in the communication data storage area provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in interrupt processing described with reference to FIG. After the process of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 in the winning check / medal payout process (see FIG. 104).

[BB check processing]
Next, the BB check process performed in S217 in the main flow (see FIG. 72) will be described with reference to FIG. FIG. 106 is a flowchart showing the procedure of the BB check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). In S821, when the main CPU 101 determines that the current gaming state is not a bonus state (when S821 is NO), the main CPU 101 performs a process of S832 described later.

  On the other hand, when the main CPU 101 determines in S821 that the current gaming state is the bonus state (when S821 is YES), the main CPU 101 counts the number of medals that can be paid out during the bonus state. The number of medals paid out in the winning check / medal payout process is subtracted from the value of the BB payout number counter (S822).

  Next, the main CPU 101 determines whether or not the value of the BB payout number counter is less than “0” (S823). In S823, when the main CPU 101 determines that the value of the BB payout number counter is not less than “0” (when S823 is NO), the main CPU 101 ends the BB check process, and the process proceeds to the main flow (FIG. 72), the process proceeds to S218.

  On the other hand, when the main CPU 101 determines in S823 that the value of the BB payout number counter is less than “0” (when S823 is YES), the main CPU 101 performs a bonus end process (S824). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the on state.

  Next, the main CPU 101 refers to the bonus end CT lottery table (see FIG. 58) to perform CT lottery at the end of the bonus (S825). Next, the main CP 91 determines whether or not the CT lottery at the end of the bonus is won (S826).

  In S826, when the main CPU 101 determines that the CT lottery has not been won (when S826 is NO), the main CPU 101 performs a process of S828 described later. On the other hand, when it is determined in S826 that the main CPU 101 has won the CT lottery (when S826 is YES), the main CPU 101 adds “1” to the number of CT sets (S827). If the CT lottery is won when the number of ART sets is “0”, “1” is added to the number of CT sets and “1” is also added to the number of ART sets in the process of S827. .

  After the processing of S827 or when S826 is NO, the main CPU 101 determines whether the number of ART sets or the number of CT sets is “1” or more (S828).

  In S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is “1” or more (when S828 is YES), the main CPU 101 sets the ART ready state to the game state of the next game. (S829). Then, after the process of S829, the main CPU 101 ends the BB check process, and moves the process to the process of S218 in the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S828 that the number of ART sets or the number of CT sets is not “1” or more (when S828 is NO), the main CPU 101 sets the normal gaming state to the gaming state of the next game. (S830). Next, the main CPU 101 refers to the normal middle / high probability lottery table (see FIG. 38B), lottery the CZ lottery state, and sets the lottery result (S831). Then, after the process of S831, the main CPU 101 ends the BB check process, and shifts the process to the process of S218 in the main flow (see FIG. 72).

  Here, returning to the processing of S821 again, if S821 is NO, the main CPU 101 determines whether or not the symbol combination related to the BB combination (the combination of symbols “C_BB1” or “C_BB2”) is displayed. (S832). When the main CPU 101 determines in S832 that the symbol combination related to the BB combination has not been displayed (in the case where S832 is NO), the main CPU 101 ends the BB check process, and the process proceeds to the main flow (see FIG. 72). The process proceeds to S218.

  On the other hand, when the main CPU 101 determines in S832 that the symbol combination related to the BB combination is displayed (YES in S832), the main CPU 101 refers to the bonus type lottery table (see FIG. 56) and bonus The type is lottery and the lottery result is set (S833). Next, the main CPU 101 sets a predetermined value (the number of payouts that triggers the end of the bonus: “216” in this embodiment) as the value of the payout amount counter during BB (S834).

  Next, the main CPU 101 performs bonus start processing (S835). In this process, the main CPU 101 performs various processes necessary for starting the bonus operation, such as setting a bonus state in the game state of the next game. After the process of S835, the main CPU 101 ends the BB check process, and moves the process to the process of S218 in the main flow (see FIG. 72).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 72) will be described with reference to FIGS. 107 and 108. FIG. 107 and 108 are flowcharts showing the procedure of the RT check process.

  First, the main CPU 101 determines whether or not the RT state is the RT5 state (S841). In S841, when the main CPU 101 determines that the RT state is the RT5 state (when S841 is YES), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 72). Move on to processing.

  On the other hand, when the main CPU 101 determines that the RT state is not the RT5 state in S841 (when S841 is NO), the main CPU 101 determines whether or not the RT state is the RT0 state (S842). In S842, when the main CPU 101 determines that the RT state is not the RT0 state (when S842 is NO), the main CPU 101 performs a process of S845 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT0 state in S842 (when S842 is YES), the main CPU 101 displays the symbol combination of the abbreviation “bell spill” (see FIG. 26). It is determined whether or not (S843). In S843, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spilled eyes” has not been displayed (when S843 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (FIG. 72), the process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S843 that the symbol combination of the abbreviation “bell spilled eyes” is displayed (when S843 is YES), the main CPU 101 sets the RT2 state flag to the on state (S844). . By this process, the RT state shifts from the RT0 state to the RT2 state. After the process of S844, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 72).

  Here, returning to the process of S842 again, if S842 is NO, the main CPU 101 determines whether or not the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (when S845 is NO), the main CPU 101 performs the process of S850 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT1 state in S845 (when S845 is YES), the main CPU 101 determines whether or not the symbol combination of the abbreviation “bell spill” is displayed. (S846).

  In S846, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spilled eyes” is displayed (when S846 is YES), the main CPU 101 sets the RT1 status flag to the OFF state and the RT2 status flag. Is set to the ON state (S847). With this process, the RT state shifts from the RT1 state to the RT2 state. Then, after the process of S847, the main CPU 101 ends the RT check process and shifts the process to the process of S219 in the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S846 that the symbol combination of the abbreviation “bell spilled eyes” has not been displayed (when S846 is NO), the main CPU 101 determines whether or not 20 games have elapsed in the RT1 state. Is determined (S848).

  In S848, when the main CPU 101 determines that 20 games have not elapsed in the RT1 state (when S848 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (see FIG. 72). ) To S219. On the other hand, in S848, when the main CPU 101 determines that 20 games have elapsed in the RT1 state (when S848 is YES), the main CPU 101 sets the RT1 state flag to the off state (S849). With this process, the RT state shifts from the RT1 state to the RT0 state. After the process of S849, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 72).

  Here, returning to the process of S845 again, when S845 is NO, the main CPU 101 determines whether or not the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (when S850 is NO), the main CPU 101 performs a process of S853 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT2 state in S850 (when S850 is YES), the main CPU 101 displays the symbol combination of the abbreviation “RT3 transition lip” (see FIG. 26). It is determined whether or not (S851). In S851, when the main CPU 101 determines that the symbol combination of the abbreviation “RT3 transition lip” has not been displayed (when S851 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (FIG. 72), the process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S851 that the symbol combination of the abbreviation “RT3 transition lip” has been displayed (when S851 is YES), the main CPU 101 sets the RT2 state flag to the OFF state and RT3. A state flag is set to an on state (S852). With this process, the RT state shifts from the RT2 state to the RT3 state. After the process of S852, the main CPU 101 ends the RT check process and moves the process to the process of S219 in the main flow (see FIG. 72).

  Here, returning to the processing of S850 again, if S850 is NO, the main CPU 101 determines whether or not the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (when S853 is NO), the main CPU 101 performs a process of S862 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT3 state in S853 (when S853 is YES), the main CPU 101 displays the symbol combination of the abbreviation “bell spill” or “RT2 transition lip”. It is determined whether or not it has been done (S854).

  In S854, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spill” or “RT2 transition lip” is displayed (when S854 is YES), the main CPU 101 sets the RT3 state flag to the off state. At the same time, the RT2 state flag is set to the on state (S855). With this process, the RT state shifts from the RT3 state to the RT2 state. After the process of S855, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S854 that the symbol combination of the abbreviation “bell spilled eyes” or “RT2 transition lip” is not displayed (when S854 is NO), the main CPU 101 transitions to the abbreviation “RT4 transition”. It is determined whether or not the “Rip” symbol combination (see FIG. 26) is displayed (S856).

  In S856, when the main CPU 101 determines that the symbol combination of the abbreviation “RT4 transition lip” is not displayed (when S856 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow ( The process proceeds to S219 in FIG. On the other hand, when the main CPU 101 determines in S856 that the symbol combination of the abbreviation “RT4 transition lip” has been displayed (when S856 is YES), the main CPU 101 sets the RT3 state flag to the OFF state and RT4. The state flag is set to the on state (S857). With this process, the RT state shifts from the RT3 state to the RT4 state.

  After the processing of S857, the main CPU 101 determines whether or not the gaming state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the gaming state is not the ART ready state (when S858 is NO), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 72). Move on to processing.

  On the other hand, when the main CPU 101 determines in S858 that the gaming state is the ART preparation state (when S858 is YES), the main CPU 101 determines whether or not the number of CT sets is “1” or more. (S859).

  In S859, when the main CPU 101 determines that the number of CT sets is “1” or more (when S859 is YES), the main CPU 101 sets CT to the game state of the next game and sets the CT game number counter. “8” is set (S860). Then, after the process of S860, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S859 that the CT set number is not “1” or more (when S859 is NO), the main CPU 101 sets the normal ART to the game state of the next game, and the ART end game. A predetermined value is set in the number counter (S861). Then, after the process of S861, the main CPU 101 ends the RT check process and shifts the process to the process of S219 in the main flow (see FIG. 72).

  Here, returning to the processing of S853 again, if S853 is NO, the main CPU 101 determines whether or not a symbol combination of abbreviation “bell spilled eyes” or “RT2 transition lip” is displayed (S862). In S862, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spill” or “RT2 transition lip” is not displayed (when S862 is NO), the main CPU 101 ends the RT check process. Then, the process proceeds to S219 in the main flow (see FIG. 72).

  On the other hand, in S862, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spill” or “RT2 transition lip” is displayed (when S862 is YES), the main CPU 101 sets the RT4 status flag to the off state. And the RT2 state flag is set to the on state (S863). With this process, the RT state shifts from the RT4 state to the RT2 state. After the process of S863, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 72).

[CZ / ART end processing]
Next, with reference to FIG. 109, the CZ / ART end process performed in S219 in the main flow (see FIG. 72) will be described. FIG. 109 is a flowchart showing a procedure of CZ / ART termination processing.

  First, the main CPU 101 determines whether or not the current gaming state is any of CZ failure and ART termination (S871). In S871, when the main CPU 101 determines that the current gaming state is not CZ failure or ART end (when S871 is NO), the main CPU 101 ends the CZ / ART end processing, The process proceeds to S201 in the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S871 that the current gaming state is either CZ failure or ART end (when S871 is YES), the main CPU 101 determines the CZ lottery table (see FIG. 39B). ), CZ pull-back lottery is performed (S872). Next, the main CPU 101 determines whether or not a CZ pullback lottery has been won (S873).

  In S873, when the main CPU 101 determines that the CZ pullback lottery has been won (when S873 is YES), the main CPU 101 sets the type of CZ that has won the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type of CZ in the CZ game number counter (S875). Then, after the processing of S875, the main CPU 101 ends the CZ / ART termination processing, and moves the processing to S201 in the main flow (see FIG. 72).

  On the other hand, when the main CPU 101 determines in S873 that the CZ pull-back lottery has not been won (when S873 is NO), the main CPU 101 sets the normal gaming state to the gaming state of the next game (S876). Next, the main CPU 101 refers to the normal middle / high probability lottery table (see FIG. 38B), lottery the CZ lottery state, and sets the lottery result (S877). Then, after the processing of S877, the main CPU 101 ends the CZ / ART termination processing, and shifts the processing to S201 in the main flow (see FIG. 72).

[Interrupt processing under the control of the main CPU (1.1172 msec)]
Next, an interrupt process performed by the main CPU 101 at a cycle of 1.1172 msec will be described with reference to FIG. FIG. 110 is a flowchart showing the procedure of interrupt processing. 1. Interrupt processing repeatedly executed at a cycle of 1172 msec occurs based on the output timing of the time-out signal of the timer circuit 113 set in the initialization processing of the timer circuit 113 (PTC) (see S2 in FIG. 62). This is a process executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs a register saving process (S901). Next, the main CPU 101 performs input port check processing (S902). In this process, signals input from various switches such as a stop switch are checked.

  Next, the main CPU 101 performs a reel rotation speed control process (details will be described later) (S903-S909). In this process, the main CPU 101 obtains the difference between the symbol position of the virtual reel that simulates the ideal reel movement and the symbol position of the actual reels 3L, 3C, 3R, and the reels 3L, 3C, 3R according to the difference. Adjust the rotation speed. Hereinafter, each step of the reel rotation speed control process including steps S903 to S909 will be briefly described.

  In the reel rotation speed control process, the main CPU 101 first executes a virtual reel control process (S903). In the virtual reel control process, the virtual symbol position is calculated by simulating the virtual reel with software. Details of the virtual reel control process (FIG. 120) will be described later. The virtual reel control process constitutes “symbol position calculation means”.

  Next, the main CPU 101 stores the 2-byte address of the first reel excitation timer storage area in the HL register (a pair register including the H register and the L register) (S904). This process is a process for making it possible to acquire the value of the reel excitation timer in the next step, the reel control process (S905).

  Next, the main CPU 101 executes a reel control process for the first reel (reel 3L) (S905). In the reel control process, it is determined whether or not it is the excitation update timing based on the value of the reel excitation timer. If it is determined that it is the excitation update timing, the value of the reel control management information at that time is set. Various processing (“Acceleration preparation 1 process”, “Acceleration preparation 2 process”, “Acceleration / stop process”, “Constant speed wait, constant speed process”, “Stop start position wait process”, “All phases Any process of “OFF process”) is executed. Details of the reel control process will be described later. The reel control process constitutes “symbol position difference calculating means” and “rotational speed adjusting means”.

  Next, the main CPU 101 sets the address of the second reel excitation timer storage area (S906), and executes a reel control process for the second reel (reel 3C) (S907). In the processing of S906 and S907, the same processing as the processing of S904 and S905 is performed on the second reel.

  Next, the main CPU 101 sets the address of the third reel excitation timer storage area (S908), and executes a reel control process for the third reel (reel 3R) (S909). In the processing of S908 and S909, the same processing as that of S904 and S905 is performed on the third reel.

  Next, the main CPU 101 performs communication data transmission processing (S910). In this processing, various commands stored in the communication data storage area are mainly transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 7) of the main control circuit 90. After transmitting a command to the sub control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. If a plurality of command data is stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the oldest stored order. When no command data is stored in the communication data storage area, that is, when the value of the communication data pointer is “0”, a no-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs inserted medal passage check processing (S911). In this process, the main CPU 101 checks whether or not the inserted medal has passed through the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs a WDT restart process (S912).

  Next, the main CPU 101 performs a 7-segment LED drive process (S913). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6 and displays, for example, the number of medals paid out, the number of credits, stop button pressing order data, and the like. Details of the 7-segment LED driving process will be described later with reference to FIG. 111 described later.

  Next, the main CPU 101 performs timer update processing (S914). In this processing, the main CPU 101 performs count (subtraction) processing for various timers that have been set. Details of the timer update process will be described later with reference to FIG. 113 described later.

  Next, the main CPU 101 performs error detection processing (S915). Next, the main CPU 101 performs a register restoration process (S916). Then, after the process of S912, the main CPU 101 ends the interrupt process.

[7-segment LED drive processing]
Next, the 7-segment LED driving process performed in S907 during the interrupt process (see FIG. 110) will be described with reference to FIG. FIG. 111 is a flowchart showing the procedure of the 7-segment LED driving process.

  First, the main CPU 101 adds “1” to the value of the interrupt counter (+1 update) (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

  In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when S922 is NO), the main CPU 101 ends the 7-segment LED driving process, and the process is interrupted (see FIG. 110). ) In S908. That is, in this embodiment, the 7-segment LED driving process is performed every two interrupt cycles. In this embodiment, the example in which the 7-segment LED driving process is executed when the interrupt counter value is an even number has been described. However, the present invention is not limited to this, and the 7-segment LED drive process is performed when the interrupt counter value is an odd number. The LED driving process may be executed, or the execution timing of the 7-segment LED driving process may be determined using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in S922 that the value of the interrupt counter is an odd number (when S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. Details of the 7-segment display data generation process will be described later with reference to FIG.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets an address of a credit display data storage area for storing credit display data output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. Details of the 7-segment display data generation process will be described later with reference to FIG.

  Next, the main CPU 101 sets an address of a 7-segment common counter storage area for storing a value of a 7-segment common counter described later (S929). Next, the main CPU 101 adds “1” to the value of the 7-segment common counter (+1 update) (S930). In this process, when the updated 7-segment common counter value is “8”, the main CPU 101 sets the 7-segment common counter value to “0”. In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 cycles.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and the address of the target cathode data storage area (the target storage area in the push order display data storage area or the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed to turn off the 7-segment LED and eliminate the influence of afterimages.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). After the process of S936, the main CPU 101 ends the 7-segment LED drive process, and moves the process to the process of S908 in the interrupt process (see FIG. 110).

[7-segment display data generation processing]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 111) will be described with reference to FIG. FIG. 112 is a flowchart showing a procedure of 7-segment display data generation processing.

  Note that “display data”, which will be described later, generated in the 7-segment display data generation process performed in S925 in the 7-segment LED drive process (see FIG. 111) corresponds to the push order display data, and the 7-segment LED drive process (see FIG. 111), “display data” described later generated in the 7-segment display data generation process performed in S928 corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, obtains the quotient value of the division result as the display data of the upper digits of the 2-digit 7-segment LED, and divides the data. The remainder of the result is acquired as display data for the lower digits (S941). Next, the main CPU 101 determines whether or not to perform upper digit display based on the acquired upper digit display data (S942).

  In S942, when the main CPU 101 determines to display the upper digits (when S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, when the main CPU 101 determines in S942 that the upper digit display is not performed (when S942 is NO), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when S942 is YES, the main CPU 101 refers to the 7-segment cathode table and acquires display data for the upper digits (S944). Next, the main CPU 101 stores the acquired upper digit display data in the upper digit display data storage area (not shown) (S945).

  Next, the main CPU 101 refers to the 7-segment cathode table and acquires display data for the lower digits (S946). Next, the main CPU 101 stores the acquired lower-digit display data in a lower-digit display data storage area (not shown) (S947).

  After the process of S947, the main CPU 101 ends the 7-segment display data generation process. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 110), the main CPU 101 shifts the process to the process of S926 during the 7-segment LED drive process. Transfer. On the other hand, when the executed 7-segment display data generation process is the process of S928 during the 7-segment LED drive process (see FIG. 110), the main CPU 101 shifts the process to the process of S929 during the 7-segment LED drive process. .

[Timer update processing]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 110) will be described with reference to FIG. FIG. 113 is a flowchart showing the procedure of the timer update process.

  First, the main CPU 101 sets an update start address of a 2-byte timer storage area (not shown) in the HL register, and sets a 2-byte timer number in the B register (S951).

  Next, the main CPU 101 compares the number of 2-byte timers with the lower limit value “0”. When the number of 2-byte timers is greater than the lower limit value “0”, the main CPU 101 subtracts 1 from the 2-byte timer number (-1 update). If the 2-byte timer number is less than or equal to the lower limit “0”, the 2-byte timer number is held at “0” (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 update) the update start address of the 2-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (updates -1) the 2-byte timer number set in the B register (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is “0” (S954).

  In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not “0” (when S954 is NO), the main CPU 101 returns the process to the process of S952, and after S952 Repeat the process.

  On the other hand, when the main CPU 101 determines in S954 that the number of 2-byte timers set in the B register is “0” (when S954 is YES), the main CPU 101 stores the 1-byte timer storage area in the HL register. The update start address is set, and the 1-byte timer number is set in the B register (S955).

  Next, the main CPU 101 compares the number of 1-byte timers with the lower limit value “0”. When the number of 1-byte timers is larger than the lower limit value “0”, the main CPU 101 subtracts 1 (1 update) the number of 1-byte timers. If the number of 1-byte timers is less than or equal to the lower limit “0”, the number of 1-byte timers is held at “0” (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (-1 update) the number of 1-byte timers set in the B register (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is “0” (S958).

  In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not “0” (when S958 is NO), the main CPU 101 returns the process to the process of S956, and after S956 Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is “0” (when S958 is YES), the main CPU 101 performs electromagnetic counter control processing (S959). ). In this process, an output control process when a signal indicating IN / OUT of medals is output to the external concentration terminal board 47 is performed. After the process of S959, the main CPU 101 ends the timer update process and shifts the process to the process of S909 during the interrupt process (see FIG. 110).

[Data decompression process]
Next, referring to FIG. 114 to FIG. 116, a data decompression process for decompressing compressed data (for example, a symbol arrangement table, various lottery tables, etc.) stored in the main ROM 102 (first storage means). explain. FIG. 114 is an example of a schematic diagram for explaining the concept of the data decompression process, and FIG. 115 is a flowchart showing the procedure of the data decompression process performed in S643, S646, and S648 in the symbol code acquisition process (see FIG. 97). FIG. 116 is an example of a schematic diagram illustrating an example in which data decompression processing is applied to a symbol arrangement table.

  Here, the gaming machine according to the present invention includes a main control means (main CPU 101) for controlling the progress of the game, and a first storage means (main ROM 102) in which information necessary for execution of control by the main control means is stored. And second storage means (main RAM 103) for storing information necessary for execution of control by the main control means, wherein the first storage means includes control data (design arrangement table, various lottery tables, etc.) The compressed data (compressed symbol arrangement table or the like) compressed by transposing the effective bits included in the second storage means, and the second storage means decompresses and stores the compressed data ( A RAM area for gaming), and the main control means has data decompression means (main CPU 101) for decompressing the compressed data and storing it in the decompression storage area, The data decompression means stores the control data in the decompression storage area by inverting the compressed data stored in the first storage means, and the main control means is stored in the decompression storage area. Control is executed based on the control data.

  The compressed data is data in which bit data of valid bit digits in each byte of the decompressed control data is integrated, and does not include invalid bit data.

  The compressed data is composed of one or more compressed blocks corresponding to each of one or more 8-byte blocks constituting the decompressed control data, and the number of compressed blocks is the same as the number of significant bit digits. Is the byte length.

  FIG. 114 shows a data decompression process comparing the compressed block (A) constituting the compressed data in which the bit data of 6 significant bits are accumulated and the 8-byte block (B) constituting the decompressed control data. It is an example of the schematic diagram explaining the concept. Here, for the sake of simplification of explanation, a case where compressed data is composed of one compressed block and decompressed control data is composed of one 8-byte block (also referred to as “decompressed block”) will be described as an example. To do.

  FIG. 114 (A) shows a compression block (6 bytes) constituting the compressed data stored in the main ROM 102, while FIG. 114 (B) shows that the main RAM 103 is decompressed by decompressing the compressed data by data decompression processing. 8 shows an 8-byte block (8 bytes) constituting control data developed. In FIG. 114A, 6 bytes indicated by bytes D1 to D6 constitute a compressed block, and 2 bytes indicated by bytes D7 to D8 indicate empty areas in units of bytes. However, the bytes D7 to D8 do not constitute a compression block but represent a data reduction amount on the main ROM 102 obtained by data compression. That is, the compressed block is configured by 6 × 8 two-dimensional bit data in the range of D1-D6: A1-A8. A1 to A8 indicate 8 bits included in each of 6 bytes of byte D1 to byte D6, and * (asterisk symbol) in the drawing represents bit data of effective bit digits. From the above, it can be understood that the compressed block constituting the compressed data does not include invalid bit data constituting invalid bit digits that are not valid bit digits in one byte (8 bits).

  On the other hand, in FIG. 114 (B), 8 bytes indicated by byte A1 to byte A8 constitute an 8-byte block. That is, the 8-byte block is composed of 8 × 8 two-dimensional bit data in the range of A1-A8: D1-D8. D1 to D8 indicate 8 bits included in each of 8 bytes of byte A1 to byte A8, and 6 bits of D1 to D6 are bit data of 6 effective bit digits, and D7 to D8 Two bits are bit data of an upper bit portion that is not used in the data. Further, * (asterisk symbol) in the figure represents bit data of effective bit digits.

  The main CPU 101 first reads a compressed block (6 bytes) composed of the byte D1 to the byte D6 shown in FIG. 114A from the main ROM 102, and then the main CPU 101 reverses the data of the compressed block. Hereinafter, details of the reverse processing will be described.

  In the inversion processing, first, the main CPU 101 starts with the D1 rows (A1D1, A2D1, A3D1, A4D1, A5D1, A6D1, A7D1) included in the 6 × 8 two-dimensional bit data constituting the compressed block (byte D1-byte D6). The bit string data (horizontal bit string consisting of A8D1) is taken out, the matrix is replaced, and the D1 column included in the 8 × 8 two-dimensional bit data constituting the 8-byte block of the decompression block shown in FIG. It is arranged in the effective bit digit part (vertical bit string including A1D1, A2D1, A3D1, A4D1, A5D1, A6D1, A7D1, and A8D1).

  Next, the main CPU 101 replaces the bit string data of the D2 row (horizontal bit string composed of A1D2, A2D2, A3D2, A4D2, A5D2, A6D2, A7D2, and A8D2) of the compressed block and is included in the 8-byte block. It is arranged in the effective bit digit part (vertical bit string including A1D2, A2D2, A3D2, A4D2, A5D2, A6D2, A7D2, and A8D2) of the D2 column.

  Thereafter, the main CPU 101 processes the compressed block from the D3 line to the D6 line in the same manner as the D1 and D2 columns, and converts all the bit data contained in the compressed block to the effective bit digit part (D1 of the 8-byte block). -D6).

  Next, the main CPU 101 determines that the upper 2 bits (D7-D8) adjacent to the effective bit digit part (D1-D6) of the 8-byte block are not included in the effective bit digit and are not used in the data, that is, all the values. As shown in FIG. 114B, an 8-byte block (8 bytes) is assembled. In the present embodiment, after matrix replacement is completed, a value of 0 is added to the upper 2 bits that are not included in the effective bit string. However, the decompression blocks are all set to 0 before the matrix replacement of the compressed block. After initialization, an 8-byte block may be assembled.

  As described above, in the main ROM 102, a 2-byte free area (FIG. 114), which is the difference between the control data (8 bytes) developed on the main RAM 103 and the compressed data (6 bytes) stored in the main ROM 102. It can be seen that (2 bytes indicated by D7 to D8 in (A)) is secured (saved) as a free area from the main ROM 102.

  In this embodiment, having data in the main ROM 102 in the compressed block format shown in FIG. 114 (A) corresponds to 25% (2 bytes / 8 bytes) of control data (8 byte blocks) on the main ROM 102. In the case of control data (8-byte block) with a smaller number of valid bits, the compressed block shown in FIG. 114 (A) is reduced, resulting in a free space in bytes. Since the area expands, more free space can be secured on the main ROM 102. That is, generally, for control data having a number of bytes that is a multiple of 8, the ROM data capacity can be reduced by a ratio that can be calculated by the equation [(8−number of effective bit digits) / 8]. For example, the ROM data capacity can be reduced by 50% if the number of effective bit digits is 4, and 75% if the number of effective bit digits is 2, and the reduced area of the main ROM 102 can be used. Various data relating to game play can be arranged.

  The procedure of data decompression processing executed by the main CPU 101 will be described below with reference to the flowchart of FIG. The main CPU 101 that executes the data decompression process in the present embodiment constitutes “data decompression means”.

  First, the main CPU 101 sets an address where the compressed data of the main ROM 102 is stored (S1201).

  Next, the main CPU 101 sets the size (byte length) of the compressed block to the same number of bytes as the number of digits based on the number of valid bit digits of the decompressed control data (S1202). For example, if the number of effective bit digits of compressed data is 4, the size (byte length) of the compressed block is 4 bytes. If the number of effective bit digits of compressed data is 6, the size of the compressed block (byte length) ) Is 6 bytes. The number of effective bit digits of the control data is determined in advance according to the type of control data. For example, when the type of control data is a symbol arrangement table, the number of valid bit digits is determined to be four digits.

  Next, the main CPU 101 sets the number of compressed blocks included in the compressed data (S1203). Specifically, the value obtained by dividing the size (byte length) of the compressed data by the size (byte length) of the compressed block is the number of compressed blocks. For example, when the size (byte length) of the compressed data is 32 bytes and the number of valid bit digits is 4, the size (byte length) of the compressed block is 4 bytes and the number of compressed blocks is 8.

  Next, the main CPU 101 sets 0 to the number of processed blocks (counter variable for loop control) (S1204).

  Next, the main CPU 101 sets the address of the compressed block on the main RAM 102 (S1205). Specifically, the first (first byte) address of the compressed data is set in the first loop (S1205 to S1209), and the second compressed data is set in the second loop (S1205 to S1209). The address of the compressed block (number of significant bit digits + 1 byte) is set, and so on.

  Next, the main CPU 101 reverses the bit data of the valid bit digits included in the compressed block whose address is set in S1205, and adds the upper bit portion (invalid bit data of invalid bit digits) to the 8-byte block ( 8x8 size two-dimensional bit data) is assembled (S1206). The process of assembling the 8-byte block is specifically executed according to the data decompression process described with reference to FIG.

  Next, the main CPU 101 accumulates the 8-byte block assembled in S1206 in the game RAM area (decompression storage area) of the main RAM 103 (second storage means) in order to generate control data before compression (S1207), Subsequently, the main CPU 101 adds 1 to the number of processed compressed blocks (counter variable for loop control) (S1208).

  Next, the main CPU 101 determines whether or not the number of compressed blocks of the compressed data is equal to the number of processed compressed blocks (S1209). If the main CPU 101 determines that the number of compressed blocks of the compressed data is equal to the number of processed compressed blocks (S1209 = YES), the main CPU 101 ends the data decompression process, and the process is performed in this subroutine (FIG. 115 is returned to the caller parent routine (subroutine related to the flowchart of the data decompression process) (for example, S644, S647, S649 of the symbol code acquisition process of FIG. 97).

  On the other hand, if the main CPU 101 does not determine in S1210 that the number of compressed blocks of the compressed data is equal to the number of processed compressed blocks (S1209 = NO), the main CPU 101 shifts the processing to S1205, and hereinafter S1205. -Repeat the process of S1209.

  Through the above processing, the main CPU 101 sets the address of the compressed block, assembles an 8-byte block from the compressed block, and repeats the processing of stacking the 8-byte block (S1205-S1208), thereby storing the main ROM 102. The control data (for example, symbol arrangement table, various lottery tables, etc.) is generated on the game RAM area (decompression storage area) of the main RAM 103 (second storage means) by reversing the compressed data of the control data. To do.

  116 is obtained by decompressing the compressed symbol arrangement table (32 bytes) shown in FIG. 116 (2) obtained by compressing the conventional symbol arrangement table (60 bytes) shown in FIG. 116 (1) by data decompression processing. An example of generating the decompressed symbol arrangement table (60 bytes) shown in (3) is shown.

  FIG. 116 (1) shows a symbol arrangement table (60 bytes) that has been stored in the main ROM 102 and bit data (8 bits) of each byte constituting the symbol arrangement table. From the contents of the bit data, it can be understood that all four high-order bits of each byte are 0. That is, it can be understood that the effective bit digit is the lower 4 bits. Here, the symbol arrangement table in the present embodiment constitutes “control data”.

  FIG. 116 (2) shows the content (bit data) of the compressed symbol arrangement table (32 bytes). The compressed symbol arrangement table (32 bytes) is composed of eight compressed blocks each having a size of 4 bytes. The size of 4 bytes is based on the fact that the number of effective bit digits in the conventional symbol arrangement table (60 bytes) shown in FIG. 116 (1) is 4 digits. Here, the compressed symbol arrangement table (32 bytes) constitutes “compressed data”, and the compressed symbol arrangement table (32 bytes) includes the bytes in the conventional symbol arrangement table (60 bytes). Bit data of valid bit digits (lower 4 bits) is accumulated.

  FIG. 116 (3) shows the contents of the decompressed symbol arrangement table (60 bytes) generated on the main RAM 103 by the data decompression process. The decompression symbol arrangement table (60 bytes) is composed of eight 8-byte blocks (8 bytes) each having a size of 8 bytes. Each of the 8-byte blocks (8 bytes) corresponds to each of the 8 compressed blocks (4 bytes) constituting the compressed symbol arrangement table (32 bytes). For the last (8th) 8-byte block, since the last 4 bytes of the last 8-byte block are empty data (all bit values are 0), the 4-byte empty data is removed. Has been. In general, when the size (number of bytes) of control data before compression is a multiple of 8, no data is generated, but the size of control data (number of bytes) before compression is not a multiple of 8. In this case, when the compressed data obtained by compressing the compressed data is decompressed by the data decompression process, the empty data is removed in the last 8-byte block. For example, if the size of the control data is 64 bytes, which is a multiple of 8, the number of 8-byte blocks is 8, and no empty data is generated. On the other hand, if the size of the control data is 65 bytes that is not a multiple of 8, the number of 8-byte blocks is 9, and 7 bytes of empty data are generated in the last (9th) 8-byte block.

  The main CPU 101 sequentially extracts eight compressed blocks (4 bytes) from the compressed symbol arrangement table (32 bytes) shown in FIG. 116 (2) in accordance with the process shown in the flowchart of the data decompression process in FIG. By reversing the bit data of the effective bit digits included in the compressed block (4 bytes), an 8-byte block is assembled, and 8 8-byte blocks are stacked, finally as shown in FIG. 116 (3). A decompressed symbol arrangement table is generated. Since the decompressed symbol arrangement table is the same table as the symbol arrangement table (see FIG. 13), description thereof is omitted.

  In the assembly of the 8-byte block, first, the bit data of the effective bit digits included in the compressed block is arranged in the B0-B3 portion of the decompressed symbol arrangement table shown in FIG. 116 (3), and further, in the B4-B7 portion. This is done by arranging bit data which is not a valid bit digit, that is, bit data whose values are all zero.

  For example, the bit string data (00010110B) in the vertical direction of the rightmost B0 column of the first 8-byte block is the bit string data (00010110B) in the horizontal direction (right to left direction) of the first row of the first compressed block. ) Are arranged vertically and horizontally. Also, the vertical bit string data (10101101B) of the second B1 column from the right of the first 8-byte block is the bit string of the second row in the horizontal direction (right to left direction) of the first compressed block. This is a result of arranging the data (10101101B) vertically and horizontally, and the same applies to the B3 column of the 8-byte block. In the B4 column to the B7 column of the 8-byte block, all bit data that is not valid bit digits, that is, all the values are 0 Is arranged with bit data.

  As described above, in this embodiment, as shown in FIG. 116, the capacity of the main ROM 102 is reduced by 28 bytes, which is the difference between the conventional symbol arrangement table (60 bytes) and the compressed symbol table (32 bytes). is made of. Therefore, according to the gaming machine of the present invention, “providing a gaming machine capable of enhancing the gameability by reducing the capacity of data used in processing of the main control circuit and increasing the free capacity of the ROM of the main control circuit. Can achieve the purpose of this application.

  In the above-described embodiment shown in FIG. 116, a table having an effective bit digit number of 4 bytes has been described as an example. However, a table having a space of 1 bit or more (a table having an effective bit digit number of 7 bits or less). ), It is possible to obtain the effect of reducing the ROM capacity. In addition, the effect is so large that it is a table with many empty bits (table with few effective bit digits).

  In the above embodiment, the symbol arrangement table has been described as an example. However, the present invention is not limited to this, and if there are empty bits (for example, data of less than 8 bits is stored in a fixed storage area of 1 byte). For example, various lottery tables (internal winning combination, ART winning, RT transition, etc.), excitation tables used for reel stepping motors, stop data tables, etc. is there.

  Further, in the above embodiment, an example in which the effective bit digit is the lower bit of each byte is described, but the present invention is not limited thereto, and when the effective bit digit is the upper bit of each byte, Alternatively, the case where the effective bit digit is an arbitrary bit digit in each byte (for example, four digits B3 to B6 of B0 to B7) is also included. According to such a configuration, even in a table having positions of various effective bit digits, “the capacity of data used in the processing of the main control circuit is reduced, and the free capacity of the ROM of the main control circuit is increased, thereby increasing the gameability. The object of the present application can be achieved.

  Further, in the embodiment related to the data decompression process, the process of decompressing (inverting) the compressed data to generate control data has been described. However, if the procedure opposite to this process procedure is executed, the original data It goes without saying that can be compressed. For example, by dividing the original data into one or more 8-byte block units, and accumulating the bit data of the effective bit digits of each byte constituting the 8-byte block to assemble the compressed block, the original data is Compressed data can be obtained by compression (transposition). According to this configuration, it is possible to increase the free space in the storage medium to which the compressed data is output.

[Reel rotation speed control processing]
Next, with reference to FIGS. 117 to 132, the reel rotation speed control process (S904-S909) executed in the interrupt process (FIG. 110) that occurs at a cycle of 1.1172 ms will be described in detail. 117 to 119 are examples of tables and the like related to the reel rotation speed control process, and FIGS. 120 to 132 are examples of flowcharts describing the processing contents of the reel rotation speed control process.

  Here, the main point of the reel rotation speed processing according to the present application is that the symbol positions of the real reels 3L, 3C, 3R detected by the symbol position detecting means and the calculated symbol position of the virtual reel calculated by the symbol position calculating means. A symbol position difference calculating means for calculating a difference; and a rotation speed adjusting means for adjusting the rotation speeds of a plurality of reels according to the difference. The adjustment of the rotation speeds of the reels 3L, 3C, 3R Is that it is performed every cycle shorter than the cycle of one rotation.

[Reel control data storage area]
FIG. 117 shows a first cylinder control data storage area, a second cylinder control data storage area, and a first cylinder control data storage area in which control information used for the reel rotation speed control processing of the plurality of reels 3L, 3C, 3R is stored. It is a table | surface which shows the content of the 3rd drum control data storage area (henceforth "reel control data storage area" generically). The reel control data storage area is arranged on the main RAM 103.

  The reel control data storage area includes a first cylinder control data storage area, a second cylinder control data storage area, and a third cylinder control data storage area. In each of these storage areas, data such as reel control management information, excitation timer, sequence data selection index, sequence data index, pulse counter, symbol position counter, etc. are stored for each of the plurality of reels 3L, 3C, 3R.

[Initial value of counter set when off edge or on edge]
FIG. 118 is a table showing initial values set in the symbol position counter and pulse counter when the off-edge or on-edge of the index sensor is detected in the constant speed waiting and constant speed processing (FIG. 128) described later (S1601). (S1602).

  Here, the on edge or the off edge of the index sensor will be described. The index sensor, that is, the reel position detecting unit constitutes the symbol position detecting means of the present application. The index sensor is provided at a predetermined position of the rotating portion of each main reel with the light sensor and the light receiving portion provided at the non-rotating portion of each main reel, and is received by the light emitting portion and the light receiving portion by the rotation of each main reel. The detection piece which passes between the parts is included.

  The light receiving unit of the index sensor can receive light emitted by the light emitting unit while the detection piece does not pass between the light emitting unit and the light receiving unit while the reels L3, C3, R3 are rotating. While passing between the light emitting unit and the light receiving unit, the light emitted by the light emitting unit is blocked by the detection piece, so that the light emitted by the light emitting unit cannot be received. “On-edge” means switching from a state in which the detection piece does not pass between the light emitting unit and the light receiving unit to a state in which the detection piece passes between the light emitting unit and the light receiving unit. On the other hand, “off-edge” refers to switching from a state in which the detection piece passes between the light emitting unit and the light receiving unit to a state in which the detection piece does not pass between the light emitting unit and the light receiving unit.

  The main CPU 101 detects the “on edge” when the index sensor switches from a state in which the light receiving unit can receive light emitted from the light emitting unit to a state in which it cannot receive light. On the other hand, the main CPU 101 detects “off edge” when the index sensor switches from a state where the light receiving unit cannot receive light emitted from the light emitting unit to a state where it can receive light.

  Further, the pulse counter is a variable indicating the numerical value of the pulse output to the stepping motor corresponding to each reel 3L, 3C, 3R. The value of the pulse counter is reset to 0 each time the output of a predetermined number of pulses (for example, 16) necessary for the rotation of one symbol is counted by the pulse counter. At this time, the symbol position counter is incremented by one. Is done. The value of the symbol counter is cleared to 0 when the reel index is detected by the reel position detector (symbol position detector). In addition, the range which the value of a symbol counter can take becomes an integer from 0 to 19 when the number of symbols arranged on each reel is 20, for example.

  If an on-edge is detected when the reels 3L, 3C, 3R are rotating in the positive direction, the symbol position counter value is set to 0 and the pulse counter value is set to 14.

  If an off-edge is detected when the reels 3L, 3C, 3R are rotating in the positive direction, the symbol position counter value is set to 10 and the pulse counter value is set to 7.

  If an on-edge is detected when the reels 3L, 3C, 3R are reversely rotated, the symbol position counter value is set to 20 and the pulse counter value is set to 16.

  If the off-edge is detected when the reels 3L, 3C, 3R are reversely rotated, the symbol position counter value is set to 10 and the pulse counter value is set to 9.

  That is, the detection piece of the index sensor provided at a predetermined position of each reel 3L, 3C, 3R is provided at a position where the value of the symbol position counter is set to 10.

  Hereinafter, the relationship between the “sequence data selection index” indicating the type of reel effect operation and the “excitation data” input to the stepping motors of the reels 3L, 3C, 3R will be described with reference to FIG. The “excitation data” is based on the “sequence data selection index”, the sequence data selection table (FIG. 119 (a)), the sequence data table (FIG. 119 (b)), and the excitation data table (FIG. 119 (c)). ). These three tables are arranged in the main ROM 102.

[Sequence data selection table]
FIG. 119 (a) is a diagram showing an example of a sequence data selection table. The sequence data selection table defines the relationship between “sequence data selection index” indicating the reel effect operation and “sequence data” indicating the reel operation pattern.

  The sequence data selection table stored in the main ROM 102 includes, for example, “label” and “sequence” columns. The “label” column stores a sequence data selection index (for example, “cRESEL_AC”), and the “sequence” column stores sequence data (for example, “cREDAT_AC”) corresponding to the sequence data selection index in the “label” column. Is stored.

  The “Summary” column is not stored in the main ROM 102 but is described to represent a reel effect operation (for example, “normal acceleration”) corresponding to the “label” indicated by the sequence data selection table.

  The “label” is a common name of a code determined by a designer to assign a storage area or program address arranged in the main RAM 103 or the main ROM 102 to a program source.

  Note that the “sequence” column may include sequence data called an end code (for example, 0FFH) represented as “END CODE” in FIG. 119 (a). The end code will be described below.

  One sequence data selection index (“label” column) corresponds to two or more sequence data (“sequence” column), of which the last sequence data is an end code. For example, the sequence data selection index “dRESEL_REV” (“label” column) of “reverse rotation long” corresponds to 11 sequence data. The first sequence data is “cREDAT_RC” indicating the reel operation pattern of “reverse rotation stop”, the second to tenth sequence data is “cREDAT_RV” indicating the reel operation pattern of “effect 4”, and the eleventh The sequence data is an end code.

[Sequence data table]
FIG. 119 (b) is a diagram illustrating an example of a sequence data table stored in the main ROM 102. The sequence data table defines the relationship between “sequence data” indicating the reel operation pattern, “number of times”, and “excitation data table address”.

  The sequence data table includes columns such as “label”, “number of times”, and “excitation table”. Sequence data (eg, “dREDAT_AC”) is stored in the “label” column. The “number of times” column stores the number of sequences indicating the number of times the stepping motor is excited by the excitation data corresponding to the excitation data address in the “excitation table” column. In addition, an excitation data table address (for example, “dMGDAT_AP”) corresponding to the reel operation pattern in the “label” column is stored in the “excitation table” column.

  The “Summary” column is not stored in the main ROM 102, but is described to represent the outline of the reel operation pattern according to the “label” indicated by the sequence data (for example, “forward rotation acceleration”). .

  The data length of the “number of times” column is 1 byte (8 bits), the sequence number is stored in the lower 7 bits (bits 0-6), and the most significant bit (bit 7) is stored in the block. Used to indicate whether it is an end block. When the most significant bit (bit 7) in the “number of times” column is on, the block is an end block, and when it is off, the block is not an end block.

  For example, “80H + 1” written in the “number of times” column of the sequence data table in FIG. 119 (b) indicates that the bit configuration is “10000001B”. That is, since the most significant bit (bit 7) is on, it indicates that the block is an end block, and at the same time, since the lower 7 bits (bits 0-6) are 1, the sequence number of the block Is 1.

  One sequence data (“label” column) corresponds to one or more blocks. For example, the sequence data “dREDAT_RC” (“label” column) of “reverse rotation stop” corresponds to three blocks. The first block is an excitation table address “dMGDAT_RP” in which the excitation table address (“excitation table” column) indicates “reverse rotation acceleration”, the sequence number is 1, and it is not an end block. The second block is an excitation table address “dMGDAT_REV” in which the excitation table address indicates “weight excitation data 0”, the number of sequences is two, and is not an end block. The third block is an end block having an excitation table address “dMGDAT_RP” indicating “reverse rotation acceleration”, a sequence number of one. That is, the end block is described as “80H + 1” or the like in the “number of times” column, that is, the block is represented by the bit configuration of 10000001B and the most significant bit (bit 7) being on. This indicates the last block among one or more blocks corresponding to one sequence data.

[Excitation data table]
FIG. 119 (c) is a diagram showing an example of an excitation data table stored in the main ROM 102. The excitation data table defines the relationship between “excitation data table address”, “excitation data”, and “excitation timer value”.

  The “excitation timer value” is not a value indicating the actual time, but a count value that is subtracted and updated when a reel control process described later is executed. For example, the “excitation timer value” is “8”. ”Represents 8 × 1.1172 msec = 8.9376.

  The excitation data table includes columns such as “label”, “excitation data”, and “excitation timer value”. An excitation data table address (for example, “dMGDAT_AP”) is stored in the “label” column. The “excitation data” column stores 8-bit (1 byte) excitation data (for example, “0100000B”) corresponding to the excitation data table address in the “label” column. The “excitation timer” column stores a 2-byte excitation timer value (for example, “8”) corresponding to the excitation data table address in the “label” column.

  The “summary” column is not stored in the main ROM 102, but is written to represent an outline (for example, “forward rotation acceleration”) according to the “label” of the excitation data table.

  Here, the three types of tables, the sequence data selection table (FIG. 119 (a)), the sequence data table (FIG. 119 (b)), and the excitation data table (FIG. 119 (c)) described above are viewed through the horizontal skewer. When the sequence data selection index (the “label” column in the sequence data selection table (FIG. 119 (a))) is specified, the excitation data and the excitation timer value (see FIG. It can be seen that the “excitation data” column and the “excitation timer value” column) of the excitation data table 119 (c) are specified.

  Hereinafter, with the sequence data selection index “c_RESEL_AC” indicating the reel effect operation of “normal acceleration” as an example, the excitation data corresponding to the sequence data selection index (reel effect operation) is specified using the above three tables. Will be explained.

  First, when the sequence data selection index (“label” column in the sequence data selection table in FIG. 119 (a)) is “c_RESEL_AC” (normal acceleration), according to the sequence data selection table (FIG. 119 (a)), It can be seen that the sequence data (“sequence” column) corresponding to this sequence data selection index is “cREDAT_AC”.

  Next, according to the sequence data table (FIG. 119 (b)), the first lowercase letter c of this sequence data “dREDAT_AC” (“cREDAT_AC” stored in the “label” column of the sequence data selection table is set to d. It can be seen that the excitation data table address ("excitation table" column) corresponding to (changed) is "dMGDAT_AP".

  Finally, according to the excitation data table (FIG. 119 (c)), the excitation data (“excitation data” column) corresponding to this excitation data table address “dMGDAT_AP” (“label” column) is bit data. The data includes three “0100000B”, and it can be seen that these excitation timer values (“excitation timer” column) are “8”.

  Here, the excitation data “0100000B” means that only the A phase of the stepping motor is excited, and the excitation data “1000000B” means that only the B phase of the stepping motor is excited, and the excitation data “1100000B”. Means that the A phase and B phase of the stepping motor are excited simultaneously, and the excitation data “0000000B” means that none of the phases of the stepping motor is excited.

  The stepping motor connected to each of the reels 3L, 3C, and 3R uses a two-phase excitation stepping motor in this embodiment, but an A-bar phase that forms a pair with the A-phase of the stepping motor, B The B-bar phase paired with the phase is not described because it is generated in the driver circuit for driving the stepping motor.

  Further, in the present embodiment, as described above, the two-phase excitation stepping motor is adopted. However, the present invention is not limited to this. For example, a one-two-phase excitation stepping motor may be adopted.

  In the pachislot machine 1 according to the present embodiment, not only the reels 3L, 3C, and 3R, but also various kinds of effect elements such as the display device 11, the speakers 65L and 65R, and the lamp group 21 are combined in a high degree as in the case of recent gaming machines. When a variety of effects are performed, for example, in the reel effect operation (see the “Summary” column of the sequence data selection table) indicated by the sequence data selection index according to the present embodiment, normal acceleration, normal stop, acceleration 1 , Acceleration 2, acceleration 3, reverse rotation 1 week, reverse rotation stop, reverse rotation long, bull, reverse acceleration 2, reach eye 1, reach eye 2, triple don 1, triple don 2, triple triple 3, wave , Time retrograde, time retrograde 1, time retrograde 2 and so on.

  Thus, it can be seen that the movement of the reels 3L, 3C, 3R is deeply related to various effects using the display device 11, the speakers 65L, 65R, the lamp group 21, and the like. Therefore, in order to achieve an effect of the high level of the pachislot 1 as a whole, the reels 3L, 3C, 3R, where the player's attention is most concentrated, are the display device 11, the speakers 65L, 65R, and the lamp group 21. It is extremely important and indispensable to make a motion that is accurately synchronized with effects such as images, sounds, and lights using the above. Therefore, it is possible to execute the operation as designed in advance even if the reel rotation speed is increased or decreased at an arbitrary timing, and a specific symbol can be stopped at a specific timing. Needless to say, it is important to “provide a game machine that can be used”.

[Virtual reel control processing]
FIG. 120 is an example of a flowchart of the virtual reel control process in step S903 of the interrupt process (1.1172 ms) shown in FIG. 110 by the main CPU 101.

  In the virtual reel control process, the rotation operation of the reels 3L, 3C, and 3R is simulated by software by periodically updating the value of the virtual reel frame position and the value of the virtual reel step of the virtual reel that performs ideal rotation. It is. A reel rotation speed calculation process for setting an excitation timer correction value for adjusting the rotation speed of the reels 3L, 3C, and 3R as the value of the virtual reel frame position and the value of the virtual reel step that are periodically updated in the virtual reel control process. (FIG. 119 (b)) is used to calculate the difference between the calculated symbol position and the symbol position of the actual reel and the correction value of the excitation timer.

  First, the main CPU 101 updates (subtracts 1) the value of the virtual reel timer (S1001).

  The range of values that can be taken by the virtual reel timer is an integer from 1 to 3, and the initial value is set to 3. This value is the virtual value in the interrupt process (FIG. 110) generated at a cycle of 1.1172 ms. Each time the reel control processing routine (FIG. 120) is called, 1 is subtracted and the next 1 is 3 (in the order of 3 → 2 → 1 → 3).

  Next, the main CU 101 determines whether or not the value of the virtual reel timer has been updated from 1 to 3 in S1001. (S1002). When the main CPU 101 determines in S1002 that the value of the virtual reel timer has not been updated from 1 to 3 (when S1002 is NO), the main CPU 101 ends the virtual reel control process and interrupts the process. Move to S904 in FIG.

  On the other hand, when the main CPU 101 determines in S1002 that the value of the virtual reel timer has been updated from 1 to 3 (when S1002 is YES), the main CPU 101 decrements the virtual reel step by 1 (S1003).

  That is, the virtual reel step of the virtual reel is decremented by 1 in S1003 every three interruptions.

  The range that the virtual reel step can take is an integer from 0 to 16, and as will be described later, when it becomes 0, 16 is set which is the number of pulses corresponding to the reel rotation for one symbol.

  Next, the main CU 101 determines whether or not the value of the virtual reel step is zero. (S1004). In S1004, when the main CPU 101 determines that the value of the virtual reel step is not 0 (when S1004 is NO), the main CPU 101 ends the virtual reel control process, and the process is being interrupted (FIG. 110). Return to S904.

  On the other hand, when the main CPU 101 determines in S1004 that the value of the virtual reel step is 0 (when S1004 is YES), the main CPU 101 sets 16 as the number of pulses corresponding to one symbol to the virtual reel step. Set (S1005).

  Next, the main CU 101 determines whether or not the value of the virtual reel frame position is zero. (S1006). In S1004, when the main CPU 101 determines that the value of the virtual reel frame position is not 0 (when S1006 is NO), the main CPU 101 shifts the processing to S1008 described later.

  On the other hand, when the main CPU 101 determines in S1006 that the value of the virtual reel frame position is 0 (when S1006 is YES), the main CPU 101 has 20 frames corresponding to one rotation of the reel at the virtual reel frame position. 21 which is a value obtained by adding 1 to is set (S1007).

  Next, the main CU 101 subtracts 1 from the virtual reel frame position (S1008). Next, the main CU 101 ends the virtual reel control process, and returns the process to S904 in the interrupt process (FIG. 110).

[Reel control processing]
FIG. 121 is an example of a flowchart of the reel control process in steps S905 (first reel), S907 (second reel), and S909 (third reel) of the interrupt process (1.1172 ms) shown in FIG. 110 by the main CPU 101. is there. That is, the reel control process is executed for each of the reels 3L, 3C, and 3R each time an interrupt process (FIG. 110) occurs at a cycle of 1.1172 ms.

  In the reel control process, the corresponding subroutine is caused to execute a process corresponding to the value of the reel control management information. The reel control management information refers to the reel status such as “acceleration preparation 1”, “acceleration preparation 2”, “accelerating”, “stopping”, “constant speed waiting”, “constant speed”, “waiting for start position”, etc. The 1-byte variable shown in FIG. 117 is stored in the reel control data storage area (main RAM 103) shown in FIG.

  First, the main CPU 101 updates (subtracts 1) the value of the excitation timer (S1101).

  The excitation timer is a variable for controlling excitation timing (timing for inputting excitation data to the stepping motor), and the value of the excitation timer is stored in the reel control data storage area (main RAM 103) shown in FIG. . The value of the excitation timer is decremented by 1 every interrupt process (1.1172 ms) (S1101), and the excitation timing is captured when the value becomes 0. Therefore, for example, if the contents of the excitation data are the same, when the value of the excitation timer is set to a small value, the value is higher than when the value of the excitation timer is set to a large value. Excitation data is input to the stepping motor at a frequency, and as a result, it is possible to control to increase the rotation speed of the stepping motor, and consequently the rotation speed of the reels 3L, 3C, 3R.

  Next, the main CPU 101 determines whether or not the value of the excitation timer is zero. (S1102). When the main CPU 101 determines in S1102 that the value of the excitation timer is not 0 (when S1102 is NO), the main CPU 101 ends the reel control process, and the process proceeds to S906 in the interrupt process (FIG. 110). , Return to S908 or S910.

  In other words, the fact that the value of the excitation timer is not 0 means that it is not the excitation timing as described above. In this case, the reel control for adjusting the reel rotation speed by transmitting the excitation data to the stepping motor. The process ends immediately and returns to the interrupt process (FIG. 110) which is the caller routine.

  On the other hand, when the main CPU 101 determines in S1102 that the excitation timer is 0 (when S1102 is YES), the main CPU 101 determines whether or not the value of the reel control management information is “acceleration preparation 1”. Judgment is made (S1103).

  When the main CPU 101 determines in S1103 that the value of the reel control management information is “acceleration preparation 1” (when S1103 is YES), the main CPU 101 executes acceleration preparation 1 processing (FIG. 122) ( S1104) Subsequently, the processing shifts to excitation output processing (S1114).

  On the other hand, in S1103, when the main CPU 101 determines that the value of the reel control management information is not “acceleration preparation 1” (when S1103 is NO), the main CPU 101 determines that the value of the reel control management information is “acceleration preparation 2”. Is determined (S1105).

  When the main CPU 101 determines in S1105 that the value of the reel control management information is “acceleration preparation 2” (when S1105 is YES), the main CPU 101 executes acceleration preparation 2 processing (FIG. 123) ( S1106) Subsequently, the process proceeds to excitation output processing (S1114).

  On the other hand, when the main CPU 101 determines in S1105 that the value of the reel control management information is not “acceleration preparation 2” (when S1105 is NO), the main CPU 101 determines that the value of the reel control management information is “accelerating”. Alternatively, it is determined whether or not “stopped” (S1107).

  In S1107, when the main CPU 101 determines that the value of the reel control management information is “accelerating” or “stopping” (in the case of YES determination in S1107), the main CPU 101 performs the suspending process during acceleration (FIG. 124) is executed (S1108), and then the process proceeds to the excitation output process (S1114).

  On the other hand, when the main CPU 101 determines in S1107 that the value of the reel control management information is not “accelerating” or “stopped” (when S1107 is NO), the main CPU 101 determines that the value of the reel control management information is It is determined whether or not “waiting for constant speed” or “during constant speed” (S1109).

  In S1109, when the main CPU 101 determines that the value of the reel control management information is “Waiting for constant speed” or “During constant speed” (when S1109 is YES), the main CPU 101 waits for constant speed, and is at constant speed. The intermediate process (FIG. 128) is executed (S1110), and the process subsequently proceeds to the excitation output process (S1114).

  On the other hand, when the main CPU 101 determines in S1109 that the value of the reel control management information is not “waiting for constant speed” or “during constant speed” (when S1109 is NO), the main CPU 101 determines that the reel control management information It is determined whether or not the value is “wait for stop start position” (S1111).

  In S1111, when the main CPU 101 determines that the value of the reel control management information is “wait for stop start position” (when S1111 is YES), the main CPU 101 executes a stop start position wait process (FIG. 130). (S1112) Subsequently, the process proceeds to the excitation output process (S1114).

  On the other hand, when the main CPU 101 determines in S1111 that the value of the reel control management information is not “wait for stop start position” (when S1111 is NO), the main CPU 101 executes an all-phase OFF process (FIG. 131). (S1113).

  Next, the main CPU 101 executes excitation output processing (FIG. 132) (S1114).

  Next, the main CPU 101 converts the pulse data (excitation data) generated in the excitation output process (S1114) and stored in the excitation data storage area into a port output IC (not shown) connected to the external bus interface 104 of the microprocessor 91. To the stepping motor connected to the target reel (S1115). Thereafter, the main CPU 101 ends the reel control process, and returns the process to S906, S908, or S910 in the interrupt process (FIG. 110).

[Acceleration preparation 1 processing]
FIG. 122 is an example of a flowchart of the acceleration preparation 1 process in step S1104 of the reel control process shown in FIG. 121 by the main CPU 101. The main purpose of the acceleration preparation 1 process (FIG. 122) and the acceleration preparation process 2 (FIG. 123) to be described later is to stabilize the stepping motor once before acceleration and to achieve a control for acceleration. Time (start-up settling time value x interrupt period 1.1172 ms) The stepping motor is set in a start-up settling hold state in which the A phase and B phase are excited and stopped.

  First, the main CPU 101 sets “acceleration preparation 2” in the reel control management information (S1201).

  Specifically, the bit corresponding to “acceleration preparation 2” of the reel control information (1 byte) stored in the reel control data storage area on the main RAM 103 is turned on, and the bit corresponding to “acceleration preparation 1” is set. Turn off.

  By this process, after the start-up settling hold time has elapsed (when the excitation timing set by the start-up settling time value becomes 0 as a result of the excitation timing being captured) Control can be performed so that the acceleration preparation 2 process (FIG. 123) is executed in the reel control process (FIG. 121) (S1105 = YES → S1106).

  Next, the main CPU 101 sets the value of the start-up settling hold time in the excitation timer (S1202).

  For example, in this process, if a value (for example, 192) corresponding to a period (for example, 193 ms) for which the excitation pulse input to the stepping motor is to be suppressed is set as the start-up static set hold time in the excitation timer, the next interrupt After the process, the reel control process is interrupted every time until the set excitation timer value (for example, 192) becomes 0 (FIG. 121: Is the reel control process S1102 excitation timer 0? = NO → return), the period (for example, , About 193 ms), the input of excitation data to the stepping motor can be stopped.

  Next, the main CPU 101 sets an initial value (for example, FFH) at the scheduled stop position (S1203).

  Next, the main CPU 101 sets the startup static hold excitation data (S1204), ends the acceleration preparation 1 process, and moves the process to S1114 (excitation output process) in the reel control process (FIG. 121).

[Acceleration preparation 2 processing]
FIG. 123 is an example of a flowchart of the acceleration preparation 2 process in step S1106 of the reel control process shown in FIG. 121 by the main CPU 101.

  First, the main CPU 101 sets “accelerating” in the reel control management information (S1301).

  Specifically, the bit corresponding to “acceleration” in the reel control information (1 byte) stored in the reel control data storage area on the main RAM 103 is turned on, and the bit corresponding to “acceleration preparation 2” is turned off. To. Thus, when the excitation timing is captured in the next reel control process (FIG. 121) (step S1102 = YES), control is performed such that the process during acceleration (FIG. 124, FIG. 125) is executed during acceleration. (S1107 = YES → S1108).

  Next, the main CPU 101 sets a start-time static hold time (for example, 192) in the excitation timer (S1302).

  Next, the main CPU 101 sets the startup static hold excitation data (S1204), ends the acceleration preparation 2 process, and moves the process to S1114 (excitation output process) in the reel control process (FIG. 121).

[Processing during acceleration and stopping]
FIG. 124 is an example of a flowchart of processing during acceleration and stop in step S1108 of the reel control processing shown in FIG. 121 by the main CPU 101.

  First, the main CPU 101 acquires sequence data from the sequence data selection index (S1401).

  Specifically, from the sequence data selection index stored in the reel control data storage area (FIG. 117) on the main RAM 103, based on the sequence data selection table (FIG. 119 (a)), the sequence data selection index ( For example, sequence data (for example, “cREDAT_AC” in the sequence string) corresponding to “cRESEL_AC” in the label string is acquired.

  Next, the main CPU 101 determines whether or not the value of the sequence data acquired in S1401 is an end code (for example, 0FFH) (S1402). In S1402, when the main CPU 101 determines that the value of the sequence data is an end code (for example, 0FFH) (when S1402 is YES), the main CPU 101 executes end code processing (FIG. 125) ( In step S1417, the process returns to the caller reel control process (FIG. 121).

  On the other hand, when the main CPU 101 determines in S1402 that the value of the sequence data is not an end code (for example, 0FFH) (when S1402 is NO), the main CPU 101 determines that the value of the sequence data is a stop code (for example, 0FEH) is determined (S1403).

  When the main CPU 101 determines that the value of the sequence data is a stop code (for example, 0FEH) (when S1403 is YES), the main CPU 101 executes stop code processing (FIG. 126) (S1418). The process returns to the calling reel control process (FIG. 121).

  On the other hand, when the main CPU 101 determines in S1403 that the value of the sequence data is not a stop code (for example, 0FEH) (when S1403 is NO), the main CPU 101 obtains the table address of the sequence data table from the sequence data. Set (S1404).

  Specifically, the main CPU 101 stores the data in the label column of the sequence data table (FIG. 119 (b)) based on the sequence data acquired in S1401 (for example, “cREDAT_AC” in the sequence column of the sequence data selection table). Set the table address (for example, “dREDAT_AC”). As a result, the sequence data table (FIG. 119 (b)) can be referred to in later processing.

  Next, the main CPU 101 determines whether or not the sequence count data is 0 (S1405).

  Here, the “sequence number data” is one of the reel control information stored in the reel control data storage area (FIG. 117) on the main RAM 103, and “sequence number data” is “1” in the sequence data table (FIG. 119 (b)). This is a variable provided for control for executing processing during acceleration and stop for the number of times set in the “number of times” column.

  In S1405, when the main CPU 101 determines that the value of the sequence count data is not 0 (when S1405 is NO), the main CPU 101 shifts the processing to S1407.

  On the other hand, when the main CPU 101 determines in S1405 that the value of the sequence count data is 0 (when S1405 is YES), the main CPU 101 acquires the sequence count from the table address and stores it in the sequence count data. (S1406).

  Specifically, the main CPU 101 refers to the sequence data table (FIG. 119 (b)), and determines the number of sequences (for example, “1”) from the table address (for example, “dREDAT_AC”) in the “label” column. ) And this value is stored in the sequence number data in the reel control data storage area (FIG. 117) on the RAM 103.

  Next, the main CPU 101 sets an excitation data table address (for example, dMGDAT_AP) from the table address (for example, “dREDAT_AC”) and the excitation data index (S1407).

  Here, the “excitation data index” is one of reel control information stored in the reel control data storage area (FIG. 117) on the main RAM 103, and an acceleration excitation data table or deceleration excitation data (not shown). This variable is used for reel control using a table.

  The acceleration data table for acceleration indicates the excitation data for the stepping motors of the reels 3L, 3C, 3R during the period from when the rotation of the reels 3L, 3C, 3R is stopped to the state of constant speed rotation (during acceleration). It is a table for controlling an input in steps. The acceleration excitation data table includes, for example, a row composed of an “excitation data index” column and an “excitation timer” column, including the number of rows corresponding to the stage of control. Stores an integer value (for example, 1, 2, 3,..., 12) that increases by 1 in accordance with the row, and the excitation timer value at each stage is stored in the “excitation timer” column. That is, at the time of acceleration, the input of excitation data to the stepping motors of the reels 3L, 3C, 3R is executed step by step according to the order of the “excitation data index” column.

  On the other hand, the excitation data table for deceleration is the excitation for the stepping motors of the reels 3L, 3C, 3R from the state where the reels 3L, 3C, 3R are rotating at a constant speed to the state where the rotation is stopped (during the stop). It is a table for controlling data input step by step.

  The deceleration excitation data table includes, for example, a row composed of an “excitation data index” column and an “excitation timer” column, including the number of rows corresponding to the stage of control, and the “excitation data index” column. Is an integer value that is incremented by 1 according to the row and is not stored in the “excitation data index” column of the acceleration excitation data table (for example, 13, 14), and is stored in the “excitation timer” column. Stores the excitation timer value at each stage. That is, at the time of deceleration, excitation data input to the stepping motors of the reels 3L, 3C, 3R is executed step by step according to the order of the “excitation data index” column.

  In the “excitation data index” stored in the reel control data storage area (FIG. 117) on the main RAM 103, “acceleration data table for acceleration or deceleration excitation data table currently applied in the stepwise control”. A value indicating the “excitation data index” column is stored.

  Next, the main CPU 101 updates (adds 1) the excitation data index (S1408).

  Next, the main CPU 101 acquires the excitation timer value and the excitation data from the excitation data table address, and stores them in the “excitation timer” in the reel control data storage area (FIG. 117) on the main RAM 103 (S1409).

  Specifically, the main CPU 101 refers to the excitation data table (FIG. 119 (c)), and in the row where the excitation data address (for example, “dMGDAT_AP”) acquired in S1407 is stored in the “label” column. The excitation data (for example, “01000000B”) and the excitation timer value (for example, “8”) stored in the “excitation data” column and the “excitation timer value” column are acquired, and this value (for example, “8”) Is stored in the sequence number data stored in the reel control data storage area (FIG. 117) on the RAM 103.

  Next, the main CPU 101 subtracts 1 from the sequence number data (S1410).

  Next, the main CPU 101 determines whether or not the sequence count data is 0 (S1411). In S1411, when the main CPU 101 determines that the number of sequences is not 0 (when S1411 is NO), the main CPU 101 shifts the processing to S1416.

  On the other hand, in S1411, when the main CPU 101 determines that the sequence count data is 0 (when S1411 is YES), the main CPU 101 updates the sequence data index by 1 (S1412).

  Next, the main CPU 101 determines whether or not the sequence table is an end block (S1413).

  Here, “sequence data is an end block” means that the current process is the process of the last block of one or more blocks corresponding to one sequence data (“label” column of the sequence data table) It means that. As described above, in the sequence data table (FIG. 119 (b)), one sequence data ("label" column) corresponds to one or more blocks. The “end block” refers to the block processed last among these one or more blocks.

  In the sequence data table (FIG. 119 (b)), the most significant bit (bit 7) of the sequence number (“number” column) corresponding to the block is turned on, that is, the sequence number value is set to “80H + 1”, “ By setting to 80H + 120, “80H + 66”, etc., it is indicated that the block is an end block.

  In S1413, when the main CPU 101 determines that the sequence table is not an end block (when S1411 is NO), the main CPU 101 shifts the processing to S1416.

  On the other hand, when the main CPU 101 determines in S1413 that the sequence table is an end block (when S1413 is YES), the main CPU 101 updates the sequence selection index by 1 (S1414), and the sequence data index and sequence The count data is cleared to 0 (S1415).

  Next, the main CPU 101 sets excitation data for the excitation data acquired in S1409 (S1416), terminates the process during acceleration and stop, and performs the process in S1114 (excitation output process) in the reel control process (FIG. 121). ).

[End code processing]
FIG. 125 is an example of a flowchart of the end code processing executed by the main CPU 101 in S1417 of the accelerating / stopping process shown in FIG.

  First, the main CPU 101 sets “Waiting for constant speed” in the reel control management information (S1420).

  Specifically, the bit corresponding to “Waiting for constant speed” of the reel control information (1 byte) stored in the reel control data storage area on the main RAM 103 is turned on, and “accelerated” or “stopped” is set. Turn off the corresponding bit. Thereby, when the excitation timing is captured in the reel control processing (FIG. 121) after the next time (step S1102 = YES), control is performed so that the constant speed waiting and constant speed processing (FIG. 128) is executed. Yes (S1109 = YES → S1110).

  Next, the main CPU 101 initializes a symbol position counter (S1421). Specifically, an initial value of 16 is set in the symbol position counter stored in the reel control data storage area (FIG. 117) on the main RAM 103.

  Next, the main CPU 101 sets a constant speed excitation update interval timer value (for example, 4) in the excitation timer (S1422).

  Next, the main CPU 101 executes a reel rotation speed calculation process (FIG. 127) (S1423).

  Next, the main CPU 101 determines the reel control data storage area on the main RAM 103 based on the correction value (0, +1, −1) of the excitation timer set in the reel rotation speed calculation process (FIG. 127) executed in S1423. The value of the excitation timer stored in (FIG. 117) is updated (S1424).

  For example, when the correction value is “+1”, a value (for example, “5”) obtained by adding 1 to the excitation timer value (for example, “4”) set in S1422 is the reel control information on the sub RAM 103. Set to excitation timer. On the other hand, when the correction value is “−1”, the excitation timer is a value obtained by adding 1 (for example, “5”) to the excitation timer value (for example, “4”) set in S1422. Set in the excitation timer of control information. If the correction value is 0, the excitation timer remains unchanged with the excitation timer value (eg, “4”) set in S1422.

  Next, the main CPU 101 determines whether or not the rotation direction of the reel to be processed (any one of the reels 3L, 3C, and 3R) is normal rotation (S1425). In S1425, when the main CPU 101 determines that the rotation direction of the reel to be processed is forward rotation (when S1425 is YES), the main CPU 101 sets the forward direction excitation data (S1426) and ends code processing. And the process returns to the stop process (FIG. 124) while the caller is accelerating.

  On the other hand, when the main CPU 101 determines in S1425 that the rotation direction of the reel to be processed is not forward rotation (when S1425 is NO), the main CPU 101 sets reverse excitation data (S1427) and ends the process. The code processing is terminated, and the process returns to the suspension process (FIG. 124) during the acceleration of the caller.

[Stop code processing]
FIG. 126 is an example of a flowchart of the stop code process executed by the main CPU 101 in S1418 of the stop process during acceleration shown in FIG.

  First, the main CPU 101 sets a stop static hold in the reel control management information (S1430).

  Specifically, the bit corresponding to “stop settling hold” of the reel control information (1 byte) stored in the reel control data storage area on the main RAM 103 is turned on, and “accelerating” or “stopping” Turn off the bit corresponding to.

  Next, the main CPU 101 sets a stop static hold timer value in the excitation timer (S1431).

  Here, the stop settling hold timer value is a period of a settling hold sufficient to stop the rotation of the rotating reels 3L, 3C, 3R (continuing a state in which no excitation data is input to the stepping motor). It needs to be a value that can be secured. Therefore, the value of the stop settling hold timer value can be a large value such as 192, for example, and according to this, 192 interrupts (stop settling hold timer value 192 x interrupt period 1.1172 ms = about 0. 19 seconds) can be secured.

  Next, the main CPU 101 sets the excitation data for stop static hold (S1432).

  The excitation data of the stationary stop hold can be, for example, “00000000B” in which no phase of the stepping motor is excited.

  Next, the main CPU 101 ends the stop code process, and returns to the stop process (FIG. 124) while the caller is accelerating.

[Reel rotation speed calculation processing]
127 is an example of a flowchart of the reel rotation speed calculation process executed by the main CPU 101 in the acceleration / stopping process S1423 shown in FIG. 125 and the constant speed waiting / fixed speed process S1605 shown in FIG. is there.

  In this process, the main CPU 101 calculates the difference between the virtual symbol position of the virtual reel and the actual symbol position of the reel, and sets the correction value (0, +1, −1) of the excitation timer according to the difference.

  As a result, the value of the excitation timer is corrected and set in the excitation timer in the reel control management information storage area (FIG. 117) in the upper routine of the reel rotation speed calculation processing subroutine. As a result, the frequency of inputting pulse signals (excitation data) to the stepping motor is adjusted, so that the rotational speed of the reels 3L, 3C, 3R can be adjusted.

  Therefore, the main CPU 101 that executes the reel rotation speed calculation process constitutes “symbol position calculation means”, “symbol position difference calculation means”, and “rotation speed adjustment means”.

  First, the main CPU 101 calculates a virtual pulse position (S1501). Specifically, the virtual pulse position is (1) a value obtained by multiplying the virtual reel frame position by 16 (the number of excitation pulses necessary for rotating the reel by one symbol), and (2) one reel's worth of rotation. It is calculated as a value obtained by adding the number of pulses (20 × 16) and (3) the virtual reel step.

  Here, the virtual reel frame position and the virtual reel step are the virtual reel frame position and the virtual reel step of the virtual reel that are simulated by software in the virtual reel control process (FIG. 120).

  In addition, in the calculation of the virtual pulse position, (2) the number of pulses per reel (20 × 16) is added because the calculation result is a negative value in the calculation of relative position (S1503) described later. This is to prevent this.

  Next, the main CPU 101 calculates the symbol pulse position on the actual reel (S1502). Specifically, the symbol pulse position includes (1) a value obtained by multiplying the symbol position counter by 16 (the number of excitation pulses necessary to rotate the reel by one symbol), and (2) the value of the pulse counter. Are calculated as values obtained by adding.

  Here, the symbol position counter and the pulse counter are reel control data stored in the reel control information storage area (FIG. 117) on the main RAM 103.

  Next, the main CPU 101 calculates a relative position (S1503). The relative position represents the difference between the virtual symbol position of the virtual reel and the actual reel symbol position. Specifically, the relative position is calculated in S1502 from the value of the virtual pulse position calculated in S1501. It is calculated as a value obtained by subtracting the calculated symbol pulse position value on the actual reel.

  Next, the main CPU 101 calculates a deviation of the symbol position on the surface (S1504). The “designated symbol position deviation” here refers to a symbol position deviation that does not take into account the so-called circulation delay, and specifically, the relative position value calculated in S1503 corresponds to one reel revolution. It is a numerical value of the remainder of the result (the quotient and the remainder which are integer values) divided by the number of pulses to be performed (20 × 16 = 320).

  For example, when the value of the virtual pulse position calculated in S1501 is 500 and the value of the symbol pulse position calculated in S1502 is 400, the value of the relative position is calculated as 500−400 = 100 in S1503. In S1504, 100, which is the remainder of the result (quotient = 0, remainder = 100) of the relative position 100 divided by the number of pulses (20 × 16 = 320) corresponding to one revolution of the reel, is calculated. It will be.

  For example, when the value of the virtual pulse position calculated in S1501 is 500 and the value of the symbol pulse position calculated in S1502 is 100, the value of the relative position is calculated as 500-100 = 400 in S1503. Therefore, in S1504, 80, which is the remainder of the result obtained by dividing the relative position 400 by the number of pulses (20 × 16 = 320) corresponding to one reel round (quotient = 1, remainder = 80), is calculated. Will be. This is an example in which the so-called lap delay has occurred, and (2) the number of pulses for one reel (20 × 16) is added to the lap delay for convenience of calculation of the virtual pulse position in step S1501. Can occur.

  Next, the main CPU 101 determines whether or not the remainder calculated in S1504 is 0 (S1505). When the main CPU 101 determines in S1505 that the remainder calculated in S1504 is 0 (when S1505 is YES), the main CPU 101 sets “0” as the correction value of the excitation timer (S1506). Then, the reel rotation speed calculation process is terminated, and the process returns to the calling source routine (acceleration, stop process or constant speed wait, constant speed process). If “0” is set as the correction value of the excitation timer, it means that there is no correction of the excitation timer.

  On the other hand, when the main CPU 101 determines in S1505 that the remainder calculated in S1504 is not 0 (when S1505 is NO), the main CPU 101 determines whether or not the remainder is 272 or more (S1507). . Note that 272 is the number of pulses required to rotate the reel by 17 symbols (17 × 16 = 272).

  In S1507, when the main CPU 101 determines that the remainder calculated in S1504 is 272 or more (when S1507 is YES), the main CPU 101 sets “+1” as the correction value of the excitation timer (S1508). ), The reel rotation speed calculation process is terminated, and the process returns to the calling source routine (acceleration, stop process or constant speed wait, constant speed process). When “+1” is set as the correction value of the excitation timer, the value of the excitation timer is increased (the frequency at which excitation data is input to the stepping motors of the reels 3L, 3C, 3R is reduced) to reduce the reel 3L. , 3C, 3R means to slow down the rotation speed.

  On the other hand, when the main CPU 101 determines in S1507 that the remainder calculated in S1504 is not 272 or more (when S1507 is NO), “−1” is set as the correction value of the excitation timer (S1509). The reel rotation speed calculation process is terminated, and the process returns to the calling source routine (acceleration, stop process, constant speed wait, constant speed process). When "-1" is set as the correction value of the excitation timer, the value of the excitation timer is reduced (by increasing the frequency of inputting excitation data to the stepping motors of the reels 3L, 3C, 3R). This means that the rotational speed of 3L, 3C, 3R is increased.

[Waiting for constant speed, processing during constant speed]
FIG. 128 is an example of a flowchart of the constant speed waiting and constant speed processing in step S1110 of the reel control process shown in FIG. 121 by the main CPU 101.

  First, the main CPU 101 determines whether an off edge or an on edge of the index sensor has been detected (S1601).

  When the main CPU 101 determines in S1601 that the off edge or the on edge of the index sensor has not been detected (when S1601 is NO), the main CPU 101 executes symbol position update processing (FIG. 129) described later (S1604). The process proceeds to S1605.

  On the other hand, when the main CPU 101 determines in S1601 that the off edge or the on edge of the index sensor has been detected (YES in S1601), the main CPU 101 initializes the pulse counter and the symbol position counter based on the table of FIG. A value is set (S1602).

  For example, when the on-edge of the index sensor is detected when the rotation of the reels 3L, 3C, 3R is positive, the main CPU 101 stores the symbol position counter stored in the reel control data storage area (FIG. 117). Set the value to 0 and set the value of the pulse counter to 14.

  Next, the main CPU 101 sets “constant speed” in the reel control management information (S1603).

  Specifically, the bit corresponding to “constant speed” of the reel control information (1 byte) stored in the reel control data storage area (FIG. 117) on the main RAM 103 is turned on, and “waiting for constant speed” is set. Turn off the corresponding bit.

  Next, the main CPU 101 executes a reel rotation speed calculation process (FIG. 127) (S1605).

  Next, the main CPU 101 stores the value in the reel control data storage area (FIG. 117) on the main RAM 103 based on the excitation timer correction value set in the reel rotation speed calculation processing subroutine (FIG. 127) called in S1605. The value of the excitation timer being updated is updated (S1606).

  For example, when the correction value is “+1”, a value obtained by adding 1 to the currently set excitation timer value is set in the excitation timer of the reel control information on the sub RAM 103. On the other hand, when the correction value is “−1”, a value obtained by adding 1 to the currently set excitation timer value is set in the excitation timer of the reel control information on the sub RAM 103. When the correction value is 0, the value of the excitation timer is not changed.

  Next, the main CPU 101 determines whether or not the rotation direction of the reel to be processed (any one of the reels 3L, 3C, and 3R) is normal rotation (S1607). In S1805, when the main CPU 101 determines that the rotation direction of the reel to be processed is forward rotation (when S1607 is YES), the main CPU 101 sets the forward direction excitation data (S1608) and waits for a constant speed. Then, the constant speed process is terminated, and the process proceeds to S1114 (excitation output process) in the reel control process (FIG. 121).

On the other hand, when the main CPU 101 determines in S1607 that the rotation direction of the reel to be processed is not forward rotation (when S1607 is NO), the main CPU 101 sets reverse excitation data (S1609), After waiting for speed, the constant speed process is terminated, and the process proceeds to S1114 (excitation output process) in the reel control process (FIG. 121).
[Design position update processing]
FIG. 129 is an example of a flowchart of the symbol position update process in step S1604 of the constant speed waiting and constant speed processing shown in FIG. 128 or step S1603 of the stop start position waiting process shown in FIG. 130 by the main CPU 101.

  In this process, the main CPU 101 updates the pulse counter and the symbol position counter stored in the reel control information storage area (FIG. 117) on the main RAM 103, so that the values of the pulse counter and the symbol position counter are actually set. The symbol position of the reel is reflected. The initial value of the pulse counter is set to 16, which is the number of pulses required to rotate the reel by one symbol, and is decremented by one each time the symbol position update subroutine is executed. When the updated pulse counter reaches 0, the pulse is input 16 times to the stepping motor, and the reel has rotated by one frame, so 1 is added to the symbol position counter (or 1 is subtracted in the case of reverse rotation). . Further, when the reel rotates by 20 symbols, the reel has made one rotation. At this time, the symbol position counter is reset to the initial value.

  First, the main CPU 101 updates (subtracts 1) the value of the pulse counter (S1701).

  Here, the pulse counter is reel control data stored in a reel control information storage area (FIG. 117) on the main RAM 103.

  Next, the main CPU 101 determines whether or not the value of the pulse counter is 0 (S1702). In S1702, when the main CPU 101 determines that the value of the pulse counter is not 0 (when S1702 is NO), the symbol position updating process is terminated, and the caller routine (constant speed waiting, constant speed processing or stoppage) Return to the start position wait process.

  On the other hand, when the main CPU 101 determines in S1702 that the value of the pulse counter is 0 (when S1702 is YES), the main CPU 101 updates the value of the symbol position counter (S1703). Specifically, 1 is added when the reel is rotating forward, and 1 is subtracted when the reel is rotating backward.

  Next, the main CPU 101 determines whether or not the value of the symbol position counter is normal (S1704). In S1704, when the main CPU 101 determines that the value of the symbol position counter is normal (when S1704 is YES), the main CPU 101 shifts the processing to S1706.

  The value of the symbol position counter is determined to be normal when the reel rotation direction is a positive rotation and is an integer from 0 to 19. On the other hand, the value of the symbol position counter is determined to be normal when the reel is rotated in the reverse direction and is an integer from 0 to -19.

  On the other hand, when the main CPU 101 determines in S1704 that the value of the symbol position counter is not normal (when S1704 is NO), the main CPU 101 clears the value of the symbol position counter to 0 (S1705).

Next, the main CPU 101 sets an initial value (16) in the pulse counter (S1706), ends the symbol position update process, and calls the caller routine (waiting for constant speed, processing during constant speed, or waiting for stop start position). Return to.
[Stop start position wait processing]
FIG. 130 is an example of a flowchart of the stop start position waiting process in step S1112 of the reel control process shown in FIG. 121 by the main CPU 101.

  First, the main CPU 101 determines whether or not the value of the symbol position counter of the symbol scheduled to stop on the winning line is equal to the value of the scheduled stop position (S1801).

  Here, the symbol position counter is one of the reel control information stored in the reel control data storage area (FIG. 117), and is updated by the symbol position update process (FIG. 129). Further, the planned stop position is stored in the reel control data storage area (FIG. 117) in S720 of the reel stop control process (FIG. 101) in S213 of the main process (FIG. 72).

  In S1801, when the main CPU 101 determines that the value of the symbol position counter is not equal to the value of the scheduled stop position (when S1801 is NO), the main CPU 101 executes symbol position update processing (FIG. 129) (S1803). ), The stop start position waiting process is terminated, and the process proceeds to S1114 (excitation output process) in the reel control process (FIG. 121).

  On the other hand, when the main CPU 101 determines in S1801 that the value of the symbol position counter is equal to the value of the scheduled stop position (if S1801 is YES), the main CPU 101 indicates that the value of the pulse counter indicates stop start. It is determined whether or not (S1802).

  In S1802, when the main CPU 101 determines that the value of the pulse counter is not 17 which means stop start (when S1802 is NO), the main CPU 101 executes symbol position update processing (FIG. 129) (S1803), The stop start position waiting process is terminated, and the process proceeds to S1114 (excitation output process) in the reel control process (FIG. 121).

  On the other hand, when the main CPU 101 determines in S1802 that the value of the pulse counter is 17 which means stop start (when S1802 is YES), the main CPU 101 sets “stopped” in the reel control management information. (S1804). Specifically, the bit corresponding to “stopped” in the reel control information (1 byte) stored in the reel control data storage area on the main RAM 103 is turned on, and the bit corresponding to “waiting for stop start position” is set. Turn off.

  Next, the main CPU 101 determines whether or not the rotation direction of the reel to be processed (any one of the reels 3L, 3C, and 3R) is normal rotation (S1805). In S1805, when the main CPU 101 determines that the rotation direction of the reel to be processed is normal rotation (when S1805 is YES), the main CPU 101 stores the sequence stored in the reel control data storage area on the main RAM 103. A forward rotation stop (for example, “cRESEL_DC”) is set in the data selection index (S1806), the stop start position waiting process is terminated, and the process proceeds to S1114 (excitation output process) in the reel control process (FIG. 121).

On the other hand, when the main CPU 101 determines in S1805 that the rotation direction of the reel to be processed is not normal rotation (when S1805 is NO), the main CPU 101 is stored in the reel control data storage area on the main RAM 103. Reverse rotation stop (for example, “cRESEL_REVBRK”) is set to the sequence data selection index (S1807), the stop start position waiting process is terminated, and the process is changed to S1114 (excitation output process) in the reel control process (FIG. 121). Transfer.
[All-phase OFF processing]
FIG. 131 is an example of a flowchart of the all-phase OFF process in step S1113 of the reel control process shown in FIG. 121 by the main CPU 101.

  First, the main CPU 101 sets “control end” in the reel control management information (S1901).

  Next, the main CPU 101 sets all-phase OFF excitation data (S1902), ends all-phase OFF processing, and shifts the processing to S1114 (excitation output processing) in the reel control processing (FIG. 121).

  Here, the all-phase OFF excitation data is specifically excitation data “00000000B” that does not illustrate both the A phase and the B phase of the stepping motor.

[Excitation output processing]
FIG. 132 is an example of a flowchart of the excitation output process in step S1114 of the reel control process shown in FIG. 121 by the main CPU 101.

  First, the main CPU 101 acquires reel information to be output (S2001).

  Next, the main CPU 101 determines whether or not the excitation data to be output is OFF for all phases (S2002). When the main CPU 101 determines in S2002 that the excitation data to be output is all-phase OFF (when S2002 is YES), the main CPU 101 sets an all-phase OFF pulse (excitation data “00000000B”) ( S2006), the process proceeds to S2007.

  On the other hand, when the main CPU 101 determines in S2002 that the excitation data to be output is not all-phase OFF (when S2002 is NO), the main CPU 101 acquires the pulse code counter of the output target reel (S2003), and the pulse The pulse code of the code counter is updated (S2004), and pulse data is generated from the pulse code (S2005).

  Next, the main CPU 101 stores the pulse data generated in S2005 in the excitation data storage area of the output target reel (S2007).

  As a result of the above processing, in the excitation output processing (FIG. 132), pulse data (excitation data) stored in the excitation data storage area of the output target reel is generated.

<Effect of the present invention>
As described above, in the present embodiment, for example, as shown in FIG. 128, based on the difference between the symbol position of the real reel and the calculation symbol position of the virtual reel, the stepping motors for the reels 3L, 3C, 3R A process for adjusting the input of excitation data is executed in a short cycle. Therefore, according to the gaming machine of the present invention, “the operation as designed in advance can be executed at any timing even if the reel rotation speed is increased or decreased, and at a specific timing. The object of the present application “providing a gaming machine capable of stopping a specific symbol” can be achieved.

[Other effects]
As described above, in this embodiment, as shown in FIG. 116, the capacity of the main ROM 102 is reduced by 28 bytes, which is the difference between the conventional symbol arrangement table (60 bytes) and the compressed symbol table (32 bytes). is made of. Therefore, according to the gaming machine of the present invention, “providing a gaming machine capable of enhancing the gameability by reducing the capacity of data used in processing of the main control circuit and increasing the free capacity of the ROM of the main control circuit. Can achieve the purpose of this application.

  In the above-described embodiment shown in FIG. 116, a table having an effective bit digit number of 4 bytes has been described as an example. However, a table having a space of 1 bit or more (a table having an effective bit digit number of 7 bits or less). ), It is possible to obtain the effect of reducing the ROM capacity. In addition, the effect is so large that it is a table with many empty bits (table with few effective bit digits).

  In the above embodiment, the symbol arrangement table has been described as an example. However, the present invention is not limited to this, and if there are empty bits (for example, data of less than 8 bits is stored in a fixed storage area of 1 byte). For example, various lottery tables (internal winning combination, ART winning, RT transition, etc.), excitation tables used for reel stepping motors, stop data tables, etc. is there.

  Further, in the above embodiment, an example in which the effective bit digit is the lower bit of each byte is described, but the present invention is not limited thereto, and when the effective bit digit is the upper bit of each byte, Alternatively, the case where the effective bit digit is an arbitrary bit digit in each byte (for example, four digits B3 to B6 of B0 to B7) is also included. According to such a configuration, even in a table having positions of various effective bit digits, “the capacity of data used in the processing of the main control circuit is reduced, and the free capacity of the ROM of the main control circuit is increased, thereby increasing the gameability. The object of the present application can be achieved.

  Further, in the embodiment related to the data decompression process, the process of decompressing (inverting) the compressed data to generate control data has been described. However, if the procedure opposite to this process procedure is executed, the original data It goes without saying that can be compressed. For example, by dividing the original data into one or more 8-byte block units, and accumulating the bit data of the effective bit digits of each byte constituting the 8-byte block to assemble the compressed block, the original data is Compressed data can be obtained by compression (transposition). According to this configuration, it is possible to increase the free space in the storage medium to which the compressed data is output.

[Other expandability of gaming machine according to this embodiment]
In the pachislot machine 1 of the present embodiment, a player's medal insertion operation (that is, an operation of inserting a hand-held medal into the medal insertion slot 14 or an operation of inserting a credited medal by operating the MAX bet switch 15a. When the game is started by the operation) and the medals are paid out when the game is finished, the hopper device 51 is driven and the medals are paid out from the medal payout outlet 24 or credited. However, it is not limited to this.

  For example, the present invention is applied to all modes in which a game medium required for a game is inserted by a player, a game is performed based on the game medium, and a privilege is granted (for example, a medal is paid out) based on the game result. be able to. In other words, not only a form in which a game medium is inserted (hanged) by a physical player's action and the game medium is paid out, but also the main control circuit 90 itself electromagnetically manages the game medium held by the player. The game may be possible without a medal. Further, the game media management apparatus that manages (games) the game media that are attached (connected) to the main control circuit 90 may electromagnetically manage the game media owned by the player.

  In this case, the game medium management device has a ROM and an RWM (or RAM) and is provided in the game machine, and is bidirectionally communicated with an external game medium handling device (not shown) via a predetermined interface. The game medium lending operation (that is, the operation for providing the necessary game medium when the player performs the operation of inserting the game medium) or the role relating to the payout of the game medium ( A game medium payout operation (that is, an operation for acquiring a game medium necessary for paying out a game medium to the player) or a game medium to be used for a game when the combination is established) It may be possible to perform an electromagnetic recording operation. The game medium management device not only manages the actual number of game media, but also displays the number of game media held on the front surface of the pachislot 1 based on the management result of the number of game media, for example. A number display device (not shown) may be provided, and the number of game media displayed on the held game media number display device may be managed. In other words, the game medium management device may record and display the total number of game media that the player can use for the game by an electromagnetic method.

  Further, in this case, the game medium management device has a performance that allows a player to freely transmit a signal indicating the number of recorded game media to an external game medium handling device. In addition to the case where the user directly operates, it has a performance that cannot reduce the number of recorded game media, and an external connection terminal board (not shown) is provided between the game media handling device and the outside. It is desirable that the player has a performance that cannot transmit a signal indicating the number of recorded game media unless it is via the external connection terminal board.

  In addition to the above, the gaming machine is provided with a lending operation means that can be operated by the player, a return (settlement) operation means, and an external connection terminal plate. Medium slot (for example, IC card), non-contact communication antenna for depositing electronic money, etc. from a portable terminal, other operation means such as lending operation means, return operation means, game medium handling device side external connection terminal board May be provided (both not shown).

  As a flow of the game at that time, for example, the player deposits the valuable value to the game medium handling device by any method, and subtracts a predetermined number of valuable values based on the operation of any of the lending operation means. Then, the number of game media corresponding to the valuable value subtracted from the game media handling device to the game media management device is increased. Then, the player plays a game and repeats the above operation when a game medium is required. After that, a predetermined number of game media are acquired as a result of the game, and when the game is ended, the game media management device transmits the number of game media to the game media handling device by operating any of the return operation means. The medium handling device discharges the recording medium on which the number of game media is recorded. The game medium management device clears the number of game media stored by itself when the number of game media is transmitted. The player takes the discharged recording medium to a prize counter or the like for exchanging prizes, or moves the gaming table to play a game based on the gaming medium recorded on another table.

  In the above example, all the game media are transmitted to the game media handling device, but the game machine or the game media handling device transmits only the number of game media desired by the player, and the game media possessed by the player It may be divided and processed. In addition to discharging the recording medium, cash or cash equivalents may be discharged or stored in a portable terminal or the like. Further, the game medium handling apparatus may be able to insert a member recording medium in the game hall and store it in the member recording medium so that it can be replayed at a later date.

  In addition, in the gaming machine or the game medium handling device, a lock operation for locking the game medium or the valuable data communication can be performed on the game medium handling device or the game medium management device by operating a predetermined operation means (not shown). It is good. At that time, information that can only be known by the player, such as a one-time password, may be set, or the player may be stored by an imaging means provided in the gaming machine or the game medium handling device.

  Note that this game medium management device may be one that allows games only without medals as described above, or a game medium is inserted (hanged) by a physical player's action, and the game medium is It may be possible to play a game in a payout form, a form that allows a game without medals, or both forms. In this case, the game medium management device can adopt a method of directly controlling the above-mentioned medal sensor (not shown) and the hopper device 51, and these are controlled by the main control circuit 90, and the control is performed. Based on the transmission of the result, it is also possible to adopt a method that enables control that allows the player to record and display the total number of game media that can be used for gaming by an electromagnetic method. it can.

  Further, in the above description, the case where the game medium management device is applied to the pachislot 1 has been described. However, in the slot machine and the enclosed game machine using the above-described game balls, the game medium management device is provided in the same manner, and the player It is also possible to manage the game media.

  As described above, by providing the above-described game medium management device, it is possible to reduce the medal sensors (not shown), the hopper device 51, and the like inside the game machine as compared with the case where the game medium is physically provided for the game. It is possible not only to reduce the cost and manufacturing cost of the gaming machine, but also to prevent the player from directly touching the game medium, improve the gaming environment, reduce noise, and the device This reduces the power consumption of the gaming machine. Also, it is possible to prevent illegal acts through game media and game media slot and payout port. That is, it is possible to provide a gaming machine that can improve various environments surrounding the gaming machine.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information indicator, 11 ... Display apparatus, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial communication circuit, 200 ... Sub control circuit, 201 ... Sub CPU 201, 301 ... first interface board, 302 ... second interface board

Claims (3)

Multiple reels with multiple designs,
Symbol changing means for changing the plurality of symbols by rotating each of the plurality of reels;
A symbol position detecting means for detecting a symbol position;
A symbol position calculating means for calculating a calculation symbol position;
A symbol position difference calculating unit that calculates a difference between the symbol position detected by the symbol position detecting unit and the calculation symbol position calculated by the symbol position calculating unit;
Rotation speed adjustment means for adjusting the rotation speed of the plurality of reels according to the difference calculated by the difference calculation means,
The gaming machine characterized in that the rotational speed adjusting means adjusts the rotational speed of the plurality of reels in a cycle shorter than a cycle in which the plurality of reels make one rotation.   The gaming machine according to claim 1, wherein the rotation speed adjusting means adjusts the rotation speeds of the plurality of reels at a period of less than a predetermined time.   The gaming machine according to claim 1, wherein the symbol position calculating means calculates the calculation symbol position by simulating the reel with software.

Images