JP6611841B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachi-slot, comprising a plurality of reels each having a plurality of symbols provided on the surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as “start operation”) after a game medium such as a medal or coin has been inserted into the gaming machine, and the rotation of all reels is detected. Outputs a signal requesting start. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and a symbol combination (display combination) related to the winning of the winning is displayed, a privilege corresponding to the symbol combination is given to the player. As an example of a privilege granted to a player, a replay (hereinafter also referred to as “replay”) in which an internal lottery process is performed again without paying out game media (medals, etc.) or consuming the game media. An operation of a bonus game in which a game medium payout opportunity increases can be cited.

  Conventionally, in the gaming machine having the above-described configuration, a function of navigating the establishment of a specific small role (a role related to the payout of game media) with a lamp or the like, that is, a function of assist time (hereinafter referred to as “AT”) is provided. Equipped with a game machine. Conventionally, a game machine having a function of operating a gaming state in which a replay winning probability is higher than normal when a specific symbol combination is displayed, that is, a replay time (hereinafter referred to as “RT”) function has also been developed. Has been. Further, a pachislot having a function of assist replay time (hereinafter referred to as “ART”) in which AT and RT operate simultaneously has been developed.

  The above-mentioned gaming machine is usually equipped with a main control circuit in which a circuit (main control circuit) for controlling the main gaming operation of the gaming machine such as determination of an internal winning combination, rotation and stop of each reel, determination of presence / absence of winning is implemented. A board and a sub-control board on which a circuit (sub-control circuit) for controlling a rendering operation by displaying an image or the like is mounted. The game operation is controlled by a CPU (Central Processing Unit) mounted on the main control circuit. At this time, under the control of the CPU, the program and various table data stored in the ROM (Read Only Memory) of the main control circuit are expanded in the RAM (Random Access Memory) of the main control circuit, and processing related to various game operations is executed. Is done.

  Conventionally, in the gaming machine having the above-described configuration, a gaming machine that obtains a checksum of data stored in the RAM at the time of power interruption and performs a checksum determination process obtained at the time of power interruption at power recovery is known. (For example, refer to Patent Document 1). In the gaming machine of Patent Document 1, in the checksum determination process at the time of power restoration, an error notification is performed when the checksum obtained at the time of power restoration does not match the checksum obtained at the time of power interruption.

JP 2009-011375 A

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and there is a demand for capacity reduction of processing programs and tables other than the game management managed by the main control circuit.

  The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce the capacity of processing programs and tables other than the game management managed by the main control circuit and to reduce the capacity of the ROM of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity and enhancing the playability by using the free space in the ROM for the increased capacity.

  In order to solve the above problems, the present invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, a main CPU 101 described later) for performing arithmetic processing for controlling the game operation;
Storage means (for example, main RAM 103 described later) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means;
Power supply means for supplying a power supply voltage (for example, a power supply substrate 53b and a switching regulator 94 described later);
Starting means for outputting a starting signal to the arithmetic processing means when the power supply voltage exceeds a predetermined starting voltage value (for example, 10V) (for example, reset signal output processing of the power management circuit 93 described later) and,
A watchdog timer (for example, WDT described later) capable of outputting a reset signal to the arithmetic processing means when the clear information is not written for a predetermined time or more ,
The arithmetic processing means includes:
A group of registers including a main register, a sub register and a stack pointer;
When the activation means outputs the activation signal, it is stored in a predetermined storage area (for example, a gaming RAM area described later) from the sum value generated at the time of the most recent power interruption. Sum value subtracting means for sequentially subtracting information (for example, S122 to S131 during sum check processing described later),
The main register is 1 and byte of the accumulator, a flag register for execution result of the operation instruction is reflected, 1 byte first pair register and a second pair register general purpose register Ru can be used in two sets of And
The flag register has a zero flag that is set to an ON state when a subtraction instruction is executed and the execution result is 0,
The sum value subtracting means includes:
An address corresponding to the predetermined storage area in the storage means for starting subtraction is set in the stack pointer, and the number of subtraction executions is set in a counter (for example, a sum calculation counter described later) provided in the storage means And the sum value stored in the sum value storage area in the storage means is set in the first pair register,
When the subtraction is started, the address stored in the stack pointer is updated in the direction of addition, and the dedicated instruction for storing the information stored in the address before update in the second pair register is executed, and Executes a subtraction instruction (for example, a SUB instruction described later) that subtracts the value stored in the second pair register from the value stored in the first pair register and stores the subtraction result in the first pair register. The process to be performed is repeatedly executed for the number of executions of the subtraction,
The arithmetic processing means includes:
When it is determined that the writing confirmation to the storage means is normal, the arithmetic processing by the sum value subtracting means is executed,
If the ON state is not set in the zero flag when the arithmetic processing by the sum value subtracting unit is completed, it is determined that the sum value stored in the sum value storage area is abnormal, and then the watch Executes an infinite loop process that repeats writing the clear information to the dog timer ,
If the zero flag is set to ON when the arithmetic processing by the sum value subtracting unit is completed, it is determined that the sum value stored in the sum value storage area is normal, and then the most recent A game machine that returns to the game before the occurrence of the power interruption.

  According to the gaming machine of the present invention configured as described above, the capacity of processing programs and tables other than the game management managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit. It is possible to provide a gaming machine that can improve the gameability by using the free area of the ROM.

It is a figure for demonstrating the function flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows schematic structure of the various display screens displayed on the sub display apparatus of one Embodiment of this invention. It is a figure which shows the example of a transition of the display screen of the sub display apparatus in one Embodiment of this invention. It is a block diagram which shows the whole circuit structure with which the game machine of one Embodiment of this invention is provided. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub control circuit in one Embodiment of this invention. It is a block diagram of the various registers | resistors which the main CPU in one Embodiment of this invention has. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the bonus state and non-bonus state of a pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the game state between the ART game state of a pachislot in one Embodiment of this invention, a non-ART game state, and a bonus state. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and stop symbol combination in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and stop symbol combination in one Embodiment of this invention. It is a figure which shows an example of the reel stop initial setting table in one Embodiment of this invention. It is a figure which shows an example of the drawing priority order table in one Embodiment of this invention. It is a figure which shows the structure (the 1) of the winning request flag storage area | region and winning operation flag storage area | region in one Embodiment of this invention. It is a figure which shows the structure (the 2) of the winning request flag storage area | region and winning operation flag storage area | region in one Embodiment of this invention. It is a figure which shows (the 3) of the winning request flag storage area | region and the winning action flag storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the carryover combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation | movement stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the corresponding table (the 1) with the internal winning combination and subflag in one Embodiment of this invention. It is a figure which shows the corresponding table (the 2) with the internal winning combination and subflag in one Embodiment of this invention. It is a figure for demonstrating alerting | reporting operation | movement when subflag EX "triple chili lip" or "reach eye lip" wins in the gaming machine of one embodiment of the present invention. It is a figure for demonstrating the flow of the game in the general game state in one Embodiment of this invention. It is a figure which shows an example of the normal medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ lottery table in one Embodiment of this invention. It is a figure which shows an example of the mode up lottery table in CZ1 in one Embodiment of this invention. It is a figure which shows an example of the point lottery table in CZ2 in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ1, CZ2) in CZ in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ3) in CZ in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in normal ART in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table during ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART medium high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of CT lottery table during ART in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table during normal ART in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in CT state in one Embodiment of this invention. It is a figure which shows an example of the table lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table during CT in one Embodiment of this invention. It is a figure which shows an example of the lot number table on the number of sets in CT in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the bonus state in one Embodiment of this invention. It is a figure which shows an example of the bonus classification lottery table in one Embodiment of this invention. It is a figure which shows an example of the lottery table on the number of bonus ART games in one Embodiment of this invention. It is a figure which shows an example of CT lottery table at the time of bonus end in one Embodiment of this invention. It is a figure for demonstrating the flow of the game (others) in the general game state in one Embodiment of this invention. It is a figure which shows an example of the non-ART flag conversion lottery table in one Embodiment of this invention. It is a figure which shows the correspondence of the main side navigation data and sub side navigation data in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of power-on (reset interruption) performed by the main control circuit of the gaming machine in one embodiment of the present invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the process at the time of power-on in one Embodiment of this invention. It is a flowchart which shows the example of the game return process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the game return process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command production | generation storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the setting change command production | generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of a power failure (external) in one Embodiment of this invention. It is a flowchart which shows the example of the checksum production | generation process (non-regulation) in one Embodiment of this invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to an embodiment of the present invention, and an operation of updating a stack pointer and an operation of reading data from a register executed in the checksum generation process FIG. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the sum check process in one Embodiment of this invention. It is a flowchart which shows the example of the main process (main operation process) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of a medal reception and start check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error process in one Embodiment of this invention. It is a figure which shows an example of a structure of the error table actually referred on the source program of the error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the internal lottery process in one Embodiment of this invention. It is a figure which shows an example of a structure of the internal lottery table (for general games) actually referred on the source program of the internal lottery process in one Embodiment of this invention. It is a figure which shows an example of the structure of the lottery value selection table classified by RT state actually referred on the source program of the internal lottery process in one Embodiment of this invention. The internal lottery value table selection table, the 1-byte internal lottery value table, the 2-byte internal lottery value table, and the 1-byte internal lottery value that are actually referred to on the internal lottery processing source program in the embodiment of the present invention It is a figure which shows an example of a structure of a table and the internal lottery value table classified by 2 bytes. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a figure which shows a response | compatibility with the special prize (bonus) winning number and small winning combination number, and internal winning combination in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the symbol setting process in one Embodiment of this invention. It is a figure which shows an example of a structure of the hit request flag table actually referred on the source program of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compression data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board control process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board output process in one Embodiment of this invention. It is a flowchart which shows the example of the control process classified by state in one Embodiment of this invention. It is a flowchart which shows the example of the subflag conversion process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the subflag conversion process in one Embodiment of this invention. It is a figure which shows an example of a structure of the subflag conversion table actually referred on the source program of the subflag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the navigation set process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the navigation set process in one Embodiment of this invention. It is a figure which shows an example of a structure of the navigation data table actually referred on the source program of the navigation set process in one Embodiment of this invention. It is a flowchart which shows the example of the flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of a normal start in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of the start in CZ in one Embodiment of this invention. It is a flowchart which shows the example of the process in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the process in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the process in CZ3 in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of start in normal ART in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of CT start in one Embodiment of this invention. It is a flowchart which shows the example of CT lottery processing in CT in one Embodiment of this invention. It is a flowchart which shows the example of the table data acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the table data acquisition process in one Embodiment of this invention. It is a figure which shows an example of a structure of CT lottery table in CT actually referred on the source program of the table data acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the 1 byte lottery process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the 1 byte lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of BB start in one Embodiment of this invention. It is a flowchart which shows the example of the attraction | saving priority order storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the drawing priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the symbol code acquisition process in one Embodiment of this invention. On the source program of the symbol code acquisition process in one embodiment of the present invention, the first reference (left reel) symbol arrangement table that is actually referred to, and the symbol reference that is referred to when the first drum symbol arrangement table is set It is a figure which shows an example of a structure of a winning action table. On the source program of the symbol code acquisition process according to one embodiment of the present invention, the second drum (medium reel) symbol arrangement table that is actually referred to and the symbol reference that is referred to when the second drum symbol arrangement table is set It is a figure which shows an example of a structure of a winning action table. On the source program of the symbol code acquisition process in one embodiment of the present invention, the third cylinder (right reel) symbol arrangement table that is actually referred to and the symbol reference that is referred to when the third cylinder symbol arrangement table is set It is a figure which shows an example of a structure of a winning action table. It is a flowchart which shows the example of the AND operation process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the drawing priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of a structure of the drawing priority order table actually referred on the source program of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the reel stop control process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the reel stop control process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal OFF process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal ON process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the non-regulation port output process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the non-regulated port output process in one Embodiment of this invention. It is a flowchart which shows the example of the winning search process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the winning search process in one Embodiment of this invention. It is a figure which shows an example of a structure of the payout number data table actually referred on the source program of the winning search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of a prize check and medal payout process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of a prize check and medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the BB check process in one Embodiment of this invention. It is a flowchart which shows the example of the RT check process in one Embodiment of this invention. It is a flowchart which shows the example of the RT check process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of CZ * ART completion | finish in one Embodiment of this invention. It is a flowchart which shows the example of the interruption process performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment LED drive processing in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the 7 segment LED drive process in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of 7 segment display data generation process in one Embodiment of this invention. It is a figure which shows an example of a structure of the 7 segment cathode table actually referred on the source program of the 7 segment display data generation process in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flowchart which shows the example of the trial test signal control process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the rotation brake signal generation process in one Embodiment of this invention. It is a flowchart which shows the example of the special prize signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the condition apparatus signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the condition apparatus signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the sub side navigation control process performed by the sub control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the player registration process in one Embodiment of this invention. It is a flowchart which shows the example of the log | history management process in one Embodiment of this invention. It is a figure which shows the flow of the game in CT precursor in the modification 1 of this invention. It is a figure which shows the correspondence of the internal winning combination and stop symbol combination in the modification 2 of this invention. It is a figure which shows the correspondence of the main side navigation data and sub side navigation data in the modification 3 of this invention. It is a figure which shows the correspondence of the pushing order in the modification 5 of this invention, and a locked state.

  Hereinafter, a pachislot machine is taken as an example of a gaming machine according to an embodiment of the present invention, and its configuration and operation will be described with reference to the drawings. In the present embodiment, a pachislot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot will be described with reference to FIG. In the pachislot machine of this embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as game media.

  When a player inserts a medal into the pachislot and operates the start lever, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is one of various processing means (processing functions) provided in a main control circuit described later. By determining the internal winning combination, a combination of symbols that permits display along an after-mentioned effective line (winning determination line) is determined. The types of symbol combinations include those related to “winning” in which benefits such as payout of medals, replay (replay) operation, bonus operation, etc. are given to the player, and so-called “out of” other than that. Such a thing is provided. In the following, a combination relating to the payout of medals is referred to as a “small combination”, and a combination relating to replay (replay) operation is referred to as a “replay combination”. In addition, a combination related to a bonus operation (bonus game) is also referred to as a “bonus combination”.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is one of various processing means (processing functions) provided in a main control circuit described later.

  In the pachi-slot, basically, control for stopping the rotation of the corresponding reel is performed within a specified time (190 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. In the present embodiment, when the specified period is 190 msec, the maximum number of sliding symbols (maximum number of sliding symbols) is determined for four symbols.

  The reel stop control means, when the internal winning combination permitting the symbol combination display related to the winning is determined, normally, the symbol combination is placed on the active line within a specified time of 190 msec (four symbols). The rotation of the reel is stopped so as to display as much as possible. In addition, the reel stop control means stops the rotation of the reel using a specified time so that the combination of symbols that are not permitted to be displayed by the internal winning combination is not displayed along the active line.

  In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the active line relates to winning. This winning determination means is also one of various processing means (processing functions) provided in the main control circuit described later. Then, when the combination of the displayed symbols is determined to be related to winning by the winning determination means, a bonus such as a medal payout is given to the player. In the pachislot, a series of flows as described above is performed as one game (unit game).

  Also, in the pachislot, in the series of gaming operations described above, various effects can be achieved by displaying images on a display device, outputting light from various lamps, outputting sound from a speaker, or a combination thereof. Is done.

  Specifically, when the start lever is operated, a random number value for presentation is extracted separately from the random number value used for determining the internal winning combination described above. When the effect random number is extracted, the effect content determination means determines the effect to be executed this time from lots of effect contents associated with the internal winning combination by lottery. This effect content determination means is one of various processing means (processing functions) provided in a sub-control circuit described later.

  Next, when the content of the effect is determined by the effect content determination means, the effect execution means responds in conjunction with each opportunity such as when the rotation of the reel starts, when the rotation of each reel stops, or when the presence or absence of a prize is determined. Execute. In this way, in the pachislot, for example, by executing the production contents associated with the internal winning combination, there is an opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) It is provided to the player and the player's interest can be improved.

<Pachislot structure>
Next, the structure of a pachislot machine according to an embodiment of the present invention will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachislot 1 includes an exterior body (game machine main body) 2. The exterior body 2 includes a cabinet 2a that houses a reel, a circuit board, and the like, and a front door 2b that is attached so that the opening of the cabinet 2a can be opened and closed.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display columns) are provided in a horizontal row. Hereinafter, the reels 3L, 3C, and 3R (main reels) are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (reel rotation direction).

  The front door 2 b includes a door body 9, a front panel 10, a waist panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachi-slot 1.

  The front panel 10 is provided on the upper portion of the door body 9. The front panel 10 is constituted by a frame-like member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is disposed to face a display device 11 described later disposed inside the cabinet 2a.

  The display device cover 30 is formed of a black translucent synthetic resin. Therefore, the player can visually recognize the video (image) displayed on the display device 11 described later via the display device cover 30. In the present embodiment, the display device cover 30 is formed of a black translucent synthetic resin, thereby suppressing the entry of external light into the cabinet 2a and the image (image) displayed by the display device 11. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21 a and 21 b provided on the upper portion of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is configured by an LED (Light Emitting Diode) or the like (refer to an LED group 85 in FIG. 7 described later), and turns on and off the light in a pattern corresponding to the contents of effects.

  The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 includes a decorative panel on which an arbitrary image is drawn, and a light source (LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal portion 13 is provided between the front panel 10 and the waist panel 12. The pedestal 13 includes a symbol display area 4 and various devices (medal slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, three stop buttons 17L, 17C, and the like to be operated by the player. 17R, a settlement button (not shown), and the like.

  The symbol display area 4 is an area that overlaps with the three reels 3L, 3C, and 3R when viewed from the front, and is arranged at a position closer to the player than the three reels 3L, 3C, and 3R. 3L, 3C, 3R has a size that enables visual recognition. The symbol display area 4 functions as a display window, and is configured so that each reel 3L, 3C, 3R provided behind the display window 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the rotation of the three reels 3L, 3C, and 3R provided behind the reel display window 4 is stopped, the reel display window 4 is continuously arranged among a plurality of symbols provided on the peripheral surface of each reel. Two symbols are displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, one symbol (three in total) is provided in each of the upper, middle and lower regions for each reel in the frame of the reel display window 4. ) Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). In the present embodiment, a pseudo line (center line) connecting the middle stage area of the left reel 3L, the middle stage area of the middle reel 3C, and the middle stage area of the right reel 3R within the frame of the reel display window 4, It is defined as an effective line for determining whether or not a prize is won.

  The reel display window 4 is formed by an opening of a frame member 31 provided on the pedestal portion 13. A substantially horizontal plane base region is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, a medal slot 14 is provided on the right side of the pedestal area, and a MAX bet button 15a and a 1 bet button 15b are provided on the left side.

  The medal slot 14 is provided to accept a medal dropped on the pachislot 1 from the outside by the player. The medals accepted from the medal slot 14 are used for one game up to a predetermined number (for example, three) set in advance, and the number of medals exceeding the predetermined number are deposited inside the pachislot 1. (So-called credit function (game medium storage means)).

  The MAX bet button 15a and the 1 bet button 15b are provided for determining the number of coins used for one game from medals deposited in the cabinet 2a. Note that a bet button LED (not shown) that is lit when a medal can be inserted is provided inside the MAX bet button 15a. The checkout button is provided to draw out (discharge) medals deposited inside the pachislot machine 1 to the outside.

  When the player depresses the MAX bet button 15a, medals corresponding to the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, each time the 1-bet button 15b is pressed, one medal is inserted. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the active line is activated.

  Hereinafter, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting a medal into the medal insertion slot 14 (operation of inserting a medal for playing a game) are all referred to as “insertion operation”.

  The start lever 16 is provided to start rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  In addition, an information display 6 is provided in the approximate center of the pedestal region on a substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

  The information display 6 has a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player as a privilege (hereinafter referred to as “paid-out number”). (Hereinafter referred to as “7-segment LED”) and information such as the number of medals deposited inside the pachislot machine 1 (hereinafter referred to as “credit number”) for digital display (notification) to the player A 2-digit 7-segment LED is provided. In this embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) information about the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of paid-out medals is switched from the display mode of the paid-out number to the display mode of the error type information.

  Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on a stop operation necessary for displaying a symbol combination corresponding to the combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a 2-digit 7-segment LED. The instruction monitor informs the player of necessary stop operation information by turning on, blinking, or turning off the 2-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. To do.

  Note that the aspect uniquely corresponding to the information of the stop operation to be notified here is, for example, in the case of informing the pressing order “1st (perform the first stop operation on the left reel 3L)”. When the numerical value “1” is displayed on the instruction monitor and the push order “2nd (perform the first stop operation on the middle reel 3C)” is notified, the numerical value “2” is displayed on the instruction monitor and the push order In a case where “3rd (perform the first stop operation on the right reel 3R)” is notified, a numerical value “3” is displayed on the instruction monitor. It should be noted that the notification mode of the stop operation information in the instruction monitor (navigation data determined on the main side described later) will be described in detail later with reference to FIG. 63 described later.

  The information display 6 is electrically connected to the main control board 71 via a door relay board 68 and a game operation display board 81 as shown in FIG. 7 described later. The display operation of the information display 6 is controlled by the main control board. It is controlled by a later-described main control circuit 90 in the substrate 71. Moreover, the control method of the various 7-segment LEDs described above is dynamic lighting control.

  In the pachislot machine 1 of this embodiment, in addition to the instruction monitor controlled by the main control board 71, a configuration for notifying the stop operation information using other means controlled by the sub control board 72 is provided. Specifically, information on a stop operation is notified by a display device 11 described later configured by a projector mechanism 211 and a display unit 212 (see FIG. 3 and FIG. 7 described later).

  When such a configuration is applied, the notification mode in the instruction monitor and the notification mode in other means controlled by the sub-control board 72 may be different from each other. That is, the instruction monitor may be notified in a manner that uniquely corresponds to the information on the stop operation to be notified, and does not necessarily need to notify the information on the stop operation directly (for example, the numerical value “1” in the instruction monitor). Even if is displayed, there is a possibility that the notification content cannot be specified depending on the player, which is not a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, information on the stop operation may be directly notified. For example, when the push order “1st” is notified, the instruction monitor displays a numerical value “1” that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11) displays the left reel 3L. The instruction information for performing the first stop operation may be directly notified.

  In the pachislot machine 1 configured as described above, not only the control of the sub-control board 72 but also the control of the main control board 71 can notify information on necessary stop operation according to the internal winning combination. In addition, the presence / absence of notification of such stop operation information may be controlled according to the gaming state. For example, the stop operation information may be notified in the later-described ART game state (see FIG. 14 described later) without notifying the stop operation information in the later-described general game state (non-ART game state).

  Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand substantially vertically from a pedestal region in a substantially horizontal plane of the pedestal portion 13 in the front portion of the door body 9. The sub display device 18 includes a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various types of information.

  A touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates in accordance with a predetermined operation principle such as a capacitance method, and when a player's operation is accepted, outputs a signal corresponding to the operation as touch input information. The pachislot machine 1 according to the present embodiment has a function that allows the display of the sub display device 18 to be switched in accordance with the player's operation received via the touch sensor 19 (touch input information output from the touch sensor 19). Have The sub display device 18 is controlled by a later-described sub control board 72 (see FIG. 7 described later) based on touch input information output from the touch sensor 19.

  In the lower part of the door body 9, a medal payout opening 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout port 24 guides medals discharged by driving a medal payout device 51 described later to the outside. The medal tray 25 stores medals discharged from the medal payout opening 24. Sounds such as sound effects and music corresponding to the contents of the effects are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the back side of the front door 2b.

  As shown in FIG. 3, the cabinet 2a includes a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. And the display apparatus 11 is arrange | positioned in the upper part in the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection member 212a onto which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, in the display device 11, image light is generated based on the position (projection distance, angle, etc.) and shape of the projection member 212a that is a three-dimensional object, and the image light is projected by the projector mechanism 211 to the projection member. Projected onto the surface of 212a. By providing such an effect function, an advanced and powerful effect can be performed. Although not shown in FIG. 3, another projected member with a curved display surface is provided on the back side of the box-shaped projected member 212 a, and either one of the projected members is provided depending on the gaming state. Used as a screen on which image light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the projection target member in accordance with the gaming state.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are disposed in the lower part of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 can store a large amount of medals and can discharge them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds 50, for example, or when the settlement button is pressed and settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

  The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 includes a power switch 53a and a power supply board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device (not shown) into the power of the DC voltage necessary for each part, and supplies the converted power to each part.

  Further, a sub control board case 57 that houses a sub control board 72 (see FIG. 7 described later) is disposed above the power supply device 53 in the cabinet 2a. A sub control circuit 72 (see FIG. 10 described later), which will be described later, is mounted on the sub control board 72 accommodated in the sub control board case 57. The sub-control circuit 200 is a circuit that controls the execution of effects by displaying images. A specific configuration of the sub control circuit 200 will be described later.

  A sub-relay board 61 is disposed above the sub-control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which wiring for connecting the sub control board 72 and a main control board 71 described later is mounted. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72, a board disposed around the sub-control board 72, various devices (units), and the like is mounted.

  Although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7 described later) is disposed in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a game medal auxiliary storage switch 77 (see FIG. 7 described later), and a medal payout count switch (not shown). Is a relay board on which wiring for connecting is mounted.

  As shown in FIG. 4, a middle door 41 is disposed at the center of the rear side of the front door 2b, and the reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, and 3R are attached to the reel display window 4 side of the middle door 41, and main control is performed on the opposite side of the middle door 41 from the reel display window 4 side. A main control board case 55 in which a board 71 (see FIG. 7 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R through gears having a predetermined reduction ratio.

  The main control board 71 accommodated in the main control board case 55 has a main control circuit 90 (see FIG. 9 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of each of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. . In the present embodiment, the main control circuit 90 also performs control such as lottery processing for determining whether ART is determined, processing for displaying navigation information on an instruction monitor, and processing for transmitting various test signals. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back side of the front door 2b. The speakers 65L and 65R are disposed at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

  A selector 66 and a door open / close monitoring switch 67 are disposed above the speaker 65L. The selector 66 is a device for selecting whether or not the medal material and shape are appropriate, and guides the appropriate medal inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that an appropriate medal has passed is provided on the path through which the medal passes in the selector 66.

  The door open / close monitoring switch 67 is disposed diagonally to the left of the selector 66 when the front door 2b is viewed from the back side. The door opening / closing monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachislot 1.

  Although not shown in FIG. 4, a door relay terminal plate 68 is disposed in the area where the front door 2 b is opened and closed by the middle door 41 on the back surface and below the reel display window 4 (see below). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub-relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, This is a relay board on which wiring for connecting each of the second interface boards 302 for the testing machine is mounted. Examples of the various buttons and switches include a MAX bet button 15a, a 1 bet button 15b, a door open / close monitoring switch 67, a BET switch 77 described later, a start switch 79, and the like.

<Display example of sub display device>
Here, various display screens displayed on the sub display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18. FIG.

  Various display screens are displayed on the sub display device 18 by a player's touch operation. As shown in FIGS. 5A to 5E, various display screens including a top screen 221, a menu screen 222, and game information screens 223, 224, and 225 are displayed. The display screen is displayed. These display screens are switched based on the player's operation signal received via the touch sensor 19.

  The top screen 221 is an initial screen among the display screens displayed on the sub display device 18, and on the top screen 221, a “MENU” button 221a and a summary game history 221b are displayed. The “MENU” button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B. When a predetermined operation (for example, tapping) is performed by the player on the “MENU” button 221a, the menu screen 222 is called. It is. On the top screen 221, a part of the game history (outline game history) of the pachislot 1 is displayed as the summary game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the summary game history 221b.

  The menu screen 222 is a screen that displays a menu that can be displayed on the sub display device 18. In the menu screen 222, a "return" button 222a, a "registration" button 222b, an "explanation" button 222c, and an "array payout" button 222d. , A “reach eye” button 222e, a “WEB site” button 222f, and a “volume” button 222g are displayed. The “return” button 222a is an operation button for calling the top screen 221. When the player performs an operation on the “return” button 222a, the top screen 221 is called. The “Register” button 222b to “Volume” button 222g are operation buttons for calling up the display screen of the corresponding menu contents. When the player performs an operation on each button, the corresponding menu contents are displayed. The display screen is called up.

  For example, when the “Register” button 222 b is operated by the player on the menu screen 222, a registration screen (not shown) for registering the player who is playing the game is called up on the display screen of the sub display device 18. In recent pachislot machines, a service is widely used in which a player is registered for each model and various information such as the achievement status of a defined mission is managed based on the player's previous game history. The registration screen called by the “registration” button 222b is a display screen for registering a player when receiving the provision of this service.

  For example, when the “explain” button 222 c is operated by the player on the menu screen 222, an explanation screen (not shown) of the pachislot 1 is called up on the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, explanation of the specifications of the pachislot 1 such as a bonus winning probability and ART winning probability for each set value, and an introduction explanation of characters appearing in the production of the pachislot 1.

  For example, when the “array payout” button 222 d is operated by the player on the menu screen 222, the array payout screen (not shown) of the pachislot 1 is called on the display screen of the sub display device 18. On the array payout screen, for example, the correspondence (payout table) between the combination of symbols determined to win in the pachislot 1 and the privilege when determined to be a win, and the reels 3L, 3C, and 3R are drawn. A symbol row (reel arrangement) or the like is displayed.

  For example, when the “reach eye” button 222 e is operated by the player on the menu screen 222, the reach eye screen (not shown) of the pachi-slot 1 is called to the display screen of the sub display device 18. On the reach eye screen, information on a symbol combination called “reach eye” set in the pachi-slot 1 is displayed. The symbol combination called “reach eyes” is a symbol combination to which a special privilege is given when the symbol combination is displayed along the active line. In the pachi-slot 1 of this embodiment, the symbol combination described later is provided. 28 to 30 corresponds to the symbol combination corresponding to the abbreviation “reach eye lip” shown in the content column of the winning action flag storage area. In the present embodiment, when the symbol combination related to the “reach eye lip” is displayed along the active line, a state advantageous for the player (for example, bonus state, normal ART or CT (see FIG. 14 described later)). See)) is confirmed.

  Further, for example, when the “WEB site” button 222 f is operated by the player on the menu screen 222, the WEB introduction screen (not shown) of the pachislot 1 is called up on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating a URL of an arbitrary WEB site such as a special WEB site provided for each model of the pachislot 1 or a WEB site of the manufacturer of the pachislot 1 Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

  Further, for example, when the “volume” button 222g is operated by the player on the menu screen 222, a volume adjustment screen (not shown) capable of adjusting the volume of the sound output from the speakers 65L and 65R is displayed on the sub display device. Called 18 display screen. The player can adjust the volume of the effect sound of the pachislot 1 via the volume adjustment screen.

  Since the sub display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212) described above, it can be controlled separately from the display device 11. Therefore, in the pachislot machine 1 of the present embodiment, the display screen of the sub display device 18 can be switched by the player's operation even during the game (during execution of the effect by the display device 11). As a result, for example, when the player wants to know the character appearing in the presentation on the display device 11, the player operates the “explain” button 222 c to call the explanation screen, thereby It is possible to grasp information such as the relationship of the game during the game. Also, for example, if a player wants to grasp the symbol that should be used as a guideline for winning a rare role during reel rotation when a so-called `` rare role '' is won during a game, By operating the “array payout” button 222d to call the array payout screen, the reel arrangement can be grasped.

  The game information screens 223, 224, and 225 are display screens that display detailed game history information including a summary game history displayed on the top screen 221 of the game history of the pachislot 1.

  On the game information screen 223, a “return” button 223a, a “MENU” button 223b, a “previous” button 223c, a “next” button 223d, and a game history 223e are displayed. The “return” button 223a and the “MENU” button 223b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 223c and the “Next” button 223d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 223c is operated by the player, the display screen Is switched from the game information screen 223 to the game information screen 225, and when the “next” button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. As the game history 223e, as shown in FIG. 5C, the number of games (number of games), the number of bonuses, the number of ARTs, and the number of CZ (chance zone) are displayed.

  On the game information screen 224, a “return” button 224a, a “MENU” button 224b, a “previous” button 224c, a “next” button 224d, and a game history 214e are displayed. The “return” button 224a and the “MENU” button 224b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 224c and the “Next” button 224d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 224c is operated by the player, the display screen is changed to the game. When the information screen 224 is switched to the game information screen 223 and the “next” button 224 d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as the game history 224e, the number of rushes and the number of successes of CZ (chance zone) described later are displayed. As will be described later, in this embodiment, three types of CZs CZ1, CZ2, and CZ3 are provided as CZ. Therefore, as the game history 224e, as shown in FIG. 5D, the number of rushes and the number of successes of CZ1 to CZ3 are displayed.

  On the game information screen 225, a “return” button 225a, a “MENU” button 225b, a “previous” button 225c, a “next” button 225d, and a game history 225e are displayed. The “return” button 225a and the “MENU” button 225b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 225c and the “Next” button 225d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the “next” button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as the game history 225e, as shown in FIG. 5E, the number of wins of the small combination and the winning probability (the fraction in which the numerator is 1) are displayed.

  In addition, as a switching method of the display screen displayed on the sub display device 18, for example, a switching method based on a tap operation on an operation button displayed on each display screen may be employed. You may employ | adopt the method of switching based on the swipe operation with respect to a display screen.

<Various display screen switching functions of the sub display device>
Next, various display screen switching functions of the sub display device 18 in the pachi-slot 1 of the present embodiment will be described.

[Transition example of the display screen of the sub display device]
First, with reference to FIG. 6A and 6B, the transition example (switching aspect) of the display screen of the sub display apparatus 18 in the pachislot 1 of this embodiment is demonstrated. 6A is a diagram showing an example of transition of the display screen of the sub display device 18 in a situation where the player registration state is not set, and FIG. 6B is a sub display in a situation where the player registration state is set. FIG. 10 is a diagram illustrating a transition example of a display screen of the device 18.

  In the situation where the player registration state is not set, the display screen of the sub display device 18 transitions between the top screen 221 and the menu screen 222 and from the menu screen 222 and the menu screen 222 as shown in FIG. 6A. Transition is possible only between various possible display screens, and transition between these display screens is controlled by a sub control board 72 (sub CPU 201 described later). For example, the sub-control board 72 is connected between the top screen 221 and the menu screen 222 based on a touch operation acquired via the touch sensor 19 (for example, a tap operation on a predetermined button or a swipe operation on the display screen). Switch the display screen. However, in a situation where the player registration state is not set, the sub-control board 72 performs control so that the display of the game information screens 223, 224, 225 is impossible. That is, in a situation where the player registration state is not set, the player cannot display the game information screens 223, 224, 225 on the sub display device 18.

  On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and between the menu screen 222 and the menu screen 222. In addition to the various display screens that can be shifted from, the transition between the menu screen 222 and the game information screens 223, 224, and 225 is also possible. CPU201). In other words, the sub-control board 72 is configured not only between the top screen 221 and the menu screen 222 but also on each of the top screen 221 and the menu screen 222 based on the touch operation acquired via the touch sensor 19 and the game information screen. The display screen can also be switched between 223, 224 and 225. Therefore, in this embodiment, when the player registration state is set, the player can display the game information screens 223, 224, and 225 on the sub display device 18.

  As shown in FIG. 6B, the display screen transition order among the top screen 221, the menu screen 222, and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, it may be configured such that the top screen 221 can directly transition to the game information screens 223, 224, 225, or the game information screens 223, 224, 225 can be changed only from the top screen 221 via the menu screen 222. You may make it the structure which can be changed.

  In the pachi-slot 1 of the present embodiment, a configuration that allows transition from the top screen 221 to the game information screens 223, 224, and 225 only via the menu screen 222 (configuration that cannot transition directly from the top screen 221 to the game information screens 223, 224, and 225) ) Is adopted. In the pachi-slot 1 of the present embodiment, when the player performs a swipe operation (not a menu selection operation) on the display screen on the menu screen 222, the display screen is changed from the menu screen 222 to the game information screen 223. , 224, 225.

  In the present embodiment, the game information screens 223, 224, and 225 are display screens provided completely independently of the menu screen 222. That is, in the pachislot machine 1 of the present embodiment, information indicating a game result that a player has a strong interest in the game, such as a game history, is independent as information that is not related to a game result such as a payout arrangement or volume control. And display. In the present embodiment, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222 in a situation where the player registration state is set. . Therefore, in this embodiment, when the player registration state is set, it is possible to easily access the information game history information desired by the player.

  In the present embodiment, the menu selection operation on the menu screen 222 cannot change the display screen to the game information screens 223, 224, and 225, and the swipe operation (specified in the menu display) is performed on the menu screen 222. If no operation is performed, the display screen cannot be changed to the game information screens 223, 224, 225. Therefore, in the pachi-slot 1 of the present embodiment, the swipe operation for changing the display screen to the game information screens 223, 224, 225 can be handled as a hidden command in the situation where the player registration state is set. In this case, since the player can see more detailed game history information that cannot be seen by other players with little knowledge due to his / her own knowledge of the pachislot 1, than the other players. The game can be advantageously performed, and as a result, it can be expected that the player actively plays the game.

[Display switching function from game information screen to top screen]
The pachi-slot 1 of the present embodiment has a function of changing the display screen of the sub display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in this embodiment, when the “return” button is operated on the game information screens 223, 224, 225, the display screen transitions from the game information screens 223, 224, 225 to the top screen 221 (manual transition). function). In the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, and 225 are displayed, the display screen automatically changes to the top screen 221 regardless of the player's operation. Transition (automatic transition function).

  More specifically, in the pachi-slot 1, in the state where the game information screens 223, 224, and 225 are displayed, the insertion operation (the operation to the MAX bet button 15a, the operation to the 1 bet button 15b and the medal insertion slot 14). When a medal insertion operation is performed, the display screen of the sub display device 18 automatically transitions to the top screen 221. In the gaming state (high lip state) where the probability that a replay role is determined as an internal winning combination is high, such as the ART gaming state, medals are automatically inserted due to the replaying action associated with the replay winning combination. As a result, in the high lip state, the opportunity to display the game information screens 223, 224, 225 may be limited. Therefore, in the pachi-slot 1 of the present embodiment, when a medal is automatically inserted by the re-game operation, the display screen is automatically displayed in response to the start operation instead of the medal insertion operation. , 224, 225 to the top screen 221.

  That is, in this embodiment, when the re-game is activated and the game information screens 223, 224, 225 are displayed, the display screen is automatically displayed on the game information screens 223, 224 in response to the start operation. , 225 to the top screen 221. On the other hand, when the re-game operation is not performed, the display screen automatically transitions from the game information screens 223, 224, 225 to the top screen 221 in response to the input operation.

[Display switching function from menu content display screen to top screen (or menu screen)]
The pachi-slot 1 of this embodiment has various menu content display screens (a registration screen, an explanation screen, an array payout screen, a reach eye screen, a WEB introduction) that can change the display screen of the sub display device 18 by a menu selection operation on the menu screen 222. The screen has a function of shifting from the screen and the volume adjustment screen) to the top screen 221 (or the menu screen 222) manually or automatically by the player. Specifically, in this embodiment, when a predetermined button (for example, “Return to TOP” button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 ( Manual transition function). In this embodiment, when a specific button (for example, a “return” button) is operated on the menu content display screen, the display screen transits from the menu content display screen to the menu screen 222 (manual transition). function).

  Furthermore, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically changes to the top screen 221 (or the menu screen 222) regardless of the player's operation. Transition (automatic transition function). At this time, the predetermined time that triggers automatic transition to the top screen 221 (or the menu screen 222) varies depending on the type of the menu content display screen currently displayed. For example, if the volume adjustment screen for adjusting the volume output from the pachislot 1 is displayed for a long time, not only may the volume be adjusted to an unintended volume due to an erroneous operation, but other players may be caused by an erroneous operation. There is also a risk of discomfort. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or the menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transition to the top screen 221 (or the menu screen 222) in a longer time than other menu content display screens in order to facilitate player registration. .

  That is, in each menu content display screen, an elapsed time (automatic transition time) that triggers automatic transition to the top screen 221 (or menu screen 222) is appropriately set according to the type of the menu content display screen. In the volume adjustment screen, an automatic transition time shorter than that of the other menu content display screen is set, and in the registration screen, an automatic transition time longer than that of the other menu content display screen is set.

[Function for selecting whether to operate the menu]
In the pachi-slot 1 of this embodiment, the display screen of the sub display device 18 is changed from the menu screen 222 to a registration screen, an explanation screen, an array payout screen, a reach eye screen, a WEB introduction screen, and a volume adjustment screen. A person can perform various operations according to these menu content display screens, and can confirm various information. It should be noted that a function (a function for selecting whether or not to operate the menu) may be provided so that such a function that allows the player to select a menu can be restricted according to the settings on the game store side.

  For example, the display screen may not be allowed to transition from the menu screen 222 to the volume adjustment screen (for example, the “volume” button 222g is not displayed on the menu screen 222) according to settings at the game store side. In this case, the volume adjustment by the player can be made impossible.

<Control system for pachislot>
Next, a control system provided in the pachislo 1 will be described with reference to FIG. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachislot 1.

  The pachi-slot 1 includes a main control board 71 provided on the middle door 41 and a sub-control board 72 provided on the front door 2b. The pachi-slot 1 includes a reel relay terminal board 74, a setting key switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot 1 includes an external concentration terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via the cabinet-side relay board 44. In addition, since the structure of the hopper apparatus 51 was mentioned above, the description is abbreviate | omitted here.

  The reel relay terminal plate 74 is disposed inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal board 74 is electrically connected to stepping motors (not shown) of the reels 3L, 3C, 3R, and relays signals output from the main control board 71 to the stepping motors.

  The setting key type switch 54 is provided on the main control board case 55. The setting key switch 54 is used when changing the setting (setting 1 to setting 6) of the pachi-slot 1 or when checking the setting of the pachi-slot 1.

  The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external concentration terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. It is. The external concentration terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52 and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot 1.

  The power supply device 53 includes a power supply board 53b and a power switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot 1. The power supply board 53 b is connected to the main control board 71 via the cabinet side relay board 44 and also connected to the sub control board 72 via the sub relay board 61.

  The pachislot machine 1 includes a door relay terminal plate 68, a selector 66, a door open / close monitoring switch 67, a BET switch 77, a checkout switch 78, which are connected to the main control board 71 via the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub-relay board 61, a first testing machine interface board 301, and a second testing machine interface board 302. Since the selector 66, the door opening / closing monitoring switch 67, and the sub relay board 61 have been described above, the description thereof is omitted here.

  The BET switch 77 (insertion operation detecting means) detects that the MAX bet button 15a or the 1 bet button 15b has been pressed by the player. The settlement switch 78 detects that a settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

  The stop switch substrate 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stopable main reel by an LED or the like. The stop switch substrate 80 is provided with a stop switch (not shown). The stop switch detects that each stop button 17L, 17C, 17R has been pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 includes, for example, three LEDs for displaying the number of inserted medals (hereinafter referred to as “first LED” to “first LED”) that are turned on in correspondence with the number of medals inserted in the current game (hereinafter referred to as “inserted number”). LED for lighting a medal insertion mark, a game start mark, a replay mark, etc. based on a signal input from the game operation display board 81) Etc. are included. In the first to third LEDs (display means), when one medal is inserted, the first LED is turned on, and when two medals are inserted, the first and second LEDs are turned on, and three medals (game) When the startable number of sheets is inserted, the first to third LEDs are turned on. Since the information display device 6 has been described above, the description thereof is omitted here.

  Both the first interface board 301 for testing machine and the second interface board 302 for testing machine are relay boards used when various signals relating to games are output to the testing machine in the pachislot 1 certification test (trial test) ( Since these relay boards are not mounted on the pachislot machine 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for testing machine and the testing machine. Various electronic components necessary for connecting to the second interface board 302 are also not mounted). For example, a test signal for controlling a main operation related to the game (for example, internal lottery, reel stop control, etc.) is output via the first interface board 301 for testing machine, and is determined by the main control board 71, for example. A test signal or the like related to the pushed push navigation is output via the second interface board 302 for the testing machine.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. The pachislot machine 1 includes a speaker group 84, LED groups 85, a 24h door opening / closing monitoring unit 63, a touch sensor 19, and a display unit 212, which are connected to the sub control board 72 via the sub relay board 61. Since the touch sensor 19 has been described above, the description thereof is omitted here.

  The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10 and a light source that emits light for illuminating the decorative panel of the waist panel 12 from the back side. The 24h door opening / closing monitoring unit 63 stores opening / closing history information of the middle door 41. Further, the 24h door opening / closing monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projection target 212a constituting the display device 11, and another projection target with a curved display surface provided on the back side of the projection target 212a.

  The pachi-slot 1 also includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub control substrate 72. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are housed in the sub control board case 57 together with the sub control board 72.

  The ROM cartridge substrate 86 is a substrate for managing various control programs executed by the sub CPU 102, production images (videos), sound (speaker groups 84), light (LED groups 85), and communication data. . The liquid crystal relay substrate 87 is a substrate that relays connection wiring between the sub control substrate 72, the projector mechanism 211 constituting the display device 11, and the sub display device 18. Since the projector mechanism 211 and the sub display device 18 have been described above, the description thereof is omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

  The microprocessor 91 is a microprocessor with a security function for gaming machines. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes specific to the microprocessor 91 that can be defined in the source program (for example, “LDQ” instruction described later, etc., hereinafter: “main CPU 101” A dedicated instruction code). In this embodiment, by using the instruction code dedicated to the main CPU 101, the processing efficiency and the program capacity are reduced. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by a main control circuit described later. To do.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

  The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). The power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the startup voltage value (10V) from 0V). When a power interruption occurs (when the power supply voltage falls below the power failure voltage value (10.5 V) from 12 V), a power interruption detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (start signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means to output (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (DC power supply voltage of 5 V DC) for the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing the internal configuration of the microprocessor 91.

  The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 105, an arithmetic circuit 107, A random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115 are included. These units constituting the microprocessor 91 are connected to each other via a signal bus 116.

  The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 and performs control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  The main CPU 101 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, 3L (main reel) after detecting the reel index. Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. The reel index includes, for example, an optical sensor having a light emitting unit and a light receiving unit, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting unit and the light receiving unit by the rotation of each main reel. It is detected by a provided reel position detector (not shown).

  Here, management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Each time the output of a predetermined number of pulses necessary for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is incremented by one. A symbol counter is provided for each reel. The value of the symbol counter is cleared when a reel index is detected by a reel position detector (not shown).

  In other words, in the present embodiment, by managing the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG.

  The external bus interface 104 electrically connects an external signal bus (not shown) to which various components (for example, each reel) provided outside the microprocessor 91 are connected to the microprocessor 104. It is an interface circuit. The clock circuit 105 includes, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is received by other components (for example, the timer circuit 113). Convert to a clock pulse signal of the frequency used. Note that the clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or WDT (watchdog timer) based on the reset signal input from the power management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when executing a “MUL (multiplication)” instruction (see FIG. 93B described later) on the source program, the arithmetic circuit 107 executes a multiplication process based on the “MUL” instruction.

  The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 generates a random number register 0 for obtaining a 2-byte hard latch random number, random number registers 1 to 3 for obtaining a 2-byte soft latch random number, and a 1-byte soft latch random number. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from a predetermined range of random numbers generated by the random number circuit 110, for example, as a random value for internal lottery. The parallel port 111 is a port (memory map I / O) for signals input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93) provided outside the microprocessor 91. . The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to one of the input ports PI0 to PI4 of the parallel port 111, and the latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110 at a timing (on edge) when the start switch 79 is turned on. Is output. In the random number circuit 110, when the latch signal is input, the random number register 0 is latched, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs an interrupt process by the main CPU 101 based on a power interruption detection signal input from the power management circuit 93 via the parallel port 111 or a time-out signal input from the timer circuit 113 at a cycle of 1.1172 ms. Control the execution timing of. When a power failure detection signal is input from the power management circuit 93 or a time-out signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. Based on the interrupt request signal input from the interrupt controller 112 in response to the time-out signal from the timer circuit 103, the main CPU 101 performs input port check processing, reel control processing, communication data transmission processing, 7-segment LED drive processing, timer Various interrupt processing such as update processing (see FIG. 158 described later) is performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (clock pulse signal having a frequency obtained by dividing a clock pulse signal for operating the main CPU by a frequency divider (not shown)). Count elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) is transmitted from the main control board 71 to the sub-control board 72. The second serial communication circuit 115 is a circuit that controls a serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Sub control circuit>
Next, the configuration of the sub control circuit 200 (sub control means) mounted on the sub control board 72 will be described with reference to FIG. FIG. 10 is a block diagram illustrating a configuration example of the sub control circuit 200 of the pachislot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 90. The sub control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge substrate 86. The driver 205 is connected to the liquid crystal relay substrate 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  In the program storage area, a control program executed by the sub CPU 201 is stored. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random number value for production are extracted, and production registration for determining and registering production contents (production data). Various programs for executing tasks are included. In addition, the control program includes a drawing control task for controlling the display of video by the display device 11 based on the determined content of the presentation, a lamp control task for controlling the output of light from a light source such as the LED group 85, and a sound by the speaker group 84. Various programs for executing a voice control task or the like for controlling the output of the program are also included.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to creation of video. Further, the data storage area includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a light on / off pattern, and the like.

  The sub RAM 202 is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create a video according to the animation data designated by the contents of the presentation, and display the created video on the display device 11 (projector mechanism 211) and / or Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the contents of the effect. Further, the sub CPU 201 controls lighting and extinguishing of the LED group 85 according to the lamp data designated by the contents of the effect.

<Various registers of main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 includes, as main registers, an accumulator A (hereinafter referred to as “A register”), a flag register F (flag register), a general purpose register B (hereinafter referred to as “B register”), and a general purpose register C (hereinafter referred to as “register A”). General purpose register D (hereinafter referred to as “D register”), general purpose register E (hereinafter referred to as “E register”), general purpose register H (hereinafter referred to as “H register”) and general purpose register L (hereinafter referred to as “C register”). , Referred to as “L register”). Further, the main CPU 101 includes, as sub registers, an accumulator A ′, a flag register F ′, a general purpose register B ′, a general purpose register C ′, a general purpose register D ′, a general purpose register E ′, a general purpose register H ′, and a general purpose register L ′. As a general purpose register. Each register is composed of a 1-byte register.

  In this embodiment, the B register and the C register are used as a pair register (hereinafter referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter referred to as “DE register”). Furthermore, in this embodiment, the H register and the L register are used as a pair register (hereinafter referred to as “HL register”).

  As shown in FIG. 11, predetermined flag information indicating the result of the arithmetic processing is set in each bit of the flag registers F and F ′. For example, in bit 6 (D6), data (zero flag) indicating whether or not the calculation result is “0” in the calculation result determination process is set. Specifically, when the operation result is “0”, data “1” is set in bit 6, and when the operation result is not “0”, data “0” is set in bit 6. In the calculation result determination process, the main CPU 101 performs determination (YES / NO) with reference to the data “0” / “1” of bit 6.

  The main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described in the various processing flows described later, various instruction codes dedicated to the main CPU 101 for performing address designation using the Q register are provided on the source program. As a result, the processing efficiency and the capacity of the main ROM 102 are reduced. In various instruction codes dedicated to the main CPU 101 that perform address designation using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. In the Q register, “F0H” is set as an initial value immediately after the main CPU 101 is reset. In addition, in the “LD Q, n (8-bit data)” instruction using the Q register, the value of the Q register is changed by setting arbitrary 1 byte data to “n” and executing the instruction. be able to.

  Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R configured by 1-byte registers, and an index register IX and an index register IY configured by 2-byte registers. The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configuration of the main ROM 102 and the main RAM 103 (hereinafter referred to as “memory map”) included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 12A to 12C. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

  In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, The XCS decode areas are arranged at predetermined addresses in this order with an unused area in between.

  In the memory map of the main ROM 102, as shown in FIG. 12B, from the head (0000H) side of the address of the main ROM 102, there are a program area, a data area, an unspecified area, a trademark recording area, a program management area, and a security setting area. In order, they are arranged at predetermined addresses.

  In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to game playability performed by the player are stored. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, various sub-control circuits 42, etc.) in various control processes related to game playability performed by the player. Data for transmitting a control command (command), etc.) are stored. In other words, the game ROM area (game storage area) composed of a program area and a data area is necessary for control processing (game-related processing) related to game playability actually performed by the player at the game store. Various programs and various data are stored.

  The non-regulated area stores control programs and data for various processes (processes that do not affect the game characteristics) that are not directly related to the game performance of the game executed by the player. For example, a program and data used in a pachislot 1 certification test (trial test), a control program and data used in checksum generation processing at power interruption or sum check processing at power recovery, and a fraud countermeasure program In addition, data necessary for the data and the like are stored in an unspecified area.

  In the memory map of the main RAM 103, as shown in FIG. 12C, from the head (F000H) side of the address of the main RAM 103, a gaming RAM area (predetermined storage area, gaming temporary storage area) and an unspecified RAM area (unspecified temporary area). Storage areas) are arranged at predetermined addresses in this order.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the game performance of the game executed by the player. . Each of the various data is stored in a work area at a predetermined address in the game RAM area.

  In addition, the non-specified RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the game performance of the game executed by the player, and a non-standard stack. In the present embodiment, various processes that are not directly related to the game playability of the game executed by the player, such as a sum check process, are executed using the non-regulated RAM area.

  As described above, in the pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes that are not directly related to the game performance of the game performed by the player are stored in the main ROM 102. The data is stored in a non-standard ROM area (non-standard storage area) arranged at an address different from the ROM area. In addition, various processes that are not directly related to game playability performed by such a player are performed in the main RAM 103 using an unspecified RAM area that is arranged at an address different from the game RAM area. .

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually played by the player are placed in the ROM area (non-specified ROM area) where it is impossible to place a program or the like according to the conventional rules. can do. Therefore, in this embodiment, compression of the capacity of the game ROM area can be avoided.

<Game state transition flow>
Next, various game states managed by the main control circuit 90 (main CPU 101) of the pachi-slot 1 of this embodiment and the transition flow thereof will be described with reference to FIGS. FIG. 13A is a transition flow diagram of the basic gaming state of the pachislot 1, and FIG. 13B is a table summarizing the transition conditions of the gaming state. FIG. 14A is a game state transition flow diagram in consideration of whether or not the notification (ART) function is activated, and FIG. 14B is a table summarizing the game state transition conditions.

[Basic game state transition flow]
In the pachi-slot 1 of the present embodiment, a big bonus (hereinafter referred to as “BB”) is provided as a type of bonus game. BB is an accessory continuous operation device related to a regular bonus (hereinafter referred to as “RB”) called a first type special accessory, and continuously operates the RB.

  Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on whether or not the bonus combination is won / actuated (winning). Specifically, as shown in FIG. 13A, the main control circuit 90 determines whether or not the bonus combination (internal winning combination of names “F_BB1” and “F_BB2” described later) is won / actuated (winning). Three types of gaming states called “bonus non-winning state”, “inter-flag state” and “bonus state” are managed.

  Note that the bonus non-winning state is a state where the bonus is non-winning and the bonus is not activated (winning), and the bonus state is a state where the bonus is activated. In this embodiment, when a bonus combination is determined as an internal winning combination, a state in which the bonus combination is carried over as an internal winning combination over a plurality of games until the bonus is won is generated. The inter-flag state is a state where the bonus combination is carried over as an internal winning combination, that is, a state where the bonus combination is won and the bonus is not activated.

  Whether or not the bonus combination is won is determined by the data stored in the later-described hit request flag storage area (see FIGS. 28 to 30 described later) and the carryover combination storage area (see FIG. 31 described later) provided in the main RAM 103. Managed based on. Further, whether or not a bonus is activated (winning) is managed based on data stored in a later-described game state flag storage area (see FIG. 32 described later) provided in the main RAM 103.

  In the present embodiment, as shown in FIG. 13A, in the gaming state where the bonus is not activated (bonus non-winning state and inter-flag state), the type of internal winning combination related to replay and the winning probability are different from each other. Six types of states, RT0 gaming state to RT5 gaming state (hereinafter referred to as “RT0 state” to “RT5 state”, respectively), are provided. The RT0 state, the RT2 state, and the RT5 state are gaming states in which the probability that a replay role is determined as an internal winning combination is low, and the RT1 state has a medium probability that a replay role is determined as an internal winning combination. It is a gaming state with a medium probability. The RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is one of the RT0 state to the RT4 state, and the RT state in the inter-flag state is the RT5 state.

  Therefore, in this embodiment, the main control circuit 90 is further based on the type of internal winning combination related to replay and its winning probability in a gaming state where the bonus is not activated (bonus non-winning state and inter-flag state). Thus, six types of states from the RT1 state to the RT5 state are also managed.

  The RT0 state to RT5 state are managed based on data stored in a game state flag storage area (described later in FIG. 32) provided in the main RAM 103. Specifically, in the pachislot machine 1 of the present embodiment, five flags indicating the RT state of the RT1 state flag to the RT5 state flag are provided, and the on / off state of these flags is managed by the main RAM 103, thereby the RT state. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag that is in the on state as the current RT state. When all the RT state flags are in the off state, the main control circuit 90 specifies that the current RT state is the RT0 state.

  As shown in FIGS. 13A and 13B, in the bonus non-winning state, when a bonus combination (an internal winning combination of names “F_BB1” and “F_BB2” described later) is determined as an internal winning combination (when transition condition (1) is satisfied) ), The main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. When the bonus combination wins in the inter-flag state (when the transition condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

  Further, when medals exceeding the prescribed number (216) are paid out in the bonus state and the bonus state is terminated (when the transition condition (3) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the RT1 state ( Shift to bonus non-winning state).

  When 20 games have elapsed in the RT1 state (when the transition condition (4) is satisfied), the main control circuit 90 shifts the gaming state from the RT1 state to the RT0 state. Further, in the RT1 state, before the 20 games have elapsed, when the symbol combination (see FIG. 28 described later) relating to the abbreviation “bell spilled eyes” is displayed on the active line (when the transition condition (5) is satisfied). The main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

  In the RT0 state, when the symbol combination related to the abbreviation “bell spill” is displayed on the active line (when the transition condition (5) is satisfied), the main control circuit 90 shifts the gaming state from the RT0 state to the RT2 state. Let In the RT2 state, when the symbol combination related to the abbreviation “RT3 transition lip” (see FIG. 28 described later) is displayed on the active line (when the transition condition (6) is satisfied), the main control circuit 90 changes the gaming state. Transition from the RT2 state to the RT3 state.

  In the RT3 state, when the symbol combination related to the abbreviation “RT4 transition lip” (see FIG. 28 described later) is displayed on the active line (when the transition condition (7) is satisfied), the main control circuit 90 changes the gaming state. Transition from the RT3 state to the RT4 state. In the RT3 state, when the symbol combination (see FIG. 28 described later) relating to the abbreviation “bell spill” or “RT2 transition lip” is displayed on the active line (when the transition condition (8) is satisfied), The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Furthermore, in the RT4 state, when the symbol combination related to the abbreviation “bell spill” or “RT2 transition lip” is displayed on the active line (when the transition condition (8) is satisfied), the main control circuit 90 The gaming state is shifted from the RT4 state to the RT2 state.

  As for the symbol combination related to the abbreviation “bell spilled eyes”, an internal winning combination (small role) related to the name “F_3 selection bell_1st”, “F_3 selection bell_2nd” or “F_3 selection bell_2rd” described later is determined, And it is a combination of symbols displayed when the order of the stop operation is incorrect for the pressing order determined for each type of the small role (see FIG. 24 described later). For the symbol combination related to the abbreviation “RT2 transition lip”, an internal winning combination (replay combination) related to a name “F_maintenance lip_1st”, “F_maintenance lip_2nd” or “F_maintenance lip_3rd” described later is determined, and This is a combination of symbols displayed when the order of the stop operation is incorrect for the pressing order determined for each type of the replay combination.

  For the symbol combination related to the abbreviation “RT3 transition Lip”, an internal winning combination (replay combination) related to the names “F_RT3 Lip_1st”, “F_RT3 Lip_213”, “F_RT3 Lip_231” or “F_RT3 Lip_3rd” described later is determined. And the combination of symbols displayed when the order of the stop operation is correct with respect to the pressing order determined for each type of the replay combination. In addition, the symbol combination related to the abbreviation “RT4 transition Lip” has an internal winning combination (replay combination) related to the names “F_RT4 Lip_123”, “F_RT4 Lip_132”, “F_RT4 Lip_2nd”, or “F_RT4 Lip_3rd” described later. This is a combination of symbols that is displayed when the order of stop operations is determined and is correct with respect to the pressing order determined for each type of replay combination.

[Game State Transition Flow Considering Operation of Notification (ART) Function]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not to activate a function (ART function) that notifies a stop operation that is advantageous to the player. Therefore, in this embodiment, in the bonus inactive state, the operating / inactive state of the ART function is also managed as a gaming state.

  In the pachi-slot 1 of the present embodiment, as shown in FIG. 14A, the main control circuit 90 distinguishes between the “general gaming state” and the “ART gaming state” based on the presence / absence of notification (ART) in the non-bonus operating state. To manage as a gaming state. That is, in the management of the gaming state in consideration of the presence / absence of notification (ART), as shown in FIG. 14A, the main control circuit 90 categorizes the “bonus state”, “general gaming state”, and “ART gaming state” as broad categories. 3 types of gaming state are managed.

  Note that the general game state is basically a game state (non-ART) in which information on a stop operation advantageous to the player is not notified, and is a disadvantageous game state for the player. Further, the general gaming state is one of the RT0 to RT4 states, and is an ART non-winning gaming state.

  On the other hand, the ART gaming state is a gaming state in which information on a stop operation advantageous to the player is notified, and is a gaming state advantageous to the player. Further, the ART gaming state is basically a RT4 state and a gaming state in which the ART is won. In this embodiment, when the RT state transitions to the RT4 state after winning the ART, the ART game is started.

  In the present embodiment, as shown in FIG. 14A, two types of states called “normal game state” and “CZ (chance zone)” are provided as the general game state.

  The normal game state is the most unfavorable game state for the player, but in the game in the normal game state, a lottery to shift to CZ is performed. Then, as shown in FIGS. 14A and 14B, in the game in the normal game state, when the winning lottery to CZ is won (when the transition condition (A) is satisfied), the main control circuit 90 changes the game state to the normal game state. To CZ.

  CZ is a gaming state (chance zone) with high expectation for the transition to the ART gaming state, and a lottery for transitioning to the ART is performed in the game in the CZ. Then, as shown in FIGS. 14A and 14B, in the game in CZ, when the lottery for shifting to ART is not won (when the transition condition (B) is satisfied), the main control circuit 90 changes the gaming state. , Transition from the CZ to the normal gaming state. On the other hand, in a game during CZ, when winning a lottery for shifting to ART (when the transition condition (C) is satisfied), the main control circuit 90 shifts the gaming state from CZ to the ART gaming state. At this time, although not shown in FIG. 14A, the main control circuit 90 shifts the gaming state from CZ to the ART gaming state (described later, normal ART or CT) via the ART preparation state described later.

  As described above, the ART gaming state is started when the RT state shifts to the RT4 state after winning the ART. As shown in FIG. 13A, since the RT4 state shifts from the RT0 to RT2 state via the RT3 state, the ART gaming state is not immediately started even after the ART is won. Therefore, in the pachi-slot 1 of the present embodiment, the gaming state during the period from the winning of the ART to the transition of the RT state to the RT4 state is set to the ART ready state. In this ART ready state game, information on a stop operation necessary to shift the RT state to the RT4 state is notified.

  Further, in the present embodiment, as shown in FIG. 14A, two types of states called “normal ART” and “CT (additional chance)”, which are different from each other, are provided as the ART gaming state.

  The normal ART is a stop operation that is advantageous to the player for a predetermined number of games (for example, a stop operation for displaying a symbol combination with a large number of medals to be paid out or a stop operation necessary for maintaining the RT4 state). Is a gaming state in which is notified. Further, in a game during normal ART, a lottery for transition to CT is performed.

  CT is a gaming state in which a stop operation that is advantageous to the player is notified, and it is possible to add a normal ART continuation period for a specific period (one set of eight games), and functions as an extra chance zone It is a gaming state to play. Also, during CT, a game is usually played without digesting the duration of ART. Note that game play during CT will be described in detail later with reference to FIGS. 52A to 52C described later.

  As shown in FIGS. 14A and 14B, in a game during a normal ART, when winning a lottery for transition to CT (when the transition condition (D) is satisfied), the main control circuit 90 changes the game state from normal ART to CT. Transition game state. In the normal ART, when the duration of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the game state from the normal ART to the general game state (normal game state or CZ). Transition. In this embodiment, the duration of the normal ART is managed by the number of games. However, the present invention is not limited to this, and the management method of the duration of the normal ART is arbitrary. For example, the duration of normal ART may be managed based on the number of medals paid out during normal ART or the number of differences, or depending on the number of times of notification (number of navigations) affecting medal payout during normal ART. May be managed.

  As shown in FIGS. 14A and 14B, in the game during CT, when the duration of CT (one set of 8 games) ends (when the transition condition (F) is satisfied), the main control circuit 90 changes the game state to CT. To normal ART.

  Further, as shown in FIG. 14A, when a bonus combination is won in the general gaming state (normal gaming state or CZ) or the ART gaming state (normal ART or CT) (the transition condition (2) described in FIGS. 13A and 13B). When established, the main control circuit 90 shifts the gaming state from the general gaming state or the ART gaming state to the bonus state.

  In the game in the bonus state, as described above, the lottery for the transition to ART is performed. In the game in the bonus state, when the lottery for transition to the ART is non-winning (when the transition condition (G) is satisfied) The main control circuit 90 shifts the gaming state from the bonus state to the general gaming state (normal gaming state or CZ). However, if the ART game state (normal ART or CT) has shifted to the bonus state, the main control circuit 90 will change the game state, Transition from the bonus state to the ART gaming state (normal ART or CT). On the other hand, in the bonus state game, when the lottery for transition to ART is won (when the transition condition (H) is satisfied), the main control circuit 90 changes the game state from the bonus state to the ART game state (normal ART or CT). Transition. As described above, since the RT state shifts to the RT1 state at the end of the bonus state, when the gaming state is shifted from the bonus state to the ART gaming state, the main control circuit 90 changes the gaming state to the ART state. A transition is made to the ART gaming state via the preparation state.

<Configuration of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 102 will be described with reference to FIGS. Various data tables used in various lotteries relating to the gameability (CZ, normal ART, CT gameability) in the general gaming state and the ART gaming state will be described later together with the description of each gaming property. .

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is data (hereinafter referred to as symbol code (in FIG. 15) that specifies the position of each symbol in the rotation direction of each of the left reel 3L, the middle reel 3C, and the right reel 3R and the type of symbol arranged at each position. )))).

  In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle area of each reel within the frame of the reel display window 4 is defined as “0”. Then, in each reel, the symbol counter value “0” corresponds to the value of the symbol counter in the order of advance in the reel rotation direction (the direction from symbol position “19” in FIG. 15 toward symbol position “0”). “0” to “19” are assigned to the symbols as symbol positions.

  That is, by referring to the symbol counter values (“0” to “19”) and the symbol arrangement table, the symbols are displayed in the upper, middle, and lower regions of each reel within the frame of the reel display window 4. It is possible to specify the type of design. In this embodiment, the symbols “white 7”, “blue 7”, “top 1”, “top 2”, “bottom”, “replay”, “hat”, “cactus 1”, Ten kinds of symbols “Cactus 2” and “Cactus 3” are used.

  In this embodiment, as shown in the symbol code table, symbol “white 7” (symbol code 1) is assigned “00000001” as data, and symbol “blue 7” (symbol code 2) “00000010” is assigned as data. The symbol “Chile top 1” (symbol code 3) is assigned “00000011” as data, and the symbol “Chile above 2” (symbol code 4) is assigned “00000100” as data.

  The symbol “Chile under” (symbol code 5) is assigned “00000101” as data, and the symbol “Replay” (symbol code 6) is assigned “00000110” as data. The symbol “hat” (symbol code 7) is assigned “0000011” as data, and the symbol “cactus 1” (symbol code 8) is assigned “00001000” as data. In addition, the symbol “cactus 2” (symbol code 9) is assigned “00000101” as data, and the symbol “cactus 3” (symbol code 10) is assigned “00001010” as data.

[Internal lottery table]
Next, an internal lottery table referred to when determining an internal winning combination will be described with reference to FIGS. 16 and 17. FIG. 16 is an internal lottery table referred to in each of the RT0 state to the RT4 state. FIG. 17A is an internal lottery table referred to in the RT5 state, and FIG. 17B is an internal lottery table referred to in the bonus state.

  The internal lottery table is provided for each gaming state, and defines the correspondence between various internal winning combinations and lottery values when each internal winning combination is determined. Note that the lottery value is defined for each setting (settings 1 to 6) for adjusting the expected value of internal winnings such as a bonus combination and a small combination set in advance. This setting is changed using, for example, the reset switch 76 and the setting key switch 54 (see FIG. 7).

  In the internal lottery process of this embodiment, first, a random number value extracted from a predetermined numerical range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 is assigned to each internal winning combination. Sequentially add with the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result has overflowed). When the lottery result exceeds 65535 in a predetermined internal winning combination, it is determined that the internal winning combination is won. In the internal lottery process of the present embodiment, an example of performing lottery by adding a lottery value to an extracted random number value has been described, but the present invention is not limited thereto, and the lottery value is subtracted from the random number value, It may be determined whether the subtraction result (lottery result) has fallen below “0” (whether the lottery result has underflowed) or not to determine whether the internal lottery is won or not.

  Therefore, in the internal lottery process of the present embodiment, the probability of being determined is higher for an internal winning combination having a larger numerical value defined as a lottery value. The winning probability of each internal winning combination can be expressed by “the lottery value specified for each winning number / the number of all random numbers that may be extracted (random number denominator: 65536)”.

  In the internal lottery table referenced in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, the type of replay combination and the winning probability determined as the internal winning combination according to the type of the RT state Changes. For example, the replay combination relating to the names “F_Chill Lip (No. 25)” to “F_Reach Eye Lip D (No. 31)” is not determined as an internal winning combination in the RT0 state to the RT3 state, but in the RT4 state. Only determined as an internal winning combination. In the pachi-slot 1 of the present embodiment, the replay roles relating to the names “F_Chilelip (No. 25)” to “F_Leach Eye Lip D (No. 31)” are determined as internal winning combinations during the RT4 state. In this case, peculiar control (flag conversion described later) is performed. This flag conversion will be described in detail later.

  Also, as shown in FIG. 16, in the RT0 state to the RT3 state, the internal winning combinations of the names “F_reach eye lip A” to “F_reach eye lip D” are related to the names “F_BB1” or “F_BB2”. Although it may be determined to overlap with the bonus combination (see Nos. 3-6, 15-18), each of the internal winning combinations (replays) of the names “F_reach eye lip A” to “F_reach eye lip D” Is not determined as an internal winning combination alone. Therefore, in the present embodiment, when the replay combination relating to the names “F_reach eye lip A” to “F_reach eye lip D” is determined as the internal winning combination during the RT0 state to the RT3 state (name from the player's point of view) A bonus combination (named “F_BB1” or “F_BB2”) and an internal winning combination are simultaneously determined when a symbol combination corresponding to a replay combination related to “F_reach lip A” to “F_reach lip D” is displayed. Will be.

  The RT5 state, which is an inter-flag state, is a gaming state in which a bonus combination is carried over as an internal winning combination as described above. Therefore, as shown in FIG. 17A, in the internal lottery table referenced in the RT5 state, the bonus combination carried over is always determined as the internal winning combination. Also, as shown in FIG. 17B, the internal lottery table referred to in the bonus state is configured such that an internal winning combination corresponding to any of the names “F_RB winning 1” to “F_RB winning 4” is always won ( "Out of the box" will not win.)

[Correspondence table between internal winning combination and symbol combination (winning combination) (design combination determination table)]
Next, with reference to FIGS. 18 to 23, a correspondence table (symbol combination determination table) between internal winning combinations and symbol combinations will be described. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line (center line) associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the active line (the type of display combination that can win a prize) is uniquely determined.

  Various data described in the symbol combination column in each symbol combination determination table is for identifying symbol combinations that are allowed to be displayed along the effective lines set over the left reel 3L, the middle reel 3C, and the right reel 3R. It is data. The relationship between each name described in the symbol combination (display combination) column and a specific symbol combination is shown in a winning action flag storage area of FIGS. 28 to 30 described later.

  The symbol “◯” described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the active line in the determined internal winning combination, that is, a display combination that can be won. For example, when the internal winning combination “F_Chilli Lip” is determined, as shown in FIG. 18 and FIG. 19, the combination names “C_Keep Lip A_01” to “C_Keep Lip G_01”, “C_Chilli Lip A_01” to “C_Chilli Lip” The symbol combination related to “D_01” can be stopped and displayed. In the symbol combination determination table, the case where the “internal winning combination” is “out of” is not defined, but this is because all symbols defined by the symbol combination table shown in FIGS. Indicates that combination display is not allowed.

  In the pachi-slot 1 of the present embodiment, the main control circuit 90 (main CPU 101) changes the stop control according to the internal winning combination and the gaming state, and when the predetermined winning combination is determined as the internal winning combination, FIG. Rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the corresponding symbol combination (combination) shown in FIG. 23 can be displayed. In the correspondence tables shown in FIGS. 18 to 23, all the symbol combinations that can be displayed for the determined internal winning combination are listed with “◯” marks, but the symbols with “○” marks are attached. Even a combination may not be displayed.

  In the present embodiment, there is a function of changing stop control (for example, a drawing to be drawn preferentially) according to a combination of symbols that can be stopped and the current gaming state. Even symbol combinations with marks may not be displayed. The correspondence between the type of internal winning combination and the symbol combination actually displayed will be described with reference to FIGS. 24 and 25 described later.

[Correspondence between winning combination in non-flag state and symbol combination to be stopped]
Here, with reference to FIG. 24, the correspondence relationship between the internal winning combination in the gaming state (non-flag state) excluding the inter-flag state and the symbol combination that is stopped and displayed will be described. FIG. 24 shows the correspondence between various internal winning combinations that can be determined in the non-flag state and symbol combinations (abbreviated) that are stopped when each internal winning combination is determined (some combinations are omitted). FIG. The name of the symbol combination described in FIG. 24 is an “abbreviation” described in the contents column shown in the winning action flag storage area of FIGS. 28 to 30 described later.

  In the pachi-slot 1 of the present embodiment, a so-called “push order” is provided in which the symbol combinations displayed differ according to the order (push order) of the player's stop operation. Note that the symbol combination associated with the “push order correct answer” shown in FIG. 24 is a symbol combination advantageous to the player among the symbol combinations displayed according to the push order, and the “push order incorrect answer” The associated symbol combinations are symbol combinations that are disadvantageous to the player among the symbol combinations displayed according to the pressing order. When notifying a stop operation that is advantageous to the player, the correct push order is notified, and if the stop operation is performed in accordance with the notification, the symbol combination associated with the “push order correct answer” is displayed. In addition, even in the ART gaming state, the push order that becomes an incorrect answer may be notified, but the contents will be described in detail later.

  In the present embodiment, for some of the push order combinations, the correct push order is shown at the end of the name. Specifically, the end “1st” of the name of the internal winning combination means that the correct pressing order is that the first stop operation (first stop operation) is for the left reel 3L, The end of the name of the internal winning combination “2nd” means that the correct pushing order is that the first stop operation is for the middle reel 3C, and the end of the name of the internal winning combination “3rd” is the correct answer. This pressing order means that the first stop operation is for the right reel 3R. In addition, the last “123” of the name of the internal winning combination means that the pressing order of the correct answer is “left, middle, right”, and the last “132” of the name of the internal winning combination is the correct answer. Means that the order of pressing is “left, right, middle”, and the last “213” of the name of the internal winning combination is the order of “middle, left, right”. And “231” at the end of the name of the internal winning combination means that the correct pressing order is “left, right, middle”.

  In the following, the stop operation sequence when the first stop operation is performed on the left reel 3L, specifically, the pressing order of “left, middle, right” and “left, right, middle” is “ It is also called “pressing forward” Furthermore, in the following, the stop operation sequence when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, “middle, left, right”, “middle, right, left”, The pressing order of “right, middle, left” and “right, left, middle” is also referred to as “anomalous pressing”.

  In the present embodiment, as shown in FIG. 24, the internal winning combination “F_Chilelip” is a pressing combination in which the symbol combination displayed according to the pressing order is different, and when the pressing order is correct, the abbreviation “ One of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to “Chilelip” (see FIG. 28 described later) is displayed along the active line. On the other hand, when the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation “Replay” (see FIG. 28 described later) is along the active line. Displayed. When the internal winning combination “F_Chillilip” is determined, as shown in FIGS. 18 to 23, the combination names “C_Chillilip A_01”, “C_Chillilip B_01” or “C_Chillilip C_01” (abbreviated “Single Chillilip”) Or, the symbol combination relating to the abbreviation “Chilelip (no triple)” in FIG. 28 to be described later) can be displayed, but the combination names “C_Chillilip D_01” to “C_1 correct Chilelip D_01” (abbreviation) “Triple Chile Lip”: Corresponding to the abbreviation “Chile Lip (Triple)” in FIG. 28 to be described later). That is, the internal winning combination “F_Chillilip” is a combination that cannot display the symbol combination related to the abbreviation “Triple Chilelip”.

  In addition, the internal winning combination “F_Challenging Lip” and “F_1 Challenging Lip” are both pushing orders with different symbol combinations displayed according to the pressing order. When the pressing order is correct, the abbreviation “Chile Lip” Among the symbol combinations related to (see FIG. 28 described later), any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, when the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation “Replay” (see FIG. 28 described later) is along the active line. Displayed. In addition, when the internal winning combination “F_accurate Chililip” or “F_1 exact Chililip” is determined, the symbol combination related to the abbreviation “Triple Chililip” can be displayed as shown in FIGS. In other words, the internal winning combination “F_accurate lip” and “F_1 accurate dip” are roles that can display the symbol combination related to the abbreviation “triple dip”.

  In addition, the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” are push combinations with different symbol combinations displayed according to the push order, and are abbreviated when the push order is correct. Of the symbol combinations related to “reach eye lip” (see FIGS. 28 and 29 to be described later), any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the active line. On the other hand, when the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation “Replay” (see FIG. 28 described later) is along the active line. Displayed.

  In the present embodiment, the correct answer push order at the time of winning the internal winning combination “F_Chile Lip”, “F_Challeng Lip”, “F_1 Chilli Lip” and “F_Reach Eye Lip A” to “F_Reach Eye Lip D” Performs a first stop operation on the left reel 3L. Therefore, for example, in a game in which the internal winning combination “F_reach eye lip A” is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation “reach eye lip” is given. Such a symbol combination is stopped and displayed. Note that the present invention is not limited to this, and at the time of winning the internal winning combination "F_Chile Lip", "F_Challenging Lip", "F_1 Chick Lip" and "F_Reach Eye Lip A" to "F_Reach Eye Lip D" The pushing order of correct answers can be arbitrarily set.

  In addition, the internal winning combination “F_Maintenance Lip A” and “F_Maintenance Lip B” are not push order combinations, but are diagrams of symbol combinations related to the abbreviation “Replay” regardless of the press order (see FIG. 28 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

  Also, all of the internal winning combinations “F_Maintenance Lip_1st” to “F_Maintenance Lip_3rd” are pressing combinations with different symbol combinations displayed according to the pressing order, and are abbreviated when the pressing order is correct. Of the symbol combinations related to “Replay” (see FIG. 28 described later), any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the active line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 in the symbol combination (see FIG. 28 described later) related to the abbreviation “RT2 transition lip” is an effective line. It is displayed along.

  Also, all of the internal winning combinations “F_RT3 Lip_1st” to “F_RT3 Lip_1rd” are push combinations having different symbol combinations displayed according to the push order. When the push order is correct, the abbreviation “RT3 The symbol combination related to “Transition Lip” (see FIG. 28 described later) is displayed along the active line. On the other hand, when the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation “Replay” (see FIG. 28 described later) is along the active line. Displayed.

  Also, the internal winning combinations “F_RT4 Lip_123” to “F_RT4 Lip_3rd” are push combinations with different symbol combinations displayed according to the push order. When the push order is correct, the abbreviation “RT4 The symbol combination related to “Transition Lip” (see FIG. 28 described later) is displayed along the active line. On the other hand, when the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation “Replay” (see FIG. 28 described later) is along the active line. Displayed.

  In addition, the internal winning combinations “F_3 selection bell_1st” to “F_3 selection bell_3rd” are all pressing combinations with different symbol combinations displayed according to the pressing order, and are abbreviated when the pressing order is correct. The symbol combination related to “Bell” (see FIG. 19 described later) is displayed along the active line. On the other hand, when the pressing order is not correct, the symbol combination related to the abbreviation “Bell spilling eyes” (see FIG. 28 described later) or the symbol combination related to the abbreviation “one-shot appearance” (refer to FIG. 30 described later). Is displayed.

  Further, the internal winning combination “F_common bell” is not a push order, and can be displayed as shown in FIGS. 18 to 23 in the symbol combination (see FIG. 29 described later) related to the abbreviation “Bell” regardless of the push order. One of the various symbol combinations is displayed along the active line. In addition, the internal winning combination “F_Cabo 1” and “F_Cabo 2” are not in the pressing order, and FIG. 18 of the symbol combinations related to the abbreviation “Cactus” regardless of the pressing order (see FIG. 30 described later). Any one of the displayable symbol combinations shown in FIG. 23 is displayed along the effective line.

  In addition, the internal winning combination “weak cherry” is not a push order, and can be displayed as shown in FIGS. 18 to 23 in the symbol combination (see FIG. 30 described later) related to the abbreviation “weak cherry” regardless of the push order. One of the various symbol combinations is displayed along the active line. In addition, the internal winning combination “F_Strong Chile 1” and “F_Strong Chile 2” are not pushing orders, and the symbol combination relating to the abbreviation “Strong Cherry” regardless of the pushing order (see FIG. 30 described later). Any one of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

[Correspondence relationship between winning combination in inter-flag state and symbol combination to be stopped]
Next, with reference to FIG. 25, the correspondence between the internal winning combination and the symbol combination that is stopped and displayed in the inter-flag state will be described. FIG. 25 is a diagram showing the correspondence between the internal winning combination and the symbol combination that is displayed in a stopped state in the inter-flag state (some combinations are omitted). In particular, the bonus combination ( It is a figure which shows whether the symbol combination (combination name "C_BB1" or "C_BB2") which concerns on BB role can be displayed.

  In the correspondence table of FIG. 25, “○” mark in the “BB establishment possibility” column indicates that the symbol combination related to the BB role can be displayed, and “X” mark indicates the symbol combination related to the BB role. Indicates that it cannot be displayed. When the symbol combination related to the BB combination cannot be displayed, the symbol combination related to the combination determined to overlap with the bonus combination as the internal winning combination is displayed. For example, when the internal winning combination “F_BB1 + F_Chillilip” is won (when the internal winning combination “F_BB1” and the internal winning combination “F_Chillilip” are duplicated), as shown in FIG. 25, the internal winning combination “F_BB1” The symbol combination related to the internal symbol combination “F_Chillilip” can be stopped and displayed.

  Further, when the symbol combination related to the BB combination cannot be displayed in the inter-flag state and the symbol combination related to the combination determined to overlap with the bonus combination is displayed, the push described in FIG. Only the symbol combination at the time of the correct answer may be displayed, or only the symbol combination at the time of the incorrect push order may be displayed.

  For example, when the internal winning combination “F_BB1 + F_3 selection bell_1st” is won, as shown in FIG. 25, the symbol combination related to the internal winning combination “F_BB1” cannot be stopped and displayed, so the internal winning combination “F_3 selection bell_1st” The symbol combination related to "" is stopped and displayed, but at this time, only the symbol combination related to the abbreviation "Bell" displayed at the correct answer in the pressing order can be displayed, and the abbreviation "Bell spilled" displayed at the incorrect answer in the pressing order. Alternatively, the symbol combination relating to “one-shot” may be disabled (see FIG. 24). Also, for example, when the internal winning combination “F_BB1 + F_RT3 Lip_1st” is won, only the symbol combination related to the abbreviation “Replay” displayed when the pressing order is incorrect can be displayed, and the abbreviation “RT3 displayed when the pressing order is correct The symbol combination related to “transition lip” may be disabled (see FIG. 24).

  In the inter-flag state, as shown in FIG. 25, the bonus combination (BB combination) and any of the internal winning combinations “out”, “F_special 1”, “F_special 2”, and “F_special 3” When it is determined redundantly, the symbol combination relating to the BB combination can be stopped and displayed.

[Reel stop initial setting table]
Next, the reel stop initial setting table will be described with reference to FIG. The reel stop initial setting table defines the correspondence between the internal winning combination and various data used in the reel stop control process described later.

  The reel stop initial setting table shown in FIG. 26 defines a correspondence relationship between an internal winning combination (small winning combination number), a drawing priority table selection table number, a drawing priority table number, and a stop table number. In FIG. 26, the gaming state to be referred to and the name of the internal winning combination are also described.

  The pull-in priority table selection table number and the pull-in priority table number are data used in the pull-in priority table selection process. For example, in the reel stop initial setting table, if a pull-in priority table number corresponding to the stop table number is defined, it corresponds to the pull-in priority table number defined in the pull-in priority table (see FIG. 27 described later). Data relating to the priority order of the display combination can be acquired. On the other hand, if the pull-in priority table number corresponding to the stop table number is not defined in the reel stop initial setting table, the pull-in priority table selection table number is referred to by referring to a pull-in priority table selection table (not shown). A corresponding pull-in priority table number is determined.

  Here, the stop control (determination method of the stop symbol position) of the reel in the pachi-slot 1 of the present embodiment will be briefly described. In this embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel stops within 190 msec. Specifically, one of the number of sliding symbols “0” to “4” is added to the value of the symbol counter corresponding to the reel when the stop operation is detected, and the value obtained corresponds to the value obtained. The symbol position is determined as the symbol position where the reel rotation stops (hereinafter referred to as “scheduled stop position”). The symbol position corresponding to the value of the symbol counter corresponding to the reel when the stop operation is detected is the symbol position at which the rotation of the reel starts to be stopped (hereinafter referred to as “stop start position”).

  That is, the number of sliding pieces is the amount of rotation of the reel from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. In other words, the number of symbols passing through the middle area of the corresponding reel in the reel display window 4 in the period from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  Referring to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is a tentative one, and the acquired number of sliding pieces does not immediately determine the planned stop position of the reel. In the present embodiment, when there is an appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), a pull-in priority table (described later) The number of sliding pieces is changed with reference to FIG. Then, the sliding piece number determination data is referred to in order to determine the search order when the priorities are compared for each of the symbols from the stop start position to the 4th symbol position that is the maximum number of sliding symbols.

[Pull-in priority table]
Next, the drawing priority table will be described with reference to FIG. The pull-in priority table is a pull-in data (winning operation flag data) for each type of payout operation flag storage area (see FIG. 28 through FIG. 30 described later) in the draw priority table numbers “00” to “05”. ) And a predetermined priority order.

  The pull-in priority order table is used for searching whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols obtained based on a stop table (not shown). The priority order is data that defines the order of priority stop display (drawn) among the types of symbol combinations (winning operation flag) related to winning. In FIG. 27, for convenience of explanation, the combination data of the winning action flag is described in the drawing data (winning action flag data) column. However, in the actual drawing priority order table, each drawing data is a prize to be described later. As shown in the operation flag storage area (see FIGS. 28 to 30 described later), it is represented by 1-byte data, and a unique symbol combination (winning operation flag) is assigned to each bit in the 1-byte data. .

  In the reel stop control of this embodiment, first, the number of sliding pieces is acquired based on a stop table (not shown). However, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces based on the priority, the number is changed to the appropriate number of sliding pieces. That is, in the present embodiment, a more appropriate number of sliding symbols is determined based on the priority order of symbol combinations that allow stop display by an internal winning combination regardless of the number of sliding symbols acquired from the stop table.

  In the present embodiment, the stop display (withdrawal) of the symbol combination having the higher priority is performed in preference to the stop display of the symbol combination having the lower priority.

  In the present embodiment, as shown in FIG. 27, not only the priority of the symbol combination (winning operation flag) differs depending on the drawing priority table number, but also the number of priority divisions. Specifically, when the pull-in priority table number is “00”, the number of priority categories is set to 5, and when the pull-in priority table number is “01” or “04”, the priority is The number of divisions is 4. Further, when the pull-in priority table number is “02” or “03”, the number of priority divisions is 2, and when the pull-in priority table number is “05”, the number of priority divisions Is 3.

  Here, the priority when the pull-in priority table number is “00” will be described, and description of priorities in other pull-in priority table numbers will be omitted. The priority order “1” (highest priority order) when the pull-in priority order table number is “00” includes the combination names “C_9 sheets A_01”, “C_1 correct dust C_01”, “C_1 correct dust D_01”, and The pull-in data corresponding to “C_RT3 Lip_01” is defined.

  The priority order “2” when the pull-in priority table number is “00” includes combination names “C_high 2 sheets C_01” to “C_high 2 sheets C_09”, “C_weak 2 sheets B_01” to “C_weak”. Corresponds to “2 sheets B_03”, “C_3 sheets E_01”, “C_3 sheets E_02”, “C_9 sheets F_01” to “C_9 sheets F_03”, “C_1 exact Chile Lip B_01”, “C_Chilli Lip D_01” and “C_Chilli Lip C_01” Withdrawal data is specified.

  The priority order “3” when the pull-in priority table number is “00” includes the combination names “C_1 correct chili lip A_01”, “C_chili lip A_01”, “C_chili lip B_01”, and “C_maintenance lip E_01” to “ Pull-in data corresponding to “C_maintenance lip E_04” is defined.

  The priority order “4” when the pull-in priority table number is “00” includes combination names “C_SP1_01”, “C_SP2_01”, “C_reach eye lip P_01”, “C_reach eye lip P_02”, “C_reach”. Eye Lip O_01 "," C_Reach Eye Lip O_02 "," C_Reach Eye Lip N_01 "," C_Reach Eye Lip N_02 "," C_Reach Eye Lip M_01 "," C_Reach Eye Lip M_02 "," C_Reach Eye Lip " L_01 ”to“ C_reach eye lip L_03 ”,“ C_reach eye lip K_01 ”to“ C_reach eye lip K_03 ”,“ C_reach eye lip J_01 ”,“ C_reach eye lip I_01 ”to“ C_reach eye lip I_09 ” , “C_reach eye lip H_01” to “C_reach eye lip H_03”, “C_reach eye lip H_01” , “C_reach eye lip F_01”, “C_reach eye lip F_02”, “C_reach eye lip E_01”, “C_reach eye lip D_01”, “C_reach eye lip D_02”, “C_reach eye lip C_01” ˜ “ C_reach eye lip C_03, “C_reach eye lip B_01”, “C_reach eye lip B_02”, “C_reach eye lip A_01”, “C_maintenance lip F_01”, “C_maintenance lip F_02”, “C_maintenance lip D_01” To “C_maintenance lip D_04”, “C_maintenance lip C_01” to “C_maintenance lip C_03”, “C_maintenance lip B_01”, “C_maintenance lip B_02” and “C_maintenance lip A_01” are defined. Is done.

  Further, in the priority order “5” (lowest priority order) when the drawing priority order table number is “00”, the pull-in data corresponding to the combination names “C_BB1” and “C_BB2” are defined.

<Configuration of storage area provided in main RAM>
Next, the configuration of various storage areas provided in the main RAM 103 will be described with reference to FIGS.

[Hit request flag storage area and winning action flag storage area]
First, the configuration of the winning request flag storage area (internal winning combination storage area) and the winning action flag storage area (display combination storage area) will be described with reference to FIGS. In the present embodiment, the winning request flag storage area (flag data storage area, winning flag data storage area) and the winning action flag storage area (winning flag data storage area) have the same configuration.

  In this embodiment, the winning request flag storage area is composed of winning request storing areas 0 to 11 each represented by 1-byte data, and the winning action flag storing area is each winning operation represented by 1-byte data. It consists of storage areas 0-11. The data stored in the storage areas of the winning request flag storage area and the winning action flag storage area is only 1-byte data in the “data” column in FIGS. 28 to 30, but in FIGS. 28 to 30, For convenience of explanation, the symbol combinations of the reels associated with the bits of each storage area (in the drawing, the symbols of the left reel 3L, the symbols of the middle reel 3C and the symbols of the right reel 3R are described in this order), The name (combination name) and abbreviation, and the number of medals to be paid out are also described.

  In each of the hit request flag storage areas 0 to 11, when “1” is stored in a predetermined bit, it indicates that the internal winning combination corresponding to the predetermined bit has been won internally. In each of the winning action storage areas 0 to 11, when “1” is stored in a predetermined bit, it indicates that a display combination (winning action flag) corresponding to the predetermined bit has won. That is, when “1” is stored in a predetermined bit, it indicates that various symbol combinations of the internal winning combination corresponding to the predetermined bit are displayed on the active line.

  In the winning request flag storage area and the winning action flag storage area, as shown in FIGS. 28 to 30, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. Some have. That is, for such a flag, it means that there are a plurality of symbol combinations (combination that can be awarded) that can be stopped and displayed.

  For example, in the bit 5 of the winning request storage area 5 and the winning action storage area 5, the symbol combination “cactus 2” − “white 7” − “hat” (combination name “C_maintenance lip C_01”), the symbol combination “cactus 2” -"Chile top 1"-"hat" (combination name "C_maintenance lip C_02") and symbol combination "cactus 2"-"cactus 2"-"hat" (combination name "C_maintenance lip C_03") Three symbol combinations are assigned. Therefore, when “1” is stored in bit 5 of the hit request storage area 5, it indicates that these three symbol combinations can be stopped and displayed on the effective line. When “1” is stored in bit 5 of the winning action storage area 5, it indicates that any one of the three symbol combinations is displayed on the active line.

[Coverage storage area]
Next, the structure of the carryover combination storage area will be described with reference to FIG. In the present embodiment, the carryover combination storage area is composed of a 1-byte data storage area.

  When the internal winning combination “F_BB1” or “F_BB2” is determined as a result of the internal lottery, the internal winning combination (BB combination) is stored in the carryover combination storage area as a carryover combination. The carryover combination stored in the carryover combination storage area is held without being cleared until the corresponding symbol combination is displayed on the active line. Further, while the carryover combination is stored in the carryover combination storage area, the carryover combination is stored in the hit request storage area in addition to the internal winning combination determined by the internal lottery.

[Game state flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. The gaming state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 32, a unique bonus type or RT type is assigned to each bit in the gaming state flag storage area.

  When “1” is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when “1” is stored in bit 0 of the game state flag storage area, it indicates that the big bonus “BB” is activated and the game state is the BB game state. For example, when “1” is stored in bit 3 of the gaming state flag storage area, it indicates that the gaming state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is composed of a 1-byte data storage area and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

  For example, if the left stop button 17L is a stop button that has been pressed this time, that is, an operation stop button, “1” is stored in bit 0 of the operation stop button storage area. Also, for example, if the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, “1” is stored in bit 4. Based on the data stored in the operation stop button storage area, the main CPU 101 identifies a stop button that has been pressed this time and a stop button that has not yet been pressed.

[Push order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The pressing order storage area is composed of a 1-byte data storage area and stores a pressing order flag consisting of 1 byte.

  In the pressing order flag, the type of stop button pressing order is assigned to each bit. For example, when the stop button pressing order is “left, middle, right”, “1” is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. In this embodiment, the symbol code storage area is composed of symbol code storage areas 0 to 11 each represented by 1-byte data. The symbol code storage area has the same configuration as the winning request flag storage area and the winning action flag storage area (see FIGS. 28 to 30).

  In the symbol code storage area, “1” is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the active line. After all the reels are stopped, the symbol codes corresponding to the display combination (winning operation flag) are stored in the symbol code storage areas 0 to 11.

[Relationship between internal winning combination and various subflags]
In the general gaming state and the ART gaming state, various data tables are referred to in various lotteries by the main control circuit 90. As parameters used at this time, in the present embodiment, not only the internal winning combination but also the internal winning combination is supported. Various parameters with different names (hereinafter referred to as “sub-flag (first sub-flag)”, “sub-flag EX (second sub-flag)”, and “sub-flag D”)) are also used. Therefore, in the present embodiment, the main control circuit 90 performs processing for converting the internal winning combination into various subflags (see subflag conversion processing, flag conversion processing, and subflag compression processing in FIG. 104 described later). In the present embodiment, as information (communication parameter) regarding the internal winning combination, a sub flag is set in the start command and transmitted from the main control circuit 90 to the sub control circuit 200.

  Here, with reference to FIG. 36 and FIG. 37, the correspondence between the internal winning combination and various subflags will be described. FIG. 36 is a diagram showing a correspondence relationship between an internal winning combination (small winning number) and various subflags, and FIG. 37 is a diagram showing a correspondence relationship between an internal winning combination (special prize winning number) and a subflag.

  In the flag conversion process of the present embodiment, first, a plurality of internal winning combinations belonging to the same type are combined into one subflag. In the present embodiment, as shown in FIG. 36, the flag conversion process has 32 types of internal winning combinations (small winning combination numbers) related to the small combination and the replay combination, and 18 types of sub-flags (“01” to “18”). : Flag data). For example, the internal winning combination “F_maintenance lip — 1st (10: small combination winning number)” to “F_maintenance lip — 3rd (12)” are collected into the sub flag “push order lip 1 (09: flag data)”. Note that the sub-flag “losing (00)” is assigned to the internal winning combination “out”.

  In the flag conversion process of the present embodiment, as shown in FIG. 36, 19 types of subflags (“00” to “18”) including the subflag “losing (00)” are converted into 9 types of subflags EX (“00 To “08”: flag data). Therefore, in this conversion process, the subflag data can be further compressed. At this time, in this embodiment, the sub flag is converted into the sub flag EX by lottery (flag conversion lottery). Specifically, it is converted as follows.

  The sub-flag “losing (00)” is converted to the sub-flag EX “losing (00)” regardless of the result of the flag conversion lottery, and the sub-flag “double-chilli (01)” is irrespective of the result of the flag converting lottery. Sub-flag EX is converted to “Replay (01)”.

  When the sub-flag “Triple Chile Lip A (02)” and the sub-flag “Triple Chile Lip B (03)” win the flag conversion lottery (in the case of “with conversion” described later), the sub-flag EX “determined role (06)” Or, when it is converted to “triple dust lip (07)” and the flag conversion lottery is non-winning (in the case of “no conversion” described later), it is converted to the sub flag EX “replay (01)”.

  When the sub-flag “reach eye lip 1 (04)” to “reach eye lip 4 (07)” wins the flag conversion lottery, it is converted into the sub flag EX “determined combination (06)” or “reach eye lip (08)”. If the flag conversion lottery is not won, it is converted to the sub flag EX “Replay (01)”.

  The subflags “Replay (08)” and “Push Order Lip 1 (09)” to “Push Order Lip 3 (11)” are converted to the subflag EX “Replay (01)” regardless of the result of the flag conversion lottery, The subflags “push order bell (12)” and “common bell (13)” are converted into the subflag EX “bell (02)” regardless of the result of the flag conversion lottery.

  The sub-flags “cactus (14)”, “weak cherry (15)”, and “strong cherry (16)” are sub-flags EX “cactus (03)” and “weak cherry (04)” regardless of the result of the flag conversion lottery. And “strong cherry (05)”. Further, the sub-flags “reach eyes 1 (17)” and “reach eyes 2 (18)” are converted into the sub-flag EX “losing (00)” regardless of the result of the flag conversion lottery.

  As described above, in the present embodiment, the sub-flags “triple lip A (02)”, “triple lip B (03)” and “reach eye lip 1 (04)” to “reach eye lip 4 (07) ) ”Only becomes the target of flag conversion lottery. The lottery table used for the flag conversion lottery described above will be described in detail later.

  Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, nine types of subflags EX (“00” to “08”) are converted into seven types of subflags D (“00” to “06”). The Therefore, in this conversion process, the subflag data can be further compressed. In this conversion process, lottery is not performed, and conversion is performed in association with the subflag EX and the subflag D as follows.

  The subflags EX “losing (00)”, “replay (01)”, and “bell (02)” are converted into subflags D “losing (00)”. Sub flag EX “cactus (03)” is converted to sub flag D “cactus (01)”, sub flag EX “weak cherry (04)” is converted to sub flag D “weak cherry (02)”, and sub flag EX “strong” Cherry (05) "is converted to sub-flag D" strong cherry (03) ".

  Further, the subflag EX “determined combination (06)” is converted into a subflag D “determined combination (04)”, and the subflag EX “triple-tilt (07)” is converted into sub-flag D “triple-tilt (05)”. Then, the sub flag EX “reach eye lip (08)” is converted into a sub flag D “reach eye lip (06)”.

  Also, in the flag conversion process of the present embodiment, as shown in FIG. 37, both the internal winning combination “F_BB1 (01: special prize winning number)” and “F_BB2 (02)” are converted to the subflag “BB”. .

[Gameability during sub-flag EX conversion]
Here, an example of the process of converting the above internal winning combination into the sub flag and the sub flag EX and an example of the game at the time of the sub flag EX conversion will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing a flag conversion process when the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is determined, and FIG. 38B is an internal winning combination “F_Reach Eye Lip A” to “F_ It is a figure which shows the flag conversion process in case one of "reach eyes lip D" is determined.

  In the pachi-slot 1 of the present embodiment, any one of the internal winning combination “F_Challenging Lip”, “F_1 Chanting Lip”, and “F_Reach Eye Lip A” to “F_Reach Eye Lip D” is alone during the RT4 gaming state. If it is determined as an internal winning combination, a flag conversion lottery is performed. In the present embodiment, when this flag conversion lottery is won, a special privilege (for example, an additional number of ART games or CT winning) is given.

  For example, when the internal winning combination “F_Challenging Lip” or “F_1 Chanting Lip” is determined, as shown in FIG. 38A, the internal winning combination “F_Challenging Lip” and “F_1 Chick Lip” are sub-flags “Three consecutive”, respectively. Converted to “Chilli Lip A (02)” and “Triple Chili Lip B (03)”.

  Next, when the sub-flag “triple dust lip A (02)” and “triple dust lip B (03)” win the flag conversion lottery, the sub-flag EX “triple dust lip (07)” or “determined role (06)” Converted. On the other hand, if the flag conversion lottery is non-winning, both the sub-flags “triple chilli lip A (02)” and “triple chilli lip B (03)” are converted to the sub-flag EX “replay (01)”. .

  Note that, as described with reference to FIG. 24, when the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is won, the symbol combination related to the abbreviated “Triple Chilli Lip” is displayed at the correct push order, and the push order is not correct. When the answer is correct, the symbol combination related to the abbreviation “Replay” is displayed. Therefore, in the present embodiment, when the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is determined and the flag conversion lottery is won, the internal winning combination “F_Challenging Lip” and “F_1 Chanting Lip” Are both treated as a combination of the sub flag EX “Triple Chile Lip (07)” or “Determined Combination (06)”.

  When the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is converted to the sub-flag EX “Triple Chilelip (07)” or “Determining Role (06)” by this flag conversion process, the abbreviation “Triple” Information for displaying the symbol combination related to “Chilelip” is notified (for example, information indicating that the Chile symbol is aimed at the player by pushing forward) is notified. On the other hand, when the flag conversion lottery becomes non-winning in this flag conversion process and the internal winning combination “F_acceptance lip” or “F_1 accuracy dip” is converted to the sub flag EX “Replay (01)”, the abbreviation “Replay” is obtained. Information for displaying such a symbol combination is notified (for example, a pressing order other than forward pressing (anomalous pressing) is notified).

  Further, for example, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined, as shown in FIG. 38B, the internal winning combinations “F_reach eye lip A” to “ F_reach eye lip D "is converted into sub-flags" reach eye lip 1 (04) "to" reach eye lip 4 (07) ", respectively.

  Next, when the sub-flags “reach eye lip 1 (04)” to “reach eye lip 4 (07)” win the flag conversion lottery, the sub flag EX “reach eye lip (08)” or “determined role (06)” Converted. On the other hand, if the flag conversion lottery is not won, the subflags “reach eye lip 1 (04)” to “reach eye lip 4 (07)” are converted to the subflag EX “replay (01)”.

  Note that, as described with reference to FIG. 24, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is won, the symbol combination related to the abbreviation “reach eye lip” when pressing correctly Is displayed, and the symbol combination related to the abbreviation “Replay” is displayed when the pressing order is incorrect. Therefore, in this embodiment, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined and the flag conversion lottery is won, the internal winning combination “F_reach eye” Any of “Lip A” to “F_reach eye lip D” is treated as a role of the sub flag EX “reach eye lip (08)” or “determined role (06)”.

  When the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is converted into, for example, the sub flag EX “reach eye lip (08)” or “determining role (06)” by this flag conversion process. , Information for displaying the symbol combination related to the abbreviation “reach eye lip” is notified (for example, information indicating that the symbol “white 7” is aimed by being pushed forward is notified to the player). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is converted to the sub flag EX “replay (01)”, the abbreviation Information for displaying the symbol combination related to “Replay” is notified (for example, a pressing order other than forward pressing (anomalous pressing) is notified).

  Further, in the present embodiment, in the flag conversion process shown in FIG. 38A or 38B, when the player performs a stop operation according to the notification after winning the flag conversion lottery, the abbreviation “triple lip” or “reach eye lip” is applied. The symbol combination is stopped and displayed on the active line, and a special privilege is given. This granting process substantially gives a special privilege to the player in response to the fact that the pachislot 1 wins the flag conversion lottery, but for the player, the abbreviation “3 By displaying the symbol combination related to “ream chililip”, it can be felt that a special privilege has been given.

  In order to improve the gameability of the pachislot, it may be preferable that the appearance frequency of the symbol combination to which a privilege is given is different depending on the state. Stop control (displayed symbol combination) varies depending on the type of internal winning combination. Therefore, as a method of varying the appearance frequency of the symbol combination to which a privilege is given depending on the state, the winning probability of the internal winning combination is varied. (In Pachislot 1, the winning probability of the internal winning combination can be varied depending on whether the bonus is activated or depending on the RT state. For example, as the RT state corresponding to the ART gaming state, only the RT4 state is possible. In addition, a method of providing another RT state such as the RT6 state or the RT7 state is also conceivable). However, since the opportunity to change the winning probability of the internal winning combination (RT state transition opportunity) is limited, this method lacks flexibility in terms of improving game play (amusement).

  On the other hand, in the pachislot machine 1 of the present embodiment, in addition to the internal lottery for determining the internal winning combination without changing the winning probability of the internal winning combination, the flag conversion lottery and the notification based on the lottery result are performed. The appearance frequency of the symbol combination to which the privilege is given can be flexibly changed according to the state. That is, in a state where it is easy to win the flag conversion lottery, the appearance frequency of the symbol combination to which the privilege is given can be increased, and conversely, in a state where it is difficult to win the flag conversion lottery, the appearance of the symbol combination to which the privilege is given is given. The frequency can be lowered.

<Gameability in general gaming state>
Next, with reference to FIGS. 39A to 39C, the flow of the game in the general game state will be described. In the pachi-slot 1 of the present embodiment, in the general gaming state, the gaming state transitions from the normal gaming state to the CZ, and then the gaming state transitions from the CZ to the ART gaming state, so that the general gaming state (non-ART gaming state) ) To the ART gaming state (see FIGS. 14A and 14B).

  FIG. 39A is a diagram illustrating a game flow when the game state shifts from the normal game state to the CZ during the general game state. As shown in FIG. 39A, the normal gaming state has a low-probability state and a high-probability state as CZ lottery states. The low-probability state and the high-probability state are states in which expectations for winning a CZ lottery performed during the normal gaming state are different from each other. The low-probability state is a state in which it is difficult to win a CZ lottery. It is in a state where it is easy to win a lottery. When the CZ lottery performed in the game in the normal game state is won, the game state shifts from the normal game state to the CZ.

  In the pachislot machine 1 of the present embodiment, a plurality of chance zones “CZ1”, “CZ2”, and “CZ3” are provided as CZ (chance zone). CZ1 to CZ3 are chance zones with different expectations for winning an ART lottery performed in a game in CZ, CZ3 is a chance zone that must win an ART lottery, and CZ1 and CZ2 have a predetermined probability. This is a chance zone to win the ART lottery. In CZ lottery performed in a game in the normal gaming state, not only CZ winning / non-winning but also the type of CZ (any one of CZ1 to CZ3) to be transferred at the time of winning is determined (see FIG. 41 described later).

  FIG. 39B is a diagram illustrating a game flow when the gaming state shifts from the general gaming state CZ1 and CZ2 to the ART gaming state. CZ1 and CZ2 are both composed of a first half and a second half. The first half is a period in which the rank of expectation for winning an ART lottery performed in a game in CZ is promoted, and the second half is a result of a lottery result of an ART lottery based on the rank (in this embodiment, a character It is a period to notify by (battle production).

  In CZ1, six stages of modes (modes 1 to 6) are prepared as ranks, and the higher the mode, the higher the degree of expectation for winning an ART lottery. In the first half of CZ1, a game is continuously performed for a period of a first predetermined number of games (for example, a maximum of 12 games), and a mode promotion lottery is performed based on an internal winning combination. Then, in the first game of the second half of CZ1, ART lottery is performed based on the mode promoted in the first half (mode at the end of the first half).

  In CZ2, 10 stages of points are prepared as ranks, and the higher the points, the higher the degree of expectation for winning an ART lottery. In the first half of CZ2, a game is continuously performed for a period of a second predetermined number of games (for example, a maximum of 15 games), and a point lottery is performed based on an internal winning combination. Then, in the first game in the second half of CZ2, ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

  In the second half of CZ1, a battle effect is performed in which the teammate character and the enemy character A battle each other. In the second half of CZ2, a battle effect is performed in which the teammate character and the enemy character B battle each other. This battle effect is performed over a game for a period of a third predetermined number of games (for example, a maximum of 4 games). In addition, the victory or defeat of the battle effect is managed (determined) based on the result of the ART lottery. Enemy character wins by directing.

  In each latter half of CZ1 and CZ2 (during battle production), ART lottery is performed based on each game and internal winning combination. Then, when the ART lottery is won, the result of the battle effect is rewritten. For example, when a so-called “rare” combination is determined as an internal winning combination during a battle presentation, an ART lottery is performed, and the result of the battle presentation is rewritten based on the result.

  In CZ1 and CZ2, if the ART is not won, the player loses the battle in the latter half, and basically the gaming state shifts to the normal gaming state. On the other hand, in CZ1 and CZ2, when the player wins ART, the player wins in the second half battle effect, and then the gaming state shifts from CZ to normal ART via the ART preparation state. In this embodiment, a freeze may occur in the game in the first half of CZ1 and CZ2, and in this case, the game state passes from the CZ via the ART ready state and is not a normal ART but a CT (addition). (Chance zone).

  FIG. 39C is a diagram showing a game flow when the gaming state shifts from the general gaming state CZ3 to the ART gaming state. In CZ3, a game is continuously performed for a period of a fourth predetermined number of games (for example, a maximum of 17 games). In CZ3, an ART lottery is performed based on each game and an internal winning combination.

  CZ3 ends when the ART lottery is won, and after the next game, the gaming state shifts from CZ3 to the CT (additional chance zone) via the ART preparation state. In CZ3, a freeze may occur. In this case, the game state is transferred from CZ3 to the CT (additional chance zone) via the ART preparation state after the next game. On the other hand, in CZ3, when the game period (fourth predetermined number of games) of CZ3 has passed without winning the ART lottery, the game state shifts from CZ3 to the normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state is confirmed.

<Various data tables used during the general gaming state>
Next, with reference to FIGS. 40 to 45, various data tables used in the lottery process relating to game play performed in the general game state will be described. Various data tables described below are stored in the main ROM 102.

  Also, in the various data tables shown below, lottery value information is conceptually shown. “0” in the data table means that a lottery value corresponding to the winning probability “0%” is defined, and “extremely low” means a lottery corresponding to the winning probability “0% to less than 1%”. It means that a value is defined, and “extremely low” means that a lottery value corresponding to a winning probability “less than 1% to 10%” is defined. “Low” in the data table means that a lottery value corresponding to the winning probability “10% to less than 30%” is defined, and “medium” means the winning probability “30% to less than 60%”. ”Means that a lottery value corresponding to the winning probability“ 60% to less than 80% ”is prescribed. Furthermore, “extremely high” in the data table means that a lottery value corresponding to the winning probability “80% to less than 99%” is defined, and “extremely high” means that the winning probability is “99% to 100%”. A lottery value corresponding to “less than%” is defined, and “confirmed” means that a lottery value corresponding to the winning probability “100%” is defined.

  In the various data tables shown below, the random number register 1 of the random number circuit 110 sequentially subtracts the random numbers for lottery extracted from the predetermined numerical range (0 to 65535) by the prescribed lottery value. The internal lottery is performed by determining whether the result of the subtraction is negative (whether a so-called “digit” has occurred). In the present embodiment, the example in which the winning / non-winning is determined by subtracting the lottery value from the random number for lottery in the lottery processing related to the game performance performed in the general gaming state is described, but the present invention is not limited to this. The lottery value is added to the extracted random number for lottery, and whether or not the addition result exceeds 65536 (whether or not so-called “digit overflow” has occurred) is determined, and the winning / non-winning is determined. Also good.

[Normal high probability lottery table]
First, with reference to FIG. 40A and 40B, the normal medium-high probability lottery table used in the transition lottery in the CZ lottery state (low probability and high probability) will be described. In the pachi-slot 1 of the present embodiment, not only the lottery of the CZ lottery state is performed based on each game and the internal winning combination, but also at the end of the bonus or at the end of CZ, ART, etc. A lottery transition lottery is performed. FIG. 40A is a configuration diagram of a normal middle / high probability lottery table that is referred to in each game during the normal gaming state, and FIG. 40B is a normal middle / high probability referred to, for example, when a setting is changed, at the end of a bonus, or at the end of CZ or ART. It is a block diagram of a probability lottery table. Note that the name of the internal winning combination shown in FIG. 40A corresponds to the name of the subflag described above.

  The normal medium / high probability lottery table shown in FIG. 40A includes each combination of the current CZ lottery state and the internal winning combination, the lottery result (low probability / high probability) of the CZ lottery state after the transition, and each lottery result. The correspondence relationship with the information of the lottery value associated with the rule is defined.

  As is clear from the normal medium-high probability lottery table shown in FIG. 40A, when the current CZ lottery state has a low probability, when the internal winning combination is a combination corresponding to the sub-flag “weak cherry”, The lottery state easily shifts with high probability. On the other hand, when the current CZ lottery state has a high probability, the internal winning combination is a combination corresponding to any of the sub-flags “common bell”, “cactus”, “weak cherry”, and “strong cherry” In addition, the lottery state of CZ is maintained with high probability.

  The normal middle / high probability lottery table shown in FIG. 40B is a lottery associated with each lottery result, each situation when referring to the table, lottery result (low probability / high probability) of the CZ lottery state after the transition. Specifies the correspondence with value information. As is apparent from the normal medium-high probability lottery table shown in FIG. 40B, the CZ lottery state always shifts to a high probability at the end of the bonus.

[CZ lottery table]
Next, a CZ lottery table used in the CZ lottery will be described with reference to FIGS. 41A and 41B. FIG. 41A is a configuration diagram of a CZ lottery table used when a CZ lottery is performed based on an internal winning combination during a normal gaming state, and FIG. 41B shows a CZ pullback when, for example, CZ fails or ART ends. It is a block diagram of the CZ lottery table used when performing CZ lottery of whether to perform. Note that the name of the internal winning combination shown in FIG. 41A corresponds to the name of the subflag described above.

  The CZ lottery table shown in FIG. 41A includes combinations of the current CZ lottery state and the internal winning combination, CZ1, CZ2, and CZ3 winning / non-winning (lottery results), and lotteries associated with the lottery results. Specifies the correspondence with value information. As is clear from the CZ lottery table shown in FIG. 41A, when the current CZ lottery state has a high probability, the CZ lottery is won more than when the current CZ lottery state has a low probability. Probability increases.

  The CZ lottery table shown in FIG. 41B is a correspondence relationship between winning / non-winning (lottery results) of CZ1, CZ2, and CZ3 and lottery value information associated with each lottery result when CZ fails or ART ends. Is specified. At the time of CZ failure (when the ART lottery in CZ1 and CZ2 is not won) or at the end of the ART gaming state, the CZ pullback lottery is performed using this CZ lottery table.

[Mode up lottery table during CZ1]
Next, with reference to FIG. 42, the CZ1 medium mode lottery table used in the CZ1 mode up lottery performed in the first half of the CZ1 will be described. FIG. 42 is a configuration diagram of the mode-up lottery table during CZ1. Note that the names of the internal winning combinations shown in FIG. 42 correspond to the names of the subflags described above.

  The mode-up lottery table during CZ1 shows the correspondence between each combination of the current mode and the internal winning combination, the result of mode-up lottery (winning / non-winning), and lottery value information associated with each lottery result. Is specified. As shown in FIG. 44A described later, in CZ1, the probability of winning an ART lottery increases as the mode increases (the mode value increases). When the mode increases to mode 6, the ART lottery is always won.

  42. The lottery result “mode 1 UP” in FIG. 42 means that the CZ1 mode is increased by one step, and the lottery result “mode 2 UP” means that the CZ1 mode is increased by two steps. Therefore, for example, in the situation where the current mode is mode 2, if the lottery result “mode 2 UP” is won, the mode of CZ1 is raised from mode 2 to mode 4. Further, for example, when a lottery result “Mode 6 UP_Freeze” is won, a freezing occurs, and the determination of the ART lottery and the grant of CT are determined.

[CZ2 medium point lottery table]
Next, a CZ2 point lottery table used in the CZ2 point-up lottery performed in the first half of CZ2 will be described with reference to FIG. FIG. 43 is a configuration diagram of the point lottery table in CZ2. Note that the names of the internal winning combinations shown in FIG. 43 correspond to the names of the subflags described above.

  The point lottery table in CZ2 shows the correspondence between each combination of the current point and the internal winning combination, the result of the point-up lottery (winning / non-winning), and lottery value information associated with each lottery result. Stipulate. As shown in FIG. 44B, which will be described later, in CZ2, the probability of winning an ART lottery increases as the point increases, and when the point increases to “point 10”, the ART lottery is always won. The lottery result “point 2 UP” in FIG. 43 means that “2” is added to the current CZ2 point. For example, in the situation where the current point is “2”, the lottery result “ When winning “Point 2 UP”, the point of CZ2 increases from “2” to “4”. Further, for example, when a lottery result “point 10 UP_freeze occurrence” is won, a freeze occurs, and the determination of the ART lottery and the grant of CT are determined.

[CZ ART lottery table]
Next, with reference to FIGS. 44A to 44C and FIG. 45, an ART lottery table in CZ used in an ART lottery executed during CZ will be described. 44A is a configuration diagram of an ART lottery table in CZ (for CZ1) used in the first game of the second half of CZ1, and FIG. 44B is an ART in CZ used in the first game of the second half of CZ2. FIG. 44C is a block diagram of a lottery table (for CZ2), and FIG. 44C is a block diagram of an ART lottery table for CZ (used in the latter half battle for CZ1 and CZ2) used in the latter half of CZ1 and CZ2. FIG. 45 is a configuration diagram of the CZ ART lottery table (for CZ3) used in the ART lottery executed during CZ3. Note that the names of the internal winning combinations shown in FIGS. 44C and 45 correspond to the names of the subflags described above.

  The ART lottery table in CZ (for CZ1) shown in FIG. 44A defines the correspondence between the current mode, the ART lottery result (presence / absence of winning), and lottery value information associated with each lottery result. . 44B, the ART lottery table in CZ (for CZ2) shows the correspondence between the current point, the ART lottery result (presence / absence of winning), and lottery value information associated with each lottery result. Stipulate.

  As is clear from the ART lottery table during CZ (for CZ1) and the ART lottery table during CZ (for CZ2), the higher the rank (mode or point) of the first half of CZ1 and CZ2, the easier it is to win the ART lottery.

  44C, the ART lottery table during CZ (common for CZ1 and CZ2 during the second half battle) includes an internal winning combination, an ART lottery result (presence / absence of winning), and lottery value information associated with each lottery result. Specify the correspondence of. As is clear from the CZ ART lottery table (common for CZ1 and CZ2 during the latter half of the battle), in the latter half of CZ1 and CZ2, the role corresponding to the sub flag “weak cherry”, “cactus” or “strong cherry” ) Is determined as an internal winning combination, the ART lottery is won with a predetermined probability.

  The ART lottery table in CZ (for CZ3) shown in FIG. 45 is a combination of the number of CZ3 digest games and an internal winning combination, an ART lottery result (presence / absence of winning), and a lottery associated with each lottery result. Specifies the correspondence with value information. As is clear from the ART lottery table during CZ (for CZ3), in the present embodiment, when the ART lottery is won in CZ3, the CT is always won.

<Gameability during normal ART>
Next, with reference to FIG. 46A and 46B, the flow of the game in game ART is demonstrated. In the pachi-slot 1 of the present embodiment, as described above, the ART gaming state is normally provided with ART and CT (see FIGS. 14A and 14B), and the inside of CT is added as a chance zone. Therefore, in this embodiment, the player plays a game aiming at the transition to CT in a game during normal ART.

[Transition mode from normal ART to CT]
FIG. 46A is a diagram showing a transition state of the gaming state from normal ART to CT. In the pachislot machine 1 of this embodiment, as shown in FIG. 46A, when a CT lottery performed during normal ART is won, the gaming state shifts from normal ART to CT. As shown in FIG. 46A, the pachislot machine 1 of this embodiment is provided with an ART level and a CT lottery state as parameters that affect various lotteries performed during normal ART.

  As the ART level, four levels of level 1 to level 4 are provided, and this ART level is controlled (determined) mainly based on the number of continuous (digestion) games in normal ART. The ART level affects the determination of the CT lottery state and the flag conversion lottery during normal ART described later.

  As the CT lottery state, there are four stages of low probability, normal, high probability, and ultra-high probability. The CT lottery state is controlled mainly based on the ART level or the internal winning combination during normal ART ( It is determined. The CT lottery state affects a CT lottery performed during normal ART, a flag conversion lottery during normal ART, which will be described later, and the like.

[Flag conversion during normal ART]
As described above, in the pachislot machine 1 of the present embodiment, during the RT4 state, that is, during the ART gaming state, the internal winning combination “F_Challenging Lip”, “F_1 Challenging Lip” and “F_Leaching Lip A” to “F_” When any one of the “reach eyes lip D” is determined as an internal winning combination alone, a flag conversion lottery is performed, and a special privilege (for example, an additional number of ART games or CT winning) is given according to the lottery result. . FIG. 46B is a diagram showing an outline of a flag conversion lottery method performed during normal ART.

  In the present embodiment, as shown in FIG. 46B, flag conversion lottery is performed with reference to the ART level and the CT lottery state during normal ART. As a result, when a flag conversion lottery is won, a special privilege is given and a symbol combination related to the abbreviation “triple chili lip” or a symbol combination related to the abbreviation “reach eye lip” is stopped and displayed on the active line. Navigation (for example, notification of information indicating that a predetermined symbol is aimed by forward pressing) is performed. On the other hand, when the flag conversion lottery is not won, navigation for displaying the symbol combination related to the abbreviation “Replay” on the active line (for example, notification of the pressing order other than the forward pressing) is performed.

  And if a player performs stop operation according to this alerting | reporting (navigation), the symbol combination according to the alerting | reporting content will be stopped and displayed on an effective line. Specifically, when winning the flag conversion lottery, the symbol combination related to the abbreviation “triple lip” or the symbol combination related to the abbreviation “reach eye lip” is stopped on the active line, and the flag conversion lottery is not displayed. In the case of winning, the symbol combination related to the abbreviation “Replay” is stopped and displayed on the active line.

<Various data tables used during normal ART>
Next, with reference to FIGS. 47 to 51, various data tables used in the lottery process during the normal ART will be described. Various data tables described below are stored in the main ROM 102.

[ART flag conversion lottery table]
47A and 47B are configuration diagrams of a flag conversion lottery table during ART used in a flag conversion lottery performed during normal ART.

  In the pachi-slot 1 according to the present embodiment, flag conversion lottery during normal ART is performed in two stages. More specifically, when the internal winning combination “F_Challenging Lip” or “F_1 Challenging Lip” is won, the first stage flag conversion lottery is performed. A second stage flag conversion lottery is performed. Then, when the second stage flag conversion lottery is won, the internal winning combination “F_accurate lip” or “F_1 credible lip” is converted to the sub flag EX “triple dip”. On the other hand, if the first-stage flag conversion lottery or the second-stage flag conversion lottery is non-winning, the internal winning combination “F_acceptance lip” or “F_1 accuracy dip” is converted to the sub-flag EX “replay”. (Handles as a normal replay role). When any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” wins, only the second-stage flag conversion lottery is performed.

  47A is a block diagram of an ART flag conversion lottery table used in the first stage flag conversion lottery, and FIG. 47B is a block diagram of an ART flag conversion lottery table used in the second stage flag conversion lottery. is there.

  The flag conversion lottery table during ART shown in FIG. 47A is an internal winning combination (“F_Challenging Lip” or “F_1 Chanting Lip”) and the lottery result of the first stage flag conversion lottery (no conversion / with conversion (provisional)) And the correspondence between lottery value information associated with each lottery result.

  47B shows a flag conversion lottery table during ART, each combination of an internal winning combination, an ART level, and a CT lottery state, a lottery result (no conversion / with conversion) of a second stage flag conversion lottery, and each lottery result. A correspondence relationship with lottery value information associated with is defined. Note that in a game until a CT is won once in normal ART, the table in the “first time (until once CT is won)” column of the item “ART level” in FIG. 47B is referred.

  In this embodiment, as shown in FIGS. 47A and 47B, in the stage and second stage flag conversion lottery using the ART flag conversion lottery table, random values (0 to 0) with a probability denominator of “256” are used. A lottery is performed using (255). Therefore, in the present embodiment, the above-described two-stage flag conversion lottery can be regarded as a lottery that is substantially the same as a lottery performed once using a random number with a probability denominator “65536”.

  In recent pachislot machines, a lottery (ART lottery, etc.) related to a ball that was conventionally performed on the sub-control board 72 side (hereinafter referred to as “sub-side”) is performed on the main control board 71 side (hereinafter referred to as “main side”) There is a need to do. However, since the capacity of the main storage means (main ROM 102) is limited to a small capacity, there is a demand for a mechanism that enables lottery without reducing the game capacity while suppressing an increase in processing capacity.

  In this regard, in the pachislot machine 1 of the present embodiment, the lottery with the probability denominator “256” can be performed in two stages, so that the lottery with the probability denominator “65536” can be performed. Side capacity increase can be suppressed. Also, in the second lottery, the ART level, CT lottery status, etc. are referred to, so that it is possible to perform flag conversion lottery according to the current state as well as the internal winning combination. A flag conversion lottery can be performed.

[ART level determination table]
48A and 48B are configuration diagrams of an ART level determination table used when determining the ART level. The ART level determination process is performed when the ART is determined to shift to the ART gaming state and during normal ART. FIG. 48A is a configuration diagram of an ART level determination table used at the time of winning the ART, and FIG. 48B is a configuration diagram of an ART level determination table used during normal ART.

  The ART level determination table shown in FIG. 48A defines the correspondence between ART levels 1 to 4 (lottery results) and lottery value information associated with each ART level. In the present embodiment, ART level 2 is determined as the ART level when freezing occurs when the ART is won.

  The ART level determination table shown in FIG. 48B is a lottery associated with each combination of the current ART level and the number of elapsed (digested) games of normal ART, the various ART levels of the transfer destination, and each ART level of the transfer destination. Specifies the correspondence with value information. Further, the ART level determination table shown in FIG. 48B is associated with each combination of the current ART level and the number of elapsed games of the normal ART at the time of CT entry, various ART levels of the transfer destination, and each ART level of the transfer destination. The correspondence relationship with the information of the lottery value obtained is defined. In other words, during normal ART, the ART level can be shifted not only when the number of elapsed (digested) games of normal ART reaches a predetermined number of games, but also when the level of CT enters normal ART. Can be migrated.

[Normal ART medium-high probability lottery table]
FIG. 49 is a configuration diagram of a normal ART medium high probability lottery table used when determining the CT lottery state during normal ART.

  The normal ART medium / high probability lottery table shows the correspondence between each combination of the current CT lottery state and the internal winning combination, various CT lottery states at the transition destination, and lottery value information associated with each CT lottery state. Stipulate. Note that the names of the internal winning combinations shown in FIG. 49 correspond to the names of the subflags described above.

  As is clear from the normal ART medium / high probability lottery table, the internal winning combination corresponding to the sub-flag “triple chilli lip (triple chilli lip A and triple chilli lip B)” and the sub-flag “reach lip (reach lip 1 to 4)” When is won, the CT lottery state easily shifts (falls) to “low probability”. However, as shown in FIG. 50, which will be described later, when the internal winning combination corresponding to the sub-flag “triple chili lip” or “reach eye lip” is won, even if the CT lottery state falls, The lottery must be won.

[CT lottery table during ART]
FIG. 50 is a configuration diagram of a CT lottery table during ART used in CT lottery performed during normal ART.

  In the ART CT lottery table, each combination of the current CT lottery state and the internal winning combination, various lottery results of CT lottery (non-winning / normal CT / high probability CT), and lottery associated with each lottery result Specifies the correspondence with value information. Note that the names of the internal winning combinations shown in FIG. 50 correspond to the names of the subflags described above.

  In this embodiment, the sub-flag “cactus”, “weak cherry”, “strong cherry”, “triple chilli lip (triple chilli lip A and triple chilli lip B)”, “reach lip (reach lip) 1 to 4) ”or“ BB ”is determined, in the CT lottery process using the CT lottery table during ART, the CT lottery using random numbers in the range where the probability denominator is“ 256 ” Is done. If an internal winning combination other than these combinations is determined as an internal winning combination (for example, a combination corresponding to the sub-flag “replay”, “common bell”, “push order bell”, etc.), the CT during ART In the CT lottery process using the lottery table, a CT lottery using a random number value in a range where the probability denominator is “65536” is performed.

  In the pachislot machine 1 of the present embodiment, two types of CT called “normal CT” and “high probability CT” are provided as CT. The normal CT and the high probability CT have different expectations of the number of ART games added in the CT (additional chance zone), and the high probability CT is more likely to add a larger number of ART games than the normal CT. (Refer to FIG. 55 described later).

[Normal lottery table during ART]
FIG. 51 is a configuration diagram of the normal ART extra lottery table used in the extra lottery for the number of ART games performed during the normal ART. Note that the names of the internal winning combinations shown in FIG. 51 correspond to the names of the subflags described above.

  The extra lottery table during the normal ART defines a correspondence relationship between the internal winning combination, various lottery results of the extra lottery (non-winning / additional 10G to 300G), and lottery value information associated with each lottery result.

<Gameability during CT>
Next, with reference to FIGS. 52A to 52C, the flow of games during CT will be described. 52A and 52B are diagrams showing an outline of the game flow during the CT when the sub flag EX “Triple Chile Lip” is won, and FIG. 52C shows an overview of the flag conversion process performed during the CT. FIG.

[Game contents during CT]
In the pachislot machine 1 of the present embodiment, one set of 8 games (8 games) is played in CT. During the CT period, the number of ART games is added and lottery is performed based on each game and internal winning combination. If the extra lottery is won, the number of CT game unit games (number of games) is not subtracted. On the other hand, if the extra lottery is non-winning, the number of CT game unit games (game) Number) is subtracted. Therefore, CT does not end for games with the number of ART games added during the CT period, and CT ends when a game in which the number of ART games is not added is executed eight times in the same set. .

  Further, in this embodiment, as shown in FIGS. 52A and 52B, when the sub flag EX “Triple Chile Lip” is won during the CT period, that is, the internal winning combination “F_Probable Chile Lip” or “F_1 Probable Chile Lip” is won. In addition, when the flag conversion lottery is won, one set of 8 CT games is reset (stocked). Then, the reset (stocked) CT game set is started after the CT game set is completed.

  For example, after a unit game that is non-winning for the number of ART games in the same set is played 7 times, if a CT game in which the number of ART games is not added is performed once, CT ends. If the sub-flag EX “Triple Chile Lip” is won, the CT game is reset. As a result, after the CT game is reset, the CT does not end until the number of ART games is increased and the unit game that is not won by lottery is performed eight times. Therefore, the CT game period becomes longer as the sub-flag EX “Triple Chile Lip” is won.

[Flag conversion during CT]
Next, with reference to FIG. 52C, a method of flag conversion lottery performed during CT will be described. As described above, in the present embodiment, when the sub-flag EX “Triple Chile Lip” is won during the CT period (internal winning combination “F_Challenging Lip” or “F_1 Chilli Lip” is won and the flag conversion lottery is won. Then, the CT is reset (stocked). Further, as shown in a CT flag conversion lottery table in FIG. 54 to be described later, if an internal winning combination “F_acceptance lip” or “F_1 accuracy dip” is won during CT, the flag conversion lottery is always won (sub flag EX “ It is always converted to “Triple Chilelip”). In other words, in the present embodiment, when the internal winning combination “F_accurate lip” or “F_1 accurate lip” is won during CT, CT is always reset.

  Further, in the flag conversion lottery when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is won, the flag is based on three types of flag conversion tables (tables 0 to 2). The winning probability of the conversion lottery is controlled. Specifically, as shown in FIG. 52C, table 0 is a flag conversion table having the lowest probability of being converted to subflag EX “reach eye lip”, and table 1 is converted to subflag EX “reach eye lip”. The flag conversion table with the next lowest probability, and Table 2 is the flag conversion table with the highest probability of being converted to the subflag EX “reach eye lip”. Note that if the sub flag EX “reach eye lip” is won during CT, CT is newly assigned as shown in the lottery table added to the set number in CT of FIG. 56 to be described later.

  In this embodiment, in normal CT, as shown in FIG. 52C, the flag conversion table is determined based on the ART level. On the other hand, in high probability CT, table 0 is always determined as the flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, with reference to FIGS. 53 to 56, various data tables used in the lottery process performed during CT will be described. Various data tables described below are stored in the main ROM 102.

[Table lottery table during CT]
FIG. 53 is a block diagram of a CT table lottery table used when determining a table to be used for flag conversion lottery out of three stages of flag conversion tables (tables 0 to 2).

  The CT table lottery table shows the correspondence between each state such as the ART level and the type of CT to be executed, the type of the flag conversion table (tables 0 to 2), and lottery value information associated with each type. Stipulate. The CT table lottery table is referred to when the CT lottery is determined to shift to CT or when CT starts.

[CT flag lottery table]
FIG. 54 is a configuration diagram of a CT flag conversion lottery table used in flag conversion lottery performed during CT.

  The CT flag conversion lottery table includes an internal winning combination (any one of “F_Correct Lip”, “F_1 Correct Chilli Lip” and “F_Reach Eye Lip A” to “F_Reach Eye Lip D”) and each flag conversion table ( The correspondence relationship between the lottery result (no conversion / with conversion) of the flag conversion lottery in the tables 0 to 2) and lottery value information associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, if the internal winning combination “F_Challenging Lip” or “F_1 Chick Lip” is won during CT, the flag conversion lottery is always won (the sub flag EX “Triple Chile Lip” must be won). Converted).

[Lottery table during CT]
FIG. 55 is a configuration diagram of the extra lottery table during CT used in the extra lottery for the number of ART games performed during CT.

  The extra lottery table during the CT is associated with each combination of the current CT state and the internal winning combination, various lottery results of the extra lottery (non-winning / additional 10 games /.../ upper 300 games), and each lottery result. It defines the correspondence with the lottery value information. The names of the internal winning combinations shown in FIG. 55 correspond to the names of the sub-flags described above. If a combination other than the internal winning combination (sub flag) shown in FIG. 55 is won internally, the winning lottery in CT will be won. Never do.

  In addition, in the extra lottery during the normal CT according to the present embodiment, the number of added games is changed according to the number of wins of the sub-flag “triple chilli lip” (internal winning combination “F_Challenging Lip” or “F_1 Challenging Lip”). To do.

  Specifically, when the number of wins of the sub-flag “triple chili lip” in the same CT set is 1 to 8, the lottery results “addition_10G” and “addition_20G” shown in FIG. 55 are given. The number of additional games is 10 games and 20 games, respectively. Therefore, in this case, 10 games are easily determined as the number of additional games of ART. Further, when the number of wins of the sub-flag “triple chili lip” in the same CT set is 9 to 16, the extra game given by the lottery results “addition_10G” and “addition_20G” shown in FIG. Both numbers are 20 games. That is, the number of added games (lottery result) corresponding to the lottery value “extremely high” of the sub-flag “triple chilli lip” in FIG. 55 is promoted to 20 games. Therefore, in this case, 20 games are easily determined as the number of additional games of ART.

  Further, when the number of wins of the sub flag “triple chili lip” in the same CT set is 17 to 24, the extra game given by the lottery results “addition_10G” and “addition_20G” shown in FIG. Both numbers are 30 games. That is, the number of added games (lottery results) corresponding to the lottery values “extremely high” and “extremely low” of the sub-flag “triple chilli lip” in FIG. 55 is promoted to 30 games. Therefore, in this case, “30 games” is easily determined as the number of additional games of ART. Further, when the number of wins of the sub flag “triple chili lip” in the same CT set is 25 times or more, the number of additional games given by the lottery results “addition_10G” and “addition_20G” shown in FIG. Both will be 50 games. That is, the number of extra games (lottery results) corresponding to the lottery values “extremely high” and “extremely low” of the subflag “triple chililip” in FIG. 55 is promoted to 50 games. Therefore, in this case, “50 games” is easily determined as the number of additional games of ART.

  As described above, in the pachi-slot 1 of the present embodiment, it is possible to increase the number of ART games that can be added by one extra lottery according to the number of wins of the sub-flag “triple chilli lip” in CT. Further, as described above, in this embodiment, as long as the number of ART games is added, CT does not end, and if the sub flag EX “triple chili lip” is won, CT is reset (stock). Is done. Therefore, in the present embodiment, as the CT continues, the player can be expected to increase the additional amount per game, and the interest during CT can be improved. In addition, since the number of wins of the sub-flag “triple chili lip”, which is an opportunity to increase the additional amount per game, is greater than the number of basic games (8 times) for CT 1 set (9 times or more), the player It is possible to prevent an excessive profit from being given to the player and to balance the profits between the player and the game store.

  In the present embodiment, the number of wins of the above-mentioned sub-flag “triple lip” (internal winning combination “F_accurate lip” or “F_1 credible lip”) is the number counted in the same CT set. The present invention is not limited to this. For example, a new CT that is given when a lottery is won by adding the number of sets performed during CT may also be included in “in the same CT set”.

[Number of sets in CT, lottery table]
FIG. 56 is a configuration diagram of an extra lottery table for the number of sets in CT used in the extra lottery of CT sets performed during CT.

  The set lottery table for the number of sets during CT includes each combination of the current CT state and the internal winning combination (sub-flag “reach eye lip (reach eye lip 1 to 4)”), and various lottery results of the extra lottery (non-win / normal) CT winning / high probability CT winning) and the lottery value information associated with each lottery result are defined.

  As is clear from the lottery table for the number of sets during CT, if you win any of the “F_reach eye lip A” to “F_reach eye lip D” during CT, you will win the extra lottery of the CT set. (CT sets are always stocked). The set of stocked CT is started after the currently set CT is finished.

<Gameability in bonus state>
Next, with reference to FIGS. 57A to 57C, the flow of the game in the bonus state will be described. FIG. 57A is a diagram showing a game flow when the gaming state shifts to the bonus state during the general gaming state (ART non-winning), and FIG. 57B shows a case where the gaming state shifts to the bonus state during the normal ART. FIG. 57C is a diagram showing a game flow when the game state shifts to a bonus state during CT.

  In the pachislot machine 1 of the present embodiment, as shown in FIGS. 57A to 57C, in terms of game play, a normal BB and a special BB are provided as bonus types, and this bonus type is determined when shifting to the bonus state. Is done. At this time, if the special BB is determined, after the bonus state is ended, the gaming state shifts to CT via the ART preparation state. On the other hand, when the normal BB is determined, the game state of the transfer destination varies depending on the state before the shift to the bonus state.

  When the game state shifts from the general game state to the normal BB, as shown in FIG. 57A, in the game in the normal BB, ART lottery is performed based on the internal winning combination. When this ART lottery is won, after the bonus state is over, the gaming state shifts to the normal ART via the ART preparation state. In this case, in the game in the bonus state after winning the ART lottery, the number of ART games is added and lottery is performed.

  When the gaming state shifts from normal ART to normal BB, CT lottery is performed at the end of normal BB, as shown in FIG. 57B. The winning probability of this CT lottery is 50%. After winning, the gaming state shifts to CT via the ART preparation state after the bonus state ends. On the other hand, if the CT lottery is not won, after the bonus state is over, the gaming state shifts to the normal ART via the ART ready state. In addition, in the game in the bonus state transferred from the normal ART, the number of ART games is added and lottery is also performed.

  When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 57C, the gaming state shifts to CT via the ART ready state after the bonus state ends. In addition, in the game in the bonus state transferred from the CT, the number of ART games is added and lottery is also performed.

<Various data tables used in games in bonus state>
Next, with reference to FIGS. 58 to 60, various data tables used in the lottery process performed in the game in the bonus state will be described. Various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 58 is a configuration diagram of a bonus type lottery table used when determining a bonus type (normal BB, special BB).

  The bonus type lottery table includes game states (CT and other) before the transition to the bonus state, various lottery results (bonus type: normal BB / special BB), and lottery values associated with the lottery results. Define the correspondence with information. Note that the bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[A lottery table with bonus ART games]
FIG. 59 is a configuration diagram of the bonus lottery table used in the bonus lottery used in the lottery and ART game lottery performed in the game in the bonus state.

  The bonus lottery table for the number of bonus ART games is associated with each combination of the current bonus type and the internal winning combination, various lottery results for the extra lottery (non-winning / 5 games /... / 300 games), and each lottery result. The correspondence relationship with the information of the lottery value obtained is defined.

  In the present embodiment, in the ART non-winning state (the state up to winning an ART lottery in the normal BB shifted from the general gaming state), the bonus ART game number adding lottery table is used for the ART lottery. Specifically, when the number of additional games is determined by lottery using the bonus lottery table in the state where the ART is not won, the number of additional games is determined when one or more games (50 games or more in the example shown in FIG. 59) are added. While winning the lottery, the corresponding number of games is given as the number of ART games. On the other hand, in the state after the ART win, the bonus ART game number addition lottery table is used only for the ART game number addition lottery.

[CT lottery table at the end of bonus]
FIG. 60 is a configuration diagram of the bonus end CT lottery table used in the CT lottery performed at the end of the bonus state.

  The CT lottery table at the end of the bonus shows each combination of the bonus type (normal BB, special BB) and the game state before transitioning to the bonus state (during normal CT, high probability CT), and various lottery results of CT lottery ( Non-winning / normal CT winning / high probability CT winning) and a lottery value information associated with each lottery result are defined. As is apparent from the bonus end CT lottery table, for example, when a normal BB is performed during a normal ART, a CT is won with a probability of 50% at the end of the bonus state.

<Exceptional gameplay in general gaming state>
Next, with reference to FIG. 61, an exceptional game flow during the general game state will be described.

  In the basic game state flow in the pachislot machine 1 of the present embodiment, the game state shifts from the normal game state to the CZ during the general game state, and the game state shifts to the ART game state by winning the ART lottery in the CZ. To do. In this embodiment, the ART gaming state is realized by performing notification in the RT4 state. Further, in the present embodiment, as shown in FIG. 61, RT state transition control is performed in accordance with the symbol combination to be stopped and displayed.

  In addition, since the symbol combination for shifting the RT state is one that is stopped and displayed in accordance with the order of the player's stop operation (pushing order) (see FIG. 24), the notification is not performed. Coincidentally, the RT state may shift to the RT4 state. Further, in the RT4 state, any of the internal winning combination "F_reach eye lip A" to "F_reach eye lip D" may be determined, so even during the general gaming state (non-ART) Reach eyes to which a special privilege is given (a symbol combination related to the abbreviation “reach eye lip”) can be displayed.

  Therefore, in the pachi-slot 1 of this embodiment, as shown in FIG. 61, the RT state accidentally shifts to the RT4 state during the general gaming state (non-ART), and the symbol combination related to the abbreviation “reach eye lip” can be displayed. When the game state is changed, the game state can be shifted to the ART game state (normal ART) without going through the CZ.

  More specifically, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined in the general gaming state and in the RT4 state, a flag conversion lottery is performed, When the flag conversion lottery is won, a notification (navigation) for displaying a symbol combination related to the abbreviation “reach eye lip” is performed, and an ART right is granted. On the other hand, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined in the general gaming state and in the RT4 state, if the flag conversion lottery is not won, A notification for displaying the symbol combination related to the abbreviation “Replay” is performed, and control is performed so that the symbol combination related to the abbreviation “Reach Eye Lip” is not displayed.

<Various data tables used in exceptional game control during the general game state>
Next, with reference to FIG. 62, a data table used in the lottery process performed in the exceptional game control during the general game state described above will be described. Note that a data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 62 is a configuration diagram of a non-ART flag conversion lottery table used in a flag conversion lottery performed in a game in the general gaming state and in the RT4 state.

  The non-ART flag conversion lottery table includes an internal winning combination (“F_reach eye lip A” to “F_reach eye lip D”), a flag conversion lottery result (no conversion / with conversion), and each lottery result. The correspondence relationship with the information of the lottery value associated with the rule is defined.

<Notification function by main side control>
In the conventional pachislot, information (navigation) of reel stop operation information (push order, etc.) is performed under the control of the sub (sub control board 72) side during ART. However, since the presence / absence of the notification affects the player's profit (so-called “out of ball”), in recent years, it is required to perform notification on the main (main control board 71) side that manages the player's profit. Yes. Therefore, in the pachi-slot 1 of the present embodiment, as described above, an instruction monitor (not shown) for notifying information of the stop operation is provided on the information display 6 controlled on the main side, and by the control on the main side, A function of notifying information on the reel stop operation is provided.

  Here, FIGS. 63A to 63D show a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the pachi-slot 1 of the present embodiment. 63A is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the ART preparation state, and FIG. 63B is during ART (normal ART or CT). It is a figure which shows the correspondence of the alerting | reporting (navigation) performed by the main side in FIG. FIG. 63C is a diagram illustrating a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flag), and FIG. 63D illustrates the RT5 state. It is a figure which shows the correspondence of alerting | reporting (navigation) performed on the main side, and alerting | reporting (navigation) performed on the sub side (between BB2 flags).

  In the present embodiment, as shown in FIGS. 63A to 63D, on the main (main control board 71) side, information on the reel stop operation is notified by displaying numerical values “1” to “11” on the instruction monitor. To do. The numerical values “1” to “11” displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

  Specifically, each of the numerical values “1” to “3” indicates the type of the reel that performs the first stop operation, and the numerical value “1” means that the first stop operation is performed on the left reel 3L. The numerical value “2” means that the first stop operation is performed on the middle reel 3C, and the numerical value “3” indicates that the first stop operation is performed on the right reel 3R.

  The numerical values “4” to “9” indicate the pressing order to be notified, and the numerical value “4” means that the pressing order is “left, middle, right”, and the numerical value “5”. Means push order is “left, right, middle”, numerical value “6” means push order is “middle, left, right”, numeric value “7” is push This means that the order is “middle, right, left”, the numerical value “8” means that the pressing order is “right, left, middle”, and the numerical value “9” means that the pressing order is It means the order of “right, middle, left”.

  The numerical values “10” and “11” respectively notify the bonus combination, and the numerical value “10” is a symbol combination (symbol “white 7” −symbol “white 7” −) associated with the combination name “C_BB1”. Symbol “white 7”), and the numerical value “11” means the symbol combination (symbol “blue 7” -design “blue 7” -design “blue 7”) associated with the combination name “C_BB2”.

  In addition, although the numerical values “1” to “11” notified on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be notified, all the players are clearly based on the numerical values. It is not always possible to grasp the contents of notification. For example, there is a possibility that the notification content cannot be grasped by some players just by displaying the numerical value “6” on the instruction monitor on the main side.

  Therefore, in the pachi-slot 1 of the present embodiment, information related to the stop operation of the stop button is also notified on the sub side together with the notification on the main side. Specifically, the display unit 11 (projector mechanism 211 and display unit 212) controlled on the sub side is used to notify information related to the stop operation by the control on the sub side.

  For example, when notifying the pressing order of performing the first stop operation on the left reel 3L, the main side displays a numerical value “1” on the instruction monitor, and on the sub side, the left reel in the display screen of the display device 11 is displayed. A numerical value “1” is displayed above 3L to notify that the left reel 3L is the target of the first stop operation. When notifying the push order “middle, left, right”, the main side displays the numerical value “6” on the instruction monitor, and the sub-side displays a numerical value above the middle reel 3C in the display screen of the display device 11. “1” is displayed, a numerical value “2” is displayed above the left reel 3L, a numerical value “3” is displayed above the right reel 3R, and the order of pressing is “middle, left, right”. Notify that. When the internal winning combination “F_BB1” is determined, the main side displays the numerical value “10” on the instruction monitor, and the sub-side displays “white 7” − “white 7” on the display screen of the display device 11. -Display information on the symbol combination of "White 7" and notify the player of the symbol to be aimed at.

  Note that the timing of notification on the main side can be set to any timing as long as it is at least a period of one game in which notification is performed. For example, the main-side notification may be performed at the timing when the player's start operation is detected (accepted), the main-side notification may be performed when the reel starts rotating, or the first stop operation to the third stop operation. The main-side notification may be performed at the timing when any one of the stop operations is detected. On the other hand, it is preferable that the notification timing on the sub side is at least a timing before the first stop operation. Therefore, in the pachi-slot 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or the timing at the start of reel rotation. Thereby, before the player performs the stop operation, information on the stop operation is notified on both the main-side instruction monitor and the sub-side display device 11.

  In the ART preparation state, as shown in FIG. 63A, notification (navigation) called “bell navigation”, “maintenance return navigation”, “RT3 transition return navigation”, and “RT4 transition return navigation” is performed by the control on the main side. In “Bell Navi”, when the internal winning combination “F_3 selection bell_1st” to “F_3 selection bell_3rd” is determined, the symbol combination related to the abbreviation “Bell” (see FIG. 29) is stopped and displayed on the active line. The order of pressing is notified. In “Maintenance Lip Navi”, when the internal winning combination “F_Maintenance Lip_1st” to “F_Maintenance Lip_3rd” is determined, the symbol combination (see FIG. 28) related to the abbreviation “Replay” is stopped and displayed on the active line. The order of pressing is notified. In the “RT3 transition Lip navigator”, when the internal winning combinations “F_RT3 transition Lip_1st” to “F_RT3 transition Lip_3rd” are determined, the symbol combination (see FIG. 28) related to the abbreviation “RT3 transition Lip” is placed on the effective line. The order of pressing for stop display is notified. Further, in the “RT4 transition Lip Navi”, when the internal winning combination “F_RT4 transition Lip_123” to “F_RT4 transition Lip_3rd” is determined, the symbol combination (refer to FIG. 28) related to the abbreviation “RT4 transition Lip” is activated. The order of pressing for stop display is informed.

  Also, in the ART gaming state (normal ART or CT), as shown in FIG. 63B, notifications called “Bell Navi”, “Maintenance Lip Navi”, “RT 3 Transition Lip Navi”, and “RT 4 Transition Lip Navi” are controlled by the main side. (Navigation) is performed. The game in the ART game state (RT4 state) is subjected to flag conversion lottery, and based on the lottery result, a symbol combination related to the abbreviation “triple chili lip”, “reach eye lip” or “replay” is displayed. However, this notification is performed only on the sub side and not on the main side.

  As mentioned above, the symbol combination related to the abbreviation “triple chili lip” or “reach eye lip” is related to the provision of a special privilege, so the presence or absence of notification affects the player's profit (out of play). Although it seems to give, in fact, in the pachislot 1 of this embodiment, since the special privilege is given based on the lottery result of the flag conversion lottery, the displayed symbol combination is given to the privilege to be given. It has no effect on it. Therefore, for example, in the state of winning the flag conversion lottery, even if the symbol combination related to the abbreviation “Replay” is stopped and displayed, a special privilege is given. On the other hand, even if the symbol combination related to the abbreviation “triple chilli lip” or “reach eye lip” can be stopped and displayed in a state where the flag conversion lottery is not won, no special privilege is given. In the pachi-slot 1 of this embodiment, when the symbol combination displayed in this way does not affect the player's profit (out), it is controlled on the sub-side without performing notification on the main-side instruction monitor. Notification is performed only on the display device 11.

  In the RT5 state (inter-flag state), as shown in FIGS. 63C and 63D, information indicating that the player is aimed at the symbol combination related to the bonus combination carried over as the internal winning combination is notified. For example, when the internal winning combination “F_BB1” is carried over, as shown in FIG. 63C, notification (navigation) referred to as “White 7 Navi” is performed under the control of the main side, and the internal winning combination “F_BB2” is performed. ”Is carried over, as shown in FIG. 63D, notification (navigation) called“ blue 7 navigation ”is performed under the control of the main side.

  In “White 7 Navi”, the symbol combination corresponding to the internal winning combination “F_BB1”, that is, the symbol combination related to the combination name “C_BB1” (“White 7”-“White 7”-“White 7”: see FIG. 28) Information on stop operation for stopping and displaying on the active line is notified. In “Blue 7 Navi”, the symbol combination corresponding to the internal winning combination “F_BB2”, that is, the symbol combination related to the combination name “C_BB2” (“Blue 7”-“Blue 7”-“Blue 7”: FIG. 28) Information on stop operation for stopping display on the active line is notified.

  In the inter-flag state, when the bonus combination and any of the internal winning combination “out of”, “F_special 1”, “F_special 2” and “F_special 3” are determined, as described in FIG. The symbol combination relating to the bonus combination (BB combination) can be stopped and displayed on the active line. However, if an internal winning combination other than the internal winning combination “Out of”, “F_Special 1”, “F_Special 2” and “F_Special 3” and a bonus combination are won, the symbol combination related to the bonus combination Cannot be stopped on the active line. Therefore, in the present embodiment, as shown in FIGS. 63C and 63D, the bonus combination that has been carried over and the internal winning combination “out”, “F_special combination 1”, “F_special combination 2”, and “F_special combination” Only when one of “3” is winning, a notification referred to as “white 7 navigation” or “blue 7 navigation” by the control on the main side is performed. Therefore, in the present embodiment, notification (navigation) called “white 7 navigation” or “blue 7 navigation” by the control on the main side can be performed at an appropriate timing at which the bonus combination can be won.

  Note that the pachi-slot 1 of the present embodiment is also provided with a function of giving a bonus notification by, for example, displaying a bonus confirmation screen or lighting a bonus confirmation lamp. Therefore, the main side may perform navigation called “white 7 navigation” or “blue 7 navigation” only after notifying (bonus notification) that the bonus combination is determined as the internal winning combination.

  As a bonus notification, for example, an effect that is performed over a plurality of game periods (a so-called continuous effect) and an effect of displaying a bonus confirmation screen according to the result of this continuous effect is generally performed. Yes. If “white 7 navigation” or the like is performed on the main side during such a continuous production, the result of the continuous production is known on the way, which may impair interest. Therefore, in the present embodiment, after the bonus notification is made, the main control board 71 performs notification (navigation) called “white 7 navigation” or “blue 7 navigation” under the control of the main side.

  It should be noted that any method for enabling the main side to grasp the timing at which the bonus notification is made is arbitrary. As one method, when the bonus combination is determined as an internal winning combination, the main control board 71 determines the number of games required until the bonus notification is completed, and after digesting the game of this number of games, A method of performing notification (navigation) called “blue 7 navigation” is conceivable. More specifically, when determining the number of games required until the bonus notification is completed, the main control board 71 notifies the sub control board 72 of the number of games. The sub-control board 72 controls the effect according to the number of games, and displays the bonus confirmation screen at the timing when the game of the number of games is consumed, thereby grasping the timing when the bonus notification is performed on the main side. Can do. That is, the main control board 71 counts the number of unit games since the bonus combination is determined as the internal winning combination in a state where the bonus combination is not carried over, and after the count result reaches a predetermined number, If any of the internal winning combination “Out of”, “F_Special combination 1”, “F_Special combination 2” and “F_Special combination 3” is determined as the internal winning combination “White 7 Navi” or “ Perform "Blue 7 Navigation".

  As another method, a method of controlling the bonus notification on the main side instead of the sub side is conceivable. More specifically, when the bonus combination is determined as an internal winning combination when the bonus combination is not carried over, the main control board 71 determines an effect (at least the number of games required for the effect) to be executed on the display device 11, The sub control board 72 is notified. The sub-control board 72 executes the notified effect and displays the bonus confirmation screen, whereby the timing at which the bonus notification is made on the main side can be grasped.

  Note that the main side may be able to grasp the timing at which the bonus notification is performed by a method other than the two methods described above. In this case, since the main control board 71 cannot accept a signal from the sub-control board 72 or the like, it is necessary to grasp the timing when the bonus notification is made based on the signal that can be accepted by the main control board 71. For example, since the signal accompanying the stop operation can be received by the main control board 71, when a predetermined stop operation (for example, other than forward pressing) is performed in a state where the bonus combination is determined as the internal winning combination In addition, a technique for giving a bonus notification is also conceivable. Specifically, the sub-control board 72 acquires information on the internal winning combination and information on the stop operation from the main control board 71, and performs bonus notification when the combination of these information is a predetermined combination. By adopting such a bonus notification method, the main control board 71 can grasp the trigger of the bonus notification, so that the timing at which the bonus notification is performed on the main side can be grasped.

<Description of main control circuit operation>
Next, contents of various processes executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS.

[Processing at power-on (reset interrupt)]
First, processing at power-on (reset interrupt) of the pachislot 1 performed under the control of the main CPU 101 will be described with reference to FIGS. 64 and 65. FIG. FIG. 64 is a flowchart showing the procedure of power-on (reset interrupt) processing, and FIGS. 65A to 65C are sources for executing the processing of S2, S7 and S8 and S13 in the flowchart, respectively. It is a figure which shows an example of a program. Note that the power-on (reset interrupt) processing shown in FIG. 64 is performed when the power management circuit 93 detects that the supply of power supply voltage to the microprocessor 91 is started. This is executed based on an interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 determines whether or not the power monitoring port (power monitoring means) is in an on state (S1).

  In S1, when the main CPU 101 determines that the power monitoring port is on (when S1 is YES), the main CPU 101 repeats the process of S1. Here, the power monitoring port being in the ON state is a state where the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

  On the other hand, when the main CPU 101 determines in S1 that the power monitoring port is not in the ON state (when S1 is NO), the main CPU 101 performs initialization processing of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 performs initial setting of the timer circuit 113. Specifically, the main CPU 101 sets a division ratio in a timer prescaler register (not shown), sets an interrupt enable setting in the timer control register (not shown), and sets a timer counter (not shown). Set the initial count value.

  Next, the main CPU 101 initializes the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. An initialization process is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test on the main RAM 103 (S5).

  Next, the main CPU 101 determines whether or not writing to the main RAM 103 has been normally performed as a result of the writing test (S6).

  In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S6 that the writing to the main RAM 103 has been performed normally (when S6 is YES), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. Is acquired (S7).

  Next, the main CPU 101 determines whether or not the current state is the generation timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether 1.1172 ms has elapsed since the start of the timer count based on the acquired state of the timer control register.

  In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. Thereafter, the status of the timer circuit 113 can be acquired by reading information in a timer control register (not shown). In this embodiment, a bit (determination bit) that can determine (refer to) whether or not the current state is the generation timing of an interrupt process (whether or not it is a timer interrupt state) in the timer control register. ) Is provided.

  Therefore, in the process of S7, the main CPU 101 reads information in the timer control register (not shown), and in the process of S8, the main CPU 101 turns on / off the discrimination bit in the timer control register ( By referring to “1” / “0”), it is determined whether or not the current state is the generation timing of the interrupt process. When 1.1172 ms elapses from the count start by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the determination bit is turned on.

  In S8, when the main CPU 101 determines that the current state is not the generation timing of the interrupt process (when S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

  On the other hand, when the main CPU 101 determines in S8 that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 performs a sum check process (not specified) (S9). . In this process, the main CPU 101 performs a sum check process of the main RAM 103, and the work of this process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. The program used in the sum check process is stored in an unspecified area in the main ROM 102 (see FIG. 12B). The details of the sum check process will be described later with reference to FIGS. 79 and 80 described later.

  In S8, when the main CPU 101 determines that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 determines the below-described interrupt before the process of S9. (See FIG. 158 described later). As a result of this interrupt processing, a no-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

  After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in an on state (S10).

  In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, when the main CPU 101 determines in S10 that the setting key switch 54 is not in the ON state (when S10 is NO), the main CPU 101 determines the sum check based on the result of the sum check process in S9. It is determined whether or not the result is normal (S11).

  In S11, when the main CPU 101 determines that the sum check determination result is not normal (when S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S11 that the sum check determination result is normal (when S11 is YES), the main CPU 101 performs a game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power interruption detection. Details of the game return process will be described later with reference to FIG. 66 described later.

  When S6 or S11 is NO, the main CPU 101 displays a character string “rr” indicating an error occurrence on the information display 6 (7-segment LED display) (S13). Thereafter, the main CPU 101 repeats the WDT clear process (S14).

  Here, returning to the process of S10 again, if S10 is YES, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation and storage process at the start of setting change. Details of the setting change confirmation process will be described later with reference to FIG. 68 described later.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared). Then, after the process of S16, the main CPU 101 starts a main process described later (see FIG. 82 described later).

  In the present embodiment, processing at power-on (reset interrupt) is performed as described above. The process of S2 during the power-on (reset interrupt) process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65A.

  In the source program of FIG. 65A, 10 MHz is set as the CPU clock (supply clock is 20 MHz), 228 is set as the prescaler register setting value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt process.

  Further, the processing of S7 and S8 during the above-described power-on (reset interrupt) processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65B. Specifically, the process of acquiring the state of the timer control register in S7 is executed by the “LD” instruction in FIG. 65B, and the determination process in S8 is executed by the “JBIT” instruction in FIG. 65B. Then, the “LD” instruction in FIG. 65B and the “JBIT” instruction in FIG. 65B are repeatedly performed until 1.1172 ms has elapsed since the timer circuit 113 started counting, and when 1.1172 ms has elapsed since the timer circuit 113 started counting. Then, an interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101 starts the interrupt process of the first 1.1172 ms cycle after the power is restored, triggered by the input of this interrupt request signal.

  Note that in the first 1.1172 ms interrupt process immediately after the power is restored (after initialization at the time of power-on), no command related to the game operation is set, so that the main control circuit 90 transfers to the sub control circuit 200. A no-operation command is sent. In this way, by permitting the interrupt processing immediately after the power is restored, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  In addition, the communication parameters 1 to 5 constituting the no-operation command transmitted in this communication operation are set with data stored in the L register, H register, E register, D register, and C register, respectively, when the power is restored. Is done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the no-operation command transmitted in the first interrupt process after the power return is made different (undefined) at each power return. Can do. That is, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power return (after initialization at the time of power-on) can be made different for each power return. In this case, fraudulent acts such as goto can be suppressed.

  Further, the processing of S13 (interrupt prohibition processing) during the above-described power-on (reset interrupt) processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65C. . Then, the control for displaying the error code “rr” on the 2-digit 7-segment LED in the information display 6 is executed by one source code “LDW HL, 100H * cZCHRAR + cBX_PAYSEG” as shown in FIG. 65C. Then, the output operation of the 7-segment common output data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are simultaneously performed.

  That is, in the pachi-slot 1 of the present embodiment, when the two-digit 7-segment LED is controlled to be dynamically lit, 7-segment common output data and 7-segment cathode output data are simultaneously output. In this case, it is possible to reduce the number of instruction codes necessary for dynamic lighting control of the 7-segment LED on the source program, and to reduce the capacity of the source program (usage capacity of the main ROM 102). Therefore, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Here, “7-segment common output data” is LED drive data output to the common (common) terminal of the 7-segment LED when the 7-segment LED is dynamically controlled, and “7-segment cathode output data” is , LED drive data output to each cathode terminal of the 7-segment LED when the 7-segment LED is dynamically controlled.

[Game return processing]
Next, with reference to FIGS. 66 and 67, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 64) will be described. FIG. 66 is a flowchart showing the procedure of the game return process, and FIG. 67 is a diagram showing an example of a source program for executing the processes of S25 to S32 in the flowchart.

  First, the main CPU 101 sets the stack pointer at the time of power interruption to the stack pointer (SP) (S21). Next, the main CPU 101 clears (turns off) the on-edge data before the interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port to the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the data storage area of the current input port and before the one interrupt process (S24).

  Next, the main CPU 101 sets the address of the spinning cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

  Next, the main CPU 101 acquires reel control management information (data relating to display row fluctuation control when power interruption occurs) based on the address of the set spinning cylinder control data storage area (S27). Note that the reel control management information (display row variation control management information) is information related to the control state (rotation state) of each reel, and is backed up and stored when power is interrupted.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation state during the reel acceleration, the constant speed waiting, or the constant speed (S28).

  In S28, when the main CPU 101 determines that the condition of S28 is not satisfied (when S28 is NO), the main CPU 101 performs a process of S31 described later. On the other hand, when the main CPU 101 determines in S28 that the condition of S28 is satisfied (when S28 is YES), the main CPU 101 clears the spinning control data (reel control management information) (S29). With this process, after the game returns, the reel rotation control is started from the acceleration process. Next, the main CPU 101 sets a reel operation timing value (rotation control data execution start timing “1”) (S30). When “1” is set as the reel operation timing, the main CPU 101 accelerates the reel rotation control because the excitation change timing is reached in the reel control processing (see S903 in FIG. 158 described later). Start with

  After the process of S30 or when S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is “0” (S32).

  In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not “0” (when S32 is NO), the main CPU 101 changes the reel to be checked and changes the process to the process of S27. Return and repeat the processing from S27.

  On the other hand, when the main CPU 101 determines in S32 that the value of the number of reels after subtraction is “0” (when S32 is YES), the main CPU 101 performs a RAM initialization process (S33). In this process, the main CPU 101 sets the address at the time of “power recovery” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the start of initialization, and starts from the start address to the end of the game RAM area. Erase (clear) information up to the address.

  Next, the main CPU 101 restores all the register data saved at the time of detecting power interruption to all the registers (S34). After the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of detecting the power interruption.

  In the present embodiment, the game return process is performed as described above. In the game return process of the present embodiment, as described above, the input / output state of each port at the time of power interruption is ensured at the time of power recovery, and if the reel is rotating at the time of power interruption, the reel control management at the time of power recovery The processing necessary for acquiring the information and starting the reel re-rotation is also performed (refer to the processing of S25 to S32). Therefore, in the present embodiment, even when the power is restored from the power interruption during the rotation of the spinning cylinder, the reel re-rotation control can be stably performed, and the player does not feel uncomfortable.

  Further, the processes of S25 to S32 during the game return process described above are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As described above, in the microprocessor 91 with a security function for gaming machines used in the pachislot machine 1 of this embodiment, various instruction codes dedicated to the main CPU 101 are provided. For example, an “LDQ” instruction (predetermined read instruction) in FIG. 67 is one of instruction codes dedicated to the main CPU 101.

  For example, when the source code “LDQ HL, k” is executed on the source program, the address specified by the contents (stored data) of the Q register and the 1-byte integer k (direct value) is stored in the HL register. To be loaded. At this time, the contents of the Q register become the address value on the higher side of the designated address, and the integer k (direct value) becomes the address value on the lower side of the designated address. Therefore, when the source code “LDQ HL, .LOW.wR1_CTRL” in FIG. 67 is executed, the contents of the Q register (the address value on the upper side of the address of the drum control data storage area) and the integer value “. The address (address of the spinning cylinder control data storage area) specified by “LOW.wR1_CTRL” (address value on the lower side of the address of the spinning cylinder control data storage area) is loaded into the HL register. “.LOW.” Is not an actual instruction but a pseudo instruction. In this pseudo-instruction function, only the lower address of the storage area address defined following “.LOW.” Is validated. The pseudo instruction is not an instruction stored in the actual ROM, but an instruction for a conversion program (assembler) to refer to when converting the source file into a format for storing in the ROM.

  As described above, in the present embodiment, by using the instruction code dedicated to the main CPU 101 that performs addressing using the Q register (extension register), the main ROM 102, the main RAM 103, and the memory map I / O can be directly converted. Can be accessed. In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Setting change confirmation process]
Next, with reference to FIGS. 68 and 69, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 64) will be described. 68 is a flowchart showing the procedure of setting change confirmation processing, FIG. 69A is a diagram showing an example of a source program for executing the processing of S44 to S47 in the flowchart, and FIG. It is a figure which shows an example of the source program for performing the process of S57 in this flowchart.

  First, the main CPU 101 performs an initialization process for an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt waiting process (S42). In this process, the main CPU 101 stands by until the transmission process of the no-operation command to the sub control circuit 200 by the interrupt process is completed.

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared).

  Next, the main CPU 101 determines whether or not the setting key type switch 54 is on (S44). A setting key (not shown) inserted into the setting key switch 54 is an operation key for operating the settings (settings 1 to 6) of the pachislot 1. When the setting key is turned on, the setting key (not shown) is set. The key type switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (in the case where S44 is NO), the main CPU 101 ends the setting change confirmation processing and turns on the power (reset interrupt). ) The process proceeds to S16 in the time process (see FIG. 64). On the other hand, when the main CPU 101 determines in S44 that the setting key type switch 54 is in the ON state (when S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medal is discharged from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets setting change start or setting check start information (005H: first value) in the L register, and generates and stores a setting change command (setting change / setting check start) (S46). . In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. A setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. Sent to.

  Next, the main CPU 101 sets the error count relay to an on state (S47). Next, the main CPU 101 determines which setting change or setting confirmation has been performed (S48).

  In S48, when the main CPU 101 determines that the setting has not been changed (setting has been confirmed) (when S48 is NO), the main CPU 101 performs the process of S55 described later.

  On the other hand, when the main CPU 101 determines in S48 that the setting has been changed (the setting has not been confirmed) (when S48 is YES), the main CPU 101 performs a setting value update process (S49). ). Next, the main CPU 101 performs setting value 7-segment display setting processing (S50). By this processing, the updated set value can be displayed by the 7-segment LED in the information display 6.

  Next, the main CPU 101 determines whether or not the reset switch 76 is on (S51).

  When the main CPU 101 determines in S51 that the reset switch 76 is in the on state (when S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, when the main CPU 101 determines in S51 that the reset switch 76 is not in the on state (when S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the on state (S52). .

  In S52, when the main CPU 101 determines that the start switch 79 is not on (when S52 is NO), the main CPU 101 returns the process to the process of S51 and repeats the processes after S51. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is on (when S52 is YES), the main CPU 101 sets a setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  Next, the main CPU 101 determines whether or not the setting key switch 54 is in an OFF state (S54).

  In S54, when the main CPU 101 determines that the setting key switch 54 is not in the OFF state (when S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (when S54 is YES), the main CPU 101 performs the process of S55 described later.

  When S48 is NO or S54 is YES, the main CPU 101 determines whether setting change or setting confirmation has been performed (S55).

  When the main CPU 101 determines in S55 that the setting has not been changed (setting confirmation has been performed) (when S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, when the main CPU 101 determines in S55 that the setting has been changed (the setting has not been confirmed) (when S55 is YES), the main CPU 101 performs a RAM initialization process (S56). . In this process, the main CPU 101 uses, as a start address for starting initialization, an address at the “setting change end” (not shown) in the game RAM area of the main RAM 103 shown in FIG. The information from the head address to the last address of the game RAM area is erased (cleared).

  After the process of S56 or when S55 is NO, the main CPU 101 sets setting change end information or setting check end information (004H: second value) in the L register, and a setting change command (setting change / setting check end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. Also, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Sent to. After the process of S57, the main CPU 101 ends the setting change confirmation process, and moves the process to the process of S16 of the power-on (reset interrupt) process (see FIG. 64).

  In the present embodiment, the setting change confirmation process is performed as described above. The processes of S44 to S47 during the setting change confirmation process described above are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 69A. Among them, for example, the setting key state determination process in S44 is executed by the source code “BITQ 7, (.LOW. (WIBUF + 4))” in FIG. 69A, and sets the error count relay in S47 to the ON state. The processing is executed by the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 69A.

  Both the “BITQ” instruction and the “SETQ” instruction are instruction codes dedicated to the main CPU 101 for performing addressing using the Q register (extension register).

  For example, when the source code “BITQ b, (k)” is executed on the source program, data stored in the Q register (upper address value) and 1-byte integer value k (direct value: lower address value) ) Is checked, and if the bit b stores “1”, the zero flag (bit 6: see FIG. 11) of the flag register F is set to “0”. If “0” is stored in the bit b, “1” is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code “BITQ 7, (.LOW. (WIBUF + 4)” in FIG. 69A is executed, the address specified by the data stored in the Q register and the integer value “.LOW. (WIBUF + 4)” If bit 7 of this memory is checked and "1" is stored in bit 7, "0" is set in the zero flag of flag register F, and if "0" is stored in bit 7 , “1” is set in the zero flag of the flag register F.

  For example, when the source code “SETQ b, (k)” is executed on the source program, data stored in the Q register (upper address value) and 1-byte integer value k (direct value: lower side) "1" is set in the bit b of the memory at the address specified by (address value). Therefore, when the source code “SETQ 1, (.LOW.wECRRREQ)” in FIG. 69A is executed, the data stored in the Q register and the memory at the address specified by the integer value “.LOW.wECRRREQ” are stored. Bit 1 is set to “1”.

  That is, in the setting change confirmation process of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extended register) as described above are used, and by using these main CPU 101 dedicated instruction codes, a direct value is obtained. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to increase the processing speed.

  In addition, the setting change command (initialization command) generation / storage process performed at the start of the setting change / setting check in S46 during the setting change checking process described above is performed by the main CPU 101 executing the “CALLF” instruction in FIG. 69A. The generation / storage processing of the setting change command (initialization command) performed at the end of the setting change / setting confirmation in S57 described above is performed by the main CPU 101 executing the “CALLF” instruction in FIG. 69B. The “CALLF” instruction is also a dedicated instruction code for the main CPU 101.

  For example, when the source code “CALLF mn” is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is designated by the stack pointer (SP). The data is saved in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the “CALLF” instruction is a 2-byte instruction, and an address range that can be jumped is a range of 0000H to 11FFH. Therefore, for example, when the source code “CALLF SB_PCINIT_00” in FIG. 69A is executed, the current PC register value is saved in the memory specified by the stack pointer (SP), and the stack pointer is updated by −2. The address of “SB_PCINIT_00” is stored in the PC register, and the process jumps to the address specified by “SB_PCINIT_00”.

  In the present embodiment, an instruction code called a “CALL” instruction is also prepared as an instruction code of the same type as the “CALLF” instruction. For example, when the source code “CALL mn” is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is stored as in the “CALLF” instruction. The data is stored in the memory designated by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address designated by "mn". However, the “CALL” instruction is a 3-byte instruction, and the address range that can be jumped is different from that of the “CALLF” instruction, and the address range that can be jumped is the range of 0000H to FFFFH. Since the “CALLF” instruction is an instruction code having a smaller number of bytes than the “CALL” instruction, the capacity of the source program (usable capacity of the main ROM 102) can be reduced and the processing efficiency can be improved. be able to.

  Further, in the setting change confirmation processing of this embodiment, as shown in FIGS. 69A and 69B, the jump destination address “SB_PCINIT_00” designated by the “CALLF” instruction in S46 is the jump destination designated by the “CALLF” instruction in S57. Is the same address as That is, in the present embodiment, a setting change command (initialization command) generation and storage process to be transmitted to the sub-control circuit 200 at the time of setting change (when a gaming machine is started), at the time of setting check start (during normal operation), and at the end of setting check. Are the same as each other, and the source program of the setting change command generation / storage process used in both the processes of S46 and S57 is shared (modularized).

  In this case, since it is not necessary to provide a source program for the setting change command generation / storage process separately in both the processes of S46 and S57, the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. . As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 68) will be described with reference to FIGS. 70 is a flowchart showing the procedure of the setting change command generation / storage process, and FIG. 71 is a diagram showing an example of a source program for executing the setting change command generation / storage process.

  First, the main CPU 101 sets information of setting values (1 to 6) in the E register (S61). Next, the main CPU 101 sets RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 performs communication data storage processing (S64). In this processing, the main CPU 101 determines the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 68) (setting change start / setting change end / setting status). The setting change command data is generated using the setting confirmation start / setting confirmation end), and the generated command data is stored in the communication data storage area. Details of the communication data storage process will be described later with reference to FIG. 72 described later.

  After the process of S64, the main CPU 101 ends the setting change command generation / storage process. When ending the setting change command generation / storage process performed in S46 during the setting change confirmation process (see FIG. 68), the main CPU 101 executes the process of the setting change confirmation process (see FIG. 68) after the process in S64. The process proceeds to S47. Further, when ending the setting change command generation / storage process performed in S57 during the setting change confirmation process (see FIG. 68), the main CPU 101 ends the setting change command generation / storage process after the process of S64 and sets the setting. The change confirmation process (see FIG. 68) is also terminated.

  In the present embodiment, the setting change command generation / storage process is performed as described above. The setting change command generation / storage process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  As described above, in the setting change command generation / storage process, the setting status is stored in the D register as the communication parameter 4 immediately before the setting change command generation / storage process is executed, and the setting value is set during the execution of the setting change command generation / storage process. Is stored in the E register as communication parameter 3, and RT information is stored in the C register as communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. Therefore, the values stored in the L register and the H register at the present time are set, respectively. Therefore, the values of the communication parameters 1 and 2 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Communication data storage processing]
Next, with reference to FIGS. 72 and 73, for example, the communication data storage process performed in S64 in the setting change command generation / storage process (see FIG. 70) will be described. Note that the communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 72 is a flowchart showing a procedure of the communication data storage process, and FIG. 73 is a diagram showing an example of a source program for executing the processes of S71 to S76 during the communication data storage process.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as communication command parameters 1 and 2, respectively (S72). .

  Next, the main CPU 101 stores the data set in the D register and E register as communication command parameters 3 and 4 in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register in the communication data temporary storage area in the main RAM 103 as the communication command parameter 5 and the RT state data, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in a communication data temporary storage area in the main RAM 103 (S76).

  After the process of S76, the main CPU 101 determines whether or not there is an empty communication data storage area in the main RAM 103 (S77). In the present embodiment, a maximum of nine command data can be stored in the communication data storage area (see FIG. 75B described later).

  In S77, when the main CPU 101 determines that there is no free space in the communication data storage area (when S77 is NO), the main CPU 101 ends the communication data storage process and, for example, a setting change command generation storage process ( The process also ends (see FIG. 70).

  On the other hand, when the main CPU 101 determines in S77 that the communication data storage area is free (when S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the processes of S71 to S76 described above. The communication data is stored in the communication data storage area as communication command data (S78).

  Next, the main CPU 101 performs communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating a communication data pointer indicating a storage address of communication data in the communication data storage area. Details of the communication data pointer update process will be described later with reference to FIG. 74 described later.

  Then, after the process of S79, the main CPU 101 ends the communication data storage process and also ends the setting change command generation / storage process (see FIG. 70), for example.

  In the present embodiment, the communication data storage process is performed as described above. Note that the processing of S71 to S76 during the above-described communication data storage processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In this series of processes, the storage process of the communication command type data, various communication parameters, gaming state flag data, and BCC data included in the command data is performed in the Q register on the source program as shown in FIG. It is executed using an “LDQ” instruction, which is a dedicated instruction code for the main CPU 101 that performs addressing using (extension register).

  Specifically, when the source code “LDQ (.LOW. (WPDT_TMP + 0)), A” is executed, the type data of the communication command stored in the A register becomes the stored data (upper address value) of the Q register and 1 It is stored in the communication data temporary storage area at the address specified by the integer value “.LOW. (WPDT_TMP + 0)” (lower address value). Further, when the source code “LDQ (.LOW. (WPDT_TMP + 1)), HL” is executed, the communication parameter 1 stored in the L register is changed to the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 1)”. The communication parameter 2 stored in the communication data temporary storage area at the address designated by "" and stored in the H register is stored in the communication data temporary storage area at the next address. In addition, when the source code “LDQ (.LOW. (WPDT_TMP + 3)), DE” is executed, the communication parameter 3 stored in the E register is stored in the Q register and the integer value “.LOW. (WPDT_TMP + 3) in 1 byte. The communication parameter 4 stored in the communication data temporary storage area of the address designated by "" and stored in the D register is stored in the communication data temporary storage area of the next address. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 5)), BC”, the communication parameter 5 stored in the C register is stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 5)”. The gaming state flag data stored in the communication data temporary storage area of the address designated by “B” and stored in the B register is stored in the communication data temporary storage area of the next address.

  Further, the BCC data serving as the sum value of the command data set in the communication data storing process is calculated by executing a series of source codes “ADD (addition instruction code) A, H” to “ADD A, B”. Stored in a register. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 7)), A”, the BCC data stored in the A register becomes the stored data in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 7)”. And stored in the communication data temporary storage area at the address specified by.

  As described above, in this embodiment, when one packet (8 bytes) of communication data (command data) is created, various parameters are transferred from the register and stored in a communication data temporary storage area (communication buffer). In such a command data creation method, data stored in each register at the time of command generation is directly stored in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. In this case, even if there is command data of the same type and the value of the use parameter is the same, the command data sum value (BCC data) can be changed every time the command is created. In this embodiment, the sum value, which is one of the error codes, is calculated by ADD (addition instruction code). However, instead of the addition instruction code, SUB (subtraction instruction code), XOR (exclusive OR) The same effect can be obtained by calculating the error code using the instruction code. Further, the same effect can be obtained by calculating an error code using MUL (multiplication instruction code) or DIV (division instruction code), which is a dedicated instruction for the main CPU 101.

  Therefore, in this embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress illegal acts such as goto, and it is necessary to add unnecessary goth countermeasure processing. Therefore, it is possible to suppress the compression of the program capacity of the main control circuit 90 due to the addition of the anti-going process.

[Communication data pointer update processing]
Next, with reference to FIGS. 74 and 75, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 72) will be described. 74 is a flowchart showing a procedure of the communication data pointer update process, FIG. 75A is a diagram showing an example of a source program for executing the communication data pointer update process, and FIG. 75B is a communication data pointer. It is a figure which shows the structure of the communication data storage area | region actually set on the source program of an update process.

  First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer for one packet (8 bytes) (S82). In this process, when the updated communication data pointer value is equal to or larger than the upper limit size of the communication data storage area (see FIG. 75B), the main CPU 101 sets the updated communication data pointer value to “0”. Thus, all the command data stored in the communication data storage area are invalidated (the state is the same as the discarded state).

  In the present embodiment, the amount of data (one packet) transmitted in one transmission operation is 8 bytes. That is, in this embodiment, one command data can be transmitted by one transmission operation. In the present embodiment, since a maximum of nine command data can be stored in the communication data storage area (see FIG. 75B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). . Therefore, in this embodiment, the range of the communication data pointer is set to “0” to “71”, and the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is “71 ( If the value exceeds the upper limit value), set the updated communication data pointer value to “0” (return the communication data storage destination address to the top address) and store the communication data. Invalidate all command data stored in the area (similar to the discarded state). If the value of the communication data pointer is set to “0”, the next time command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area. The command data is overwritten with new command data. Therefore, in this embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds “71 (upper limit value)”.

  After the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 72).

  In the present embodiment, the communication data pointer update process is performed as described above. The communication data pointer update process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 75A. Among them, the communication data pointer update processing in S82 is executed by the “ADD” instruction and the “ICPLD” instruction (predetermined update instruction) in FIG. 75A. This “ICPLD” instruction is also dedicated to the main CPU 101. Instruction code.

  In the source program, for example, when the source code “ICPLD A, n” is executed, the content (stored data) of the A register is compared with the integer n, and the content of the A register is less than the integer n. When “1” is added to the contents of the A register and the contents of the A register are equal to or greater than the integer n, “0” is set in the A register.

  Therefore, when the communication data pointer update process of S82 is executed, the source code “ADD A, 7” is first executed on the source program of FIG. 75A, and the contents of the A register (the communication data pointer before the update are updated). “7” is added to the value), and the addition result is stored in the A register. Next, the source code “ICPLD A, 71” is executed, and the content of the A register (the value of the communication data pointer after addition of 7) is compared with the integer “71”, and the content of the A register is less than the integer “71”. In some cases, “1” is added to the content of the A register, and when the content of the A register is equal to or greater than the integer “71”, “0” is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7 and the updated communication data pointer value exceeds the upper limit “71”, the process of clearing the communication data pointer to zero (communication Processing for returning the data storage address to the start address of the communication data storage area is performed. On the other hand, if the updated communication data pointer value does not exceed the upper limit value “71”, “1” is further added to the communication data pointer by the “ICPLD” instruction, so that the communication data pointer value is totaled. Update +8.

  As described above, in this embodiment, in the communication data pointer update process, communication data is updated by one “ICPLD” instruction code (an instruction code in which a transmission buffer upper limit determination instruction and a determination branch instruction are integrated). The pointer update (addition of 1) process, the updated communication data pointer determination check process, and the communication data pointer clear process can be executed together. In this case, there is no need to provide an instruction code for executing each process separately. For example, it is possible to omit the branch instruction code for determining whether or not the value of the updated communication data pointer exceeds the upper limit “71”.

  Therefore, by using the “ICPLD” instruction code dedicated to the main CPU 101 in the communication data pointer update processing or the like, the capacity of the source program (the capacity used by the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Power failure (external) processing]
Next, the process at the time of power interruption (external) of the pachislot 1 performed under the control of the main CPU 101 will be described with reference to FIG. FIG. 76 is a flowchart showing a procedure of processing at the time of power interruption (external). Note that the power interruption (external) processing shown in FIG. 76 is performed when the power management circuit 93 detects a decrease (power interruption) in the power supply voltage supplied to the microprocessor 91. And is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 saves data set in all registers (S91). Next, the main CPU 101 reads data set in the power interruption detection port (S92).

  Next, the main CPU 101 determines whether or not the power failure detection port is on (S93).

  In S93, when the main CPU 101 determines that the power interruption detection port is not in the on state (when S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 terminates the power interruption (external) processing. It should be noted that these processes performed when S93 is NO corresponds to the instantaneous power failure countermeasure process that occurs when the power management circuit 93 instantaneously detects a power interruption.

  On the other hand, when the main CPU 101 determines in S93 that the power failure detection port is in the ON state (when S93 is YES), the main CPU 101 sets the medal insertion impossible and sets the stop of the hopper device 51. (S95).

  Next, the main CPU 101 stores the value of the currently set stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 performs checksum generation processing of the main RAM 103 (S97). This process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. Further, the program used in the checksum generation process is stored in an unspecified area in the main ROM 102 (see FIG. 12B). Details of the checksum generation process will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 sets prohibition of access to the main RAM 103 (S98). Then, after the process of S98, an infinite loop process is performed until the power supply stops (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation processing (not specified)]
Next, with reference to FIGS. 77 and 78, the checksum generation processing performed in S97 during power interruption (external) processing (see FIG. 76) will be described. 77 is a flowchart showing the procedure of the checksum generation process, FIG. 78A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 78B is the checksum generation process. It is a figure which shows the mode of the update operation | movement of the stack pointer performed, and the read-out operation | movement of the data to the register from main RAM103.

  First, the main CPU 101 stores the current stack pointer (SP) value (the in-use address of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets an upper address value (F0H) of the RAM address (non-standard stack area address) in the Q register (S103). Next, the main CPU 101 sets a power interruption occurrence flag (S104).

  Next, the main CPU 101 sets the calculation start address of the sum value in the game RAM area to the stack pointer, and sets the sum calculation counter to the value obtained by dividing the number of bytes in the storage area for the sum value calculation by “2”. Set (S105). The sum calculation counter is a counter for determining the end timing of the sum value calculation, and is provided in the main RAM 103. When the sum calculation counter set in S105 becomes “0”, the game RAM area sum value calculation process of the main RAM 103 ends.

  Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value “0” of the sum value is set.

  Next, the main CPU 101 executes an instruction code called “POP instruction” (specific instruction) (source code “POP DE” described in FIG. 78A) and stores it in the main RAM 103 set in the stack pointer (SP). Data (stored value) of the area of 2 bytes is read from the area address to the DE register (S107).

  When the “POP” instruction is executed, the data (memory contents) stored in the 1-byte area at the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address obtained by updating the updated address by 1 is loaded into the upper register of the pair register. When the “POP” instruction is executed, an address update process for 2 bytes (a process of adding “2” to the address) is performed on the address set in the stack pointer (SP).

  Therefore, in the process of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and stored at the address obtained by adding “1” to the address specified by the stack pointer. Data (memory contents) is loaded into the D register.

  FIG. 78B shows the state of the data reading operation to the DE register and the updating operation of the address set in the stack pointer when the “POP” instruction is executed. If the address set in the stack pointer (SP) is “F010h” at the start of the calculation of the sum value, the data (memory contents) stored in the address “F010h” is loaded into the E register, and the address Data (memory contents) stored in “F011h” is loaded into the D register. At this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from “F010h” to “F012h”. Next, when the “POP” instruction is executed again, the data (memory content) stored at the address “F012h” is loaded into the E register, and the data (memory content) stored at the address “F013h” is loaded. Loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from “F012h” to “F014h”. Thereafter, every time the “POP” instruction is executed, the above-described operation for reading data into the DE register and the operation for updating the address set in the stack pointer are repeated.

  After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (in the case where S110 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standardized thumb count value is the number of bytes in the non-standardized storage area. Therefore, when the sum calculation counter set in S111 becomes “0”, the sum value calculation process for the non-standard RAM area of the main RAM 103, that is, the sum value calculation process for the entire main RAM 103 is completed.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S112).

  Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register, and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S115).

  In S115, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S115 is NO), the main CPU 101 returns the process to the process of S112 and repeats the processes after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the unspecified RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

  On the other hand, when the main CPU 101 determines in S115 that the value of the sum calculation counter is “0” (in the case where S115 is YES), the main CPU 101 uses the value stored in the HL register when the power interruption occurs. Is stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S101 to the stack pointer (S117). After the process of S117, the main CPU 101 ends the checksum generation process, and moves the process to the process of S98 of the power interruption (external) process (see FIG. 76).

  In the present embodiment, the checksum generation process is performed as described above. The checksum generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 78A. As described above, in the present embodiment, the checksum of the main RAM 103 when a power interruption occurs is calculated by an addition formula. At this time, in the calculation of the sum value of the game RAM area, an addition process is performed in units of 2 bytes (refer to the source code “ADD HL, DE” in FIG. 78A), and in the unspecified RAM area, the addition process is performed in units of 1 byte. (See source code “ADDWB HL, A” in FIG. 78A).

[Sum check processing (not specified)]
Next, the sum check process performed in S9 during the power-on process (see FIG. 64) will be described with reference to FIGS. 79 and 80 are flowcharts showing the procedure of the sum check process, and FIG. 81 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the sum check process.

  First, the main CPU 101 stores the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets a value obtained by dividing the number of bytes in the sum value calculation target storage area by “2” in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end timing of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 obtains a sum value (check sum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power interruption occurs is stored in the HL register.

  Next, the main CPU 101 executes a “POP” instruction, and reads data (stored value) of 2 bytes from the storage area address of the main RAM 103 set in the stack pointer (SP) to the DE register (S124). . At this time, by executing the “POP” instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is set. Data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register (see FIG. 78B). When the “POP” instruction is executed, an address update process for two bytes (a process for adding two addresses) is performed on the address set in the stack pointer (SP).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial value of the sum value or the sum value after the previous subtraction process). The value is stored in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S127 is NO), the main CPU 101 returns the process to the process of S124 and repeats the processes after S124. That is, the processes of S124 to S127 are repeated until the sum value subtraction process is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is “0” (in the case where S127 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard thumb count value is the number of bytes in the non-standard RAM area.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S129).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S132).

  In S132, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S132 is NO), the main CPU 101 returns the process to the process of S129 and repeats the processes after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire non-standard RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is “0” (when S132 is YES), the main CPU 101 sets “sum abnormality” in the determination result of the sum check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

  In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value is “0” when the value of the sum calculation counter set in S128 becomes “0”, that is, when the sum value subtraction process is completed over the entire area of the main RAM 103. Is set to “1” in the zero flag of the flag register F, and “0” is set in the zero flag of the flag register F when the sum value is not “0”. Therefore, if “1 (ON state)” is set in the zero flag of the flag register F at the time of the processing of S134, the main CPU 101 determines that the sum value is “0”.

  In S134, when the main CPU 101 determines that the calculated sum value is not “0” (when S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, when the main CPU 101 determines in S134 that the calculated sum value is “0” (when S134 is YES), the main CPU 101 sets “power failure abnormality” as the determination result (S135). ).

  Next, the main CPU 101 acquires a power interruption occurrence flag (S136). Next, the main CPU 101 determines whether or not the power interruption occurrence flag is in a state without power interruption (off state) (S137).

  In S137, when the main CPU 101 determines that the power interruption occurrence flag is in a state where there is no power interruption (when S137 is YES), the main CPU 101 performs a process of S139 described later. On the other hand, when the main CPU 101 determines in S137 that the power interruption occurrence flag is not in the state without power interruption (when S137 is NO), the main CPU 101 sets “normal” as the determination result (S138).

  After S138, if S134 is NO or S137 is YES, the main CPU 101 stores the determination result in the sum check determination result and clears (turns off) the power interruption occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S121 to the stack pointer (S140). After the process of S140, the main CPU 101 ends the sum check process and moves the process to the process of S10 of the power-on process (see FIG. 64).

  In the present embodiment, the sum check process is performed as described above. Then, the processing of S122 to S132 during the above-described sum check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  As described above, in the thumbchock determination process of the main RAM 103 in the present embodiment, first, the checksum value generated when the power interruption occurs is sequentially subtracted by the data stored in the main RAM 103 when the power is restored. At this time, subtraction processing (see source code “SUB HL, DE” in FIG. 81) is performed in the gaming RAM area (see source code “SUB HL, DE” in FIG. 81). Source code “SUBWB HL, A”). Next, whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is “0” (whether or not the zero flag is on). When the subtraction result is “0” (when the zero flag is in the on state), it is determined as normal, and when the subtraction result is not “0” (when the zero flag is in the off state), it is determined as abnormal. Determined.

  In other words, in the present embodiment, the checksum generation process when power interruption occurs is performed by the addition method, and the checksum determination process when power is restored is performed by the subtraction method. Then, normal / abnormal determination is performed based on the final checksum subtraction result. When such checksum generation processing and determination processing are performed, it is not necessary to generate the checksum again when the power is restored and to check the checksum against the checksum when the power interruption occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, a free space corresponding to the omission of the collation instruction code can be secured, and the increased free space can be used to improve the game performance. Note that the “POP” instruction executed in the checksum generation process when the power interruption occurs and the checksum determination process when the power is restored is a stack pointer (SP) operation-dedicated instruction, and the source code “ In addition to “POP DE”, source codes “POP HL”, “POP AF”, and the like exist.

[Main processing of pachislot by control of main CPU]
Next, with reference to FIG. 82, the main process (main operation process) of the pachi-slot 1 executed under the control of the main CPU 101 will be described. FIG. 82 is a flowchart showing the procedure of main processing (hereinafter referred to as main flow).

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address at the end of one game in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the start of initialization, and starts from the start address in the game RAM area. Erase (clear) information up to the last address. The storage area in this range is a storage area that needs to be erased for each unit game (game) such as an internal winning combination storage area or a display combination storage area.

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this processing, the main CPU 101 performs input check processing such as a medal sensor (not shown) and the start switch 79. The details of the medal acceptance / start check process will be described later with reference to FIG. 83 described later.

  Next, the main CPU 101 performs random number acquisition processing (S203). In this processing, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: the value of the random number register 0 of the random number circuit 110 to be a hard latch random number) or a random number value for effects used in various lotteries related to ART ( 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 serving as a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 serving as a soft latch random number) The various random numbers extracted are stored in a random value storage area (not shown) provided in the main RAM 103. Details of the random number acquisition process will be described later with reference to FIG. 91 described later.

  Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 92 described later.

  Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. Etc. Details of the symbol setting process will be described later with reference to FIG. 97 described later.

  Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates start command data to be transmitted to the sub control circuit 200 and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. Note that the start command includes a parameter (such as a subflag) that identifies an internal winning combination.

  Next, the main CPU 101 performs a second interface board control process (S207). Note that the second interface board control process is executed in a non-standard work area of the main RAM 103. Details of the second interface board control process will be described later with reference to FIG.

  Next, the main CPU 101 performs state-specific control processing (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-specific control processing will be described later with reference to FIG.

  Next, the main CPU 101 performs reel stop initial setting processing (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (see FIG. 26), and sets the pull-in priority table selection table number, the pull-in priority table number, and the stop table number based on the internal winning combination and the gaming state. Processing to acquire, processing to store “3” in the stop button non-operation counter, and the like are performed.

  Next, the main CPU 101 performs reel rotation start processing (S210). In this process, the main CPU 101 requests the start of rotation of all reels. When it is requested to start rotation of all reels, three stepping motors (not shown) are driven by an interrupt process (see FIG. 158, which will be described later) executed at a constant cycle (1.1172 msec). Is controlled, and rotation of the left reel 3L, the middle reel 3C, and the right reel 3R is started. Next, each reel is controlled to be accelerated until its rotational speed reaches a constant speed, and then controlled so as to maintain the constant speed.

  Next, the main CPU 101 performs reel rotation start command generation / storage processing (S211). In this process, the main CPU 101 generates reel rotation start command data to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The reel rotation start command includes a parameter indicating that the reel rotation start operation has started.

  Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the pull-in priority data and stores it in the pull-in priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 126 described later.

  Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 performs stop control of rotation of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C, and the right stop button 17R are respectively pressed and the internal winning combination. Details of the reel stop control process will be described later with reference to FIG.

  Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 35) in the winning action flag storage area (see FIGS. 28 to 30). In this process, the main CPU 101 determines whether or not a display combination is displayed on the active line, and sets the number of medals to be paid out based on the determination result. Details of the winning search process will be described later with reference to FIG.

  Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 combines a winning request flag (internal winning combination) and a winning action flag (display combination), and determines the presence or absence of an illegal hit error based on the combined result. The details of the illegal hit check process will be described later with reference to FIG.

  Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a winning operation command generation process. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of display combination payouts determined in S214, and performs a medal payout process. Details of the winning check / medal payout process will be described later with reference to FIG.

  Next, the main CPU 101 performs a BB check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. Details of the BB check process will be described later with reference to FIG.

  Next, the main CPU 101 performs RT check processing (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination that is stopped and displayed on the active line. Details of the RT check process will be described later with reference to FIGS. 155 and 156 described later.

  Next, the main CPU 101 performs CZ / ART termination processing (S219). In this process, the main CPU 101 mainly performs a CZ pull-back lottery process. Details of the CZ / ART termination process will be described later with reference to FIG. After the process of S219 (after the end of one game), the main CPU 101 returns the process to the process of S201.

[Medal reception / start check processing]
Next, with reference to FIGS. 83 and 84, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 82) will be described. FIG. 83 is a flowchart showing the procedure of the medal acceptance / start check process, and FIG. 84 is a diagram showing an example of a source program for executing the processes of S231 to S233 during the medal acceptance / start check process. is there.

  First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is “1” or more, the main CPU 101 determines that there is an automatic insertion request. The automatic insertion medal counter is data for identifying whether or not a display combination relating to replay (replay) has been established in the previous unit game. When the display combination related to the re-game is established, the medals for the number of coins inserted in the previous unit game are automatically inserted into the automatic insertion medal counter.

  In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is “0” (when S221 is YES), the main CPU 101 performs the process of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not “0” (when S221 is NO), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, a medal insertion number LED lighting control process, and the like. The details of the medal insertion process will be described later with reference to FIG.

  Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is “0” (S224).

  In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not “0” (when S224 is NO), the main CPU 101 returns the process to S222 and repeats the processes after S222.

  On the other hand, when the main CPU 101 determines in S224 that the value of the automatic insertion medal counter is “0” (when S224 is YES), or when S221 is YES, the main CPU 101 stores the medal auxiliary storage. A warehouse switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not a medal can be inserted based on the result of the medal insertion state check process (S227).

  When the main CPU 101 determines in S227 that the medal cannot be inserted (when S227 is NO), the main CPU 101 performs a process of S231 described later.

  On the other hand, when the main CPU 101 determines in S227 that the medal can be inserted (when S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, for example, based on the medal sensor input state, the main CPU 101 determines whether or not a medal has passed normally, and credits the medal when a medal is inserted beyond a prescribed number. Perform processing. The details of the medal insertion check process will be described later with reference to FIG. 87 described later.

  Next, based on the result of the medal insertion check process, the main CPU 101 determines whether or not a medal can be inserted or credited (S229).

  When the main CPU 101 determines in S229 that the medal can be inserted or credited (YES in S229), the main CPU 101 performs a process of S231 described later. On the other hand, when the main CPU 101 determines in S229 that the medal cannot be inserted or credited (NO in S229), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24.

  After S230, when S227 is NO or when S229 is YES, the main CPU 101 determines whether or not the current number of inserted medals is the game start possible number (S231). In the present embodiment, the number of games that can be started is three (see FIGS. 28 to 30).

  In S231, when the main CPU 101 determines that the current number of inserted medals is the game start number (when S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of inserted medals is not the game start possible number (when S231 is NO), the main CPU 101 determines whether or not there are medals inserted (S232). ).

  When the main CPU 101 determines in S232 that a medal has been inserted (when S232 is YES), the main CPU101 returns the process to S226 and repeats the processes after S226. On the other hand, when the main CPU 101 determines in S232 that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described in FIG. 68 (S233). In this processing, the main CPU 101 performs processing for generating and storing a setting change command at the start of setting confirmation.

  After the processing of S233 or when S231 is YES, the main CPU 51 determines whether or not the start switch 79 is on (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the ON state (when S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines in S234 that the start switch 79 is on (when S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24. After the process of S235, the main CPU 101 ends the medal acceptance / start check process, and moves the process to S203 of the main flow (see FIG. 82).

  In the present embodiment, the medal acceptance / start check process is performed as described above. The processing in S231 to S233 during the above-described medal acceptance / start check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. Among them, in the process of S233, the process is jumped to the address “SB_WVSC_00” of the execution program of the setting change confirmation process by the “CALLF” instruction which is the instruction code dedicated to the main CPU 101, and the setting change confirmation explained in FIG. 68 and FIG. Process.

  Then, the processing of S233 during the above-described medal acceptance / start check processing, that is, the setting change confirmation processing is executed regardless of the gaming state. Therefore, in this embodiment, regardless of the gaming state, that is, even if the gaming state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power interruption history, etc.)) are displayed. It is possible to confirm, and it is possible to suppress illegal acts such as goto.

[Medal insertion processing]
Next, with reference to FIGS. 85 and 86, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 83) will be described. FIG. 85 is a flowchart showing a procedure of medal insertion processing, and FIG. 86 is a diagram showing an example of a source program for executing medal insertion processing.

  First, the main CPU 101 adds “1” to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 performs medal insertion command generation / storage processing (S242). In this processing, the main CPU 101 generates medal insertion command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 every time a medal is inserted. The medal insertion command includes a parameter for specifying the number of inserted coins.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the medal insertion number based on the medal insertion number (medal counter value) (S244). In this process, for example, when the number of inserted medals is 1, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated. For example, the number of inserted medals is 3. LED lighting data for lighting all the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 uses the calculated LED lighting data to light up the corresponding medal insertion number display LED (S245). After the process of S245, the main CPU 101 ends the medal insertion process, and moves the process to S223 of the medal acceptance / start check process (see FIG. 83).

  In the present embodiment, the medal insertion process is performed as described above. The medal insertion process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. In the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the calculation process. This arithmetic processing is performed by the main CPU 101 sequentially executing source codes “LD A, L” to “OR L” in the source program shown in FIG.

  In this calculation process, first, by executing the source code “LD A, L”, data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, “00000011B” (decimal number “3”) is stored in the A register. In the present embodiment, 1-byte data is described as “*******”, but the last character “B” is “0” or “1” indicated before the character “B”. "Means bit data.

  Next, by executing the source code “ADD A, A”, the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, if the data stored in the A register before the execution of the “ADD” instruction is “00000011B” (when the number of inserted medals is three), the addition result is obtained by the “ADD” instruction. “00000110B” is stored in the A register.

  Next, by executing the source code “DEC A”, 1 is subtracted from the data stored in the A register, and the subtraction result is stored in the A register. For example, when the data stored in the A register before the execution of the “DEC” instruction is “00000110B”, “00000101B” as a subtraction result is stored in the A register by the “DEC” instruction. .

  Next, by executing the source code “OR L”, a logical sum operation is performed on the data stored in the L register (the number of inserted medals) and the data stored in the A register, and the operation result is stored in the A register. Stored. For example, when the data stored in the A register before the execution of the “OR” instruction is “00000101B” and the data stored in the L register is “00000011B” (the number of inserted medals is 3) In this case, “000011B”, which is the result of the logical OR operation of both data, is stored in the A register by this “OR” instruction. The data stored in the A register by the execution of the “OR” instruction becomes LED lighting data for displaying the number of medal insertions (data indicating the lighting state of the medal insertion LED).

  For example, when the number of inserted medals is 3, as described above, the final calculation result “00000111B” is displayed for displaying the number of inserted medals by the calculation processing of the LED lighting data for displaying the number of inserted medals in S244. LED lighting data. In this embodiment, “0” of bit 0 of the finally calculated LED lighting data is “ON / OFF” of the output port to the first medal insertion number display LED (first LED). "1/0" of bit 1 corresponds to the "on / off" state of the output port to the LED for displaying the second medal insertion number (second LED), and "1" of bit 2 "/ 0" corresponds to the "ON / OFF" state of the output port to the third medal insertion number display LED (third LED). Therefore, when the number of inserted medals is 3, as described above, “00000111B” is generated as the LED lighting data, so that all output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the on state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

  When the LED lighting data for displaying the number of inserted medals is generated by the arithmetic processing as described above, the table data to be referred to when generating the LED lighting data for displaying the number of inserted medals is unnecessary, so the table area of the main ROM 102 Free space can be increased, and an increase in program capacity can be minimized. That is, in the above-described medal insertion process of the present embodiment, the medal insertion LED display process can be made more efficient, the free capacity of the main ROM 102 is secured (increased), and the increased free area is utilized, It becomes possible to improve game nature.

[Medal insertion check process]
Next, with reference to FIGS. 87 and 88, the medal insertion check process performed in S228 in the medal acceptance / start check process (see FIG. 83) will be described. 87 is a flowchart showing the procedure of the medal insertion check process, and FIG. 88 is a diagram showing an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

  First, the main CPU 101 determines whether or not replaying is in progress (S251).

  When the main CPU 101 determines in S251 that the game is being replayed (if S251 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 83). To S229.

  On the other hand, when the main CPU 101 determines in S251 that the game is not being replayed (when S251 is NO), the main CPU 101 permits medal acceptance (S252). In this processing, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 24 are accepted. The received medals are counted and guided to the hopper device 51.

  Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1 bet button 15b) has been operated based on the on / off state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the bet button check process in S253 (S254).

  When the main CPU 101 determines in S254 that the betting operation has been completed (when S254 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 83). To S229.

  On the other hand, when the main CPU 101 determines in S254 that the betting operation has not been completed (in the case where S254 is NO), the main CPU 101 determines the medal sensor input state (game medium acceptance state) during the current process, The medal sensor input state at the time of the previous process is acquired (S255). The medal sensor input state is information indicating the passage status of medals received in the medal insertion slot 24 in the selector 66, and the detection results of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by

  In this embodiment, the medal sensor input state is represented by 1-byte (8-bit) data, and the first medal sensor (not shown) on the upstream side provided side by side in the medal passage direction at the exit of the selector 66. The detection result corresponds to the information of bit 0 (“0” or “1”), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the information of bit 1 (“0” or “1”). To do. When the passage of the medal is detected by the first medal sensor, “1” is set to the bit 0, and when the passage of the medal is detected by the second medal sensor, “1” is set to the bit 1. Is done. Therefore, the medal sensor input state “00000000B” indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state “00000001B” indicates the state when the medal passage starts, and the medal sensor input state “ “00000011B” indicates a state in which a medal is passing, and a medal sensor input state “00000010B” indicates a state immediately before completion of medal passing.

  Next, the main CPU 101 determines whether or not the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (S256).

  In S256, when the main CPU 101 determines that the medal sensor input state during the current process has not changed from the medal sensor input state during the previous process (when S256 is NO), the main CPU 101 proceeds to S261 described below. Process.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (when S256 is YES), the main CPU 101 Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained in the current process is generated by arithmetic processing (S257).

  In this process, when the medal sensor input state at the time of the previous process is “00000000B” (when both the first and second medal sensors are not detected), the normal change value of the medal sensor input state is used. When “00000001B” (when the first medal sensor is medal detection and the second medal sensor is not medal detection) is generated, and the medal sensor input state at the previous processing is “00000001B”, the medal sensor As a normal change value of the input state, “00000011B” (when both the first and second medal sensors are medal detection) is generated. In this process, if the medal sensor input state at the previous process is “00000011B”, the normal change value of the medal sensor input state is “00000010B” (the first medal sensor is not detected, the second When the medal sensor is medal detection) and the medal sensor input state at the time of the previous process is “00000010B”, the normal change value of the medal sensor input state is “00000000B” (first and second medals). When both medals have not been detected yet). The method for generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current process is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition in S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

  In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not the same as the normal change value generated in S257 (when S258 is NO), the main CPU 101 performs the process of S262 described later. Do.

  On the other hand, when the main CPU 101 determines in S258 that the medal sensor input state at the current process is the same as the normal change value generated at S257 (when S258 is YES), the main CPU 101 It is determined whether or not the medal sensor input state is a medal passing state (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is a state when the medal passes (when S259 is YES), the main CPU 101 performs the process of S263 described later.

  In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not a medal passage state (when S259 is NO), the main CPU 101 sets a medal passage check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to the medal sensor input state at the time of the current process, for example.

  After the processing of S260 or when S256 is NO, the main CPU 101 determines whether the medal sensor input state at the time of the current processing is a state in which a medal is passing (“00000011B”) and the medal passing check timer is stopped. Is determined (S261). In this determination process, it is determined whether or not a medal passage error (inserted medal passage time error) has occurred, and when the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passage error has occurred.

  In S261, when the main CPU 101 determines that the determination condition of S261 is not satisfied (when S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is YES), or when S258 is NO, that is, a medal passing error or a medal retrograde error has occurred. When it is determined that the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation / storage process. Details of error processing will be described later with reference to FIG. 89 described later. After the process of S262, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  Here, returning to the process of S259 again, if S259 is YES, the main CPU 101 determines whether or not a prescribed number (three in this embodiment) of medals has been inserted (S263). .

  In S263, when the main CPU 101 determines that the prescribed number of medals has not been inserted (when S263 is NO), the main CPU 101 performs the medal insertion process described with reference to FIG. 85 (S264). After the process of S264, the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines in S263 that the specified number of medals has been inserted (when S263 is YES), the main CPU 101 adds “1” to the value of the credit counter (S265). ). Next, the main CPU 101 performs medal insertion command generation storage processing (S266). In this processing, the main CPU 101 generates medal insertion command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the credit number of medals is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

  When the main CPU 101 determines that the medal credit number is not the upper limit value in S267 (when S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, when the main CPU 101 determines in S267 that the credit number of medals is the upper limit value (when S267 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check. The process proceeds to S229 in the process (see FIG. 83).

  In the present embodiment, the medal insertion check process is performed as described above. Then, the processing of S255 to S258 during the above-described medal insertion check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among them, the generation process of the normal change value of the medal sensor input state in S257 is performed not by the process of obtaining with reference to the table but by the calculation process. Specifically, the normal change value generation process is performed by the main CPU 101 executing the source code “RLA” and “AND cBX_MDINSW” in the source program shown in FIG. 88 in this order.

  The “RLA” instruction is an instruction code that shifts 1-byte data stored in the A register to the left (in the direction from bit 0 to bit 7) once (one bit). In the example shown in FIG. 88, 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LD A, B” executed before the “RLA” instruction is the “RLA” instruction. Shifts to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code “CP cBX_MDISW2” executed before the “RLA” instruction.

  The “CP” instruction is an instruction code for executing a comparison operation. “CBX_MDISW2” is 1-byte data, and is “00000010B” in the present embodiment. When the source code “CP cBX_MDISW2” is executed, 1-byte data indicating the previous medal sensor input state stored in the A register is compared with “cBX_MDISW2 (00000010B)”.

  If the result of executing the source code “CP cBX_MDISW2” indicates that the 1-byte data indicating the previous medal sensor input state is less than “cBX_MDISW2 (00000010B)”, the carry flag of the flag register F is obtained. “1” is set in (see FIG. 11), and the carry flag “1” of the flag register F is stored in bit 0 of the A register when the “RLA” instruction is executed. On the other hand, as a result of executing the source code “CP cBX_MDISW2”, if the result that the 1-byte data indicating the previous medal sensor input state is “cBX_MDISW2 (00000010B)” or more is obtained, the carry flag of the flag register F “0” is set in (see FIG. 11), and the carry flag “0” of the flag register F is stored in bit 0 of the A register when the “RLA” instruction is executed.

  Therefore, for example, if the 1-byte data indicating the previous medal sensor input state is “00000000B (before or after passing medal) (<cBX_MDISW2”), the “RLA” command If “00000001B” is generated by execution, and the 1-byte data indicating the previous medal sensor input state is “00000001B (the state at the start of medal passage)” (<cBX_MDISW2 ”), the“ RLA ”instruction is executed. As a result, “00000011B” is generated. On the other hand, for example, if 1-byte data indicating the previous medal sensor input state is “00000011B (medal passing state)” (> “cBX_MDISW2”), “00000110B” is generated by executing the “RLA” instruction. If the 1-byte data indicating the previous medal sensor input state is “00000010B (state immediately before completion of medal passage)” (= “cBX_MDISW2”), “00000100B” is generated by executing the “RLA” instruction. The

  Next, when the source code “AND cBX_MDINSW” is executed, 1-byte data (stored data in the A register) generated by executing the “RLA” instruction is logically ANDed with 1-byte data “cBX_MDINSW”, and the medal sensor A normal change value of the input state is calculated. The 1-byte data “cBX_MDISW” is “00000011B” in the present embodiment. Therefore, when the source code “AND cBX_MDINSW” is executed, only the data of bit 0 and bit 1 in the data stored in the A register is masked, and the other bit data becomes “0”.

  As a result, for example, if 1-byte data indicating the previous medal sensor input state is “00000000B (the state before passing the medal)”, the normal change value of the medal sensor input state is “00000001B (the state when the medal passage is started). ) ”Is generated, and if 1-byte data indicating the previous medal sensor input state is“ 00000001B (the state at the start of medal passage) ”, the normal change value of the medal sensor input state is“ 00000011B (the medal passing state). Status) "is generated. On the other hand, for example, if 1-byte data indicating the previous medal sensor input state is “00000011B (medal passing state)”, the normal change value of the medal sensor input state is “00000010B (state immediately before completion of medal passing)”. ”Is generated, and if the 1-byte data indicating the previous medal sensor input state is“ 00000010B ”(a state immediately before completion of medal passage), the normal change value of the medal sensor input state is“ 00000000B (after the medal passage (passing) State) ”is generated.

  As described above, by changing the detection process of the change state of the medal sensor input state from the table reference process to the calculation process, the free space in the table storage area of the main ROM 102 can be increased, and the program capacity can be increased. Can be minimized. Therefore, by adopting the above-described method, it is possible to improve the efficiency of the medal insertion sensor state detection process, and it is possible to improve the gameability by utilizing the increased free space in the main ROM 102.

[Error handling]
Next, with reference to FIGS. 89 and 90, for example, the error process performed in S262 during the medal insertion check process (see FIG. 87) will be described. FIG. 89 is a flowchart showing a procedure of error processing, and FIG. 90 is a diagram showing an example of the configuration of an error table that is actually referred to on the error processing source program.

  In the error table shown in FIG. 90, for each 1-byte data (eg, 1-byte data stored in the address “dERR_HE” in FIG. 90) indicating the on / off state of the port indicating the type of error factor, Error display data (for example, 1-byte data stored in addresses “dERR_HE + 1” and “dERR_HE + 2” in FIG. 90) is defined. This error display data is output to a 2-digit 7-segment LED (used for both the payout number display and the error display) included in the information display 6.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 performs evacuation processing of medal payout number display data (S272).

  Next, the main CPU 101 performs error table setting processing (S273). By this processing, the head address of the error table shown in FIG. 90 is set on the source program.

  Next, the main CPU 101 acquires an error factor (S274). Note that the error factor acquired in this process varies depending on the process from which the currently processed error process is read. As the error factors to be targeted in the present embodiment, as shown in FIG. 90, “hopper empty error”, “hopper jam error”, “inserted medal passage count error”, “inserted medal passage check error”, “ The “inserted medal passage check error”, “inserted medal passage time error”, “inserted medal retrograde error”, “inserted medal auxiliary storage full error”, and “illegal hit error” are defined. For example, if an error process is read after the process of S258 during the medal insertion check process, “inserted medal retrograde error (Cr)” in FIG. 90 is acquired as an error factor in this process. For example, when an error process is read after the process of S261 during the medal insertion check process, the “inserted medal passage time error (CE)” in FIG. 90 is acquired as an error factor in this process. .

  Next, the main CPU 101 acquires error display data from the error table and error factors (S275). For example, when the error factor is “inserted medal retrograde error (Cr)”, the error display data shown in FIG. 90 is output as error display data to be output to the upper 7-segment LED of the 2-digit 7-segment LED in this process. 1-byte data “01001110B” stored at address “dERR_CR + 1” in the table is acquired, and 1-byte data “00001001B” stored at address “dERR_CR + 2” is output as error display data to the 7-segment LED of the lower digit. Is acquired. In this case, two characters “Cr” are displayed as error information on the two-digit 7-segment LED.

  Next, the main CPU 101 performs error command (occurrence) generation and storage processing (S276). In this process, the main CPU 101 generates error command data to be transmitted to the sub control circuit 200 when an error occurs, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. . An error command at the time of occurrence of an error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The error command when an error occurs includes a parameter indicating the error occurrence.

  Next, the main CPU 101 performs standby processing for one interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been canceled (S278).

  When the main CPU 101 determines in S278 that the error has not been canceled (when S278 is NO), the main CPU 101 returns the process to the process of S277 and repeats the processes after S277.

  On the other hand, when the main CPU 101 determines in S278 that the error has been canceled (in the case where S278 is YES), the main CPU 101 performs error factor clear processing (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a return process of the payout number display data of medals saved in S272 (S280).

  Next, the main CPU 101 performs error command (cancellation) generation and storage processing (S281). In this process, the main CPU 101 generates error command data at the time of error cancellation to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. . The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. The error command at the time of error cancellation includes a parameter indicating error cancellation. After the process of S281, the main CPU 101 ends the error process, and moves the process to S253 in the medal insertion check process (see FIG. 87), for example. In the error cancellation, the error factor that has occurred is canceled, and the error state is canceled by pressing the reset switch 76.

[Random number acquisition processing]
Next, with reference to FIG. 91, the random number acquisition processing performed in S203 in the main flow (see FIG. 82) will be described. FIG. 91 is a flowchart showing the procedure of random number acquisition processing.

  First, the main CPU 101 acquires the hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as the random number value for the internal winning combination lottery in the random value storage area (invalid) in the main RAM 103. (S291).

  Next, the main CPU 101 generates soft latch random numbers (0 to 65535: production random numbers used in ART-related lottery processing, and 0 to 255: 1 byte random processing). To set the soft latch random number acquisition register (S292). Next, the main CPU 101 sets the number of acquired soft latch random numbers (for example, 7) (S293).

  Next, the main CPU 101 obtains the acquired number of soft latch random numbers at once and stores the acquired number of soft latch random numbers in the random number storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random value storage area. It is stored in an area different from the area where the latch random number (random number value for internal winning combination lottery) is stored. After the process of S294, the main CPU 101 ends the random number acquisition process, and moves the process to S204 of the main flow (see FIG. 82). In this embodiment, in order to store four 2-byte random numbers and four 1-byte random numbers, a 12-byte storage area is allocated as a random number storage area in the main RAM 103.

[Internal lottery processing]
Next, the internal lottery process performed in S204 in the main flow (see FIG. 82) will be described with reference to FIGS. 92 is a flowchart showing the procedure of the internal lottery process, FIG. 93A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. It is a figure which shows an example of the source program for performing the process of S308-S309 in an internal lottery process.

  FIG. 94 is a diagram showing an example of the configuration of an internal lottery table (for general games) that is actually referred to on the source program for internal lottery processing, and FIG. It is a figure which shows an example of the structure of the lot value selection table classified by RT state actually referred. Further, FIG. 96 shows an internal lottery value table selection table, a 1-byte internal lottery value table, a 2-byte internal lottery value table, and a 1-byte internal lottery value table that are actually referred to on the internal lottery processing source program. It is a figure which shows an example of a structure of the internal lottery value table classified by 2 bytes setting. In the present embodiment, an internal lottery table for RB (BB) is also provided, but here, the configuration of the internal lottery table for RB referred to on the source program of the internal lottery processing is illustrated. Omitted.

  First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 performs a check process for the current game setting value (any one of 1 to 6) and the number of inserted medals (three in this embodiment).

  Next, the main CPU 101 sets the internal lottery table for general games and the number of lotteries (53 times in this embodiment) (S302). In this process, the value (winning request flag status) of “special prize winning number + small bonus winning number” in the internal lottery table (for general game) shown in FIG. 94 is set in the C register, and “lottery value selection table or The value of the “lottery coefficient table” (determination data: data related to the address) is set in the A register. As shown in FIG. 94, the winning request flag status is a special prize winning number (“00H (out)”, “01H (BB1)”, “02H (BB2)”: 0, 1, 2 in decimal number). “25H (hexadecimal: 37 in decimal notation (special prize number described later)) is added to the small combination winning number (“ 00H ”to“ 24H ”: 0 to 36 in decimal) .

  Next, the main CPU 101 determines whether or not the RB is operating (S303). In S303, when the main CPU 101 determines that the RB is not operating (when S303 is NO), the main CPU 101 performs a process of S305 described later.

  On the other hand, when the main CPU 101 determines in S303 that the RB is operating (when S303 is YES), the main CPU 101 determines the internal lottery table for RB and the number of lotteries (in this embodiment, five times). Set (S304). In this process, the internal lottery table and the number of lotteries for the general game set in S302 are overwritten with the internal lottery table for the RB and the number of lotteries.

  After the process of S304 or when S303 is NO, the main CPU 101 acquires the determination data (data relating to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether the determination data is RT state data (S306). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the RT state. Specifically, the main CPU 101 determines whether or not the address defined in the currently acquired determination data of the lottery object combination is an address in the RT state-specific lottery value selection table shown in FIG. .

  For example, in the determination data “(dRPPPTR01−dRTRB_SEL) * 2 + 001H” associated with the internal winning combination “F_Chilelip” in the internal lottery table of FIG. 94, the internal winning combination in the RT state-specific lottery value selection table shown in FIG. Since the address “dRPPPTR01” of the combination “F_Chillilip” is defined, the determination data associated with the internal winning combination “F_Chillilip” corresponds to the RT state-specific data. Therefore, when the lottery target combination that is currently acquired is the internal winning combination “F_Chillilip”, the main CPU 101 determines in the process of S306 that the determination data is RT state-specific data.

  In S306, when the main CPU 101 determines that the determination data is not RT state data (when S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, when the main CPU 101 determines in S306 that the determination data is the RT state-specific data (when S306 is YES), the main CPU 101 selects the RT state lottery value shown in FIG. 95 based on the determination data. Selection data is acquired from the table, and the acquired selection data is set as determination data (S307).

  After the processing of S307 or when S306 is NO, the main CPU 101 determines whether the determination data of the lottery target combination is data by setting (S308). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the set value. Specifically, the main CPU 101 determines that the address specified in the currently acquired lottery object combination determination data is in the 1-byte setting internal lottery value table or 2-byte setting internal lottery value table shown in FIG. It is determined whether it is the address.

  For example, in the determination data “((dNMLB00F289−dPRB_DB_WV) / 6 + 080H” associated with the internal winning combination “F_strong Chile 1” in the internal lottery table of FIG. Since the address “dNMLB00F289” of the internal winning combination “F_strong Chile 1” in the lottery value table is defined, the determination data associated with the internal winning combination “F_Strong Chile 1” corresponds to the setting-specific data. To do. Therefore, when the lottery target combination currently acquired is the internal winning combination “F_strong Chile 1”, the main CPU 101 determines that the determination data is the setting-specific data in the process of S308.

  In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, when the main CPU 101 determines in S308 that the determination data is data by setting (when S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). Note that the setting value data added to the determination data in this process is data associated with the setting value, but the setting value data “0” to “5” are not values of the setting value itself, but “ Data corresponding to “Setting 1” to “Setting 6”.

  After the processing of S309 or when S308 is NO, the main CPU 101 calculates the address of the area where the lottery value of the lottery target role is stored based on the set determination data (address data), and sets the address The stored lottery value is acquired (S310).

  In the process of S310, for example, when the lottery target combination is an internal winning combination “F_Sabo2” whose lottery value does not depend on both the RT state and the set value, the 1-byte internal lottery value table shown in FIG. The lottery value “128” stored in the address “dNM_B00F26” is acquired. For example, when the lottery target combination is an internal winning combination “F_RT3 Lip_1st” whose lottery value changes depending on the RT state, and the RT state is the RT2 state, the 2-byte internal lottery value table shown in FIG. The lottery value “1800” stored in the address “dRT2B00F13456” is acquired.

  In the process of S310, for example, when the lottery target combination is an internal winning combination “F_strong Chile 1” whose lottery value varies depending on the set value, an internal lottery value table classified by 1 byte setting shown in FIG. 6 types of lottery values “150 (setting 1), 150 (setting 2), 150 (setting 3), 150 (setting 4), 160 (setting 5), 170 (setting 6)” A lottery value corresponding to the set value is acquired. At this time, the lottery value corresponding to the set value is acquired by specifying the address obtained by adding the set value data to the determination data (processing in S309). Therefore, for example, when the lottery target combination is “F_strong 1” and the set value is “6” (set value data is “5”), the lottery value “0” stored in the address “dNMLB00F289 + 5” is stored. 170 "is acquired.

  In the present embodiment, when the lottery value depends on both the RT state and the set value, such as the internal winning combination “F_Maintenance Lip A”, for example, the internal lottery value table and the internal lottery classified by setting are used. The lottery value is acquired with reference to both of the value tables.

  Next, the main CPU 101 acquires a random number value (any one of 0 to 65535) for internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 performs lottery execution processing (S312). In this process, the main CPU 101 adds the random number acquired in S311 to the lottery value acquired in S310, and sets the addition result as a lottery result (winning / non-winning for the lottery target role). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (when overflowing), it is determined that the lottery target combination is won (the lottery target combination is determined as an internal winning combination). The

  Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not a lottery execution process has been won (whether or not an overflow has occurred) (S314).

  In S314, when the main CPU 101 determines that the lottery execution process has been won (when S314 is YES), the main CPU 101 refers to the internal lottery table, and the winning request flag status (corresponding to the internal winning combination won) “Value of special prize winning number + small role winning number”) is acquired (S315). For example, in a general game, when winning the lottery execution process when the lottery target role is “F_definite chip”, the winning request flag status “(00H * 25H) + 02H” (special prize winning number = 0, small winning number = 2) is acquired. Then, after the process of S315, the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 82).

  On the other hand, when it is determined in S314 that the main CPU 101 has not won the lottery execution process (when S314 is NO), the main CPU 101 updates the lottery object combination to the next combination in the internal lottery table, and lottery is performed. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the number of lotteries after subtraction is not “0” (when S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

  On the other hand, when the main CPU 101 determines in S317 that the number of lotteries after subtraction is “0” (when S317 is YES), that is, when the internal winning combination is “out”, the main CPU 101 The lose status is set (S318). Note that the “losing status” corresponds to a hit request flag status in which both the special prize winning number and the small bonus winning number are “0”. Then, after the process of S318, the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 82).

  In the present embodiment, the internal lottery process is performed as described above. Note that the processing of S302 to S305 during the internal lottery processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 93A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 93A.

  For example, when the source code “LDIN ss, (HL)” is executed on the source program, a memory specified by an address set in the HL register (pair register) and an address obtained by adding “1” to the address. Is loaded into the ss (BC, DE, AC, AE, or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 93A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the determination data acquisition process of S305, as described above, the determination data (the value of the “lottery value selection table or lottery coefficient table”) is stored in the A register by the “LDIN” instruction (predetermined read instruction). Stored and the C flag is stored with a request flag status (value of “special prize winning number + small winning number”).

  As described above, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed with one instruction code ("LDIN" instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Further, the processing of S308 and S309 during the internal lottery processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 93B. Among them, the addition processing of the set value data (any one of 0 to 5) in S309 is performed by the main CPU 101 using the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM)” in FIG. 93B. This is done by executing in this order. Note that both the “MUL” instruction and the “ADDQ” instruction are instruction codes dedicated to the main CPU 101, and the “ADDQ” instruction is an instruction code dedicated to the main CPU 101 that performs address designation using the Q register (extension register).

  For example, when the source code “MUL A, n” is executed on the source program, the data stored in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code “MUL A, 6” in FIG. 93B, the contents (stored data) of the A register are multiplied by the 1-byte integer 6, and the multiplication result is stored in the A register. This multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachislot machine 1 of the present embodiment, an arithmetic dedicated circuit (arithmetic circuit 107) for executing multiplication processing and division processing on the source program is provided, so that the efficiency of the multiplication processing and division processing is improved. Can do.

  For example, when the source code “ADDQ r, (k)” is executed on the source program, the data stored in the Q register (upper address value) and a 1-byte integer k (direct value: lower address value) The data stored in the r register (A, B, C, D, E, H, or L register) is added to the memory contents (stored data) at the address specified in (), and the addition result is stored in the r register. The Therefore, when the source code “ADDQ A, (.LOW.wWAVENUM)” in FIG. 93B is executed, the data stored in the Q register and the memory at the address specified by the 1-byte integer value “.LOW.wWAVENUM” The contents (stored data) of the A register are added to the contents (set value data), and the addition result is stored in the A register.

  That is, in the example shown in FIG. 93B, in the setting value addition process of S309, the lottery table selection relative value is multiplied by the coefficient “6”, and the setting value data is added to the multiplied value, thereby The address of the lottery table in which the lottery values are stored is calculated.

  As described above, in the present embodiment, in the internal lottery process, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extension register) is used. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. Therefore, an instruction relating to address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Design setting process]
Next, the symbol setting process performed in S205 in the main flow (see FIG. 82) will be described with reference to FIGS.

  FIG. 97 is a flowchart showing the procedure of the symbol setting process. FIG. 98 is a correspondence table of special prize (bonus) winning numbers and small winning combination numbers and internal winning combinations. In FIG. 98, the special prize winning number and the small bonus winning number corresponding to “out (00)” are not shown. FIG. 99 is a diagram showing an example of a source program for executing the processes of S324 to S330 during the symbol setting process, and FIG. 100 is a hit actually referenced on the source program of the symbol setting process. It is a figure which shows an example of a structure of a request flag table (flag data table, winning flag table data).

  First, the main CPU 101 extracts a special prize winning number and a small bonus winning number based on the winning request flag status acquired in the internal lottery process, and the extracted special winning prize number and small bonus winning number are stored in the main RAM 103. It is stored in a winning number storage area (not shown) (S321).

  In the present embodiment, as shown in FIG. 98, special winning (bonus) winning numbers “1” and “2” are associated with internal winning combinations “F_BB1” and “F_BB2”, respectively. Further, the small winning combination numbers “1” to “36” are associated with the internal winning combinations “F_Chillilip” to “F_RB combination 4”, respectively. As described with reference to FIG. 94, the value of the winning request flag status is obtained by multiplying the special prize number by the special prize number (in the present embodiment, “37 (25H in hexadecimal)”) and the small prize winning number. It is the added value. Therefore, in the process of S321, in order to extract the special prize winning number and the small bonus winning number from the value of the winning request flag status, in this embodiment, the main CPU 101 sets the winning request flag status value as the special prize number (“37”). ). As a result, the value of the quotient generated by the division process becomes the special prize winning number (0 to 2 in decimal number), and the remainder value is the small winning number (any one of 0 to 36 in decimal number). Become.

  Next, the main CPU 101 determines whether or not a small combination is won based on the extracted small combination winning number (S322). In this process, when the small combination winning number is any one of 1 to 36, the main CPU 101 determines that the small combination winning number has been won, and when the small combination winning number is 0, the main CPU 101 It is determined that the small role did not win.

  In S322, when the main CPU 101 determines that a small role is not won (when S322 is NO), the main CPU 101 performs processing of S331 described later. On the other hand, when the main CPU 101 determines in S322 that the small combination has been won (when S322 is YES), the main CPU 101 sets the small combination winning number as an initial value of the subtraction result (S323).

  Next, the main CPU 101 sets a hit request flag table (see FIG. 100) (S324). Next, the main CPU 101 subtracts 1 from the subtraction result and updates the subtraction result (S325). Next, the main CPU 101 determines whether or not the subtraction result is less than “0” (S326).

  When the main CPU 101 determines in S326 that the subtraction result is not less than “0” (when S326 is NO), the main CPU 101 performs a bit number calculation process (S327). In the bit number calculation process of S327, the number of blocks in the storage area of the hit request flag data corresponding to the small combination winning number specified in the hit request flag table is acquired.

  In the present embodiment, in the hit request flag storage area (internal winning combination storage area), blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11 are provided. Therefore, the maximum value of the number of blocks in the storage area for the hit request flag data acquired in the bit number calculation process of S327 is “2”. For example, when the internal winning combination is “F_definite chip”, as shown in the hit request flag table (see FIG. 100), the storage area 7 included in the blocks of the hit request storage areas 0 to 7 and the hit request Since the hit request flag data is defined for each of the storage areas 9 included in the blocks of the storage areas 8 to 11, the number of blocks in the storage area for the hit request flag data acquired in the bit number calculation process of S327 is “2”. It becomes.

  Next, the main CPU 101 performs a bit number calculation process (S328). In the bit number calculation process in S328, the number of bytes of hit request flag data in block units defined in the hit request flag table (see FIG. 100) is calculated. For example, when the internal winning combination is “F_definite chip”, both the storage area 7 and the storage area 9 store 1-byte hit request flag data as shown in the hit request flag table (see FIG. 100). Therefore, the number of bytes of the per-block request flag data acquired in the bit number calculation process of S328 is 1 byte. In the table shown in FIG. 100, the hit request flag data stored in the storage area 7 is described as “10000000B | 01000000B”. This is because the hit request flag data stored in the storage area 7 is It means “10000000B” or (“|” is a logical sum symbol) “01000000B”.

  In addition, the process of S325-S328 mentioned above is repeated by the frequency | count of a small winning number. For example, when the internal winning combination is “F_Challenging Lip” (the small winning combination number is “2”), the above-described processing of S325 to S328 is repeated twice. In addition, when the processes of S325 to S328 are repeated a plurality of times, the number of blocks and the number of bytes of the per-block hit request flag data respectively obtained in the bit number calculation processes of S327 and S328 are stored in separate storage areas. Is done. Further, the number of blocks and the number of bytes of hit request flag data in units of blocks obtained by the above-described processing of S325 to S328 are information (on-bit information) for specifying the storage destination of the hit request flag data.

  Here, returning to the process of S326 again, when the main CPU 101 determines in S326 that the subtraction result is less than “0” (when S326 is YES), the main CPU 101 determines the hit request flag storage area ( The internal winning combination storage area) is set (S329). At this time, the main CPU 101 determines the hit request flag to be checked (updated) based on the number of blocks obtained by the above-described processing of S325 to S328 and the number of bytes of hit request flag data (on-bit information) in block units. Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register (see FIG. 99).

  Next, the main CPU 101 performs compressed data storage processing (S330). In this process, the main CPU 101 mainly performs a process of transferring (developing) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). Details of the compressed data storage processing will be described later with reference to FIG.

  After the process of S330 or when S322 is NO, the main CPU 101 refers to the carryover combination storage area (see FIG. 31) and determines whether there is a carryover combination (S331). When the main CPU 101 determines in S331 that there is a carryover combination (when S331 is YES), the main CPU 101 performs a process of S334 described later.

  On the other hand, when the main CPU 101 determines in S331 that there is no carryover combination (when S331 is NO), the main CPU 101 determines the bonus combination (BB1 or BB2) based on the special prize winning number extracted in the process of S321. ) Is determined whether or not (S332).

  In S332, when the main CPU 101 determines that the bonus combination is not won (when S332 is NO), the main CPU 101 ends the symbol determination process, and the process proceeds to S206 of the main flow (see FIG. 82). Transfer.

  On the other hand, when the main CPU 101 determines that the bonus combination is won in S332 (when S332 is YES), the main CPU 101 stores the winning prize winning number in the carryover combination storage area (S333).

  After the processing of S333 or when S331 is NO, the main CPU 101 sets the special prize winning number in the winning number storage area (not shown), sets the winning request flag data in the winning request flag storing area, and sets the RT state to RT5. The state is set, and the RT game number (the number of digested games in the RT1 state) is cleared (“0”) (S334). After the process of S334, the main CPU 101 ends the symbol setting process, and moves the process to S206 of the main flow (see FIG. 82).

  In the present embodiment, the symbol setting process is performed as described above. The processing of S324 to S330 (data compression / decompression processing related to winning) during the symbol setting processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. . Among them, the compressed data storage process of S330 is performed by the main CPU 101 executing the source code “CALLF SB_BTEP_00” in FIG.

  The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_BTEP_00” in FIG. 99 is executed, the process is performed at the address specified by “SB_BTEP_00”. The jump is made to start the compressed data storage process. In the compressed data storage process of S330, as described above, the hit request flag data (compressed data) stored in the hit request flag table is expanded (copied) into the corresponding hit request flag storage area.

  In addition, the process of setting the address of the hit request flag storage area in S329 during the symbol setting process described above is performed by the main CPU 101 executing the source code “LDQ DE, .LOW.wWAVEBIT” in FIG. That is, the process of S329 during the symbol setting process is performed by an “LDQ” instruction dedicated to the main CPU 101 that performs addressing using the Q register (extension register). In this case, the instruction code related to the address setting can be omitted on the source program for the symbol setting process, and the capacity of the source program for the symbol setting process (the capacity used in the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Furthermore, in this embodiment, the compression / decompression processing of the data related to winning is performed according to the processing procedure described in S324 to S330 during the above-described symbol setting processing, and the above-described instruction code dedicated to the main CPU 101 is included in the processing. By using it, it is possible to improve the efficiency of the compression / decompression processing of data related to winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Compressed data storage processing]
Next, with reference to FIG. 101, for example, the compressed data process performed in S330 during the symbol determination process (see FIG. 97) will be described. FIG. 101 is a flowchart showing the procedure of compressed data storage processing.

  The compressed data storage process shown in FIG. 101 is executed not only in S330 during the symbol determination process (see FIG. 97) but also in S649 during a symbol code acquisition process (see FIG. 128 described later). In the compressed data storage process executed in S330 during the symbol determination process (see FIG. 97), the flag data to be processed is the hit request flag data (flag data related to the winning combination). In the compressed data storage process executed in S649 (see FIG. 128 described later), the flag data to be processed is winning action flag data (flag data relating to a winning combination). The two processes are the same except that the types of flag data to be processed are different.

  Therefore, in the flowchart of FIG. 101, flag data to be processed is referred to as “processing target flag data”, and a flag table to be processed is referred to as “processing target flag table”. In accordance with this description, in the following explanation of the compressed data storage process, the winning request flag data or the winning action flag data is referred to as “processing target flag data”, and the winning request flag table (see FIG. 100) or described later. The symbol corresponding winning action table (for example, see FIG. 130A described later) is referred to as a “processing target flag table”.

  First, the main CPU 101 sets a storage location check bit (S341). In this processing, the storage destination check bit is stored in a register other than the A register.

  The storage destination check bit is 1-byte data for designating a block that is a storage destination (transfer destination) of processing target flag data. In the present embodiment, the winning request flag storage area and the winning action flag storage area are both composed of two blocks (a storage area 0-7 block and a storage area 8-11 block). Then, for example, when the internal winning combination “F_definite chip” is determined, the hit request flag data is stored in each of the storage area 7 and the storage area 9 as shown in the hit request flag table of FIG. (Since the number of storage destination blocks is “2”), in the process of S341, “00000011B” is set as the storage destination check bit. Note that the value of bit 0 (1/0) of the 1-byte data corresponds to the presence or absence of the storage destination in the blocks of the storage areas 0 to 7, and the value of bit 1 (1/0) is the storage areas 8 to 11. This corresponds to the presence or absence of the storage destination in the block.

  Next, the main CPU 101 sets the value of the transfer counter in bytes to “8” (S342). In this embodiment, since the number of bytes in each block is “8”, “8” is set as the initial value of the transfer counter.

  Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the process of S343, the storage destination check bit stored in the 1-byte register is right-shifted once (one bit). As a result, the transfer instruction bit is extracted. Specifically, when a 1-byte register (register other than the A register) storing the storage destination check bit is right-shifted once, the data stored in bits 7 to 1 is changed to bits 6 to 0, respectively. While moving, the data of bit 0 before the shift is output. The data output by this shift process becomes the value of the transfer instruction bit.

  Next, the main CPU 101 determines whether there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when “00000011B” is set as the storage destination check bit, transfer processing is performed in the determination process of S344 for the first time (corresponding to the first block of the storage area) and for the second time (corresponding to the second block of the storage area). Although it is determined that there is an instruction, it is determined that there is no transfer instruction in the determination process of S344 after the third time.

  In S344, when the main CPU 101 determines that there is no transfer instruction (when S344 is NO), the main CPU 101 performs the process of S354 described later.

  On the other hand, when the main CPU 101 determines in S344 that there is a transfer instruction (YES in S344), the main CPU 101 acquires byte unit storage location designation information from the processing target flag table (S345). In this processing, 1 indicating the transfer destination, which is stored at the start address of the area in which the flag data of the processing target combination (winning combination or winning combination) in the processing target flag table is stored as the byte unit storage location designation information. Byte data is obtained. For example, when the internal winning combination is “F_acceptance chip”, the storage stored in the head address of the area in which the flag data of “F_acceptance reply” in the hit request flag table shown in FIG. 1-byte data “10000000B” designating the area 7 as a transfer destination is acquired as byte unit storage location designation information.

  Next, the main CPU 101 performs an update process of an address referred to in the process target flag table (a process of adding 1 to the address) (S346). In this process, the main CPU 101 sets an address that designates the head storage area of the block that is the storage (transfer) destination of the processing target flag data as an initial address. For example, in the process of the first block, the address of the storage area 0 is set as the initial address in the process of S346, and in the process of the second block, the address of the storage area 8 is set as the initial address in the process of S346. .

  Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage location designation information (S347). Note that the transfer instruction bit here corresponds to bit 0 of the byte unit storage location designation information, and in the process of S347, the byte unit storage location designation information stored in the 1 byte register is shifted once to the right. Thus, the value of the transfer instruction bit is extracted (bit 0 data is output).

  Next, the main CPU 101 determines whether there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when “00000010B” is set as the byte unit storage location designation information, the data “1” of bit 1 in the processing of S347 for the second time (storage area 1 of the first block or storage area 9 of the second block). Is output as the value of the transfer instruction bit, and it is determined that there is a transfer instruction, but in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

  When the main CPU 101 determines in S348 that there is no transfer instruction (when S348 is NO), the main CPU 101 performs the process of S351 described later.

  On the other hand, when the main CPU 101 determines that there is a transfer instruction in S348 (when S348 is YES), the main CPU 101 determines the processing target flag stored at the address in the currently set processing target flag table. Data (winning request flag data or winning action flag data) is transferred (copied) to the designated storage area (S349).

  For example, if the internal winning combination is “F_definite chip” and the current process is being performed on the storage area (storage areas 0 to 7) of the first block, the byte unit storage location designation information is “ 10000000B "(data designating the storage area 7 as the storage destination), it is determined that there is a transfer instruction in the process of S347 for the eighth time, and in subsequent processes of S349, the hit request flag data" 10000000B "," 01000000B " ”,“ 00100000B ”, and“ 00010000B ”are transferred (copied) to the storage area 7 of the hit request flag storage area.

  Next, the main CPU 101 performs an update process of an address referred to in the process target flag table (a process of adding 1 to the address) (S350).

  After the process of S350 or when S348 is NO, the main CPU 101 performs an address update process (a process of adding 1 address) that specifies a storage area that is a storage destination of the processing target flag data (S351). Next, the main CPU 101 subtracts 1 from the value of the transfer counter (S352).

  Next, the main CPU 101 determines whether or not the value of the transfer counter is “0” (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not “0” (when S353 is NO), the main CPU 101 returns the process to the process of S347 and repeats the processes after S347.

  On the other hand, in S353, when the main CPU 101 determines that the value of the transfer counter is “0” (in the case of YES determination in S353), the main CPU 101 determines whether the transfer instruction target remains in the current storage destination check bit. It is determined whether or not (S354). In this process, the main CPU 101 determines whether or not there remains a bit storing “1” in the storage destination check bit at the time of the current process. Then, the main CPU 101 instructs to transfer to the current storage destination check bit when there is a bit storing “1” in the storage destination check bit, that is, when there is a block to be processed. It is determined that the target remains.

  When the main CPU 101 determines in S354 that the transfer instruction target remains in the current storage location check bit (when S354 is YES), the main CPU 101 returns the process to the process of S342, and the processes after S342 repeat. On the other hand, when the main CPU 101 determines in S354 that there is no transfer instruction target remaining in the current storage destination check bit (when S354 is NO), the main CPU 101 ends the compressed data storage process and performs the process. For example, the process proceeds to S331 in the symbol determination process (see FIG. 97).

[Second interface board control processing (not specified)]
Next, the second interface board control process performed in S207 in the main flow (see FIG. 82) will be described with reference to FIG. FIG. 102 is a flowchart showing the procedure of the second interface board control process. This process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. The program used in the second interface board control process is stored in an unspecified area in the main ROM 102 (see FIG. 12B).

  First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 to the stack pointer (SP) (S362).

  Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in an unspecified work area in the main RAM 103 (S364).

  Next, the main CPU 101 refers to the navigation conversion table and acquires the second interface push order number (S365). Next, the main CPU 101 stores the acquired second interface push order number in a specified extra push order number storage area (not shown) provided in the extra work area (S366). Next, the main CPU 101 sets “0” to the value of the pressed position table selection counter provided in the non-standard work area (S367).

  Next, the main CPU 101 determines whether or not the acquired navigation data is push order navigation (navigation data for a push order small combination) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is push order navigation (when S368 is YES), the main CPU 101 performs the process of S372 described later.

  On the other hand, when the main CPU 101 determines in S368 that the acquired navigation data is not push order navigation (when S368 is NO), the main CPU 101 determines that the acquired navigation data is navigation data for BB1 stop operation (10). It is determined whether or not (S369).

  In S369, when the main CPU 101 determines that the acquired navigation data is navigation data for BB1 stop operation (when S369 is YES), the main CPU 101 performs the process of S371 described later. On the other hand, when the main CPU 101 determines in S369 that the acquired navigation data is not navigation data for the BB1 stop operation (when S369 is NO), the main CPU 101 sets “1” to the value of the pressed position table selection counter. Are added (S370). In S370, the process of adding “1” to the value of the pressed position table selection counter is a process performed to acquire the pressed position of BB2 from the pressed position table (not shown).

  After the process of S370 or when S369 is YES, the main CPU 101 adds “1” to the value of the pressed position table selection counter (S371). In S371, the process of adding “1” to the value of the pressed position table selection counter is a process performed to acquire the pressed position of BB1 or BB2 from the pressed position table (not shown).

  After the process of S371 or when S368 is YES, the main CPU 101 selects a pressed position table (not shown) based on the value of the pressed position table selection counter (S372). Next, the main CPU 101 refers to the selected pressing position table, and acquires pressing position data for three reels (left reel 3L, middle reel 3C, and right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressing position data in a non-standard pressing position storage area (not shown) provided in the non-standard working area (S374). If the navigation data is push order navigation by the processing of S367 to S371, the value of the pressed position table selection counter is “0”, and if the navigation data is navigation data for BB1 stop operation, the value of the pressed position table selection counter is set. The value is “1”, and if the navigation data is navigation data for BB2 stop operation, the value of the pressed position table selection counter is “2”. That is, the pressed position data is acquired based on the navigation data.

  Next, the main CPU 101 performs a second interface board output process (S375). The details of the second interface board output process will be described later with reference to FIG. 103 described later.

  Next, the main CPU 101 performs restoration processing for all registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 to the stack pointer (SP) (S377). After the process of S377, the main CPU 101 ends the second interface board control process, and moves the process to S208 of the main flow (see FIG. 82).

[Second interface board output processing]
Next, the second interface board output process performed in S375 in the second interface board control process (see FIG. 102) will be described with reference to FIG. FIG. 103 is a flowchart showing the procedure of the second interface board output process. The second interface board output process is performed in a non-standard work area of the main RAM 103.

  First, the main CPU 101 determines whether or not a transmission operation is being performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). When the main CPU 101 determines in S381 that the transmission operation is being performed via the second interface serial line (when S381 is YES), the main CPU 101 ends the second interface board output process, The process moves to S376 of the second interface board control process (see FIG. 102).

  On the other hand, when the main CPU 101 determines in S381 that the transmission operation is not performed via the second interface serial line (when S381 is NO), the main CPU 101 is provided in an unspecified work area. “3” (the number of reels) is set to the value of the loop counter, and the initial value “1” is set to the serial communication thumb value (S382). Next, the main CPU 101 transmits transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

  Next, the main CPU 101 refers to the non-regulated pressing position storage area of the predetermined reel (rotating cylinder), and acquires the pressing position data of the predetermined reel (S384). Next, the main CPU 101 updates the non-regulated pressing position storage area to be referred to that of the next target reel (rotor) (S385).

  Next, the main CPU 101 acquires pulse number data corresponding to the pressed position data (design position) based on the pulse conversion data (not shown) and the acquired pressed position data (S386). The details of the correspondence between the pressed position data (symbol position) and the pulse number data are omitted. For example, the acquired pressed position data (symbol position) is “3” (the symbol “white 7” in the left reel 3L). ), “38” is acquired as the pulse number data, and when the pressed position data (design position) is “10” (design “replay” in the left reel 3L), “38” is obtained as the pulse number data. 155 "is acquired. Further, for example, when the acquired pressing position data (symbol position) is “12” (symbol “blue 7” in the left reel 3L), “189” is acquired as the pulse number data, and the pressing position data (symbol) If the (position) is “15” (the symbol “replay” in the left reel 3L), “239” is acquired as the pulse number data.

  Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

  Next, the main CPU 101 determines whether or not the value of the loop counter is “0” (S390). In S390, when the main CPU 101 determines that the value of the loop counter is not “0” (when S390 is NO), the main CPU 101 changes the target reel to the next reel and returns the process to S384. The processes after S384 are repeated.

  On the other hand, when the main CPU 101 determines in S390 that the value of the loop counter is “0” (in the case where S390 is YES), the main CPU 101 converts the serial communication sum value to the second interface serial line (second interface). 2 serial communication circuit 115: SCU2) (S391). After the process of S391, the main CPU 101 ends the second interface board output process, and moves the process to S376 of the second interface board control process (see FIG. 102).

[Control processing by status]
Next, referring to FIG. 104, the state-specific control process performed in S208 in the main flow (see FIG. 82) will be described. FIG. 104 is a flowchart showing the procedure of the state-specific control process.

  First, the main CPU 101 performs sub-flag conversion processing (S401). In this process, the main CPU 101 performs a process of converting the internal winning combination into a sub flag (see FIGS. 36 and 37). Details of the subflag conversion process will be described later with reference to FIG.

  Next, the main CPU 101 performs a navigation set process (S402). In this process, the main CPU 101 acquires navigation data based on the RT state, the gaming state, and the small combination winning number. Details of the navigation set process will be described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the current RT state is the RT4 state (S403). In S403, when the main CPU 101 determines that the current RT state is not the RT4 state (when S403 is NO), the main CPU 101 performs a process of S406 described later.

  On the other hand, when the main CPU 101 determines in S403 that the current RT state is the RT4 state (when S403 is YES), the main CPU 101 performs flag conversion processing (S404). In this process, the main CPU 101 performs a flag conversion lottery process (sub-flag data compression process) for converting the sub-flag into the sub-flag EX (see FIG. 36). By this flag conversion process, 19 types (including loss) of sub-flags are converted (compressed) into 9 types (including loss) of sub-flags EX. The details of the flag conversion process will be described later with reference to FIG.

  Next, the main CPU 101 performs sub-flag compression processing (S405). In this process, the main CPU 101 converts the sub flag EX into a sub flag D (see FIG. 36), and further compresses the sub flag data. By this sub-flag compression processing, nine types (including loss) of sub-flags EX are converted (compressed) into seven types (including loss) of sub-flags D.

  After the processing of S405 or when S403 is NO, the main CPU 101 determines whether or not the current gaming state is the normal gaming state (S406).

  In S406, when the main CPU 101 determines that the current gaming state is the normal gaming state (when S406 is YES), the main CPU 101 performs normal start processing (S407). The details of the normal start process will be described later with reference to FIG. Then, after the processing of S407, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S406 that the current gaming state is not the normal gaming state (when S406 is NO), the main CPU 101 determines whether or not the current gaming state is CZ ( S408).

  In S408, when the main CPU 101 determines that the current gaming state is CZ (when S408 is YES), the main CPU 101 performs start processing during CZ (S409). The details of the CZ start process will be described later with reference to FIG. 113 described later. Then, after the processing of S409, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S408 that the current gaming state is not CZ (when S408 is NO), the main CPU 101 determines whether or not the current gaming state is normal ART (S410). ).

  In S410, when the main CPU 101 determines that the current gaming state is the normal ART (when S410 is YES), the main CPU 101 performs a start process during the normal ART (S411). Details of the start processing during normal ART will be described later with reference to FIG. 117 described later. Then, after the processing of S411, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S410 that the current gaming state is not the normal ART (when S410 is NO), the main CPU 101 determines whether or not the current gaming state is CT (S412). ).

  In S412, when the main CPU 101 determines that the current gaming state is CT (when S412 is YES), the main CPU 101 performs start processing during CT (S413). The details of the CT start process will be described later with reference to FIG. 118 described later. Then, after the processing of S413, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S412 that the current gaming state is not CT (when S412 is NO), the main CPU 101 determines whether or not the current gaming state is a bonus state (S414). ).

  In S414, when the main CPU 101 determines that the current gaming state is a bonus state (when S414 is YES), the main CPU 101 performs a start-time process during BB (S415). The details of the start processing during BB will be described later with reference to FIG. 125 described later. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and moves the processing to S209 of the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines that the current gaming state is not the bonus state in S414 (when S414 is NO), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a gaming state other than the gaming state targeted by the various determination processes. For example, when the current gaming state is the ART ready state, processing corresponding to the ART ready state is performed. Then, after the processing of S416, the main CPU 101 ends the state-based control processing, and moves the processing to S209 of the main flow (see FIG. 82).

[Sub flag conversion processing]
Next, with reference to FIGS. 105 to 107, the subflag conversion process performed in S401 in the state-specific control process (see FIG. 104) will be described. FIG. 105 is a flowchart showing the sub-flag changing process. FIG. 106 is a diagram showing an example of a source program for executing the subflag change process. FIG. 107 shows a subflag conversion table (conversion table) actually referred to on the source program of the subflag conversion process. It is a figure which shows an example of a structure.

  First, the main CPU 101 acquires a small combination winning number (0 to 36) (S421). Next, the main CPU 101 determines whether or not a bonus is currently being operated (S422).

  In S422, when the main CPU 101 determines that the bonus operation is currently being performed (in the case where S422 is YES), the main CPU 101 converts the small role winning number into a bonus operating sub-flag and saves it (S423). . The main CPU 101 executes the source code “SUB (subtraction instruction) cNHT_RBST-c7HT1_FLA” in FIG. 106 to convert the small role winning number into a sub flag during bonus operation. In the present embodiment, by executing this “SUB” instruction, the winning combination number is uniformly converted to the subflag “cactus (14)”. Then, after the processing of S423, the main CPU 101 ends the subflag conversion processing, and shifts the processing to S402 of the state-specific control processing (see FIG. 104).

  On the other hand, when it is determined in S422 that the main CPU 101 is not currently operating the bonus (when S422 is NO), the main CPU 101 sets the sub flag conversion table shown in FIG. 107 (S424). In this process, the initial value of the subflag to be determined is set to “losing (00)”, and the subflag “losing (00)” is used as the initial address of the block in the subflag conversion table shown in FIG. Is stored (“dSBCVTB + 1”).

  Next, the main CPU 101 determines whether the data of the small role winning number specified in the block in the subflag conversion table currently being referred to is data corresponding to the small bonus winning number acquired in the current game. It is determined whether or not (S425).

  In S425, the main CPU 101 determines that the data of the small role winning number specified in the block in the subflag conversion table to be referred to is not data corresponding to the small bonus winning number acquired in the current game. When (NO in S425), the main CPU 101 updates the block in the subflag conversion table to be referenced to the block of the next address (S426). Next, the main CPU 101 adds “1” to the value of the subflag (S427). After the process of S427, the main CPU 101 returns the process to the process of S425, and repeats the processes after S425.

  On the other hand, in S425, the data of the small combination winning number specified in the block in the sub flag conversion table that is the reference target of the main CPU 101 is data corresponding to the small combination winning number acquired in the current game. (S425 is YES), the main CPU 101 refers to the sub-flag conversion table shown in FIG. 107, sub-flag conversion control data associated with the small-combination winning number (the address of the small-combination winning number) 1-byte data stored at the next address) is acquired, and the sub-flag conversion control data is stored in a sub-flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). In this processing, for example, when the small winning combination number acquired in the current game is “03” (internal winning combination “F — 3 consecutive chips”), sub flag conversion is performed with reference to the sub flag conversion table shown in FIG. Control data “00000011B” is acquired. After the process of S428, the main CPU 101 ends the subflag conversion process, and moves the process to S402 of the control process for each state (see FIG. 104).

  In the present embodiment, the subflag conversion process is performed as described above. Note that the sub-flag conversion process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In the subflag conversion table shown in FIG. 107 that is actually referred to in the source program of the subflag conversion process, subflag conversion control data (control status) is associated with each subflag. At this time, the same subflag conversion control data (control status) is associated with the same type of subflag.

  For example, the subflag conversion control data (control status) “00000011B” is commonly assigned to the subflags “triple dust A” and “triple dust B”. For example, subflag conversion control data (control status) “00000001B” is commonly allocated to the subflags “reach eye lip 1” to “reach eye lip 4”. In the flag conversion lottery process when converting the internal winning combination (sub flag) to the sub flag EX, lottery is performed based on the sub flag conversion control data (control status) stored in the sub flag conversion control data storage area. .

  By providing common sub-flag conversion control data for the same type of internal winning combination (sub flag) in the sub flag conversion table for converting the flag (internal winning combination) managed on the main side into a flag manageable on the sub side Therefore, the versatility of the conversion table is increased, and the conversion program change accompanying the model change can be dealt with with a slight change, thereby suppressing an increase in development cost.

[Naviset processing]
Next, with reference to FIGS. 108 to 110, the navigation set process performed in S402 in the state-specific control process (see FIG. 104) will be described. FIG. 108 is a flowchart showing the procedure of the navigation set process. FIG. 109 is a diagram showing an example of a source program for executing the processes of S434 to S436 described later during the navigation set process, and FIG. 110 is actually referred to on the source program of the navigation set process. It is a figure which shows an example of a structure of a navigation data table.

  First, the main CPU 101 determines whether or not a navigation set flag is set in a sub-flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub-flag conversion control data storage area, and the set sub-flag conversion control data is data corresponding to the small combination winning numbers (10 to 23) that generate the push order navigation. It is determined whether or not. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub-flag conversion control data storage area (when S431 is NO), the main CPU 101 ends the navigation set process, and the process is classified by state. Control proceeds to S403 of the control process (see FIG. 104).

  On the other hand, when the main CPU 101 determines in S431 that the navigation set flag is set in the sub-flag conversion control data storage area (when S431 is YES), the main CPU 101 is in the RT0 or RT1 state. Whether or not (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (when S432 is NO), the main CPU 101 ends the navigation set process, and the process is controlled according to the state (see FIG. 104). To S403.

  On the other hand, in S432, when the main CPU 101 determines that the RT state is the RT0 or RT1 state (when S432 is YES), the main CPU 101 determines whether or not the gaming state is the general gaming state ( S433). In S433, when the main CPU 101 determines that the gaming state is the general gaming state (when S433 is YES), the main CPU 101 ends the navigation set process, and the process is controlled according to the state (see FIG. 104). To S403.

  On the other hand, when the main CPU 101 determines in S433 that the gaming state is not the general gaming state (when S433 is NO), the main CPU 101 acquires the small role winning number (S434). Next, the main CPU 101 refers to the navigation data table shown in FIG. 110 and acquires navigation data (any one of 1 to 9) based on the small role winning number (S435).

  Next, the main CPU 101 stores the acquired navigation data (information related to the stop operation of the variable display of the plurality of display columns) in a navigation data storage area (stop operation instruction information storage area) (not shown) in the main RAM 103 (S436). After the process of S436, the main CPU 101 ends the navigation set process, and moves the process to S403 of the state-specific control process (see FIG. 104).

  In the present embodiment, the navigation set process is performed as described above. Note that the processing of S434 to S436 during the navigation set processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. In this series of processing, as shown in FIG. 109, a “LDQ” instruction dedicated to the main CPU 101 that uses the Q register (extension register) for addressing is used on the source program.

  For example, when the source code “LDQ A, (k)” is executed on the source program, the data stored in the Q register (upper address value) and a 1-byte integer k (direct value: lower address value) The contents (stored data) of the memory at the address specified by are loaded into the A register. Therefore, for example, when the source code “LDQ A, (wHITFRT)” in FIG. 109 is executed, the data stored in the Q register and the memory contents at the address specified by the integer value “wHITFRT” are stored in the A register. To be loaded.

  For example, when the source code “LDQ (k), A” is executed on the source program, the data stored in the A register is stored in the data stored in the Q register (upper address value) and a 1-byte integer k. It is loaded into the memory at the address specified by (direct value: lower address value). Therefore, for example, by executing the source code “LDQ (wNAVIPTN), A” in FIG. 109, the data (navigation data) stored in the A register is changed to the data stored in the Q register (upper address value) and 1 byte. Is stored in the navigation data storage area of the address designated by the integer value “wNAVIPTN” (lower address value).

  As described above, in this embodiment, the main CPU 101 dedicated instruction code using the Q register (extension register) is used in the navigation set process, and the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, an instruction relating to address setting can be omitted on the source program of the navigation set process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Flag conversion process]
Next, with reference to FIG. 111, the flag conversion process performed in S404 in the state-specific control process (see FIG. 104) will be described. FIG. 111 is a flowchart showing the procedure of flag conversion processing.

  First, the main CPU 101 determines whether or not it is the CT start time (S441).

  In S441, when the main CPU 101 determines that it is not the CT start time (when S441 is NO), the main CPU 101 performs the process of S443 described later. On the other hand, when it is determined in S441 that the main CPU 101 is at the start of CT (when S441 is YES), the main CPU 101 determines the table number of the flag conversion lottery table used for the flag conversion lottery during CT by lottery. And set (S442).

  After the processing of S442 or when S441 is NO, the main CPU 101 sets a flag conversion lottery table corresponding to the current state (S443). For example, when the current state is a non-ART RT4 state, a non-ART flag conversion lottery table (see FIG. 62) is set, and when the current state is a normal ART RT4 state, An ART flag conversion lottery table (see FIGS. 47A and 47B) is set. If the current state is the RT4 state during CT, a CT flag conversion lottery table (see FIG. 54) is set.

  Next, the main CPU 101 refers to the set flag conversion lottery table and performs flag conversion lottery processing based on the internal winning combination (S444). Actually, in this process, the main CPU 101 performs the flag conversion lottery process using the sub flag conversion control data acquired from the sub flag conversion table shown in FIG. 107, based on the sub flag corresponding to the internal winning combination.

  Next, the main CPU 101 determines whether or not the flag conversion lottery of S444 has been won (S445).

  When the main CPU 101 determines in S445 that the flag conversion lottery has been won (when S445 is YES), the main CPU 101 performs sub-flag conversion processing (S446). In this process, for example, when the internal winning combination is “F_1 correct Chile Lip”, that is, when the sub flag is “Triple Chile Lip B (03)”, when the flag conversion lottery process is won, the sub flag conversion process of S446 is performed. Then, the subflag “triple dust B (03)” is converted into the subflag EX “determined combination (06)” or subflag EX “triple dust (07)” (see FIG. 36).

  After the processing of S446, the main CPU 101 determines whether or not the current gaming state is a non-ART state (S447). In S447, when the main CPU 101 determines that the current gaming state is not the non-ART state (when S447 is NO), the main CPU 101 ends the flag conversion process, and the process is controlled according to the state (see FIG. 104). ) To S405.

  On the other hand, when the main CPU 101 determines in S447 that the current gaming state is the non-ART state (when S447 is YES), the main CPU 101 adds “1” to the number of ART sets (S448). Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S449). Then, after the process of S449, the main CPU 101 ends the flag conversion process, and moves the process to S405 of the state-specific control process (see FIG. 104).

  Here, returning to the process of S445 again, when it is determined in S445 that the main CPU 101 has not won the flag conversion lottery (when S445 is NO), the main CPU 101 performs the sub flag maintaining process (S450). . In this process, for example, when the internal winning combination is “F_1 exact Chile Lip”, that is, when the sub flag is “Triple Chile Lip B (03)”, if the flag conversion lottery is non-winning, the sub flag is maintained in S450. Through the processing, the subflag “triple lip B (03)” is converted (maintained) into the subflag EX “replay (01)”. After the process of S450, the main CPU 101 ends the flag conversion process, and moves the process to S405 of the control process for each state (see FIG. 104).

[Normal start processing]
Next, with reference to FIG. 112, the normal start process performed in S407 during the state-specific control process (see FIG. 104) will be described. FIG. 112 is a flowchart showing the procedure of normal start processing.

  First, the main CPU 101 refers to the CZ lottery table (see FIG. 41A) and performs CZ lottery processing based on the current CZ lottery state and internal winning combination (sub flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery of S461 has been won (S462).

  In S462, when the main CPU 101 determines that the CZ lottery has not been won (when S462 is NO), the main CPU 101 performs a process of S465 described later.

  On the other hand, when it is determined in S462 that the main CPU 101 has won the CZ lottery (when S462 is YES), the main CPU 101 sets the type of CZ that has won the game state of the next game (S463). Next, the main CPU 101 sets the number of CZ games of the winning type in the CZ game number counter (S464). The CZ game number counter is a counter that counts the duration of CZ and is provided in the main RAM 103. In the process of S464, for example, when CZ1 is won, the first predetermined game number (for example, “12”) is set in the CZ game number counter (first half), and CZ2 is won. When the second predetermined game number (for example, “15”) is set in the CZ game number counter (first half) and CZ3 is won, the fourth predetermined game number is displayed in the CZ game number counter. (For example, “17”) is set.

  After the processing of S464 or when S462 is NO, the main CPU 101 refers to the normal medium / high probability lottery table (see FIG. 40A), and performs the lottery of the CZ lottery state based on the internal winning combination (sub flag) (S465). ). Next, the main CPU 101 updates the lottery state of the CZ based on the result of the transfer lottery (S466). Then, after the processing of S466, the main CPU 101 ends the normal start processing and also ends the state-specific control processing (see FIG. 104).

[Process during start during CZ]
Next, with reference to FIG. 113, the start process during CZ performed in S409 during the state-specific control process (see FIG. 104) will be described. FIG. 113 is a flowchart showing a procedure of a start time process during CZ.

  First, the main CPU 101 determines whether or not the current gaming state is CZ1 (S471).

  In S471, when the main CPU 101 determines that the current gaming state is CZ1 (when S471 is YES), the main CPU 101 performs processing during CZ1 (CZ2) (S472). The details of the intermediate processing in CZ1 (CZ2) will be described later with reference to FIGS. 114 and 115 described later. Then, after the process of S472, the main CPU 101 ends the start-time process during CZ and also ends the control process by state (see FIG. 104).

  On the other hand, when the main CPU 101 determines in S471 that the current gaming state is not CZ1 (when S471 is NO), the main CPU 101 determines whether or not the current gaming state is CZ2 (S473). .

  In S473, when the main CPU 101 determines that the current gaming state is CZ2 (when S473 is YES), the main CPU 101 performs processing during CZ1 (CZ2) (S474). Details of the intermediate processing in CZ1 (CZ2) will be described later with reference to FIGS. 114 and 115 described later. Then, after the processing of S474, the main CPU 101 ends the start-time processing during CZ and also ends the state-specific control processing (see FIG. 104). In the present embodiment, only the rank (mode or point) indicating the degree of expectation for winning the ART lottery is different between the CZ1 middle processing and the CZ2 middle processing, and the basic processing content is the same. Therefore, in the present embodiment, the CZ1 mid-process and the CZ2 mid-process are described as one process as CZ1 (CZ2) mid-process.

  On the other hand, when the main CPU 101 determines in S473 that the current gaming state is not CZ2 (when S473 is NO), the main CPU 101 performs CZ3 mid-process (S475). Details of the CZ3 intermediate process will be described later with reference to FIG. 116 described later. Then, after the processing of S475, the main CPU 101 ends the start-time processing during CZ and also ends the state-specific control processing (see FIG. 104).

[CZ1 (CZ2) medium processing]
Next, with reference to FIG. 114 and FIG. 115, the process during CZ1 (CZ2) performed in S472 or S474 during the process during start during CZ (see FIG. 113) will be described. FIG. 114 and FIG. 115 are flowcharts showing the procedure of the process during CZ1 (CZ2).

  First, the main CPU 101 determines whether or not the current game is a game in the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not a game in the first half of CZ1 (or CZ2) (when S481 is NO), the main CPU 101 performs the process of S490 described later.

  On the other hand, when the main CPU 101 determines in S481 that the current game is a game in the first half of CZ1 (when S481 is YES), the main CPU 101 refers to the mode-up lottery table during CZ1 (see FIG. 42). Then, a mode-up lottery process is performed based on the internal winning combination (sub flag) (S482). In S481, when the main CPU 101 determines that the current game is a game in the first half of CZ2 (when S481 is YES), the main CPU 101 refers to the point lottery table during CZ2 (see FIG. 43). Then, point-up lottery is performed based on the internal winning combination (sub flag) (S482).

  Next, the main CPU 101 updates the rank (mode or point) based on the lottery result in S482 (S483). Next, the main CPU 101 determines whether or not the freezing is won in the lottery of S482 (S484).

  When it is determined in S484 that the main CPU 101 has won the freeze (when S484 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game, and also includes the number of ART sets and the number of CT sets. "1" is added to (S485). In this process, the main CPU 101 determines and sets the ART level with reference to the ART level determination table (see FIG. 48A). When freeze occurs, “ART level 2” is determined as the ART level.

  Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S486). Then, after the processing of S486, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing during start during CZ (see FIG. 113).

  Here, returning to the processing of S484 again, when it is determined in S484 that the main CPU 101 has not won the freeze (when S484 is NO), the main CPU 101 determines the value of the CZ game number counter (first half). 1 is subtracted (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half) is “0” (S488).

  In S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is not “0” (when S488 is NO), the main CPU 101 ends the processing in CZ1 (CZ2). The start process during CZ (see FIG. 113) is also terminated.

  On the other hand, in S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is “0” (when S488 is YES), the main CPU 101 determines that the game state of the next game is CZ1 or The latter half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing during start during CZ (see FIG. 113).

  Here, returning to the processing of S481 again, if S481 is NO, the main CPU 101 determines whether or not the current game is the first game in the second half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game in the second half of CZ1 or CZ2 (when S490 is NO), the main CPU 101 performs the process of S495 described later.

  On the other hand, when the main CPU 101 determines in S490 that the current game is the first game in the second half of CZ1 or CZ2 (when S490 is YES), the main CPU 101 determines that the ART lottery table in CZ (FIG. 44A and FIG. 44B), an ART lottery process is performed based on the rank (mode or point) of the first half (S491).

  Next, the main CPU 101 determines whether or not the ART lottery has been won (S492). In S492, when the main CPU 101 determines that the ART lottery has not been won (when S492 is NO), the main CPU 101 performs a process of S494 described later.

  On the other hand, when the main CPU 101 determines that the ART lottery has been won in S492 (when S492 is YES), the main CPU 101 adds “1” to the number of ART sets, and the ART level determination table (see FIG. 48A). ) To perform ART level lottery and set the lottery result (S493).

  After the processing of S493 or when S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half) (S494). In the process of S494, for example, when the ART lottery is won, “4” is set in the CZ game number counter (second half), and when the ART lottery is not won, the number of CZ games is set. “3” is set in the counter (second half).

  After the process of S494 or when S490 is NO, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 44C) and performs the ART lottery process based on the internal winning combination (sub flag) (S495).

  Next, the main CPU 101 determines whether or not the ART lottery has been won (S496). When the main CPU 101 determines in S496 that the ART lottery has not been won (when S496 is NO), the main CPU 101 performs a process of S498 described later.

  On the other hand, when it is determined in S496 that the main CPU 101 has won the ART lottery (when S496 is YES), the main CPU 101 adds “1” to the number of ART sets and determines the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S497).

  After the processing of S497 or when S496 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (second half) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is “0” (S499).

  In S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is not “0” (when S499 is NO), the main CPU 101 ends the CZ1 (CZ2) process, The start process during CZ (see FIG. 113) is also terminated.

  On the other hand, when the main CPU 101 determines in S499 that the value of the CZ game number counter (second half) is “0” (when S499 is YES), the main CPU 101 determines that the number of ART sets is “1” or more. It is determined whether or not (S500).

  In S500, when the main CPU 101 determines that the number of ART sets is “1” or more (when S500 is YES), the main CPU 101 sets the ART ready state to the game state of the next game (S501). Then, after the processing of S501, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at start during CZ (see FIG. 113).

  On the other hand, when the main CPU 101 determines in S500 that the number of ART sets is not “1” or more (when S500 is NO), the main CPU 101 sets the CZ failure state to the gaming state of the next game ( S502). Then, after the processing of S502, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing during start during CZ (see FIG. 113).

[CZ3 medium processing]
Next, with reference to FIG. 116, the process during CZ3 performed in S475 during the process during start during CZ (see FIG. 113) will be described. FIG. 116 is a flowchart showing the procedure of the CZ3 middle process.

  First, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 45) and performs ART lottery processing based on the internal winning combination (sub flag) (S511).

  Next, the main CPU 101 determines whether or not the ART lottery has been won (S512). When the main CPU 101 determines in S512 that the ART lottery has not been won (when S512 is NO), the main CPU 101 performs a process of S518 described later.

  On the other hand, when it is determined in S512 that the main CPU 101 has won the ART lottery (when S512 is YES), the main CPU 101 adds “1” to the number of ART sets and “1” to the number of CT sets. Addition is performed (S513). Next, the main CPU 101 determines whether or not the freezing is won in the ART lottery of S512 (S514).

  In S514, when the main CPU 101 determines that it has not won the freeze (when S514 is NO), the main CPU 101 performs a process of S516 described later. On the other hand, when it is determined in S514 that the main CPU 101 has won the freeze (when S514 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game (S515).

  After the processing of S515 or when S514 is NO, the main CPU 101 performs ART level lottery processing with reference to the ART level determination table (see FIG. 48A) and sets the lottery result (ART level) (S516). . Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S517). Then, after the processing of S517, the main CPU 101 ends the processing during CZ3 and also ends the processing during start during CZ (see FIG. 113).

  Here, returning to the processing of S512 again, if S512 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether or not the value of the CZ game number counter is “0” (S519).

  In S519, when the main CPU 101 determines that the value of the CZ game number counter is not “0” (in the case of NO determination in S519), the main CPU 101 ends the processing during CZ3 and starts the processing during CZ (FIG. 113) also ends.

  On the other hand, when the main CPU 101 determines in S519 that the value of the CZ game number counter is “0” (when S519 is YES), the main CPU 101 adds “1” to the number of ART sets, and ART The ART level lottery is performed with reference to the level determination table (see FIG. 48A) and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state to the game state of the next game (S521). Then, after the processing of S521, the main CPU 101 ends the processing during CZ3 and also ends the processing during start during CZ (see FIG. 113).

[Normal start processing during ART]
Next, with reference to FIG. 117, the normal ART start process performed in S411 in the state-specific control process (see FIG. 104) will be described. FIG. 117 is a flowchart showing a procedure of a start-time process during normal ART.

  First, the main CPU 101 adds “1” to the value of the ART continuing game number counter (S531). The ART continued game number counter is a counter that counts the number of games (the number of digested games) that the normal ART has continued. In the present embodiment, in addition to the ART continuing game number counter, an ART end game number counter that counts the number of games that the normal ART can continue is provided. Then, in the pachi-slot 1 of this embodiment, the value of the ART continuing game number counter is compared with the value of the ART ending game number counter, and when the value of the ART continuing game number counter reaches the value of the ART ending game number counter, The gaming state ends.

  Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 50), and performs CT lottery processing based on the current CT lottery state and the internal winning combination (sub flag) (S532). Next, the main CPU 101 determines whether or not a CT lottery has been won (S533). In S533, when the main CPU 101 determines that the CT lottery has not been won (when S533 is NO), the main CPU 101 performs the process of S536 described later.

  On the other hand, when it is determined in S533 that the main CPU 101 has won the CT lottery (when S533 is YES), the main CPU 101 adds “1” to the number of CT sets and sets the value of the CT game number counter to “ 8 ”is set (S534). Next, the main CPU 101 sets the type of CT that won the gaming state of the next game (S535).

  After the processing of S535 or when S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48B), lotteries the ART level based on the value of the ART continuing game number counter, and sets the lottery result. (S536). Next, the main CPU 101 refers to the normal ART medium / high probability lottery table (see FIG. 49), lottery the destination CT lottery state based on the current CT lottery state and the internal winning combination (subflag), and the lottery result. Is set (S537).

  Next, the main CPU 101 refers to the extra lottery table during normal ART (see FIG. 51), and performs an extra lottery process for the number of ART games based on the internal winning combination (sub flag) (S538). Next, the main CPU 101 determines whether or not the extra lottery is won (S539).

  When the main CPU 101 determines in S539 that the winning lottery has not been won (when S539 is NO), the main CPU 101 performs the process of S541 described later. On the other hand, when the main CPU 101 determines in S539 that the winning lottery has been won (when S539 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S540).

  After the processing of S540 or when S539 is NO, the main CPU 101 determines whether or not the value of the ART continuing game number counter has reached the value of the ART end game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continued game number counter has not reached the value of the ART end game number counter (when S541 is NO), the main CPU 101 performs normal start processing during ART. And the state-specific control process (see FIG. 104) are also terminated.

  On the other hand, when the main CPU 101 determines in S541 that the value of the ART continued game number counter has reached the value of the ART end game number counter (when S541 is YES), the main CPU 101 sets the ART set number to 1. Subtraction is performed (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 ends the start processing during normal ART, and also ends the state-specific control processing (see FIG. 104).

[Processing at start during CT]
Next, with reference to FIG. 118, the start process during CT performed in S413 during the state-specific control process (see FIG. 104) will be described. FIG. 118 is a flowchart showing a procedure of a start time process during CT.

  First, the main CPU 101 refers to the extra lottery table during CT (see FIG. 55), and performs extra lottery for the number of ART games based on the internal winning combination (subflag) (S551). Next, the main CPU 101 determines whether or not the extra lottery is won (S552).

  When the main CPU 101 determines in S552 that the winning lottery has not been won (when S552 is NO), the main CPU 101 performs the process of S556 described later. On the other hand, when the main CPU 101 determines in S552 that the winning lottery has been won (when S552 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S553). As described above, in the pachislot machine 1 of this embodiment, as the number of wins for the sub-flag “triple chilli lip (triple chilli lip A or triple chilli lip B)” increases during the same CT, The amount of addition increases.

  After the processing of S553, the main CPU 101 determines whether or not the internal winning combination is a combination corresponding to the sub flag EX “triple combination” (or “determined combination”), that is, the internal winning combination “F_acceptance combination” or “F_1”. It is determined whether or not it is “probable dust” and the flag conversion lottery process of S444 in FIG. 111 has been won (S554).

  When the main CPU 101 determines in S554 that the internal winning combination is not a combination corresponding to the sub flag EX “triple chip” (when S554 is NO), the main CPU 101 ends the start processing during CT, The state-specific control process (see FIG. 104) is also terminated.

  On the other hand, when the main CPU 101 determines in S554 that the internal winning combination is a combination corresponding to the sub flag EX “triple chip” (when S554 is YES), the main CPU 101 sets the value of the CT game number counter to “1” is added (S555). Then, after the process of S555, the main CPU 101 ends the start-time process during CT and also ends the control process for each state (see FIG. 104).

  Here, returning to the processing of S552 again, when S552 is NO, the main CPU 101 performs CT lottery processing during CT (S556). In this process, the main CPU 101 mainly performs lottery by adding the number of CT sets. Details of the CT lottery process during CT will be described later with reference to FIG. 119 described later.

  Next, the main CPU 101 subtracts 1 from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether or not the value of the CT game number counter is “0” (S558).

  In S558, when the main CPU 101 determines that the value of the CT game number counter is not “0” (when S558 is NO), the main CPU 101 ends the start-up process during CT and also controls each state ( The process also ends (see FIG. 104). On the other hand, when the main CPU 101 determines in S558 that the value of the CT game number counter is “0” (when S558 is YES), the main CPU 101 determines whether or not the number of CT sets is “1” or more. Is discriminated (S559).

  In S559, when the main CPU 101 determines that the number of CT sets is “1” or more (when S559 is YES), the main CPU 101 subtracts 1 from the number of CT sets (S560). Next, the main CPU 101 sets “8” to the value of the CT game number counter (S561). Then, after the processing of S561, the main CPU 101 ends the start-time processing during CT and also ends the state-specific control processing (see FIG. 104).

  On the other hand, when the main CPU 101 determines in S559 that the number of CT sets is not “1” or more (when S559 is NO), the main CPU 101 sets the normal ART in the gaming state of the next game (S562). After the process of S562, the main CPU 101 ends the start-time process during CT and also ends the control process for each state (see FIG. 104).

[CT lottery processing during CT]
Next, with reference to FIG. 119, the CT lottery process during CT performed in S556 during the start time process during CT (see FIG. 118) will be described. FIG. 119 is a flowchart showing the procedure of CT lottery processing during CT.

  First, the main CPU 101 sets a CT lottery table during CT (S571). Here, the CT lottery table set during CT is the lottery table added with the number of sets during CT explained with reference to FIG. 56, but the CT lottery table during CT (set during CT) actually set on the source program. The configuration of the number addition lottery table will be described later with reference to FIG. 122 described later.

  Next, the main CPU 101 performs table data acquisition processing (S572). In this process, the main CPU 101 acquires the address of the lottery table to be referred to in the CT lottery process during CT. Details of the table data acquisition process will be described later with reference to FIG. 120 described later.

  Next, the main CPU 101 performs a 1-byte lottery process (S573). In this process, the main CPU 101 performs lottery addition on the CT set. Details of the 1-byte lottery process will be described later with reference to FIG. 123 described later.

  Next, the main CPU 101 determines whether or not a 1-byte lottery process has been won (S574). When the main CPU 101 determines in S574 that the 1-byte lottery process has not been won (when S574 is NO), the main CPU 101 ends the CT lottery process during CT, and the process is started during CT (see FIG. 118).

  On the other hand, when it is determined in S574 that the main CPU 101 has won the 1-byte lottery process (when S574 is YES), the main CPU 101 adds “1” to the number of CT sets (S575). After the process of S575, the main CPU 101 ends the CT lottery process during CT, and moves the process to S557 of the start time process during CT (see FIG. 118).

[Table data acquisition processing]
Next, with reference to FIGS. 120 to 122, the table data acquisition process performed in S572 during the CT lottery process during CT (see FIG. 119) will be described. FIG. 120 is a flowchart illustrating the procedure of the table data acquisition process. FIG. 121 is a diagram showing an example of a source program for executing table data acquisition processing, and FIG. 122 is actually referred to on the source program for CT lottery processing during CT and table data acquisition processing. FIG. 57 is a diagram illustrating an example of a configuration of a CT lottery table during CT (corresponding to the lottery table added with the number of sets during CT described in FIG. 56); The specific various lottery values stored in the CT lottery table during CT shown in FIG. 122 are examples.

  In this embodiment, when acquiring lottery values to be referred to in CT CT lottery processing during CT, lottery values are stored through two-stage address calculation processing (first and second stage table data acquisition processing). The current address is calculated. First, in the first-stage table data acquisition process (the processes of S582 and S583 described later), the “selection value (1 byte)” associated with the internal winning combination (actually the subflag D) is acquired. In addition, the selection value is provided for each type of internal winning combination, it is possible to determine whether the internal winning combination is a lottery target, and can specify the location of the lottery table associated with the internal winning combination Value (relative value) is specified. In the present embodiment, a selection value “0” is defined in advance for internal winning combinations (actually, subflag D) in which the lottery result of CT lottery processing during CT is non-winning, and those internal winning combinations are set to 1. Treated as “lost” at the stage of the table data acquisition process. In the second-stage table data acquisition process (the processes of S585 to S587 described later), the address storing the lottery value of the internal winning combination in which the selection value other than “0” is defined is calculated (the lottery table). The address obtained by adding the relative value (selection value) from the reference address (2 bytes) of the above is calculated.

  First, the main CPU 101 refers to a CT lottery selection table during CT (not shown), calculates the addresses of the CT lottery table during CT, the addresses of the first stage and second stage addition selection data, and CT The number of lotteries for lottery (in this embodiment, twice) is acquired (S581). Next, the main CPU 101 adds the address of the first stage addition selection data to the address of the CT lottery table during CT to calculate the first stage selection address (S582).

  Next, the main CPU 101 acquires the selection value stored in the calculated first stage selection address (S583). Next, the main CPU 101 determines whether or not the selection value is “0” (S584).

  In S584, when the main CPU 101 determines that the selection value is “0” (when S584 is YES), the main CPU 101 ends the table data acquisition process, and the CT lottery process during CT (FIG. 119). (See step S573).

  On the other hand, when the main CPU 101 determines that the selection value is not “0” in S584 (when S584 is NO), the main CPU 101 adds the selection value to the selection address and sets the second-stage selection address. Calculate (S585). Next, the main CPU 101 adds the address of the second stage addition selection data to the second stage selection address to calculate the selection address (S586).

  Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates an address to be referred to in the CT lottery table during CT (S587). . After the process of S587, the main CPU 101 ends the table data acquisition process, and moves the process to S573 of the CT lottery process during CT (see FIG. 119).

  In the present embodiment, the table data acquisition process is performed as described above. The table data acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  Among them, in the first stage table data acquisition processing (processing of S581 to S584), the data is stored in the area from the address “dCTCTSTTB” to “dCTCTS_RER-1” in the CT winning CT lottery table shown in FIG. A table (a table selection relative table by winning combination) is referred to. In addition, in each winning combination table selection relative table (lottery table selection table), each winning combination (sub-flag D “losing”, “cactus”, “weak cherry”, “strong cherry”, “determining winning combination”) “0” is stored as the above-described selection value (relative value) at the address of the selection table of “3”. In the first-stage table data acquisition process (address calculation process), if the selected value is “0”, the lottery result is set to “losing” (see the determination process in S584 above).

  In the CT CT winning lottery table with the above configuration, in the winning combination table selection relative table referred to in the first-stage table data acquisition process, “losing” can be set only by the type of the combination. It is no longer necessary to specify the lottery value for the “losing” role Therefore, in the present embodiment, it is not necessary to store lottery value data (“0”) for “losing” in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

  Further, in the process of S587 during the table data acquisition process (the process of S585 to S587) at the second stage (when sub flag D “reach eye lip” is acquired), the CT shown in FIG. 122 is based on the calculated lottery table address. From the medium CT winning lottery table (corresponding to the lottery table added with the number of sets in CT of FIG. 56), the lottery table used in the normal CT state (first address “dNMTCTCS_RER”) or the high probability CT state lottery table (first address “dSPCTCTS_RER” ) Is selected.

  In the lottery table used in the high-probability CT state, as shown in FIG. 122, “determination bit” (determination data) consisting of 1-byte data is stored in the address area next to the head address “dSPCTCTS_RER”. The determination bit stores data indicating an address range in which the lottery value to be lottery is stored. As in the example shown in FIG. 122, when the lottery value of the lottery target (highly accurate CT) is stored only at the address next to the storage area of the “determination bit” in the lottery table in the high probability CT state, the determination is made. In the bit storage area, 1-byte data “00000001B” in which “1” is stored only in bit 0 is stored as a determination bit. On the other hand, when the lottery value of the lottery object (highly accurate CT and normal CT) is stored at the next address and the next address of the determination bit storage area as in the lottery table used in the normal CT state, FIG. In the determination bit storage area, 1-byte data “00000011B” in which “1” is stored only in bits 0 and 1 is stored as a determination bit. When such a determination bit is provided, it is not necessary to store lottery value data that is not subject to lottery in an area of an address where the bit data is “0” in the determination bit in the lottery table.

  Furthermore, in the lottery table used in the high probability CT state, as shown in FIG. 122, the lottery value for the high probability CT is stored at the address “dSPCTCTS_RER + 2” next to the “judgment bit”, and the lottery value for the high probability CT winning is obtained. Data defined in the address “cABS_HIT” is stored. In the present embodiment, the data defined in the address “cABS_HIT” is data indicating the winning determination (100% winning) (hereinafter referred to as “determining data”). In the present embodiment, since it is not necessary to provide lottery value data (“0”) for losing in the CT winning lottery table during CT, as shown in FIG. 122, the fixed data defined in the address “cABS_HIT” “0” can be defined in That is, in the CT CT winning lottery table having the above configuration, the lottery value “0” can be used as the confirmed data.

  Note that, as explained in the CT set number addition lottery table in FIG. 56, in this embodiment, “high probability CT winning” is always determined in the CT set number addition lottery in the high probability CT state. Therefore, in the present embodiment, on the source program, in the CT winning CT lottery table shown in FIG. 122, the determined data can be stored as the lottery value for the high probability CT winning.

  As in the lottery table at the second stage (when the sub flag D “reach eye lip” is acquired), depending on the value of each bit data constituting the determination bit, the lottery target part and the non-lottery part of the CT lottery (sub flag D ) Is eliminated, it is not necessary to store lottery value data (losing data) of a combination not subject to lottery in the table. In addition, a lottery value “0” can be used as the confirmed data in which the winning probability of the lottery target combination is 100%. For these reasons, in the present embodiment, the capacity of the CT winning lottery table during CT (the lottery table added with the number of sets during CT) can be compressed, and free space can be secured (increased) in the main ROM 102. It is possible to improve the gameability by utilizing the increased free space. Further, in this embodiment, an example in which this technique is used in the CT winning process during CT has been described. However, the present invention is not limited to this, and an ART lottery (see FIG. 115) and an ART game number extra lottery (see FIG. 117). ), A later-described CT lottery (see FIG. 154 described later), a later-described CZ pull-back lottery (see later-described FIG. 157), and the like.

[1-byte lottery processing]
Next, the 1-byte lottery process performed in S573 during the CT lottery process during CT (see FIG. 119) will be described with reference to FIGS. FIG. 123 is a flowchart showing the procedure of the 1-byte lottery process. FIG. 124 is a diagram showing an example of a source program for executing the 1-byte lottery process.

  First, the main CPU 101 stores a 1-byte random number value (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110) for CT lottery in CT stored in a random number storage area (not shown) in the main RAM 103. Set (S591). Next, the main CPU 101 obtains the lottery determination data (the determination bit in the lottery table defined in the second stage in FIG. 122) from the CT lottery table during CT based on the address calculated in S587 during the table data acquisition process. Obtain (S592). Further, in this process, the main CPU 101 sets the number of determination bits “8” as the initial value of the number of lotteries.

  Next, the main CPU 101 determines whether the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to bit data in a determination bit associated with the current number of lotteries, and determines that the bit data is “1” if the bit data is “1”. In this embodiment, bits 0 to 7 in the determination bits are associated with the number of lotteries “8” to “1”, respectively.

  In S593, when the main CPU 101 determines that the lottery determination data is not a lottery target (when S593 is NO), the main CPU 101 performs a process of S599 described later. On the other hand, in S593, when the main CPU 101 determines that the lottery determination data is a lottery target (when S593 is YES), the main CPU 101 acquires a lottery value from the CT CT lottery table during CT (S594).

  Next, the main CPU 101 determines whether or not the lottery value is “0” (winning determination data) (S595).

  In S595, when the main CPU 101 determines that the lottery value is “0” (in the case where S595 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is the CT CT lottery process during CT (FIG. 119). (See step S574). On the other hand, when the main CPU 101 determines that the lottery value is not “0” in S595 (when S595 is NO), the main CPU 101 performs a CT lottery (an addition lottery for the number of CT sets) (S596). Specifically, the main CPU 101 subtracts the lottery value from the random value (1-byte random value) and sets the subtraction result as the random value.

  Next, the main CPU 101 determines whether or not the CT lottery of S596 has been won (S597). In the CT lottery in S596, the main CPU 101 determines that the winning is made when the subtraction result in S596 is equal to or less than “0” (so-called “digit” occurs).

  When the main CPU 101 determines in S597 that the CT lottery has been won (when S597 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is a CT lottery process during CT (see FIG. 119). Move to S574. On the other hand, when the main CPU 101 determines in S597 that the CT lottery has not been won (when S597 is NO), the main CPU 101 stores the lottery value storage address (lottery address) referred to in the CT lottery table during CT. Is updated to the next lottery address (S598).

  After the processing of S598 or when S593 is NO, the main CPU 101 subtracts 1 from the number of lotteries (S599). Next, the main CPU 101 determines whether or not the number of lotteries is “0” (S600).

  In S600, when the main CPU 101 determines that the number of lotteries is not “0” (when S600 is NO), the main CPU 101 returns the process to S593 and repeats the processes after S593. On the other hand, when the main CPU 101 determines in S600 that the number of lotteries is “0” (when S600 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is a CT lottery process during CT ( The process proceeds to S574 in FIG.

  In the present embodiment, the 1-byte lottery process is performed as described above. The 1-byte lottery process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  In the random number acquisition process of S591 during the 1-byte lottery process, as shown in FIG. 124, an “LDQ” instruction, which is an instruction code dedicated to the main CPU 101 for performing address designation using the Q register (extension register), is generated on the source program. Used. Therefore, in this embodiment, even in the 1-byte lottery process, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values by using an instruction code using the Q register (extension register). Therefore, the instruction code relating to the address setting can be omitted, and the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Process during start during BB]
Next, with reference to FIG. 125, the BB start-time process performed in S415 during the state-specific control process (see FIG. 104) will be described. FIG. 125 is a flowchart showing the procedure of the start-time processing during BB.

  First, the main CPU 101 refers to the bonus ART game number addition lottery table (see FIG. 59), and performs an ART game number addition lottery process based on the internal winning combination (S611). Next, the main CPU 101 determines whether or not the extra lottery is won (S612).

  When the main CPU 101 determines in S612 that the winning lottery has not been won (when S612 is NO), the main CPU 101 ends the BB start-time processing and also performs control processing by state (see FIG. 104). finish. On the other hand, when it is determined in S612 that the main CPU 101 has won the extra lottery (when S612 is YES), the main CPU 101 adds the winning result (the number of added games) to the ART end game number counter (S613). .

  Next, the main CPU 101 determines whether or not the number of ART sets is “0” (S614). In S614, when the main CPU 101 determines that the number of ART sets is not “0” (in the case where S614 is NO), the main CPU 101 ends the BB start-time processing and also controls by state (see FIG. 104). ) Also ends.

  On the other hand, when the main CPU 101 determines in S614 that the number of ART sets is “0” (when S614 is YES), the main CPU 101 adds “1” to the number of ART sets (S615). Then, after the processing of S615, the main CPU 101 ends the start-time processing during BB and also ends the state-specific control processing (see FIG. 104).

[Retrieve priority storage processing]
Next, with reference to FIG. 126 and FIG. 127, the drawing priority order storing process performed in S212 in the main flow (see FIG. 82) will be described. FIG. 126 is a flowchart illustrating a procedure of the pull-in priority storage process. FIG. 127 is a diagram showing an example of a source program for executing the later-described processing of S625 and S626 during the pull-in priority storage process.

  First, the main CPU 101 sets “3” as the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, the pull-in priority table (see FIG. 27) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the search target reel is selected. Next, the main CPU 101 sets “20” as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs symbol code acquisition processing (S625). In this process, a symbol code is acquired with reference to a winning action flag storage region and a symbol code storage region corresponding to the number of symbol checks. Details of the symbol code acquisition process will be described later with reference to FIG. 128 described later.

  Next, the main CPU 101 performs a logical product operation process (S626). In this processing, the main CPU 101 performs winning operation flag data generation processing. Details of the AND operation processing will be described later with reference to FIG. 133 described later.

  Next, the main CPU 101 performs a drawing priority order acquisition process (S627). In this processing, the main CPU 101 sets the bit to “1” in the winning action flag (winning combination) storage area (see FIGS. 28 to 30), and sets the bit to “1” in the winning request flag storage area. Referring to the drawing priority order table (see FIG. 27), the drawing priority order data is acquired for the combination indicated by “”. The details of the acquisition priority order acquisition process will be described later with reference to FIGS. 134 and 135 described later.

  Next, the main CPU 101 stores the acquired pull-in priority data in a pull-in priority data storage area (not shown) in the main RAM 103 (S628). At this time, the pull-in priority data is stored in the pull-in priority data storage area so that each priority value corresponds to a bit in the storage area.

  The pull-in priority data storage area is provided with a priority data storage area for each main reel type. Each drawing priority data storage area stores drawing priority data determined according to the symbol positions “0” to “19” of the corresponding main reel. In the present embodiment, by referring to this pull-in priority data storage area, it is searched whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols determined based on the stop table.

  The contents of the priority pull-in data stored in the pull-in priority data storage area differ depending on the type of the pull-in priority table number in the pull-in priority table referenced when determining the pull-in priority data. The pull-in priority data indicates that the higher the value, the higher the priority. By referring to the drawing priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol for which the largest value is determined as the pull-in priority data becomes the symbol with the highest priority. Therefore, it can be said that the pull-in priority data indicates the rank between the symbols arranged on the peripheral surface of the main reel. When there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

  Next, the main CPU 101 performs an update process of the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is “0” (S631).

  In S631, when the main CPU 101 determines that the number of symbol checks is not “0” (when S631 is NO), the main CPU 101 returns the process to the process of S625, and repeats the processes after S625. On the other hand, when the main CPU 101 determines in S631 that the number of symbol checks is “0” (when S631 is YES), the main CPU 101 performs a search target reel changing process (S632).

  Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the above-described series of processing has been performed on all main reels (S634).

  In S634, when the main CPU 101 determines that the number of search reels is not “0” (when S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (in the case where S634 is YES), the main CPU 101 terminates the pull-in priority storage process, and the process proceeds to the main flow (FIG. 82).

  In the present embodiment, the pull-in priority storage process is performed as described above. The processing of S625 and S626 during the above-described pull-in priority storage processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  Among them, the logical product operation processing of S626 is performed by the main CPU 101 executing the source code “CALLF SB_DAND_00” in FIG. The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_DAND_00” in FIG. 127 is executed, the process is performed at the address specified by “SB_DAND_00”. The jump is performed, and the logical product operation process is started.

[Design code acquisition processing]
Next, with reference to FIG. 128 to FIG. 132, the symbol code acquisition process performed in S625 in the pull-in priority storage process (see FIG. 126) will be described. 128 is a flowchart showing the procedure of the symbol code acquisition process, and FIG. 129 is a diagram showing an example of a source program for executing the symbol code acquisition process. FIG. 130A is a diagram showing an example of the configuration of a first reel (left reel) symbol arrangement table that is actually referred to in the symbol code acquisition process source program, and FIG. 130B is a first reel symbol arrangement table set. It is a figure which shows an example of a structure of the symbol corresponding winning action table referred sometimes. FIG. 131A is a diagram showing an example of the configuration of a second reel (medium reel) symbol arrangement table that is actually referred to in the symbol code acquisition process source program, and FIG. 131B shows a second reel symbol arrangement table set. It is a figure which shows an example of a structure of the symbol corresponding winning action table referred sometimes. 132A is a diagram showing an example of the configuration of a third reel (right reel) symbol arrangement table that is actually referred to in the symbol code acquisition process source program, and FIG. 132B is a third reel symbol arrangement. It is a figure which shows an example of a structure of the symbol corresponding winning action table referred at the time of table setting.

  First, the main CPU 101 performs clear processing of the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all the storage areas in the winning action flag storage area (see FIGS. 28 to 30). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 130A) (S642).

  Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

  In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, when the main CPU 101 determines in S643 that it is not when the first reel (left reel 3L) is stopped (when S643 is NO), the main CPU 101 uses the second reel symbol arrangement table (see FIG. 131A). Set (S644). In this process, the first reel symbol arrangement table set in S642 is overwritten with the second reel symbol arrangement table.

  Next, the main CPU 101 determines whether or not the second reel (medium reel 3C) is stopped (S645).

  In S645, when the main CPU 101 determines that the second reel (medium reel 3C) is stopped (when S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, when the main CPU 101 determines in S645 that it is not when the second reel (medium reel 3C) is stopped (when S645 is NO), the main CPU 101 displays the third reel symbol arrangement table (see FIG. 132A). Set (S646). In this process, the second reel symbol arrangement table set in S644 is overwritten with the third reel symbol arrangement table.

  After the process of S646, or when S643 or S645 is YES, the main CPU 101 performs a symbol check process when the stop operation is performed on the reel to be stopped and corresponds to the symbol corresponding to the symbol acquired by the symbol check process. A winning action table is acquired (S647). For example, when the first reel (left reel 3L) is stopped and the symbol located on the active line is “white 7” during the stop operation, the main CPU 101 determines that the address “dR1_SVN1” to the address “dR1_SVN2” in FIG. The head address of the symbol corresponding winning action table defined in the block in the range of “−1” is acquired.

  Next, the main CPU 101 sets a winning operation flag storage area (S648). Next, the main CPU 81 performs the compressed data storage process described with reference to FIG. 101 (S649). In this process, the main CPU 101 mainly performs a process of transferring (developing) winning winning action flag data stored in the symbol corresponding winning action table to a corresponding storage area in the winning action flag storage area.

  For example, when the first reel (left reel 3L) is stopped and the symbol positioned on the active line at the time of the stop operation is “white 7”, the symbol combinations (combinations) that can be won are shown in FIGS. 30, combination names “C_2nd_A_01”, “C_2nd_A_01” and “C_SP1_01” defined in the second storage area, combination names “C_9 sheets C_01” to “C_9 sheets C_03” defined in the third storage area, “C_9 sheets C_07” to “C_9 sheets C_09” and “C_9 sheets E_01”, combination names “C_RB role A_01”, “C_RB role A_02”, “C_RB role B_01” to “C_RB role B_04” defined in the fourth storage area ”,“ C_RB combination C_01 ”and“ C_RB combination C_02 ”, and the sixth storage area Combination names “C_reach eye lip C_01” to “C_reach eye lip C_03”, “C_reach eye lip D_01”, “C_reach eye lip D_02” and “C_reach eye lip E_01”, and the tenth storage area Is a combination name “C_BB1”.

  In this case, the storage destination of the first block (0th to 7th storage areas) of the winable winning action flag data stored in the symbol corresponding winning action table is stored at the address “dR1_SVN1 + 1” in the table shown in FIG. 130B. Is designated by the designated data “01011100B” (see the column “Comment storage area +2, +3, +4, +6” in FIG. 130B). Further, the storage destination of the second block (eighth to eleventh storage areas) of the winning action flag data stored in the symbol corresponding winning action table is stored at the address “dR1_SVN1 + 6” in the table shown in FIG. 130B. 1 byte of designated data “10000000B” (refer to the comment “storage area + 10” column in FIG. 130B).

  In this embodiment, bits 0 to 7 of the designated data of the first block are bits that designate the 0th to 7th storage areas of the first block as storage destinations, respectively, and the designated data of the second block Bit 0 to Bit 3 are bits that specify the eighth to eleventh storage areas of the second block as storage destinations, respectively. In the 1-byte designation data of each block, “1” is stored in the bit corresponding to the storage area in the winning action flag storage area which is the storage destination of the winning action flag data.

  Therefore, for example, when the first reel (left reel 3L) is stopped and the symbol located on the active line is “white 7” at the time of the stop operation, the address in the table shown in FIG. The winning action flag data “00010000B” or “00000100B” stored in “dR1_SVN1 + 2” is transferred from the symbol corresponding winning action table to the second storage area in the winning action flag storage area and stored in the address “dR1_SVN1 + 3”. The winning action flag data “00100000B” or “00000100B” is transferred from the symbol corresponding winning action table to the third storage area in the winning action flag storage area. In this case, in the process of S649, the winning operation flag data “10000000B”, “01000000B” or “00100000B” stored at the address “dR1_SVN1 + 4” in the table shown in FIG. 130B is received from the symbol corresponding winning operation table. The winning action flag data “00100000B”, “00010000B” or “00001000B” transferred to the fourth storage area in the action flag storage area and stored at the address “dR1_SVN1 + 5” is stored from the symbol corresponding winning action table. It is transferred to the sixth storage area in the area. Further, in this case, in the process of S649, the winning action flag data “10000000B” stored at the address “dR1_SVN1 + 8” in the table shown in FIG. 130B is changed from the symbol corresponding winning action table to the tenth in the winning action flag storage area. Transferred to storage area.

  After the process of S649, the main CPU 101 sets the winning action flag storage area updated by the compressed data storing process, sets the symbol code storage area, and the data length of the winning action flag storage area (12 bytes in this embodiment). Is set (S650). After the process of S650, the main CPU 101 ends the symbol code acquisition process, and moves the process to S626 of the pull-in priority storage process (see FIG. 126).

  In the present embodiment, the symbol code acquisition process is performed as described above. The above-described symbol code acquisition process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among them, the compressed data storage process of S649 is performed by the main CPU 101 executing the source code “CALLF SB_BTEP_00” in FIG.

  The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_BTEP_00” in FIG. 129 is executed, the process is performed at the address specified by “SB_BTEP_00”. The jump is made to start the compressed data storage process. In this compressed data storing process, as described above, the winning action flag data (compressed data) stored in the symbol corresponding winning action flag table of each reel is expanded (copied) in the winning action flag storage area.

  In this embodiment, the compression / decompression processing of the data related to winning is performed according to the processing procedure described in S647 to S649 during the above-described symbol code acquisition processing, and the above-described instruction code dedicated to the main CPU 101 is included in the processing. By using this, it is possible to increase the efficiency of the data compression / decompression processing related to winning, and to effectively utilize the limited capacity of the main RAM 103.

  In this embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address “SB_BTEP_00” specified by the “CALLF” instruction is the compression of S330 during the symbol setting process described with reference to FIG. In the data storage process, it is the same as the jump destination address specified by the “CALLF” instruction. That is, in this embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process, and S649 and S330 In both processes, the source program for the compressed data storage process is shared (modularized). In this case, since it is not necessary to provide a source program for the compressed data storage process separately in both the processes of S649 and S330, the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[AND operation]
Next, with reference to FIG. 133, for example, the AND operation process performed in S626 in the pull-in priority storage process (see FIG. 126) will be described. FIG. 133 is a flowchart illustrating a procedure of logical product operation processing. The logical product calculation process shown in FIG. 133 is performed not only in S626 in the pull-in priority storage process (see FIG. 126) but also in S687 in the pull-in priority acquisition process (see FIGS. 134 and 135 described later). Is also executed.

  In the logical product operation process executed in S626 during the pull-in priority storage process (see FIG. 126), the two data subjected to the logical product operation are stored in the winning action flag set in S650 during the above-described symbol code acquisition process. Area data and symbol code storage area data. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “12” of the data length (12 bytes) set in S650 during the above-described symbol code acquisition process corresponds to “number of logical products” described later.

  On the other hand, in the AND operation executed in S687 in the below-described pull-in priority acquisition process (see FIG. 134 and FIG. 135 described later), two data to be AND-operated are hit (withdraw) request flag storage areas. And data of a winning action flag storage area. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag described in FIG. 136B described later corresponds to the “number of logical products” described later.

  First, the main CPU 101 acquires logical product source data (for example, data in a symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation on the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and stores the calculation result as the logical product destination data (S662).

  Next, the main CPU 101 adds 1 to the address of the logical product data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

  Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is “0” (S666).

  In S666, when the main CPU 101 determines that the number of logical products is not “0” (when S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is “0” (in the case where S666 is YES), the main CPU 101 ends the logical product operation processing and stores the processing, for example, the drawing priority order storage. The process proceeds to S627 in the process (see FIG. 126).

[Withdrawal priority acquisition processing]
Next, with reference to FIGS. 134 to 137, description will be given of the pull-in priority acquisition process performed in S627 in the pull-in priority storage process (see FIG. 126). FIG. 134 and FIG. 135 are flowcharts showing the procedure of the acquisition priority order acquisition process. FIG. 136A is a diagram showing an example of a source program for executing the processing of S680 to S683, which will be described later, during the pull-in priority acquisition process, and FIG. 136B shows the processing of S686, described later, during the pull-in priority acquisition process. FIG. 136C is a diagram illustrating an example of a source program for executing, and FIG. 136C is a diagram illustrating an example of a source program for executing processing of S687 described later during the pull-in priority acquisition processing. FIG. 137 is a diagram showing an example of the configuration of a pull-in priority table that is actually referred to on the source program of the pull-in priority acquiring process.

  First, the main CPU 101 determines whether or not the right reel 3R (specific display column) is being checked (S671).

  In S671, when the main CPU 101 determines that it is not at the time of checking the right reel 3R (when S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, when the main CPU 101 determines in S671 that the right reel 3R is being checked (when S671 is YES), the main CPU 101 determines “ANY combination” as the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (predetermined symbol combination) is included (S672). Here, the “ANY combination” refers to a combination in which a winning is determined regardless of at least the stop design of the right reel 3R (a winning combination in which at least the stop design of the right reel 3R is an arbitrary design).

  In S672, when the main CPU 101 determines that “ANY combination” is not included in the symbol combination related to the internal winning combination (when S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that “ANY combination” is included in the symbol combination related to the internal winning combination (when S672 is YES), the main CPU 101 determines “ANY combination” in the winning action flag storage area. The storage area corresponding to “comb” is masked (S673). Specifically, the main CPU 101 sets “1” to a bit corresponding to “ANY combination” in the winning action flag storage area.

  After the process of S673, or when S671 or S672 is NO, the main CPU 101 sets “1” as the address of the last storage area as the address of the winning action flag storage area (see FIGS. 28 to 30). The added address is set, stop prohibition data is set, and a winning action flag data length (data length of the winning action flag storage area: 12 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation has been detected. Further, the stop button operation state is acquired by referring to the operation stop button storage area (see FIG. 33).

  Next, the main CPU 101 subtracts 1 (-1 update) the address of the set winning operation flag storage area (S676). Next, the main CPU 101 generates winning request flag data from the set winning operation flag storage area and the corresponding winning request flag storage area (see FIGS. 28 to 30), and the generated winning request flag data. The prohibited winning action position is generated based on (S677).

  Next, the main CPU 101 determines whether or not the stop operation position is a prohibited winning action position (S678).

  In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning action position (when S678 is NO), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (when S678 is YES), the main CPU 101 has the value of the stop button operation counter being the value of the third stop. Whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when S679 is YES), the main CPU 101 performs a process of S705 described later. On the other hand, when the main CPU 101 determines in S679 that the value of the stop button operation counter is not the value of the third stop (when S679 is NO), the main CPU 101 determines that the value of the stop button operation counter is the second stop. Whether it is a value or not is discriminated (S680).

  In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the second stop value (when S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, when the main CPU 101 determines in S680 that the value of the stop button operation counter is the second stop value (when S680 is YES), the main CPU 101 determines whether or not the right reel 3R has stopped. Is discriminated (S681).

  When the main CPU 101 determines in S681 that the right reel 3R has been stopped (when S681 is YES), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S681 that the right reel 3R has not been stopped (NO in S681), the main CPU 101 determines that the hit request flag may be subject to interference “ANY role”. Or not (whether or not “ANY combination” is included in the symbol combination (winning combination) related to the internal winning combination) (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may receive the “ANY role” interference (YES in S682), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be subject to interference of “ANY role” (when S682 is NO), the main CPU 101 determines that the current check is “ANY”. It is determined whether or not it is at the time of checking the hit request flag including “combination” (S683).

  In S683, when the main CPU 101 determines that the current check is a check of the hit request flag including “ANY role” (when S683 is YES), the main CPU 101 performs a process of S705 described later.

  On the other hand, when the main CPU 101 determines in S683 that the current check is not at the time of checking the hit request flag including “ANY role” (when S683 is NO), S678 or S680 is NO, or S681. Alternatively, when S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning action flag data length is “0” (S685).

  In S685, when the main CPU 101 determines that the winning action flag data length is not “0” (when S685 is NO), the main CPU 101 returns the process to the process of S676 and repeats the processes after S676.

  On the other hand, when the main CPU 101 determines in S685 that the winning action flag data length is “0” (when S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). . This process is performed by the main CPU 101 sequentially executing each process defined by the source program in FIG. 136B. Therefore, in this process, the AND operation process described with reference to FIG. 133 is performed. In the logical product calculation process executed in the process of S686, as described above, the data in the winning (withdrawal) request flag storage area is set to “logical product destination data”, and the data in the winning action flag storage area is In the “logical product source data”, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag is set in the “logical product number”. The RT action combination display flag is a storage area in which a symbol combination related to RT transition is defined in the winning action flag storage area. In the present embodiment, only the storage area 11 as shown in FIGS. Become.

  Next, the main CPU 101 refers to the pull-in priority table address storage area and acquires the pull-in priority table (S687). This process is performed by the main CPU 101 sequentially executing each process defined by the source program in FIG. 136C. Therefore, in this process, the initial value “1 (001H)” of the pull-in priority data is set to the currently set address, and the top addresses shown in FIG. 137 are “dPLVLTB00” to “dPLVLTB05”. The pull-in priority table stored in one of the blocks is acquired. Note that the pull-in priority table stored in the blocks whose head addresses are “dPLVLTB00” to “dPLVLTB05” shown in FIG. 137 are the pull-in priority table numbers “00” to “05” described in FIG. 27, respectively. Corresponds to the pull-in priority table.

  Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is an end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data in the pull-in priority order table stored at the currently set address is an end code (when S688 is YES), the main CPU 101 determines that S705 to be described later. Perform the process. On the other hand, when the main CPU 101 determines in S688 that the data in the drawing priority table stored at the currently set address is not an end code (when S688 is NO), the main CPU 101 A flag storage area is set (S689).

  Next, the main CPU 101 acquires pull-in priority data from the pull-in priority table based on the currently set address (S690). Next, the main CPU 101 sets a block counter in the pull-in priority table (S691). In this embodiment, in this process, the main CPU 101 sets “2” to the value of the block counter in the pull-in priority table.

  Next, the main CPU 101 sets the number of checks in the pull-in priority table, and adds 1 (+1 update) to the address of the pull-in priority table to be referred to (S692). In the present embodiment, in this processing, the main CPU 101 sets “8” (the number of bits of check data defined in the pull-in priority table shown in FIG. 137) as the number of checks in the pull-in priority table.

  Next, the main CPU 101 acquires check data (see FIG. 137) based on the updated address of the drawing priority table, and extracts check bits from the check data (S693). In this embodiment, the check bit extracted here corresponds to bit 0 of the check data. For example, in the process of S690, when the pull-in priority data “03EH” is acquired from the pull-in priority data table specified for the block whose head address is “dPLVLTB00”, “10001000B” is used as the check data in the process of S693. Acquired and “0” is extracted as the value of the check bit.

  Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

  In S694, when the main CPU 101 determines that the value of the extracted check bit is not “1” (when S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is “1” (when S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced. (+1 update), and based on the updated address, determination data (“flag determination data” in FIG. 137) is acquired from the pull-in priority table (S695).

  Next, the main CPU 101 determines based on the determination data acquired in S695 whether or not the currently acquired winning action flag data is a determination target (S696). In this process, the main CPU 101 compares the currently acquired winning action flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently acquired winning action flag data is a determination target.

  In S696, when the main CPU 101 determines that the winning action flag data is not a determination target (when S696 is NO), the main CPU 101 performs a process of S699 described later. On the other hand, when the main CPU 101 determines in S696 that the winning operation flag data is the determination target (when S696 is YES), the main CPU 101 performs the update processing of the drawing priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set pull-in priority data with the pull-in priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 performs check data update processing (S698). In this process, the main CPU 101 shifts the check data rightward by 1 bit (in the direction from bit 7 to bit 0). In this process, “0” is set in bit 7 of the check data after the shift.

  After the processing of S698, or when S694 or S696 is NO, the main CPU 101 determines whether or not there is a bit to be checked (bit in which “1” is set) in the check data (S699).

  In S699, when the main CPU 101 determines that there is no check target bit in the check data (when S699 is NO), the main CPU 101 performs a process of S702 described later. On the other hand, when the main CPU 101 determines in S699 that there is a bit to be checked in the check data (when S699 is YES), the main CPU 101 adds 1 to the address of the winning action flag storage area to be checked (+1 update) And 1 is subtracted from the number of checks (S700).

  Next, the main CPU 101 determines whether or not the number of checks is “0” (S701). In S701, when the main CPU 101 determines that the number of checks is not “0” (when S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

  On the other hand, when the main CPU 101 determines in S701 that the number of checks is “0” (in the case where S701 is YES), the main CPU 101 sets the number of checks in the address of the winning action flag storage area that is currently referenced. The initial value “8” is added to update the address of the winning action flag storage area, and the value of the block counter is decremented by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is “0” (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (when S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

  On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is “0” (when S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced (+1 update). (S704). For example, when the pull-in priority table currently being referred to is a pull-in priority table defined for a block whose head address is “dPLVLTB00”, the pull-in priority table to be referred to has a leading address “ It is changed to the pull-in priority table defined for the block “dPLVLTB01”. After the process of S704, the main CPU 101 returns the process to the process of S688, and repeats the processes after S688.

  Here, returning to the processing of S679, S683, or S688 again, if S679, S683, or S688 is YES, the main CPU 101 uses the pulling order data set at this time as the final pulling priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets “0 (00H)” as final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data “0 (00H)”, no pull-in data (stop prohibition) is set. After the process of S705, the main CPU 101 ends the pull-in priority order acquisition process, and moves the process to S628 in the pull-in priority order storing process (see FIG. 126).

  In the present embodiment, the pull-in priority acquisition process is performed as described above. Note that the “ANY role” pull-in priority handling process of S680 to S683 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 136A. Is called. Among them, for example, the determination process of S683 is executed by a “JCP” instruction (predetermined determination instruction) on the source program. The “JCP” instruction is an instruction for executing an operation equivalent to a comparison instruction, and is a dedicated instruction code for the main CPU 101.

  For example, when the source code “JCP cc, A, n, e” is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. Then, the process is jumped to the address designated by e. In the “cc condition” of the “JCP” instruction, one of a carry flag state and a zero flag state in the flag register F is designated (see FIG. 11). For example, if “C” is specified for cc, the condition of cc means that the carry flag is “1” (ON state), and if “NC” is specified for cc, the condition of cc Means that the carry flag is “0” (off state). For example, if “Z” is specified for cc, the condition of cc means that the zero flag is “1” (ON state), and if “NZ” is specified for cc, The condition means that the zero flag is “0” (off state).

  When the “JCP” instruction is used as shown in FIG. 136A on the source program of the “ANY role” pull-in priority handling process, the instruction relating to the address setting can be omitted (the instruction relating to the address setting is separately provided). Therefore, the processing efficiency of the “ANY role” pull-in priority handling process can be increased, and the capacity of the source program (the capacity of the main ROM 102) can be reduced.

  Further, the stop control pull-in request flag setting process of S686 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program in FIG. 136B. In the stop control pull-in request flag setting process in S686, as shown in FIG. 136B, an “LDQ” instruction for specifying an address using the Q register (extension register), which is a dedicated instruction code for the main CPU 101, and “CALLF” Instructions are used.

  Therefore, by using the “LDQ” instruction using the Q register (extension register) in the stop request pull-in request flag setting process in S686, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, an instruction relating to address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced. The “CALLF” instruction is a 2-byte instruction code as described above. Therefore, by using these instruction codes dedicated to the main CPU 101 in the stop control pull-in request flag setting process, the processing efficiency can be improved, and the limited capacity of the main RAM 103 can be effectively utilized. .

  Furthermore, in the present embodiment, in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process, the jump destination logical product operation process address “SB_DAND_00” specified by the “CALLF” instruction is the above-described FIG. This is the same as the jump destination address specified by the “CALLF” instruction in the logical product operation process of S626 during the pull-in priority storage process described in (1). That is, in the present embodiment, the source program for executing the AND operation performed in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process is the logic performed in S626 during the pull-in priority storage process. It is the same as the source program for executing the product operation process, and the source program for the AND operation process is shared (modularized) in both processes of S686 and S626. In this case, since it is not necessary to separately provide a source program for the logical product operation process in both the processes of S686 and S626, the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  In addition, the acquisition processing of the acquisition priority table (see FIG. 137) in S687 during the above-described acquisition priority acquisition processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 136C. Done. Then, in the acquisition processing of the pull-in priority order table in S687, as shown in FIG. 136C, an “LDQ” instruction that performs address designation using the Q register (extended register), which is a main CPU 101 dedicated instruction code, is used.

  Therefore, even in the acquisition processing of the pull-in priority table in S687, an instruction relating to address setting can be omitted on the source program by using the “LDQ” instruction. As a result, it is possible to increase the efficiency of the acquisition priority table acquisition process and reduce the capacity of the source program (the capacity of the main ROM 102).

  As described above, in the various processes during the priority pull-in order acquisition process of the present embodiment, the above-described various instruction codes dedicated to the main CPU 101 are used as appropriate, realizing the efficiency of the corresponding process and the reduction in the capacity of the source program. doing. As a result, in this embodiment, the efficiency of the program processing of the main control circuit 90 and the reduction of the capacity can be achieved, and it is possible to improve the gameability by utilizing the free space corresponding to the reduced capacity. It becomes.

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 82) will be described with reference to FIGS. FIG. 138 is a flowchart showing the reel stop control process. FIG. 139 is a diagram illustrating an example of a source program for executing processes of S711 to S716 described later during the reel stop control process, and FIG. 140 executes a process of S726 described later during the reel stop control process. It is a figure which shows an example of the source program for this.

  First, the main CPU 101 performs a reel stop possible signal OFF process (S711). In this process, the main CPU 101 mainly performs a port output process of the reel stop possible signal OFF data. Further, this process is performed using an unspecified work area in the main RAM 103. Details of the reel stop enable signal OFF process will be described later with reference to FIG. 141 described later.

  Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not it has become “constant speed”) (S712). In S712, when the main CPU 101 determines that the rotation speeds of all the reels are not “constant speed” (when S712 is NO), the main CPU 101 repeats the process of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotation speeds of all the reels have become “constant speed” (when S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal ON data. Further, this process is performed using an unspecified work area in the main RAM 103. Details of the reel stop enable signal ON process will be described later with reference to FIG. 142 described later.

  Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

  When the main CPU 101 determines in S714 that a valid stop button has not been pressed (in the case where S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, when the main CPU 101 determines in S714 that a valid stop button has been pressed (in the case where S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 33), and the stop button has not been pressed. The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines a search target reel from the operation stop button (S716). In addition, in this process, an address (head address) setting process of the spinning control data storage area in which the reel control management information of the search target reel is stored is also performed (source code “LDQ IX, wR1_CTRL− (wR2_CTRL in FIG. 139) -WR1_CTRL) ").

  Next, the main CPU 101 performs a reel stop possible signal OFF process (S717). This process is performed using an unspecified work area of the main RAM 103, as in S711. Details of the reel stop enable signal OFF process will be described later with reference to FIG. 141 described later. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 performs reel stop selection processing (S719). Although a detailed description is omitted, in this process, the main CPU 101 performs the number of sliding pieces selection process.

  Next, the main CPU 101 determines a planned stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined planned stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding frames to the stop start position, and sets the addition result as the planned stop position.

  Next, the main CPU 101 executes symbol code storage processing (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button non-operating counter. When it is “0”, it is determined that the reel to be controlled is the final stop reel.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stop reel (when S722 is NO), the main CPU 101 performs a control change process (S723). In this process, the stop information group used for stopping the reel is updated when the stop position is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 126 (S724).

  Next, the main CPU 101 performs standby interval remaining time standby processing (S725). In this process, the main CPU 101 performs a standby process until a predetermined reel stop interval time has elapsed. After the process of S725, the main CPU 101 returns the process to the process of S711, and repeats the processes after S711.

  Here, the process returns to S722 again, and when the main CPU 101 determines in S722 that the reel to be controlled is the final stop reel (when S722 is YES), the main CPU 101 energizes all reels. It is determined whether or not is in a stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all the reels is not stopped (when S726 is NO), the main CPU 101 repeats the process of S726.

  On the other hand, when the main CPU 101 determines in S726 that the excitation of all the reels is in a stopped state (when S726 is YES), the main CPU 101 remains in the on state in which the stop button operated for the third stop is on. It is determined whether or not (the stop button has not been released) (S727). In S727, when the main CPU 101 determines that the stop button subjected to the third stop operation remains on (when S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, when the main CPU 101 determines in S727 that the stop button for which the third stop operation has been performed is not in the on state (when S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. The process proceeds to S214 in the main flow (see FIG. 82).

  In the present embodiment, the reel stop control process is performed as described above. Note that the processing of S711 to S716 during the reel stop control processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 139, in the reel stop control processing source program of the present embodiment, the main CPU 101 dedicated instruction code, for example, an “LDQ” instruction for addressing using a Q register (extension register), “ The “CALLF” instruction is used.

  Therefore, by using such an instruction code dedicated to the main CPU 101 in the reel stop control process, it is possible to reduce the capacity of the source program for the reel control process and improve the processing efficiency of the reel stop control process. it can. That is, in the present embodiment, it is possible to increase the efficiency of the program processing speed and reduce the capacity in the main control circuit 90, and to utilize the free space of the main ROM 102 increased according to the reduced capacity, Can be increased.

  Further, the determination process of S726 during the reel stop control process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 140, this processing is executed using “LDQ” instruction and “ORQ” instruction (predetermined OR operation instruction) on the source code.

  The “ORQ” instruction is an instruction code for performing an OR operation, and is a dedicated instruction code for the main CPU 101 for performing address designation using a Q register (extension register). For example, when the source code “ORQ (k)” is executed on the source program, the data stored in the Q register (upper address value) and 1-byte integer k (direct value: lower address value) are used. A logical OR operation is performed on the contents (stored data) of the memory at the specified address and the contents (stored data) of the A register, and the calculation result is stored in the A register.

  Therefore, in the determination process of S726 during the reel stop control process, first, when the source code “LDQ A, (.LOW.wR1_TIM)” in FIG. 140 is executed, the data stored in the Q register and the integer value “ . LOW.wR1_TIM ”is loaded into the A register at the address specified by“ LOW.wR1_TIM ”. In the present embodiment, the address of the area storing the excitation timer value of the first reel in the main RAM 103 is “F032h”. In the determination processing of S726 described above, the upper address value “F0h” of the address “wR1_TIM (F032h)” is set in advance in the Q register when the LDQ instruction is executed, and the lower value is set to the value of k (direct value). The address value (“.LOW.wR2_TIM” = 32h) is substituted.

  Next, when the source code “ORQ (.LOW.wR2_TIM)” in FIG. 140 is executed, the address “wR2_TIM () of the storage data (F0h) of the Q register and the excitation timer value of the second reel are stored. F03Dh) ”is obtained by performing an OR operation between the memory contents (excitation timer value of the second reel) at the address specified by the lower address value (3Dh) and the contents of the A register (excitation timer value of the first reel). The calculation result (combination result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code “ORQ (.LOW.wR3_TIM)” in FIG. 140 is executed, the address “wR3_TIM () of the storage data (F0h) of the Q register and the excitation timer value of the third reel are stored. F048h) ”lower address value (48h), the memory contents (third reel excitation timer value) and the A register contents (first reel excitation timer value and second reel excitation timer). OR operation with the value (combination result with the value) is performed, and the operation result (combination result of the excitation timer values of the first to third reels) is stored in the A register.

  As described above, in the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) are used in the reel (rotating cylinder) stop state check process. Therefore, by using these dedicated instruction codes for the main CPU 101, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values, and instructions relating to address setting are omitted from the source program. Accordingly, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  As described above, in the various processes during the reel stop control process of the present embodiment, the above-described various instruction codes dedicated to the main CPU 101 are used as appropriate, thereby realizing the efficiency of the corresponding process and the reduction of the capacity of the source program. ing. As a result, in this embodiment, the efficiency of the program processing of the main control circuit 90 and the reduction of the capacity can be achieved, and it is possible to improve the gameability by utilizing the free space corresponding to the reduced capacity. It becomes.

[Reel stop enable signal OFF processing]
Next, with reference to FIG. 141, the reel stop enable signal OFF process performed in S711 or S717 during the reel stop control process (see FIG. 138) will be described. FIG. 141 is a flowchart showing a procedure of reel stop possible signal OFF processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

  Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 performs a reel stop enable signal OFF data setting process (S734).

  Next, the main CPU 101 performs non-standard port output processing (S735). In this process, the main CPU 101 generates and outputs OFF output data (output off mode data), which will be described later, based on the reel stop enable signal OFF data. This process is performed using an unspecified work area in the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG.

  Next, the main CPU 101 restores all register data saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

  Then, after the process of S737, the main CPU 101 ends the reel stop possible signal OFF process. At this time, if the executed reel stop enable signal OFF process is the process of S711 during the reel stop control process (see FIG. 138), the main CPU 101 shifts the process to the process of S712 during the reel stop control process. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 during the reel stop control process (see FIG. 138), the main CPU 101 shifts the process to the process of S718 during the reel stop control process.

[Reel stop enable signal ON process]
Next, with reference to FIG. 142, the reel stop possible signal ON process performed in S713 during the reel stop control process (see FIG. 138) will be described. FIG. 142 is a flowchart showing the procedure of reel stop enable signal ON processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

  Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 refers to the operation stop button storage area (see FIG. 33) and acquires the stop button state (S744). Next, the main CPU 101 performs a reel stop enable signal ON data setting process (S745).

  Next, the main CPU 101 performs non-standard port output processing (S746). In this process, the main CPU 101 generates and outputs ON output data (output on mode data), which will be described later, based on the reel stop enable signal ON data. This process is performed using an unspecified work area in the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG.

  Next, the main CPU 101 restores all register data saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 to the stack pointer (SP) (S748). After the process of S748, the main CPU 101 ends the reel stop enable signal ON process, and moves the process to the process of S714 in the reel stop control process (see FIG. 138).

[Non-standard port output processing]
Next, with reference to FIG. 143 and FIG. 144, the non-specified port output processing performed in S735 during the reel stop enable signal OFF process (see FIG. 141) and S746 during the reel stop enable signal ON process (see FIG. 142). explain. FIG. 143 is a flowchart illustrating the procedure of non-standard port output processing. In addition, FIG. 144 is a diagram illustrating an example of a source program for executing non-standard port output processing.

  First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and when the reel stop enable signal OFF data is set. It is determined that the port output setting is not the ON output mode.

  In S751, when the main CPU 101 determines that the port output setting is the ON output mode (when S751 is YES), the main CPU 101 performs the process of S753 described later. On the other hand, when the main CPU 101 determines in S751 that the port output setting is not in the ON output mode (when S751 is NO), the main CPU 101 performs processing for generating OFF output data (output off mode data) (S752). ). In this process, among the ports (bits) that are currently in the output on state, the ports (bits) that are to be turned off are turned off, and the ports (bits) that are currently in the output off state are turned off. OFF output data for maintaining the state is generated.

  After the processing of S752 or when S751 is NO, the main CPU 101 performs processing for generating ON output data (output on mode data) (S753). In this process, among the ports (bits) that are currently in the output off state, the ports (bits) that are to be turned on are turned on, and the ports (bits) that are currently in the output on state are turned on. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

  Then, after the processing of S754, the main CPU 101 ends the non-standard port output processing. At this time, if the executed non-regulated port output process is the process of S735 during the reel stop enable signal OFF process (see FIG. 141), the main CPU 101 executes the process of S736 during the reel stop enable signal OFF process. Move to. On the other hand, if the executed non-regulated port output process is the process of S746 during the reel stop enable signal ON process (see FIG. 142), the main CPU 101 shifts the process to the process of S747 during the reel stop enable signal ON process. Transfer.

  In the present embodiment, the non-specified port output process is performed as described above. The non-specified port output process described above is performed by the main CPU 101 sequentially executing each source code specified by the source program of FIG.

  Among them, the OFF output data generation process of S752 during the non-regulated port output process described above executes the source codes “XOR (HL)” and “AND (HL)” in FIG. 144 in this order. Done. Further, the generation processing of the ON output data in S753 during the non-standard port output processing described above is performed by executing the source code “OR (HL)” in FIG.

  By performing such output data generation processing on the source program, the OFF output data generated in S752 even if the ON output data generation processing in S753 is performed after the OFF output data generation processing in S752. Does not change.

  For example, the port output setting is the OFF output mode, the output data indicating the non-standard port to be turned off in this processing is “000111011” (“1” is the bit to be turned off), and the non-standard port is currently set. When the output data (backup data) output to is “01010011” (“1” is currently an on-state bit), the data of bit 0, bit 1 and bit 5 of the backup data is changed from “1” to “1”. OFF output data for generating “0” is generated. In this case, first, when the source code “XOR (HL)” in FIG. 144 is executed, an exclusive OR operation between the output data “00010111” and the backup data “01010011” is performed. 01000100 "is obtained. Next, when the source code “AND (HL)” in FIG. 144 is executed, a logical product operation of the operation result “01000100” and the backup data “01010011” is performed, and the operation result “01000000” is set as OFF output data. Generated.

  After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 144) is executed, the calculation result “01000000” (OFF output data) is turned on in this process. An OR operation is performed on the output data “00000000” indicating the non-standard port to be set (the port output setting is the OFF output mode, so each bit of the output data is set to “0”). “01000000” is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, the output for maintaining the port (bit) that is in the output ON state in the OFF output data in the ON output data generation processing in S753 is maintained in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation processing in S753 is performed after the OFF output data generation processing in S752.

[Winning Search Process]
Next, with reference to FIGS. 145 to 147, the winning search process performed in S <b> 214 in the main flow (see FIG. 82) will be described. FIG. 145 is a flowchart showing the procedure of the winning search process. FIG. 146 is a diagram illustrating an example of a source program for executing a winning search process. FIG. 147 is a diagram showing an example of the configuration of a payout number data table that is actually referred to on the winning search source program.

  First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 35) to the corresponding storage area in the winning action flag storage area (see FIGS. 28 to 30). (S761). At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets the address of the payout number data table (the start address “dPAYNUMB” of the payout number data table shown in FIG. 147) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables (“5” in this embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

  Next, based on the address set in the HL register, the main CPU 101 sets data on the number of medals to be paid out (in this embodiment, one, two, three, or nine) in the C register. The determination target data is set in the A register, and “2” is added (+2 update) to the address set in the HL register (S764). In the payout number data table shown in FIG. 147, the payout number data of medals is “payout number (1, 2, 3 or 9) * 2 + 0”, and the determination target data is the next to the payout number data. 1-byte data (for example, “11111000B”) stored in the address. Hereinafter, the data “0” in the data “payout number (1, 2, 3, or 9) * 2 + 0” of the medal payout number set in the C register is referred to as “determination bit”. This determination bit is information indicating whether or not it is a determination target block for winning search.

  Next, the main CPU 101 extracts the value of the determination bit from the medal payout number data set in the C register (S765). Next, the main CPU 101 determines whether the block is a determination target block based on the extracted determination bit value (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is “1”. In the present embodiment, as shown in FIG. 147, the value of the determination bit is always “0” regardless of the number of medals paid out, and therefore the process of S766 is always NO.

  In S766, when the main CPU 101 determines that the block is not a determination target block (when S766 is NO), the main CPU 101 performs a process of S768 described later. On the other hand, when the main CPU 101 determines in S766 that the block is a determination target block (when S766 is YES), the main CPU 101 subtracts 1 from the address of the winning action flag storage area set in the DE register (- 1 update) (S767).

  After the process of S767 or when S766 is NO, the main CPU 101 extracts the data in the storage area specified by the address of the winning action flag storage area set in the DE register as the determination data (S768).

  Next, the main CPU 101 determines whether or not the determination result is a win based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a win.

  In S769, when the main CPU 101 determines that the result of the determination is not a win (when S769 is NO), the main CPU 101 performs a process of S776 described later. On the other hand, when the main CPU 101 determines in S769 that the result of the determination is a win (when S769 is YES), the main CPU 101 determines that the current game is three games (the number of medals bet is three). ) Is determined (S770).

  In S770, when the main CPU 101 determines that the current game is a three-game game (when S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, when the main CPU 101 determines in S770 that the current game is not a three-game (when S770 is NO), the main CPU 101 pays out a two-game (a game with two medal bets). The number of sheets (2 sheets) is set in the C register (S771).

  After the processing of S771 or when S770 is YES, the main CPU 101 performs payout number update processing (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current value of the winning number counter, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether or not the value of the payout number is less than the maximum payout number “10” (S773).

  In S773, when the main CPU 101 determines that the value of the payout number is less than the maximum payout number “10” (when S773 is YES), the main CPU 101 performs a process of S775 described later. On the other hand, when the main CPU 101 determines in S773 that the value of the payout number is not less than the maximum payout number “10” (when S773 is NO), the main CPU 101 sets the maximum payout number “10” as the payout number. (S774).

  After the processing of S774 or if S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

  After the processing of S775 or when S769 is NO, the main CPU 101 determines whether or not there is another winning (S776). When the main CPU 101 determines that there is another winning in S776 (when S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

  On the other hand, when the main CPU 101 determines in S776 that there are no other winnings (when S776 is NO), the main CPU 101 subtracts 1 from the winning search counter (-1 update) (S777). Note that when there is one active line as in the present embodiment, a plurality of small roles will not be won in duplicate, so the determination process in S776 is always NO.

  Next, the main CPU 101 determines whether or not the value of the winning search counter is “0” (S778).

  In S778, when the main CPU 101 determines that the value of the winning search counter is not “0” (when S778 is NO), the main CPU 101 returns the process to the process of S764 and repeats the processes after S764. On the other hand, when the main CPU 101 determines in S778 that the value of the winning search counter is “0” (in the case where S778 is YES), the main CPU 101 ends the winning search process, and the process proceeds to the main flow (FIG. 82), the process proceeds to S215.

  In the present embodiment, the winning search process is performed as described above. The winning search process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among these, the payout number and determination target data setting processing in S764 is performed by the main CPU 101 executing the source code “LDIN AC, (HL)”.

  For example, when the source code “LDIN ss, (HL)” is executed on the source program, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 146 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The payout number and determination target data) are loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the process of S764, in accordance with the “LDIN” instruction, the payout number data is stored in the A register, the determination target data is stored in the C register, and the address set in the HL register is updated by +2.

  As described above, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one “LDIN” instruction. In this case, an instruction relating to address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  In addition, the medal counter value acquisition process referred to in the determination process of S770 during the above-described winning search process, the winning sheet counter value acquisition process referred to in the process of S772, and the winning number counter executed in the process of S775. As shown in FIG. 146, all of the storage (update) processing is executed by an “LDQ” instruction (instruction code dedicated to the main CPU 101) that performs addressing using the Q register (extended register). Therefore, in the winning search process of this embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values by using the “LDQ” instruction. A command related to the setting can be omitted (there is no need to separately provide a command related to the address setting), and accordingly, the capacity of the source program (used capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Further, the determination process of S769 during the above-described winning search process is executed by a “JSLAA” instruction (predetermined determination instruction) on the source program as shown in FIG. The “JSLAA” instruction is an instruction for executing an operation equivalent to a left shift (SLA) instruction.

  For example, when the source code “JSLAA cc, e” is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address specified by e. The “cc condition” defined by the “JSLAA” instruction specifies the state of the carry flag in the flag register F. For example, if “C” is specified for cc, the condition of cc means that the carry flag is “1” (ON state), and if “NC” is specified for cc, the condition of cc Means that the carry flag is “0” (off state). Therefore, in the source code “JSLAA NC, MN_CKLN — 06” in FIG. 146, if the carry flag is “0” (off state), the process jumps to the address specified by “MN_CKLN — 06”.

  Further, the determination processing of S770 and S773 during the above-described winning search processing is executed by the “JCP” instruction on the source program as shown in FIG. As described above, the “JCP” instruction is an instruction for executing an operation corresponding to the comparison instruction, and is a dedicated instruction code for the main CPU 101.

  Therefore, when the above-described “JSLAA” instruction and “JCP” instruction are used in the source program for winning search processing, the instruction for address setting can be omitted (the instruction for address setting needs to be provided separately). Therefore, the capacity of the source program (capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 82) will be described with reference to FIGS. 148 and 149. FIG. FIG. 148 is a flowchart showing the procedure of the illegal hit check process. FIG. 149 is a diagram illustrating an example of a source program for executing illegal hit check processing. An illegal hit is a lottery in an internal lottery process (see FIG. 92), and a BB winning number and a small bonus winning number (internal winning combination) stored in a winning number storage area in a symbol setting process (see FIG. 97). This is a term indicating that the left reel 3L, the middle reel 3C, and the right reel 3R are stopped on a valid line with a combination of symbols that cannot be established (design combination is not established).

  First, the main CPU 101 sets the address of the winning action flag storage area (see FIGS. 28 to 30) (S781). Next, the main CPU 101 sets the size (number of bytes, “12” in the present embodiment) of the winning action flag storage area to the value of the check counter (S782).

  Next, the main CPU 101, based on the address of the currently set winning action flag storage area, stores the internal winning combination stored in the storage area in the winning request flag storage area (internal winning combination storage area) corresponding to the address. (Hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored at the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

  In this synthesis process, first, the main CPU 101 obtains an exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data) (source program shown in FIG. 149). Source code "XOR (HL)"). Next, the main CPU 101 obtains a logical product of the obtained exclusive OR calculation result and winning combination data (winning operation flag data) (source code “AND (HL)” in the source program shown in FIG. 149). ), The calculation result of the logical product is taken as the synthesis result. If an illegal hit error has not occurred, the value of the synthesis result is “0”.

  Next, the main CPU 101 determines whether an illegal hit error has occurred based on the result of the synthesis process in S784 (S785).

  In S785, when the main CPU 101 determines that an illegal hit error has not occurred (when S785 is NO), the main CPU 101 updates the address of the winning action flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is “0” (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (when S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is “0” (when S788 is YES), the main CPU 101 ends the illegal hit check process, and the process proceeds to the main flow (FIG. 82), the process proceeds to S216.

  Here, the process returns to S785 again. When the main CPU 101 determines in S785 that an illegal hit error has occurred (YES in S785), the main CPU 101 determines that the error processing described with reference to FIG. (S789). By this process, the two characters “EE” indicating the occurrence of the illegal hit error are displayed as error information on the 2-digit 7-segment LED (used for displaying the number of payouts and for error display) included in the information display 6. Error display data is output. The occurrence state (error state) of the illegal hit error is canceled by pressing the reset switch 76 (see FIG. 7).

  Next, the main CPU 101 clears the value of the winning number counter and the data in the winning request flag storage area (S790). After the process of S790, the main CPU 101 ends the illegal hit check process, and moves the process to the process of S216 in the main flow (see FIG. 82).

  In the present embodiment, the illegal hit check process is performed as described above. The illegal hit check process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  In the present embodiment, as shown in FIGS. 28 to 30, the configuration of the winning action flag storage area (display combination storage area) is the same as that of the winning request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning action flag storage area arranged in the main RAM 103 during the combination processing of the combination of the winning action flag storage area and the internal winning combination can be configured identically. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of combining the winning combination data and the internal winning combination data) is, as described above, the winning combination data and the internal It is obtained by simply ANDing (executing with an “AND” instruction) with the winning data. As a result, in this embodiment, the illegal hit check process can be streamlined and simplified, the free capacity of the main control program can be secured (increased), and the increased free capacity can be used to increase game play. It becomes possible to increase.

[Winning check / medal payout processing]
Next, with reference to FIG. 150 and FIG. 151, the winning check / medal payout process performed in S216 in the main flow (see FIG. 82) will be described. FIG. 150 is a flowchart showing a procedure of a winning check / medal payout process. FIG. 151 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the winning check / medal payout process.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning action command transmitted to the sub control circuit 200. The winning action command includes a parameter for specifying a winning action flag (display combination) and the like.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 72 (S802). With this processing, the winning operation command data is stored in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in the interrupt processing described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is “0” (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (in the case of YES determination in S803), the main CPU 101 ends the winning check / medal payout process, and the process proceeds to the main flow ( The process proceeds to S217 in FIG.

  On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not “0” (NO in S803), the main CPU 101 determines that the number of credits (stored number) of medals is the upper limit number (the number of books). It is determined whether or not the number is 50 or more in the embodiment (S804).

  In S804, when the main CPU 101 determines that the number of credits of the medal is not equal to or greater than the upper limit (when S804 is NO), the main CPU 101 adds “1” to the value of the credit counter (+1 update) ( S805). The added credit counter value is displayed by a two-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). Details of the medal payout number check process will be described later with reference to FIG. 152 described later.

  Next, the main CPU 101 determines whether or not the medals have been paid out (S807). When the main CPU 101 determines in S807 that the payout of medals has ended (when S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 82). The process proceeds to S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not ended (when S807 is NO), the main CPU 101 performs payout interval waiting processing (S808). In this process, the main CPU 101 waits until a preset medal payout interval time (in this embodiment, 60.33 msec: 54 cycles of an interrupt process (1.1172 msec period) described later with reference to FIG. 158). Wait. After the process of S808, the main CPU 101 returns the process to the process of S803 and repeats the processes after S803.

  Here, returning to the processing of S804 again, when the main CPU 101 determines in S804 that the number of credits of medals is equal to or greater than the upper limit number (50) (when S804 is YES), the main CPU 101 A medal payout process is performed (S809). Through this process, one medal is paid out. After the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and moves the processing to S217 in the main flow (see FIG. 82).

  In the present embodiment, the winning check / medal payout process is performed as described above. Note that the processing of S804 to S808 during the above-described winning check / medal payout processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  In this embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval waiting) process for 60.33 ms in the process of S808. On the source program, the main CPU 101 executes the source codes “LD BC, cTM_PAYC” and “RST SB_W1BC_00” in this order. In this way, in the winning check / medal payout process, when the payout operation is continued after the credit counter is updated (+1), when waiting for 60.33 ms (waiting for payout interval) is performed, useless waiting time is reduced. Can reduce the mental burden of the player.

[Medal payout number check process]
Next, with reference to FIGS. 152 and 153, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 150) will be described. FIG. 152 is a flowchart showing the procedure of the medal payout number check process. FIG. 153A is a diagram showing an example of a source program for executing the later-described processing of S811 to S814 during the medal payout number check process, and FIG. 153B shows later-described S816 and the medal payout number check process during the medal payout number check process. It is a figure which shows an example of the source program for performing the process of S817.

  First, the main CPU 101 adds “1” to the value of the medal OUT counter (+1 update) (S811). The medal OUT counter is a counter for counting the number of medals paid out. Next, the main CPU 101 adds “1” to the value of the payout number counter (+1 update) (S812). The payout number counter is a counter for counting the number of medals to be paid out.

  Next, the main CPU 101 performs a payout number 7 SEG display process (S813). In this process, the main CPU 101 performs a control process for displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

  Next, the main CPU 101 performs update processing of the combination end number counter (S814). The consecutive end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the consecutive end number counter with its lower limit “0”, and when the value of the end of consecutive number counter is greater than the lower limit “0”, The counter value is decremented by 1 (-1 is updated), and when the value of the combination end number counter is equal to or lower than the lower limit “0”, the value of the combination end number counter is held at “0”.

  Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

  Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub control circuit 200. The credit information command includes a parameter for specifying the number of medals for credit.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 72 (S817). By this processing, the credit information command data is stored in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. After the process of S817, the main CPU 101 ends the medal payout number check process, and moves the process to the process of S807 in the winning check / medal payout process (see FIG. 150).

  In the present embodiment, the medal payout number check process is performed as described above. Note that the processing of S811 to S814 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 153A. Among them, the update processing of the combination end number counter in S814 is executed by the “DCPLD” command (predetermined update command) in FIG. 153A. The “DCPLD” instruction is an instruction code dedicated to the main CPU 101.

  For example, when the source code “DCPLD (HL), n” is executed on the source program, the contents (stored data) of the memory at the address specified by the HL register are compared with the integer n, and the contents of the memory are If it is larger than the integer n, 1 is subtracted from the contents of the memory, and if the memory content is less than or equal to the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code “DCPLD (HL), 0” in FIG. 153A is executed, the contents of the memory at the address specified by the HL register (value of the consecutive end number counter) and the integer 0 (lower limit) Are compared, and if the memory content (the value of the combination end number counter) is larger than the integer 0, the memory content is decremented by 1, and if the memory content is less than or equal to the integer 0, the memory content “0” is set to (the value of the counter end number counter). In other words, if the current value of the consecutive end number counter is greater than “0”, the update process of the consecutive end number counter is performed, and if the current end of number counter value is “0” or less. Then, a process of holding the value of the combination end number counter at “0” is performed.

  As described above, in the process of S814 during the medal payout number check process, the number of consecutively completed sheets is determined by one “DCPLD” command (a command that combines the lower limit determination command of the number management counter and the determination branch command). Both the counter update (subtraction) process and the process of holding the value of the consecutive end number counter at “0” can be executed. In this case, there is no need to provide an instruction code for executing both processes separately. For example, the determination branch instruction code for determining whether or not the value of the consecutive end number counter is “0” can be omitted. Therefore, in the medal payout number check process according to the present embodiment, the capacity of the source program (usage capacity of the main ROM 102) can be reduced, and a free capacity can be secured (increased) in the main ROM 102. It is possible to improve the playability by utilizing the free space.

  Further, the processing of S816 and S817 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 153B.

  In the processing of S816, as shown in FIG. 153B, the communication parameter 1 of the credit information command is set to the value of the payout number counter via the L register, and the communication parameter 5 is credited via the C register. The counter value is set. However, values (undefined values) stored in the H register, E register, and D register at the present time are set in the other communication parameters 2 to 4 constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[BB check processing]
Next, with reference to FIG. 154, the BB check process performed in S217 in the main flow (see FIG. 82) will be described. FIG. 154 is a flowchart showing the procedure of the BB check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). In S821, when the main CPU 101 determines that the current gaming state is not a bonus state (when S821 is NO), the main CPU 101 performs a process of S832 described later.

  On the other hand, when the main CPU 101 determines in S821 that the current gaming state is the bonus state (when S821 is YES), the main CPU 101 counts the number of medals that can be paid out during the bonus state. The number of medals paid out in the winning check / medal payout process is subtracted from the value of the BB payout number counter (S822).

  Next, the main CPU 101 determines whether or not the value of the BB payout number counter is less than “0” (S823). In S823, when the main CPU 101 determines that the value of the BB payout number counter is not less than “0” (when S823 is NO), the main CPU 101 ends the BB check process, and the process proceeds to the main flow (FIG. 82), the process proceeds to S218.

  On the other hand, when the main CPU 101 determines in S823 that the value of the BB payout number counter is less than “0” (when S823 is YES), the main CPU 101 performs a bonus end process (S824). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the on state.

  Next, the main CPU 101 refers to the bonus end CT lottery table (see FIG. 60), and performs the CT lottery at the end of the bonus (S825). Next, the main CP 91 determines whether or not the CT lottery at the end of the bonus is won (S826).

  In S826, when the main CPU 101 determines that the CT lottery has not been won (when S826 is NO), the main CPU 101 performs a process of S828 described later. On the other hand, when it is determined in S826 that the main CPU 101 has won the CT lottery (when S826 is YES), the main CPU 101 adds “1” to the number of CT sets (S827). If the CT lottery is won when the number of ART sets is “0”, “1” is added to the number of CT sets and “1” is also added to the number of ART sets in the process of S827. .

  After the processing of S827 or when S826 is NO, the main CPU 101 determines whether the number of ART sets or the number of CT sets is “1” or more (S828).

  In S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is “1” or more (when S828 is YES), the main CPU 101 sets the ART ready state to the game state of the next game. (S829). Then, after the process of S829, the main CPU 101 ends the BB check process, and shifts the process to the process of S218 in the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S828 that the number of ART sets or the number of CT sets is not “1” or more (when S828 is NO), the main CPU 101 sets the normal gaming state to the gaming state of the next game. (S830). Next, the main CPU 101 refers to the normal medium / high probability lottery table (see FIG. 40B), lottery the CZ lottery state, and sets the lottery result (S831). After the process of S831, the main CPU 101 ends the BB check process, and moves the process to the process of S218 in the main flow (see FIG. 82).

  Here, returning to the processing of S821 again, if S821 is NO, the main CPU 101 determines whether or not the symbol combination related to the BB combination (the combination of symbols “C_BB1” or “C_BB2”) is displayed. (S832). When the main CPU 101 determines in S832 that the symbol combination related to the BB combination has not been displayed (NO in S832), the main CPU 101 ends the BB check process, and the process proceeds to the main flow (see FIG. 82). The process proceeds to S218.

  On the other hand, when the main CPU 101 determines in S832 that the symbol combination related to the BB combination has been displayed (YES in S832), the main CPU 101 refers to the bonus type lottery table (see FIG. 58), The type is lottery and the lottery result is set (S833). Next, the main CPU 101 sets a predetermined value (the number of payouts that triggers the end of the bonus: “216” in this embodiment) as the value of the payout amount counter during BB (S834).

  Next, the main CPU 101 performs bonus start processing (S835). In this process, the main CPU 101 performs various processes necessary for starting the bonus operation, such as setting a bonus state in the game state of the next game. After the process of S835, the main CPU 101 ends the BB check process, and moves the process to S218 in the main flow (see FIG. 82).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 82) will be described with reference to FIGS. 155 and 156. FIG. 155 and 156 are flowcharts showing the procedure of the RT check process.

  First, the main CPU 101 determines whether or not the RT state is the RT5 state (S841). In S841, when the main CPU 101 determines that the RT state is the RT5 state (when S841 is YES), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 82). Move on to processing.

  On the other hand, when the main CPU 101 determines that the RT state is not the RT5 state in S841 (when S841 is NO), the main CPU 101 determines whether or not the RT state is the RT0 state (S842). In S842, when the main CPU 101 determines that the RT state is not the RT0 state (when S842 is NO), the main CPU 101 performs a process of S845 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT0 state in S842 (when S842 is YES), the main CPU 101 displays the symbol combination of the abbreviation “bell spilled eyes” (see FIG. 28). It is determined whether or not (S843). In S843, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spilled eyes” has not been displayed (when S843 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (FIG. 82), the process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S843 that the symbol combination of the abbreviation “bell spilled eyes” is displayed (when S843 is YES), the main CPU 101 sets the RT2 state flag to the on state (S844). . By this process, the RT state shifts from the RT0 state to the RT2 state. Then, after the process of S844, the main CPU 101 ends the RT check process and moves the process to the process of S219 in the main flow (see FIG. 82).

  Here, returning to the process of S842 again, if S842 is NO, the main CPU 101 determines whether or not the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (when S845 is NO), the main CPU 101 performs the process of S850 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT1 state in S845 (when S845 is YES), the main CPU 101 determines whether or not the symbol combination of the abbreviation “bell spill” is displayed. (S846).

  In S846, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spilled eyes” is displayed (when S846 is YES), the main CPU 101 sets the RT1 status flag to the OFF state and the RT2 status flag. Is set to the ON state (S847). With this process, the RT state shifts from the RT1 state to the RT2 state. After the process of S847, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S846 that the symbol combination of the abbreviation “bell spilled eyes” has not been displayed (when S846 is NO), the main CPU 101 determines whether or not 20 games have elapsed in the RT1 state. Is determined (S848).

  In S848, when the main CPU 101 determines that 20 games have not elapsed in the RT1 state (NO in S848), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (see FIG. 82). ) To S219. On the other hand, in S848, when the main CPU 101 determines that 20 games have elapsed in the RT1 state (when S848 is YES), the main CPU 101 sets the RT1 state flag to the off state (S849). With this process, the RT state shifts from the RT1 state to the RT0 state. After the process of S849, the main CPU 101 ends the RT check process and moves the process to S219 in the main flow (see FIG. 82).

  Here, returning to the process of S845 again, when S845 is NO, the main CPU 101 determines whether or not the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (when S850 is NO), the main CPU 101 performs a process of S853 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT2 state in S850 (when S850 is YES), the main CPU 101 displays the symbol combination of the abbreviation “RT3 transition lip” (see FIG. 28). It is determined whether or not (S851). In S851, when the main CPU 101 determines that the symbol combination of the abbreviation “RT3 transition lip” has not been displayed (when S851 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow (FIG. 82), the process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S851 that the symbol combination of the abbreviation “RT3 transition lip” has been displayed (when S851 is YES), the main CPU 101 sets the RT2 state flag to the OFF state and RT3. A state flag is set to an on state (S852). With this process, the RT state shifts from the RT2 state to the RT3 state. After the process of S852, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 82).

  Here, returning to the processing of S850 again, if S850 is NO, the main CPU 101 determines whether or not the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (when S853 is NO), the main CPU 101 performs a process of S862 described later.

  On the other hand, when the main CPU 101 determines that the RT state is the RT3 state in S853 (when S853 is YES), the main CPU 101 displays the symbol combination of the abbreviation “bell spill” or “RT2 transition lip”. It is determined whether or not it has been done (S854).

  In S854, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spill” or “RT2 transition lip” is displayed (when S854 is YES), the main CPU 101 sets the RT3 state flag to the off state. At the same time, the RT2 state flag is set to the on state (S855). With this process, the RT state shifts from the RT3 state to the RT2 state. After the process of S855, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S854 that the symbol combination of the abbreviation “bell spilled eyes” or “RT2 transition lip” is not displayed (when S854 is NO), the main CPU 101 transitions to the abbreviation “RT4 transition”. It is determined whether or not the “Rip” symbol combination (see FIG. 28) is displayed (S856).

  In S856, when the main CPU 101 determines that the symbol combination of the abbreviation “RT4 transition lip” is not displayed (when S856 is NO), the main CPU 101 ends the RT check process, and the process proceeds to the main flow ( The process proceeds to S219 in FIG. On the other hand, when the main CPU 101 determines in S856 that the symbol combination of the abbreviation “RT4 transition lip” has been displayed (when S856 is YES), the main CPU 101 sets the RT3 state flag to the OFF state and RT4. The state flag is set to the on state (S857). With this process, the RT state shifts from the RT3 state to the RT4 state.

  After the processing of S857, the main CPU 101 determines whether or not the gaming state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the gaming state is not the ART ready state (when S858 is NO), the main CPU 101 ends the RT check process, and the process is S219 in the main flow (see FIG. 82). Move on to processing.

  On the other hand, when the main CPU 101 determines in S858 that the gaming state is the ART preparation state (when S858 is YES), the main CPU 101 determines whether or not the number of CT sets is “1” or more. (S859).

  In S859, when the main CPU 101 determines that the number of CT sets is “1” or more (when S859 is YES), the main CPU 101 sets CT to the game state of the next game and sets the CT game number counter. “8” is set (S860). After the process of S860, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S859 that the CT set number is not equal to or greater than “1” (when S859 is NO), the main CPU 101 sets the normal ART to the game state of the next game, and the ART end game. A predetermined value is set in the number counter (S861). Then, after the process of S861, the main CPU 101 ends the RT check process and shifts the process to the process of S219 in the main flow (see FIG. 82).

  Here, returning to the processing of S853 again, if S853 is NO, the main CPU 101 determines whether or not a symbol combination of abbreviation “bell spilled eyes” or “RT2 transition lip” is displayed (S862). In S862, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spill” or “RT2 transition lip” is not displayed (when S862 is NO), the main CPU 101 ends the RT check process. Then, the process proceeds to the process of S219 in the main flow (see FIG. 82).

  On the other hand, in S862, when the main CPU 101 determines that the symbol combination of the abbreviation “bell spill” or “RT2 transition lip” is displayed (when S862 is YES), the main CPU 101 sets the RT4 status flag to the off state. And the RT2 state flag is set to the on state (S863). With this process, the RT state shifts from the RT4 state to the RT2 state. Then, after the process of S863, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 82).

[CZ / ART end processing]
Next, with reference to FIG. 157, the CZ / ART termination process performed in S219 in the main flow (see FIG. 82) will be described. FIG. 157 is a flowchart showing the procedure of CZ / ART termination processing.

  First, the main CPU 101 determines whether or not the current gaming state is either when CZ fails or when ART ends (S871). In S871, when the main CPU 101 determines that the current gaming state is not CZ failure or ART end (when S871 is NO), the main CPU 101 ends the CZ / ART end processing, The process proceeds to S201 in the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S871 that the current gaming state is either CZ failure or ART end (when S871 is YES), the main CPU 101 determines the CZ lottery table (see FIG. 41B). ), CZ pull-back lottery is performed (S872). Next, the main CPU 101 determines whether or not a CZ pullback lottery has been won (S873).

  In S873, when the main CPU 101 determines that the CZ pullback lottery has been won (when S873 is YES), the main CPU 101 sets the type of CZ that has won the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type of CZ in the CZ game number counter (S875). After the process of S875, the main CPU 101 ends the CZ / ART end process, and moves the process to the process of S201 in the main flow (see FIG. 82).

  On the other hand, when the main CPU 101 determines in S873 that the CZ pull-back lottery has not been won (when S873 is NO), the main CPU 101 sets the normal gaming state to the gaming state of the next game (S876). Next, the main CPU 101 refers to the normal medium / high probability lottery table (see FIG. 40B), lotteries the lottery state of CZ, and sets the lottery result (S877). Then, after the processing of S877, the main CPU 101 ends the CZ / ART termination processing, and shifts the processing to S201 in the main flow (see FIG. 82).

[Interrupt processing under the control of the main CPU (1.1172 msec)]
Next, an interrupt process performed by the main CPU 101 at a cycle of 1.1172 msec will be described with reference to FIG. FIG. 158 is a flowchart showing the procedure of interrupt processing. 1. Interrupt processing repeatedly executed at a period of 1172 msec is generated based on the output timing of the time-out signal of the timer circuit 113 set in the initialization processing of the timer circuit 113 (PTC) (see S2 in FIG. 64). This is a process executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs a register saving process (S901). Next, the main CPU 101 performs input port check processing (S902). In this process, signals input from various switches such as a stop switch are checked.

  Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotation of the left reel 3L, the middle reel 3C, and the right reel 3R when the start of rotation of all reels is requested, and thereafter, each reel rotates at a constant speed. Three stepping motors are driven and controlled. When the number of sliding symbols is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the effective line of the display window), and The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

  Next, the main CPU 101 performs communication data transmission processing (S904). In this processing, various commands stored in the communication data storage area are mainly transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting a command to the sub control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. If a plurality of command data is stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the oldest stored order. When no command data is stored in the communication data storage area, that is, when the value of the communication data pointer is “0”, a no-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs inserted medal passage check processing (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed through the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs a WDT restart process (S906).

  Next, the main CPU 101 performs a 7-segment LED drive process (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6 and displays, for example, the number of medals paid out, the number of credits, stop button pressing order data, and the like. The details of the 7-segment LED driving process will be described later with reference to FIG. 159 described later.

  Next, the main CPU 101 performs timer update processing (S908). In this processing, the main CPU 101 performs count (subtraction) processing for various timers that have been set. Details of the timer update process will be described later with reference to FIG. 164 described later.

  Next, the main CPU 101 performs error detection processing (S909). Next, the main CPU 101 performs a door open / close check process (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on / off (door closed) / off (door open) state of the door open / close monitoring switch 67.

  Next, the main CPU 101 performs a test firing test signal control process (S911). In this processing, control processing is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed by using an unspecified work area (see FIG. 12C) of the main RAM 103. In the present embodiment, this process is also performed at times other than during the test firing test (after the pachislot 1 is installed in the amusement store). At this time, the main control board 71 is connected via the second interface boat or the like. Since it is not connected to a testing machine, various test signals are generated but not output. Details of the test test signal control process will be described later with reference to FIG.

  Next, the main CPU 101 performs a register restoration process (S912). Then, after the process of S912, the main CPU 101 ends the interrupt process.

[7-segment LED drive processing]
Next, with reference to FIGS. 159 and 160, the 7-segment LED driving process performed in S907 during the interrupt process (see FIG. 158) will be described. FIG. 159 is a flowchart illustrating the procedure of the 7-segment LED driving process. FIG. 160A is a diagram illustrating an example of a source program for executing the processes of S923 to S925 described later during the 7-segment LED driving process, and FIG. 160B illustrates the process of S931 described later during the 7-segment LED driving process. It is a figure which shows an example of the source program for performing the process of S936.

  First, the main CPU 101 adds “1” to the value of the interrupt counter (+1 update) (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

  In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when S922 is NO), the main CPU 101 ends the 7-segment LED driving process, and the process is interrupted (see FIG. 158). ) In S908. That is, in this embodiment, the 7-segment LED driving process is performed every two interrupt cycles. In this embodiment, the example in which the 7-segment LED driving process is executed when the interrupt counter value is an even number has been described. However, the present invention is not limited to this, and the 7-segment LED drive process is performed when the interrupt counter value is an odd number. The LED driving process may be executed, or the execution timing of the 7-segment LED driving process may be determined using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in S922 that the value of the interrupt counter is an odd number (when S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 161 described later.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets an address of a credit display data storage area for storing credit display data output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 161 described later.

  Next, the main CPU 101 sets an address of a 7-segment common counter storage area for storing a value of a 7-segment common counter described later (S929). Next, the main CPU 101 adds “1” to the value of the 7-segment common counter (+1 update) (S930). In this process, when the updated 7-segment common counter value is “8”, the main CPU 101 sets the 7-segment common counter value to “0”. In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 cycles.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and the address of the target cathode data storage area (the target storage area in the push order display data storage area or the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed to turn off the 7-segment LED and eliminate the influence of afterimages.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). After the process of S936, the main CPU 101 ends the 7-segment LED drive process, and moves the process to the process of S908 in the interrupt process (see FIG. 158).

  In the present embodiment, the 7-segment LED driving process is performed as described above. Note that the processing of S923 to S925 during the 7-segment LED driving processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 160A. Further, the processing of S931 to S936 during the 7-segment LED driving processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 160B.

  Among them, the output processing of each 7-segment output data in S936 is executed by one source code “LD (cPA_SEGCOM), BC” as shown in FIG. 160B. Therefore, in the 7-segment LED driving process of the present embodiment, 7-segment common output (selection) data and 7-segment cathode output data are output simultaneously when dynamic lighting control is performed on a 2-digit 7-segment LED. That is, in the 7-segment LED dynamic lighting control when carrying out the push order navigation on the instruction monitor, and in the 7-segment LED dynamic lighting control when displaying credit information with the 2-digit 7-segment LED, the 7-segment common output ( Selection) data and 7-segment cathode output data are output simultaneously.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Therefore, it becomes possible to improve game playability. In this embodiment, an example in which a 7-segment drive circuit (not shown) that performs 7-segment LED drive processing is configured by a cathode common circuit and controlled by the cathode has been described. However, the present invention is not limited to this, The segment drive circuit may be configured by an anode common circuit, and the 7-segment LED may be controlled by the anode.

  In addition, the navigation data acquisition process of S923 and the address setting process of the push display data storage area of S924 during the 7-segment LED driving process described above both use a Q register (extension register) as shown in FIG. 160A. This is executed by an “LDQ” instruction (instruction code dedicated to the main CPU 101) for specifying an address. Therefore, in the 7-segment LED driving process of this embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values by using the “LDQ” instruction. The command for address setting can be omitted (there is no need to separately provide the command for address setting), and accordingly, the capacity of the source program (capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[7-segment display data generation processing]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 159) will be described with reference to FIGS. FIG. 161 is a flowchart showing the procedure of the 7-segment display data generation process. FIG. 162 is a diagram illustrating an example of a source program for executing the 7-segment display data generation process. FIG. 163 is a diagram illustrating an example of the configuration of a 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

  Note that “display data”, which will be described later, generated in the 7-segment display data generation process performed in S925 in the 7-segment LED drive process (see FIG. 159) corresponds to the push order display data, and the 7-segment LED drive process (see FIG. 159), “display data” described later generated in the 7-segment display data generation process performed in S928 corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, obtains the quotient value of the division result as the display data of the upper digits of the 2-digit 7-segment LED, and divides the data. The remainder of the result is acquired as display data for the lower digits (S941). Next, the main CPU 101 determines whether or not to perform upper digit display based on the acquired upper digit display data (S942).

  In S942, when the main CPU 101 determines to display the upper digits (when S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, when the main CPU 101 determines in S942 that the upper digit display is not performed (when S942 is NO), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the upper digits (S944). Next, the main CPU 101 stores the acquired upper digit display data in the upper digit display data storage area (not shown) (S945).

  Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires display data for the lower digits (S946). Next, the main CPU 101 stores the acquired lower-digit display data in a lower-digit display data storage area (not shown) (S947).

  After the process of S947, the main CPU 101 ends the 7-segment display data generation process. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 158), the main CPU 101 shifts the process to the process of S926 during the 7-segment LED drive process. Transfer. On the other hand, when the executed 7-segment display data generation process is the process of S928 during the 7-segment LED drive process (see FIG. 158), the main CPU 101 shifts the process to the process of S929 during the 7-segment LED drive process. .

  In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

[Timer update processing]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 158) will be described with reference to FIGS. 164 and 165. FIG. FIG. 164 is a flowchart showing the procedure of the timer update process. FIG. 165 is a diagram showing an example of a source program for executing the processes of S951 to S954 described later during the timer update process.

  First, the main CPU 101 sets an update start address of a 2-byte timer storage area (not shown) in the HL register, and sets a 2-byte timer number in the B register (S951).

  Next, the main CPU 101 compares the 2-byte timer value with its lower limit value “0”, and when the 2-byte timer value is larger than the lower limit value “0”, the 2-byte timer value is subtracted by 1 (-1 update). If the 2-byte timer value is less than or equal to the lower limit value “0”, the 2-byte timer value is held at “0” (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 update) the update start address of the 2-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (updates -1) the 2-byte timer number set in the B register (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is “0” (S954).

  In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not “0” (when S954 is NO), the main CPU 101 returns the process to the process of S952, and after S952 Repeat the process.

  On the other hand, when the main CPU 101 determines in S954 that the number of 2-byte timers set in the B register is “0” (when S954 is YES), the main CPU 101 stores the 1-byte timer storage area in the HL register. The update start address is set, and the 1-byte timer number is set in the B register (S955).

  Next, the main CPU 101 compares the 1-byte timer value with its lower limit value “0”, and when the 1-byte timer value is greater than the lower limit value “0”, the 1-byte timer value is subtracted by 1 (-1 update). If the 1-byte timer value is less than or equal to the lower limit value “0”, the 1-byte timer value is held at “0” (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (-1 update) the number of 1-byte timers set in the B register (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is “0” (S958).

  In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not “0” (when S958 is NO), the main CPU 101 returns the process to the process of S956, and after S956 Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is “0” (when S958 is YES), the main CPU 101 performs electromagnetic counter control processing (S959). ). In this process, an output control process when a signal indicating IN / OUT of medals is output to the external concentration terminal board 47 is performed. After the process of S959, the main CPU 101 ends the timer update process and shifts the process to the process of S909 during the interrupt process (see FIG. 158).

  In the present embodiment, the timer update process is performed as described above. Note that the processing of S951 to S954 (2-byte timer update processing) during the timer update processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  Among them, the process of S952 (2-byte timer update process) is executed by a “DCPWLD” instruction (predetermined update instruction) in FIG. The “DCPWLD” instruction is an instruction code dedicated to the main CPU 101.

  On the source program, for example, when the source code “DCPWLD (HL), n” is executed, the memory content (stored data) for 2 bytes from the address specified by the HL register is compared with the integer n, If the memory content for 2 bytes is larger than the integer n, 1 is subtracted from the memory content for 2 bytes. If the memory content for 2 bytes is less than or equal to the integer n, it is specified by the HL register. An integer n is stored in a 2-byte memory from the address.

  Therefore, in the source code “DCPWLD (HL), 0” in FIG. 165, the memory content (2-byte timer value) for 2 bytes from the address specified by the HL register and the integer “0” (lower limit value) When the contents of the memory for 2 bytes are larger than the integer “0”, the contents of the memory for 2 bytes are decremented by 1 and the contents of the memory for 2 bytes are less than the integer “0”. “0” is set in the memory contents of 2 bytes. That is, if the current 2-byte timer value is greater than “0”, the 2-byte timer update process is performed. If the current 2-byte timer value is less than “0”, the 2-byte timer value is “0”. Is held.

  As described above, in the timer update process of the present embodiment, both the update (subtraction) process of the timer value and the process of holding the timer value at “0” are executed by the “DCPWLD” instruction that is the instruction code dedicated to the main CPU 101. can do. In this case, there is no need to provide an instruction code for executing both processes separately. Also, the decision branch instruction code for determining whether or not the timer value is “0” can be omitted. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Therefore, it becomes possible to improve game playability. In this embodiment, an example in which the “DCPWLD” instruction is used only in the update process of the 2-byte timer has been described. However, the present invention is not limited to this, and the “DCPWLD” instruction is also used in the update process of the 1-byte timer. May be used.

[Trial test signal control processing (not specified)]
Next, with reference to FIG. 166, the test firing test signal control process performed in S911 during the interrupt process (see FIG. 158) will be described. FIG. 166 is a flowchart showing the procedure of the test test signal control process.

  First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves data in all registers (S963).

  Next, the main CPU 101 performs a rotating brake signal generation process (S964). In this process, the main CPU 101 generates and outputs a rotation control signal (drive signal) for each reel that is output to the testing machine via the second interface boat or the like. The details of the rotation brake signal generation processing will be described later with reference to FIG. 167 described later.

  Next, the main CPU 101 performs a special signal control process (S965). In this process, the main CPU 101 performs an output process of a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. Details of the special signal control process will be described later with reference to FIG.

  Next, the main CPU 101 performs a conditional device signal control process (S966). In this process, the main CPU 101 performs a control signal output process corresponding to the state of the conditional device signal control flag. Details of the condition device signal control processing will be described later with reference to FIGS. 169 and 170 described later.

  Next, the main CPU 101 performs a process for restoring the data of all registers saved in the process of S963 (S967). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S968). Then, after the process of S968, the main CPU 101 ends the test fire test signal control process, and shifts the process to the process of S912 in the interrupt process (see FIG. 158).

[Rotating brake signal generation processing]
Next, with reference to FIG. 167, the rotation brake signal generation process performed in S964 in the test fire test signal control process (see FIG. 166) will be described. In addition, FIG. 167 is a flowchart showing the procedure of the rotation brake signal generation process.

  First, the main CPU 101 sets a spinning cylinder control data storage area (not shown) in an unspecified work area (S971). Next, the main CPU 101 sets “3” as the number of reels, and clears the spinning cylinder control signal and its generation state (1 byte data) (S972).

  Next, the main CPU 101 determines whether or not the rotation control data is “less than stopped” data (S973). Note that the “less than stop” rotation control data here refers to rotation control data other than the rotation control data for stopping the reel, that is, rotation control data (acceleration for rotating the reel). Preparation, acceleration, waiting for constant speed, waiting for constant speed, and waiting for stop start position).

  In S973, when the main CPU 101 determines that the rotation control data is “less than stopped” data (when S973 is YES), the main CPU 101 performs the process of S975 described later. On the other hand, in S973, when the main CPU 101 determines that the rotation control data is not “less than stopped” data (when S973 is NO), the main CPU 101 determines that the rotation control data is “end of static hold control”. It is determined whether or not the data is “S” (S974). Note that the “rotation control data” of “end of static hold control” here is the rotation control data indicating the all-phase all-stop state of the reels.

  In S974, when the main CPU 101 determines that the spinning cylinder control data is “end of static hold control” (when S974 is YES), the main CPU 101 performs the process of S976 described later. On the other hand, in S974, when the main CPU 101 determines that the rotation control data is not “end of the static hold control” (when S974 is NO), or when S973 is YES, the main CPU 101 Bit 3 of the rotation control signal generation state (1-byte data) is turned on (“1”) (S975).

  After the process of S975 or when S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by one bit to the right (in the direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the spinning cylinder control data storage area to the address of the next reel to be controlled (S977).

  Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is “0” (S979).

  In S979, when the main CPU 101 determines that the number of reels is not “0” (when S979 is NO), the main CPU 101 returns the process to the process of S973 and repeats the processes after S973.

  On the other hand, when the main CPU 101 determines in S979 that the number of reels is “0” (in the case where S979 is YES), the main CPU 101 sends the generated state data to the testing machine via the rotating brake signal output port. To the first interface board 301 (see FIG. 7) (S980). Then, after the processing of S980, the main CPU 101 ends the rotation brake signal generation processing, and shifts the processing to the processing of S965 in the test firing test signal control processing (see FIG. 166).

[Special signal control processing]
Next, with reference to FIG. 168, the special prize signal control process performed in S965 in the test fire test signal control process (see FIG. 166) will be described. FIG. 168 is a flowchart showing the procedure of the special signal control process.

  First, the main CPU 101 refers to the gaming state flag storage area (see FIG. 32) and acquires a gaming state flag (S991). Next, the main CPU 101 determines whether or not the gaming state is an RB gaming state (S992).

  In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (when S992 is YES), the main CPU 101 sends an ON signal from the RB signal port for the test signal to the first interface for the testing machine. The data is output to the board 301 (see FIG. 7) (S993). On the other hand, when the main CPU 101 determines in S992 that the gaming state is not the RB gaming state (when S992 is NO), the main CPU 101 sends an OFF signal from the RB signal port for the test signal to the first for testing machine. The data is output to the interface board 301 (see FIG. 7) (S994).

  After the processing of S993 or S994, the main CPU 101 refers to the gaming state flag storage area (see FIG. 32) to determine whether or not the gaming state is the BB gaming state (S995).

  In S995, when the main CPU 101 determines that the gaming state is the BB gaming state (when S995 is YES), the main CPU 101 sends an ON signal from the BB medium signal port for the test signal to the first interface for the testing machine. The data is output to the board 301 (see FIG. 7) (S996). On the other hand, when the main CPU 101 determines in S995 that the gaming state is not the BB gaming state (when S995 is NO), the main CPU 101 sends an OFF signal from the BB medium signal port for the test signal to the first for testing machine. The data is output to the interface board 301 (see FIG. 7) (S997).

  After the process of S996 or S997, the main CPU 101 ends the special signal control process, and moves the process to the process of S966 in the test test signal control process (see FIG. 166).

[Condition device signal control processing]
Next, with reference to FIG. 169 and FIG. 170, the condition device signal control process performed in S966 in the test fire test signal control process (see FIG. 166) will be described. 169 and 170 are flowcharts showing the procedure of the condition device signal control process.

  First, the main CPU 101 determines whether or not the conditional device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the condition device signal control flag is in the initial state (when S1001 is YES), the main CPU 101 ends the condition device signal control process, and the process is a test test signal control process. The process proceeds to S967 in (see FIG. 166).

  On the other hand, when the main CPU 101 determines in S1001 that the condition device signal control flag is not in the initial state (when S1001 is NO), the main CPU 101 determines that the condition device signal control flag indicates that the re-game state identification signal is on. It is determined whether or not it is to be shown (S1002).

  In S1002, when the main CPU 101 determines that the conditional device signal control flag indicates the ON state of the re-playing state identification signal (when S1002 is YES), the main CPU 101 serves the conditional device signal control state. The on state of the object condition apparatus signal is set (S1003). Next, the main CPU 101 outputs information on the RT state from the condition device 1-6 signal port to the first interface board 301 for tester (see FIG. 7) (S1004). After the process of S1004, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 166).

  On the other hand, when the main CPU 101 determines in S1002 that the conditional device signal control flag does not indicate the ON state of the re-playing state identification signal (when S1002 is NO), the main CPU 101 determines that the conditional device signal control flag is It is determined whether or not the re-playing state identification signal indicates an off state (S1005).

  In S1005, when the main CPU 101 determines that the conditional device signal control flag indicates the off state of the re-playing state identification signal (when S1005 is YES), the main CPU 101 detects the conditional device 1-8 signal port. The OFF signal is output to the first interface board 301 for testing machine (see FIG. 7) (S1006). After the process of S1006, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 166).

  On the other hand, when the main CPU 101 determines in S1005 that the conditional device signal control flag does not indicate the off state of the re-gaming state identification signal (when S1005 is NO), the main CPU 101 indicates that the conditional device signal control state is It is determined whether or not the accessory condition device signal is in an ON state (S1007).

  In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (when S1007 is YES), the main CPU 101 receives the special prize winning from the condition devices 1 to 8 signal port. The number information is output to the first interface board 301 for tester (see FIG. 7), and at this time, the ON signal is output from the condition device 8 signal port to the first interface board 301 for tester (see FIG. 7) (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) to the conditional device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal output waiting state to the condition device signal control state (S1010). Then, after the process of S1010, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 166).

  On the other hand, when the main CPU 101 determines in S1007 that the condition device signal control state is not the ON state of the accessory condition device signal (when S1007 is NO), the main CPU 101 determines that the condition device signal control state is the condition device signal. It is determined whether or not the output is waiting (S1011).

  In S1011, when the main CPU 101 determines that the condition device signal control state is the condition device signal output waiting state (when S1011 is YES), the main CPU 101 sets the value of the condition device signal output waiting timer to “0”. Is determined (S1012).

  In S1012, when the main CPU 101 determines that the value of the conditional device signal output waiting timer is not “0” (when S1012 is NO), the main CPU 101 ends the conditional device signal control processing and performs the test test. The process proceeds to S967 in the signal control process (see FIG. 166). On the other hand, when the main CPU 101 determines in S1012 that the value of the conditional device signal output waiting timer is “0” (when S1012 is YES), the main CPU 101 enters the small device condition device in the conditional device signal control state. The signal on state or the condition device signal off state is set (S1013). Then, after the process of S1013, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 166).

  Here, returning to the processing of S1011 again, in S1011, when the main CPU 101 determines that the condition device signal control state is not a condition device signal output waiting state (when S1011 is NO), the main CPU 101 It is determined whether or not the device signal control state is the ON state of the small role condition device signal (S1014).

  In S1014, when the main CPU 101 determines that the condition device signal control state is the ON state of the small role condition device signal (when S1014 is YES), the main CPU 101 starts the small role from the condition devices 1 to 8 signal port. The information of the winning number is output to the first interface board 301 for tester (see FIG. 7), and at this time, the ON signal is output from the condition device 7 signal port to the first interface board 301 for tester (see FIG. 7). (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set to the conditional device signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal output waiting state to the condition device signal control state (S1017). Then, after the process of S1017, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 166).

  On the other hand, when the main CPU 101 determines in S1014 that the condition device signal control state is not the ON state of the small role condition device signal (when S1014 is NO), the main CPU 101 turns OFF from the condition devices 1 to 8 signal port. The signal is outputted to the first interface board 301 for tester (see FIG. 7) (S1018). Then, after the process of S1018, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 166).

<Description of operation of sub-control circuit>
Next, contents of various processes executed by the sub CPU 201 of the sub control circuit 200 using a program will be described with reference to FIGS. 171 to 173.

[Sub-side navigation control processing]
First, the sub-side navigation control process will be described with reference to FIG. FIG. 171 is a flowchart showing the procedure of the sub-side navigation control process.

  First, the sub CPU 201 determines whether navigation data has been acquired (S1101). The sub CPU 201 acquires navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1101, the sub CPU 201 determines whether or not navigation data is included in the received start command data.

  When the sub CPU 201 determines in S1101 that the navigation data has been acquired (when S1101 is YES), the sub CPU 201 sets sub navigation data corresponding to the navigation data (S1102). For example, when the sub CPU 201 acquires the navigation data “4”, as shown in FIG. 63, the navigation data for informing the push order “left, middle, right” is set as the sub-side navigation data in this process. The As a result, the contents of the stop operation can be notified on both the main side and the sub side. Then, after the process of S1102, the sub CPU 201 ends the sub-side navigation control process.

  On the other hand, when it is determined in S1101 that the sub CPU 201 has not acquired navigation data (NO in S1101), the sub CPU 201 determines whether navigation (notification of stop operation) is necessary. (S1103). In the present embodiment, the sub CPU 201 needs to navigate, for example, when a flag conversion lottery is performed on the main control board 71 or when a predetermined combination is determined as an internal winning combination on the main control board 71. Is determined. Note that the result of the flag conversion lottery and the type of the internal winning combination are included in the start command data. Therefore, in the processing of S1103, the sub CPU 201 determines whether or not navigation is necessary based on the various information included in the start command data.

  When the sub CPU 201 determines that the navigation is not necessary in S1103 (when S1103 is NO), the sub CPU 201 ends the sub-side navigation control process.

  On the other hand, when the sub CPU 201 determines that navigation is necessary in S1103 (when S1103 is YES), the sub CPU 201 sets sub-side navigation data according to various lottery results (S1104). For example, if the internal winning combination “F_Chief Lip” is determined and the flag conversion lottery is won, the sub CPU 201 uses this processing to display a symbol combination related to the abbreviation “Triple Chile Lip”. Set the data (for example, navigation data that targets the Chile symbol by pushing forward). In addition, for example, when the internal winning combination “F_acceptance lip” is determined and the flag conversion lottery is non-winning, the sub CPU 201 displays a symbol combination related to the abbreviation “Replay” in this process. Navigation data (for example, navigation data indicating a pressing order other than the forward pressing) is set. By these processes, even if the main side does not notify the details of the stop operation, the sub-side alone can notify the details of the stop operation. Then, after the process of S1104, the sub CPU 201 ends the sub-side navigation control process.

[Player registration process]
Next, a player registration process will be described with reference to FIG. FIG. 172 is a flowchart showing the procedure of player registration processing.

  First, the sub CPU 201 determines whether or not a registration operation has been accepted (S1111). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18 and a predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 performs the registration operation. Is determined to have been accepted.

  In S1111, when the sub CPU 201 determines that a registration operation has been received (when S1111 is YES), the sub CPU 201 sets a player registration state (S1112). In the situation where the player registration state is set, the sub CPU 201 sets the sub display device 18 so that the game information screens 223, 224, and 225 (see FIGS. 5C to 5E) can be displayed on the sub display device 18. Control the display screen. Then, after the process of S1112, the sub CPU 201 ends the player registration process.

  On the other hand, when the sub CPU 201 determines in S1111 that the registration operation has not been received (when S1111 is NO), the sub CPU 201 determines whether or not a registration deletion operation has been received (S1113). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that a registration deletion operation has been accepted.

  When the sub CPU 201 determines in S1113 that the registration deletion operation has not been accepted (NO in S1113), the sub CPU 201 ends the player registration process.

  On the other hand, when it is determined in S1113 that the sub CPU 201 has accepted the registration deletion operation (when S1113 is YES), the sub CPU 201 clears the player registration state (S1114). In the situation where the player registration state is cleared, the sub CPU 201 causes the sub display device 18 so that the game information screens 223, 224, and 225 (see FIGS. 5C to 5E) cannot be displayed on the sub display device 18. Control the display screen. Then, after the processing of S1114, the sub CPU 201 ends the player registration processing.

[History management processing]
Next, the history management process will be described with reference to FIG. FIG. 173 is a flowchart showing the procedure of history management processing.

  First, the sub CPU 201 acquires a game result from various command data received from the main control board 71 (S1121). For example, in this process, the sub CPU 201 can grasp the type of the combination determined as the internal winning combination from the start command data. Further, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning action command data (that is, whether or not a winning combination is determined as an internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current gaming state and the transition state of the gaming state from the start command data or the like.

  Next, the sub CPU 201 performs a game history update process based on the acquired game result (S1122). By this processing, the sub CPU 201, for example, based on the game results acquired from the various command data, for example, the number of bonuses, the number of ARTs, the number of games (games), the number of CZs, the number of successful CZs, Various game histories such as probabilities can be managed. Then, after the process of S1122, the sub CPU 201 ends the history management process.

<Various effects>
In the pachi-slot 1 of the present embodiment, the following various effects are obtained in the game playability.

[Management of duration during CT]
In the pachi-slot 1 of this embodiment, CT is provided as an extra chance zone that can extend the duration of normal ART, and the number of ART games is added based on the internal winning combination (subflag) in this CT. In CT, one set of 8 games is played, but if the number of ART games can be added during CT, the number of games is not subtracted without adding the number of games, and the number of games is set only if it cannot be added. Subtract. Therefore, for the player, it is not known how long the CT will continue, and since the CT will not end as long as the addition is performed, the interest of the game during the CT can be enhanced.

  In the present embodiment, when CT is won by winning the sub-flag EX “Triple Chile Lip” (winning the sub-flag conversion lottery) during the CT, one set of 8 CT games is also reset (stock). Is done. In this case, for example, even if the CT game period is just before the end, when the sub flag EX “Triple Chile Lip” is won, the addition is performed and the CT is restarted from the beginning. As a result, the game can be continued without being bored and the interest of the game during CT can be enhanced.

  In addition, the addition at the time of winning the sub flag EX “Triple Chile Lip” is performed only when the internal winning combination “F_Challenging Lip” or “F_1 Chilli Lip” is determined as the internal winning combination and the flag conversion lottery is won. . Therefore, it is possible to prevent an excessive profit from being given to the player and to balance the profit between the player and the game store. In the above-described embodiment, an example (see FIG. 54) in which a flag conversion lottery is always won when the internal winning combination “F_Correct Lip” or “F_1 Accurate Lip” is determined during CT has been described. The present invention is not limited to this, and the winning probability of the flag conversion lottery can be appropriately set according to the profit balance between the player and the game store.

[Number of games added at the time of winning “Triple Chile Lip” in CT]
In the pachislot machine 1 of the above embodiment, when the sub-flag “triple chilli lip” is won during CT and the number of times of addition based on the sub-flag “triple chilli lip” exceeds a predetermined number, The number of games added to the winning ART increases (see FIG. 55). Further, as described above, as long as the number of ART games is added, CT does not end, and CT is reset when the sub flag EX “Triple Chile Lip” is hit. Therefore, the player can have an expectation that the additional amount per time (one game) increases as the CT continues, and the interest during CT is improved. Furthermore, the number of times that the amount of addition per game (one game) is increased is the number of times (9 times or more) larger than the number of basic games (8 times) for one set of CT. Therefore, it is possible to prevent an excessive profit from being given, and to balance (keep good) the profit between the player and the game store.

[Bonus notification on the main side]
In the pachi-slot 1 of the above embodiment, the numerical value “10” uniquely associated with the stop operation information for displaying the symbol combination related to the bonus combination (BB combination) on the instruction monitor (not shown) of the information display 6. ”(Or“ 11 ”) is displayed, bonus notification is performed on the main side (see FIG. 63). However, in the pachislot, the priority order of the symbols to be drawn (stopped display) on the active line is usually set, and if the bonus combination and other combinations are determined as internal winning combinations, Thus, the symbol combination related to the bonus combination may be withdrawn or may not be withdrawn.

  For example, in the pachi-slot 1 of this embodiment, the bonus combination and any of the internal winning combination “out of”, “F_special combination 1”, “F_special combination 2”, and “F_special combination 3” are determined in an overlapping manner. If it is, the combination of symbols related to the bonus combination can be drawn, but the bonus combination and the internal winning combination “out”, “F_special combination 1”, “F_special combination 2” and “F_special combination 3” When a combination other than is determined in duplicate, the symbol combination related to the bonus combination cannot be drawn. Therefore, in the present embodiment, the bonus combination and any of the internal winning combination “out of”, “F_special combination 1”, “F_special combination 2”, and “F_special combination 3” are determined in an overlapping manner. Only in some cases, the numerical value “10” (or “11”) is displayed on the instruction monitor. In this case, navigation on the main side (bonus notification) can be performed at an appropriate timing at which a bonus combination can be won.

  Also, in the pachislot 1 of the present embodiment, the bonus combination and any of the internal winning combination “out”, “F_special combination 1”, “F_special combination 2”, and “F_special combination 3” are determined in an overlapping manner. Even if the bonus combination is won for the first time until the predetermined number of games have elapsed, the numerical value “10” (or “11”) is not displayed on the instruction monitor (no navigation), and the predetermined number of times. On condition that the game has passed, a numerical value “10” (or “11”) is displayed on the instruction monitor.

  For example, when an effect (so-called continuous effect) is performed over a plurality of games triggered by winning the bonus combination, a numerical value “10” (or “ If 11 ") is displayed, the meaning of the continuous performance may be lost and the interest may be impaired. Therefore, in the pachislot machine 1 of this embodiment, the display by the instruction monitor is not performed until a predetermined number of games have elapsed, and the display by the instruction monitor is performed after the predetermined number of games have elapsed. As a result, the bonus notification on the main side can be performed without impairing the effect.

[Notification performed on both the main side and the sub side and notification performed on the sub side alone]
In the pachi-slot 1 of the present embodiment, a plurality of types of symbols having different symbol combinations displayed according to the mode (pushing order) of the stop operation are provided (see FIG. 24), and the symbols to be displayed are displayed on these multiple types of symbols. A combination to which a different privilege is given depending on the combination and a combination to which the same privilege is given even if the displayed symbol combination is different are included.

  For example, the number of medals to be paid out is different between the case where the symbol combination related to the abbreviation “Bell” is displayed and the case where the symbol combination related to the abbreviation “Bell spill” is displayed. It is a role to which different privileges are given depending on the combination. Whether or not the transition of the RT state is performed in addition to the re-game operation when the symbol combination related to the abbreviation “Replay” is displayed and when the symbol combination related to the abbreviation “RT2 transition lip” is displayed. Therefore, the internal winning combination “F_3 selection bell_1st” and “F_maintenance lip_1st” are also roles to which different privileges are given depending on the displayed symbol combination.

  On the other hand, in the case where the symbol combination related to the abbreviation “Triple Chile Lip” is displayed and the case where the symbol combination related to the abbreviation “Replay” is displayed, both only re-actuate. Therefore, the internal winning combination “F_Challenging Lip” or “F_1 Chicking Lip” is a role to which the same privilege is given even if the displayed symbol combinations are different. As described above, the internal winning combination “F_Challenging Lip” or “F_1 Challenging Lip” has different privileges depending on the result of the flag conversion lottery, but the privilege to be given by the displayed symbol combination It is not a role that affects.

  In the pachi-slot 1 of the present embodiment, notification is given on both the main side and the sub-side for a role that is given a different privilege depending on the displayed symbol combination, but even if the displayed symbol combination is different, the same For the combination to which a privilege is given, notification is not performed on the instruction monitor on the main side, but only on the display device 11 on the sub side. By providing such a notification function, notification that affects the privilege is appropriately performed on the instruction monitor on the main side that manages the privilege, while notification that does not affect the privilege is diverse on the display device 11 on the sub side. Can be done with navigation.

[Game history display function]
In the pachi-slot 1 of the present embodiment, a sub display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and various information useful to the player is displayed by the sub display device 18. For example, as shown in FIGS. 5A to 5E, a top display 221 representing an outline game history, a menu screen 222 capable of various operations on the pachislot 1, and game information screens 223, 224, and 225 representing detailed game history are displayed as sub-display devices. 18 can be displayed.

  Further, the pachislot machine 1 of the present embodiment has a function of enabling registration of a player who performs a game and a function of providing a unique service to the registered player via the sub display device 18. For example, in this embodiment, when the player registration is not accepted, the game information screens 223, 224, and 225 showing the detailed game history are not displayed on the sub display device 18, but the player registration is not performed. If it is received, the game information screens 223, 224, and 225 showing the detailed game history are displayed on the sub display device 201. Making it possible to confirm a more detailed game history leads to an improvement in the convenience of the player. Therefore, in the present embodiment, the convenience can be improved when registration of the player is accepted.

  Further, in the pachislot machine 1 of the present embodiment, the sub display device 18 is provided separately from the display device 11 that produces effects. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Moreover, the display unit 212 which comprises the display apparatus 11 is controlled by the sub control board 72 (sub CPU201) via the accessory relay board | substrate (not shown). Therefore, in the present embodiment, the sub display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub display device 18 can be switched even during the game (that is, during the performance of the display device 11). Therefore, even during the game, the player can acquire various information by switching the display of the sub display device 18 without interfering with the effect performed by the display device 11.

  Further, in the display device 11 of the pachislot machine 1 of the present embodiment, a planar image display is used by switching a plurality of screen mechanisms (display units 212) that cause an image to appear by irradiation of irradiation light from the projector mechanism 211. When performing an effect, an effect using a video display with a sense of depth (stereoscopic effect), and an effect using a curved image display, the effect can be remarkably enhanced. However, such a display form of information is not suitable for displaying information that is not related to an effect such as a game history during the effect. Therefore, in the pachi-slot 1 of the present embodiment, information that is not related to the effect can be displayed on the sub display device 18 provided separately from the display device 11, so that the effect of the effect is not impaired and the game Various information such as history can be displayed appropriately.

  By the way, in a general pachislot machine, when viewed from the player side, a medal slot 14 is provided on the right side of the pedestal portion 13, and bet buttons 15 a and 15 b and a start lever 16 are provided on the left side of the pedestal portion 13. Therefore, usually, when the game is advanced, the player operates the operation unit on the right side or the left side (side) of the pedestal unit 13.

  On the other hand, in the pachislot machine 1 of the present embodiment, the sub display device 18 is provided on the side (left side) of the surface standing upright from the pedestal portion 13, and the sub display device 18 is displayed on the screen of the sub display device 18. A touch sensor 19 for switching the display screen is provided. Therefore, in this embodiment, the sub display device 18 and the input device (touch sensor 19) for controlling the display are provided at a place where the player's hand is located during the game. Can be improved. In particular, as in this embodiment, when the sub display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 that is erected from the horizontal plane, the player places his / her hand on the pedestal portion 13. However, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player accompanying the operation can be reduced, and as a result, an improvement in the operating rate can be expected.

[Non-standard ROM area and non-standard RAM area]
In the pachi-slot 1 of this embodiment, as shown in FIG. 12B, various programs and various types used for various processes (various processes that do not affect game characteristics) that are not directly related to the game performance of the game performed by the player. Data (table) is stored in a non-specified ROM area located at an address different from the game ROM area in the main ROM 102.

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually performed by the player are placed in the ROM area (non-regulated ROM area) where it is impossible to place a program or the like according to conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid compression of the capacity of the game ROM area in the main ROM 102 of the main control board 71, and it is possible to improve the expandability of programs and tables in the main ROM 102.

[Effects obtained by processing at power-on (reset interrupt)]
In the power-on (reset interrupt) process of the pachislot machine 1 of this embodiment, as shown in FIG. 64, the first 1.1172 ms cycle interrupt process is performed immediately after power recovery (before the sum check) (S7 and S8). ), A no-operation command is transmitted from the main control circuit 90 to the sub-control circuit 200. In this way, by permitting the interrupt processing immediately after the power is restored, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  Further, the communication parameters 1 to 5 constituting the no-operation command transmitted immediately after the power is restored are set with the data stored in the L register, H register, E register, D register and C register, respectively, when the power is restored. Is done. Therefore, in the present embodiment, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power recovery can be made different every time the power is recovered, thereby suppressing illegal acts such as goto. it can.

  Furthermore, the control for displaying the error code “rr” on the 2-digit 7-segment LED in the information display 6 performed in the process of S13 during the process of turning on the power (reset interrupt) is performed by one “LDW”. ”Command (predetermined read command), the 7-segment common (selection) data output operation to the 2-digit 7-segment LED and the 7-segment cathode output data output operation are performed simultaneously (see FIG. 65C). That is, in the pachislot machine 1 of the present embodiment, when the 2-digit 7-segment LED is dynamically controlled in the power-on (reset interrupt) process, the 7-segment common output (selection) data and the 7-segment cathode output data are Output simultaneously.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

[Effects obtained by game return processing]
In the game return process of the pachi-slot 1 of this embodiment, as shown in FIG. 66, while ensuring the input / output state of each port at the time of power interruption at the time of power recovery, The reel control management information is acquired when the power is restored, and processing necessary for starting the reel re-rotation is also performed (see S25 to S32). Therefore, in this embodiment, even when the power is restored from the power interruption during the reel rotation, the reel re-rotation control can be stably performed, and the player is not discomforted.

  Moreover, the pachislot 1 of this embodiment is provided with the microprocessor 91 with the security function for game machines as mentioned above. The microprocessor 91 is provided with various kinds of instruction codes (instruction codes dedicated to the main CPU 101) specific to the microprocessor 91 that can be defined in the source program, and the instruction codes dedicated to the main CPU 101 are used in various processes. As a result, processing efficiency and program capacity can be reduced.

  For example, in the game return process, as shown in FIG. 67, the “LDQ” instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The “LDQ” instruction is an instruction code for specifying an address using a Q register (extension register), and can access the main ROM 102, the main RAM 103, and the memory map I / O as direct values as described above. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program for the game return process (the capacity used for the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by setting change confirmation process]
In the setting change confirmation process of the pachi-slot 1 of the present embodiment, as shown in FIG. 69A, the “BITQ” instruction and the “SETQ” instruction (predetermined instructions), which are instruction codes dedicated to the main CPU 101, are used on the source program. . Each of the “BITQ” instruction and the “SETQ” instruction is an instruction code for specifying an address using a Q register (extension register). When these instruction codes are used, the main RAM 103 is a direct value as described above. And memory map I / O. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to increase the processing speed.

  69A and 69B shows the setting change command (initialization command) generation / storage process performed at the time of setting change / setting check start in S46 and at the time of setting change / setting check end in S57 during the setting change checking process. In addition, it is executed by a “CALLF” instruction which is an instruction code dedicated to the main CPU 101 on the source program. The jump destination address designated by the “CALLF” instruction in S46 is the same as the jump destination address designated by the “CALLF” instruction in S57. That is, in the present embodiment, a setting change command (initialization command) generation and storage process to be transmitted to the sub-control circuit 200 at the time of setting change (when a gaming machine is started), at the time of setting check start (during normal operation), and at the end of setting check Are the same as each other, and the source program is shared (modularized) in both processes of S46 and S57.

  In this case, since it is not necessary to provide a source program for generating and storing the setting change command separately in both the processes of S46 and S57, the capacity of the source program (the capacity of the main ROM 102) can be reduced correspondingly. it can. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects of setting change command generation / storage processing]
In the setting change command generation / storage processing of the pachi-slot 1 of this embodiment, as shown in FIG. 70, the setting value is stored as the communication parameter 3 in the E register, and the RT information is stored as the communication parameter 5 in the C register. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), communication parameters 3 and 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1, 2, and 4 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. And 4 are set to values currently stored in the L register, H register, and D register, respectively. Therefore, the values of the communication parameters 1, 2, and 4 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Effects obtained by communication data storage processing]
In the communication data storage process of the pachi-slot 1 of this embodiment, as shown in FIG. 72, the data stored in the A register is set as the type data of the communication command, and the L register, H register, E register, D register, and C The data stored in the register is set as communication parameters 1 to 5 of the communication command, respectively, and the data stored in the B register is set as gaming state flag data of the communication command. That is, in the present embodiment, when creating communication data (command data) of one packet (8 bytes), various parameters are transferred from the register and stored in a communication data temporary storage area (communication buffer).

  In this case, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. That is, in command data including unused parameters, even if there is command data of the same type and the values of the used parameters are the same, the command data sum value (BCC data) can be changed every time the command is created. . Therefore, in this embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress illegal acts such as goto, and it is necessary to add unnecessary goth countermeasure processing. Therefore, it is possible to suppress the compression of the program capacity of the main control circuit 90 due to the addition of the anti-going process.

[Effects obtained by communication data pointer update processing]
In the communication data pointer update process of the pachi-slot 1 of this embodiment, as shown in FIG. 75A, an “ICPLD” instruction that is an instruction code dedicated to the main CPU 101 is used on the source program.

  In the communication data pointer update process, the “ICPLD” instruction is an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated. Therefore, an instruction code for executing each instruction process separately is provided. There is no need to provide it. Therefore, by using the “ICPLD” instruction, it is possible to reduce the capacity of the source program for the communication data pointer update process (the capacity used by the main ROM 102). As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by checksum generation processing and sumcheck processing]
In the pachi-slot 1 of this embodiment, in the checksum generation process (not specified) performed at the time of power interruption, as shown in FIG. 77, the checksum is calculated by sequentially adding the data in the main RAM 103. On the other hand, in the sum check process (not specified) performed when the power is turned on (when the power is restored), as shown in FIG. 79, the checksum value generated when the power interruption occurs is stored in the main RAM 103 when the power is restored. The data is sequentially subtracted, and whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is “0”. In other words, in the present embodiment, the checksum generation process when power interruption occurs is performed by the addition method, and the checksum determination process when power is restored is performed by the subtraction method.

  When such checksum generation processing and determination processing are employed, it is not necessary to generate the checksum again when the power is restored and to check the checksum with the checksum when the power interruption occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omission of the collation instruction code, and it is possible to improve the gameability by utilizing the increased free space. Become.

[Effects obtained by medal reception and start check processing]
In the medal acceptance / start check process of the pachi-slot 1 of this embodiment, as shown in FIG. 83, a setting change confirmation process (the process of S233) is performed. This process is executed regardless of the gaming state. Therefore, in this embodiment, even if the gaming state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power interruption history, etc.)) can be confirmed, Can be suppressed.

[Effects obtained by medal insertion processing]
In the medal insertion process of the pachislot 1 of this embodiment, as shown in FIG. 85, in the process of S244, the LED lighting data for displaying the number of medal insertions is generated not by the loop process referring to the table but by the arithmetic process. . Specifically, a series of source codes “LD A, L” to “OR L” in the source program shown in FIG. 86 are sequentially executed to generate LED lighting data for displaying the number of inserted medals.

  When the LED lighting data for displaying the number of inserted medals is generated by calculation processing, the free space in the table area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. That is, in the medal insertion process of the present embodiment, the medal insertion LED display process can be made more efficient, the free capacity of the main ROM 102 is secured (increased), and the increased free area is utilized to increase the game performance. Can be increased.

[Effects obtained by medal insertion check processing]
In the medal insertion check process (see FIG. 87) of the pachi-slot 1 of the present embodiment, the normal change value generation process of the medal sensor input state in S257 is performed by an arithmetic process, not a process of obtaining with reference to a table. Specifically, the medal sensor input state normal change value is calculated by sequentially executing the source code “RLA” and “AND cBX_MDINSW” in the source program shown in FIG.

  By changing the detection process of the change state of the medal sensor input state from the table reference process to the calculation process, the free space in the table storage area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. it can. Therefore, by adopting the processing method described above, it is possible to increase the efficiency of the detection process of the change state of the medal insertion sensor state, and it is possible to improve the gameability by utilizing the increased free space in the main ROM 102. it can.

[Effects obtained by internal lottery processing]
In the internal lottery process (see FIG. 92) of the pachi-slot 1 of this embodiment, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 93A. As a result of the execution of the “LDIN” instruction, determination data (value of “lottery value selection table or lottery counting table”) is stored in the A register in the process of S305, and a request flag status (“special prize winning number” is stored in the C register. + Small Bonus Winning Number ”) is stored. Also, by executing the “LDIN” instruction, the address set in the HL register is updated by +2 (added by 2).

  That is, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed with one instruction code ("LDIN" instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Further, the addition processing of the set value data (any one of 0 to 5) in S309 of the internal lottery processing is performed by the main CPU 101 using the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM) in FIG. 93B. ) "In this order.

  The “MUL” instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachislot machine 1 of the present embodiment, an arithmetic dedicated circuit (arithmetic circuit 107) for executing multiplication processing and division processing on the source program is provided, so that the efficiency of the multiplication processing and division processing is improved. Can do.

  The “ADDQ” instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for performing address designation using the Q register (extension register). By using this “ADDQ” instruction, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values. Therefore, by using the “ADDQ” instruction, an instruction relating to address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (usage capacity of the main ROM 102) is reduced correspondingly. Can do. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by the symbol setting process]
In the symbol setting process (see FIG. 97) of the pachislot 1 of the present embodiment, the compressed data storage process of S330 is performed by the main CPU 101 executing the source code “CALLF SB_BTEP_00” in FIG. The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_BTEP_00” in FIG. 99 is executed, the process is performed at the address specified by “SB_BTEP_00”. The compressed data storage process is started by jumping.

  Also, the process of setting the address of the hit request flag storage area in S329 during the symbol setting process is performed by the main CPU 101 executing the source code “LDQ DE, .LOW.wWAVEBIT” in FIG. That is, the process of S329 is performed by the “LDQ” instruction dedicated to the main CPU 101 using the Q register (extension register). In this case, the instruction code related to the address setting can be omitted on the source program for the symbol setting process, and the capacity of the source program for the symbol setting process (the capacity used in the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  In the present embodiment, the data compression / decompression processing for winning is performed according to the processing procedure described in S324 to S330 during the above-described symbol setting processing, and the above-described instruction code dedicated to the main CPU 101 is included in the processing. By using it, it is possible to improve the efficiency of the compression / decompression processing of data related to winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Effects obtained by sub-flag conversion processing]
In the pachi-slot 1 of this embodiment, in the sub-flag conversion table shown in FIG. 107 that is actually referred to in the source program of the sub-flag conversion process, sub-flag conversion control data (control status) is associated with each sub-flag. . At this time, the same subflag conversion control data (control status) is associated with the same type of subflag.

  For example, the subflag conversion control data (control status) “00000011B” is commonly assigned to the subflags “triple dust A” and “triple dust B”. Then, in the flag conversion lottery process when converting the internal winning combination (sub flag) to the sub flag EX, lottery is performed based on the sub flag conversion control data (control status) associated with the sub flag.

  As described above, in the sub flag conversion table managed on the main side, by providing common sub flag conversion control data for the same type of internal winning combination (sub flag), the versatility of the conversion table is increased, and accompanying the model change Since the conversion program can be changed with a slight change, an increase in development cost can be suppressed.

[Effects obtained by navigator set processing]
In the navigation set process of the pachislot 1 of the present embodiment, as shown in FIG. 109, an “LDQ” instruction (instruction code dedicated to the main CPU 101) for specifying an address using a Q register (extension register) is used on the source program. It is done.

  Therefore, in the navigation set process according to the present embodiment, an instruction relating to address setting can be omitted from the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by table data acquisition processing]
In the table data acquisition process (see FIG. 120) of the pachislot 1 of this embodiment, in the first-stage table data acquisition process of S581 to S584, the winning combination table selection in the CT CT lottery table during CT (see FIG. 122) A relative table is referenced. In the winning combination table selection relative table to be referred to in the first stage table data acquisition process, the CT lottery “losing” is set by the selection value provided for each type of the internal winning combination (sub flag D). Therefore, it is not necessary to specify the lottery value for the “losing” role in the lottery table. Therefore, in the present embodiment, it is not necessary to store lottery value data for “losing” in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

  Also, in the lottery table at the second stage in the CT winning lottery table during CT (when the sub flag D “reach eye lip” is acquired), a lottery target role or a non-lottery target role is determined based on the value of each bit constituting the determination bit. Therefore, it is not necessary to store lottery value data (loss data) in a table for a combination that is not a lottery target. Further, in the CT winning CT lottery table during CT, a lottery value “0” can be used as the confirmed data in which the winning probability of the lottery object combination is 100%. For these reasons, in the present embodiment, the capacity of the CT winning lottery table during CT (the lottery table added with the number of sets during CT) can be compressed, and free space can be secured (increased) in the main ROM 102. , You can increase the playability by utilizing the increased free space.

[Effects obtained by symbol code acquisition processing]
In the symbol code acquisition process (see FIG. 128) of the pachislot 1 of the present embodiment, the data related to winning is compressed / decompressed according to the processing procedure described in S647 to S649, and the instruction dedicated to the main CPU 101 in the process By using a code (such as a “CALLF” instruction), it is possible to improve the efficiency of the compression / decompression processing of data related to winning, and the limited capacity of the main RAM 103 can be used effectively.

  In the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address specified by the “CALLF” instruction is the compressed data storage process of S330 during the symbol setting process (see FIG. 97). Are the same as the jump destination address designated by the “CALLF” instruction. That is, in the present embodiment, the source program for executing the compressed data storage process is shared (modularized) in both the symbol code acquisition process and the symbol setting process. In this case, since it is not necessary to provide a source program for compressed data storage processing separately in each process, the capacity of the source program (usable capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by pull-in priority acquisition processing]
In the pull-in priority acquisition process (see FIGS. 134 and 135) of the pachislot 1 of the present embodiment, the determination process in S683 during the pull-in priority corresponding process of “ANY role” is based on the instruction code dedicated to the main CPU 101 on the source program. It is executed by a certain “JCP” instruction (comparison instruction) (see FIG. 136A).

  When the “JCP” instruction is used in the “ANY role” pull-in priority processing, the address setting command can be omitted as described above. The processing efficiency of the processing can be increased, and the capacity of the source program (used capacity of the main ROM 102) can be reduced.

  In addition, in the stop request pull-in request flag setting process in S686 during the pull-in priority acquisition process, as shown in FIG. 136B, the Q register (extended register), which is a dedicated instruction code for the main CPU 101, is used in the source program. An “LDQ” instruction and “CALLF” instruction for addressing are used.

  Therefore, in the stop control pull-in request flag setting process in S686, by using the “LDQ” instruction, an instruction for address setting can be omitted in the source program, and the capacity of the source program (use of the main ROM 102) can be omitted. Capacity) can be reduced. The “CALLF” instruction is a 2-byte instruction code as described above. Therefore, by using these instruction codes dedicated to the main CPU 101 in the stop control pull-in request flag setting process, the processing efficiency can be improved, and the limited capacity of the main RAM 103 can be effectively utilized. .

  Further, in the present embodiment, in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process, the address of the logical product operation process of the jump destination specified by the “CALLF” instruction is the pull-in priority storage process ( This is the same as the jump destination address designated by the “CALLF” instruction in the logical product operation processing of S626 in FIG. 126 (see FIG. 127). That is, in this embodiment, the source program for executing the AND operation processing is shared (modularized) in both the priority pull-in order acquisition process and the pull-in priority order storage process.

  In this case, since it is not necessary to provide a source program for logical product operation processing separately in both the priority pull-in order acquisition process and the pull-in priority order storage process, the capacity of the source program (the capacity used in the main ROM 102) correspondingly. Can be reduced. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  In addition, in the acquisition processing of the acquisition priority table (see FIG. 137) in S687 during the acquisition priority acquisition processing, as shown in FIG. 136C, an “LDQ” instruction (instruction code dedicated to the main CPU 101) is used. Therefore, even in the acquisition process of the pull-in priority table in S687, an instruction for address setting can be omitted on the source program. As a result, it is possible to increase the efficiency of the acquisition priority table acquisition process and reduce the capacity of the source program (the capacity of the main ROM 102).

[Effects obtained by reel stop control processing]
In the reel stop control process (see FIG. 138) of the pachi-slot 1 of this embodiment, in the processes of S711 to S715, as shown in FIG. 139, address designation is performed using a Q register (extension register) on the source program. An “LDQ” instruction and a “CALLF” instruction are used.

  Therefore, in this embodiment, by using these instruction codes dedicated to the main CPU 101, it is possible to reduce the capacity of the source program of the reel control process and improve the processing efficiency of the reel stop control process. That is, in this embodiment, it is possible to increase the efficiency of the program processing speed and reduce the capacity in the main control circuit 90, and to utilize the free area of the main ROM 102 that increases according to the reduced capacity, Can be increased.

  Further, in the determination processing of S726 (reel (rotating drum) stop state check processing) during the reel stop control processing, as shown in FIG. 140, the “LDQ” instruction and the “ORQ” instruction (Q An instruction code dedicated to the main CPU 101 that performs addressing using a register (extended register) is used.

  Therefore, in the present embodiment, an instruction for address setting can be omitted on the source program of the reel stop control process, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced accordingly. . As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by winning search processing]
In the payout search process (see FIG. 145) of the pachislot 1 of the present embodiment, the “LDIN” instruction is used on the source program as shown in FIG. 146 in the payout number and determination target data setting process in S764.

  Therefore, in the winning search process of this embodiment, both the data load process and the address update process can be performed by one “LDIN” instruction. In this case, an instruction relating to address setting can be omitted from the source program of the winning search process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Further, the medal counter value acquisition process referred to in the determination process of S770 during the winning search process, the winning sheet counter value acquisition process referred to in the process of S772, and the winning number counter stored in the process of S775 ( In each of the (update) processing, as shown in FIG. 146, an “LDQ” instruction for specifying an address using a Q register (extended register) is used. Therefore, in the winning search process of the present embodiment, an instruction relating to address setting can be omitted on the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Further, in the determination process in S769 during the winning search process, as shown in FIG. 146, the “JSLAA” instruction is used in the source program, and in the determination processes in S770 and S773, the “JCP” instruction is used. When the “JSLAA” instruction and the “JCP” instruction are used on the source program of the winning search process, as described above, the address setting instruction can be omitted, and the capacity of the source program (main ROM 102) Used capacity) can be reduced. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Effects obtained by illegal hit check processing]
In this embodiment, as shown in FIGS. 28 to 30, the configuration of the winning action flag storage area (display combination storage area) is the same as that of the winning request flag storage area (internal winning combination storage area). Therefore, in the arithmetic processing of S784 in the illegal hit check processing of the present embodiment, the winning combination data and the internal winning combination data are simply ANDed (“AND” instruction) on the source program (see FIG. 149). Just execute it, you can get the result of combining the winning combination data and the internal winning combination data.

  Therefore, in this embodiment, the illegal hit check process can be made efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space is used to improve the game performance. be able to.

[Effects obtained by winning check / medal payout processing]
In the winning check / medal payout process (see FIG. 150) of the pachislot 1 of the present embodiment, when the payout operation is continued after the credit counter is updated (+1), a wait between 60.33 ms (payout interval) in the process of S808. Wait) processing is performed. In this case, useless waiting time can be reduced, and the mental burden on the player can be reduced.

[Effects obtained by the medal payout number check process]
In the update processing of the combination end number counter in S814 during the medal payout number check process (see FIG. 152) of the pachislot 1 of this embodiment, as shown in FIG. 153A, the instruction code dedicated to the main CPU 101 is displayed on the source program. A “DCPLD” instruction is used.

  In the process of S814, the “DCPLD” instruction is an instruction code in which the lower limit determination instruction of the number management counter and the determination branch instruction are integrated. Both processes for holding the value of the counter at “0” can be executed. In this case, there is no need to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process according to the present embodiment, the capacity of the source program (usage capacity of the main ROM 102) can be reduced, and a free capacity can be secured (increased) in the main ROM 102. The free space can be used to improve gameplay.

  In the process of S816 during the medal payout number check process, as shown in FIG. 153B, the payout number counter value is set in the communication parameter 1 of the credit information command, and the credit counter value is set in the communication parameter 5. Is done. However, values stored in the H register, E register, and D register at the present time are set in the other communication parameters 2 to 4 (unused parameters) constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Effects obtained by 7-segment LED drive processing]
The output processing of 7-segment common output (selection) data and 7-segment cathode output data performed in S936 during the 7-segment LED drive processing (see FIG. 159) of the pachislot 1 of this embodiment is performed as one source as shown in FIG. 160B. It is executed by the code “LD (cPA_SEGCOM), BC”. That is, in the present embodiment, in the 7-segment LED driving process, when the two-digit 7-segment LED is controlled to be dynamically lit, 7-segment common output data and 7-segment cathode output data are output simultaneously. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program of the 7-segment LED driving process. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

[Effects obtained by timer update processing]
In the process of S952 (2-byte timer update process) in the timer update process (see FIG. 164) of the pachislot 1 of the present embodiment, as shown in FIG. DCPWLD "instruction is used.

  When the “DCPWLD” instruction is executed in the timer update process, both the update (subtraction) process of the timer value (2-byte timer value) and the process of holding the timer value at “0” are executed as described above. Can do. In this case, there is no need to provide an instruction code for executing both processes separately. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

<Various modifications>
Heretofore, the configuration and operation of the gaming machine according to the present invention have been described including the effects thereof. However, the present invention is not limited to the above-described embodiments, and includes various other embodiments and modifications without departing from the gist of the present invention described in the claims.

[Variation 1: CT sign game and notification lottery during normal ART]
In the pachislot machine 1 of the above-described embodiment, in order to facilitate understanding, an example of shifting the game state from the next game (next game) to the advantageous state when winning the player's advantageous state (for example, CT) is won. However, the present invention is not limited to this. For example, when performing game control in an advantageous state for a player, the game control in the advantageous state may be performed after a predetermined number of games, which is referred to as a so-called “predictive game” or the like. .

  Here, with reference to FIGS. 174A and 174B, an example will be described in which the gaming state shifts from normal ART to CT via a predetermined number of precursor games. In addition, FIG. 174A is a diagram showing a game flow at the time of CT lottery winning in Modification 1, and FIG. 174B is a configuration diagram of a flag conversion lottery table used in a flag conversion lottery performed during a precursor game.

  In the game during the normal ART in this example, first, as shown in FIG. 174A, the CT lottery table (see FIG. 50) is used as in the above embodiment, and the CT lottery is based on the internal winning combination (sub flag). I do. When this CT lottery is won, it is determined that the gaming state shifts to an advantageous state for the player called CT (additional chance zone), so various lotteries for CT lottery are used until the CT is won. Is performed on the main side (main control board 71). For example, the main control board 71 (main CPU 101) performs an internal lottery for determining the internal winning combination, and as the internal winning combination, the internal winning combination “F_Challenging Lip”, “F_1 Correcting Chilli Lip”, and “F_Reach Eye Lip A”. ”To“ F_reach eye lip D ”, flag conversion lottery is performed using the ART flag conversion lottery table (see FIGS. 47A and 47B).

  Next, when a CT lottery is won in a game during a normal ART, in this example, a precursor game (CT precursor game) for a predetermined period is performed before the transition to CT. In this example, in the CT sign game, for example, a bonus for a player such as a CT lottery based on the sub-flag EX determined by flag conversion lottery (“triple chili lip”, “reach eye lip”, “replay”, etc.), etc. The lottery that gives However, in this example, in CT precursor game, for example, flag conversion lottery using the flag conversion lottery table shown in FIG. 174B is performed on the sub side (sub control board 72 side), and flag conversion lottery performed on this sub side is performed. Based on the result, the notification content to be performed on the sub side is controlled (determined). For example, when winning the flag conversion lottery performed on the sub side, information for displaying the symbol combination related to the abbreviation “reach eye lip” is notified on the display device 11 (projector mechanism 211 and display unit 212), When the flag conversion lottery is non-winning, the display device 11 notifies the display device 11 of information for displaying the symbol combination related to the abbreviation “Replay”.

  As described above, in recent pachislot machines, it is required to perform a lottery that affects the player's profit (out), but in the pachislot machine 1 of this example, the lottery result of the flag conversion lottery is a game. A period (CT precursor game period) that does not affect the profits of the player is provided, and flag conversion lottery is performed on the sub side only during this period. Therefore, in this example, for example, in a situation where the grant of a privilege that is CT precursor is decided, for example, the opportunity to display a special symbol combination such as a symbol combination related to the abbreviation “reach eye lip” can be increased. At the same time, variations in how to show symbol combinations can be increased. As a result, according to the configuration of this example, it is possible to further improve the playability.

  Note that the lottery table shown in FIG. 174B is a flag conversion lottery table for CT precursors used for flag conversion lottery performed on the sub side, and is stored in the ROM cartridge substrate 86. The flag conversion lottery table during the CT sign shows the internal winning combination “F_reach eye lip A” to “F_reach eye lip D”, the lottery result (non-winning / winning) of the flag conversion lottery performed on the sub side, and each lottery. The correspondence relationship with the lottery value information associated with the result is defined.

  As is clear from the flag conversion lottery table shown in FIG. 174B, in this example, in the CT precursor game, the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” has a very high probability of sub-flag EX “ It is converted to “reach eye lip” (winning flag conversion lottery). That is, in the CT sign game, when any of the internal winning combination “F_reach eye lip A” to “F_reach eye lip D” is determined, the symbol combination of the abbreviation “reach eye lip” is stopped and displayed with high probability. As a result, it can be suggested to the player that the current game is a CT precursor game. At this time, as described above, when winning the flag conversion lottery performed on the sub side in CT precursor game, a notification is given to display the symbol combination related to the abbreviation “reach eye lip”, but a privilege is given There is no.

  In this example, a flag conversion lottery during CT sign game may be performed on the main side. However, as in the example described with reference to FIGS. 174A and 174B, by performing lottery on the sub-side during a period that does not affect the player's profit, the data capacity and processing load on the main side can be reduced.

[Variation 2: Another example of pressing order for triple-tilt display]
In the pachi-slot 1 of the above embodiment, when the internal winning combination “F_accurate lip” or “F_1 credible lip” is determined, if the stop button is pressed in the correct order, the symbol combination related to the abbreviation “triple chill” The example in which the symbol combination related to the abbreviation “Replay” is displayed when the displayed order and the pressing order is incorrect has been described (see FIG. 24). In the above-described embodiment, an example in which the push order of the correct answers associated with the internal winning combination “F_Challenging Lip” and “F_1 Chick Lip” is “Forward”. However, the present invention is not limited to this.

  For example, when the internal winning combination “F_Challenging Lip” or “F_1 Challenging Lip” is determined, the number of symbol combinations displayed when the push order is incorrect is increased, and the internal winning combination “F_Challenging Lip” The order of pushing correct answers when "" is determined may be different from that when the internal winning combination "F_1 correct chililip" is determined. One example (Modification 2) will be described with reference to FIGS. 175A and 175B. 175A is a diagram showing a correspondence relationship between the internal winning combination and the symbol combination to be stopped (stop symbol (abbreviation)) in the second modification, and FIG. 175B is a normal ART in the second variation. It is a figure which shows the correspondence of the result of this flag conversion lottery and the navigation classification performed by the sub side.

  In this example, as shown in FIG. 175A, in the case where the internal winning combination “F_acceptance lip” is determined, the correct pressing order is “forward pressing (the left reel 3L is first stopped)”, and the incorrect answer is pressed. The order is “middle reel 3C first stop (hereinafter referred to as“ middle push ”) or right reel 3R first stop (hereinafter referred to as“ reverse push ”), that is,“ anomalous push ”. In this example, when the internal winning combination “F_Chili Lip” is determined, the symbol combination related to the abbreviation “Triple Chilli Lip” is displayed when pressed forward, and when the key is pressed, the abbreviation “Replay” is displayed. When the symbol combination related to is displayed and pressed backwards, the symbol combination related to the abbreviation “Dual Chilli Lip” is displayed.

  Further, in this example, when the internal winning combination “F_1 certainty lip” is determined, the correct answer push order is reverse push, and the incorrect answer push order is forward push and middle push. In this example, when the internal winning combination “F_1 correct chili lip” is determined, the symbol combination related to the abbreviation “triple chili lip” is displayed when pressed backward, and the abbreviation “replay” when pressed in the middle. When the symbol combination related to is displayed and pressed forward, the symbol combination related to the abbreviation “two-line chili lip” is displayed.

  In the case of the pachislot 1 in this example, when either of the internal winning combination “F_Challenging Lip” and “F_1 Chick Lip” is determined, depending on the type of internal winning combination, A symbol combination related to “double lip” is displayed. In addition, when either of the internal winning combination “F_Challenging Lip” or “F_1 Accuracy Chilli Lip” is determined, if the reverse pressing is performed, the abbreviation “Triple Chilli Lip” or “Dual Chilli Lip” or “Dual Chilli Lip” is selected depending on the type of the internal winning combination. ”Is displayed. Furthermore, in this example, when either of the internal winning combination “F_Challenging Lip” and “F_1 Chick Lip” is determined, the combination of symbols related to the abbreviation “Replay” regardless of the type of the internal winning combination. Is displayed.

  When the correspondence relationship between the internal winning combination and the symbol combination to be stopped (stopped symbol (abbreviation)) is set to the relationship shown in FIG. 175A, for example, the internal winning combination “F_accurate lip” or “F_1 accurate dip” is determined. In this case, it is possible to perform various navigations (notifications) for causing the player to aim for the Chile symbol.

  For example, it is possible to perform both “navigation that targets a Chile symbol by pressing forward” and “navigation that targets a Chile symbol by pressing backward”. In addition, when the internal winning combination “F_Chili Lip” is determined, “Navi that targets the Chile symbol by pressing forward” becomes a navigation for displaying the symbol combination related to the abbreviation “Triple Chile Lip”. The “navigation that targets the Chile symbol by reverse pressing” is a navigation for not displaying the symbol combination related to the abbreviation “Triple Chile Lip” (the navigation in which the symbol combination related to the “Two Chilli Lip” is displayed). On the other hand, when the internal winning combination “F_1 Chilli Lip” is determined, “Navi that targets the Chile symbol by pushing forward” is a navigation for not displaying the symbol combination related to the abbreviation “Triple Chilli Lip” (abbreviated “Abbreviation“ "Navi that displays the symbol combination related to" Two Chilli Lips "is displayed, and" Navigation that targets the Chile symbol by reverse pressing "is a navigation for displaying the symbol combinations related to the abbreviation" Triple Chilli Lip ".

  In this example, whether or not to perform the navigation described above is managed by a flag conversion lottery performed on the main side, and navigation is executed by the control on the sub side based on the result of the flag conversion lottery on the main side. . At this time, the correspondence between the lottery result of the flag conversion lottery performed on the main side during the normal ART and the navigation type controlled on the sub side is the correspondence shown in FIG. 175B.

  Also in this example, when the internal winning combination “F_Challenging Lip” or “F_1 Chanting Lip” is determined in the game during the normal ART, the main control board 71 (main CPU 101) performs a two-stage flag conversion lottery ( (See FIG. 47). On the other hand, the sub-side obtains the result of the two-stage flag conversion lottery from the start command data, and determines the navigation to be performed on the display device 11 based on the result of the two-stage flag conversion lottery.

  Therefore, in this example, when the lottery result is non-winning at the time of the first-stage flag conversion lottery, the sub control board 72 (sub CPU 201) displays “Replay Navi” as shown in FIG. 175B. To perform navigation. In “Replay Navi”, information instructing the player to press the middle is informed. In this example, as shown in FIG. 174A, the symbol combination related to the abbreviation “Replay” is displayed when the internal winning combination is “F_accurate lip” or “F_1 credible lip”, even when the center is pressed. .

  Also, in this example, when the first-stage flag conversion lottery is won and the lottery result of the second-stage flag conversion lottery is non-winning, the sub control board 72 (sub CPU 201) displays FIG. 175B. As shown in FIG. 5, navigation called “chili lip slewing navigation” is performed. It should be noted that, in the “Chilli Lip Scrolling Navi”, when the internal winning combination “F_Probable Chilli Lip” has been determined, instruction information is provided so that the player can aim for the Chile symbol by reverse pressing. On the other hand, in the “Chilli Lip Scrolling Navi”, when the internal winning combination “F_1 Chilli Lip” is determined, the player is informed of instruction information that allows the player to aim the Chile symbol by pushing forward. Then, in such “Chile Lip Rotation Navi”, as shown in FIG. 174A, when the internal winning is “F_accurate Chili Lip”, the symbol combination related to the abbreviation “Double Chile Lip” is displayed at the time of reverse pressing, In the case where the internal winning combination is “F — 1 Chilli Lip”, the symbol combination related to the abbreviation “Dual Chilli Lip” is displayed when pressed forward.

  Further, in this example, when both the first-stage and second-stage flag conversion lotteries are won, the sub control board 72 (sub CPU 201) is referred to as “chili lip uniform navigation” as shown in FIG. 175B. Navigate. It should be noted that in the “Chilli Lip Matching Navi”, when the internal winning combination “F_Challenging Chili Lip” is determined, instruction information that allows the player to aim the Chile symbol by pushing forward is notified. On the other hand, in the “Chilli Lip Uniform Navi”, when the internal winning combination “F_1 Chilli Lip” is determined, instruction information for making the player aim the Chile symbol by reverse pressing is notified. Then, in such “Chilli Lip Matching Navi”, as shown in FIG. 174A, when the internal winning is “F_accurate Chili Lip”, the symbol combination related to the abbreviation “Triple Chili Lip” is displayed at the time of forward pressing, When the internal winning combination is “F_1 correct Chile Lip”, the symbol combination related to the abbreviation “Triple Chile Lip” is displayed at the time of reverse pressing.

  In this example, the notification based on the lottery result of the flag conversion lottery described above does not affect profits (the flag conversion lottery itself affects profits, but the symbol combination displayed as a result does not affect profits. Therefore, the notification operation in this example is not performed on the main side (instruction monitor) but only on the sub side (display device 11). In addition, in this example, as described above, not only “chili lip matching navigation” but also “chili lip navigation” can be performed on the sub-side in various manners so that navigation that does not affect profits can be controlled. . As a result, the interest of the game can be improved.

[Variation 3: Another example of a bell navigation mode between flags and non-flags]
In the pachi-slot 1 of the above-described embodiment, as described above, a numerical value uniquely corresponding to the information on the reel stop operation is displayed on the instruction monitor (not shown), thereby performing notification on the main side. At this time, the correspondence relationship of the navigation data described with reference to FIGS. In the above embodiment, an example has been described in which “white 7 navigation” or “blue 7 navigation” is performed during the state between the BB flags (RT5 state), but “bell navigation” is not performed. It is not limited. In the state between the BB flags (RT5), “bell navigation” may be performed in addition to “white 7 navigation” and “blue 7 navigation”.

  In this case, the numerical values displayed on the instruction monitor may be different from each other during the BB flag state and during the non-BB flag state. Here, FIGS. 176A and 176B show a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the state between the BB flags in the third modification. 176A is a diagram showing a correspondence relationship between notification (navigation) performed on the main side and notification (navigation) performed on the sub side during the RT5 state (between the BB1 flags), and FIG. 176B is a diagram during the RT5 state. It is a figure which shows the correspondence of alerting | reporting (navigation) performed on the main side, and alerting | reporting (navigation) performed on the sub side (between BB2 flags).

  In this example, the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the non-BB flag state is the same as in the above embodiment (see FIGS. 63A and 63B). . Therefore, when “Bell Navi” is performed in the non-BB flag state, numerical values “1” to “3” (push order second instruction information) are displayed on the instruction monitor.

  In this example, as shown in FIGS. 176A and 176B, when “Bell Navi” is performed in the state between the BB flags, numerical values “12” to “14” (push order first instruction information) are displayed on the instruction monitor. The Note that the present invention is not limited to this, and the numerical value displayed on the instruction monitor can be changed as appropriate when “bell navigation” is performed in the state between the BB flags. In this example, the sub-side navigation performed using the display device 11 may be provided in common in both the BB flag state and the non-BB flag state.

[Variation 4: Another example of privilege grant]
In the pachi-slot 1 of the above-described embodiment, the notification content is controlled based on the result of the flag conversion lottery performed on the main side, and therefore the symbol combination displayed when the stop operation is performed according to the notification is different. That is, in the above-described embodiment, the example in which it is determined whether or not to grant a privilege based on the result of the flag conversion lottery performed on the main side has been described, but the present invention is not limited to this. For example, the main side (main control board 71) may be configured to give a privilege based on the actually displayed symbol combination.

  In this case, the main control board 71 (main CPU 101) gives a privilege when a predetermined symbol combination is displayed according to the notification performed according to the result of the flag conversion lottery, and when the predetermined control combination is not followed, Even if a predetermined symbol combination is displayed, it may be configured not to give a privilege. In the pachi-slot 1 of the above embodiment, the symbol combinations displayed according to the pressing order are different, but the symbol combination related to the abbreviation “triple chili lip” also when the player ignores the notification and performs the stop operation There is a possibility that a special symbol combination such as the above will be displayed. Therefore, in this example, even if a special symbol combination is displayed ignoring the notification, the privilege is granted only when the special symbol combination is displayed according to the notification without giving the privilege. May be.

[Variation 5: Another example of notification control that does not affect profit (privilege)]
In the pachi-slot 1 of the above-described modification 1 (see FIGS. 174A and 174B), whether or not to make a notification affecting the profit is determined by a notification lottery (flag conversion lottery) on the main side, and does not affect the profit. An example in which whether or not to perform notification is determined by a notification lottery on the sub-side has been described. And, as an example of the notification that does not affect the profit, an example of performing the notification for displaying the symbol combination related to the abbreviation “reach eye lip” during the precursor game has been described, but the notification that does not affect the profit is However, the present invention is not limited to this example.

  In recent pachislot machines, there is a case where the game is shifted to a state where it is easy (hard) to perform game lock depending on the order of stop operations. For example, transition to a state where it is easy to perform game lock when the order is “left, middle, right”, and transition to a state where it is difficult to perform game lock when the order is “right, middle, left” There is. In such a pachislot, it is possible to make a transition to a state where it is easy (hard) to perform the game lock by notifying the pressing order. However, in the case where whether or not to perform a game lock affects the profit, it is necessary to control this notification on the main side. In the case where whether or not to perform the game lock does not affect the profit, this notification may be controlled on the sub side.

  Further, as a case where whether or not the game lock is performed affects the profit, for example, a case where the game lottery is performed and the ART lottery is won can be considered. On the other hand, when the game lock does not affect the profit, the game lock is performed as an effect. For example, by performing frequent game locks during a precursor game where it is decided to give profits (privileges), it becomes possible to show that the profits will be given in subsequent games .

  Here, with reference to FIG. 177A and 117B, the structural example which matches the pushing order and the locked state in the modification 5 is demonstrated. Note that FIG. 177A is a diagram illustrating a correspondence relationship between the pressing order and the locked state, and FIG. 177B is a diagram illustrating a relationship between presence / absence of an influence on the profit due to the game lock and a notification mode.

  In the example shown in FIG. 177A, when the internal winning combination “F_Maintenance Lip A” is determined, if the stop operation is performed in the order of “left, middle, right”, the lock state is “0” (the state that is difficult to lock). ) To “1” (easy to lock), and when the stop operation is performed in the order of “left, right, middle”, “middle, left, right” or “middle, right, left” When the stop operation is performed in the pressing order of “right, left, middle” or “right, middle, left”, the lock state transits from “1” to “0”. In addition, when the internal winning combination “F_Maintenance Lip B” is determined, if the stop operation is performed in the order of “middle, left, right”, the lock state is changed from “0” (a state in which it is difficult to lock) to “1”. ”(A state where it is easy to lock), and when a stop operation is performed in the other pressing order, the current locked state is maintained.

  In the example shown in FIG. 117A, in order to simplify the description, an example in which the lock state is set in two stages of “0 (a state that is difficult to lock)” and “1 (a state that is easy to lock)” will be described. The present invention is not limited to this. For example, three or more lock states may be provided. Further, in this case, the lock state may not be changed one step at a time, but may be configured to change multiple steps at a time.

  In this example, as shown in FIG. 117B, when a game lock affects profits, a notification lottery on whether or not to perform notification is performed on the main (main control board 71) side, and the lottery result Based on the above, a predetermined pressing order is notified on both the main side and the sub side. On the other hand, if the game lock does not affect profits, the sub lot (sub control board 72) performs a lottery for determining whether or not to make a notification, and the sub side determines a predetermined push order based on the lottery result. Is notified.

  Note that there are pachislots in which the game lock affects the profit over the entire period of the game, and there are pachislots in which the game lock does not affect the profit over the entire period of the game. In addition, as a pachislot, there is a pachislot where the game lock affects the profit during a predetermined period of the game, but the game lock does not affect the profit during a specific period of the game. Therefore, during the period in which the game lock affects profits, a notification lottery on whether to perform notification is performed on the main side, and a predetermined push order is notified on both the main side and the sub side based on the lottery result. On the other hand, during a period when the game lock does not affect profits, a notification lottery on whether or not to perform notification is performed on the sub side, and a predetermined push order is notified on the sub side based on the lottery result. Good.

  Since the game lock is normally controlled on the main side (main control board 71), the main control board 71 has a function of changing the lock state in accordance with the pressing order shown in FIG. 117A. That is, the main control board 71 determines whether or not to perform the game lock with a probability corresponding to the lock state set by the lock state setting unit that sets the lock state based on the detected order of stop operations. It also functions as a game lock determining means determined by the above and a lock executing means for temporarily stopping the progress of the game when the game lock determining means determines that the game is locked. In addition, the main control board 71 and / or the sub-control board 72 performs a notification lottery for determining whether or not to notify the pressing order when the lock state setting means sets a lock state in which the game lock is easy (hard) to lock. It also functions as notifying means for notifying the predetermined pushing order based on the lottery means and the lottery result of the notifying lottery means.

[Modification 6: Another example of termination conditions for normal ART and CT]
The termination conditions of normal ART and CT are not limited to the examples described in the above embodiment, and any termination conditions can be adopted. For example, the number of medals awarded during normal ART or CT, the number of times a unit game is consumed during normal ART or CT, the number of information notifications that are beneficial to the player during normal ART or CT, End conditions such as the number of sets when the predetermined number of games (for example, 50 games) is one set, the continuation rate at the end of one set, and the like can be adopted.

  In addition, as a method of counting the number of medals awarded during normal ART or CT, for example, a method of counting the number of medals paid out in a unit game may be adopted, or in a unit game A method of counting the difference number (pure increase number) obtained by subtracting the bet number of the medals used in the unit game from the number of medals obtained may be employed. In addition, as a method for counting the number of medals granted during normal ART or CT, a method of calculating based on the actually increased medals (calculation based on actual values) may be adopted, or whether the number actually increased Regardless of whether or not, a method of calculating based on the number of medals scheduled to increase when the notification is followed (calculation based on an ideal value) may be employed.

  Further, a configuration in which the number of awarded medals is not increased depending on the type of the internal winning combination, that is, a configuration in which the number of medals or the difference number as an end condition of the number of awarded medals is not counted may be employed. . For example, even if a part of a combination (rare combination) with a low probability of being determined as an internal winning combination or a combination of switching between display / non-display of the symbol combination depending on the timing of the stop operation is determined as an internal winning combination The number of awarded medals may not be increased / decreased (counted).

[Modification 7: Others]
The content of the notification normally performed during ART or CT is not limited to the above-described example, but is arbitrary. For example, the stop operation order (pushing order) in which a special symbol combination that is advantageous to the player is displayed may be notified, or the timing of the stop operation necessary to display the symbol combination ( You may make it alert | report the symbol which should aim.

  As an advantageous state for the player, the winning probability of the internal winning combination relating to the re-game does not change (or changes within a range not affecting the game performance), but the mode of the stop operation which is advantageous for the player is It may be a gaming state in which the function to notify, that is, the AT function is activated. Further, as a state advantageous to the player, a re-game high probability state (replay time) in which the winning probability of the internal winning combination relating to re-game is activated, and a mode of a stop operation advantageous to the player is notified. It may be a gaming state in which the function is activated, that is, the ART function is activated.

  Further, in the pachislot machine 1 of the above embodiment, an example in which various display screens are displayed on the sub display device 18 provided on the left side of the reel display window 4 as viewed from the player side has been described, but the present invention is not limited to this. . For example, another sub display device may be provided on the right side of the reel display window 4 when viewed from the player side, and various display screens may be displayed on this sub display device. In this case, the touch sensor is provided on the display surface of the sub display device provided on the right side of the reel display window 4, and the display screen of the sub display device is switched based on the touch input information output from the touch sensor. It may be.

  Moreover, in the said embodiment and various modifications, the pachislot was mentioned as an example as a game machine, However, This invention is not limited to this. Features other than the features peculiar to the pachislot machine 1 such as features relating to reel control and features relating to setting changes and confirmation according to the present invention can also be applied to a gaming machine called “pachinko”, and similar effects can be obtained. For example, checksum generation and determination processing, various processing using an instruction code dedicated to the main CPU 101 (address designation processing using a Q register, soft timer update processing, 7 segment LED drive processing, communication data generation and storage processing, etc. ), Features such as various processes using the non-standard ROM area and the non-standard RAM area are also applicable to “pachinko”.

<Various functions of the main control board and sub-control board>
The embodiment and various modifications of the pachislot machine 1 according to the present invention have been described above. Here, various functions of the main control board 71 (main control circuit 90, main CPU 101) and the sub control board 72 (sub control circuit 200, sub CPU 201) of the pachislot machine 1 according to the present invention will be described together.

  The main control board 71 is connected to the start switch 79 and the stop switch board 80, and controls the progress of the game shown in FIG. Therefore, the main control board 72 functions as start operation detection means, symbol variation means, internal winning combination determination means, stop operation detection means, reel stop control means (stop control means), and winning determination means.

  The main control board 71 performs a flag conversion lottery when an internal winning combination “F_accurate lipping” or “F_1 accurate lipping” is determined during normal ART, and the result of this flag conversion lottery and other internal winning combinations When a CT lottery based on the above is won, a CT for extending the duration of the normal ART is started. Therefore, the main control board 71 also functions as conversion lottery means and extra game start means.

  In addition, the main control board 71 adds (extends) the number of ART games indicating the duration of the normal ART according to the internal winning combination during CT. Specifically, when the internal winning combination corresponding to the sub flag “cactus”, “weak cherry” or “strong cherry” is determined, the main control board 71 adds the number of normal ART ART games to a predetermined amount, When the internal winning combination corresponding to the sub-flag “triple chilli lip (triple chilli lip A or triple chilli lip B)” is determined, the number of normal ART ART games is added by a specific amount. Further, the main control board 71 adds 1 when the number of times of adding the number of ART games based on the sub-flag “triple chip” exceeds 9 times, which is the basic game number of one set of CT. Increase the amount added per time. Therefore, the main control board 71 also functions as an addition control means.

  Further, the main control board 71 counts the number of games in which the number of ART games is not added during the CT using the CT game number counter, and terminates the CT when the CT game number counter counts “8”. At this time, if the sub flag EX “triple reel” is won (that is, the flag conversion lottery is won), the main control board 71 resets the CT game of one set eight times (eight games) (in the CT game number counter). Reset the value to the initial value). Therefore, the main control board 71 also functions as a counting means and an extra game ending means.

  Further, when the bonus combination (internal winning combination “F_BB1”, “F_BB2”) is determined as the internal winning combination, the main control board 71 shifts the gaming state to the state between the BB flags (RT5 state) and the BB flag. In the interim state, the bonus combination is carried over as an internal winning combination until the bonus is activated (until the bonus combination is won). Therefore, the main control board 71 also functions as a bonus carry-over means. When the bonus combination is won in the state between the BB flags, the main control board 71 operates the bonus and shifts the gaming state to the bonus state. Therefore, the main control board 71 also functions as bonus starting means and advantageous game means.

  Further, as shown in FIG. 25, in the state between the BB flags, the main control board 71 overlaps the bonus combination and a predetermined internal winning fixed combination (“out”, “F_special 1” to “F_special 3”). If it is determined, stop control is performed so that the symbol combination (“C_BB1”, “C_BB2”) related to the bonus combination can be displayed, and an internal winning combination other than the bonus combination and the predetermined internal winning combination is performed. Is determined to overlap, the stop control is performed so that the symbol combination related to the bonus combination cannot be displayed. When the symbol combination related to the bonus combination can be displayed during the state between the BB flags, the main control board 71 controls the instruction monitor (not shown) of the information display 6 to win the bonus combination. The numerical value “10” or “11” uniquely indicating the mode of the stop operation is displayed to notify the bonus instruction information. On the other hand, when the symbol combination related to the bonus combination cannot be displayed during the state between the BB flags, the main control board 71 does not display (notify) the numerical values “10” and “11” on the instruction monitor. Therefore, the main control board 71 and the instruction monitor of the information display 6 function as instruction information notification means.

  At this time, the main control board 71 notifies the numerical value “10” or “11” via the instruction monitor only after the bonus notification. Specifically, when the main control board 71 determines that the bonus combination is an internal winning combination without carrying over the bonus combination, it counts the number of subsequent games, and the bonus after the count result reaches a predetermined number. When a combination and a predetermined internal winning combination (“out of”, “F_special 1” to “F_special 3”) are determined to overlap, a numerical value “10” or “11” is notified via the instruction monitor. . Therefore, the main control board 71 also functions as a counting means for counting the number of unit games since the bonus combination is determined as the internal winning combination.

  The sub control board 72 manages the game history based on the various command data received from the main control board 71, and accepts the registration of the player who performs the game when accepting the registration operation from the player. Therefore, the sub control board 72 functions as a history management unit and a registration receiving unit.

  In addition, the pachislot machine 1 according to the present invention is provided separately from the display device 11 that produces effects according to the progress of the game and the display device 11, and includes a top screen 221, game information screens 223, 224, 225, and the like. The sub-display device 18 for displaying the display screen and the touch sensor 19 provided on the display unit of the sub-display device 18. The sub-control board 72 controls the operations of the display device 11 and the sub-display device 18. To do. Specifically, the sub control board 72 controls the sub display device 18 so that the game information screens 223, 224, and 225 can be displayed on the sub display device 18 when registration of the player is accepted. When the registration of the player is not accepted, control is performed so that the game information screens 223, 224, and 225 cannot be displayed on the sub display device 18. Therefore, the sub control board 72 also functions as a control means.

  The main control board 71 also functions as a privilege granting means because it grants various privileges according to the game results. Specifically, the main control board 71 gives a privilege according to the symbol combination displayed along the effective line.

  For example, in the game in which the internal winning combination “F_3 selection bell_1st” is determined, when the symbol combination related to the abbreviation “Bell” is displayed on the active line, the main control board 71 gives nine medals, When the symbol combination related to the abbreviation “bell spill” is displayed on the active line, the main control board 71 gives 0 medals. In addition, for example, in a game in which the internal winning combination “F_Challenging Lip” is determined, when the symbol combination related to the abbreviation “Triple Chile Lip” or the abbreviation “Replay” is displayed on the active line, the main control board 71 Grants the same privilege of replay activation. Moreover, the main control board 71 gives a privilege not based on the symbol combination displayed along the effective line but also based on the result of the flag conversion lottery. For example, the main control board 71 performs a flag conversion lottery when the internal winning combination “F_Challenging Lip” is determined, and gives a privilege such as winning a CT lottery when winning the flag conversion lottery.

  In addition, the sub control board 72 performs an effect corresponding to the mode of the stop operation via the display device 11. Therefore, the sub control board 72 and the display device 11 also function as effect execution means. At this time, if the privilege to be given differs depending on the symbol combination displayed along the active line, the main control board 71 provides information uniquely indicating the mode of the stop operation advantageous to the player via the instruction monitor. When the privilege provided by the symbol combination displayed along the active line is the same, the mode of the stop operation advantageous to the player is not notified. On the other hand, the sub-control board 72 executes an effect indicating the order of the stop operation regardless of whether the privilege to be given by the displayed symbol combination is the same or different.

  In addition, the main control board 71 performs a CT lottery to determine whether or not to start CT. When a CT lottery is won, the main control board 71 starts CT after, for example, a predetermined number of precursor games have been won. Therefore, the main control board 71 also functions as an advantageous state lottery means and an advantageous state start means. Further, at this time, if the internal winning combination “F_Challenging Lip” or “F_1 Chanting Lip” is determined during the CT sign game, the sub-control board 72 performs a flag conversion lottery on the sub side. Therefore, the sub control board 72 also functions as a notification lottery means.

  Further, in the pachislot machine 1 according to the present invention, the main control board 71 gives a privilege based on the result of the flag conversion lottery, and the main control board 71 and the sub control board 72 are connected via the instruction monitor and the display device 11. Announces the pressing order. Therefore, the main control board 71 also functions as privilege provision means. Further, the main control board 71, the sub control board 72, the instruction monitor and the display device 11 also function as notification means.

  Furthermore, in the pachislot machine 1 according to the present invention, the main control board 71 (main control circuit 90, main CPU 101) performs various control processes over the entire game operation. Therefore, the main control board 71 also functions as a calculation control means. Further, in the pachislot machine 1 according to the present invention, the main control board 71 (main control circuit 90, main CPU 101) also functions as means for executing various processes described below.

  The main control board 71 (the main control circuit 90 and the main CPU 101) performs a checksum generation process (see FIG. 77) when a power interruption occurs (see FIGS. 77 and 80). Therefore, the main control board 71 also functions as sum value calculation means, sum value subtraction means, and sum value determination means.

  The main control board 71 (main control circuit 90, main CPU 101) performs a winning search process (see FIG. 145). Therefore, the main control board 71 also functions as a privilege grant determination unit and a winning combination determining unit.

  The main control board 71 (main control circuit 90, main CPU 101) performs communication data transmission processing (S904 during interrupt processing in FIG. 158). Therefore, the main control board 71 also functions as data transmission means.

  The main control board 71 (main control circuit 90, main CPU 101) performs a setting change confirmation process (see FIG. 68). Therefore, the main control board 71 also functions as a setting change confirmation unit, a start command generation unit, and an end command generation unit.

  The main control board 71 (main control circuit 90, main CPU 101) performs communication data storage processing (see FIG. 72) and communication data pointer update processing (see FIG. 74). Therefore, the main control board 71 also functions as communication data generation means and communication data generation storage means.

  The main control board 71 (main control circuit 90, main CPU 101) performs 7-segment LED drive processing (see FIG. 159). Therefore, the main control board 71 also functions as 7-segment LED drive means and LED drive control means.

  The main control board 71 (main control circuit 90, main CPU 101) performs a game return process (see FIG. 68). Therefore, the main control board 71 also functions as a game return means.

  The main control board 71 (main control circuit 90, main CPU 101) performs medal acceptance / start check processing (see FIG. 83). Therefore, the main control board 71 also functions as a game start determination unit and a setting confirmation unit (S233).

  The main control board 71 (main control circuit 90, main CPU 101) performs a medal insertion check process (see FIG. 87). Therefore, the main control board 71 also functions as game medium reception state determination means (S255 to S258).

  The main control board 71 (main control circuit 90, main CPU 101) repeatedly executes the interrupt process (see FIG. 158) at a cycle of 1.1172 msec. Therefore, the main control board 71 also functions as interrupt processing execution means and fixed cycle processing means.

  The main control board 71 (main control circuit 90, main CPU 101) performs power-on processing (see FIG. 64). Therefore, the main control board 71 also functions as a power recovery process execution means.

  The main control board 71 (main control circuit 90, main CPU 101) performs an internal lottery process (see FIG. 92). Therefore, the main control board 71 also functions as internal lottery means.

  The main control board 71 (main control circuit 90, main CPU 101) performs symbol setting processing (see FIG. 97). Therefore, the main control board 71 includes an internal winning combination generating means (S321), a flag table expanding means, a winning flag table expanding means (S324), a flag storage area specifying means, a winning flag storage area specifying means (S329), and flag data. It also functions as storage means and winning flag data storage means (S330).

  The main control board 71 (main control circuit 90, main CPU 101) performs symbol code acquisition processing (see FIG. 28). Therefore, the main control board 71 also functions as a winning flag storage area designating means (S648) and a symbol code storage area setting means (S650).

  The main control board 71 (main control circuit 90, main CPU 101) performs a reel stop control process (see FIG. 139). Therefore, the main control board 71 also functions as stop operation detection result acquisition means (S714) and stop control data storage area setting means (source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139). .

  The main control board 71 (the main control circuit 90, the main CPU 101) performs a pull-in priority acquisition process (see FIGS. 134 and 135). Therefore, the main control board 71 includes priority stop symbol determination means, arbitrary combination handling means (S680 to S683), winning flag storage area designation means (S686), winning flag storage area designation means (S686), logical product calculation means. It also functions as (S686) and priority data table acquisition means (S687).

  The main control board 71 (main control circuit 90, main CPU 101) performs illegal hit check processing (see FIG. 148). Therefore, the main control board 71 also functions as error detection means, error processing means, winning flag storage area designation means (S781), AND operation means (S784), and error determination means (S785).

  The main control board 71 (main control circuit 90, main CPU 101) performs a winning check / medal payout process (see FIG. 150). Therefore, the main control board 71 also functions as a game medium payout means, a game medium addition means (S805), a payout end determination means (S807), and a weight generation means (S808).

  The main control board 71 (main control circuit 90, main CPU 101) performs CT lottery processing during CT (see FIG. 119). Therefore, the main control board 71 also functions as privilege provision determining means.

  The main control board 71 (main control circuit 90, main CPU 101) performs sub-flag conversion processing (see FIG. 105). Therefore, the main control board 71 also functions as the first sub flag conversion means.

  The main control board 71 (main control circuit 90, main CPU 101) performs flag conversion processing (see FIG. 111). Therefore, the main control board 71 also functions as a second sub-flag conversion unit.

<Appendix (summary of the present invention)>
[First gaming machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine that obtains a checksum of data stored in a RAM at the time of power interruption and performs a determination process of the checksum obtained at the time of power interruption at power recovery is known ( For example, refer to JP2009-011375). In the gaming machine disclosed in Japanese Patent Application Laid-Open No. 2009-011375, in the checksum determination process at the time of power recovery, an error notification is performed when the checksum calculated at the time of power recovery does not match the checksum calculated at the time of power interruption.

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and there is a demand for capacity reduction of processing programs and tables other than the game management managed by the main control circuit.

  The present invention has been made to solve the first problem, and a first object of the present invention is to reduce the capacity of processing programs and tables other than the game management managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM of a main control circuit and enhancing the gameability by utilizing the free space of the ROM for the increased capacity.

  In order to solve the first problem, the present invention provides a first gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Power supply means for supplying a power supply voltage (for example, the power supply substrate 53b and the switching regulator 94);
Starting means for outputting a starting signal to the arithmetic processing means when the power supply voltage exceeds a predetermined starting voltage value (for example, 10 V) (for example, reset signal output processing of the power management circuit 93);
When the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V), a power failure means for outputting a power failure signal to the arithmetic processing means (for example, output of a power interruption detection signal of the power management circuit 93) Processing), and
The arithmetic processing means includes:
A flag register (eg, flag register F) that stores data corresponding to the result of the arithmetic processing;
When the power failure means outputs the power failure signal, the sum value is calculated by accumulating all the information stored in the predetermined storage area (for example, the game RAM area) in the second storage means. Sum value calculation means (for example, checksum generation processing);
Sum value that sequentially subtracts the information stored in the predetermined storage area from the sum value generated by the sum value calculation means when the power interruption occurred most recently, when the activation means outputs the activation signal. Subtraction means (for example, S122 to S131 during the sum check process);
When the subtraction processing by the sum value subtracting unit is completed for all information stored in the predetermined storage area, the subtraction result set in the predetermined bit area (for example, zero flag) in the flag register is displayed. Summing value determining means (for example, S134 during the sum check process) for determining whether or not an abnormality has occurred based on the corresponding data.

In the first gaming machine of the present invention, the sum value calculation means executes a specific instruction (for example, a POP instruction) when adding the information stored in the predetermined storage area, Obtain and add 2 bytes of information stored in succession, update the information of the read start address of the information by 2 bytes,
The sum value subtracting means executes the specific instruction when subtracting the information stored in the predetermined storage area from the sum value generated at the time of occurrence of power interruption, thereby continuously storing 2 While acquiring and subtracting bytes of information, the information of the read start address of the information may be updated by 2 bytes.

Further, in the first gaming machine of the present invention, the arithmetic processing means has a stack pointer capable of setting an address of the predetermined storage area of the second storage means,
The specific instruction executed when the sum value calculation means adds the information stored in the predetermined storage area may be a dedicated instruction (for example, a POP instruction) for operating the stack pointer. Good.

  According to the first gaming machine of the present invention configured as described above, the capacity of processing programs and tables other than gaming is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. The playability can be improved by utilizing the free space in the ROM for the capacity.

[Second to fifth gaming machines]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine in which a main controller that processes numerical data by using a stack pointer as an operation instruction is mounted (see, for example, JP-A-2005-237737) ).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the second problem, and a second object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the second problem, the present invention provides a second gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means executes a predetermined instruction (for example, a “BITQ” instruction, a “SETQ” instruction, an “LDQ” instruction, etc.) capable of performing address designation in the second storage means using the extension register. A gaming machine characterized by being capable.

  In the second gaming machine of the present invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  In order to solve the second problem, the present invention provides a third gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means includes:
In the process of checking the stop state of the display column,
A predetermined read instruction (for example, an “LDQ” instruction) capable of performing addressing in the second storage means by using the extension register is executed, and the predetermined stored in the second storage means Read the information indicating the status of the variable display in the display column,
Next, a predetermined OR operation instruction (for example, an “ORQ” instruction) that can perform addressing in the second storage means is executed using the extension register, and is stored in the second storage means Reading information indicating the state of the variable display of the other one display column, and performing an OR operation on the information and information indicating the state of the variable display of the predetermined display column,
Thereafter, the execution of the predetermined logical sum operation instruction is repeated, and the logical sum operation of the result of the logical sum operation and the information indicating the change display state of each remaining display column is repeated, and the logical sum for all the display columns A game machine characterized by determining whether or not all display columns are in a stopped state based on a result of an arithmetic sum operation obtained when the operation is completed.

  In the third gaming machine of the present invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  In order to solve the second problem, the present invention provides a fourth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the internal winning combination determining operation by the internal winning combination determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The internal winning combination determined by the internal winning combination determining means includes an internal winning combination for each setting whose winning probability changes in accordance with a setting value for adjusting an expected value for determining an internal winning combination related to the granting of a privilege. Is provided,
The arithmetic processing means includes:
In the process of determining the internal winning combination,
By setting a predetermined addition instruction (for example, “ADDQ” instruction) that can perform address designation in the second storage means using the extension register, setting of the internal winning combination by setting to be a lottery target Add the current setting value to the top address of the area where the lottery value for each value is stored, and specify the address where the lottery value of the internal winning combination for each setting associated with the current setting value is stored, A gaming machine characterized by obtaining the lottery value.

  In the fourth gaming machine of the present invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  In order to solve the second problem, the present invention provides a fifth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the variable display of the plurality of display columns is stopped by the stop control means, the symbol corresponding to the internal winning combination relating to the payout of the game medium on the determination line set across the plurality of display columns Privilege grant determination means (for example, winning search process) for determining whether or not the combination of
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the privilege grant determination means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
The arithmetic processing means includes:
In the process of determining whether or not the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
The game that can be given when a predetermined read command (for example, “LDIN” command) is executed and a combination of symbols corresponding to an internal winning combination related to the payout of the game media is stopped and displayed on the determination line It is characterized by simultaneously obtaining data on the number of paid-out media and determination data indicating the type of symbol combination corresponding to the internal winning combination related to the payout of the game media, which is associated with the data on the paid-out amount To play.

In the fifth gaming machine of the present invention, the arithmetic processing means is
In the process of determining whether or not the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
A predetermined determination instruction (for example, a “JSLAA” instruction) that can execute a determination instruction, a process jump destination address designation instruction, and a process jump operation instruction with a single instruction is executed, and an internal portion related to payout of the game medium It may be determined whether or not the symbol combination corresponding to the winning combination has been stopped.

  According to the second to fifth gaming machines of the present invention configured as described above, the capacity of processing programs and tables managed by the main control circuit is reduced, and the free capacity of the ROM (first storage means) of the main control circuit is reduced. It is possible to increase the playability by utilizing the ROM free area corresponding to the increased capacity.

[Sixth and seventh gaming machines]
Conventionally, in the gaming machine having the above-described configuration, when an abnormality occurs in the data stored in the RAM of the main control unit, it is controlled to a RAM abnormality error state, and the progress of the game is disabled. When a setting value is newly selected and set based on a setting change operation, a gaming machine has been proposed in which the game progress disabled state is canceled and the game progress enabled state ( For example, refer to JP 2007-209810 A).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the above third problem, and a third object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the third problem, the present invention provides a sixth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Data transmission means for transmitting command data related to the gaming operation (for example, S904 (communication data transmission processing) during interrupt processing);
A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for determining an internal winning combination related to the granting of a privilege;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the setting value changing operation or the confirming operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A start command generation means for generating first command data at the start of the setting value change process or the setting value confirmation process (for example, S43 during the setting change confirmation process);
An end-time command generation means for generating second command data at the end of the setting value change process or the setting value confirmation process (for example, S57 during the setting change confirmation process);
The first command data generation processing executed by the start time command generation means and the second command data generation processing executed by the end time command generation means are shared. A featured gaming machine.

In the sixth gaming machine of the present invention, the arithmetic processing means has a general-purpose register for storing data when the arithmetic processing means executes the arithmetic processing,
The arithmetic processing means includes:
When generating the first command data, a first value (for example, “005H”) is set in a predetermined register (for example, the L register) of the general-purpose register, and the generation process is executed.
When generating the second command data, a second value (for example, “004H”) may be set in a predetermined register of the general-purpose register, and the generation process may be executed.

  In order to solve the third problem, the present invention provides a seventh gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Data transmission means for transmitting command data related to the gaming operation (for example, S904 (communication data transmission processing) during interrupt processing);
Communication data generation means for creating the command data (for example, setting change command generation storage processing and communication data storage processing);
A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for determining an internal winning combination related to the granting of a privilege;
Arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling command data generation operation by the communication data generation means and setting value change operation or confirmation operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
At the start of the setting value change process or the setting value confirmation process, start command generation means for generating start command data (for example, S43 during the setting change confirmation process);
End-time command generation means (for example, S57 during the setting change confirmation process) that generates end-time command data at the end of the setting value change process or the setting value confirmation process;
The start command data generation process executed by the start command generation means and the end command data generation process executed by the end command generation means are shared,
The arithmetic processing means has a plurality of general purpose registers in which a plurality of types of data are respectively stored when the arithmetic processing is executed by the arithmetic processing means,
The arithmetic processing means includes:
In the command data generation process,
Among a plurality of types of communication parameters constituting the command data, a communication parameter to be used is set in a corresponding general-purpose register among the plurality of general-purpose registers,
Storing the communication parameters used in the general-purpose register in a predetermined storage area (for example, a communication data temporary storage area) in the second storage unit;
If there is a communication parameter that is not used among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter when the command data is generated is used as the communication parameter. In the storage area of
A gaming machine, wherein a sum value of the command data is generated based on data stored in the general-purpose register associated with a communication parameter.

  In the seventh gaming machine of the present invention, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. By doing so, a sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

  According to the sixth and seventh gaming machines of the present invention configured as described above, the capacity of the processing program and table managed by the main control circuit is reduced to increase the ROM capacity of the main control circuit, and the increased capacity It is possible to improve the playability by using the free space of the ROM.

[Eighth and ninth gaming machines]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine that transmits a command from a game control board (main control circuit) to an effect control board (sub control circuit) is known (see, for example, JP-A-2002-360766). ).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the above fourth problem, and a fourth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the fourth problem, the present invention provides an eighth gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Data transmission means (for example, S904 (communication data transmission processing) during interrupt processing) for transmitting communication data related to gaming operations;
Communication data generation and storage means (for example, communication data storage processing and communication) for generating the communication data and storing the generated communication data in a communication data storage area provided in a predetermined address range in the second storage means Data pointer update processing), and
The communication data generation storage means
When the communication data is sequentially stored in the communication data storage area from the storage area of the start address of the predetermined address range toward the storage area of the tail address, an update instruction, an upper limit determination instruction, and a determination branch instruction are combined. By executing a predetermined update instruction (for example, “ICPLD” instruction) that can be executed by one instruction, the current value of the communication data pointer, which is a parameter for addressing in the communication data storage area, and the last address And the communication data pointer is added and updated if the current communication data pointer is less than the upper limit value, and the current communication data pointer is updated to the upper limit value. If it is above, the communication data pointer is below the communication data pointer corresponding to the head address. Gaming machine and changing the value.

  In the eighth gaming machine of the present invention, the communication data generation and storage means may change the communication data storage area when the communication data pointer is changed to a lower limit value of the communication data pointer corresponding to the head address. The communication data stored in the network may be invalidated.

  In order to solve the fourth problem, the present invention provides a ninth gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
In a counting process (for example, a medal payout number check process) of a predetermined data value related to the progress of a game operation,
When updating the value of the predetermined data, by executing a predetermined update instruction (for example, “DCPLD” instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, The predetermined data value is compared with the lower limit value of the predetermined data value, and if the current predetermined data value is greater than the lower limit value of the predetermined data value, the predetermined data value The game machine is characterized in that if the current value of the predetermined data is equal to or lower than the lower limit value of the predetermined data value, the predetermined data value is held at the lower limit value.

  In the ninth gaming machine of the present invention, the predetermined data may be the number of payouts of the game medium.

  According to the eighth and ninth gaming machines of the present invention configured as described above, the capacity of processing programs and tables managed by the main control circuit is reduced, and the free capacity of the ROM (first storage means) of the main control circuit is reduced. It is possible to increase the playability by utilizing the ROM free area corresponding to the increased capacity.

[Tenth gaming machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine controlled by software timer subtraction processing is known (for example, see Japanese Patent Application Laid-Open No. 2004-041261).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the fifth problem, and a fifth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the fifth problem, the present invention provides a tenth gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
In the count process (for example, timer update process) of the timer value of the soft timer,
By executing a predetermined update instruction (for example, a “DCPWLD” instruction) that can execute an update instruction, a lower limit determination instruction, and a determination branch instruction in one instruction, the current timer value of the soft timer and the lower limit of the timer value And if the current timer value of the soft timer is greater than the lower limit value, the timer value of the soft timer is subtracted and updated, and if the current timer value of the soft timer is less than or equal to the lower limit value, The gaming machine is characterized in that the timer value of the soft timer is held at the lower limit value.

  In the tenth gaming machine of the present invention, the soft timer may be a 2-byte soft timer.

Further, in the tenth gaming machine of the present invention, the arithmetic processing means has a fixed period processing means (for example, an interrupt process repeatedly executed at a period of 1.1172 msec) for performing a process at a constant period,
The counting process of the timer value by the soft timer is realized by the periodic processing means,
The elapsed time of the soft timer may be determined based on a cycle in which the periodic processing unit performs processing and the timer value.

  Further, in the tenth gaming machine of the present invention, the processing by the fixed cycle processing means is executed based on an interrupt signal generated by a timer function (for example, timer circuit 113) built in the arithmetic processing means. You may make it do.

  According to the tenth gaming machine of the present invention configured as described above, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, It is possible to provide a gaming machine capable of enhancing the gameability by using the ROM free space for the increased capacity.

[Eleventh and twelfth gaming machines]
Conventionally, in the gaming machine having the above-described configuration, there is known a gaming machine that displays an internal lottery result with a 7-segment LED under the control of a main control circuit (see, for example, Japanese Patent Application Laid-Open No. 2008-237337).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the sixth problem, and a sixth object of the present invention is to reduce the capacity of a processing program or a table managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the sixth problem, the present invention provides an eleventh gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
A plurality of 7-segment LEDs for notifying specific information about the game;
7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, 7-segment LED drive processing);
LED drive control means for controlling the drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The LED drive control means includes
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (for example, “LDW” command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by that.

Further, in the eleventh gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a constant cycle,
The periodic processing means counts the number of executions of processing by the periodic processing means,
When the counted value is an even number, the control process by the LED drive control means may be executed.

  In order to solve the sixth problem, the present invention provides a twelfth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
An indication display (for example, an indication monitor) including a plurality of 7-segment LEDs for informing information related to a stop operation of the variable display of the plurality of display rows;
7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, 7-segment LED drive processing);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (for example, “LDW” command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by that.

In the twelfth gaming machine of the present invention, the arithmetic processing means is
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) that stores data at the time of execution of the arithmetic processing by the arithmetic processing means, and that can specify a part of the address in the second storage means by the stored data;
The arithmetic processing means executes a predetermined read instruction (for example, “LDQ” instruction) capable of performing address designation in the second storage means by using the extension register, thereby causing the second storage means to And an address of a stop operation instruction information storage area (for example, a navigation data storage area) that stores information related to the stop operation of the variable display of the plurality of display columns, and Information regarding the stop operation may be stored in the stop operation instruction information storage area.

  According to the eleventh and twelfth gaming machines of the present invention configured as described above, the capacity of processing programs and tables managed by the main control circuit is reduced, and the free capacity of the ROM (first storage means) of the main control circuit is reduced. It is possible to increase the playability by utilizing the ROM free area corresponding to the increased capacity.

[13th game machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine in which a gaming control board (main control board) controls a reel unit is known (see, for example, JP 2012-034914 A).

  By the way, in the rotation control of the reel (rotor), the lack of a sense of stability of the rotation operation of the reel may cause discomfort for the player (especially an expert), and the interest of the game may be cut off from the discomfort. There is. In this case, it is disadvantageous for the game store and may affect the sales of the game machine itself.

  The present invention has been made to solve the seventh problem described above, and a seventh object of the present invention is to suppress the lack of a sense of stability of the rotation operation of the reel and to prevent the player from feeling uncomfortable. It is providing the game machine which can be made to do.

  In order to solve the seventh problem, the present invention provides a thirteenth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
A setting switch (for example, a setting key-type switch 54) for initializing a predetermined area of the second storage means,
The arithmetic processing means includes:
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the power is restored, the input state of the input port and the output state of the output port at the time of power failure are set, and when the display row is fluctuating at the time of power failure, it is stored in the second storage means The game return that clears the variation control management information (for example, reel control management information) of the display row at the time of occurrence of power interruption, and sets information instructing the start of variation of the display row to the variation control management information of the display row And a means (for example, a game return process).

In the thirteenth gaming machine of the present invention, the arithmetic processing means is
When the setting switch is in the off state, the processing by the game return means is executed,
When the setting switch is in the ON state, a predetermined area of the second storage unit may be initialized without executing the process by the game return unit.

  According to the thirteenth gaming machine of the present invention having the above-described configuration, it is possible to suppress the lack of stability of the reel rotation operation (display row variation display operation) and to prevent the player from feeling uncomfortable. .

[14th game machine]
2. Description of the Related Art Conventionally, in gaming machines having the above-described configuration, gaming machines that can display setting values (1 to 6) by operating a setting change switch are known (for example, Japanese Patent Application Laid-Open No. 2008-245704 and Japanese Patent Application Laid-Open No. 2008-245704). 2013-042870).

  By the way, conventionally, while a game is being played in a game state advantageous to the player, such as during a bonus game or an ART game, a gaming machine in which the set value cannot be confirmed is mainly used. In such a gaming machine, if a bonus game or an ART game is started immediately after an illegal act called “Goto”, the illegal act cannot be confirmed, and there is a possibility of giving a disadvantage to the game store. is there.

  The present invention has been made to solve the above eighth problem, and the eighth object of the present invention is to provide a game state that is advantageous to the player even during the game. It is an object of the present invention to provide a gaming machine capable of confirming information such as a set value and suppressing illegal acts such as goto.

  In order to solve the eighth problem, the present invention provides a fourteenth gaming machine having the following configuration.

A setting switch arranged at a predetermined position inside the gaming machine body;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Based on the internal winning combination determined by the internal winning combination determining means, advantageous gaming means (for example, a bonus game described later) for executing a gaming state advantageous to the player;
A setting change confirmation means (for example, S233 during medal acceptance / start check processing) capable of changing or confirming a setting value related to the probability that an internal winning combination is determined according to the operation of the setting switch;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Game start determining means (for example, medal reception / start check processing) for determining whether or not the game can be started,
The setting change confirmation means can change a setting value related to a probability that an internal winning combination is determined according to an operation of the setting switch when power is turned on,
When it is determined by the game start determining means that the game can be started and the setting switch is operated, a setting value relating to the probability that an internal winning combination is determined regardless of the gaming state is confirmed by the setting change. A gaming machine characterized by being able to be confirmed by processing by means.

  Further, in the fourteenth gaming machine of the present invention, the setting change confirmation means, when the gaming machine is powered on while the setting switch is operated, a predetermined storage area of the second storage means. May be initialized, the set value may be changed, and the changed set value may be stored in the second storage means.

  According to the fourteenth gaming machine of the present invention configured as described above, even when a game is being played in a gaming state advantageous to the player, such as during a bonus game or an ART game, Information can be confirmed and fraudulent acts such as goto can be suppressed.

[15th and 16th gaming machines]
Conventionally, a gaming machine having a display device for displaying the number of inserted medals in the gaming machine having the above-described configuration is known (for example, see JP-A-1999-178983).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the ninth problem, and a ninth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the ninth problem, the present invention provides a fifteenth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Game medium detecting means (for example, medal sensor) for detecting the reception state of the game medium (for example, medal sensor input state);
Based on the reception state of the game medium detected in the previous process, whether or not the change state of the current reception state of the game medium detected by the game medium detection means is normal is determined by calculation processing. A gaming medium reception state determining means (for example, S255 to S258 during the medal insertion check process).

  In the fifteenth gaming machine of the present invention, the game medium reception state determination means is a normal value of the reception state of the game medium that can be detected in the current process based on the reception state of the game medium detected in the previous process. May be calculated by a logical operation, and the normal value may be compared with the current reception state of the game medium to determine whether or not the change state of the reception state of the game medium is normal. .

  In the fifteenth gaming machine of the present invention, the game medium reception state determination means determines whether the change state of the reception state of the game medium is normal or not based on 2 bits in 1-byte information. You may do it.

  In order to solve the ninth problem, the present invention provides a sixteenth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Display means (for example, a first LED to a third LED) for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media;
Arithmetic processing means (for example, main CPU 101, medal insertion processing) for performing arithmetic processing for controlling the notification operation by the display means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Lighting control data for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media is generated by logical operation processing based on the number of inserted game media. To play.

  In the sixteenth gaming machine of the present invention, in the logical operation process, the lighting control data of the game medium may be generated from 3-bit data of information in one byte.

  According to the fifteenth and sixteenth game machines of the present invention configured as described above, the capacity of the processing program and table managed by the main control circuit is reduced to increase the ROM capacity of the main control circuit, and the increased capacity It is possible to improve the playability by using the free space of the ROM.

[17th and 18th game machines]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine in which a main board (main control board) and a sub board (sub control board) are connected by communication and a command is transmitted from the main board to the sub board is known. (For example, see Japanese Patent No. 5725590).

  By the way, conventionally, communication between the main control board that performs control related to the game and the sub control board that performs control related to the effect is one-way communication from the main control board to the sub control board. There is a large gap between the start time of the main control board and that of the sub control board. Therefore, there is a possibility that the communication connection between the main control board and the sub-control board when the power is turned on becomes unstable.

  The present invention has been made to solve the tenth problem, and a tenth object of the present invention is to provide a main control board (main control means) and a sub control board (sub control means) at the time of power-on. It is to provide a gaming machine capable of stably operating communication between the two.

  In order to solve the tenth problem, the present invention provides a seventeenth gaming machine having the following configuration.

Comprising main control means (for example, main control circuit 90) for transmitting communication data relating to gaming operations;
The main control means includes
During the control process by the main control means, an interrupt process is executed at a predetermined cycle, and when there is no communication data related to a gaming operation at the time of executing the interrupt process, an interrupt process execution means for transmitting a no-operation command (for example, , Interrupt processing)
Power recovery processing execution means (for example, power-on processing) for executing a predetermined power recovery processing at the time of power recovery,
The power recovery process execution means waits until the interrupt process execution means can execute the interrupt process after starting the power recovery process (for example, S7 and S8 during the power-on process). Done
The game machine according to claim 1, wherein the interrupt process execution means executes the interrupt process and transmits the no-operation command to the sub-control means at the end of the standby by the power recovery process execution means.

In the seventeenth gaming machine of the present invention, the main control means is
A timer circuit (for example, timer circuit 113) for measuring the predetermined period;
An interrupt circuit (for example, interrupt controller 112) that generates an interrupt signal for executing the interrupt processing based on a timeout signal of the timer circuit,
The power recovery processing execution means includes
After setting the initial setting for generating the timeout signal in the predetermined cycle in the timer circuit, performing a process of waiting until the interrupt process can be executed by the interrupt process execution means,
The end of the standby may be determined based on whether the timer circuit has generated the timeout signal.

  In order to solve the tenth problem, the present invention provides an eighteenth gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
Communication data generation means for creating command data related to gaming operations (for example, setting change command generation storage processing and communication data storage processing);
During the control process by the arithmetic processing means, an interrupt process is executed at a predetermined cycle, and when there is no command data relating to a game operation at the time of executing the interrupt process, an interrupt process execution means for transmitting a no-operation command (for example, , Interrupt processing)
Power recovery processing execution means (for example, power-on processing) for executing a predetermined power recovery processing at the time of power recovery;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The power recovery process execution means waits until the interrupt process execution means can execute the interrupt process after starting the power recovery process (for example, S7 and S8 during the power-on process). Done
The interrupt process execution means executes the interrupt process and transmits the no-operation command at the end of the standby by the power recovery process execution means,
The arithmetic processing means includes:
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing unit executes the arithmetic processing;
The command data includes a command type, a plurality of communication parameters, and a sum value.
A plurality of the communication parameters are respectively assigned to the plurality of general purpose registers,
The communication data generating means
In accordance with the command type of the command data, after setting the communication parameter in the general-purpose register assigned to the communication parameter, the communication parameter set in the general-purpose register is stored in a predetermined storage in the second storage means Stored in an area (for example, a temporary communication data storage area)
Even if there is a communication parameter that is not used based on the command type of the command data among the plurality of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter is changed to the communication parameter. Stored in the predetermined storage area as
A gaming machine, wherein a sum value of the command data is generated based on the command type and data stored in the general-purpose register assigned to a communication parameter.

The eighteenth gaming machine of the present invention further includes power supply monitoring means (for example, a power supply monitoring port) for monitoring the power supply voltage state.
The arithmetic processing means includes:
If the state of the power supply voltage is not stable, wait until the state of the power supply voltage is stable,
On the condition that the state of the power supply voltage is stable, after initializing the timer circuit, serial communication circuit, and random number circuit of the arithmetic processing means, the predetermined area of the second storage means is used to 2 Check whether the storage means is normal,
The no-operation command may be transmitted on condition that the second storage means is normal.

  According to the seventeenth and eighteenth game machines of the present invention configured as described above, the communication between the main control board and the sub-control board when the power is turned on can be stably operated.

[19th and 20th game machines]
Conventionally, in the gaming machine having the above-described configuration, based on the lottery result, for example, a gaming machine that executes a control called a reel winning symbol drawing control and a control called a reel winning symbol kicking control is known. (For example, refer to JP 2002-219213 A).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Furthermore, in recent years, the gameability has become more complex and the number of winning combinations (winning combinations) has increased. As a result, the RAM capacity of the main control circuit is under pressure, and the processing executed by the main control circuit is made more efficient. Therefore, development of a technology capable of effectively utilizing the limited RAM capacity of the main control circuit is demanded.

  The present invention has been made to solve the eleventh problem, and an eleventh object of the present invention is to improve the efficiency of processing executed by the main control circuit and to effectively use the RAM capacity of the main control circuit. It is to provide a gaming machine that can be utilized.

  In order to solve the eleventh problem, the present invention provides a nineteenth gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Internal lottery means (for example, internal lottery processing) for determining flag status information (for example, hit request flag status) related to the internal winning combination with a predetermined probability;
An internal symbol combination generating unit that generates an internal symbol combination from the flag status information acquired by the internal lottery unit (for example, S321 during the symbol setting process);
Flags defining a correspondence relationship between the internal winning combination, flag data corresponding to the internal winning combination, and storage destination data for specifying a storage destination of the flag data in the second storage unit, and stored in the first storage unit A flag table expansion means (for example, S324 during the symbol setting process) for expanding a data table (for example, a hit request flag table) in the second storage means;
Flag storage area designating means (for example, S329 during the symbol setting process) for designating an address of a flag data storage area (for example, a hit request flag storage area) that is arranged in the second storage means and stores the flag data; ,
Flag data for transferring and storing the flag data corresponding to the internal winning combination generated by the internal winning combination generating means from the flag table in the flag data storage area based on the corresponding storage destination data And a storage means (for example, S330 during the symbol setting process).

  In the nineteenth gaming machine of the present invention, the arithmetic processing means calculates on-bit information indicating the storage destination data in the flag data table and sets the on-bit information to be transferred. The flag data may be transferred to the flag data storage area.

  In order to solve the eleventh problem, the present invention provides a twentieth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data )When,
Internal lottery means (for example, internal lottery processing) for determining flag status information (for example, hit request flag status) related to the internal winning combination with a predetermined probability;
An internal symbol combination generating unit that generates an internal symbol combination from the flag status information acquired by the internal lottery unit (for example, S321 during the symbol setting process);
A winning flag data table (for example, a hit request) that defines the correspondence between the internal winning combination, the winning flag data corresponding to the internal winning combination, and the storage destination data that specifies the storage destination of the winning flag data in the second storage means. A winning flag table expanding means (for example, S324 during the symbol setting process) for expanding the flag table) in the second storage means;
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing address designation in the second storage means by using the extension register, it is arranged in the second storage means and the winning register A winning flag storage area designating unit (for example, S329 during the symbol setting process) for designating an address of a winning flag data storage area (for example, a hit request flag storage area) for storing flag data;
The winning flag data corresponding to the internal winning combination generated by the internal winning combination generating means is transferred from the winning flag table to the winning flag data storage area based on the corresponding storage destination data and stored. Winning flag data storage means (for example, S330 during the symbol setting process),
Stop control means (for example, reel stop control process) for stopping the symbol variation display based on the determination result of the internal lottery means and detection of the stop operation by the stop operation detection means;
When the variable display of the plurality of display columns is stopped by the stop control means, the combination of symbols corresponding to the internal winning combination is stopped and displayed on the determination line set across the plurality of display columns. A winning combination determining means for determining whether or not (for example, a winning search process);
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area specifying means (for example, S648 during the symbol code acquisition process) for specifying an address of the winning action flag storage area);
By executing the predetermined read command, the address of the symbol code storage area for storing symbol code data corresponding to the symbol combination arranged in the second storage means and stopped and displayed on the determination line is designated. And a symbol code storage area setting means (for example, S650 during symbol code acquisition processing).

  In the twentieth gaming machine of the present invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  According to the nineteenth and twentieth gaming machines of the present invention configured as described above, the processing executed by the main control circuit can be made more efficient, and the RAM (second storage means) capacity of the main control circuit can be effectively utilized. .

[21st and 22nd game machines]
Conventionally, in the gaming machine having the above-described configuration, the reel symbol variable display stop control is performed based on the internal winning combination and the player's stop operation, the winning combination is determined based on the combination of symbols, and the hopper is determined based on the winning determination result. A gaming machine that controls a medal payout device to control payout of medals is known (see, for example, JP-A-2008-119498).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the twelfth problem, and a twelfth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the twelfth problem, the present invention provides a twenty-first gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) in which data is stored when the arithmetic processing unit performs the arithmetic processing, and a part of the address in the second storage unit can be specified by the stored data;
By executing a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means using the extension register, the detection result of the stop operation by the stop operation detecting means is obtained. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired;
When a stop operation of a player for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, it is arranged in the second storage means and the predetermined display row Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139)) for designating an address of a stop control data storage area for storing variable display stop control data; A gaming machine characterized by comprising:

  In the twenty-first gaming machine of the present invention, a part of the address that can be specified by the extension register may be a higher-order address value constituting the address.

  In order to solve the twelfth problem, the present invention provides a twenty-second gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means and the determination operation of the combination of symbols to be stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) in which data is stored when the arithmetic processing unit performs the arithmetic processing, and a part of the address in the second storage unit can be specified by the stored data;
By executing a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means using the extension register, the detection result of the stop operation by the stop operation detecting means is obtained. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired;
When a stop operation of a player for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, it is arranged in the second storage means and the predetermined display row Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139)) for designating an address of a stop control data storage area for storing variable display stop control data;
In the process of preferentially determining the combination of symbols to be stopped and displayed on the determination line by the priority stop symbol determination means, a comparison determination command, a process jump destination address designation command, and a process jump operation command By executing a predetermined determination instruction (for example, “JCP” instruction) executable by the instruction, a combination of symbols corresponding to the internal winning combination to be determined is added to a specific display sequence (for example, currently determined) In addition, it is determined whether or not a predetermined symbol combination (for example, “ANY” combination) in which the stop symbol on the determination line in the right reel 3R) is arbitrary is included, and the internal winning combination to be determined When it is determined that the predetermined symbol combination is included in the corresponding symbol combination, a stop display of the symbol combination corresponding to the internal winning combination to be determined is displayed. Gaming machine, characterized in that it comprises any combination corresponding processing means for locking (e.g., S683 in attraction priority acquisition processing), the.

  In the twenty-second gaming machine of the present invention, a part of the address that can be designated by the extension register may be an upper address value constituting the address.

  According to the twenty-first and twenty-second gaming machines of the present invention configured as described above, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity It is possible to improve the playability by using the free space of the ROM.

[23rd to 25th game machines]
2. Description of the Related Art Conventionally, in gaming machines having the above-described configuration, a gaming machine that performs symbol stop control using a pull-in priority table during symbol stop control is known (see, for example, Japanese Patent Application Laid-Open No. 2007-175450).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The present invention has been made to solve the thirteenth problem, and a thirteenth object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit and reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of a ROM and enhancing the playability by using the free space of the ROM corresponding to the increased capacity.

  In order to solve the thirteenth problem, the present invention provides a twenty-third gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the second storage means by the stored data. ,
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing addressing in the second storage means using the extension register, the internal memory is arranged in the second storage means and the internal A winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) for specifying an address of a winning flag data storage area (for example, a hit request flag storage area) for storing the winning flag data corresponding to the winning combination;
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area designating means (for example, S686 during the drawing priority order acquisition process) for designating an address of a winning action flag storage area);
A gaming machine comprising: AND operation means (for example, S686 during the drawing priority order acquisition process) for performing an AND operation between the winning flag data and the corresponding winning flag data.

In the twenty-third gaming machine of the present invention, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined When a predetermined combination of symbols (for example, “ANY” combination) in which a stop symbol on the determination line in a specific display row (for example, the right reel 3R) currently being determined is included is included in
The arithmetic processing means includes: an address specifying process of the winning flag data storage area by the winning flag storage area specifying means, an address specifying process of the winning flag data storage area by the winning flag storage area specifying means, and the AND operation The AND operation processing by the means may not be executed.

  In order to solve the thirteenth problem, the present invention provides a twenty-fourth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing addressing in the second storage means using the extension register, the internal memory is arranged in the second storage means and the internal A winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) for specifying an address of a winning flag data storage area (for example, a hit request flag storage area) for storing the winning flag data corresponding to the winning combination;
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area designating means (for example, S686 during the drawing priority order acquisition process) for designating an address of a winning action flag storage area);
AND operation means for performing an AND operation between the winning flag data and the winning flag data corresponding to the winning flag data (for example, S686 during the pull-in priority acquisition process);
By executing the predetermined read command, priority order data table acquisition means (for example, pull-in priority order) for acquiring a data table defining the priority order of the combination of symbols to be stopped and displayed among the plurality of types of symbol combinations S687) during the acquisition process.

In the twenty-fourth gaming machine of the present invention, the combination of symbols corresponding to the internal winning combination to be determined in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means. When a predetermined symbol combination (for example, “ANY” combination) in which a stop symbol on the determination line in a specific display row (for example, right reel 3R) currently being determined is included is included in
The arithmetic processing means includes: an address specifying process of the winning flag data storage area by the winning flag storage area specifying means, an address specifying process of the winning flag data storage area by the winning flag storage area specifying means, and the AND operation The AND operation processing by the means may not be executed.

  In order to solve the thirteenth problem, the present invention provides a twenty-fifth gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
An error detection means for determining whether or not an illegal hit error has occurred (for example, an illegal hit check process);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the error detection means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit performs the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the second storage means by the stored data. ,
In the process of determining whether or not an illegal hit error has occurred by the error detection means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing address designation in the second storage means by using the extension register, the plurality of instructions are arranged in the second storage means and the plurality A winning flag that specifies an address of a winning flag data storage area (for example, a winning action flag storage area) that stores winning flag data corresponding to a combination of symbols stopped and displayed on the determination line set across the display line Storage area designating means (for example, S781 during illegal hit check processing);
AND operation means for performing an AND operation between the winning flag data stored in the winning flag data storage area and the corresponding winning flag data indicating the internal winning combination (for example, S784 during illegal hit check processing) When,
Error determination means (for example, S785 during the illegal hit check process) for determining whether or not an illegal hit error has occurred based on the calculation result by the logical product calculation means;
A gaming machine, wherein the structure of a winning flag data storage area (for example, a winning request flag storage area) in which the winning flag data is stored is the same as that of the winning flag data storage area.

  In the twenty-fifth gaming machine of the present invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

Furthermore, in the twenty-fifth gaming machine of the present invention, the arithmetic processing means has error processing means for performing error processing when the error detecting means determines that there is an illegal hit error,
The error processing means may notify the illegal hit error so as to be visible, and may stop the game until the illegal hit error is canceled.

  According to the twenty-third to twenty-fifth gaming machines of the present invention configured as described above, the capacity of the processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity. It is possible to improve the playability by using the free space of the ROM.

[26th game machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine that transmits command data from a gaming control board (main control board) to an effect control board (sub control board) is known (for example, Japanese Patent Application Laid-Open No. 2013-027655). And Japanese Patent Application Laid-Open No. 2014-033751).

  By the way, in recent years, with diversification of game playability, there is a tendency that processing related to game play increases in effect control by the sub control circuit. For this reason, an illegal act called “Goto” that tampers communication data transmitted from the main control circuit to the sub-control circuit has occurred, causing damage to the game shop. On the other hand, conventionally, as proposed in, for example, the above-mentioned Japanese Patent Application Laid-Open No. 2014-033751 and the like, countermeasures for performing anti-going processing on transmission data in the main control circuit have also been implemented. However, there is a problem that the program capacity of the main control circuit is compressed by the addition of such anti-going processing.

  The present invention has been made to solve the fourteenth problem, and a fourteenth object of the present invention is to suppress fraud without performing fraud prevention processing on transmission data, It is an object of the present invention to provide a gaming machine that can eliminate the compression of the program capacity of a main control circuit due to fraud prevention processing.

  In order to solve the fourteenth problem, the present invention provides a twenty-sixth gaming machine having the following configuration.

Data transmission means (for example, main control circuit 90) for transmitting communication data relating to the gaming operation;
Communication data generation means for generating the communication data (for example, communication data storage processing);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling communication data generating operation by the communication data generating means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing unit executes the arithmetic processing;
The arithmetic processing means includes:
In the communication data generation process by the communication data generation means,
A plurality of types of communication parameters constituting the communication data are assigned to the plurality of general purpose registers, respectively.
Among a plurality of types of communication parameters constituting the communication data, a communication parameter based on the type of the communication data is set in a corresponding general-purpose register among the plurality of general-purpose registers,
Storing the communication parameters set in the general-purpose register in a predetermined storage area (communication data temporary storage area) in the second storage means;
Among the plurality of types of communication parameters, data stored in a general-purpose register associated with an unused communication parameter when generating communication data is stored as a communication parameter in the predetermined storage area,
A gaming machine, wherein a sum value of the communication data is generated based on data set in the plurality of general-purpose registers according to the plurality of types of communication parameters.

  Further, in the twenty-sixth gaming machine of the present invention, the communication data generating means, if there is no free space in the predetermined storage area in the second storage means, the communication data set in the plurality of general purpose registers. You may make it complete | finish a production | generation process of communication data, without storing a parameter in the predetermined storage area in the said 2nd memory | storage means.

  According to the twenty-sixth gaming machine of the present invention configured as described above, fraudulent acts can be suppressed without performing fraud prevention processing on transmission data (communication data), and the program capacity of the main control circuit by fraud prevention processing can be suppressed. The pressure of can be eliminated.

[The 27th game machine]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine having a function of updating the number of credits according to the number of medals paid out under the control of a main control circuit is known (for example, Japanese Patent Application Laid-Open No. 2009-2009). No. 079777).

  Conventionally, in games during ART or bonuses, medals are often paid out. At this time, the payout interval for each medal is often controlled uniformly (fixed). In this case, useless waiting time occurs in the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes uselessly long, which may be a mental burden on the player.

  The present invention has been made to solve the fifteenth problem, and a fifteenth object of the present invention is to reduce useless waiting time and reduce a player's mental burden during a medal payout period. It is to provide a gaming machine capable of doing so.

  In order to solve the fifteenth problem, the present invention provides a twenty-seventh gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
A stop operation detecting means (for example, a stop switch substrate 80) for detecting a stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the variable display of the plurality of display columns is stopped by the stop control means, the symbol corresponding to the internal winning combination relating to the payout of the game medium on the determination line set across the plurality of display columns Privilege grant determination means (for example, winning search process) for determining whether or not the combination of
A game medium payout means for paying out the game medium when the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line by the bonus grant determination means (for example, , Winning check / medal payout processing),
Game medium storage means for storing the game medium (for example, a credit function);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the game medium payout operation by the game medium payout means,
The arithmetic processing means includes:
The game medium determined by the bonus granting determination means that the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line, and stored in the game medium storage means If the storage number of the game medium is less than the upper limit value, game medium addition means for adding 1 to the number of storage of the game medium (for example, S805 during the winning check / medal payout process);
After the game medium is added to the number of stored game media by the game medium adding means, the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed. A payout end determination means for determining whether or not the payout of the total payout number of game media has ended (for example, S807 during the winning check / medal payout process);
When the payout end determination means determines that the payout of the total payout amount of the game medium has not ended, a weight generation means (for example, a prize check A game machine characterized by having a medal payout process (S808).

In the twenty-seventh gaming machine of the present invention, the arithmetic processing means includes interrupt processing execution means for executing interrupt processing at a predetermined cycle,
The interrupt processing by the interrupt processing execution means may be executed a predetermined number of times with the weight at which the operation related to the game by the weight generation means is invalid.

  According to the twenty-seventh gaming machine of the present invention configured as described above, in the medal (game medium) payout period, useless waiting time can be reduced and the mental burden on the player can be reduced.

[28th and 29th game machines]
Conventionally, in the gaming machine having the above-described configuration, a gaming machine in which a lottery table for determining an internal winning combination or an AT game is stored in a ROM is known (for example, see Japanese Patent Application Laid-Open No. 2009-12559).

  By the way, in the gaming machine described in JP 2009-12559 A, the lottery table and the lottery processing program for AT games are stored in a ROM provided on the sub-control board with sufficient storage capacity. However, for reasons specific to the gaming machine industry in recent years, tables and programs related to AT game lottery need to be stored in the ROM provided on the main control board. For this reason, the ROM capacity of the main control board, which is limited to a small capacity, is pressed.

  The present invention has been made to solve the above sixteenth problem, and a sixteenth object of the present invention is to reduce the capacity of data used in processing of the main control circuit and to free up ROM in the main control circuit. It is to provide a gaming machine capable of increasing the capacity.

  In order to solve the sixteenth problem, the present invention provides a twenty-eighth gaming machine having the following configuration.

Start operation detecting means for detecting a start operation by the player (for example, a start switch 79);
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Based on the internal winning combination determining means determined by the internal winning combination determining means, a bonus grant determining means (for example, a CT lottery process during CT) for determining whether or not a gaming state advantageous to the player is granted as a bonus. When,
A lottery table (for example, CT CT lottery table during CT) referred to by the privilege grant determining means,
In the lottery table,
Determination data (for example, a determination bit) that specifies the type of the internal winning combination to be a lottery target and the lottery value of the internal winning combination that is specified by the determination data are defined.
The lottery value of the internal winning combination that is not subject to lottery is not specified,
A value other than 0 is specified for the lottery value of the internal winning combination for the lottery subject with a winning probability of less than 100%, and 0 is specified for the lottery value of the internal winning combination for the lottery target with a winning probability of 100%. A gaming machine characterized by being.

In the twenty-eighth gaming machine of the present invention, the privilege grant determining means is
Get a 1-byte random value from the soft latch random number,
It may be determined whether to give a gaming state advantageous to the player as a privilege by lottery using the acquired random number value and the lottery value.

  In order to solve the sixteenth problem, the present invention provides a twenty-ninth gaming machine having the following configuration.

Start operation detecting means for detecting a start operation by the player (for example, a start switch 79);
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Based on the internal winning combination determining means determined by the internal winning combination determining means, a bonus grant determining means (for example, a CT lottery process during CT) for determining whether or not a gaming state advantageous to the player is granted as a bonus. When,
A lottery table (for example, a CT winning lottery table during CT) which is referred to by the privilege grant determining means and provided for each type of the internal winning combination;
A lottery table selection table (for example, a table selection relative table for each winning combination) for selecting the lottery table associated with the currently determined internal winning combination;
In the lottery table selection table,
For each type of the internal winning combination, it is possible to determine whether or not the internal winning combination of the type is a lottery target, and the location of the lottery table associated with the internal winning combination of the type can be specified Selection value is defined,
The selection value of the internal winning combination that is not subject to lottery is defined as 0, in which the lottery result by the privilege grant determining means is treated as lost,
Data other than 0 is defined in the selection value of the internal winning combination to be a lottery target.

  In the 29th gaming machine of the present invention, the selection value of the lottery table selection table is a relative value up to the lottery table to be selected, and the relative value is a value of 1 byte. Good.

  According to the twenty-eighth and twenty-ninth gaming machines of the present invention configured as described above, it is possible to reduce the capacity of data used in the processing of the main control circuit and increase the free space of the ROM of the main control circuit.

[30th game machine]
Conventionally, in the gaming machine having the above-described configuration, a program and a table are respectively arranged in predetermined areas in a ROM mounted on a main control board (see, for example, JP 2012-110635 A).

  By the way, as in the gaming machine described in JP 2012-110635 A, the programs and tables that can be arranged in the ROM of the main control board are limited by the rules of the gaming machine industry, and the ROM of the main control board The program and table expandability is extremely poor.

  The present invention has been made to solve the seventeenth problem, and a seventeenth object of the present invention is a gaming machine capable of enhancing the expandability of programs and tables in the ROM of the main control board. Is to provide.

  In order to solve the seventeenth problem, the present invention provides a thirtieth gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
In the first storage means, a game storage area (for example, a game ROM area) in which information necessary for executing a process related to the game performance of a game executed by a player is stored, and the game storage An unspecified storage area (for example, an unspecified ROM area) in which information necessary for execution of processing that is arranged in an area different from the area and is not related to the game performance of the game executed by the player is provided. A gaming machine characterized by

  In the thirtieth gaming machine of the present invention, the second storage means temporarily stores information necessary for execution of processing related to game playability performed by the player. A game temporary storage area including a work area and a game stack area (for example, a game RAM area) and a game playability that is arranged in a different area from the game temporary storage area and executed by the player A non-standard temporary storage area (for example, a non-standard RAM area) including a non-standard work area and a non-standard stack area in which information necessary for execution of processes not involved in the process is temporarily stored. Also good.

Furthermore, in the thirtieth gaming machine of the present invention, the arithmetic processing means has a stack pointer as a dedicated register,
The arithmetic processing means includes:
When executing the program stored in the non-standard storage area of the first storage unit, the address of the non-standard stack area of the second storage unit is set in the stack pointer,
When the program stored in the non-specified storage area of the first storage means is to be terminated, the game of the second storage means saved when executing the program stored in the non-standard storage area The address of the stack area may be set in the stack pointer to return to the program stored in the game storage area of the first storage area.

  According to the thirtieth gaming machine of the present invention configured as described above, the expandability of the program and table in the ROM of the main control board can be enhanced.

[31st game machine]
Conventionally, in the gaming machine having the above-described configuration, in order to use the information of the internal winning combination determined by the main control circuit in the production control of the sub-control circuit, the internal winning combination is converted into a sub flag that categorizes the types in groups. A gaming machine having a function is known (for example, see JP 2010-051471 A).

  In the gaming machine described in the above-mentioned Japanese Patent Application Laid-Open No. 2010-05471, the conversion table and conversion processing program for converting the internal winning combination into a subflag are stored in a ROM provided on the sub-control board with sufficient storage capacity. Has been. However, for reasons specific to the recent gaming machine industry, the information on the internal winning combination determined by the main control circuit cannot be transmitted to the sub control circuit, and the conversion table and conversion processing program related to the subflag are also provided on the main control board. Need to be stored in ROM. In this case, the ROM capacity of the main control board, which is limited to a small capacity, is pressed by these tables and programs. Therefore, it is necessary to develop a technology that can suppress the pressure on the ROM capacity of the main control board by the conversion table and conversion processing program related to the subflag, and can efficiently cope with changes in the model, planning, and specifications of the gaming machine. ing.

  The present invention has been made to solve the eighteenth problem, and an eighteenth object of the present invention is to suppress the compression of the ROM capacity of the main control board and to make the model, plan, and specifications of the gaming machine. It is an object of the present invention to provide a gaming machine that can efficiently cope with changes such as the above.

  In order to solve the eighteenth problem, the present invention provides a thirty-first gaming machine having the following configuration.

Start operation detecting means for detecting a start operation by the player (for example, a start switch 79);
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
First sub-flag conversion means (for example, sub-flag conversion process) for converting the internal winning combination determined by the internal winning combination determination means to a first sub-flag (for example, sub-flag) with reference to a conversion table;
The first subflag obtained by the conversion process by the first subflag conversion means is converted into a second subflag (for example, subflag EX) by lottery with reference to a lottery table (for example, various flag conversion lottery tables). Second sub-flag conversion means (for example, flag conversion processing),
In the conversion table, a correspondence relationship between the internal winning combination, the control status data associated with the internal winning combination, and the first subflag is defined, and for the first subflag of the same type, The control status data with the same value is assigned,
The gaming machine, wherein the lottery by the second sub-flag conversion means is performed based on the control status data.

The gaming machine of the present invention further includes data transmission means for transmitting command data relating to the gaming operation,
The data transmission unit may transmit the first subflag as a communication parameter of command data when the start operation detection unit detects a start operation.

  According to the thirty-first gaming machine of the present invention configured as described above, the ROM capacity of the main control board can be suppressed, and changes in the gaming machine model, planning, specifications, and the like can be efficiently performed.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information indicator, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub-control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit 200 ... sub control circuit 201 ... sub CPU 201 301 ... first interface board 302 ... second interface board

Claims (1)

Arithmetic processing means for performing arithmetic processing for controlling gaming operations;
Storage means for storing information necessary for execution of the arithmetic processing by the arithmetic processing means;
Power supply means for supplying power supply voltage;
An activation unit that outputs an activation signal to the arithmetic processing unit when the power supply voltage exceeds a predetermined activation voltage value ;
A watchdog timer capable of outputting a reset signal to the arithmetic processing means when the clear information is not written for a predetermined time or more ,
The arithmetic processing means includes:
A group of registers including a main register, a sub register and a stack pointer;
Sum value subtracting means for sequentially subtracting information stored in a predetermined storage area in the storage means from the sum value generated at the time of the most recent power interruption, triggered by the start means outputting the start signal; Have
The main register is 1 and byte of the accumulator, a flag register for execution result of the operation instruction is reflected, 1 byte first pair register and a second pair register general purpose register Ru can be used in two sets of And
The flag register has a zero flag that is set to an ON state when a subtraction instruction is executed and the execution result is 0,
The sum value subtracting means includes:
The address corresponding to the predetermined storage area in the storage means for starting subtraction is set in the stack pointer, the number of subtraction executions is set in a counter provided in the storage means, and the first pair register is stored in the first pair register. Set the sum value stored in the sum value storage area in the storage means,
When the subtraction is started, the address stored in the stack pointer is updated in the direction of addition, and the dedicated instruction for storing the information stored in the address before update in the second pair register is executed, and wherein by subtracting the stored value from the value stored in the first pair register to said second compare register, a process for executing a subtraction instruction to store the subtraction result to the first pair register, execution of the subtraction Run repeatedly,
The arithmetic processing means includes:
When it is determined that the writing confirmation to the storage means is normal, the arithmetic processing by the sum value subtracting means is executed,
If the ON state is not set in the zero flag when the arithmetic processing by the sum value subtracting unit is completed, it is determined that the sum value stored in the sum value storage area is abnormal, and then the watch Executes an infinite loop process that repeats writing the clear information to the dog timer ,
If the zero flag is set to ON when the arithmetic processing by the sum value subtracting unit is completed, it is determined that the sum value stored in the sum value storage area is normal, and then the most recent A game machine that returns to the game before the occurrence of the power interruption.

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