JP2019165392A - Delay adjustment device - Google Patents

Abstract

To properly adjust the difference in delay that can occur between two polarization signals before demodulation.SOLUTION: A delay adjustment device includes a signal generation unit 110 that generates a first test pattern signal indicating a test pattern of a first polarization signal that is demodulated by a first demodulation device 10, a transmission processing unit 120 that transmits the first test pattern signal to a second demodulation device that demodulates a second polarization signal, a reception processing unit 130 that receives a first test pattern return signal sent back from the second demodulation device 20 in response to the first test pattern signal, and an adjustment unit 140 that adjusts a delay amount generated before demodulation between the first polarization signal and the second polarization signal on the basis of the first test pattern signal and the first test pattern return signal.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a delay adjusting device that adjusts a delay amount generated between a plurality of polarization signals.

  For example, in a digital microwave communication device, two orthogonal polarization planes of the same frequency, vertical polarization (hereinafter referred to as V (Vertical) polarization) and horizontal polarization (H (Horizontal) polarization) are used for signal transmission. A dual-polarization transmission system that performs transmission is used. In both polarization transmission systems, the same carrier frequency is used for V polarization and H polarization, so if there is a deviation in the orthogonal plane of polarization, a signal with a different polarization leaks into its own polarization and becomes an interference component. As a result, signal transmission quality deteriorates. In particular, in the case of a multi-level modulation system, this influence cannot be ignored, so it is necessary to remove interference components on the receiving side. As a technique for removing this interference component, cross polarization interference compensation (XPIC: Cross Polarization Interference Canceller) is known.

  The above-described V / H polarization is demodulated by each independent V / H polarization demodulator. For this reason, it is necessary to transmit a different polarization signal bidirectionally between the V polarization demodulator and the H polarization demodulator. As signal transmission means between the above-described V polarization demodulator and H polarization demodulator, for example, analog transmission using a cable is performed.

  In Patent Document 1, cross-polarization interference compensation is performed by comparing the tap coefficient with a threshold and adjusting the delay time of the own polarization according to whether there is a tap coefficient larger than the threshold. It is described.

  Patent Document 2 discloses that a phase of a clock signal is detected from outputs of demodulator circuits on different polarization sides and a control signal is output, and a phase of the clock signal is shifted by the control signal, It describes that the sampling timing of the output is controlled.

  Further, Patent Document 3 discloses that when receiving a main polarization signal and a different polarization signal transmitted by mutually orthogonal polarizations in synchronization with each transmission clock signal, the different polarization side to the main polarization side. A cross-polarization interference compensator that removes cross-polarized signal components that cross-interfered with each other is described.

JP 2017-139606 A JP 09-214461 A Japanese Patent Laid-Open No. 05-211493

  However, when high-speed serial transmission using a transceiver that can be mounted on an FPGA or ASIC device is used as the signal transmission means described above, there is a problem that the processing delay of the different polarization signal becomes large.

  Here, the deviation of the delay amount between the two polarization signals before the demodulation process is compensated by a demodulation circuit (equalizer) located in the latter stage of the signal processing system. However, if there is a delay amount difference between the two polarization signals (the own polarization signal and the different polarization signal) in the circuit processing before the demodulation processing, the margin of the compensation capability is reduced. For this reason, the circuit processing of the own polarization signal and the different polarization signal before the demodulation circuit input is required to have the same delay amount. Although manual adjustment is possible for each circuit, it is troublesome.

  An object of the present invention is to provide a delay adjustment device capable of appropriately adjusting a delay amount difference that can occur between two polarization signals before demodulation.

  The delay amount adjustment apparatus of the present invention includes a signal generation unit that generates a first test pattern signal indicating a test pattern of a first polarization signal that is demodulated by the first demodulation apparatus, and a second polarization A transmission processor for transmitting the first test pattern signal to a second demodulator that demodulates the signal, and a first test sent back from the second demodulator in response to the first test pattern signal Based on the reception processing unit that receives the pattern return signal, the first test pattern signal, and the first test pattern return signal, the first polarization signal and the second polarization signal And an adjustment unit for adjusting a delay amount generated before demodulation.

  According to the present invention, it is possible to appropriately adjust a delay amount difference that may occur between two polarization signals before demodulation. In addition, according to this invention, another effect may be show | played instead of the said effect or with the said effect.

FIG. 1 is an explanatory diagram illustrating an example of a schematic configuration of a wireless communication device 1 according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a schematic configuration of the first delay adjustment apparatus 100 according to the first embodiment. FIG. 3 is a block diagram illustrating an example of a schematic configuration of the second delay adjustment apparatus 200 according to the first embodiment. FIG. 4 is a block diagram illustrating an example of schematic signal processing performed inside the first delay adjustment apparatus 100 and the second delay adjustment apparatus 200. FIG. 5 is a diagram illustrating an example of a schematic data structure of a signal input or output in each process illustrated in FIG. 4. FIG. 6 is a block diagram illustrating an example of a schematic configuration of the delay adjustment apparatus 300 according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and drawings, elements that can be similarly described are denoted by the same reference numerals, and redundant description may be omitted.

The description will be made in the following order.
1. Outline of Embodiment of the Present Invention 2. Configuration of wireless communication device 1 First embodiment 3.1. Configuration of first delay adjustment apparatus 100 3.2. Configuration of second delay adjustment device 200 3.3. Technical features 3.4. Example 4 Second Embodiment 4.1. Configuration of delay adjusting apparatus 300 4.2. Technical features 5. Other forms

<< 1. Outline of Embodiment of the Present Invention >>
First, an outline of an embodiment of the present invention will be described.

(1) Technical issues For example, in a digital microwave communication device, signal transmission is performed using two polarization planes of the same frequency orthogonal to each other, vertical polarization (V polarization) and horizontal polarization (H polarization). A dual polarization transmission system is used. In both polarization transmission systems, the same carrier frequency is used for V polarization and H polarization, so if there is a deviation in the orthogonal plane of polarization, a signal with a different polarization leaks into its own polarization and becomes an interference component. As a result, signal transmission quality deteriorates. In particular, in the case of a multi-level modulation system, this influence cannot be ignored, so it is necessary to remove interference components on the receiving side. As a technique for removing this interference component, cross polarization interference compensation (XPIC: Cross Polarization Interference Canceller) is known.

  The above-described V / H polarization is demodulated by each independent V / H polarization demodulator. For this reason, it is necessary to transmit a different polarization signal bidirectionally between the V polarization demodulator and the H polarization demodulator. As a signal transmission means between the above-described V polarization demodulator and H polarization demodulator, analog transmission using a cable is performed.

  However, when high-speed serial transmission using a transceiver that can be mounted on an FPGA or ASIC device is used as the signal transmission means, there is a problem that processing delay of different polarization signals becomes large.

  Here, the deviation of the delay amount between the two polarization signals before the demodulation process is compensated by a demodulation circuit (equalizer) located in the latter stage of the signal processing system. However, if there is a delay amount difference between the two polarization signals (the own polarization signal and the different polarization signal) in the circuit processing before the demodulation processing, the margin of the compensation capability is reduced. For this reason, the circuit processing of the own polarization signal and the different polarization signal before the demodulation circuit input is required to have the same delay amount. Although manual adjustment is possible for each circuit, it is troublesome.

  An object of the present embodiment is to provide a delay adjustment device capable of appropriately adjusting a delay amount difference that may occur between two polarization signals before demodulation.

(2) Technical features In the embodiment of the present invention, for example, the delay adjustment device generates a first test pattern signal indicating a test pattern of the first polarization signal that is demodulated by the first demodulation device. The first test pattern signal is transmitted to a second demodulator that demodulates the second polarization signal, and the second demodulator is sent back in response to the first test pattern signal. 1 test pattern return signal is received, and between the first polarization signal and the second polarization signal based on the first test pattern signal and the first test pattern return signal. To adjust the delay amount generated before demodulation.

  As a result, for example, it is possible to appropriately adjust the difference in delay amount that can occur between two polarization signals before demodulation.

  The technical features described above are specific examples of the embodiments of the present invention, and the embodiments of the present invention are naturally not limited to the technical features described above.

<< 2. Configuration of Wireless Communication Device 1 >>
With reference to FIG. 1, the example of a structure of the radio | wireless communication apparatus 1 which concerns on embodiment of this invention is demonstrated. FIG. 1 is an explanatory diagram illustrating an example of a schematic configuration of a wireless communication device 1 according to an embodiment of the present invention. Referring to FIG. 1, the wireless communication device 1 includes a first demodulator 10 that demodulates, for example, a V polarization signal, and a second demodulator 20 that demodulates, for example, an H polarization signal.

(1) First demodulator 10
The first demodulator 10 includes, for example, a bandpass filter 11, a quadrature demodulator 12, an A / D converter 13, a first delay adjuster 100, a transceiver 14 (hereinafter also referred to as XCVR 14), and a demodulator 15. including. The first demodulator 10 may be referred to as a panel or a first panel.

  In the first demodulator 10 configured as described above, for example, each processing unit performs the following processing.

  The bandpass filter 11 converts the RF signal corresponding to the V polarization signal into an IF signal corresponding to the V polarization signal by performing filter processing, and outputs the IF signal to the quadrature demodulation unit 12. The quadrature demodulator 12 performs quadrature demodulation on the IF signal and outputs the result to the A / D converter 13. The A / D converter 13 converts the orthogonally demodulated analog V-polarized signal into a digital V-polarized signal and outputs it. The XCVR 14 is a transceiver that can be implemented by, for example, an FPGA or an ASIC device, and transmits the digital V polarization signal output from the A / D converter 13 to the second demodulator 20, as will be described later. A digital H polarization signal transmitted from the second demodulator 20 is received. The first delay adjustment apparatus 100 is between the digital V polarization signal output from the A / D converter 13 and the digital H polarization signal received from the second demodulation apparatus 20 via the XCVR 14. The generated delay amount is adjusted, and these two digital polarization signals (V polarization signal and H polarization signal) are output to the demodulator 15. The demodulator 15 demodulates the V polarization signal using the H polarization signal and outputs it to the outside.

(2) Second demodulator 20
The second demodulator 20 includes, for example, a bandpass filter 21, an orthogonal demodulator 22, an A / D converter 23, a second delay adjustment device 200, a transceiver 24 (hereinafter also referred to as XCVR 24), and a demodulator 25. including. The second demodulator 20 may be called a panel or a second panel.

  In the second demodulator 20 configured as described above, for example, each processing unit performs the following processing.

  The band pass filter 21 performs filtering on the RF signal corresponding to the H polarization signal to convert it to an IF signal corresponding to the H polarization signal, and outputs the IF signal to the quadrature demodulation unit 22. The quadrature demodulator 22 performs quadrature demodulation on the IF signal and outputs the result to the A / D converter 23. The A / D conversion unit 23 converts the orthogonally demodulated analog H polarization signal into a digital H polarization signal and outputs it. The XCVR 24 is a transceiver that can be implemented by, for example, an FPGA or an ASIC device, and transmits the digital H-polarized signal output from the A / D converter 23 to the first demodulator 10 as described above. The digital V polarization signal transmitted from the first demodulator 10 is received. The second delay adjustment device 200 is between the digital H polarization signal output from the A / D converter 23 and the digital V polarization signal received from the first demodulation device 10 via the XCVR 24. The generated delay amount is adjusted, and these two digital polarization signals (V polarization signal and H polarization signal) are output to the demodulation unit 25. The demodulator 25 demodulates the H polarization signal using the V polarization signal and outputs it to the outside.

<< 3. First Embodiment >>
Subsequently, a first embodiment of the present invention will be described with reference to FIGS. Hereinafter, specific functions of the first delay adjustment device 100 and the second delay adjustment device 200 will be described.

<3.1. Configuration of First Delay Adjustment Device 100>
An example of the configuration of the first delay adjustment apparatus 100 according to the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram illustrating an example of a schematic configuration of the first delay adjustment apparatus 100 according to the first embodiment. Referring to FIG. 2, the first delay adjustment apparatus 100 includes a signal generation unit 110, a transmission processing unit 120, a reception processing unit 130, and an adjustment unit 140. The first delay adjustment apparatus 100 can further include other components other than these components. That is, the first delay adjustment apparatus 100 can perform operations other than the operations of these components. Specific operations of the signal generation unit 110, the transmission processing unit 120, the reception processing unit 130, and the adjustment unit 140 will be described in detail later.

  For example, the first delay adjustment device 100 (transmission processing unit 120) performs processing of transmitting the X polarization signal output from the A / D conversion unit 13 to the second demodulation device 20 via the XCVR 14. In addition, the first delay adjustment apparatus 100 (reception processing unit 130) performs processing for receiving the H polarization signal transmitted from the second demodulation apparatus 20 via the XCVR 14.

  The first delay adjustment apparatus 100 is mounted as a digital circuit in an FPGA or ASIC device, for example.

<3.2. Configuration of Second Delay Adjustment Device 200>
An example of the configuration of the second delay adjustment apparatus 200 according to the first embodiment will be described with reference to FIG. FIG. 3 is a block diagram illustrating an example of a schematic configuration of the second delay adjustment apparatus 200 according to the first embodiment. Referring to FIG. 3, the second delay adjustment apparatus 200 includes a signal generation unit 210, a transmission processing unit 220, a reception processing unit 230, and an adjustment unit 240. The second delay adjustment device 200 can further include other components other than these components. That is, the second delay adjustment device 200 can perform operations other than the operations of these components. Specific operations of the signal generation unit 210, the transmission processing unit 120, the reception processing unit 130, and the adjustment unit 140 will be described in detail later.

  For example, the second delay adjustment device 200 (transmission processing unit 220) performs processing of transmitting the H polarization signal output from the A / D conversion unit 23 to the first demodulation device 10 via the XCVR 24. In addition, the second delay adjustment device 200 (reception processing unit 230) performs processing for receiving the V polarization signal transmitted from the first demodulation device 10 via the XCVR 24.

  The second delay adjustment device 200 is mounted as a digital circuit in an FPGA or ASIC device, for example.

<3.3. Technical features>
Next, technical features according to the first embodiment will be described.

  The first delay adjustment device 100 (signal generation unit 110) is a first test pattern signal indicating a test pattern of a first polarization signal (X polarization signal) that is demodulated by the first demodulation device 10. Is generated. Then, the first delay adjustment device 100 (transmission processing unit 120) transmits the first test pattern signal to the second demodulation device 20 that demodulates the second polarization signal (H polarization signal). . Then, the first delay adjustment device 100 (reception processing unit 130) receives the first test pattern return signal sent back from the second demodulation device 20 in response to the first test pattern signal. Then, the first delay adjustment apparatus 100 (adjustment unit 140) is configured to output the first polarization signal (V polarization signal) based on the first test pattern signal and the first test pattern return signal. ) And the second polarization signal (V polarization signal) are adjusted.

  In particular, the first demodulator 10 (demodulator 15) uses the second polarization signal (H polarization signal) with the delay amount adjusted to use the first polarization signal (V polarization). Signal) cross polarization interference compensation.

  The second delay adjustment device 200 (signal generation unit 210) also performs a second test indicating a test pattern of the second polarization signal (H polarization signal) that is demodulated by the second demodulation device 20. A pattern signal is generated. Then, the second delay adjustment device 200 (transmission processing unit 220) transmits the second test pattern signal to the first demodulation device 10 that demodulates the first polarization signal (V polarization signal). . Then, the second delay adjustment device 200 (reception processing unit 230) receives the second test pattern return signal sent back from the first demodulator 10 in response to the second test pattern signal. Then, the second delay adjustment device 200 (adjustment unit 240), based on the second test pattern signal and the second test pattern return signal, outputs the first polarization signal (V polarization signal). ) And the second polarization signal (V polarization signal) are adjusted.

  In particular, the second demodulator 20 (demodulator 25) uses the first polarization signal (V polarization signal) with the delay amount adjusted to use the second polarization signal (H polarization). Signal) cross polarization interference compensation.

(1) Specific processing of first delay adjustment device 100-reception processing The first delay adjustment device 100 (reception processing unit 130) receives the second polarization signal (H from the second demodulation device 20). The second test pattern signal indicating the test pattern of the polarization signal is further received. For example, when adjusting the delay amount, the first delay adjustment device 100 (reception processing unit 130) receives the second test pattern signal from the second demodulation device 20 via the XCVR 14.

  More specifically, the first delay adjustment apparatus 100 (reception processing unit 130) is an N-bit string signal (N is a natural number) including the second test pattern signal and the first test pattern return signal. May be received.

  For example, N is a natural number of 2 or more. In this case, for example, the upper N / 2 bit string includes the second test pattern signal, and the lower N / 2 bit string includes the first test pattern return signal.

-Transmission Processing The first delay adjustment device 100 (transmission processing unit 120) further transmits a second test pattern return signal that is sent back to the second demodulation device 20 in response to the second test pattern signal. For example, when adjusting the delay amount, the first delay adjustment device 100 (transmission processing unit 120) transmits the second test pattern return signal to the second demodulation device 20 via the XCVR 14.

  More specifically, the first delay adjustment apparatus 100 (transmission processing unit 120) is an N-bit string signal (N is a natural number) including the first test pattern signal and the second test pattern return signal. May be sent.

  For example, when N is a natural number greater than or equal to 2, the first test pattern signal is included in the upper N / 2 bit string, and the second test pattern return signal is included in the lower N / 2 bit string.

  The first delay adjustment apparatus 100 (transmission processing unit 120) may transmit a first control signal indicating the presence / absence of the first test pattern signal in the N-bit string signal. Further, the first delay adjustment apparatus 100 (transmission processing unit 120) may transmit a second control signal indicating the presence or absence of the second test pattern return signal in the N bit string signal. For example, the first control signal and the second control signal are added to the minimum bit side of the N bit string signal.

(2) Specific Processing of Second Delay Adjustment Device 200 -Reception Processing The second delay adjustment device 200 (reception processing unit 230) receives the first polarization signal (V from the first demodulation device 10). The first test pattern signal indicating the test pattern of the polarization signal is further received. For example, when adjusting the delay amount, the second delay adjustment device 200 (reception processing unit 230) receives the first test pattern signal from the first demodulation device 10 via the XCVR 24.

  More specifically, the second delay adjustment apparatus 200 (reception processing unit 230) is an N-bit string signal (N is a natural number) including the first test pattern signal and the second test pattern return signal. May be sent.

  For example, N is a natural number of 2 or more. In this case, for example, the upper N / 2 bit string includes the first test pattern signal, and the lower N / 2 bit string includes the second test pattern return signal.

-Transmission Processing The second delay adjustment device 200 (transmission processing unit 220) further transmits a first test pattern return signal that is sent back to the first demodulation device 10 in response to the first test pattern signal. For example, when adjusting the delay amount, the second delay adjustment device 200 (transmission processing unit 220) transmits the first test pattern return signal to the first demodulation device 10 via the XCVR 24.

  More specifically, the second delay adjusting apparatus 200 (transmission processing unit 220) is an N-bit string signal including the second test pattern signal and the first test pattern return signal (N is a natural number). May be sent.

  As described above, for example, when N is a natural number equal to or greater than 2, the upper N / 2 bit string includes the second test pattern signal, and the lower N / 2 bit string includes the first test pattern return signal.

  The second delay adjustment apparatus 200 (transmission processing unit 220) may transmit a second control signal indicating the presence or absence of the second test pattern signal in the N bit string signal. The second delay adjustment apparatus 200 (transmission processing unit 220) may transmit a first control signal indicating the presence or absence of the first test pattern return signal in the N bit string signal. For example, the second control signal and the first control signal are added to the minimum bit side of the N bit string signal.

<3.4. Example>
Next, an example according to the first embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a block diagram illustrating an example of schematic signal processing performed inside the first delay adjustment apparatus 100 and the second delay adjustment apparatus 200. FIG. 5 is a diagram showing an example of a schematic data structure of a signal input or output in each process shown in FIG.

  Specifically, FIG. 5A illustrates an example of a schematic data structure of a signal that is input or output in each process at the normal time when the delay adjustment process is not performed. On the other hand, FIG. 5B shows an example of a schematic data structure of a signal input or output in each process at the time of delay adjustment.

  First, the following processing is performed in “test pattern generation processing S401, S451”. That is, the first delay adjustment apparatus 100 (signal generation unit 110) generates the first test pattern signal of an N / 2 bit string (S401).

  Further, the second delay adjustment device 200 (signal generation unit 210) generates the second test pattern signal of an N / 2 bit string (S451).

  Next, in the “LSB side all0 insertion processing S402, S452”, the following processing is performed. That is, the first delay adjustment apparatus 100 (for example, the transmission processing unit 120) inserts all 0s into the lower N / 2 bit string that follows the N / 2 bit string, that is, the LSB side of the N bit string (S402).

  Further, the second delay adjustment apparatus 200 (for example, the transmission processing unit 220) inserts all 0s into the lower N / 2 bit string subsequent to the N / 2 bit string, that is, the LSB side of the N bit string (S452).

  Next, in the “first switching process S403, S453”, the following process is performed. That is, the first delay adjustment apparatus 100 (for example, the transmission processing unit 120) switches between the path of the V polarization signal and the path of the first test pattern signal (S403). For example, the path of the V-polarized signal is selected during normal operation, and the path of the first test pattern signal is selected during delay adjustment. The signal of the selected path is output as the N bit string signal.

  Further, the second delay adjustment apparatus 200 (for example, the transmission processing unit 220) switches between the path of the H polarization signal and the path of the second test pattern signal (S453). For example, the path of the H polarization signal is selected during normal operation, and the path of the second test pattern signal is selected during delay adjustment. The signal of the selected path is output as the N bit string signal.

  Next, in “control bit addition processing S404, S454”, the following processing is performed. That is, the first delay adjustment device 100 (for example, the transmission processing unit 120) sets the control bits (the first control signal and the second control signal) for determining the normal time or the delay adjustment time to the “first control signal”. 1 ”is added to the LSB side of the N-bit string signal output from the switching process S403” (S404).

  Specifically, 1 bit is assigned to each of the first control signal and the second control signal, and a total of 2 bits are added. Here, in a normal state, the bit corresponding to the first control signal is set to 0. On the other hand, at the time of delay adjustment, the bit corresponding to the first control signal is set to 1. The bit corresponding to the second control signal is set to 0.

  Further, the second delay adjustment device 200 (for example, the transmission processing unit 220) sets the control bits (the first control signal and the second control signal) for determining the normal time or the delay adjustment time to the “first control signal”. 1 ”is added to the LSB side of the N-bit string signal output from the switching process S453” (S454). Here, in a normal state, the bit corresponding to the second control signal is set to 0. On the other hand, at the time of delay adjustment, the bit corresponding to the second control signal is set to 1. The bit corresponding to the first control signal is set to 0.

  Next, in the “bit string change processing S405, S455”, the following processing is performed. That is, the first delay adjustment device 100 outputs N output from the control bit addition process S404 so that the first delay adjustment device 100 and the second delay adjustment device 200 can simultaneously perform the delay adjustment processing. The bit string is divided into an upper N / 2 bit string and a lower N / 2 bit string, and a signal is assigned to each bit string (S405).

  Here, for example, the first test pattern signal transmitted by the transmission processing unit 120 is assigned to the upper N / 2 bit string. Further, for example, the second test pattern signal received by the reception processing unit 130 is assigned to the lower N / 2 bit string as the second test pattern return signal transmitted by the transmission processing unit 120. Furthermore, of the two bits following the lower N / 2 bit string, the first control signal is assigned to the upper bits, and the second control signal is assigned to the lower bits.

  Further, the second delay adjustment apparatus 200 outputs N output from the control bit addition process S454 so that the first delay adjustment apparatus 100 and the second delay adjustment apparatus 200 can simultaneously perform the delay adjustment process. The bit string is divided into an upper N / 2 bit string and a lower N / 2 bit string, and signal allocation is performed (S455).

  Here, for example, the second test pattern signal transmitted by the transmission processing unit 220 is assigned to the upper N / 2 bit string. Further, for example, the first test pattern signal received by the reception processing unit 230 is assigned to the lower N / 2 bit string as the first test pattern return signal transmitted by the transmission processing unit 220. Furthermore, of the two bits following the lower N / 2 bit string, the second control signal is assigned to the upper bits, and the first control signal is assigned to the lower bits.

  Next, in the “second switching process S406, S456”, the following process is performed. That is, the first delay adjustment apparatus 100 switches the path of the V polarization signal and the path of the test pattern signal (S406). The path of the V polarization signal is selected during normal operation, and the path of the test pattern signal is selected during delay adjustment.

  The second delay adjustment apparatus 200 switches the path of the H polarization signal and the path of the test pattern signal (S456). The path of the H polarization signal is selected during normal operation, and the path of the test pattern signal is selected during delay adjustment.

  Next, in “delay comparison processing S407, S457”, the following processing is performed. That is, the first delay adjustment device 100 (for example, the adjustment unit 140) reciprocates between the signal that does not pass through the XCVR 14 (the first test pattern signal) and the second demodulation device 20 (the first delay signal). (1 test pattern return signal) is calculated (S407). Here, the first delay adjustment device 100 (for example, the adjustment unit 140) assumes that the forward path and the return path have the same delay, and reduces the half delay amount corresponding to one way to the first polarization signal and the above-described first polarization signal. It is calculated as a delay amount generated before demodulation with the second polarization signal.

  In addition, the second delay adjustment device 200 (for example, the adjustment unit 240) reciprocates between the signal that does not pass through the XCVR 24 (the second test pattern signal) and the first demodulation device 10 (the first delay device). The delay amount with respect to (1 test pattern return signal) is calculated (S457). Here, the second delay adjustment device 200 (for example, the adjustment unit 240) assumes that the forward path and the return path have the same delay, and reduces the half delay amount corresponding to one way to the first polarization signal and the above-described first polarization signal. It is calculated as a delay amount generated before demodulation with the second polarization signal.

  Next, in “control bit deletion processing S408, S458”, the following processing is performed. That is, the first delay adjustment apparatus 100 deletes the control bits (the first control signal and the second control signal) added to the LSB side of the N-bit string signal (S408).

  The second delay adjustment apparatus 200 also deletes the control bits (the first control signal and the second control signal) added to the LSB side of the N-bit string signal (S458).

  Next, in “delay addition processing S409, S459”, the following processing is performed. In other words, the first delay adjustment apparatus 100 delays the first polarization signal and the second polarization signal so that the delay amount calculated in the delay comparison process S408 becomes a preset delay amount. Is output to the demodulator 15 (S409). Here, it is assumed that the delay amount set in advance is larger than the delay of the circuit processing.

  Further, the second delay adjustment apparatus 200 delays the first polarization signal and the second polarization signal so that the delay amount calculated in the delay comparison process S458 becomes a preset delay amount. Is output to the demodulator 25 (S459). Here, it is assumed that the delay amount set in advance is larger than the delay of the circuit processing.

  The processing shown in FIG. 4 has been described above. According to the processing shown in FIG. 4 described above, with the accuracy of the operation clock frequency for the delay amount of the own polarization signal and the different polarization signal in the digital circuit processing before input to the demodulation circuit (for example, the demodulation units 15 and 25) It becomes possible to automatically adjust to a fixed delay amount. Therefore, the process shown in FIG. 4 has an advantage that it is not necessary to manually adjust the delay amount for each device type. Further, according to the process shown in FIG. 4, the first delay adjustment device 100 and the second delay adjustment device 200 can simultaneously adjust the delay.

  As another embodiment, for example, when the signal delay is adjusted in a configuration in which a data signal is transmitted and received between a plurality of demodulating devices such as a MIMO (Multiple Input Multiple Output) configuration, the above-described FIG. The following process can be used.

<< 4. Second Embodiment >>
Subsequently, a second embodiment of the present invention will be described with reference to FIG. The first embodiment described above is a specific embodiment, but the second embodiment is a more generalized embodiment.

<4.1. Configuration of Delay Adjustment Device 300>
With reference to FIG. 6, the example of a structure of the delay adjustment apparatus 300 which concerns on 2nd Embodiment is demonstrated. FIG. 6 is a block diagram illustrating an example of a schematic configuration of the delay adjustment apparatus 300 according to the second embodiment. Referring to FIG. 6, the delay adjustment apparatus 300 includes a signal generation unit 310, a transmission processing unit 320, a reception processing unit 330, and an adjustment unit 340. Note that the delay adjustment device 300 may further include other components other than these components. That is, the delay adjustment device 300 can perform operations other than the operations of these components. Specific operations of the signal generation unit 310, the transmission processing unit 320, the reception processing unit 330, and the adjustment unit 340 will be described in detail later.

<4.2. Technical features>
Next, technical features according to the second embodiment will be described.

  The delay adjustment device 300 (signal generation unit 310) generates a first test pattern signal indicating a test pattern of the first polarization signal that is demodulated by the first demodulation device. Then, the delay adjustment device 300 (transmission processing unit 320) transmits the first test pattern signal to the second demodulation device that demodulates the second polarization signal. Then, the delay adjusting device 300 (reception processing unit 330) receives the first test pattern return signal sent back from the second demodulator in response to the first test pattern signal. Then, the delay adjustment device 300 (adjustment unit 340) is configured so that the first polarization signal and the second polarization signal are based on the first test pattern signal and the first test pattern return signal. The amount of delay that occurs before demodulation is adjusted.

  For example, the signal generation unit 310 may perform the operation of the signal generation unit 110 according to the first embodiment described above. Further, the transmission processing unit 320 may perform the operation of the transmission processing unit 120 according to the first embodiment described above. In addition, the reception processing unit 330 may perform the operation of the reception processing unit 130 according to the first embodiment described above. The adjustment unit 340 may perform the operation of the adjustment unit 140 according to the first embodiment described above.

  The second embodiment has been described above. According to the second embodiment, for example, it is possible to adjust a delay amount difference that can occur in two polarization signals before demodulation.

<< 5. Other forms >>
As mentioned above, although embodiment of this invention was described, this invention is not limited to these embodiment. Those skilled in the art will appreciate that these embodiments are merely exemplary and that various modifications can be made without departing from the scope and spirit of the invention.

  For example, the steps in the processing described in this specification are not necessarily executed in time series in the order described in the sequence diagram. For example, the steps in the processing may be executed in an order different from the order described as the sequence diagram or may be executed in parallel. Also, some of the steps in the process may be deleted, and additional steps may be added to the process.

  In addition, a device (for example, a plurality of devices constituting the delay adjustment device (for example, a signal adjustment unit, a transmission processing unit, a reception processing unit, and / or an adjustment unit) including the components of the delay adjustment device described in this specification ( Or a unit), or a module for one of the plurality of devices (or units). In addition, a method including processing of the above-described components may be provided, and a program for causing a processor to execute the processing of the above-described components may be provided. Moreover, a non-transitory recording medium (Non-transitory computer readable medium) readable by a computer that records the program may be provided. Of course, such a device, module, method, program, and computer-readable non-transitory recording medium are also included in the present invention.

  Part or all of the above embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A signal generator that generates a first test pattern signal indicating a test pattern of a first polarization signal that is demodulated by the first demodulator;
A transmission processor that transmits the first test pattern signal to a second demodulator that demodulates the second polarization signal;
A reception processing unit for receiving a first test pattern return signal sent back from the second demodulator in response to the first test pattern signal;
Based on the first test pattern signal and the first test pattern return signal, a delay amount generated before demodulation between the first polarization signal and the second polarization signal is adjusted. And a delay adjustment device.

(Appendix 2)
The delay adjustment device according to appendix 1, wherein the first demodulation device performs cross polarization interference compensation of the first polarization signal using the second polarization signal with the delay amount adjusted.

(Appendix 3)
The reception processing unit further receives a second test pattern signal indicating a test pattern of the second polarization signal from the second demodulator,
The delay adjustment device according to appendix 1 or 2, wherein the transmission processing unit further transmits a second test pattern return signal to be sent back to the second demodulator in response to the second test pattern signal.

(Appendix 4)
The delay adjustment device according to appendix 3, wherein the transmission processing unit transmits an N-bit string signal (N is a natural number) including the first test pattern signal and the second test pattern return signal.

(Appendix 5)
N is a natural number of 2 or more,
The delay adjustment according to appendix 4, wherein the transmission processing unit transmits a signal in which the first test pattern signal is included in an upper N / 2 bit string and the second test pattern return signal is included in a lower N / 2 bit string. apparatus.

(Appendix 6)
6. The delay adjustment device according to appendix 4 or 5, wherein the transmission processing unit transmits a first control signal indicating presence / absence of the first test pattern signal in the N bit string signal.

(Appendix 7)
The delay adjustment device according to appendix 6, wherein the transmission processing unit transmits a second control signal indicating presence / absence of the second test pattern return signal in the N bit string signal.

(Appendix 8)
The delay adjustment device according to appendix 7, wherein the transmission processing unit transmits a signal obtained by adding the first control signal and the second control signal to the minimum bit side of the N-bit string signal.

(Appendix 9)
9. The delay adjustment device according to claim 4, wherein the reception processing unit receives the N-bit string signal including the first test pattern return signal and the second test pattern signal.

(Appendix 10)
N is a natural number of 2 or more,
The delay adjustment according to claim 9, wherein the reception processing unit receives a signal in which the upper N / 2 bit string includes the second test pattern signal and a lower N / 2 bit string includes the first test pattern return signal. apparatus.

(Appendix 11)
Generating a first test pattern signal indicating a test pattern of a first polarization signal to be demodulated by the first demodulator;
Transmitting the first test pattern signal to a second demodulator that demodulates a second polarization signal;
Receiving a first test pattern return signal sent back from the second demodulator in response to the first test pattern signal;
Based on the first test pattern signal and the first test pattern return signal, a delay amount generated before demodulation between the first polarization signal and the second polarization signal is adjusted. A method comprising:

(Appendix 12)
A first demodulator that demodulates a first polarization signal,
A signal generator for generating a first test pattern signal indicating a test pattern of the first polarization signal;
A transmission processor that transmits the first test pattern signal to a second demodulator that demodulates the second polarization signal;
A reception processing unit for receiving a first test pattern return signal sent back from the second demodulator in response to the first test pattern signal;
Based on the first test pattern signal and the first test pattern return signal, a delay amount generated before demodulation between the first polarization signal and the second polarization signal is adjusted. And a first demodulator.

  In the process of demodulating a polarization signal by cross polarization interference compensation (XPIC), it is possible to appropriately adjust the delay amount difference that may occur between the two polarization signals before demodulation.

DESCRIPTION OF SYMBOLS 1 Radio | wireless communication apparatus 100 1st delay adjustment apparatus 110,210,310 Signal generation part 120,220,320 Transmission process part 130,230,330 Reception process part 140,240,340 Adjustment part 200 2nd delay adjustment apparatus 300 Delay adjustment device

Claims (10)

A signal generator that generates a first test pattern signal indicating a test pattern of a first polarization signal that is demodulated by the first demodulator;
A transmission processor that transmits the first test pattern signal to a second demodulator that demodulates the second polarization signal;
A reception processing unit for receiving a first test pattern return signal sent back from the second demodulator in response to the first test pattern signal;
Based on the first test pattern signal and the first test pattern return signal, a delay amount generated before demodulation between the first polarization signal and the second polarization signal is adjusted. And a delay adjustment device.   2. The delay adjustment device according to claim 1, wherein the first demodulation device performs cross-polarization interference compensation of the first polarization signal using the second polarization signal with the delay amount adjusted. . The reception processing unit further receives a second test pattern signal indicating a test pattern of the second polarization signal from the second demodulator,
3. The delay adjustment device according to claim 1, wherein the transmission processing unit further transmits a second test pattern return signal to be sent back to the second demodulator in response to the second test pattern signal.   The delay adjustment device according to claim 3, wherein the transmission processing unit transmits an N-bit string signal (N is a natural number) including the first test pattern signal and the second test pattern return signal. N is a natural number of 2 or more,
5. The delay according to claim 4, wherein the transmission processing unit transmits a signal in which the first test pattern signal is included in an upper N / 2 bit string and the second test pattern return signal is included in a lower N / 2 bit string. Adjustment device.   6. The delay adjustment device according to claim 4, wherein the transmission processing unit transmits a first control signal indicating presence / absence of the first test pattern signal in the N bit string signal.   The delay adjustment apparatus according to claim 6, wherein the transmission processing unit transmits a second control signal indicating presence / absence of the second test pattern return signal in the N bit string signal.   The delay adjustment device according to claim 7, wherein the transmission processing unit transmits a signal obtained by adding the first control signal and the second control signal to a minimum bit side of the N bit string signal.   9. The delay adjustment device according to claim 4, wherein the reception processing unit transmits the signal of the N bit string including the first test pattern return signal and the second test pattern signal. 10. . N is a natural number of 2 or more,
The delay according to claim 9, wherein the reception processing unit receives a signal in which the upper N / 2 bit string includes the second test pattern signal and a lower N / 2 bit string includes the first test pattern return signal. Adjustment device.

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