JP2019164536A - Electronic apparatus and control method thereof - Google Patents

Abstract

To allow checking the occurrence states of errors when the errors occurred in chips elsewhere in an electronic apparatus in which a plurality of chips are cascade-connected.SOLUTION: There is provided an electronic apparatus including a cascade-connected plurality of chips, and that each chip comprises: transmitting means in which error signals indicating errors received from the chips elsewhere located in the subsequent section or error signals indicating errors occurred in the own chip are transmitted to the chips elsewhere located in the preceding section; writing means in which information relating to the error occurrence into a memory; and switching means in which the path of error signals received from the chips elsewhere located in the subsequent section is switched between a first path connecting to the transmitting means and a second path connecting to the writing means. The switching means is configured in a fashion that, as the initial state, the path is connected to the second path, and is configured in a fashion to switch thereof to the first path after the information is written in the memory.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an electronic device including a plurality of chips connected in series and a control method thereof.

  There is a multi-chip system in which a plurality of chips are connected in cascade. Each chip is monitored by a watchdog timer. For example, when an abnormal state (for example, a watchdog timer error) occurs due to a runaway of the CPU included in the chip, the watchdog timer provided in the chip detects the abnormal state and automatically Reset control for the chip is performed. In a multi-chip system, it is required to share an abnormal state that can occur in each chip with each chip. For example, if the CPU included in the chip goes out of control, control of the recording head and motor control cannot be performed normally, which may lead to a failure of the main body. For this reason, each chip that performs these controls is required to share an abnormal state, safely stop and reset the system.

  Patent Document 1 discloses an electronic device configured by connecting a plurality of control chips in cascade. A technique is disclosed in which a logical sum signal of a watchdog timer interrupt signal from another control chip input from the outside and a watchdog timer interrupt signal of its own chip is transmitted to the preceding chip. Also disclosed is a technique for resetting all of the own chip in which the watchdog timer is operated and the chip located at the subsequent stage.

JP 2006-224730 A

  With the technique of Patent Document 1, it is possible to safely reset the entire system. However, if the reset is performed before the error occurrence status is stored, information regarding the error occurrence status may not be stored in the memory. For this reason, it may be difficult to check the state when an error occurs.

  An object of the present invention is to make it possible to easily check an error occurrence state when an error occurs in another chip in an electronic device in which a plurality of chips are connected in cascade.

  An electronic device according to one embodiment of the present invention is an electronic device including a plurality of chips connected in series, and each chip is generated by an error signal indicating an error received from another chip located in a subsequent stage or by its own chip A transmission means for transmitting an error signal indicating the error to another chip located in the preceding stage, a writing means for writing information relating to the occurrence of the error in a memory, and a path of the error signal received from the other chip located in the subsequent stage. Switching means for switching between a first path connected to the transmission means and a second path connected to the writing means, and the switching means is connected to the second path in an initial state. And after the information is written to the memory, the connection is switched to the first path. .

  According to the present invention, in an electronic device in which a plurality of chips are connected in cascade, it is possible to easily check an error occurrence state when an error occurs in another chip.

It is a figure when a recording device is in a standby state. FIG. 3 is a block diagram illustrating a control configuration of a recording apparatus. It is a figure which shows the structure regarding a controller. It is a figure which shows the detailed structure of a chip | tip. It is a flowchart when an error occurs in the third chip. It is a flowchart when an error occurs in the second chip.

  Hereinafter, a recording apparatus according to an embodiment of the present invention will be described with reference to the drawings. The following embodiments do not limit the present invention, and all combinations of features described in the present embodiment are not necessarily essential to the solution means of the present invention. In the present embodiment, an inkjet recording apparatus will be described as an example of the electronic apparatus.

<Internal configuration of recording apparatus>
FIG. 1 is an internal configuration diagram of an ink jet recording apparatus 1 (hereinafter, recording apparatus 1). In the figure, the x direction indicates the horizontal direction, the y direction indicates the direction in which ejection openings are arranged in the recording head 8 described later, and the z direction indicates the vertical direction.

  The recording apparatus 1 is a multifunction machine including a printing unit 2 and a scanner unit 3, and executes various processes relating to a recording operation and a reading operation individually or in conjunction with the printing unit 2 and the scanner unit 3. Can do. The scanner unit 3 includes an ADF (Auto Document Feeder) and an FBS (Flatbed Scanner), and reads a document automatically fed by the ADF and reads a document placed on a document table of the FBS by a user ( Scanning).

  Here, a multi-function machine having both the print unit 2 and the scanner unit 3 is shown, but a configuration without the scanner unit 3 may be used. FIG. 1 shows a state in which the recording apparatus 1 is in a standby state in which neither a recording operation nor a reading operation is performed.

  In the print unit 2, a first cassette 5 </ b> A and a second cassette 5 </ b> B for accommodating a recording medium (cut sheet) S are detachably installed on the bottom portion of the casing 4 in the vertical direction.

  The conveyance roller 7, the discharge roller 12, the pinch roller 7a, the spur 7b, the guide 18, the inner guide 19, and the flapper 11 are conveyance mechanisms for guiding the recording medium S in a predetermined direction. The conveyance roller 7 is a driving roller that is arranged on the upstream side and the downstream side of the recording head 8 and is driven by a conveyance motor (not shown). The pinch roller 7 a is a driven roller that rotates while nipping the recording medium S together with the conveying roller 7. The discharge roller 12 is a drive roller that is disposed on the downstream side of the transport roller 7 and is driven by a transport motor (not shown). The spur 7 b sandwiches and transports the recording medium S together with the transport roller 7 and the discharge roller 12 disposed on the downstream side of the recording head 8. The discharge tray 13 is a tray for stacking and holding the recording medium S that has completed the recording operation and is discharged by the discharge roller 12.

  The recording head 8 is a full-line type color inkjet recording head, and a plurality of ejection openings for ejecting ink according to the recording data are arranged along the y direction in FIG. 1 corresponding to the width of the recording medium S. . When the recording head 8 is in the standby position, the ejection port surface 8a of the recording head 8 is capped by the cap unit 10 as shown in FIG. When performing the recording operation, the orientation of the recording head 8 is changed by the print controller 202 described later so that the ejection port surface 8 a faces the platen 9. The platen 9 is constituted by a flat plate extending in the y direction, and supports the recording medium S on which the recording operation is performed by the recording head 8 from the back side.

The ink tank unit 14 stores the four colors of ink supplied to the recording head 8. Here, the four color inks indicate cyan (C), magenta (M), yellow (Y), and black (K) inks. The ink supply unit 15 is provided in the middle of the flow path connecting the ink tank unit 14 and the recording head 8, and adjusts the pressure and flow rate of ink in the recording head 8 to an appropriate range. The recording apparatus 1 has a circulation type ink supply system, and the ink supply unit 15 adjusts the pressure of ink supplied to the recording head 8 and the flow rate of ink collected from the recording head 8 to an appropriate range.

  The maintenance unit 16 includes a cap unit 10 and a wiping unit 17, which are operated at a predetermined timing to perform a maintenance operation on the recording head 8.

<Control configuration of recording apparatus>
FIG. 2 is a block diagram showing a control configuration in the recording apparatus 1. The recording apparatus 1 includes a print engine unit 200 that mainly controls the printing unit 2, a scanner engine unit 300 that controls the scanner unit 3, a power supply unit 400, and a controller unit 100 that controls the entire recording apparatus 1. The print controller 202 controls various mechanisms of the print engine unit 200 in accordance with instructions from the main controller 101 of the controller unit 100. Various mechanisms of the scanner engine unit 300 are controlled by the main controller 101 of the controller unit 100. Details of the control configuration will be described below.

  In the controller unit 100, a main controller 101 including a CPU controls the entire recording apparatus 1 according to a program and various parameters stored in the ROM 107 while using the RAM 106 as a work area. The ROM 107 is an example of a non-volatile memory, and the RAM 106 is an example of a volatile memory. When a print job is input from the host apparatus 500 via the host I / F 102 or the wireless I / F 103, the image processing unit 108 performs predetermined image processing on the received image data in accordance with an instruction from the main controller 101. . The main controller 101 transmits image data subjected to image processing to the print engine unit 200 via the print engine I / F 105.

  The recording device 1 may acquire image data from the host device 500 via wireless communication or wired communication, or may acquire image data from an external storage device (such as a USB memory) connected to the recording device 1. Also good. When a read command is input from the host device 500, the main controller 101 transmits this command to the scanner engine unit 300 via the scanner engine I / F 109.

  The operation panel 104 is a mechanism for the user to input and output to the recording apparatus 1. The user can instruct operations such as copying and scanning, set a print mode, and recognize information of the recording apparatus 1 via the operation panel 104.

  In the print engine unit 200, a print controller 202 including a CPU controls various mechanisms included in the printing unit 2 while using the RAM 204 as a work area according to programs and various parameters stored in the ROM 203. The ROM 203 is an example of a non-volatile memory, and the RAM 204 is an example of a volatile memory. When various commands and image data are received via the controller I / F 201, the print controller 202 temporarily stores them in the RAM 204. The print controller 202 causes the image processing controller 205 to convert the stored image data into recording data so that the recording head 8 can be used for the recording operation. When the recording data is generated, the print controller 202 causes the recording head 8 to execute a recording operation based on the recording data via the head I / F 206 via the head control controller 211. In accordance with an instruction from the print controller 202, the recording operation by the recording head 8 is executed in conjunction with the conveying operation of the recording medium S, and printing processing is performed.

  The head carriage control unit 208 changes the orientation and position of the recording head 8 in accordance with an operation state such as a maintenance state or a recording state of the recording apparatus 1. The ink supply control unit 209 controls the ink supply unit 15 so that the pressure of the ink supplied to the recording head 8 falls within an appropriate range. The maintenance control unit 210 controls the operation of the cleaning mechanism such as the cap unit 10 and the wiping unit 17 in the maintenance unit 16 when performing a maintenance operation on the recording head 8.

  In the scanner engine unit 300, the main controller 101 controls hardware resources of the scanner controller 302 while using the RAM 106 as a work area according to programs and various parameters stored in the ROM 107. Thereby, various mechanisms provided in the scanner unit 3 are controlled. For example, when the main controller 101 controls hardware resources in the scanner controller 302 via the controller I / F 301, a document loaded on the ADF by the user is conveyed via the conveyance control unit 304 and is read by the sensor 305. . Then, the scanner controller 302 stores the read image data in the RAM 303. The print controller 202 can cause the recording head 8 to execute a recording operation based on the image data read by the scanner controller 302 by converting the image data acquired as described above into recording data. .

<Example of connecting multiple chips>
FIG. 3 is a diagram illustrating a configuration related to the controller. FIG. 3 shows a configuration in which a plurality of chips are connected. Hereinafter, a configuration in which a plurality of chips are connected is also referred to as a multi-chip system. The multichip system includes an external reset IC 701, a first chip 601, a second chip 602, and a third chip 603. Although other chips may be included, here, in order to simplify the description, it will be described as having three chips. Each chip is connected in cascade.

  The first chip 601 is a main controller chip corresponding to the main controller 101. The first chip 601 mainly serves as a main chip that manages the entire system such as I / F processing and power control. The second chip 602 and the third chip 603 are print controller chips corresponding to the print controller 202 and the image processing controller 205. The second chip 602 and the third chip 603 each perform a process sharing a role. For example, the second chip 602 is responsible for the movement of the recording head 8, the cleaning operation, the control of the motor and sensor relating to ink supply, and the control of half of the image processing. The third chip 603 is responsible for control of the motor that transports the recording medium S, control of half of the image processing, and data transfer to the recording head 8.

  The first chip 601, the second chip 602, and the third chip 603 are connected in a column as shown in FIG. The first chip 601 connected to the external reset IC 701 is assumed to be the preceding stage (upstream side). In FIG. 3, the third chip is the last stage (the most downstream) chip. Each chip can be controlled to be reset by a preceding chip or an external reset IC 701. For example, reset control by the external reset IC 701 is performed on the first chip 601. That is, a reset control signal is output from the external reset IC 701 to the first chip 601, and the first chip 601 is reset based on the reset control signal.

  For the second chip 602 and the third chip 603, reset control is performed using a general-purpose IO terminal of another chip located in the preceding stage of the own chip. For example, for the second chip 602, a reset control signal is output from a general-purpose IO terminal of the first chip 601 that is the preceding chip, and the second chip 602 is reset based on the reset control signal.

  Here, until the preceding chip rises (that is, until the general-purpose IO terminal of the previous-stage chip becomes controllable after reset), the general-purpose IO terminal of the previous-stage chip is in the input state. After the preceding chip rises, the general-purpose IO terminal can be controlled in the previous-stage chip, and the reset control of the next-stage chip can be performed by switching the general-purpose IO terminal to the output.

  In this embodiment, an external resistor is prepared, and the logic level until the general-purpose IO terminal of the previous-stage chip in the input state is switched to the output state and can be controlled is fixed. The logic level to be fixed is a logic level at which the chip (next-stage chip) to which the reset signal is connected is reset when the previous-stage chip is in the reset state. By doing so, for example, when the second second chip 602 is reset, the third third chip 603 that is controlled to be reset by the second chip can be automatically reset. That is, when the second chip 602 is reset, according to the reset, the logic level of the general-purpose IO terminal used for reset control is fixed to the logic level at which the next-stage chip is reset, and the third chip 603 is In response to this signal, it is reset.

  The reason why the rear stage chip can be reset when the front stage chip is reset in this way is that the front stage chip may control the rear stage chip, which occurs on the front stage side. This is to prevent the abnormalities from affecting the subsequent stage. In the present embodiment, the first chip 601 manages the entire system, and the subsequent chip controls the recording head 8 and the motor under the control of the first chip 601. If an abnormality occurs in the first chip 601 and the subsequent chip cannot be controlled correctly, the control state of the recording head 8 and the motor cannot be guaranteed if the subsequent chip is not reset. There is a fear.

  As described above, since the chip on the rear stage is reset in response to the reset of the chip on the front stage, it is possible to ensure safety. However, information indicating a situation where an error (abnormality) has occurred (hereinafter referred to as error information) may not be appropriately stored in the memory due to the reset process. For example, a reset process may be started before error information is stored in an external memory or the like. In this case, for example, the user or service person cannot grasp the situation in which the error has occurred. In the present embodiment described below, a configuration in which error information can be grasped will be described.

<Detailed configuration example of chip>
FIG. 4 is a diagram showing a detailed configuration of the chip. In FIG. 4, the detailed configuration will be described using the second chip 602 as an example. The second chip 602 has a CPU 604. The CPU 604 is connected to the external memory 605. In FIG. 4, the second chip 602 is taken as an example, but the first chip 601 and the third chip 603 also have the same configuration as FIG. That is, an external memory is connected to each chip. Note that FIG. 2 described above shows a functional configuration example, and a separate external memory different from the external memory 605 of the second chip 602 is also connected to the third chip 603. The external memory 605 corresponds to the ROM 203 in FIG. The external memory 605 may correspond to the RAM 204.

  The watchdog timer generation unit 607 has a function of outputting a WDT_INT signal when an abnormality is detected by the watchdog timer function. The watchdog timer is a timer that counts clocks, for example, and although it is possible to clear the count value, it cannot be stopped, and the count value is cleared at a predetermined timing. When the count value overflows without being cleared due to an abnormality or the like, a WDT_INT signal is output. In this embodiment, for easy understanding, the WDT_INT signal (error signal) may be called a WDT_INT external input signal or a WDT_INT external output signal depending on the mode. In the present embodiment, the count value overflowing without being cleared due to an abnormality or the like is called a watchdog timer error.

  The logic circuit 608 includes an OR gate that calculates a logical sum. The logic circuit 608 calculates a logical sum of the WDT_INT signal generated by the watchdog timer generation unit 607 of its own chip and the WDT_INT external input signal output from the third chip 603 and input to the second chip 602. The logic circuit 608 outputs a logical sum result to the first chip 601 as a WDT_INT external output signal. By passing the signal output from the logic circuit 608 to the first chip 601 in the previous stage, the watchdog timer interrupt signal WDT_INT generated in the chip located lower than itself is supplied to the first chip. Is possible.

  A selector 609 is present before the WDT_INT external input signal output from the third chip 603 and input to the second chip 602 is input to the logic circuit 608. The selector 609 can switch between a first path for connecting the WDT_INT external input signal to the logic circuit 608 and a second path for connecting the WDT_INT external input signal to the interrupt control unit 606. The selector 609 performs path switching according to a selector setting signal (setting value) from the CPU 604. The initial state of the set value of the selector 609 is “0”, and the selector 609 is in a state of outputting a WDT_INT external input signal to the interrupt control unit 606. When the set value of the selector 609 is set to ‘1’, the selector 609 is in a state of outputting a WDT_INT external input signal to the logic circuit 608.

  When receiving an interrupt detection signal from the interrupt control unit 606, the CPU 604 confirms an interrupt factor. Further, the CPU 604 writes information to the external memory 605 and outputs a selector setting signal for changing the setting of the selector 609.

<When watchdog timer interrupt occurs in the third chip 603>
FIG. 5 is a diagram illustrating an example of a processing flow when an error occurs in the third chip 603 positioned third. Hereinafter, an example in which an error occurs in the third chip 603 located third and the watchdog timer operates will be described with reference to FIGS. 4 and 5.

  In S31, a watchdog timer error occurs in the third chip 603. When a watchdog timer error occurs, the third chip 603 outputs a WDT_INT # 3 signal in S32. In S21, the WDT_INT # 3 signal (WDT_INT external input signal) is input to the selector 609 in the second chip 602 located second. The third chip 603 is then changed to a safe state by resetting the entire chip by a watchdog timer interrupt in S33. Details of the reset process by the watchdog timer interrupt generated in the own chip will be described later.

  In the second chip 602, the WDT_INT external input signal is input to the selector 609 in the second chip 602 in S21. Since the initial value of the setting value of the selector 609 is “0”, the selector 609 is connected to a path for outputting the WDT_INT external input signal to the interrupt control unit 606. Therefore, the WDT_INT external input signal is input to the interrupt control unit 606. In S <b> 22, the interrupt control unit 606 detects the input of the WDT_INT external input signal and transmits an interrupt detection signal to the CPU 604.

  In S23, the CPU 604 confirms from the interrupt detection signal that the WDT_INT external input signal from the third chip 603 has been input. The CPU 604 writes the information that the WDT_INT signal is input from the third chip 603 and the status and log information of the second chip 602 at that time in the external memory 605. Specifically, information such as the communication log between the second chip 602 and the third chip 603 and how far the sequence of the second chip 602 has progressed is written. As described above, the CPU 604 writes error information indicating a situation where an error has occurred in the external memory 605. It may be called status information because it indicates a situation where an error has occurred. When the writing to the external memory 605 is completed, in S24, the CPU 604 transmits a selector setting signal and changes the setting value of the selector 609 to “1”. A dedicated control unit may play a part or all of the roles played by the CPU 604 so far.

  While the set value of the selector 609 is “0”, no signal is output to the logic circuit 608. After the writing to the external memory 605 is completed, the setting value of the selector 609 is set to “1”, so that the WDT_INT external input signal is output to the logic circuit 608. As described above, in this embodiment, the WDT_INT signal is transmitted to the first chip 601 in the previous stage after the CPU 604 writes the error information in the external memory 605. For this reason, before the writing of the error information to the external memory 605 is completed, the reset processing of the own chip (second chip 602) is prevented from being operated by the reset processing by the control of the first chip 601 in the previous stage. be able to.

  In S25, the logic circuit 608 outputs a signal obtained by ORing the internal WDT_INT signal and the WDT_INT external input signal of the second chip 602 itself as a WDT_INT external output signal (WDT_INT # 2 signal). In this example, since a WDT_INT external input signal indicating that a watchdog timer interrupt has occurred is input, a WDT_INT external output signal indicating that a watchdog timer interrupt has occurred is output from the logic circuit 608. The WDT_INT external output signal output from the logic circuit 608 reaches the first chip 601 located first. Thereby, the first chip 601 managing the entire system recognizes that an abnormality has occurred in the second and subsequent chips. As described above, in the present embodiment, when an error occurs in the subsequent chip connected in cascade, there is a chip in which an error has occurred at least between the chips in which the error has occurred. Can share that. Further, since error information is written in the external memory 605, for example, as will be described later, a user or a service person can grasp the situation in which an error has occurred in more detail.

  Examples of the processing of the first chip 601 after the WDT_INT external output signal (WDT_INT # 2 signal) is input to the first chip 601 include two patterns of processing.

  In the first example, when the first chip 601 recognizes that an abnormality has occurred in the second and subsequent chips, the entire print engine unit 200 including the print controller 202 is immediately stopped to ensure safety. It is a form. In this case, when the first chip 601 recognizes that an abnormality has occurred in the second and subsequent chips, the power supply of the second chip 602 and the third chip 603, and the modules under their control. Performs processing to shut off the power. Alternatively, the first chip 601 performs control to reset the second chip 602 and the third chip 603. Here, when the configuration described in this embodiment is not employed, error information is not written to the external memory 605. Alternatively, even if the writing is performed, the writing is interrupted by the control from the first chip 601, and therefore it cannot be guaranteed that the error information is stored in the external memory 605. On the other hand, in the present embodiment, as described above, after the writing to the external memory 605 is completed, the WDT_INT # 2 signal is output to the first chip 601 in the previous stage. For this reason, after the writing of error information to the external memory 605 is completed, the power is shut off or reset control is performed. For this reason, it can be ensured that error information is stored in the external memory 605. Thereafter, for example, a user or a service person returns the shut-off power supply or releases the reset state for operation confirmation and failure analysis. In this example, a watchdog timer interrupt is generated in the third chip 603 and each status and log information of the second chip 602 are stored in the external memory 605. Therefore, the error information stored in the external memory 605 can be read out by the first chip 601 so that failure analysis at the time of a serviceman call or product design phase can be performed smoothly. The first chip 601 performs inter-chip communication (not shown) with the second chip 602, and the first chip 601 has an error in the external memory 605 connected to the second chip 602 via inter-chip communication. Information can be read out. That is, the first chip 601 is configured to be able to acquire error information of the external memory 605 connected to the second chip 602. In the first example, since the power supply is once cut off, a non-volatile memory (ROM) is preferably used as the external memory 605. Next, a second example will be described. In the second example, when the first chip 601 recognizes that an abnormality has occurred in the second and subsequent chips, the first chip 601 does not immediately perform power-off or reset processing of the subsequent chip, and the first chip 601 This is a form for confirming the location and situation of the occurrence. The flow of FIG. 5 shows a second example. In S11, the first chip 601 inputs a WDT_INT signal, which is a watchdog interrupt signal from the subsequent chip. In S12, the first chip 601 detects that a watchdog timer error has occurred in the subsequent chip. In S13, the first chip 601 reads out error information stored in the external memory 605 connected to the second chip 602 positioned second. As described above, the first chip 601 reads error information from the external memory 605 in the second chip 602 via inter-chip communication (not shown). In S <b> 14, the first chip 601 can specify from the read error information that a watchdog timer interrupt has occurred in the third third chip 603. Further, the first chip 601 can identify the situation at the time of occurrence of an error by reading each status and log information at the time of occurrence of the watchdog interrupt. In the second example, a nonvolatile memory (ROM) may be used as the external memory 605, or a volatile memory (RAM) may be used.

  For the first example and the second example, an example suitable for the product specification may be used, for example. Note that the second example describes a case where communication with the second chip 602 is possible. Hereinafter, a case where an error occurs in the second chip 602, that is, a mode in which the first chip 601 cannot read error information from the external memory 605 connected to the second chip 602 will be described. As a process of the second chip 602, the selector setting value is changed to 1 in S24, but the selector value of the second chip 602 returns to 0 by the subsequent reset control from the first chip to the second chip.

<When watchdog timer interrupt occurs in second chip 602>
FIG. 6 is a diagram illustrating an example of a processing flow when an error occurs in the second chip 602 positioned second. Hereinafter, an example in which an error occurs in the second chip 602 located second and the watchdog timer operates will be described with reference to FIGS. 4 and 6.

  In S51, a watchdog timer error occurs in the second chip 602. Then, a WDT_INT signal (internal) is transmitted from the watchdog timer generation unit 607 of the second chip 602 to the logic circuit 608. The logic circuit 608 of the second chip 602 performs an OR operation between the WDT_INT signal (internal) and the WDT_INT # 3 signal (WDT_INT external input signal) input from the selector 609. In this example, since a WDT_INT signal (internal) indicating that a watchdog timer interrupt has occurred is input, a WDT_INT external output signal indicating that a watchdog timer interrupt has occurred is output from the logic circuit 608. In S <b> 52, a WDT_INT external output signal (WDT_INT # 2 signal) is output from the second chip 602 to the first chip 601.

  In S41, the first chip 601 receives the WDT_INT # 2 signal. In S42, the first chip 601 detects that an error has occurred in the second and subsequent chips. At the same time, in S53, the second chip 602 changes to a safe state by resetting the whole chip by the watchdog timer function.

  Hereinafter, details of resetting the second chip 602 by the watchdog timer function of the second chip 602 will be described. When an error occurs in the second chip 602, an interrupt control signal is output from the interrupt control unit 606 to the CPU 604 in response to a WDT_INT signal (internal) output from the watchdog timer generation unit 607. Further, the second chip system reset signal is asserted from the reset control unit 610 in response to the WDT_INT signal (internal) output from the watchdog timer generation unit 607. The entire second chip 602 including the CPU 604 is reset by the second chip system reset signal. When the second chip 602 is reset, the general-purpose IO terminal of the second chip 602 changes to the input state as described above. For this reason, the third chip reset control signal assigned to one of the general-purpose IOs is in the input state. The third chip reset control signal is fixed to the reset state by an external resistor. The third chip reset control signal is input to a reset control unit (not shown) of the third chip 603. As a result, in the third chip 603, the third chip system reset signal is asserted and the entire third chip 603 is reset.

  As described above, when the second chip 602 is reset in S53, the third chip 603 for which reset control is performed by the second chip 602 is also reset in S61. Thereby, the third chip 603 can also be changed to a safe state. The continuation of the processing of the first chip 601 will be described. That is, the processing after the first chip 601 detects that an error has occurred in the second and subsequent chips in S42 will be described. In the subsequent processing, the first chip 601 cannot read the error information stored in the external memory 605 connected to the second chip 602 in both the first example and the second example. It is common. For example, in the first example in which power shutdown or reset processing is performed in order to immediately stop the entire system, the first chip 601 cannot read error information stored in the external memory 605 after the system is restarted. This is because when the error occurs in the second chip 602, the reset process of the second chip 602 is performed without writing to the external memory 605. That is, error information is not stored in the external memory 605. In addition, the first chip 601 reads out the error information stored in the external memory 605 even in the second example in which the watchdog interrupt occurrence location and situation are confirmed first, instead of immediately stopping the entire system. I can't. This is because communication with the second chip 602 cannot be performed even if the first chip 601 attempts to read error information stored in the external memory 605.

  When the reset due to the watchdog interrupt occurs in the second chip 602 as described above, the first chip 601 cannot read the error information stored in the external memory 605 connected to the second chip 602.

  Therefore, the first chip 601 that has detected that an error has occurred in S42 performs a process of reading the error information stored in the external memory 605 connected to the second chip 602 in S43, but fails. . Here, since the communication between the first chip 601 and the second chip 602 is not established, the reading process fails. Even if communication between the first chip 601 and the second chip 602 is established, the read process fails because the external memory 605 does not contain information in the first place. Therefore, in S44, the first chip 601 can specify that the watchdog timer interrupt generated in the subsequent chip is generated in the second chip 602. Also, the first chip 601 refers to the communication log between the first chip 601 and the second chip 602, information on how far the sequence of the first chip 601 has progressed, etc. Can be identified. Note that these pieces of information are stored in the external memory of the first chip 601.

  As described above, in this embodiment, when a watchdog timer interrupt is generated in the subsequent chip, or when a watchdog timer interrupt is generated in the own chip, an interrupt is generated in the subsequent stage or in the own chip. Communicate what happened. When a watchdog timer interrupt occurs in the subsequent chip, error information is written to the external memory connected to the chip itself. After the writing is completed, the fact that the watchdog timer interrupt has occurred in the subsequent stage or the own chip is transmitted to the preceding chip. According to such a configuration, when a watchdog timer interrupt occurs in any one of the chips located in the subsequent stage, the chip located in the previous stage identifies which chip caused the watchdog timer interrupt. Can do. In addition, it is possible to know the error occurrence status by reading the log and status information when the watchdog timer interrupt is generated stored in the external memory. Therefore, it is possible to smoothly perform failure analysis at the time of serviceman's failure handling or in the product design phase.

  Further, since the cause of the error and the situation at the time of the error can be specified, setting and sequence corresponding to the situation can be performed at the time of restart after reset. For example, it is assumed that the recording head 8 is in a standby state at the initial position when an error occurs, but the recording medium S is in the middle of conveyance. In this case, it is possible to execute a sequence in which the initial operation of the recording head 8 is not performed and only the initial operation of the transport unit is performed.

  Further, since the cause of the error and the situation at the time of occurrence of the error can be specified, the first chip 601 may perform processing for switching whether to reset the second chip 602 based on the cause of the error and the situation at the time of occurrence of the error. . For example, there is a case where the main controller 101 does not need to be reset, but the entire print engine unit 200 needs to be reset.

  In the above-described embodiment, an example in which chips are connected in cascade in three rows has been described as an example, but the present invention is not limited to this. It can also be applied to four or more cascade connection configurations. In addition, the chip of the main controller 101 and the print engine unit 200 has been described as an example, but the chip of the scanner engine unit 300 may be further included. Further, although the recording apparatus 1 has been described as an example of the electronic apparatus, the present invention is not limited to this. Any electronic device having a configuration in which a plurality of chips are connected in cascade can be used.

  Further, in the embodiment described above, the mode in which the chip at the foremost stage is responsible for resetting the entire system has been described as an example, but this is not restrictive. For example, in a configuration of four or more cascade connections, the second chip from the front stage may control the entire system. In this case, all the chips need not have the same configuration. For example, the frontmost chip that does not control resetting may have a different configuration. In this case, formally, the frontmost chip is also connected in cascade, but it is considered that a multichip system is formed that is connected in cascade by a plurality of chips excluding the frontmost chip. good. The same applies to the last chip.

601 First chip 602 Second chip 603 Third chip 605 External memory

Claims (9)

An electronic device including a plurality of chips connected in series,
Each chip is
A transmission means for transmitting an error signal indicating an error received from another chip located in the subsequent stage or an error signal indicating an error generated in the own chip to another chip located in the previous stage;
Writing means for writing into the memory information relating to the occurrence of the error;
Switching means for switching the path of the error signal received from the other chip located at the subsequent stage between a first path connected to the transmission means and a second path connected to the writing means;
With
The switching means is configured to connect to the second path in an initial state, and is configured to switch the connection to the first path after the information is written to the memory. Features electronic equipment.   The electronic apparatus according to claim 1, wherein the error signal is a watchdog timer interrupt signal indicating a watchdog timer interrupt.   3. The electronic device according to claim 2, wherein the information includes at least one of information specifying a chip in which the watchdog timer interrupt has occurred, a status when the watchdog timer interrupt has occurred, and log information. machine.   The electronic device according to claim 1, wherein the memory is provided for each chip, and each chip can write the information in a memory connected to the chip.   The other chip located in the preceding stage further comprises an acquisition means for acquiring the information written in the memory connected to the chip subsequent to itself in response to receiving the transmitted error signal. The electronic device according to claim 4.   The other chip located in the preceding stage further comprises a specifying means for specifying the chip located in the subsequent stage as the chip in which the error has occurred when the acquiring means cannot acquire the information written in the memory. The electronic device according to claim 5, characterized in that: The acquisition means can further acquire a communication log with its subsequent chip,
Other chips located in the previous stage are:
The electronic apparatus according to claim 5, further comprising: a reset control unit that outputs a reset signal to the subsequent chip based on the information acquired by the acquiring unit or the communication log. Each chip is
When reset processing is performed in the other chip located in the preceding stage, the reset processing of the own chip is performed in accordance with the reset signal output from the other chip, and the reset signal is output to the other chip located in the subsequent stage of the own chip. The electronic device according to claim 1, wherein the electronic device is an electronic device. A method for controlling an electronic device including a plurality of chips connected in series,
Each chip is
Writing information about an error indicated by an error signal received from another chip located in a subsequent stage to a memory;
After the writing is completed, the error signal received from the other chip located in the succeeding stage, the error signal received from the other chip located in the succeeding stage from the second path connected to the writing means, A step of switching to a first path connected to a transmission means for transmitting an error signal indicating an error occurring in the own chip to another chip located in the previous stage;
Is possible and
The method of controlling an electronic device, wherein the path of the error signal is configured to connect to the second path in an initial state.

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