JP2019161920A - Semiconductor switch control circuit, intelligent power module, switching power supply device, and semiconductor switch control method - Google Patents

Abstract

To provide a switching power supply device such as a ringing choke converter that prevents an uncontrollable state of the device due to the occurrence of large ringing, etc., controls the on/off state of a semiconductor switch, and converts an input/output voltage.SOLUTION: A semiconductor switch control circuit 1 that performs on/off control between a drain electrode D and a source electrode S by applying a gate voltage to a gate electrode G of a semiconductor switch 200 having the drain electrode D, the source electrode S, the gate electrode G, and body diode BD between the drain electrode D and the source electrode S, includes: a negative current detection unit 20 that detects a negative current flowing through a diode BD; and a correction control unit 40 that corrects the on/off control on the basis of information on the detected value of the negative current detected by the negative current detection unit 20.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor switch control circuit, an intelligent power module (IPM) having a semiconductor switch control circuit, a switching power supply device having an IPM having a semiconductor switch control circuit, and a method for controlling a semiconductor switch.

  There is a switching power supply device that supplies a predetermined power by controlling on / off of a semiconductor switch. Switching power supply device has excessive output current (excessive current, excessive current, overcurrent), semiconductor switch or switching power supply device is destroyed (overcurrent destruction), output voltage becomes excessive, and switching power supply device is destroyed In order to prevent this problem, various methods have been tried.

Japanese Patent Application Laid-Open No. 2004-228561 describes an invention that detects an excessive current flowing through a semiconductor switch to prevent overcurrent breakdown or the like.
Such a conventional example will be described with reference to FIG.
FIG. 21 shows a power conversion circuit (switching power supply device) 2000 using the semiconductor switch control circuit 1P.
On the input side of the power conversion circuit 2000, a rectifier circuit 3P is provided. The rectifier circuit 3P rectifies the AC voltage of the commercial AC power supply 2P and converts it into a DC voltage, which is used as the input voltage VIP of the power converter circuit 2000. The power conversion circuit 2000 has an input voltage of VIP and an input current of IIP. An input unit capacitor 4P is provided on the input side.
The input voltage VIP is voltage-converted by the insulating transformer 400. The output voltage is VOP and the output current is IOP. On the output side, a rectifying diode 500 and an output capacitor 600 are provided, and a load 700 is connected.

The switch semiconductor switch 200P (transistor) includes a drain electrode D1, a source electrode S1, and a gate electrode G1. By applying a gate voltage VG1 to the gate electrode G1, the drain electrode D1 and the source electrode S1 are turned on / off, an induced voltage is generated in the insulating transformer 400, and voltage conversion is performed.
The gate electrode G1 is controlled by the power supply control IC 100P. The semiconductor switch control circuit 1P detects that the current (switching current) IZ flowing between the drain electrode D1 and the source electrode S1 is an overcurrent by the excessive switching current detection circuit 800.

More specifically, the detection that the switching current IZ is an abnormal overcurrent is performed by inserting a resistor RZ in the current path of the switching current IZ and measuring a voltage drop VZ (potential difference between both ends of the resistor RZ) VZ. To do. Since the drop voltage VZ changes according to the magnitude of the switching current IZ, if the drop voltage VZ is larger than a voltage value corresponding to a predetermined overcurrent value, the switching current IZ is detected as an overcurrent.
In response to the detection result, the power supply control IC 100P changes the width of the pulse for turning on the gate voltage VG1 applied to the gate electrode G1 of the semiconductor switch 200P or changes the frequency of the pulse.

In Patent Document 1, the temperature change of the resistance value of the resistor RZ through which the switching current IZ flows is compensated.
Further, a feedback circuit F / B is provided that feeds back to the power supply control IC 100P when the output voltage VOP becomes excessive.

JP 2016-226112 A

  In general, in a switching power supply such as a ringing choke converter that controls input / output voltage by controlling on / off of a semiconductor switch, when the input voltage drops during startup, overload, instantaneous power failure, etc. When the input voltage is abnormal such as when the voltage rises, there is a problem that the switching current becomes excessive and the overcurrent breakdown or the overvoltage breakdown due to the increase of the ringing voltage occurs.

  In addition, with the development of next-generation devices, the switching speed is increasing. However, when the switching power supply switching (ON / OFF) speed is increased, the switching on / off timing of the semiconductor switch In some cases, a large surge voltage may be applied. Further, abnormal oscillation may occur due to parasitic capacitance, inductance, or the like, and control may be impossible. For example, there is a case where a parasitic oscillation loop is formed between the drain and the source of the MOSFET to cause parasitic oscillation.

However, it is difficult to solve these problems with the prior art such as Patent Document 1 described in FIG.
Although the prior art of FIG. 21 tries to prevent the switching power supply device and the like from being destroyed when the switching current becomes excessive, it is not always sufficient, and it is difficult to cope with high-speed switching. It was difficult.

  Therefore, the present invention provides a semiconductor switch control circuit that solves at least one of the above problems, an intelligent power module (IPM) having the semiconductor switch control circuit, a switching power supply device, and a method for controlling the semiconductor switch. For the purpose.

[1] A semiconductor switch control circuit according to the present invention includes a gate of a semiconductor switch having a first electrode, a second electrode, a gate electrode, and an internal or external diode between the first electrode and the second electrode. A semiconductor switch control circuit for performing on / off control between a first electrode and the second electrode by electrical control of an electrode, comprising: a negative current detection unit that detects a negative current flowing through a diode; and at least a negative current detection unit And a correction control unit that corrects the on / off control based on information on the detected value of the detected negative current.

[2] In the semiconductor switch control circuit described above, the negative current detection unit may detect a negative current flowing through the diode by detecting a current flowing between the first electrode and the second electrode.

[3] The semiconductor switch control circuit described above can be a control circuit when the diode of the semiconductor switch is mainly a body diode between the first electrode and the second electrode.

[4] In the semiconductor switch control circuit described above, the diode of the semiconductor switch includes a body diode between the first electrode and the second electrode and a diode other than the body diode between the first electrode and the second electrode. The control circuit can be used.

[5] In the semiconductor switch control circuit described above, the correction control unit can be a correction control unit that corrects the on / off control when the negative current detected by the negative current detection unit is predetermined.

[6] In the semiconductor switch control circuit described above, the correction control unit includes a gate-on signal time width correction control unit that corrects the on-signal time width of the gate voltage based on information on the detected value of the negative current. May be.

[7] In the semiconductor switch control circuit described above, the correction control unit includes a gate current correction control unit that corrects the current value of the gate current flowing through the gate electrode based on information on the detected value of the negative current. Also good.

[8] In the semiconductor switch control circuit described above, the gate current correction control unit stores the gate current in the gate source current for charging the capacity of the gate electrode (input capacity) and the capacity of the gate electrode (input capacity). It is also possible to correct and control at least one of the gate sink current that discharges the charged charges.

[9] In the semiconductor switch control circuit described above, the correction control unit may include a gate voltage correction control unit that corrects the voltage value of the gate voltage based on information on the detected value of the negative current. Good.

[10] The correction control unit may perform correction control either when the input power supply connected to the semiconductor switch control circuit is activated or when the input voltage of the semiconductor switch control circuit is abnormal.

[11] In the semiconductor switch control circuit described above, the semiconductor switch control circuit further includes a storage unit that stores reference value related information of a negative current flowing through the diode, and the correction control unit is detected by the negative current detection unit. The on / off control may be corrected based on the information related to the detected value of the negative current and the reference value related information stored in the storage unit.

[12] The intelligent power module of the present invention can be configured to include a semiconductor switch and the semiconductor switch control circuit described above.

[13] In the intelligent power module, at least one semiconductor switch among a gallium nitride semiconductor switch, a silicon carbide semiconductor switch, a gallium oxide semiconductor switch, and a diamond semiconductor switch can be used as the semiconductor switch.

[14] A switching power supply device of the present invention can include the above-described intelligent power module.

[15] A method of controlling a semiconductor switch according to the present invention includes: an electrical gate electrode of a semiconductor switch having a first electrode, a second electrode, a gate electrode, and a diode between the first electrode and the second electrode. A control method of a semiconductor switch for performing on / off control between a first electrode and a second electrode by control, a detection step (detection step) for detecting a negative current flowing through a diode, and a negative current detected by the detection step And a correction control step (correction control step) for correcting the on / off control based on the information on the detected value.

A semiconductor switch control circuit according to the present invention includes a gate electrode of a semiconductor switch having a first electrode, a second electrode, a gate electrode, and a diode (built-in or external diode) between the first electrode and the second electrode. A semiconductor switch control circuit that performs on / off control between the first electrode and the second electrode by electrical control of the negative current detection unit that detects a negative current flowing through the diode, and is detected by the negative current detection unit A correction control unit that corrects the on / off control based on information on the detected value of the negative current.
Thus, paying attention to the negative current flowing through the diode between the first electrode and the second electrode of the semiconductor switch, since it has a negative current detection unit for detecting the negative current, the on / off of the semiconductor switch is controlled to input / output A switching power supply or the like that converts voltage can accurately detect at least one of an input voltage abnormality at startup, an input voltage abnormality at an overload, and an input voltage abnormality at an instantaneous power failure.
And since the correction control part which correct | amends on / off control based on the information regarding the detected value of the negative current detected by the negative current detection part is provided, abnormal vibration arises at the time of starting etc., and on / off control of a semiconductor switch It is possible to suppress the occurrence of an abnormality such as the inability to do so.
As a result, a large surge voltage is applied to the semiconductor switch in at least one of suppression of overcurrent when the input voltage is abnormal, suppression of overvoltage breakdown when the input voltage is abnormal, and suppression of ringing when performing high-speed switching. It is possible to suppress at least one of suppression of the occurrence of control and abnormal control due to abnormal oscillation.

1 is a circuit diagram showing a semiconductor switch control circuit 1, an intelligent power module 100, and a switching power supply device 1000 according to Embodiment 1. FIG. 2A, 2B, and 2C are explanatory diagrams of a method for detecting a negative current in the semiconductor switch control circuit 1 according to the first embodiment. 3 is an explanatory diagram of a current detection element used in the semiconductor switch control circuit 1 according to the first embodiment. FIG. 4A and 4B are explanatory diagrams showing the operation of the semiconductor switch 200 in a normal state, where FIG. 5A is a timing chart of the gate voltage VGS, FIG. 5B is a timing chart of the gate current IG, FIG. ) Is a timing chart of the switching current ISW. 4A and 4B are explanatory diagrams showing the operation of the semiconductor switch 200 in an abnormal state, where FIG. 5A is a timing chart of the gate voltage VGS, FIG. 5B is a timing chart of the gate current IG, FIG. ) Is a timing chart of the switching current ISW. FIG. 4 is a timing chart explanatory diagram in the case where the semiconductor switch control circuit 1 according to the first embodiment performs correction control of the ON time width of the gate voltage VGS, where (a) is a timing chart of the gate voltage VGS, and (b) is a gate current IG. (C) is a timing chart of the drain voltage VDS, (d) is a timing chart of the switching current ISW, (e) is a timing chart of the overnegative current detection signal DT, and (f) is a pulse width restriction command signal PW. It is a timing chart. FIG. 3 is a circuit diagram of a control unit that performs on-time width correction control in the semiconductor switch control circuit 1 according to the first embodiment. FIG. 3 is a timing chart explanatory diagram in the case of performing current value correction control of the gate current IG in the semiconductor switch control circuit 1 according to the first embodiment, where (a) is a timing chart of the gate voltage VGS, and (b) is a timing chart of the gate current IG. (C) is a timing chart of the drain voltage VDS, (d) is a timing chart of the switching current ISW, (e) is a timing chart of the overnegative current detection signal DT, and (f) is a timing chart of the gate current limit command signal GI. It is. 3 is a circuit diagram of a control unit that performs current value correction control of a gate current in the semiconductor switch control circuit 1 according to the first embodiment. FIG. FIG. 4 is a timing chart explanatory diagram when gate voltage correction control is performed in the semiconductor switch control circuit 1 according to the first embodiment, where (a) is a timing chart of the gate voltage VGS, (b) is an IG timing chart of the gate current, and (c). Is a timing chart of the drain voltage VDS, (d) is a timing chart of the switching current ISW, (e) is a timing chart of the overnegative current detection signal DT, and (f) is a timing chart of the gate voltage limit command signal GV. FIG. 3 is a circuit diagram of a control unit that performs gate voltage correction control in the semiconductor switch control circuit according to the first embodiment. It is a circuit diagram of the modification of the control part which performs gate voltage correction control with a semiconductor switch control circuit. It is a circuit diagram which shows the semiconductor switch control circuit 1, the intelligent power module 100, and the switching power supply device 1000 which concern on Embodiment 2 whose diodes are diodes (external diode) other than a body diode. It is explanatory drawing of embodiment at the time of deform | transforming the semiconductor switch 200 into 200Z. FIGS. 15A and 15B are diagrams illustrating examples of diodes of the semiconductor switch 200 used in the second embodiment. FIG. 4 is a control explanatory diagram of the semiconductor switch control circuit 1 in the case of an abnormality, where (a) is an explanatory diagram when the power supply is abnormal and (b) is an explanatory diagram when the input voltage is abnormal. It is a figure explaining the gate source current and gate sink current in the semiconductor switch 200 which is the control object of the semiconductor switch control circuit 1 of the present invention. FIG. 3 is an explanatory diagram of a circuit that includes a storage unit (reference value memory) that stores a reference value of a negative current flowing through a diode (body diode BD and / or external diode BDO) and performs correction control in the semiconductor switch control circuit 1 of the present invention. . 4 is an explanatory diagram when a gallium nitride semiconductor switch is used as the semiconductor switch 200. FIG. 6 is an explanatory diagram in the case where there is a capacitance between a first electrode (drain electrode) D and a second electrode (source electrode S) of the semiconductor switch 200. FIG. It is explanatory drawing of a prior art example.

  Hereinafter, a semiconductor switch control circuit, an IPM having the semiconductor switch control circuit, a switching power supply device, and a semiconductor switch control method of the present invention will be described based on the embodiments shown in the drawings. Each drawing is a schematic diagram, and does not necessarily accurately reflect an actual structure, circuit, timing chart, and the like. Further, the circuits, timing charts, and the like of the following embodiments show examples of circuits and the like, and the present invention is not limited to these circuits and the like.

1. Description of Embodiment 1 [Embodiment 1]
(1) Overall Configuration FIG. 1 is a circuit diagram showing a semiconductor switch control circuit 1, an intelligent power module (IPM) 100, and a switching power supply device 1000 according to the first embodiment.
The IPM 100 and the switching power supply apparatus 1000 include a semiconductor switch 200. The semiconductor switch control circuit 1 controls on / off and the like of the semiconductor switch 200 (described in an n-channel MOSFET, n-channel Metal Oxide Semiconductor Field Effect Transistor).

The switching power supply 1000 will be described. The input power supply 2 is connected to the input side of the switching power supply 1000. The input power source 2 is, for example, a commercial AC power source, and is rectified by the rectifier circuit 3 and converted into a DC voltage, which is used as the input voltage VI and the input current II of the switching power supply device 1000 and the IPM 100. The input power supply 2 may be a DC power supply. An input capacitor 4 is provided on the input side as necessary for smoothing the voltage.
The input voltage VI is converted by the insulation transformer 400 to obtain the output voltage VO. The output current is IO. On the output side, a rectifying diode 500 and a smoothing output unit capacitor 600 are provided as necessary.

The switching power supply apparatus 1000 has an IPM 100. With the IPM 100 in which the main part of the power supply device is modularized, the switching power supply device 1000 can be easily configured.
The IPM 100 has a module configuration including the semiconductor switch 200, the semiconductor switch control circuit 1, the insulating transformer 400, and the like. T1 to T4 and TVDD are provided as terminals of the IPM. T1 to T4 are input terminals T1 and T2 for input voltage VI (ground terminal (GND terminal) in FIG. 1), output voltage VO terminal T3, and the other output voltage terminal T4 (ground terminal (GND terminal) in FIG. 1). It is. There is TVDD as a driving power supply terminal for the internal circuit.
In FIG. 1, the switching power supply apparatus 1000 has an IPM 100 as a core and further has an input capacitor (smoothing capacitor) 4 on the input side.

  The terminal TVDD will be described. It is convenient to provide the input terminal TVDD as a terminal for supplying the power supply VDD of the semiconductor switch control circuit 1 as shown in FIG. Note that the input terminal TVDD is not provided, and the semiconductor switch control circuit 1 or the IPM 100 uses the input voltage input to the terminal T1 and uses an operational amplifier (operational amplifier, abbreviation for operational amplifier, low consumption of 0 operational amplifier). A power voltage generation circuit may be provided as the power supply VDD. Alternatively, there is a method of dividing the input voltage VI by resistance to generate the voltage VDD, but power is consumed by the resistance division.

  The semiconductor switch 200 includes a drain electrode D that is a first electrode, a source electrode S that is a second electrode, and a gate electrode G. A diode (BD) is provided between the first electrode D and the second electrode S of the semiconductor switch 200. Here, an example in which a body diode BD is formed as a diode is shown.

  The body diode BD is a diode formed between the drain electrode (first electrode) D and the source electrode (second electrode) S, and is formed by a PN junction between the drain electrode D and the source electrode S. Also called a parasitic diode or internal diode. The body diode BD is inevitably formed due to the structure of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, metal oxide semiconductor field effect transistor).

  The following description will be given in the case where the body diode BD is formed as an example of the diode. However, when a diode other than the body diode (external diode, etc.) is formed, both the body diode and the diode other than the body diode are provided. The same applies to the case where it is used. This will be described later with reference to FIGS.

  As described above, the semiconductor switch 200 includes the first electrode (drain electrode) D, the second electrode (source electrode) S, the gate electrode G, and the diode (body diode BD) between the first electrode D and the second electrode S. And). The semiconductor switch control circuit 1 performs on / off control between the first electrode D and the second electrode S by electrically controlling the gate electrode G of the semiconductor switch 200 by the gate electrode drive control unit 10.

In the present invention, the semiconductor switch control circuit 1 is based on a negative current detection unit 20 that detects a negative current flowing through a diode (body diode BD), and information on a detected value of the negative current detected by the negative current detection unit 20. And a correction control unit 40 that corrects the on / off control of the semiconductor switch 200.
In FIG. 1, the switching current is indicated by ISW, the current (negative current) flowing through the diode BD is indicated by ID, and the voltage between the first electrode D and the second electrode S is indicated by VDS.

The correction control unit 40 corrects the on / off control of the semiconductor switch 200 when the negative current ID detected by the negative current detection unit 20 is predetermined.
The correction control unit 40 corrects the ON signal time width of the gate voltage (voltage between the gate electrode G and the second electrode S) VGS based on the information regarding the detected value of the negative current (the gate on signal time width correction control unit is Or the current value of the gate current IG flowing through the gate electrode G is corrected (having a gate current correction control unit), or the voltage value of the gate voltage VGS is corrected (having a gate voltage correction control unit). can do.

  In addition, you may further provide the memory | storage part 30 which memorize | stores the reference value relevant information of the negative current which flows through a diode (body diode BD).

(2) The negative current detection semiconductor switch control circuit 1 includes a gate electrode drive control unit 10, a negative current detection unit 20, and a correction control unit 40 that corrects on / off control. 30.

  The gate electrode drive control unit 10 performs on / off control of the semiconductor switch 200 by controlling the gate (electrically controlling the gate electrode G).

  The negative current detection unit 20 detects a negative current ID that flows through a diode (body diode BD) between the first electrode D and the second electrode S. The reference value related information related to the reference value such as abnormality of the negative current ID may be stored in the storage unit 30.

  The correction control unit 40 corrects the control of the gate (gate electrode G) by the gate electrode drive control unit 10 (on / off control of the semiconductor switch 200). When the negative current is detected by the negative current detector, the on / off control is corrected based on the information regarding the detected value of the negative current. When a negative current is detected by the negative current detection unit 20 and a correction command is issued by the correction control unit 40, the gate electrode drive control unit 10 corrects the control and controls the gate electrode G. For example, the ON signal time width of the gate voltage VGS is corrected, the current value of the gate current IG flowing through the gate electrode G is corrected, or the voltage value of the gate voltage VGS is corrected. When performing such correction, the reference value related information of the negative current stored in the storage unit 30 may be referred to.

The negative current detection unit 20 that detects the negative current ID flowing through the diode (body diode BD) between the first electrode D and the second electrode S is very important, but can be configured by various methods (circuits).
2A, 2B, and 2C are explanatory diagrams of various methods (examples of detecting a negative current) for detecting a negative current in the semiconductor switch control circuit 1 according to the first embodiment.

  In the circuit of FIG. 2A, a resistor RBD is inserted on the anode side of the body diode BD formed between the first electrode D and the second electrode S (between the anode of the body diode BD and the second electrode S) (body). A resistor RBD may be inserted on the cathode side of the diode BD (between the cathode of the body diode BD and the first electrode D). A voltage drop DVBD (voltage across the resistor RBD) due to the resistor RBD is detected by the voltage detector DV, and the detected voltage is converted into a current value by the V / I (voltage / current) conversion circuit VIT, whereby the body diode BD. The negative current ID flowing through is detected.

The current value flowing through the resistor RBD is a value obtained by dividing the voltage value VRBD by the resistance value RBD. Therefore, if the voltage value VRBD is divided by the resistance value RBD, the V / I (voltage / current) conversion circuit VIT is not provided. Even current values can be detected. Alternatively, a voltage / current correspondence table may be stored and converted into a current value corresponding to the measured voltage value.
In FIG. 2A, the switching current ISW is also shown.

  Here, “negative current” (ID) refers to a current flowing in the forward direction through the body diode BD. When the semiconductor switch 200 is viewed as a whole, the switching current ISW flows from the first electrode D side to the second electrode S side in the on state. In the off state, the switching current ISW does not flow.

  However, in an abnormal state, a current may flow from the second electrode S side to the first electrode D side through the body diode BD, which is referred to as a negative current. 1 and 2A to 2C, the current flows from the lower side to the upper side of the body diode BD. (Note that depending on the conditions of the input voltage VI, the transformer 400, and the like, exceptionally, a resonance may occur due to the capacitance between the drain and source of the switch 200, which is a MOSFET, and the inductance of the transformer 400, and a negative current may flow.)

  “Switching current” (ISW) refers to a current switched by the semiconductor switch 200. This includes not only the current that flows between the first electrode D and the second electrode S when the semiconductor switch 200 is on, but also the current that flows through the electric circuit via the diode (BD) when the semiconductor switch 200 is off.

  FIG. 2B is an explanatory diagram of a method for detecting the negative current of the body diode BD by detecting the switching current ISW of the semiconductor switch 200. A resistor RS is inserted in the electric path through which the switching current ISW flows. The voltage across the resistor RS is detected by the voltage detector DV. The V / I (voltage / current) conversion circuit VIT converts the measurement voltage (voltage drop due to the resistor RS) into a current value.

  Here, the current that flows through the resistor RS is the switching current ISW that flows through the semiconductor switch 200, and is a current that combines the current that flows between the drain electrode D and the source electrode S and the current that flows through the diode (body diode BD).

  Whether or not the switching current ISW is a negative current ID flowing through the body diode BD can be determined (detected) by the direction of the switching current ISW, the on / off state of the semiconductor switch 200, and the like.

When the semiconductor switch 200 is on, the switching current ISW flows between the first electrode D and the second electrode S, but the switching current ISW does not flow through the body diode BD.
On the other hand, in principle, when the semiconductor switch 200 is off, the switching current ISW does not flow between the first electrode D and the second electrode. However, the switching current ISW may flow depending on the input voltage state or the like, which is the negative current of the body diode BD. It is. In this case, the switching current ISW is almost the negative current ID, and thus the switching current ISW can be detected.

As described above, whether or not the switching current ISW is the negative current ID flowing through the body diode BD depends on the direction of the switching current ISW, the on / off state of the semiconductor switch 200, and the like (applied voltage state to the gate electrode G). The determination is made directly or indirectly based on the relationship between the potential of the first electrode D and the potential of the second electrode S (whether the potential of the first electrode D is higher or lower than the potential of the second electrode S) or the like ( Detection).
Note that, in each of the on state and the off state, a minute current that cannot be compared with the switching current ISW and the negative current ID described in this specification will be ignored. Ignoring has little effect on the present invention.

  FIG. 2C is an explanatory diagram in the case of detecting the negative current ID flowing through the body diode BD by measuring the switching current ISW, as in FIG. In the method of FIG. 2B, the switching current ISW is measured by putting the resistor RS in the circuit of the switching current. However, in the method of FIG. 2C, the switching current ISW is measured without putting the resistor RS in the circuit. For example, the switching current ISW is measured in a non-contact state on the switching current path by using the Rogowski coil COI and the integration circuit INT.

A method of measuring the negative current ID using the Rogowski coil COI will be described with reference to FIG.
The Rogowski coil COI is configured by surrounding a circuit WI through which a switching current ISW passes with a loop. The Rogowski coil COI is wrapped around a thin thin plastic tube and surrounded by an insulator. The Rogowski coil (both ends of the coil) COI is connected to the integration circuit INT. The integration circuit INT is composed of an operational amplifier OPEC (using an operational amplifier as an integrator, an operational amplifier: an operational amplifier, an operational amplifier), a resistor ROP, and a capacitor COP. One end of the coil is connected to the plus side input part of the operational amplifier OPEC, and the other end is connected to the minus side input part via the resistor ROP. The negative side input unit and output unit of the operational amplifier OPEC are connected via a capacitor COP. When a current as shown in the figure (time is on the horizontal axis and current intensity is on the vertical axis) ISW flows in the circuit of the switching current ISW, an induced power is generated in the coil. This is integrated by the integration circuit INT to generate a voltage VOP proportional to the switching current ISW.

  Thereby, the switching current ISW can be measured. When the switching current ISW is negative (when the current flows from the second electrode S side to the first electrode D side), the semiconductor switch 200 is off in that state, and thus the negative current ID flows through the body diode BD. It becomes. In this way, the negative current of the body diode BD can be measured.

  The semiconductor switch control circuit 1 according to the first embodiment includes a correction control unit 40 that corrects on / off control of the semiconductor switch 200 when the negative current detected by the negative current detection unit 20 is predetermined. The correction control unit 40 corrects the ON signal time width of the gate voltage VGS, corrects the current value of the gate current IG flowing through the gate electrode G, or corrects the gate voltage VGS based on information on the detected value of the negative current. Correct the voltage value of. This point will be described.

(3) Relationship between negative current and various phenomena
(3) -1 Normal State FIGS. 4A to 4D are diagrams illustrating the relationship between the negative current of the body diode BD and various phenomena.
4A is a timing chart of the gate voltage VGS (the horizontal axis is time, the vertical axis is the gate voltage VGS), and FIG. 4B is a timing chart of the gate current IG (the horizontal axis is time, and the vertical axis is the gate current IG (current). (Value)), (c) is a timing chart of the drain voltage VDS (the horizontal axis is time, the vertical axis is the drain voltage VDS), and (d) is the timing chart of the switching current ISW (the horizontal axis is time, the vertical axis is the switching current ISW). (Current value)).

A state where the switching power supply apparatus 1000 is normal will be described with reference to FIGS.
As shown in FIG. 4A, an ON gate voltage VGS (ON signal pulse, ON signal voltage) is applied to the gate electrode G of the semiconductor switch 200 at the timing T0.
(When the gate voltage VGS is equal to or higher than the gate threshold voltage, the semiconductor switch 200 is turned on.
Here, the gate voltage VGS is ideally a rectangular wave (the dotted waveform in FIG. 4A). However, in reality, the gate voltage VGS is not an ideal rectangular wave due to the influence of the threshold voltage of the semiconductor switch, stray capacitance, and the like.

When the semiconductor switch 200 is turned on, when the gate voltage VGS is turned on at the timing of T0, the gate voltage VGS rises, but does not rise to the saturation voltage at once, but rises to some extent and then slightly delays from the timing of T0. The rising curve is changed at the timing of T01, and it rises to T02 and becomes almost saturated voltage.
When the semiconductor switch 200 is turned off, the gate voltage VGS decreases at the timing T03. It becomes almost zero at the timing of T1, which is slightly delayed from T03.

The gate voltage VGS that is turned on is not applied to the gate electrode G during the period from T1 to T2 (an off voltage lower than the gate threshold voltage is applied). In FIG. 4A, the gate voltage VGS is equal to or lower than the gate threshold voltage during the period from T1 to T2.
The gate voltage VGS off control voltage (off control signal) does not necessarily have to be 0 volts. It may be less than (less than) the gate threshold voltage to be turned on / off. The same applies to the ON control voltage (ON control signal) as long as it is equal to or higher than (or exceeds) the gate threshold voltage to be turned ON / OFF.

Although it is an ON period starting from T2, the gate voltage VGS rises at T2 similarly to the timing of T0, but does not rise to the saturation voltage at once, and almost saturates at a timing slightly delayed from T2.
When turning off, similarly to the timing of T1, the gate voltage VGS starts to decrease at a timing slightly before T3 and becomes almost zero at T3.

The gate voltage VGS (gate threshold voltage) that is turned on is not applied to the gate electrode G during the period from T3 to T4.
The gate voltage VGS rises at T4 in the same manner as the timings T0 and T2, but starts at T4. However, the gate voltage VGS does not rise to the saturation voltage at once, but almost rises at a timing slightly later than T4.
In the case of turning off, the gate voltage VGS starts to decrease at a timing slightly before T5, as in the timings of T1 and T3, and becomes substantially zero at T5.

FIG. 4B is a timing chart of the gate current IG.
When the semiconductor switch 200 is turned on, when the gate voltage VGS on signal is applied to the gate electrode G at the timing of T0 (at the rise of the gate voltage VGS), the gate current IG flows as a positive current. The gate current IG increases rapidly at the timing T01 slightly delayed from the timing T0 and then rises, and then decreases rapidly to zero.
When the semiconductor switch 200 is turned off, when the gate voltage VGS falls from the saturation voltage at the timing of T03 (at the falling timing of the gate voltage VGS), the gate current IG flows in the negative direction and then becomes substantially zero (the gate voltage VGS becomes zero). When the saturation voltage is reached, the gate current IG becomes almost zero).

The area surrounded by the current curve and time of the gate current IG (positive current) when the semiconductor switch 200 is turned on (the area in the positive direction of the gate current IG), and the gate current IG (when the semiconductor switch 200 is turned off) The area surrounded by the current curve (negative current) and time (area of the gate current IG in the negative direction) is almost equal. These can be regarded as a charging current and a discharging current of the input capacitance of the gate electrode G (such as a stray capacitance formed in the gate electrode G).
The timings T2 and T4 are the same as those at the timing T0, and the cases T3 and T5 are the same as those at the time T1.

FIG. 4C is a timing chart of the drain voltage VDS.
When the semiconductor switch 200 is turned on, when the ON gate voltage VGS is applied at the timing T0, the drain voltage VDS is in a saturated state (a state of a saturated voltage between the first electrode D and the second electrode S) with a slight delay from T0. Rapidly decline.
When the semiconductor switch 200 is turned off, the drain voltage VDS rapidly rises (goes to the off state) when the gate voltage VGS falls at the timing T03 slightly before T1. At this time, the waveform is slightly oscillated.
The timings T2 and T4 are the same as those at the timing T0, and the cases T3 and T5 are the same as those at the time T1.

FIG. 4D is a timing chart of the switching current ISW.
When the semiconductor switch 200 is turned on, the switching current ISW continues to rise from the zero level (off state) at the timing of T0 and is almost saturated. More specifically, the rising curves of T0 to T01 and T01 are different. After the rise from T0, the rise once becomes gentle (stagnation and decreases in some cases) and continues to rise again from T01.
When the semiconductor switch 200 is turned off, when the gate voltage VGS decreases at the timing T03 slightly before T1, the switching current ISW rapidly decreases and eventually becomes zero.
The timings T2 and T4 are the same as those at the timing T0, and the cases T3 and T5 are the same as those at the time T1.

4A to 4D, the waveforms between T2 to T3 and T4 to T5 are similar to those between T0 to T1, and the waveforms between T3 to T4 are similar to those between T1 to T2.
4A to 4D, the time axis (horizontal axis) is aligned, but the gate voltage VGS (FIG. 4A) and the drain voltage VDS (FIG. 4C) voltage ( The vertical axis) is not necessarily the same scale. The current (vertical axis) of the gate current IG (FIG. 4A) and the switching current ISW (FIG. 4C) are not necessarily the same scale.

In the normal case, there are some exceptions (for example, when the input voltage VI is low, etc.), but in general, the waveform of the switching current ISW in FIG. ) Is a normal waveform example), the current value is positive and not negative. It can be seen that no negative current flows.
In some cases, the current value may be slightly negative, but the value is small.

(3) -2 Abnormal State A case where the switching power supply apparatus 1000 is abnormal (becomes an abnormal operating state) will be described with reference to FIGS. 5A to 5D, such as the drain voltage VDS causing ringing. FIG. 5 illustrates an example in which the input voltage VI falls below the rated input voltage range, and in this case, the switching current ISW abnormally increases. 5A is a timing chart of the gate voltage VGS, FIG. 5B is a timing chart of the gate current IG, FIG. 5C is a timing chart of the drain voltage VDS, and FIG. 5D is a timing chart of the switching current ISW.

The gate voltage VGS in FIG. 5A and the gate current IG in FIG. 5B are substantially the same as the timing charts in FIGS. 4A and 4B, respectively (the gate voltage in FIG. 5A). For VGS, there is vibration in the waveform at T1, T3, and T5). The timings at T01 and T02 are the same as those in FIG.
FIG. 5C is a timing chart of the drain voltage VDS.
In the case of turning on the semiconductor switch 200, when the ON gate voltage VGS is applied at the timing T0, the drain voltage VDS rapidly decreases from the saturated state with a slight delay from T0 (from the OFF state to the ON state rapidly). . After further lowering the zero level (VDSD), it rises to zero.
When the semiconductor switch 200 is turned off, the drain voltage VDS rapidly rises (goes to the off state) when the gate voltage VGS decreases at the timing T03 slightly before T1. At this time, the waveform is greatly waved (ringing, VDSR) and eventually converges.

The switching current ISW will be described (FIG. 5 (d)).
When turning on the semiconductor switch 200, the switching current ISW rises after dropping from zero at the timing of T0.
When the semiconductor switch 200 is turned off, when the gate voltage VGS decreases at the timing of T03 slightly before T1, the switching current ISW rapidly decreases, falls below zero, and then exceeds zero. Thus, it becomes a large vibration waveform (ISWR) that repeatedly rises and falls below zero, and eventually converges to zero (FIG. 5D).
5A to 5D, the waveform between T2 and T3, between T4 and T5 is the same waveform as between T0 and T1, and between T3 and T4 is the same waveform as between T1 and T2.

  When large ringing as shown in FIG. 5C occurs in the drain voltage VDS, the semiconductor switch 200, the IPM and the switching power supply device are destroyed by the large ringing voltage (overvoltage). Overcurrent) (FIG. 5 (d)), and problems such as destruction of the semiconductor switch 200 and the like, and occurrence of abnormal oscillation and difficulty in control.

(4) Correction Control Unit The correction control unit 40 corrects the on / off control of the semiconductor switch 200 based on the information regarding the detection value of the negative current detected by the negative current detection unit 20.
The “information regarding the negative current detection value” means information related to the negative current detection value. For example, a negative current detection value itself, a value obtained by increasing or decreasing a negative current detection value, and the like.
For example, when “information regarding the detected value of negative current” is “detected value of negative current”, the correction control unit 40 turns on / off when the negative current detected by the negative current detecting unit 20 is a predetermined value. Correct the control. “Negative current is predetermined (value)” means “negative current has been detected / detected (negative current has exceeded 0)”, “negative current has exceeded (or has exceeded) predetermined value”, “negative” It means either “current is less than or equal to a predetermined value (or less)” or “negative current is in a certain range”.

The correction control unit 40 may include a gate-on signal time width correction control unit that corrects the on-signal time width of the gate voltage based on information regarding the detected value of the negative current.
Further, the correction control unit 40 may include a gate current correction control unit that corrects the current value of the gate current flowing through the gate electrode based on information on the negative current detection value.
The correction control unit 40 may include a gate voltage correction control unit that corrects the voltage value of the gate voltage based on information on the detection value of the negative current.
The gate-on signal time width correction control (part), the gate current correction control (part), and the gate voltage correction control (part) may be combined.
When correcting and controlling the gate current, the gate current correction control unit accumulates the gate source current for charging the capacity (input capacity) of the gate electrode and the capacity (input capacity) of the gate electrode as the gate current. You may make it carry out correction control of at least 1 of the gate sink current which discharges an electric charge.

  The correction control unit 40 may be incorporated in the gate electrode drive control unit 10, or the correction control unit 40 may also serve as the gate electrode control unit 10 (or the gate electrode drive control unit 10 may be the correction control unit 40. May also serve as). In some cases, it is difficult to clearly separate the gate electrode control unit 10 and the correction control unit 40. The correction control unit 40 can be broadly understood as a control unit (control circuit) that corrects the on / off control based on the detected value of the negative current.

(5) Gate-on signal time width control (gate-on signal time width correction control) of the gate voltage VGS applied to the gate electrode G
With reference to FIGS. 6A to 6F, a case where the semiconductor switch control circuit 1 according to the first embodiment performs on-signal time width control of the gate (gate electrode G) (gate-on signal time width control) will be described with reference to a timing chart. To do. In this example, gate-on signal time width correction control for correcting the on-signal time width of the gate voltage VGS is performed based on information on the detected value of the negative current.
6A is a timing chart of the gate voltage VGS, FIG. 6B is a timing chart of the gate current IG, FIG. 6C is a timing chart of the drain voltage VDS, FIG. 6D is a timing chart of the switching current ISW, and FIG. A timing chart of the overnegative current detection signal DT, and (f) is a timing chart of the pulse width restriction command signal PW.
FIG. 7 is a circuit diagram of a drive control unit (correction control unit) that performs on-signal time width control correction of the gate voltage VGS in the semiconductor switch control circuit 1 according to the first embodiment, and will be described in conjunction with FIG.

The correction control at the time of abnormality will be described.
6A to 6D, the waveform indicated by the dotted line indicates a state before correction (during an abnormal state in which a large ringing occurs in the drain voltage VDS). The solid line is the waveform after correction control.
The waveforms before correction indicated by dotted lines in FIGS. 6A to 6D are the same as the waveforms in FIGS. 5A to 5D in the abnormal state. The explanation is the same.
6 and FIG. 7 will be schematically described. However, the description of FIG. 5 or FIG. 4 is applied for details, and description thereof is omitted here.

When an ON gate voltage VGS (ON pulse) is applied to the gate electrode G at the timing of T0 (FIG. 6A), the drain voltage VDS is temporarily negative (VDSD) in an abnormal state (FIG. 6C). The switching current ISW is negative (is ISWD (FIG. 6D)), which is a negative current flowing through the diode BD.
The switching current is detected by the switching current detector DISW, but converted to a voltage value by the current / voltage conversion circuit IVT and used as a comparator (comparator) OPER (an operational amplifier is used as a comparator (comparator). “Comparator”). May be rephrased as “op-amp”), an overnegative current detection signal DT is output (FIG. 7, FIG. 6E). (Dotted line 20 is a negative current detector.)

When the overnegative current detection signal DT is output, the one-shot pulse PONES1 is output from the one-shot circuit ONES1, and the pulse width limit command signal PW of the gate voltage VGS is output from the gate electrode application pulse width limit command circuit INSG1 (FIG. 6 (f)). .
The pulse width restriction command signal PW is input to the gate electrode drive control unit 10, and the gate electrode drive control unit 10 controls the pulse width of the drive pulse (ON signal) of the gate electrode G (the pulse width of the gate voltage VGS before correction is set). (Narrow) (FIG. 6A).
When the pulse width (ON signal pulse width) of the gate voltage VGS (gate voltage pulse) is narrowed, the rising timing of the drain voltage VDS (drain voltage waveform) is advanced, and the ringing (VDSR) at the time of rising becomes small or almost absent (FIG. 6). (C))).
In addition, the timing of falling of the switching current ISW is advanced, and the oscillation (ISWR) at the time of falling is reduced or almost eliminated (FIG. 6D).
The gate current IG is as shown in FIG.

  As described above, in an abnormal state, ringing occurs in the drain voltage VDS (waveform VDSR), or large oscillation occurs in the switching current ISW (waveform ISWR). In the present invention, as a precursor, the switching current ISW also has a negative waveform. Focusing on the fact that the ISWD is output, the negative waveform ISWD of the switching current ISW, that is, the negative current of the diode is detected and the pulse width of the ON signal of the gate voltage VGS (gate applied pulse) is corrected and controlled. Suppresses ringing and the like.

This will be described in more detail.
As shown in FIG. 7, a current detector DISW of the switching current ISW is installed in the electric path through which the switching current flows, using a non-contact Rogowski coil COI in the electric circuit, resistors RBD, RS, etc. to be inserted in the electric circuit. The switching current ISW (FIG. 6 (d)) detected by the switching current detector DISW is converted into a voltage by the current / voltage conversion circuit IVT and converted into a voltage corresponding to the magnitude of the current. The output IVTO of the current / voltage conversion circuit IVT is input to one input side (+ side) of the comparator OPER.

In some cases, the current detector DISW is used to detect a current regardless of whether the switching current ISW is a positive current or a negative current, or only a negative current is detected. Either method is acceptable. However, if only a negative current is detected, subsequent processing may be facilitated.
Further, when a voltage corresponding to the switching current ISW is generated by the switching current detector DISW, the current / voltage conversion circuit IVT is not necessary.

  A comparison voltage (VREF) corresponding to a predetermined negative value of the switching current ISW illustrated in FIG. 6D is input to the other input side (− side) of the comparator OPER as a comparison value of the comparator OPER. The comparison value is set to a threshold value that causes abnormal oscillation when the ringing becomes larger or lower. The comparator OPER raises the overnegative current detection signal DT when the switching current ISW falls to a constant value in the negative direction, and exceeds when the switching current ISW rises from a minimum value and becomes a negative constant value again. The negative current detection signal DT falls (FIG. 6 (e)). The overnegative current detection signal DT can be said to be a signal that detects an overnegative current having a magnitude corresponding to the occurrence of abnormal oscillation due to large ringing in the drain voltage VDS.

  The output of the comparator OPER (overnegative current detection signal DT) is input to the one-shot circuit ONES1. The one-shot circuit ONES1 raises the one-shot pulse PONS1 at the rise of the output of the comparator OPER (overnegative current detection signal DT) (TPW1), and falls after a predetermined period (TPW2). The output PONES1 of the one-shot circuit ONES1 is input to the gate electrode application pulse width restriction command circuit INSG1, and the pulse width control signal PW shown in FIG.

The pulse width restriction command signal PW is input to the gate electrode drive control unit 10. The gate electrode drive control unit 10 is a circuit that generates a drive control signal for the gate electrode G. A gate electrode drive voltage is generated from the power supply VDD (a drive pulse for the gate electrode G is generated). The pulse width of the gate electrode drive pulse is corrected by the pulse width restriction command signal PW (applied to the gate electrode G). The period of the saturation voltage of the gate voltage VGS is shortened) (FIG. 6A).
Note that IVTO, which is the output of the current / voltage conversion circuit IVT, is input to the gate electrode application pulse width restriction command circuit INSG1, and the gate electrode application pulse width restriction command circuit INSG1 receives a command signal PW corresponding to the magnitude of the switching current ISW. May be generated.
In this way, the gate electrode drive control unit 10 sets the gate electrode G so that the gate electrode application pulse width is improved when the switching current ISW is large (when the negative current is large) compared to when the negative current is small. To drive.
Alternatively, the gate electrode application pulse width command circuit INSG1 may be omitted, and the pulse width control signal PW may be output from the one-shot circuit ONES1 (the output PONS1 of the one-shot circuit ONES1 is input to the gate electrode drive control unit 10). The pulse width control signal PW may be used).
The one-shot circuit ONES1 and the gate electrode application pulse width restriction command circuit INSG1 may be configured such that the pulse width of the pulse width restriction command signal changes depending on the magnitude of negative current, temperature, and the like.

In this way, the gate voltage VGS (gate electrode application pulse) has a saturation voltage time width (on-pulse width, on-signal time width) that is wide before correction (dotted line) becomes narrow after correction (solid line).
As a result, the gate current IG changes as shown in FIG.

Then, the large ringing (VDSR) of the drain voltage VDS is reduced or eliminated. The risk of overvoltage breakdown due to large ringing is suppressed. The risk of abnormal oscillation is also suppressed.
Note that the output INVO of the current / voltage conversion circuit IVT may also be input to the gate electrode application pulse width restriction command circuit INSG1, and the ON signal pulse width may be changed according to the magnitude of the negative current (for example, negative When the current is large, an example is given for S which makes the ON signal pulse width smaller).
In addition, large oscillation (ISWR) of the switching current ISW is also reduced. Overcurrent breakdown due to an excessive switching current ISW is also suppressed.
In the examples of FIGS. 6 and 7 described above, the switching current detector DISW, or a circuit including the current / voltage conversion circuit IVT and the comparator OPER corresponds to the negative current detection unit 20. A circuit including the gate electrode application pulse width command circuit INSG1 or the one-shot circuit ONES1 corresponds to the correction control unit 40.

(6) Current value control of gate current flowing through the gate electrode (gate current correction control)
The case where the semiconductor switch control circuit 1 according to the first embodiment performs correction control of the gate current IG (gate current correction control) will be described using timing charts with reference to FIGS.
This is an example of correcting and controlling the current value of the gate current flowing through the gate electrode based on the information related to the detected value of the negative current.
8A is a timing chart of the gate voltage VGS, FIG. 8B is a timing chart of the gate current IG, FIG. 8C is a timing chart of the drain voltage VDS, FIG. 8D is a timing chart of the switching current ISW, and FIG. A timing chart of the overnegative current detection signal DT, (f) is a timing chart of the gate current limit command signal GI.
FIG. 9 is a circuit diagram of a drive control unit that performs gate current correction control in the semiconductor switch control circuit 1 according to the first embodiment, and FIGS. 8 and 9 will be described together.

The correction control at the time of abnormality that causes large ringing in the gate voltage VGS will be described. Since there are many points in common with FIGS. 6A to 6F and FIG. 7, description of common points is omitted as much as possible.
A waveform indicated by a dotted line shows a state before correction (during an abnormality such as ringing (VDSR) in the drain voltage VDS). The solid line is the waveform after correction control.
The state before correction (FIGS. 8A to 8D) indicated by a dotted line is the same as the explanatory diagram at the time of abnormality (FIGS. 5A to 5D).
Although FIG. 8 and FIG. 9 will be schematically described, the details of FIG. 5 or FIG. 4 are applied for details, and description thereof is omitted here.

When the ON gate voltage VGS (ON pulse) is applied to the gate electrode G at the timing of T0 (FIG. 8A), the drain voltage VDS temporarily becomes negative (VDSD) in the abnormal state (FIG. 8C). . Then, the switching current ISW becomes negative (ISWD) (FIG. 8 (d)). This is a negative current flowing through the diode BD.
The switching current is detected by the switching current detector DISW, but is converted into a voltage value by the current / voltage conversion circuit IVT, the signal IVTO is input to the comparator OPER, and the overnegative current detection signal DT is output from the comparator OPER. (FIG. 9, FIG. 8 (e)).
When the overnegative current detection signal DT is output and input to the one-shot circuit ONES2, the one-shot pulse PONS2 is output from the one-shot circuit ONES2 and input to the gate current limit command signal generation circuit INSG2, and the gate current limit command signal GI is output. (FIG. 8F).

  As shown in FIG. 9, a resistor RVG (RVG1, RVG2,... RVGn-1) and a switch SWV (SWV1, SWV2,... SWVn) are directly or indirectly connected to the gate G. The gate current limit command signal generation circuit INSG2 receives the output PONS2 from the one-shot circuit ONES2 and the output from the current / voltage conversion circuit IVT, and the output PONS2 from the one-shot circuit ONES2 rises (see FIG. 8 (f)). Limit the gate current IG.

  The gate current limit command signal generation circuit INSG2 is supplied with IVTO that is the output of the current / voltage conversion circuit IVT, and the gate current limit command signal generation circuit INSG2 receives a command signal (for example, a negative current) according to the magnitude of the switching current ISW. (Command signal for reducing the gate current) may be generated when the current is large.

  When the switching current ISW is not a negative current (exactly, the current flowing through the diode, the current flowing through the diode is detected by detecting the switching current ISW), the switch SWV1 is turned on (the other switches SWV2,. ). In this case, the gate current IG is not limited.

  Even if the switching current ISW is a negative current, if the switching current ISW is a very small negative current, the switch SWV1 may be turned on (the other switches SWV2,... Are off), and the gate current IG may not be limited.

  When it is necessary to limit the gate current IG while the negative current of the switching current ISW is small, the switch SWV2 is turned on (the other switches SWV1,... Are off). Then, the gate current IG becomes a current flowing through the resistor RVG1, and the current value is limited accordingly.

When the negative current of the switching current ISW is further larger, the switch SWV3 is turned on (the other switches SWV1, SWV2,... Are turned off). Then, the gate current IG becomes a current flowing through the resistor RVG1 and the resistor RVG2, and the current value is further limited by that amount.
When n switches SWV are used, when the switch SWVn is turned on (the other switches SWV1, SWV2,... Are off), the gate current IG becomes a current that flows through all of the resistors RVG1 to RVGn-1, and further Value is limited.

As shown in FIG. 8B, the current amount of the gate current IG (dotted line) before correction decreases after the correction (solid line).
When the gate current IG is corrected, the large ringing (VDSR) at the rise of the drain voltage VDS is reduced or almost eliminated (FIG. 8C).
Further, the large vibration (ISWR) at the fall of the switching current ISW is reduced or almost eliminated (FIG. 8D).

  As described above, in the abnormal state, a large ringing occurs in the drain voltage VDS (waveform VDSR) and a large vibration occurs in the switching current ISW (waveform ISWR). Focusing on the appearance of the waveform ISWD, the negative waveform ISWD of the switching current ISW, that is, the negative current of the diode is detected and the gate current IG is corrected and controlled to suppress large ringing and the like.

This will be described in more detail.
The switching current detector DISW, current / voltage conversion circuit IVT, comparator OPER, overnegative current detection signal DT, comparison voltage VREF, and the like in FIG. 9 are the same as those in FIG.

  In the circuit shown in FIG. 9, the output of the comparator OPER (overnegative current detection signal DT) is input to the one-shot circuit ONES2. The one-shot circuit ONES2 raises the one-shot pulse PONES2PW at the rise of the output of the comparator OPER (overnegative current detection signal DT), and falls after a predetermined period. The output PONES2 of the one-shot circuit ONES2 is input to the gate current limit command signal generation circuit INSG2, and the gate current limit command signal GI shown in FIG.

The pulse width of the gate current limit command signal GI is, for example, not less than the time width during which the gate voltage VGS is saturated (switch-on state). When the switching current ISW rises at T0 and the gate voltage VGS decreases (shifts to the switch-off state), when the undulation ends largely near the timing T1, the timing may be set to the same level or longer. While the gate current limit command signal GI is output (during saturation), the current value of the gate current IG is suppressed.
The gate current limit command signal generation circuit INSG2 may be omitted, and the gate current limit command signal GI may be output from the one-shot circuit ONES2 (the output PONS2 of the one-shot circuit ONES2 may be used as the gate current limit command signal GI). Good).
Further, the output IVTO of the current / voltage conversion circuit IVT may be input to the gate current limit command signal generation circuit INSG2, and the gate current limit command signal may be changed according to the magnitude of the negative current (for example, the negative current is large). If so, issue a command signal to make the gate current smaller).

In the circuit of FIG. 9, the switch SWV (SWV1 to SWVn) and the resistor RVG (RVG1 to RVGn-1) are used to limit the gate current IG, but instead, a constant current source may be used.
For example, when the limit command signal GI is output from the gate current limit command signal generation circuit INSG2, the gate electrode G is connected to a constant current source, and the current flowing through the gate electrode G and the gate electrode G is set as the current flowing through the constant current source. The constant current supplied from the constant current source is a constant value current.
A plurality of constant current sources having different constant current magnitudes are provided, and one of the constant current sources corresponds to the magnitude of the current detected by the current / voltage conversion circuit INV (the magnitude of the negative current). A gate current IG connected to the gate electrode G and corresponding to the magnitude of the negative current may be supplied.

The constant current source may be only one of the constant current source of the current flowing in the direction of the gate electrode and the constant current source in the opposite direction, but it is more preferable to use both. If a negative current is detected, both constant currents are detected from the time of detection until the fall of the gate voltage (T1), a period in which T1 is slightly extended, or one cycle (from the time of negative current detection slightly after T0 to T2). A source is connected to the gate electrode.
Alternatively, when the gate current is positive, the constant current source in the positive direction is connected to the gate electrode, and when the gate current is negative, the constant current source in the negative direction is connected to the gate electrode. For example, when a negative current having a predetermined value is detected, a positive constant current source is connected to the gate electrode. When the gate voltage VGS falls, a constant current source in the negative direction is connected to the gate electrode.

When the value of the gate current IG decreases, the drain voltage VDS has little or almost no large ringing at the time of rising (when the switch is turned off) (FIG. 8C). The dotted line in FIG. 8C is smaller than the dotted line in the case where the gate current IG is not suppressed (before correction) when the gate current IG is suppressed (after correction), as shown by the solid line, to a level where there is no problem with large ringing. This is illustrated.
As a result, abnormal oscillation is suppressed. Overcurrent breakdown is also suppressed.

As a result of the suppression of the gate current IG (FIG. 8B), a large oscillation of the switching current ISW is also suppressed. As shown in FIG. 8D, the switching current ISW oscillated greatly (dotted line) when the gate current IG is not controlled (before correction) at the timing when the switch shifts from on to off (near T1). However, in a state where the gate current IG is limited (after correction), the vibration is reduced to a level where there is no problem (solid line) or almost eliminated.
As a result, overcurrent breakdown and the like are also suppressed.

Note that, as described above, the negative current generated at the rise of the gate voltage VGD is detected to control the gate current IG. Since the control is performed first when the switching current ISW flows in earnest, overcurrent breakdown may be further suppressed.
In the examples of FIGS. 8 and 9 described above, the switching current detector DISW, or a circuit including the current / voltage conversion circuit IVT and the comparator OPER corresponds to the negative current detection unit 20. The gate current limit command signal generation circuit INSG2 or a circuit including the one-shot circuit ONES2 and SWK corresponds to the correction control unit 40.

(7) Control of gate voltage value (gate voltage correction control)
A case where gate voltage control is performed in the semiconductor switch control circuit 1 according to the first embodiment (when gate voltage correction control is performed) will be described using timing charts with reference to FIGS.
This is an example of performing gate voltage correction control for correcting the voltage value of the gate voltage based on the information regarding the detected value of the negative current.
10A is a timing chart of the gate voltage VGS, FIG. 10B is a timing chart of the gate current IG, FIG. 10C is a timing chart of the drain voltage VDS, FIG. 10D is a timing chart of the switching current ISW, and FIG. A timing chart of the overnegative current detection signal DT, (f) is a timing chart of the gate voltage limit command signal GV.
FIG. 11 is a circuit diagram of a drive control unit that performs gate voltage control (correction) in the semiconductor switch control circuit according to the first embodiment, which will be described together with FIG.

The correction control at the time of abnormality that causes large ringing in the gate voltage VGS will be described. Since there are many points in common with FIGS. 6A to 6F, FIG. 7 and the like, description of common points is omitted as much as possible.
A waveform indicated by a dotted line indicates a state before correction (during an abnormality such as a large ringing (VDSR) in the drain voltage VDS). The solid line is the waveform after correction control.
The states before correction (FIGS. 10A to 10D) indicated by dotted lines are the same as the explanatory diagrams at the time of abnormality (FIGS. 5A to 5D).

In FIGS. 10A to 10D, a dotted line indicates a waveform before correction, which is the same as the waveforms in FIGS. 5A to 5D in the abnormal state. The explanation is the same.
Although FIG. 10 and FIG. 11 are schematically described, the details of FIG. 5 or FIG. 4 are applied for details, and the description thereof is omitted here.

  When the ON gate voltage VGS (ON pulse) is applied to the gate electrode G at the timing of T0 (FIG. 10A), the drain voltage VDS temporarily becomes negative (VDSD) in the abnormal state (FIG. 10C). . Then, the switching current ISW becomes negative (ISWD) (FIG. 10 (d)). This is a negative current flowing through the diode BD.

The switching current is detected by the switching current detector DISW, but is converted into a voltage value by the current / voltage conversion circuit IVT, and an overnegative current detection signal DT is output from the comparator OPER (FIGS. 11 and 10 (e)).
When the overnegative current detection signal DT is output, the one-shot pulse PONES3 is output from the one-shot circuit ONES3, the one-shot pulse PONS3 is input to the gate voltage limit command signal generation circuit INSG3, and the gate voltage limit command signal GV is output (FIG. 10 (f)).

The gate voltage VGS applied to the gate electrode G is corrected by the gate voltage restriction command signal GV.
The circuit of FIG. 11 will be described later. When the gate voltage limit command signal GV is output, the voltage value of the gate voltage VGS (pulse) applied to the gate electrode G is not corrected (dotted line) but after corrected (solid line). Lower (FIG. 10A).

When the voltage value of the gate voltage VGS is corrected, the large ringing (VDSR) at the rise of the drain voltage VDS is reduced or almost eliminated (FIG. 10C).
Further, the large vibration (ISWR) at the fall of the switching current ISW is reduced or almost eliminated (FIG. 10 (d)).

  As described above, in the abnormal state, a large ringing occurs in the drain voltage VDS (waveform VDSR) and a large vibration occurs in the switching current ISW (waveform ISWR). Focusing on the appearance of the waveform ISWD, the negative waveform ISWD of the switching current ISW, that is, the negative current of the diode is detected, and the gate voltage VGS is corrected and controlled to suppress large ringing and the like.

This will be described in more detail.
The switching current detector DISW, current / voltage conversion circuit IVT, comparator OPER, and overnegative current detection signal DT in FIG. 11 are the same as those in FIG.
As shown in FIG. 11, the output of the comparator OPER (overnegative current detection signal DT) is input to the one-shot circuit ONES3. The one-shot circuit ONES3 raises the one-shot pulse PONES3PW at the rise of the output of the comparator OPER (overnegative current detection signal DT), and falls after a predetermined period. The output PONES3 of the one-shot circuit ONES3 is input to the gate voltage limit command signal generation circuit INSG3, and the gate voltage limit command signal GV of FIG.

  The output pulse width of the gate voltage limit command signal GV is made longer than the time during which the gate voltage VGS is saturated (switch-on state). When the switching current ISW rises at T0 and the gate voltage VGS decreases (shifts to the switch-off state), when the undulation ends largely near the timing T1, the timing may be set to the same level or longer. While the gate voltage limit command signal GV is output (during the saturation state), the voltage value of the gate voltage VGS is suppressed.

  The gate voltage limit command signal generation circuit INSG3 may be omitted and the gate voltage limit command signal GV may be output from the one-shot circuit ONES3 (the output PONS3 of the one-shot circuit ONES3 may be used as the gate voltage limit command signal GV). Good).

When the gate voltage limit command signal GV is output, the magnitude (amplitude) of the gate voltage VGS is limited. FIG. 10A shows how the peak of the gate voltage VGS is limited.
Briefly, as shown in FIG. 11, when the gate voltage limit command signal GV is output, the gate voltage limit command signal GV is input to the gate drive voltage adjustment unit CGV. The gate drive voltage adjustment unit CGV is a circuit that generates a gate drive voltage (maximum value) from the power supply voltage VDD. When the gate voltage limit command signal GV is input, the gate drive voltage (maximum value) is lowered. The gate electrode drive control unit 10 drives the gate electrode G using the gate drive voltage adjusted by the gate drive voltage adjustment unit CGV.

For example, a lower voltage (VGS) is applied to the gate electrode G when the negative current is large. Alternatively, when the negative current flows for a long time, there is a method in which the voltage (voltage lower than the normal voltage) first applied to the gate electrode G is switched to a lower voltage after a certain time.
Note that IVTO, which is the output of the current / voltage conversion circuit IVT, is input to the gate voltage limit command signal generation circuit INSG3, and the gate voltage limit command signal generation circuit INSG3 receives a command corresponding to the magnitude of the switching current ISW (negative current). The signal GV may be generated.

  In this way, the gate drive voltage adjusting unit CGV generates a gate drive voltage having a smaller gate drive voltage (maximum value) when the switching current ISW is large (when the negative current is large) than when the negative current is small. This is supplied to the gate electrode drive control unit 10. Then, the gate electrode drive control unit 10 drives the gate electrode G with a more limited gate voltage (smaller gate voltage).

  As shown in FIG. 10A, when the peak of the gate voltage VGS (the gate voltage VGS at the time of abnormality shown by the dotted line) falls as shown by the solid line, the peak (dotted line) of the gate current IG in FIG. Lower (solid line). Alternatively, the area surrounded by the current value and time in the positive direction of the gate current IG, or the area surrounded by the current value and time in the negative direction of the gate current IG becomes small. Then, the large ringing (dotted line) at the switch-off timing T1 (T3, T5) when the gate voltage VDS is abnormal becomes small (solid line) or almost disappears, and abnormal oscillation is suppressed. In the switching current ISW, the large vibration (dotted line) at the timing T1 (T3, T5) when the switch is woven becomes small (solid line) or almost disappears.

  In the example of FIGS. 10 and 11 described above, the switching current detector DISW, or a circuit including the current / voltage conversion circuit IVT and the comparator OPER corresponds to the negative current detection unit 20. The gate voltage limit command signal generation circuit INSG3, or a circuit including the one-shot circuit ONES3 and SWV corresponds to the correction control unit 40.

Variation of Gate Voltage Voltage Control A semiconductor switch control circuit that performs gate voltage voltage control in a circuit different from FIG. 11 will be described with reference to FIG. The circuit of FIG. 12 is a circuit of a control unit that performs gate voltage correction control, as in FIG.
12, the same reference numerals as those in FIG. 11 have the same meaning as in FIG. The embodiment 1-2 using the circuit of FIG. 12 has much in common with FIG. The description of FIG. 11 etc. is used about the common content. The description of FIG. 10 used in conjunction with FIG. 11 is also incorporated. The description here is omitted as much as possible.

  In the circuit of FIG. 12, the resistor RVW (RVW1, RVW2,...) And the switch SWW (SWW1, SWW2,...) Are connected to the gate electrode G to which the gate voltage VGS is applied, and an abnormal negative current is detected. Then, the gate voltage VGS applied to the gate electrode G in the normal state is not applied to the gate electrode as it is, the voltage drops by the resistor RVW, and the dropped voltage is applied to the gate electrode G.

This will be described briefly from the detection of an abnormal negative current.
The switching current is detected by the switching current detector DISW, but is converted into a voltage value by the current / voltage conversion circuit IVT, and an overnegative current detection signal DT is output from the comparator OPER (FIGS. 12 and 10 (e)).
When the overnegative current detection signal DT is output (FIG. 10 (e)), the one-shot pulse PONES3 is output from the one-shot circuit ONES3, and the one-shot pulse PONS3 is input to the gate voltage limit command signal generation circuit INSG3. The signal GV is output (FIG. 10 (f)).

  In a normal state where no negative current is detected, in the circuit of FIG. 12, the output signal GV of the gate voltage limit command signal generation circuit INSG3 is an output signal GV indicating that no negative current is detected and is normal, and SWW1 is turned on. The other switches SWW2, SWW3,... Are turned off. The output signal GV of the gate voltage limit command signal generation circuit INSG3 does not limit the gate voltage VGS applied to the gate electrode G (the gate voltage VGS applied in a normal state) (does not limit the peak value of the gate voltage). . The gate voltage VGS (the gate voltage VGS applied in a normal state) is applied to the gate electrode G without being lowered. Even when a negative current is detected, the magnitude thereof is small, and the same may be applied when a problem such as abnormal oscillation due to ringing does not occur.

When the detected negative current value is a value that causes or may cause an abnormal state such as ringing, the gate voltage limit command signal generation circuit INSG3 turns off the switch SWW1, and switches SWW2, SWW3, .. Outputs an output signal GV that turns on one of the following. For example, when the switch SWW1 is turned off, the switch SWW2 is turned on, and the other switches SWW3, SWW4,... Are turned off, the gate voltage VGS is divided by the resistors RVW1, RVW2,. Then, the voltage dropped by the resistor RVW1 is applied to the gate electrode G via the switch SWW2 (FIG. 10A). Then, the ringing of the drain-source voltage VDS is suppressed (FIG. 10C). The vibration of the switching current ISW is suppressed (FIG. 10 (d)). The gate current IG is also suppressed (FIG. 10 (b)).
The magnitude (drop voltage width) of the gate voltage VGS may be changed corresponding to the magnitude of the negative current.

  In the embodiment 1-2 described with reference to FIG. 12, IVTO, which is the output of the current / voltage conversion circuit IVT, is input to the gate voltage limit command signal generation circuit INSG3 in the same manner as described in the first embodiment of FIG. The gate voltage limit command signal generation circuit INSG3 may generate the command signal GV corresponding to the magnitude of the switching current ISW (negative current). A command signal GV is generated as a signal for changing the switches SWW1, SWW2,... To be turned on / off according to the magnitude of the switching current ISW (negative current).

  For example, the gate voltage limit command signal generation circuit INSG3 turns off the switch SWW1, turns on the switch SWW2, when no negative current is detected (or a very small negative current that does not cause an abnormality such as lip ring), An output signal GV for turning off the switches SWW3, SWW4,. A gate voltage VGS that is not limited (the voltage is not lowered) is applied to the gate electrode G.

  When a large negative current is detected (when a negative current detection that may cause an abnormality such as a lip ring is detected), the gate voltage limit command signal generation circuit INSG3 turns off the switch SWW1 and switches An output signal GV for turning on SWW2 and turning off the other switches SWW3, SWW4,. The voltage dropped by the resistor RVW1 is applied to the gate electrode G via the switch SWW2.

  When a larger negative current is detected, the gate voltage limit command signal generation circuit INSG3 outputs an output signal GV that turns off the switches SWW1 and SWW2, turns on the switch SWW3, and turns off the other switches SWW4,. Then, the voltage dropped by the resistors RVW1 and RVW2 is applied to the gate electrode G via the switch SWW3. A voltage (lower voltage) that is more limited than when the switch SWW2 is turned on and the other switches SWW1, SWW3,... Are turned off is applied to the gate electrode G.

  When a larger negative current is detected, the gate voltage limit command signal generation circuit INSG3 outputs an output signal GV that turns on the switch SWW4 and turns off the other switches SWW1. Then, the voltage dropped by the resistors RVW1, RVW2, and RVW3 is applied to the gate electrode G through the switch SWW3. A much more limited voltage (lower voltage) is applied to the gate electrode G.

In the above description, the case where the ON signal time width of the gate voltage, the current value of the gate current flowing through the gate electrode and the voltage value of the gate voltage are individually controlled has been described. However, the control of the ON signal time width of the gate voltage is described. Control of the current value of the gate current flowing through the gate electrode, control of the ON signal time width of the gate voltage and control of the voltage value of the gate voltage, control of the current value of the gate current flowing through the gate electrode and control of the voltage value of the gate voltage And may be combined.
Alternatively, the control of the ON signal time width of the gate voltage, the control of the current value of the gate current flowing through the gate electrode, and the control of the voltage value of the gate voltage may be performed in combination.
In this way, more accurate control is possible.

(8) Information regarding the detection value of the negative current The “negative current” is the forward current of the body diode BD as described above. In FIG. 1, the current is indicated by a dotted line beside the body diode BD. In FIG. 5 (d), the switching current ISW is a current at a negative value (the same applies to FIGS. 6 (c), 8 (c), and 10 (c)).

The “information regarding the detected value of negative current” means the information related to the detected value of negative current as described above. For example, the negative current detection value itself, a value obtained by increasing or decreasing the negative current detection value, a value obtained by converting the negative current detection value into a symbol, or the like, or multiplying or dividing the negative current detection value by a certain value Etc., and some processed values.
The negative current detector may or may not include a negative current detector such as a Rogowski coil.

(9) About abnormal time In the above description, the semiconductor switch control at the time of overload was explained.
A similar abnormality may occur at startup. As in the above example, correction control is performed based on information including a negative current detection value. Specifically, by controlling the ON signal time width of the gate voltage VGS, the current value of the gate current IG flowing through the gate electrode G or the voltage value of the gate voltage VGS, overcurrent breakdown, overvoltage breakdown due to large ringing or abnormal oscillation At least one of the above can be suppressed.
The same applies when the input voltage VI drops, such as a momentary power failure.
The same applies when the input voltage is abnormally increased.
If the input voltage is made smaller than the lower limit value of the rated input value of the switching power supply device or made larger than the upper limit value, the drooping characteristics will fluctuate due to this.
Abnormalities can be suppressed even when high-speed switching is performed.

2. Description of Embodiment 2 [Embodiment 2]
FIG. 13 is a circuit diagram showing the semiconductor switch control circuit 1, the intelligent power module 100, and the switching power supply device 1000 according to the second embodiment.
This is almost the same as the semiconductor switch control circuit 1 and the like according to the first embodiment shown in FIG.
The difference from FIG. 1 is that the semiconductor switch 200 is provided with an external diode BDO instead of the body diode BD.
The power supply voltage VDD of the semiconductor switch control circuit is supplied from an external power supply (for supplying VDD).

As a case where the body diode BD is not formed, for example, an IGBT (Insulated Gate Bipolar Transistor) may be used for the semiconductor switch 200.
FIG. 13 shows a semiconductor switch control circuit 1, an intelligent power module 100, and a switching power supply device 1000 configured to include a semiconductor switch 200 including an IGBT and an external diode BDO provided between the collector electrode C and the emitter electrode E of the IGBT. FIG. The same reference numerals as those described above in the drawings have the same meanings as described above. The description here is omitted.

  The IGBT is a bipolar transistor in which a MOSFET is incorporated in the base portion. Like the thyristor, the IGBT is a semiconductor element composed of four layers of PNPN (or NPNP), but the current can be controlled by the MOS gate without performing the thyristor operation. In principle, the IGBT has no body diode (parasitic diode, built-in diode) BD between the collector electrode C and the emitter electrode E. However, in the circuit shown in FIG. 13, an external diode BDO is connected between the collector electrode C and the emitter electrode E of the IGBT. Was provided.

  As an embodiment of the present invention, a normally-off type semiconductor switch 200Z is formed by cascode connection with a high breakdown voltage normally-on transistor (switch) and a low breakdown voltage normally-off transistor (switch). There is. An example of such a semiconductor switch 200Z is shown in FIG. The same reference numerals as those described above in the drawings have the same meanings as described above. The description here is omitted.

A semiconductor switch 200Z shown in FIG. 14 is cascode-connected to a high breakdown voltage normally-on transistor (switch) SEM1 and a low breakdown voltage normally-off transistor (switch) SEM2. The high breakdown voltage normally-on transistor (switch) SEM1 is a GaN-based HEMT (High Electron Mobility Transistor), a FET (Field Effect Transistor), and a low breakdown voltage normally-off transistor (switch). ) SEM2 is a low-voltage Si-MOSFET (silicon-based MOSFET), and the transistors SEM1 and SEMI2 are cascode-connected as shown in FIG. The transistor SEM1 has a drain electrode DM1, a source electrode SM1, and a gate electrode GM1, and the transistor SEM2 has a drain electrode DM2, a source electrode SM2, and a gate electrode GM2. The source electrode SM1 of the transistor SEM1 and the drain electrode D2 of the transistor SEM2 The gate electrode GM1 of the transistor SEM1 and the source electrode S2 of the transistor SEM2 are connected.
In the transistor SEM2, a body diode (parasitic diode, built-in diode) BD is formed between the drain electrode DM2 and the source electrode SM2.
Thus, when the semiconductor switch 200Z is turned on / off, the gate GM2 of the transistor SEM2 may be driven with a low voltage.

  FIG. 15A is a circuit diagram of the location of the semiconductor switch 200. The body diode BD indicated by the dotted line is not formed or can be ignored. An external diode BD0 is formed in the semiconductor switch 200. The current detection element DISW for detecting the switching current ISW is provided in the switching current path. A resistor is formed in the electric circuit and a current is detected from the voltage. Alternatively, a Rogowski coil is placed beside the electric circuit to detect the current. In this way, the switching current is detected by the current detection element DISW, thereby detecting the negative current of the external diode BDO. In this case, the description of Embodiment 1 replaces “body diode” with “external diode”.

  When the body diode BD is formed in the semiconductor switch 200, as shown in FIG. 15B, an external diode BDO may be formed in parallel with the body diode BD. A switching current detection element DISW is provided in the electric path of the switching current (by putting a resistor in the electric circuit or arranging a Rogowski coil on the side of the electric circuit). In this way, the total negative current of the body diode BD and the external diode BDO can be detected. You may provide the electric current detection element DI in the electric circuit of an external diode, or an electric circuit side.

  When the body diode is negligible, or when the relationship between the current value of the total negative current of the negative current flowing through the body diode and the negative current flowing through the external diode and the current value flowing through the body diode is known, the external diode If a negative current flowing through is detected, appropriate control can be performed based on the detected value. In the case of FIG. 15B, Embodiment 1 replaces “body diode” with “external diode”.

3. The correction control unit may perform correction control for an abnormality in a specific case either when the input power supply connected to the semiconductor switch control circuit is activated or when the input voltage of the semiconductor switch control circuit is abnormal.
Further, correction control may be performed only in one case or both cases when the input power source is activated and when the input voltage of the semiconductor switch control circuit is abnormal.
In this way, more accurate correction control can be performed by narrowing down the correction control target.
FIGS. 16A and 16B are explanatory diagrams of correction control of the semiconductor switch control circuit in the case of an abnormality. FIG. 16A is an explanatory diagram when the power supply is abnormal, and FIG. 16B is an explanatory diagram when the input voltage is abnormal.

(1) Abnormality at power-on (Fig. 16 (a))
The control at the time of power activation abnormality will be described. If the input voltage is out of the rated range when the power is turned on, or if a surge voltage is applied, excessive ringing may occur and abnormal oscillation may occur, making control difficult.

  As shown in FIG. 16A, when an ON signal is input to the semiconductor switch 200 at T0, the gate voltage VGS temporarily becomes a negative voltage, and the switching current ISW also becomes negative (becomes a negative current). Thereafter, the semiconductor switch 200 is turned off, the drain voltage VDS is zero, and the switching current ISW continues to increase. At T1, the semiconductor switch 200 is turned off, and the switching current ISW does not flow.

  However, if there is an abnormality when the power supply is started, the drain voltage VDS is turned off at the timing of T1 and a large ringing occurs (dotted line), and the switching current ISW also causes a large oscillation phenomenon (dotted line). If this is excessive, the semiconductor switch 200 is destroyed or abnormal oscillation occurs and control becomes difficult. However, as described in the first or second embodiment, the semiconductor switch control circuit of the present invention is not a body diode or an external diode. The negative current flowing through the attached diode (or both) is detected directly or indirectly from the detection of the switching current ISW.

  Then, control of the ON signal time width of the gate voltage VGS, control of the current value of the gate current IG flowing through the gate electrode G, or control of the voltage value of the gate voltage VGS (or control of any two or three of these) is performed. . Then, the large ringing phenomenon at T1 of the drain voltage VDS is as small or hardly generated as the solid line when controlled from the dotted line when not controlling. The large vibration at the time T1 of the switching current ISW is reduced or almost eliminated from a dotted line (when correction control is not performed) to a solid line (when correction control is performed).

Control starts after detecting negative current abnormality. The reason why “control” is described between T1 and T2 is to indicate that the large ringing (dotted line) of the drain voltage VDS at the time of T1 is corrected and controlled as indicated by the solid line (the same applies to the switching current ISW).
When the input voltage is then normalized, the drain voltage VDS and the switching current ISW do not cause the oscillation phenomenon or become small (solid line).

(2) Abnormal input voltage (Fig. 16 (b))
FIG. 16B is an explanatory diagram for the control when the input voltage becomes abnormal after it is normal at startup.
When the semiconductor switch is repeatedly turned on (T0 to T1), off (T1 to T2), on (T2 to T3), and off (T3), the drain voltage VDS and the switching current ISW are on / off. Normal vibration does not occur when switching off.

  However, when an abnormality occurs in the input voltage after that, ON (TX0 to TX1), OFF (TX1 to TX2), ON (TX2 to TX3), OFF (TX3 to TX4), ON (TX4 to TX5), OFF (TX5) ...) .. At the timings TX1, TX3, TX5,... At the time of on / off switching, a large ringing occurs in the drain voltage VDS or a large oscillation phenomenon occurs in the switching current ISW (dotted line). However, the ON signal time width of the gate voltage is controlled, the current value of the gate current flowing through the gate electrode, or the voltage value of the gate voltage is controlled (or any two or three of these controls). Then, the large ringing at T1 of the drain voltage VDS is small or hardly generated like the solid line when the correction control is performed from the dotted line when the correction control is not performed. The large vibration at the time T1 of the switching current ISW is reduced or almost eliminated from a dotted line (when not controlled) where the vibration is large to a solid line (when controlled).

Large ringing often occurs when the input circuit connected to the semiconductor switch control circuit 1 is powered on and when the input voltage of the semiconductor switch control circuit 1 is abnormal. In at least one of these cases, by controlling at least one of the ON signal time width of the gate voltage VGS, the current value of the gate current IG flowing through the gate electrode G, and the voltage value of the gate voltage VGS, abnormal oscillation due to large ringing, etc. Many of the problems can be solved.
The control may be performed only when the input circuit connected to the semiconductor switch control circuit 1 is powered on and when the input voltage of the semiconductor switch control circuit 1 is abnormal.

4). Gate current (gate source current, gate sink current)
When the gate electrode drive control unit 10 controls the gate current IG, the gate current IG may be any one of controlling the gate source current, controlling the gate sink current, and controlling the gate source current and the gate sink current. .
In other words, the gate current correction control unit (a circuit including the gate current restriction command signal generation circuit INSG2 in FIG. 9) has a gate source current that charges an input capacitance (such as a floating capacitance) of the gate electrode G as a gate current IG, It is possible to correct and control at least one of the gate sink current that discharges the charge accumulated in the capacitance (input capacitance) of the gate electrode G.

FIG. 17 is an explanatory diagram of the gate current IG of the semiconductor switch 200.
If there is a capacitor CGD between the gate electrode G and the drain electrode D of the semiconductor switch 200 and a capacitor CGS between the gate electrode G and the source electrode S, it can be drawn as shown in FIG. These capacitors may be actively produced, but also exist as stray capacitors. Alternatively, the total capacity of the stray capacitance and the capacitance other than the stray capacitance may be used.

Here, the capacitance CGD between the gate electrode G and the drain electrode D and the capacitance CGS between the gate electrode G and the source electrode S are collectively referred to as the input capacitance of the gate electrode G.
The gate source current is a current for charging the input capacitance of the gate electrode G. When a predetermined amount of gate-source current flows, the input capacitor is charged and the semiconductor switch 200 is turned on.
The gate sink current is a discharge current of charges in the input capacitance of the gate electrode G. A predetermined amount of gate sink current flows, and the charge of the input capacitance of the gate electrode is discharged, turning off the semiconductor switch 200.

The gate current IG can be controlled by controlling the current value of the gate source current.
Further, it can be performed by controlling the current value of the gate sink current.
It can also be performed by controlling both the gate source current and the gate sink current. When both the gate source current and the gate sink current are controlled so that the amounts of current are substantially the same, it is possible to perform control in which charging and discharging are balanced.
This can be done by controlling the current value of the gate current without considering whether the current is the gate source current or the gate sink current.

  As described above, the gate current IG can be controlled more accurately by controlling the gate source current, the gate sink current, or both. At least one of overcurrent breakdown, overvoltage breakdown, and abnormal oscillation can be more accurately suppressed.

5). The storage unit semiconductor switch control circuit 1 further includes a storage unit that stores reference value related information of the negative current flowing through the diode, and the correction control unit 40 relates to the detected value of the negative current detected by the negative current detection unit 20. On / off control correction can be performed based on the information and the reference value related information stored in the storage unit.

  The “reference value related information of the negative current” flowing through the diode means the information related to the reference value such as whether the negative current flowing through the diode is abnormal or normal, and the detected negative current is This is information related to whether it is below a certain value (reference value) (or less than a certain value) or more (or exceeds a certain value). For example, the negative current value at the normal / abnormal boundary, the voltage value of the current / voltage conversion circuit IVT corresponding to the normal / abnormal current value, and the symbol corresponding to the negative current value at the normal / abnormal boundary The current value of the current / voltage conversion circuit IVT corresponding to the current value of the negative current at the boundary of normal / abnormal, the value obtained by increasing / decreasing or dividing the current value of the negative current at the normal / abnormal boundary by a certain number Is a value obtained by multiplying or dividing by a certain number.

FIG. 18 is a circuit explanatory diagram in the case where the semiconductor switch control circuit 1 of the present invention includes a body diode BD, an external diode BDO, or a storage unit for storing a reference value of a negative current flowing through both. The semiconductor switch control circuit 1 of FIG. 7, FIG. 9 or FIG. 11 further includes a storage unit 30. A part of the control circuit of FIG. 7, FIG. 9 or FIG. 11 is changed or added. The portions not shown in FIG. 18 are the same as those in FIG. 7, FIG. 9, FIG.
The control circuit of FIG. 18 stores a comparison target with the negative current detected by the current / voltage conversion circuit IVT in the storage unit (reference value memory) 30 in advance, and compares the comparison value stored in the reference value memory with the negative value. An overnegative current detection signal DT is output based on the detected current value.

  The reference value memory includes negative current values (“0”, “−A1”, “−A2”,... In the reference value memory of FIG. 18), and corresponding voltage values (in the reference value memory of FIG. 18). “0”, “−B1”, “−B2”,..., Output voltage IVTO of the current / voltage conversion circuit IVT), presence / absence of abnormality (“OK”, “NG” in the reference value memory of FIG. 18) ), A comparison reference value (voltage, “reference value 1” and “reference value 2” in the reference value memory of FIG. 18) to be input to the comparator OPER (comparator, which uses an operational amplifier as a comparator in the embodiment). The comparison table of “···) is stored.

For example, when a negative current is not detected, the negative current voltage value (the voltage value obtained by converting the current value of the negative current into a voltage by the current / voltage conversion circuit IVT, the output voltage IVTO of the current / voltage conversion circuit IVT) is zero “0. ", No abnormality (" OK "), and no comparison reference value is stored.
When the current value of the negative current is “−A1”, the negative current voltage value (the output voltage of the current / voltage conversion circuit IVT) is “−B1”, and the negative current is detected, but the current value is small, which is abnormal. No sex (“OK”) and no comparison reference value is stored.
When the current value of the negative current is “−A2”, the negative current voltage value (the output voltage of the current / voltage conversion circuit IVT) is “−B2”, and the negative current is detected, but the current value is small, and thus abnormal. No sex (“OK”) and no comparison reference value is stored.

When the current value of the negative current is “−A3” larger than “−A2”, the negative current voltage value (output voltage of the current / voltage conversion circuit IVT) is detected as “−B3” larger than “−B2”. Since the negative current is large, there is anomaly (“NG”), and the comparison reference value is stored as “reference value 1”.
When the current value of the negative current is “−A4” larger than “−A3”, the negative current voltage value (output voltage of the current / voltage conversion circuit IVT) is detected as “−B4” larger than “−B3”. Since the negative current is large, there is abnormality (“NG”), and the comparison reference value is stored as “reference value 2” which is larger than “reference value 1”.

When a negative current is detected and converted into a voltage by the current / voltage conversion circuit IVT, the output voltage IVTO is input to one terminal (+ terminal) of the operational amplifier OPER.
The output of the current / voltage conversion circuit IVT is also input to the reference value memory and the reference value setting command unit INSST. The reference value memory outputs a signal corresponding to the detected negative current to the reference value setting command unit INSST.

  For example, when a negative current is not detected, there is no negative voltage output from the current / voltage conversion circuit IVT, so the circuit reference value setting command unit INSST receives the output (no negative voltage output) of the current / voltage conversion circuit IVT. The comparison voltage (-terminal) of the reference comparator OPER is a normal voltage. In this case, the comparison “reference value” signal is not output from the memory to the command unit.

  Here, when the current value of the negative current is “−A3” or more (when the absolute value of the negative current is “−A3” or more, ie, “−A3”, “−A4”,...). If the negative current value is abnormal and you want to detect it as “NG”, the reference value memory stores “reference value 1” as the “reference value” corresponding to the negative current value “−A3”. deep. If the current value (absolute value) of the negative current is not more than “−A2” at the comparison voltage terminal (−terminal) of the comparator OPER, there is no abnormality (OK). If it is “−A3” or more (“−A3” [−A4]...), It is abnormal (NG) so that the overnegative current detection signal DT is output from the comparator OPER. This means that a command signal for setting a comparison voltage at the terminal can be output (output from the command unit INSST).

  In this case, the command unit INSST outputs the overnegative current detection signal DT from the comparator OPER when the negative current value is “−A2” or less (“−A2”, “−A1”, “0”). In the case of “−A3” or more (in the case of “−A3”, “−A4”,...), A voltage (comparison voltage) is applied to the − terminal of the comparator OPER so that the overnegative current detection signal DT is output. To do. A voltage corresponding to a voltage to be applied as a comparison voltage is selected by a switch (SWS) according to a command (signal) from the command unit INSST among the voltage drops caused by a plurality of resistors RST provided between the power supply voltage VDD and the ground. The voltage is applied to the OPER comparison voltage input terminal (-terminal).

  Accordingly, in FIG. 18, the negative current value “−A3” (negative current voltage value “−B3”) having an absolute value (absolute value) larger than the negative current value “−A2” (negative current voltage value “−B2”). )) Is input to the + terminal of the comparator OPER as the output INVO of the current / voltage conversion circuit INT, the overnegative current detection signal DT is output.

  Further, when the current value of the negative current is “−A4” or more (when the magnitude of the absolute value of the negative current is “−A4” or more, that is, “−A4”...), The current value of the negative current is Is detected as “NG”, the “reference value 2” is stored as the “reference value” corresponding to the current value “−A4” of the negative current in the reference value memory. This is because there is no anomaly if the negative current value is “−A3” or less (“−A3”, “−A2”, “−A1”,...) At the comparison voltage terminal (−terminal) of the comparator OPER ( OK). If it is greater than “−A4” (if it is “−A4”, “−A5”,...), An over-current detection signal DT is output from the comparator OPER as abnormal (NG). This means that a command signal for setting a comparison voltage at the terminal can be output (output from the command unit INSST).

  In this case, the command unit INSST detects an overnegative current from the comparator OPER when the current value of the negative current is “−A3” or less (“−A3”, “−A2”, “−A1”, “0”). When the signal DT is not output and is “−A4” or more (in the case of “−A4”), a voltage (comparison voltage) is applied to the − terminal of the comparator OPER so that the overnegative current detection signal DT is output. To do. A voltage corresponding to a voltage to be applied as a comparison voltage is selected by a switch SWS according to a command (signal) from a reference value setting command unit INSST among the voltage drops caused by a plurality of resistors RST provided between the power supply voltage VDD and the ground. Applied to the comparison voltage input terminal (-terminal) of the comparator OPER. Thus, in FIG. 18, the negative current value “−A4” (negative current voltage value “−B4”) (having an absolute value) larger than the negative current value “−A3” (negative current voltage value “−B3”). )) Is input to the + terminal of the comparator OPER as the output INVO of the current / voltage conversion circuit INT, the overnegative current detection signal DT is output.

  As described above, the comparison voltage is input to the negative terminal of the comparator OPER. In accordance with a designation signal from the reference value setting command unit INSST, one of the voltages obtained by dividing the voltage between the power supply voltage VDD and the ground by resistance division by the resistor RST is selected by the switch SWS and input.

  In this way, in the case of an input voltage abnormality or the like, it is possible to determine the permissible range in detail, or to flexibly determine the control method according to the degree of abnormality. Flexible control according to the purpose of control and the purpose of control becomes possible.

It should be noted that the configuration can be simplified without using the reference value memory as shown in FIG. For example, in the circuit of FIG. 18, the output of the negative current / voltage conversion circuit IVT is input to one input part (+ side) of the comparator OPER. Connect a capacitor between the other input (-side) and ground. The capacitor is charged with a voltage corresponding to the lower limit of the negative current that is abnormal. Then, the storage unit corresponds to the capacitor, and the reference value related information corresponds to the voltage value (or charge amount) of the capacitor.
As described above, the “storage unit” is a storage unit that performs digital storage, an analog storage such as the capacitor, or a combination of digital storage and analog storage. May be.

6). Various semiconductor switches 200 include various semiconductor switches.
Most commonly, a semiconductor switch uses T silicon as a semiconductor material. A drain electrode D, a source electrode S, and a gate electrode G are formed on a semiconductor substrate mainly composed of silicon, and are isolated by a silicon insulating layer INS, so that a MOS-type FET (Metal-Oxide-Semiconductor Field-Effect Transistor, A semiconductor switch of a metal oxide semiconductor field effect transistor) is configured.

As the semiconductor switch 200, a gallium nitride semiconductor switch having a built-in or external diode, a silicon carbide semiconductor switch, a gallium oxide semiconductor switch, and a diamond semiconductor switch can be used.
As semiconductor materials, the gallium nitride semiconductor switch uses gallium nitride, the silicon carbide semiconductor switch uses silicon carbide, the gallium oxide semiconductor switch uses gallium oxide, and the diamond semiconductor switch is a semiconductor switch using diamond.

  According to the present invention, even when the semiconductor switch is switched at high speed, at least one of overcurrent breakdown, overvoltage breakdown, abnormal oscillation, and the like can be suppressed.

(1) Gallium nitride semiconductor switch An example of a gallium nitride semiconductor switch is shown in FIG.
A buffer layer Buffer layer is provided on the silicon substrate (substrate) Si (upper side in the drawing), and a gallium nitride layer GaN is formed thereon. An aluminum gallium nitride layer AlGaN (Alminium Gallium Nitride) layer is formed thereon. A source electrode S, a drain electrode D, and a gate electrode G are formed thereon. An insulating layer INS is formed between these electrodes. A two-dimensional electron gas 2DEG (Two Dimensional Electron Gas) is distributed over the GaN layer. The semiconductor substrate 1A is a gallium nitride (GaN) semiconductor substrate as a whole.
The drain electrode D, the source electrode S, and the gate electrode G constitute a semiconductor switch.

  When a gallium nitride based semiconductor substrate is used as the semiconductor substrate 1A, when a semiconductor switch or the like is formed on the semiconductor substrate 1A by a semiconductor process, high withstand voltage, low conduction resistance characteristics, high-speed switching properties, etc. can be easily imparted. it can. It is also suitable for semiconductor control and power for high current and high voltage switching.

(2) Silicon Carbide Semiconductor Switch A silicon carbide semiconductor switch is a semiconductor switch that uses silicon carbide (SiC) as a semiconductor material. Silicon carbide is composed of silicon (Si) and carbon (C).

  The dielectric breakdown electric field strength is about 10 times that of silicon (Si) and the band gap is about 3 times that of silicon. Also, p-type and n-type control is possible in a wide range. In addition, operation at a high temperature exceeding 200 ° C., which is the limit of silicon, is possible.

(3) Gallium oxide semiconductor switch A gallium oxide semiconductor switch is a semiconductor switch using gallium oxide (Ga ₂ O ₃ ) as a semiconductor material.

  The manufacturing method of the wafer is almost the same as that of silicon and easy to manufacture. High band gap and excellent power device material. Moreover, the Variger performance index which is an index indicating that it is suitable as a power semiconductor material is also high.

(4) Diamond semiconductor switch A semiconductor mainly using artificial diamond.

  In particular, it is excellent in forbidden band width (band gap), breakdown electric field, mobility, and thermal conductivity. The band gap and dielectric breakdown electric field are high, and the output voltage can be increased. Since the mobility is high, the resistance value when a current is passed is reduced, and the power consumption can be reduced. Furthermore, since heat conductivity is high, it is excellent in heat dissipation, and the heat risk at the time of applying a high voltage can be suppressed. Compared to the current mainstream silicon semiconductors, it is possible to achieve a significant speed increase of several tens to several hundred times.

7). Other (capacity between the first electrode and the second electrode)
There may be a capacitor CDS shown in FIG. 20 between the first electrode D and the second electrode S of the semiconductor switch 200. The capacitor CDS may be a parasitic capacitor, an external capacitor, or both.

8). Semiconductor Switch Control Method The semiconductor switch 200 is controlled by the following control method.
First, the objects to be controlled are a first electrode D, a second electrode S, a gate electrode G, and a diode (a body diode BD or a diode BDO other than a body diode) provided between the first electrode D and the second electrode S. Or a diode of both). The semiconductor switch 200 performs on / off control between the first electrode D and the second electrode S by applying a gate voltage VGS to the gate electrode G.

A negative current flowing through a diode (a body diode BD, a diode BDO other than the body diode, or both diodes) is detected.
Based on the information regarding the detected value of the detected negative current, the on / off control of the semiconductor switch 200 is corrected.
Details of the operation are as described in the first embodiment.
By controlling the semiconductor switch 200 by such a method, the effects described in the first embodiment, such as suppression of overcurrent breakdown, can be obtained.
As the correction control, there are correction control of the ON signal time width of the gate voltage, current value correction control of the gate current flowing through the gate electrode, and correction control of the voltage value of the gate voltage.

9. Intelligent power module.
As shown in FIG. 1, the intelligent power module 100 is configured by the semiconductor switch 200, the semiconductor switch control circuit 1, the insulating transformer 400 provided on the output side, the rectifying diode 500, and the output capacitor 600.

  An input voltage VI is applied between the terminals T1 and T2, and an input tradition flows from the terminal T2. An output voltage is output from the terminals T3 and T4. An output current flows out from the terminal T4. Terminal T2 is an input side ground terminal, and T4 is an output side ground terminal. The driving power for the semiconductor switch control circuit 1 is supplied from the terminal TVDD.

  Since such an intelligent power module is integrated with the semiconductor switch 200 and the semiconductor switch control circuit 1 for accurately controlling the semiconductor switch 200, a switching power source or the like that is unlikely to cause overcurrent breakdown can be easily configured. .

10. Switching power supply device A switching power supply device including the semiconductor switch control circuit or the intelligent power module can be configured.
The switching power supply device can be composed of, for example, the above intelligent power module and the input unit capacitor 4.
Such a switching power supply device is a stable power supply device in which overcurrent breakdown is suppressed.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor switch control circuit 2, 2P ... Input power supply 3, 3P ... Rectifier circuit, 4, 4P ... Capacitor, 10 ... Gate electrode drive control part, 20 ... Negative current detection part, 30 ... Memory | storage part, 40 ... Correction Control unit, 100 ... IPM, 100P ... Power supply control IC, 200, 200P ... Semiconductor switch, 400 ... Insulation transformer, 500 ... Diode, 700 ... Load, 800 ... Excessive switching current detection circuit, 1000 ... Switching power supply device, 2000 ... Power Conversion circuit, BD: Body diode, BDO: External diode, CGD: Capacitance between gate electrode and first electrode (drain electrode), CGS: Capacitance between gate electrode and second electrode (source electrode), CGD: First electrode Capacity between second electrodes (drain electrode / source electrode), D, D1... First electrode (drain electrode), S, S1. G, G1... Gate electrode, VGS... Gate voltage (voltage between gate electrode and source electrode, voltage between gate electrode and second electrode), VGSR, VGSJ... Gate voltage applied to gate electrode, VDS. Voltage between electrode and second electrode (voltage between drain electrode and source electrode, drain voltage), VDSD: Negative voltage between first electrode and second electrode (voltage between drain electrode and source electrode, drain voltage), VDSR: Ringing Generated voltage between the first electrode and the second electrode (drain electrode-source electrode voltage, drain voltage), VG1... Gate electrode applied voltage, VZ... Voltage drop due to resistor RZ, VIT... V / I (voltage / current) Conversion circuit, DV ... voltage detector, INT ... integration circuit, CDO ... drooping characteristic control unit, DINV ... input voltage detection unit, ID ... negative current, ISW, IZ ... switching power , ISWD: negative switching current, ISEW: switching current in which vibration phenomenon occurs, IG: gate current, IVT: current / voltage conversion circuit, VREF: comparison voltage input to comparator (operational amplifier), DISW: switching current detection ONES1, ONES2, ONES3 ... one-shot circuit, INSG1 ... gate electrode application pulse width command circuit, INSG2 ... gate current limit command signal generation circuit, INSG3 ... gate voltage limit command signal generation circuit, INSST ... reference value setting command unit, SWK, SWV, SWS ... switch, II, IIP ... input current, VI, VIP ... input voltage, IO, IOP ... output current, VO, VOP ... output voltage, T1, T2, T3, T4, TVDD ... terminal, VDD ... Power supply for control circuit, F / B ... Feedback circuit, RK, R BD, RS, RVG, RST, ROP ... resistor, VRBD ... voltage across resistor RBD, OPEC ... op amp, OPER ... comparator (op amp), VOP ... op amp output voltage, COP ... capacitor, WI ... electric circuit, COI ... Rogowski coil, 1A ... Semiconductor substrate

Claims (15)

The semiconductor switch having a first electrode, a second electrode, a gate electrode, and an internal or external diode between the first electrode and the second electrode is electrically controlled by the gate electrode. A semiconductor switch control circuit for performing on / off control between an electrode and the second electrode,
A negative current detector for detecting a negative current flowing through the diode;
A correction control unit that corrects the on / off control based on at least information on the detected value of the negative current detected by the negative current detection unit;
A semiconductor switch control circuit comprising:   2. The semiconductor according to claim 1, wherein the negative current detection unit detects a negative current flowing through the diode by detecting a current flowing between the first electrode and the second electrode. Switch control circuit.   The semiconductor switch control circuit according to claim 1, wherein the diode is mainly a body diode between the first electrode and the second electrode.   3. The diode according to claim 1, wherein the diode is a body diode between the first electrode and the second electrode and a diode other than the body diode between the first electrode and the second electrode. Semiconductor switch control circuit.   The said correction control part correct | amends the said on / off control when the negative current detected by the said negative current detection part is predetermined | prescribed, The correction | amendment control part in any one of Claim 1 thru | or 4 characterized by the above-mentioned. Semiconductor switch control circuit.   The said correction control part has a gate ON signal time width correction control part which correct | amends the ON signal time width of the said gate voltage based on the information regarding the detected value of the said negative current, The 1st thru | or 5 characterized by the above-mentioned. A semiconductor switch control circuit according to any one of the above.   The said correction control part has a gate current correction control part which correct | amends the electric current value of the gate current which flows through the said gate electrode based on the information regarding the detected value of the said negative current, Any one of Claim 1 thru | or 5 characterized by the above-mentioned. A semiconductor switch control circuit according to claim 1.   The gate current correction control unit corrects at least one of a gate source current for charging the capacitance of the gate electrode and a gate sink current for discharging the charge accumulated in the capacitance of the gate electrode as the gate current. The semiconductor switch control circuit according to claim 7, wherein the semiconductor switch control circuit is controlled.   The said correction control part has a gate voltage correction control part which correct | amends the voltage value of the said gate voltage based on the information regarding the detected value of the said negative current, The Claim 1 thru | or 5 characterized by the above-mentioned. Semiconductor switch control circuit.   The semiconductor switch control circuit according to claim 1, wherein the correction control unit performs correction control when the input power supply is activated or when the input voltage is abnormal. The semiconductor switch control circuit further includes a storage unit that stores reference value related information of the negative current flowing through the diode.
The correction control unit is configured to perform the on / off control based on the information related to the detected value of the negative current detected by the negative current detection unit and the reference value related information stored in the storage unit. 11. The semiconductor switch control circuit according to claim 1, wherein correction is performed.   An intelligent power module comprising: a semiconductor switch; and the semiconductor switch control circuit according to claim 1.   The intelligent power module according to claim 12, wherein the semiconductor switch is at least one of a gallium nitride semiconductor switch, a silicon carbide semiconductor switch, a gallium oxide semiconductor switch, and a diamond semiconductor switch.   A switching power supply comprising the intelligent power module according to claim 12. A semiconductor switch having a first electrode, a second electrode, a gate electrode, and a diode between the first electrode and the second electrode, by electrically controlling the gate electrode, the first electrode and the second electrode. A method of controlling a semiconductor switch that performs on / off control between electrodes,
A detecting step for detecting a negative current flowing through the diode;
A correction control step of correcting the on / off control based on information on the detected value of the negative current detected by the detection step;
A method for controlling a semiconductor switch, comprising: