JP2019154234A - Switching converter and control circuit thereof - Google Patents

Abstract

To provide a switching converter capable of detecting a failure and abnormality, and to provide a control circuit thereof.SOLUTION: A current limit comparator 202 asserts a reset pulse S11, when a current detection signal Vaccording to a voltage drop of a detection resistor Rexceeds a first threshold value V. A zero current detection circuit 204 generates a set pulse S13 for instructing turn ON of a switching transistor M1. A logic circuit 206 generates an output pulse S14 in response to the reset pulse S11 and the set pulse S13. When the current detection signal Vexceeds a second threshold value V, a second comparator 212 asserts a comparison signal S15. An abnormality detection circuit 214 determines abnormality when the comparison signal S15 is asserted during an abnormality detection period, i.e., from turn ON of the switching transistor M1 until first time elapses.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a switching converter.

Semiconductor light sources such as LEDs (light emitting diodes) have been widely used as liquid crystal backlights and lighting fixtures. In recent years, a step-down type of LED lighting has been developed. FIG. 1 is a circuit diagram of a step-down switching converter studied by the present inventors. The switching converter 100r receives an input voltage _VIN from a power source (not shown), and supplies the output voltage _VOUT to the LED light source 502 as a load by stepping down the input voltage _VIN , and a current (load current or drive) flowing through the LED light source 502. Stabilize I _{LED (referred} to as current) to target value I _REF . For example, the LED light source 502 is a light emitting diode (LED) string, and the switching converter 100r sets the target current value I _REF of the load current I _LED according to the target luminance of the LED string.

The switching converter 100r includes an output circuit 102 and a control circuit 200r. The output circuit 102 includes a smoothing capacitor C1, the rectifying diode D1, a switching transistor M1, the inductor L1, an auxiliary winding L2, and the detection resistor _{R CS.}

In the on period of the switching transistor M1, the detection resistor R _CS, current flows through the switching transistor M1. The current detection (CS) terminals of the control circuit 200 r, the voltage drop across the sense resistor _{R CS} (detection _{voltage) V CS} is fed back.

  The control circuit 200 includes a current limit comparator 202, a zero current detection circuit 204, a logic circuit 206, and a driver 208.

FIG. 2 is an operation waveform diagram of the switching converter 100r of FIG. Switching transistor M1 is turned on period (ON period), the coil current _{I L} corresponds to the current _{I M1} flowing through the switching transistor M1, LED light source 502, an inductor L1, flows through the switching transistor M1 and the detection resistor _{R CS.} As the output current I _OUT increases, the current detection signal _VCS rises. The current limit comparator 202 compares the current detection signal V _CS with the target voltage V _ADIM set corresponding to the target current value I _REF , and when the current detection signal V _CS reaches the target voltage V _ADIM , that is, the output current When I _OUT reaches the limit current I _LIM (= V _ADIM / R _CS ), the limit current detection signal S1 is asserted (for example, high level). In the ON period, the energy stored in the inductor L1 increases.

  When the limit current detection signal S1 is asserted, the logic circuit 206 changes the pulse signal S2 to an off level (for example, a low level) corresponding to the switching transistor M1 being turned off. The driver 208 turns off the switching transistor M1 in response to the pulse signal S2.

While the switching transistor M1 is off, the output current I _OUT corresponds to the current I _D1 flowing through the rectifier diode D1, and flows through the LED light source 502, the inductor L1, and the rectifier diode D1. As the off time elapses, the energy stored in the inductor L1 decreases, and the output current I _OUT decreases.

The auxiliary winding L2 is coupled to the inductor L1, and a transformer T1 is formed. The voltage V _ZT of the auxiliary winding L2 is input to the zero cross detection (ZT) terminal of the control circuit 200r. The zero current detection circuit 204 detects that the output current I _OUT flowing through the inductor L1 becomes zero (zero cross) based on the voltage V _ZT of the auxiliary winding Lz, and asserts the zero cross detection signal S3.

  When the zero-cross detection signal S3 is asserted, the logic circuit 206 changes the pulse signal S2 to an on level (for example, a high level) corresponding to the on state of the switching transistor M1. The driver 208 turns on the switching transistor M1 in response to the pulse signal S2.

The control circuit 200r repeats the above operation. The load current I _LED becomes a current obtained by smoothing the output current I _OUT by the smoothing capacitor C1, and the target current value I _{REF at} that time becomes I _LIM / 2.

As shown in FIG. 2, immediately after the output pulse signal S _OUT of the driver 208 transitions to the ON level, the current detection signal V _CS jumps greatly influence of surge noise. In order to prevent the output (limit current detection signal) S1 of the current limit comparator 202 from being asserted even though the output current I _OUT has not reached the limit current I _LIM due to the spike noise, the switching transistor M1 Immediately after turning on, a mask time T _MSK having a predetermined length is set, and the comparison result by the current limit comparator 202 is invalidated during the mask time T _MSK . This is also referred to as leading edge blanking (LEB).

JP 2003-153529 A JP 2004-47538 A

  As a result of studying the switching converter 100r of FIG. 1, the present invention has recognized the following problems. When a failure / abnormality occurs, such as when the LED light source 502 is short-circuited due to a failure, a large current flows through the circuit elements to generate heat, and the voltage between the elements exceeds the withstand voltage, which may adversely affect reliability. Such a problem can occur not only in the LED light source 502 but also in various loads.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an aspect thereof is to provide a switching converter capable of detecting a failure or abnormality and a control circuit thereof.

  One embodiment of the present invention relates to a control circuit for a switching converter. The switching converter includes an output capacitor provided between the input line and the output line, an inductor, a switching transistor and a detection resistor provided in series between the output line and the ground line, and a cathode connected to the input line. And a diode having an anode connected to a connection point of the switching transistor. When the current detection signal corresponding to the voltage drop of the detection resistor exceeds the first threshold, the control circuit asserts a reset pulse and a set pulse that asserts a set pulse at a timing when the switching transistor should be turned on. A generator and a logic circuit that receives a set pulse and a reset pulse and generates an output pulse. (I) When the set pulse is asserted, the output pulse transitions to an on level corresponding to the switching transistor being turned on. (Ii) a logic circuit that transitions to an off level corresponding to the switching transistor being turned off when the reset pulse is asserted, and a second signal that asserts the comparison signal when the current detection signal exceeds the second threshold value. 2. Is the comparator and switching transistor turned on? Until elapse of the first time the abnormality detection period comprises comparison signal during the abnormality detection period is asserted and the abnormality detecting circuit for determining an abnormality, the.

  As a result of studying the switching converter, the present inventor has come to recognize that when the switching transistor is turned on while the switching converter is abnormal, a large current flows through the inductor and the current detection signal rises at a high speed. Therefore, an abnormality detection period is set immediately after the switching transistor is turned on, and an abnormality or failure of the switching converter can be detected by determining whether or not the current detection signal exceeds the second threshold value during this period. it can.

  The first threshold value and the second threshold value are equal, and the first comparator and the second comparator share a single comparator, and the reset pulse and the comparison signal may be the same.

The abnormality detection circuit may determine that an abnormality occurs when assertion of the comparison signal during the abnormality detection period occurs continuously for a predetermined determination time.
Further, the present inventor further applies a large voltage to the inductor immediately after the switching converter is activated, depending on circuit constants such as the inductor and capacitor of the switching converter, and the current detection signal rises at a high speed. Recognized that there may be cases. Thus, by making the determination time longer than the activation time and performing abnormality determination, erroneous detection at the activation can be prevented.

  The abnormality detection circuit receives a first timer signal that generates a first timer signal that is asserted and a comparison signal between the first timer signal and an intermediate determination signal until the first time elapses after the switching transistor is turned on. (I) The intermediate determination signal is asserted when the first timer signal is asserted and the comparison signal is asserted, and (ii) the intermediate determination signal is the first timer signal. And an intermediate determination unit that is negated when the comparison signal is asserted, and a final determination unit that asserts a final determination signal when the intermediate determination signal is continuously asserted for a determination time, May be included.

The abnormality detection circuit may determine that an abnormality occurs when assertion of the comparison signal during the abnormality detection period continues for a predetermined number of cycles.
By setting the predetermined number of cycles longer than the startup time and performing abnormality determination, erroneous detection at startup can be prevented.

  The abnormality detection circuit receives a first timer circuit that generates a first timer signal that is asserted for a first time after the switching transistor is turned on, a first timer signal, and a comparison signal, and outputs an intermediate determination signal (I) the intermediate determination signal is asserted when the first timer signal is asserted and the comparison signal is asserted; and (ii) the intermediate determination signal is negated by the first timer signal. The intermediate determination unit, the intermediate determination signal, and the output pulse, which are negated when the comparison signal is asserted, are turned on for a predetermined number of cycles during the period in which the intermediate determination signal is asserted. And a final determination unit that asserts a final determination signal when transitioning to a level.

  The intermediate determination unit receives the first timer signal and the comparison signal, the first timer signal is asserted, and when the comparison signal is asserted, a first gate that outputs an abnormality detection signal that is asserted, and the first timer signal When the comparison signal is received, the first timer signal is negated and the comparison signal is asserted, the second gate that outputs the assertion release signal, the clock terminal receives the abnormality detection signal, and the reset terminal receives the release signal And a flip-flop that outputs an intermediate determination signal, the intermediate determination signal being asserted when the abnormality detection signal is asserted, and negated when the release signal is asserted.

  The final determination unit includes a capacitor, a current source for charging the capacitor while the intermediate determination signal is asserted, a switch for discharging the capacitor when the intermediate determination signal is negated, and a voltage of the capacitor as a predetermined threshold voltage. And a comparator for comparison.

  The final determination unit may include a counter in which an output pulse is input to the clock terminal and an intermediate determination signal is input to the reset terminal.

  The abnormality detection circuit may invalidate the abnormality detection for a predetermined time from the start of activation. This prevents erroneous detection of an abnormality immediately after startup.

  A control circuit according to one aspect sets a mask period from a turn-on of a switching transistor to a lapse of a predetermined second time, masks assertion of a reset pulse during the mask period, and outputs a reset pulse after masking to a logic circuit A leading edge blanking circuit may be further provided.

  The first time and the second time may be equal. In this case, since the first timer signal and the second timer signal may be the same, the timer circuit can be reduced and the circuit can be simplified.

  The leading edge blanking circuit receives a second timer circuit that generates a second timer signal that is asserted for a second time after the switching transistor is turned on, a second timer signal, and a reset pulse. And a third gate for generating a reset pulse.

  The first time is equal to the second time, the first threshold value is equal to the second threshold value, the first comparator and the second comparator share a single comparator, and the reset pulse and the comparison signal are the same. It may be.

  The abnormality detection circuit and the leading edge blanking circuit may share a timer circuit that generates a timer signal having a predetermined level for a second time after the switching transistor is turned on. The abnormality detection circuit receives the timer signal and the reset pulse, the timer signal is asserted, and when the reset pulse is asserted, the first gate that outputs the asserted abnormality detection signal, the timer signal and the reset pulse, When the timer signal is negated and the reset pulse is asserted, the second gate that outputs the release signal that is asserted, the abnormality detection signal is received at the clock terminal, the release signal is received at the reset terminal, and the intermediate determination signal is output The intermediate determination signal may include a flip-flop that is asserted when the abnormality detection signal is asserted and negated when the release signal is asserted. The leading edge blanking circuit may include a third gate that performs a logical operation on the timer signal and the reset pulse and generates a reset pulse after masking.

The set pulse generator may assert the set pulse when the current flowing through the inductor is substantially zero.
The above-described abnormality detection technique is particularly effective in a quasi-resonant (QR) operation mode in which soft switching is performed.

The switching converter may further include a first capacitor and a resistor provided in series between the connection point of the inductor and the switching transistor and the ground line. The set pulse generator may assert the set pulse when a voltage at a connection point between the first capacitor and the resistor crosses a predetermined threshold voltage.
Thereby, it can be detected that the current of the inductor becomes zero.

The switching converter may further comprise an auxiliary winding coupled with the inductor. A set pulse may be asserted when the voltage of the auxiliary winding crosses a predetermined threshold voltage.
Thereby, it can be detected that the current of the inductor becomes zero.

The set pulse generator may assert the set pulse after a predetermined off time elapses after the switching transistor is turned on.
The abnormality detection technique described above can also be applied to an operation mode in which hard switching is performed.

  The control circuit may stop when it detects an abnormality.

The control circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to a switching converter. The switching converter includes any of the control circuits described above.

  Another aspect of this invention is related with an illuminating device. The illumination device receives an LED light source including a plurality of LEDs (light emitting diodes) connected in series, a rectifier circuit that smoothes and rectifies commercial AC voltage, and a DC voltage that is smooth rectified by the rectifier circuit as an input voltage. And a switching converter using as a load. The switching converter may include any of the control circuits described above.

  Another embodiment of the present invention relates to an electronic device. The electronic apparatus may include a liquid crystal panel and the above-described illumination device that is a backlight that irradiates the liquid crystal panel from the back surface.

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as embodiments of the present invention.

  According to the present invention, an abnormality of a step-down converter can be detected.

FIG. 3 is a circuit diagram of a step-down switching converter investigated by the present invention. It is an operation | movement waveform diagram of the switching converter of FIG. It is a circuit diagram which shows the structure of the switching converter which concerns on embodiment. It is a block diagram of an abnormality detection circuit. It is a circuit diagram which shows the structural example of an abnormality detection circuit. It is an operation | movement waveform diagram of a control circuit. It is a circuit diagram of a switching converter concerning the 1st modification. It is a circuit diagram of an abnormality detection circuit according to a second modification. It is a circuit diagram of a control circuit concerning the 4th modification. It is a circuit diagram of the switching converter which concerns on a 5th modification. It is a block diagram of the illuminating device using a switching converter. 12A to 12C are diagrams illustrating specific examples of the lighting device.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

FIG. 3 is a circuit diagram showing a configuration of the switching converter 100 according to the embodiment. The switching converter 100 is a step-down converter (buck converter) that steps down the input voltage _VIN of the input line 104 and outputs the stepped down output voltage _VOUT from the output line 106. One end (anode) of the LED light source 502 is connected to the input line 104, and the other end (cathode) is connected to the output line 106. A drive voltage V _IN −V _OUT is supplied between both ends of the LED light source 502.

The LED light source 502 is a device that should be driven at a constant current, and the switching converter 100 stabilizes the current I _LED that flows through the LED light source 502 to a target amount. For example, the LED light source 502 may be an LED string including a plurality of light emitting elements (LEDs) connected in series. The switching converter 100 stabilizes the current I _LED flowing through the LED light source 502 to the target current I _REF corresponding to the target luminance.

The output circuit 102, a smoothing capacitor C1, the input capacitor C2, a rectifying diode D1, a switching transistor M1, the inductor L1, comprising a detection resistor _{R CS.} One end of the smoothing capacitor C <b> 1 is connected to the input line 104, and the other end is connected to the output line 106.

One end of the inductor L1 is connected to the output line 106, and the other end is connected to the drain of the switching transistor M1. Detection resistor R _CS, the switching transistor M1 is the period of the on, are disposed in the path of the current I _L flowing through the switching transistor M1 and the inductor L1. The cathode of the rectifier diode D1 is connected to the input line 104, and the anode thereof is connected to the connection point N1 (drain) of the inductor L1 and the switching transistor M1.

The control circuit 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate, and has an output (OUT) terminal, a current detection (CS) terminal, an auxiliary (ZT) terminal, and a ground (GND) terminal. . The GND terminal is grounded. OUT terminal is connected to the gate of the switching transistor M1, the CS terminal, the current detection signal _{V CS} corresponding to the voltage drop across the sense resistor _{R CS} is input. The switching transistor M1 may be built in the control circuit 200.

  The control circuit 200 includes a first comparator (current limit comparator) 202, a set pulse generator (zero current detection circuit) 204, a logic circuit 206, a driver 208, a LEB (Leading Edge Blanking) circuit 210, a second comparator 212, and an abnormality detection. A circuit 214.

Current limit comparator 202, when the current detection signal _{V CS} exceeds a first threshold value (dimming _{setpoint) V ADIM,} asserts the reset pulse S11 (e.g. a high level). The first threshold value V _ADIM corresponds to the set value of analog dimming. The zero current detection circuit 204 generates a set pulse S13. The assertion (for example, high level) of the set pulse S13 instructs to turn on the switching transistor M1.

Switching converter 100 in FIG. 3 is a converter of the quasi-resonant (QR) type, the current I _L flowing through the inductor L1 becomes zero, performing a soft switching operation to turn on the switching transistor M1. Capacitor C11, resistor R10 is provided to detect the coil current _{I L.} When the voltage V _{N2 at} the connection point N2 between the capacitor C11 and the resistor R10 crosses the threshold value near zero, the zero current detection circuit 204 asserts the set pulse S13. Although the voltage V _N2 at the connection point N2 may be directly input to the ZT terminal, the voltage V _ZT divided by the resistors R11 and R12 may be input.

The zero current detection circuit 204 includes a comparator, and asserts the set pulse S13 (for example, high level) when the voltage V _{ZT at the} ZT terminal crosses the threshold voltage V _ZERO set near zero.

  The LEB circuit 210 masks, that is, invalidates the assertion of the reset pulse S11 during the mask period τ2 until the second time τ2 elapses after the switching transistor M1 is turned on, and outputs the reset pulse S12 after masking to the logic circuit. It outputs to 206. That is, the second time τ2 of the LEB circuit 210 defines the minimum width of the on-time of the switching transistor M1.

  The configuration of the LEB circuit 210 is not particularly limited. For example, the LEB circuit 210 includes a second timer circuit 236 and a third gate 238. The second timer circuit 236 generates a second timer signal S22 that is asserted (for example, high level) for a second time τ2 after the switching transistor M1 is turned on. The third gate 238 receives the second timer signal S22 and the reset pulse S11, and generates a reset pulse S12 after masking. Most simply, the third gate 238 is an AND gate that generates a logical product of the inverted signal of the second timer signal S22 and the reset pulse S11.

  The logic circuit 206 receives the set pulse S13 and the reset pulse S12 and generates an output pulse S14. (I) When the set pulse S13 is asserted, the output pulse S14 transitions to an on level (for example, a high level) corresponding to the on state of the switching transistor M1, and (ii) when the reset pulse S12 is asserted, the switching transistor Transition to an off level (for example, a low level) corresponding to the off state of M1.

  The driver 208 switches the switching transistor M1 according to the output pulse S14. In the present embodiment, the signal at the OUT terminal and the output pulse S14 are the same.

The second comparator 212, when the current detection signal _{V CS} exceeds the second threshold value _{V TH,} asserting a comparison signal S15 (e.g., high level). The abnormality detection circuit 214 sets an abnormality detection period from when the switching transistor M1 is turned on until the first time τ1 elapses. When the comparison signal S15 is asserted during the abnormality detection period τ1, the abnormality detection circuit 214 determines that there is an abnormality. Is asserted (eg, high level). If it is determined that the control circuit 200 is abnormal, the control circuit 200 stops switching of the switching transistor M1 and / or notifies a surrounding microcontroller (not shown).

  FIG. 4 is a block diagram of the abnormality detection circuit 214. The abnormality detection circuit 214 includes a first timer circuit 216, an intermediate determination unit 218, and a final determination unit 220. The first timer circuit 216 generates a first timer signal S17 that is asserted (high level) during an abnormality detection period from when the switching transistor M1 is turned on until the first time τ1 has elapsed. The intermediate determination unit 218 receives the first timer signal S17 and the comparison signal S15, and outputs an intermediate determination signal S18. (I) The intermediate determination signal S18 is asserted (high level) when the first timer signal S17 is asserted and the comparison signal S15 is asserted. (Ii) The intermediate determination signal S18 is negated (low level) when the first timer signal S17 is negated (low level) and the comparison signal S15 is asserted.

  The final determination unit 220 generates a final determination signal S19 (abnormality determination signal S16 in FIG. 3) based on the intermediate determination signal S18. The condition for abnormality determination in the present embodiment is that the comparison signal S15 is asserted continuously for a predetermined determination time τ3 during the abnormality detection period. That is, the final determination unit 220 asserts the final determination signal S19 when the intermediate determination signal S18 is continuously asserted without being canceled during the determination time τ3.

  The first time τ1 and the second time τ2 may be the same or different. In the same case, the second timer circuit 236 in FIG. 3 and the first timer circuit 216 in FIG. 4 can share a single timer, and the circuit area can be reduced.

  FIG. 5 is a circuit diagram illustrating a configuration example of the abnormality detection circuit 214. The intermediate determination unit 218 includes a first gate 222, a second gate 224, and a flip-flop 226. The first gate 222 receives the first timer signal S17 and the comparison signal S15, and generates an abnormality detection signal S20. When the first timer signal S17 is asserted and the comparison signal S15 is asserted, the abnormality detection signal S20 is asserted. The first gate 222 is most simply an AND gate, but the configuration is not particularly limited.

  The second gate 224 receives the first timer signal S17 and the comparison signal S15 and generates a release signal S21. When the first timer signal S17 is negated and the comparison signal S15 is asserted, the release signal S21 is asserted. The second gate 224 may be configured by a combination of an OR gate and an inverter, or may have another configuration.

  The flip-flop 226 receives the abnormality detection signal S0 at its clock terminal, receives the release signal S21 at its reset terminal (inverted logic), and outputs an intermediate determination signal S18. The intermediate determination signal S18 is asserted when the abnormality detection signal S20 is asserted, and is negated when the release signal S21 is asserted.

Final determination unit 220 includes a capacitor C 21, a current source 228, a switch 230, and a comparator 232. The current source 228 charges the capacitor C21 while the intermediate determination signal S18 is asserted. The switch 230 is turned on when the intermediate determination signal S18 is negated, and discharges the capacitor C21. The comparator 232 compares the voltage V _C21 of the capacitor C21 with a predetermined threshold voltage V _τ3 and outputs a final determination signal S19. The threshold voltage V _τ3 is determined corresponding to the determination time τ3. The final determination signal S19 is latched by, for example, a latch (flip-flop) 234, and a predetermined protection process is executed.

  The above is the configuration of the control circuit 200. Next, the operation will be described. FIG. 6 is an operation waveform diagram of the control circuit 200. Note that the vertical and horizontal axes of the waveform diagrams and time charts in this specification are enlarged or reduced as appropriate for easy understanding, and each waveform shown is also simplified for easy understanding. Or is emphasized.

This time _chart, τ1> τ2, the operation of the case of the _{V ADIM>} V _TH is shown. Before time _{t A,} the switching converter 100 and the LED light source 502 is operating normally.

Each time the current detection signal V _CS reaches the dimming set value V _ADIM , the reset pulse S11 is asserted. At time t0, the output pulse S14 is turned on, and the switching transistor M1 is turned on. Thus the coil current _{I L} of the inductor L1 is increased, the current detection signal _{V CS} rises. When the current detection signal _{V CS} exceeds the dimming setpoint _{V ADIM} at time t1, the reset pulse S11 is asserted. The reset pulse S11 passes through the LEB circuit 210 without being masked and is input to the logic circuit 206, and the output pulse S14 is turned off.

When the switching transistor M1 is turned off, the coil current I _L decreases. When the coil current _{I L} is zero at time t2, the zero current detection circuit 204 asserts the set pulse S13. As a result, the output pulse S14 changes to the on level again. The control circuit 200 operates using the times t0 to t2 as basic cycles.

As shown at time t3, noise superimposed on the current detection signal V _CS immediately turn the switching transistor M1 is masked by LEB circuit 210 does not affect the switching.

In a normal state before time t _A, release signal S21 for each cycle is asserted (low level). Therefore, even if the abnormality detection signal S20 is asserted due to noise at time t3, the final abnormality determination cannot be made because the reset is applied by the release signal S21 in the next cycle.

Next, the operation at the time of abnormality will be described. At time _{t A,} the abnormality or malfunction such as a short circuit of the LED light source 502 has occurred. When an abnormality occurs, the voltage applied to the inductor L1 increases immediately after the switching transistor M1 is turned on at time t4, so that the speed at which the coil current _IL increases increases. As a result, shortly after time t5 switching transistor M1 is turned on, the current detection signal _{V CS} exceeds the threshold value _{V TH,} the comparison signal S15 is asserted. If the comparison signal S15 is asserted between the turn-on and the first time τ1, the abnormality detection signal S20 is asserted. When the abnormality detection signal S20 is asserted, the intermediate determination signal S18 is asserted, and the time determination is started by the final determination unit 220.

At time t6, the current detection signal V _CS exceeds the dimming set value V _ADIM and the reset pulse S11 is asserted. The LEB circuit 210 masks the assertion of the reset pulse S11 during the second time τ2 from the turn-on of the switching transistor M1. As a result, the output pulse S14 is turned off at time t7, and the on time of the switching transistor M1 becomes the second time τ2. When the time t8 coil current I _L becomes zero, the output pulse S14 is the switching transistor M1 turns on level is turned on. In the abnormal state, the operation from time t4 to t8 is repeated.

In a normal state before time t _A, release signal S21 for each cycle is asserted (low level). On the other hand, since the release signal S21 maintains negation (high level) in an abnormal state, once the intermediate determination signal S18 is asserted, the state continues. When the intermediate determination signal S18 is asserted for the determination time τ3, the final determination signal S19 is asserted.

The above is the operation of the control circuit 200. According to the control circuit 200, focusing on the waveforms of the turn-on immediately after the current detection signal V _CS of the switching transistor M1, the abnormal state, based on the fact that the current detection signal V _CS rises quickly detects an abnormality be able to.

The present inventor applies a large voltage to the inductor L1 immediately after the switching converter 100 is activated, depending on circuit constants such as the inductor L1 and the capacitor C1 of the switching converter 100, and the current detection signal. V _CS has recognized that there is a case to rise to the high speed.
Therefore, in the embodiment, the abnormality detection circuit 214 determines that an abnormality occurs when the assertion of the comparison signal S15 during the abnormality detection period τ1 occurs continuously for a predetermined determination time τ3. Thereby, the detection time τ3 is set longer than the activation time, and the abnormality determination is performed, thereby preventing erroneous detection at the activation.

Attention is again directed to FIG. After the time t _A when the abnormality occurs, the pulse width (on time) of the output pulse S14 becomes equal to the minimum on time defined by the second time τ2. Therefore, the abnormality detection circuit 214 of the control circuit 200 determines that the state in which the pulse width of the output pulse S14 is the minimum pulse width (minimum on time) defined by the LEB circuit 210 continues for a predetermined time or a predetermined number of cycles. It can also be understood that it is determined to be abnormal.

  The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. . Hereinafter, such modifications will be described.

(First modification)
FIG. 7 is a circuit diagram of a switching converter 100a according to a first modification. The output circuit 102 is the same as that in FIG. In the control circuit 200a according to the first modification, the dimming setting value (first threshold value) V _ADIM and the threshold voltage (second threshold value) V _TH are equal, and the current limit comparator 202 and the second comparator 212 are A single comparator is shared, and the output of the current limit comparator 202 also serves as the reset pulse S11 and the comparison signal S15. According to this modification, the number of comparators can be reduced and the circuit area can be reduced.

(Second modification)
In the second modification, the processing of the abnormality detection circuit 214 is different from that described above. In the second modification, the abnormality detection circuit 214 determines that there is an abnormality when the assertion of the comparison signal S15 during the abnormality detection period continues for a predetermined number of cycles N.

  Please refer to FIG. The operations of the first timer circuit 216 and the intermediate determination unit 218 are as described above. In the second modification, the final determination unit 220 receives the intermediate determination signal S18 and the output pulse S14 (OUT), and during the period in which the intermediate determination signal S18 is asserted, the output pulse S14 is set to a predetermined cycle number N and on level. When the transition is made, the final determination signal S19 is asserted.

  FIG. 8 is a circuit diagram of the abnormality detection circuit 214 according to the second modification. The intermediate determination unit 218 is the same as in FIG. The final determination unit 220a includes a counter in which the output pulse S14 is input to the clock terminal and the intermediate determination signal S18 is input to the reset terminal (inverted logic). The count value of the counter 220a is counted up according to the output pulse S14 while the intermediate determination signal S18 is asserted (high level). When the count value reaches the predetermined value N, the final determination signal S19 is asserted. Also by this modification, the same effect as the embodiment can be obtained.

(Third Modification)
The abnormality detection circuit 214 may invalidate the abnormality detection for a predetermined time from the start of activation. Thereby, the erroneous detection of the abnormality immediately after starting can be prevented.

(Fourth modification)
The first time τ1 for abnormality detection and the second time τ2 for LEB may be equal. In this case, the first timer circuit 216 and the second timer circuit 236 can be shared, and the circuit area can be reduced. FIG. 9 is a circuit diagram of a control circuit 200b according to a fourth modification. In this modification, the LEB circuit 210 and the abnormality detection circuit 214 share the timer circuit 236 (216).

  The first gate 222 receives the timer signal S22 (S17) and the reset pulse S11 (S15), and outputs the asserted abnormality detection signal S20 when the timer signal S22 is asserted and the reset pulse S11 is asserted. The second gate 224 receives the timer signal S22 (S17) and the reset pulse S11. When the timer signal S22 is negated and the reset pulse S11 is asserted, the second gate 224 outputs the release signal S21 that is asserted. The flip-flop 226 receives the abnormality detection signal S20 at the clock terminal, receives the release signal S21 at the reset terminal (inverted logic), and outputs the intermediate determination signal S18. The third gate 238 performs a logical operation on the timer signal S22 and the reset pulse S11 to generate a masked reset pulse S12. According to this modification, the configuration of the control circuit 200 can be greatly simplified.

(5th modification)
FIG. 10 is a circuit diagram of a switching converter 100b according to a fifth modification. Switching converter 100b includes an auxiliary winding L2 coupled to inductor L1 instead of capacitor C11 and resistor R10. A voltage V _ZT corresponding to the voltage V _L2 generated in the auxiliary winding L2 is input to the ZT terminal of the control circuit 200b. The zero current detection circuit (set pulse generator) 204 asserts the set pulse S13 when the voltage V _ZT of the auxiliary winding L2 crosses a predetermined threshold voltage V _ZERO . Also with this configuration, a pseudo resonance mode can be realized.

(Sixth Modification)
In the embodiment, the switching converter 100 in the quasi-resonant mode has been described. However, the present invention is not limited to this, and can be applied to a separate excitation system. In this case, the set pulse generator 204 may be configured by a timer circuit that asserts the set pulse S13 after a predetermined off time T _OFF has elapsed after the switching transistor M1 is turned on.

(Seventh Modification)
In the present embodiment, the setting of the logic values of the high level and low level of the logic circuit is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

(Eighth modification)
Although the case where the LED light source 502 is an LED string has been described in the embodiment, the type of load is not particularly limited.

  Further, combinations of the above-described embodiments and arbitrary modifications are also effective as aspects of the present invention.

Finally, the use of the switching converter 100 will be described. FIG. 11 is a block diagram of an illumination device 500 that uses the switching converter 100. The illumination device 500 includes a rectifier circuit 504, a smoothing capacitor 506, and a microcomputer 508 in addition to the light emitting unit that is the LED light source 502 and the switching converter 100. Rectifier circuit 504 and smoothing capacitor 506, a commercial AC voltage _{V AC} is rectified smoothed into a DC voltage _{V DC.} The microcomputer 508 generates a control signal S _DIM that indicates the luminance of the LED light source 502. The switching converter 100 receives the direct-current voltage V _DC as the input voltage _VIN , and supplies a drive current I _LED corresponding to the control signal S _DIM to the LED light source 502.

  12A to 12C are diagrams illustrating a specific example of the lighting device 500. FIG. 12A to 12C do not show all the components, and some of them are omitted. The illumination device 500a in FIG. 12A is a straight tube type LED illumination. A plurality of LED elements constituting the LED string that is the LED light source 502 are laid out on the substrate 510. A rectifier circuit 504, a control circuit 200, an output circuit 102, and the like are mounted on the substrate 510.

  The illuminating device 500b of FIG.12 (b) is light bulb type LED illumination. The LED module that is the LED light source 502 is mounted on the substrate 510. The control circuit 200 and the rectifier circuit 504 are mounted inside the housing of the lighting device 500b.

  The illumination device 500c in FIG. 12C is a backlight built in the liquid crystal display device 600. The illumination device 500c irradiates the back surface of the liquid crystal panel 602.

  Or the illuminating device 500 can also be utilized for a ceiling light. As described above, the lighting device 500 of FIG. 11 can be used for various applications.

  Although the present invention has been described based on the embodiments, it should be understood that the embodiments merely illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. It goes without saying that many modifications and changes in arrangement are allowed without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Switching converter, 102 ... Output circuit, 104 ... Input line, 106 ... Output line, C1 ... Smoothing capacitor, D1 ... Rectifier diode, M1 ... Switching transistor, T1 ... Transformer, L1 ... Inductor, L2 ... Auxiliary winding, R _CS : detection resistor, 200: control circuit, 202: current limit comparator, 204: zero current detection circuit, 206 ... logic circuit, 208 ... driver, 210 ... LEB circuit, 212 ... second comparator, 214 ... abnormality detection circuit, 216 ... first timer circuit, 218 ... intermediate determination unit, 220 ... final determination unit, 222 ... first gate, 224 ... second gate, 226 ... flip-flop, 228 ... current source, 230 ... switch, 232 ... comparator, 234 ... Latch, 236... Second timer circuit, 238. S11, S12 ... Reset pulse, S13 ... Set pulse, S14 ... Output pulse, S15 ... Comparison signal, S16 ... Abnormality judgment signal, S17 ... First timer signal, S18 ... Intermediate judgment signal, S19 ... Final judgment signal, S20 ... abnormality detection signal, S21 ... release signal, S22 ... second timer signal, 500 ... illumination device, 502 ... LED light source, 504 ... rectifier circuit, 506 ... smoothing capacitor, 508 ... microcomputer, 510 ... substrate.

Claims (1)

A control circuit for a switching converter,
The switching converter is
An output capacitor provided between the input line and the output line;
An inductor, a switching transistor and a detection resistor provided in series between the output line and the ground line;
A diode having a cathode connected to the input line and an anode connected to a connection point between the inductor and the switching transistor;
With
The control circuit includes:
A first comparator that asserts a reset pulse when a current detection signal corresponding to a voltage drop of the detection resistor exceeds a first threshold;
A set pulse generator that asserts a set pulse at a timing to turn on the switching transistor;
A logic circuit that receives the set pulse and the reset pulse and generates an output pulse; (i) when the set pulse is asserted, the output pulse transitions to an on level corresponding to an on state of the switching transistor; (Ii) when the reset pulse is asserted, a logic circuit that transitions to an off level corresponding to the off state of the switching transistor;
A second comparator that asserts a comparison signal when the current detection signal exceeds a second threshold;
An abnormality detection circuit that determines from the turning on of the switching transistor to the lapse of a first time as an abnormality detection period, and determining that an abnormality occurs when the comparison signal is asserted during the abnormality detection period;
A control circuit comprising:

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