JP2019153742A - Semiconductor device - Google Patents

Abstract

To obtain high breakdown voltage by suppressing creeping discharge.SOLUTION: In a semiconductor device 1, in an outer peripheral region Y which is a region between the outside of an element region X and the end E of a semiconductor substrate 20, three rows of trenches (grooves) T extending in the direction perpendicular to the paper surface in FIG. 1 are formed on the semiconductor substrate 20 from the surface. A thin insulating layer 51 is formed on the entire outer peripheral region Y (region outside the interlayer insulating layer 50). The insulating layer 51 at the bottom of the trench T is made lower than the surface of the semiconductor substrate 20, and therefore, a creeping distance between the element region X and the end E can be increased.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure of a semiconductor device that operates by applying a high voltage.

  In power semiconductor devices such as Schottky diodes and power MOSFETs, a high voltage is applied between the electrodes on the front surface or between the front surface electrode and the back surface electrode. ) Is difficult to occur, and a high withstand pressure is required. Here, the dielectric breakdown between the electrode on the front surface and the electrode on the back surface is known as side discharge that occurs particularly in a region outside the active region of the semiconductor element.

  Patent Document 1 describes a semiconductor device that can suppress such side discharge. In this semiconductor device, on the surface side, a thick insulating layer is formed so as to surround the element region by forming a thick insulating layer so as to surround the electrode around the element region including the electrode. As a result, the element region is formed on the bottom of the mortar-shaped insulating layer having a gently curved inner surface on the surface. Further, a guide electrode having the same potential as the surface electrode (element region) is provided on the inner surface of the curved surface. Thereby, the occurrence of dielectric breakdown due to electric field concentration around the element region is suppressed, and the side discharge is suppressed, so that the breakdown voltage of the semiconductor device can be increased.

JP 2001-291860 A

  As described above, in a semiconductor device in which dielectric breakdown occurs due to a potential difference between the back surface side and the front surface side, a creeping discharge in which a current flows along the exposed insulating layer surface occurs, and the breakdown voltage is limited by the creeping discharge. There are many cases. In such a point, in the semiconductor device described in Patent Document 1, since current may flow from the surface electrode or the outer guide electrode through the surface of the outer insulating layer, this creeping discharge is sufficiently suppressed. It was difficult to do. For this reason, in the semiconductor device described in Patent Document 1, it is difficult to sufficiently suppress the dielectric breakdown (discharge) between the back surface side and the front surface side. For this reason, a semiconductor device that can obtain a high breakdown voltage by suppressing creeping discharge has been desired.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention is a semiconductor device in which a semiconductor element is formed in an element region that is a region separated from an end on the surface side of the semiconductor substrate in plan view, and the element region and the end in plan view In the outer peripheral region that is a region between the groove and the semiconductor substrate, a groove is formed by digging from the surface, and the inner surface of the groove and the surface of the semiconductor substrate in the outer peripheral region have a height on the bottom surface side of the groove. An insulating layer is formed so that is lower than the surface.
The semiconductor device of the present invention is characterized in that the groove is formed so as to surround the element region in plan view.
The semiconductor device according to the present invention is characterized in that a plurality of the grooves are formed in the outer peripheral region.
The semiconductor device of the present invention is characterized in that a main electrode is formed on each of the element region on the front surface side of the semiconductor substrate and on the back surface side of the semiconductor substrate.
In the semiconductor device according to the present invention, the groove has a tapered shape whose width is narrowed according to the depth.
In the semiconductor device according to the present invention, the groove has an inversely tapered shape whose width increases with depth.
The semiconductor device according to the present invention is characterized in that the insulating layer is formed thicker in accordance with the depth inside the groove.
The semiconductor device according to the present invention is characterized in that the insulating layer is formed thinly in accordance with the depth inside the groove.
The semiconductor device of the present invention is characterized in that the semiconductor substrate is made of a wide band gap semiconductor material.

  Since the present invention is configured as described above, a high breakdown voltage can be obtained by suppressing creeping discharge.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a top view which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the creeping path | route in the trench vicinity in the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of two types of examples of the structure in the trench in the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the condition at the time of dicing of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the 1st modification of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the 2nd modification of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the 3rd modification of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the 4th modification of the semiconductor device which concerns on embodiment of this invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. In this semiconductor device, a Schottky barrier diode (SBD) serving as a power semiconductor element is formed on the surface of a semiconductor substrate, and an electrode (anode electrode) on the surface in contact with the Schottky is provided on the surface. On the other hand, the cathode electrode is provided on the back surface side, and a high voltage is applied between the anode electrode and the cathode electrode particularly when the cathode electrode is off.

  FIG. 1 is a cross-sectional view showing the structure of the semiconductor device 1. Here, in order to show the characteristics of the structure in a simplified manner, the structure is shown in a state in which the aspect ratio is different from the actual one. The semiconductor device 1 is formed on a semiconductor substrate 20. The semiconductor material constituting the semiconductor substrate 20 is a material that can constitute a power semiconductor element, such as silicon (Si), silicon carbide (SiC), nitride compound semiconductor (GaN, etc.), and the like.

In the semiconductor substrate 20, an n-type layer (semiconductor layer) 22 which becomes a drift layer in the SBD and is doped at a low concentration is formed on the n ⁺ layer 21 having high conductivity because it is doped n-type at a high concentration by epitaxial growth. Is formed. An anode electrode layer (main electrode) 30 that is in Schottky contact with the n-type layer 22 is formed on the n-type layer 22 so as to be in direct contact with the n-type layer 22 locally. Although simplified and described as a single layer in FIG. 1, the anode electrode layer 30 is actually a metal that is in direct contact with the n-type layer 22 and creates a Schottky barrier between the n-type layer 22. Thus, a laminated structure including a thin Schottky electrode layer and a thick wiring metal layer having a lower resistance than that of the Schottky electrode layer is formed.

A p-type layer 23 that forms a guard ring is formed on the surface of the semiconductor substrate 20 that is in contact with the outer peripheral portion of the anode electrode layer 30. Further, a cathode electrode layer (main electrode) 40 that is in ohmic contact with the n ⁺ layer 21 is formed on the back surface side of the semiconductor substrate 20. In the semiconductor device 1, a high voltage is applied between the anode electrode layer 30 on the front surface side and the cathode electrode layer 40 on the back surface side. For this reason, the interlayer insulating layer 50 is formed on the surface side of the region operating as a Schottky barrier diode in a state in which a portion that is in electrical contact with a bonding wire or the like is exposed. The interlayer insulating layer 50 is made of SiO ₂ or the like having a high insulation resistance and is formed thick by a CVD method or the like. When a forward voltage is applied between the anode electrode layer 30 and the cathode electrode layer 40, a large current flows between them. This current flows vertically in the semiconductor substrate 20 in the element region X in FIG.

  Here, in the semiconductor device 1, a trench (groove) extending in a direction perpendicular to the paper surface in FIG. 1 in an outer peripheral region Y, which is a region between the outside of the element region X and an end E (outer periphery) of the semiconductor substrate 20. T) is formed on the semiconductor substrate 20 from the surface over three rows. FIG. 2 is a plan view of the semiconductor device 1 as seen from the surface, and FIG. 1 shows a cross-sectional view in the AA direction. In the semiconductor device 1, a region (element region X) through which current flows during operation is substantially equal to the anode electrode layer 30 in plan view. In FIG. 2, the trenches T are formed in three rows so as to surround the element region X (the anode electrode layer 30). Of these, the end (outer periphery) E or the semiconductor substrate 20 is formed outside the outermost trench T. Sides are located. Here, in FIG. 1, the cross-sectional shape of the trench T is assumed to be a rectangular shape, and other cases will be described later.

In FIG. 1, a thin insulating layer 51 is formed on the entire outer peripheral region Y (region outside the interlayer insulating layer 50). Since the insulating layer 51 is thin and conformal, it is uniformly formed over the entire surface including the inner surface of the trench T, as shown in FIG. Yes. For example, the insulating layer 51 can be formed by thinly forming SiO ₂ or SiN by a CVD method or the like. At this time, the film forming conditions are selected so that they can be formed conformally.

  Thus, by forming the trench T in the outer peripheral region Y and forming the insulating layer 51 on the entire surface including the inner surface of the trench T in the outer peripheral region Y, the exposed anode electrode layer from the end E of the semiconductor substrate 20. The creepage distance up to 30 can be increased. In FIG. 3, P0 is a path (creeping path) constituting a creeping distance when the trench T is not formed, and P1 is a path (creeping path) constituting the creeping distance in the structure of FIG. This is shown schematically at the points. Here, the creepage distance is a distance along the surface made of an insulator between the end E and the exposed anode electrode layer 30. In the configuration of FIG. 1, the creeping path P1 can be set longer than the creeping path P0, so that the breakdown voltage of the semiconductor device 1 can be increased. That is, the trench T itself in which the insulating layer 51 is formed on the inner surface as described above does not function electrically actively, but this can increase the breakdown voltage.

  1 and 3, since the insulating layer 51 is sufficiently thinner than the opening width of the trench T, the insulating layer 51 is formed with a uniform thickness on the inner surface of the trench T. However, in practice, the thickness of the insulating layer 51 is often not uniform in the trench T. FIGS. 4A and 4B are diagrams showing an example of such a case corresponding to FIG. In FIG. 4A, the insulating layer 51 is thick on the bottom side of the trench T, and the surface of the insulating layer 51 at the bottom of the trench T is deeper than the surface of the semiconductor substrate 20 (n-type layer 22). In the figure, D> 0. On the other hand, FIG. 4B shows a state in which the insulating layer 51 is too thick so that the trench T is completely buried by the insulating layer 51, which corresponds to a state where D <0 in FIG. . As described above, from the viewpoint of increasing the creepage distance, the form of FIG. 4B is not preferable, and the form of FIG. 4A is preferable. That is, by making the insulating layer 51 on the bottom surface of the trench T lower than the surface of the semiconductor substrate 20, the creepage distance between the element region X and the end E can be increased as described above.

  4 (a) and 4 (b), the trench T is densely embedded with the insulating layer 51. However, even when a void is formed inside the trench T, the outermost surface thereof is shown in FIG. ) The situation is the same if it is similar to (b). However, when there is a void, there are other problems such as a decrease in insulation and instability due to the void itself. Therefore, as shown in FIG. Is preferably made sufficiently thin. Specifically, the opening width of the trench T in FIG. 1 is preferably about 2 μm, the depth is 5 μm or more, and the thickness of the insulating layer 51 is preferably several hundred nm or more.

  Further, by providing the trench T that does not function electrically in the outer peripheral region Y as described above, the yield in manufacturing the semiconductor device 1 can be increased. This will be described below. In manufacturing the semiconductor device 1, a large number of structures shown in FIG. 1 are actually arranged on a semiconductor wafer to be a semiconductor substrate 20. Thereafter, the semiconductor wafer 1 is diced and cut and separated, whereby a plurality of semiconductor devices 1 each having the structure of FIG. 1 can be obtained.

  FIG. 5 is a cross-sectional view showing the situation at the time of dicing, and shows the situation when the semiconductor wafer 100 to be the semiconductor substrate 20 is cut from the upper side by a dicing saw (cutting blade) B. FIG. During this work, a crack C may occur in the semiconductor substrate 20 due to the force applied from the dicing saw B. If the crack C extends to the element region X, the electrical characteristics of the semiconductor device 1 after cutting may be adversely affected.

  On the other hand, in the semiconductor device 1 described above, the innermost extension of the crack C can be suppressed by the outermost trench T. At this time, the trench T itself does not actively function in the operation of the semiconductor device 1 and the creeping distance to the end E can be increased as described above. For this reason, the yield at the time of manufacture of the semiconductor device 1 which comprises the structure of FIG. 1 can be raised.

As the material constituting the insulating layer 51, various materials can be used as long as the insulating property and the cross-sectional structure as described above can be realized. For example, an organic film such as polyimide can be used instead of SiO ₂ and SiN as described above. The film forming method can be appropriately set according to the material, the opening width of the trench, and the like.

  Further, the cross-sectional shape of the trench T and the form of the insulating layer 51 can be set in order to make the manufacturing easier or to make the creeping distance longer. FIG. 6 is a diagram showing a structure of a semiconductor device 2 as a first modified example that is easier to manufacture, corresponding to FIG.

  The cross-sectional shape of the trench T <b> 1 formed here is a tapered shape whose width becomes narrower according to the depth. In the case of this structure, it is easy to form the insulating layer 51 uniformly up to the bottom surface of the trench T1. For this reason, manufacture becomes especially easy.

  Moreover, the structure of the semiconductor device 3 which becomes a 2nd modification is shown in FIG. The cross-sectional shape of the trench T2 in this modified example is a rectangular shape like the trench T in FIG. However, here, in the trench T2, the insulating layer 51 is thin on the entrance side and thick on the bottom side. Depending on the type of the insulating layer 51 and the film forming method, the film thickness distribution of the insulating layer 51 takes such a form, but in this case as well, the above-described effect that the creeping distance from the end E is increased by this structure is the same. It is. In addition, when the insulating layer 51 is thinly formed, the insulating layer 51 may not be sufficiently formed particularly at the bottom end of the trench. In this case, the n-type layer 22 may be exposed. On the other hand, it is possible to prevent the n-type layer 22 from being exposed on the bottom surface side by adopting film forming conditions that can obtain the insulating layer 51 having the form shown in FIG.

  The structures of the semiconductor devices 4 and 5 as the third and fourth modified examples are similarly shown in FIGS. In these modified examples, although the manufacturing is somewhat difficult, the creepage distance can be further increased as compared with the semiconductor device 1 of FIG.

  The cross-sectional shape of the trench T3 formed in the semiconductor device 4 shown in FIG. 8 is a rectangular shape similar to the trench T in FIG. On the other hand, the insulating layer 51 is thicker at the entrance side of the trench T3 and thinner at the bottom side than the case of the semiconductor device 3 described above. For this reason, the cross-sectional shape of the surface of the insulating layer 51 in the trench T3 is an inversely tapered shape in which the opening becomes wider according to the depth, contrary to the cross-sectional shape of the surface of the insulating layer 51 in the trench T2 in FIG. Thereby, the creepage distance can be made larger than in the case of FIG. Such a film thickness distribution of the insulating layer 51 can be realized by adjusting the film forming conditions when the insulating layer 51 is formed by the CVD method.

  On the other hand, in the semiconductor device 5 shown in FIG. 9, the thickness of the insulating layer 51 is uniform, but the sectional shape of the formed trench T4 is the sectional shape of the surface of the insulating layer 51 in FIG. It is the same reverse taper shape as. Even in this case, the creepage distance can be increased as in the structure of FIG. The trench T4 having such a reverse taper shape can be realized by adjusting the dry etching conditions for forming the trench.

  In the above example, the trenches are formed over three rows. However, the creepage distance can be further increased by increasing the number of trenches. On the other hand, in this case, since the outer peripheral area Y is widened, the area of the entire semiconductor device is increased, making it difficult to reduce the cost of the semiconductor device. Alternatively, when the area of the entire semiconductor device is determined, it is difficult to increase the element region X, and it is difficult to increase the operating current. Even if only one row of trenches is formed, the creepage distance is smaller than when many trenches are provided, but the creepage distance can be increased as compared with the case where no trench is used. The number of trenches is set in consideration of such a situation.

  In the above example, the trench is formed so as to surround all sides in the element region X in plan view. However, the form of the trench is set according to the form of the semiconductor device, the potential distribution inside, and the like. For example, in FIG. 2, when creeping discharge is likely to occur on a specific side in plan view, trenches may be provided in a row only on this side without surrounding the element region (anode electrode layer 30). Similarly, in FIG. 2, it is not necessary that the trench T is continuously formed around the entire periphery of the element region.

  In the above example, a Schottky barrier diode is formed in which one of the main electrodes is provided in the element region on the front surface and the other of the main electrodes is provided on the back surface side in the semiconductor substrate. However, as long as the semiconductor device generates a large potential difference between the element region provided on the front surface side of the semiconductor substrate and the back surface side, the above configuration is also effective in a semiconductor device having another structure. . Such a situation is particularly prominent in a semiconductor device that operates by flowing a large current in the thickness direction of the semiconductor substrate. For example, when the power MOSFET is formed in the element region and the current MOSFET is operated in the thickness direction of the semiconductor substrate, the structure in the outer peripheral region Y can be similarly used. The same applies to pn junction diodes, IGBTs, bipolar transistors, and the like when the potential difference between the front surface side and the back surface side becomes large.

  At this time, for example, when a trench type power MOSFET or IGBT is formed in the element region, the trench in the outer peripheral region and the trench in the element region can be formed simultaneously. Therefore, the above semiconductor device can be manufactured through a particularly simple process.

  When the semiconductor substrate 20 is made of a wide band gap semiconductor material such as silicon carbide (SiC) or a nitride compound semiconductor (GaN, etc.) having a dielectric breakdown electric field larger than that of silicon (Si), it is made of silicon (Si). There is an advantage that the chip area can be reduced as compared with the case. However, on the other hand, the creeping path P0 in FIG. 3 is shorter than that in the case where the semiconductor substrate 20 is made of silicon (Si), and the problem that creeping discharge is likely to occur becomes remarkable. Therefore, when the semiconductor substrate 20 is made of a wide band gap semiconductor material, it is particularly preferable to form the creeping path P1 by applying the present invention.

1 to 5 Semiconductor device 20 Semiconductor substrate 21 n ⁺ layer 22 n-type layer 23 p-type layer 30 Anode electrode layer (main electrode)
40 Cathode electrode layer (main electrode)
50 Interlayer Insulating Layer 51 Insulating Layer B Dicing Saw C Crack E Edges P0, P1 Creepage Path T, T1-T4 Trench (Groove)
X Element area Y Perimeter area

Claims (9)

A semiconductor device in which a semiconductor element is formed in an element region that is a region separated from an end portion on the surface side of the semiconductor substrate in a plan view,
In an outer peripheral region that is a region between the element region and the end portion in plan view, a groove is formed by digging the semiconductor substrate from the surface, and an inner surface of the groove in the outer peripheral region and a surface of the semiconductor substrate Further, the semiconductor device is characterized in that an insulating layer is formed so that the height of the groove on the bottom side is lower than the surface.   2. The semiconductor device according to claim 1, wherein the groove is formed so as to surround the element region in a plan view.   The semiconductor device according to claim 1, wherein a plurality of the grooves are formed in the outer peripheral region.   4. The semiconductor device according to claim 1, wherein a main electrode is formed on each of the element region on the front surface side of the semiconductor substrate and on a back surface side of the semiconductor substrate.   5. The semiconductor device according to claim 1, wherein the groove has a tapered shape whose width is narrowed according to a depth.   5. The semiconductor device according to claim 1, wherein the groove has an inversely tapered shape whose width increases with depth.   7. The semiconductor device according to claim 1, wherein the insulating layer is formed thicker in accordance with a depth inside the groove.   6. The semiconductor device according to claim 1, wherein the insulating layer is formed thinly in accordance with a depth inside the groove. 6.   9. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide band gap semiconductor material.

Images