JP2019147248A - Liquid discharge device - Google Patents

Abstract

To enhance waveshape precision of a driving signal and suppress deterioration in liquid discharging accuracy.SOLUTION: A driving circuit 122a comprises: a comparator 1204 that compares a voltage of an original driving signal Ca with a voltage of a return signal of a driving signal Com-A; transistors 231 and 232; a control signal generating circuit 126 that generates a gate signal Gp to the transistor 231 and a gate signal Gn to the transistor 232; and a constant potential circuit 202a. The constant potential circuit 202a outputs a voltages corresponding to the original driving signal Ca when a switch 293 is turned on by a signal FLsa.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a liquid ejection apparatus, for example.

  As an example of a liquid ejecting apparatus, an ink jet printer that ejects ink and prints an image or a document is known. In an inkjet printer, a piezoelectric element (for example, a piezo element) is used to eject ink, and the piezoelectric element is provided corresponding to each of a plurality of nozzles in a print head. Each of the piezoelectric elements is driven according to a drive signal, whereby a predetermined amount of ink is ejected from the nozzle at a predetermined timing to form dots. Since the piezoelectric element is a capacitive load such as a capacitor when viewed electrically, it is necessary to supply a sufficient current to operate the piezoelectric element of each nozzle.

For this reason, the ink jet printer is configured to amplify an original drive signal, which is a source of the drive signal, by an amplifier circuit and supply the amplified drive signal to the print head as a drive signal to drive the piezoelectric element. An example of the amplifier circuit is a method of amplifying the current of the original drive signal with a class AB or the like (linear amplification method, for example, see Patent Document 1).
However, since power consumption is large and energy efficiency is low in the linear amplification method, in recent years, a class D amplification method has been proposed (see, for example, Patent Document 2). Briefly speaking, the class D amplification method performs pulse modulation on the original drive signal, and switches the high-side transistor and the low-side transistor inserted in series between the power supply voltages according to the pulse-modulated signal, and outputs by this switching. The original drive signal is amplified by filtering the signal with a low-pass filter.

  The class D amplification method has higher energy efficiency than the linear amplification method, but the power consumed by the low-pass filter cannot be ignored. For this reason, a new type of drive circuit has been proposed for the purpose of further improving power consumption (see Patent Document 3).

JP 2009-190287 A JP 2010-114711 A JP 2017-149064 A

  However, with the new drive circuit, the power consumption can be improved, but when the number of nozzles (the number of piezoelectric elements) increases significantly in order to meet the demand for high-speed printing and high-definition printing, the drive signal There was a problem that the waveform accuracy deteriorated and the liquid discharge accuracy decreased.

  In order to solve one of the above problems, a liquid ejection apparatus according to an aspect of the present invention includes a nozzle and a piezoelectric element that is displaced when a drive signal is applied, and the displacement of the piezoelectric element causes the above-described displacement. A print head that ejects liquid from the nozzles, a comparator that compares the voltage of the original drive signal with the voltage of a feedback signal that is a signal obtained by feeding back the drive signal, a first transistor having a first gate terminal, A second transistor having two gate terminals, a pair of transistors that outputs the driving signal, and an output signal of the comparator, and a first control signal that controls a switching operation of the first transistor and the first transistor The second control signal for controlling the switching operation of the two transistors is alternated between the first transistor and the second transistor. A control signal generation circuit that is generated so as to be turned on, and a constant potential circuit that is electrically connected to the piezoelectric element via a switch, and the drive signal includes the first transistor and the second transistor. A first region where the voltage of the drive signal rises alternately, a second region where the first transistor and the second transistor alternately turn on, and the voltage of the drive signal falls; The first transistor and the second transistor are turned off, between the first region and the second region, a third region following the second region, the first transistor and the second transistor And a fourth region that is between the first region and the second region and continues to the first region, and the constant potential circuit has the third region or the fourth region, Previous By turning on the switches, and outputs a drive signal having a voltage corresponding to the original drive signal.

In the liquid ejection device according to the above aspect, the first transistor and the second transistor are alternately turned on based on the comparison result between the voltage of the original drive signal and the voltage of the feedback signal of the drive signal. Ascending and descending are repeated alternately, that is, they vibrate. Here, in the first region or the second region, when the voltage of the feedback signal becomes higher than the voltage of the original drive signal, the second transistor is quickly turned on, the voltage of the drive signal decreases, and the voltage of the feedback signal becomes the original. When the voltage becomes lower than the voltage of the drive signal, the first transistor is quickly turned on to increase the voltage of the drive signal. Therefore, according to the liquid ejection device according to the above aspect, the voltage followability of the drive signal with respect to the original drive signal is improved, so that the liquid ejection accuracy can be improved along with the waveform accuracy of the drive signal.
In the liquid ejection device according to the above aspect, in the third region or the fourth region, when the switch is turned on, a drive signal having a voltage corresponding to the original drive signal is output, so that the vibration width is suppressed to almost zero. Can do.
For this reason, according to the liquid ejection apparatus according to the above aspect, the waveform accuracy of the drive signal can be improved.
Note that the term “connection” means any direct or indirect connection or coupling between two or more elements, with one or more intermediate elements between two elements “connected” to each other. Including being present.

In the liquid ejection device according to the above aspect, the constant potential circuit may include a linear amplifier that outputs a voltage corresponding to the original drive signal.
According to the above configuration, in the third region or the fourth region where both the first transistor and the second transistor are turned off, a drive signal without vibration can be output with high accuracy by the linear amplifier.
The linear amplifier is used in the sense that the first transistor and the second transistor are alternately turned on, that is, different from the switching amplifier. Further, in the third region or the fourth region, the voltage of the drive signal is in a constant state (including a state that can be regarded as substantially constant), so that a high driving capability is not required for the linear amplifier.

In the liquid ejection apparatus according to the above aspect, the constant potential circuit may include a power supply line to which a voltage according to the original drive signal is applied.
According to the above configuration, the voltage applied to the feeder line is output as the drive signal in the third region or the fourth region, so that a constant potential circuit can be realized with a simple configuration.

The liquid ejecting apparatus according to the above aspect further includes a switch control circuit that turns on the switch when the current of the drive signal becomes a threshold value or less during a period in which the voltage of the original drive signal is constant. It is also good.
According to the above configuration, since the switch is turned on when the current of the drive signal becomes equal to or lower than the threshold during the period when the voltage of the original drive signal is constant, the occurrence of spike noise or the like caused by turning on the switch can be suppressed. In addition, the error of the drive signal with respect to the original drive signal can be reduced.

In order to solve one of the above-described problems, a liquid ejection apparatus according to another aspect of the present invention includes a nozzle and a piezoelectric element that is displaced when a drive signal is applied. A print head that ejects liquid from the nozzles, a comparator that compares the voltage of the original drive signal with the voltage of a feedback signal that is a signal obtained by feeding back the drive signal, a first transistor having a first gate terminal, A first transistor pair that outputs a drive signal when the voltage of the original drive signal is in a first range; and a third transistor that has a third gate terminal; And a fourth transistor having a fourth gate terminal, and outputs the drive signal when the voltage of the original drive signal is in a second range higher than the first range. The output signal of the second transistor pair and the comparator is input, and the first control signal for controlling the switching operation of the first transistor or the third transistor and the switching operation of the second transistor or the fourth transistor are controlled. A control signal generating circuit that generates a second control signal to be turned on alternately by the first transistor and the second transistor or the third transistor and the fourth transistor, and via a switch A constant potential circuit electrically connected to the piezoelectric element, wherein the constant potential circuit is when the voltage of the original drive signal is in the first range and in a constant period, When a switch is turned on, a drive signal having a voltage corresponding to the original drive signal is output. That.
According to the liquid ejection device according to the above aspect, the voltage followability of the drive signal with respect to the original drive signal is increased as in the liquid ejection device according to the above aspect. Can be improved. Furthermore, according to the liquid ejection device according to the other aspect, the withstand voltage of the constituent elements in the comparator and the control signal generation circuit may be low as compared with the liquid ejection device according to the above aspect. Etc. can be suppressed.

In the liquid ejection device according to the above aspect, the first transistor and the second transistor may be alternately turned on during a period in which the voltage of the original drive signal increases.
According to this configuration, when the voltage of the drive signal rises following the voltage of the original drive signal, if the voltage of the feedback signal becomes higher than the voltage of the original drive signal, the voltage of the drive signal quickly increases. When the voltage of the feedback signal becomes lower than the voltage of the original drive signal, the voltage of the drive signal immediately changes from the fall to the rise, so that the ripple generated in the drive signal is reduced. Therefore, in the above configuration, the waveform accuracy of the drive signal is increased, and the liquid ejection accuracy can be improved.

In the liquid ejection device according to the above aspect, the first transistor and the second transistor may be alternately turned on during a period in which the voltage of the original drive signal decreases.
According to this configuration, when the voltage of the drive signal decreases following the voltage of the original drive signal, the voltage of the drive signal starts to decrease rapidly if the voltage of the feedback signal becomes lower than the voltage of the original drive signal. When the voltage of the feedback signal becomes higher than the voltage of the original drive signal, the voltage of the drive signal immediately changes from the rise to the drop, so that the ripple generated in the drive signal is reduced. Therefore, in the above configuration, the waveform accuracy of the drive signal is increased, and the liquid ejection accuracy can be improved.

In the liquid ejection apparatus according to the above aspect, the print head may include 600 or more nozzles arranged at a density of 300 or more per inch.
In a configuration in which the head includes 600 or more nozzles arranged at a density of 300 or more per inch, the load of the drive circuit increases and the current I increases. Therefore, the drive signal includes the parasitic inductance L and the current I. Noise with a magnitude proportional to the product of the change rate (L × dI / dt) is superimposed, and a large ripple is likely to occur. In the liquid ejection device having this configuration, the followability of the voltage of the drive signal to the voltage of the original drive signal is high even during the period in which the voltage of the original drive signal rises or falls, so the number of driven piezoelectric elements increases. Even when the load increases, the ripple generated in the drive signal can be kept small. Therefore, in the above configuration, the waveform accuracy of the drive signal is increased, and the liquid ejection accuracy can be improved.

1 is a perspective view showing an ink jet printer according to an embodiment. It is a figure which shows the internal structure of an inkjet printer. It is a figure which shows an example of a nozzle arrangement | sequence. It is sectional drawing which shows the structure of an actuator module. It is a block diagram which shows the electrical structure of an inkjet printer. It is a block diagram which shows the structure of a drive part and a print head. It is a figure which shows the structure of a drive circuit. It is a figure which shows the detailed structure of a drive circuit. It is a figure which shows an example of a structure of a control signal generation circuit. 6 is a timing chart for explaining the operation of the drive circuit. 3 is a timing chart for explaining the operation of a control signal generation circuit. It is a figure which shows waveforms, such as a drive signal. It is a figure which expands and shows a waveform etc. of a drive signal partially. It is a figure which expands and shows a waveform etc. of a drive signal partially. It is a figure which shows another structure of a constant potential circuit. It is a figure which shows the structure of the drive circuit which concerns on a 1st application example. It is a figure for demonstrating operation | movement of the drive circuit which concerns on a 1st application example. It is a figure which shows an example of the characteristic of the applied voltage-displacement in a piezoelectric element. It is a figure which shows the structure of the conventional drive circuit. It is a figure for demonstrating operation | movement of the conventional drive circuit. It is a partial enlarged view of a waveform of a drive signal generated by a conventional drive circuit. It is a partial enlarged view of a waveform of a drive signal generated by a conventional drive circuit.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In each figure, the size and scale of each part are appropriately changed from the actual ones. Further, since the embodiments described below are preferable specific examples of the present invention, various technically preferable limitations are attached thereto. However, the scope of the present invention is particularly limited in the following description. Unless otherwise stated, the present invention is not limited to these forms.

FIG. 1 is a diagram illustrating a configuration of an ink jet printer 1 which is an example of a liquid ejection apparatus according to an embodiment.
The inkjet printer 1 prints an image on the surface of the medium P by ejecting ink, which is an example of a liquid, onto the medium P. The medium P is a sheet, a film, or the like that is an ejection target of ink. The ink jet printer 1 is a printing apparatus (LFP: Large Format Printer) capable of printing on a medium-sized medium P of A3 or larger according to international standards, and includes a housing 12 and legs 14 as shown in the figure. Have.

The housing 12 is a long structure along the X direction corresponding to the width direction of the medium P. In the present embodiment, a plurality of liquid containers 16 that store different types of ink are mounted on the housing 12. The leg portion 14 supports the housing 12 at a predetermined height.
The plurality of liquid containers 16 may be configured to store the same type of ink.

In the following description, the vertical direction, that is, the direction of action of gravity is expressed as the Z direction, and the direction perpendicular to the XZ plane, that is, the feeding direction of the medium P is expressed as the Y direction.
In the figure, the lid member 22 is a cover that is pivotally supported by a rotating shaft 23 that is parallel to the X direction, and the user can manually open and close the lid member 22.

FIG. 2 is a diagram illustrating an internal configuration of the inkjet printer 1.
As shown in this figure, the control module 10, the carriage 18, the transport mechanism 80, and the moving mechanism 90 are accommodated inside the inkjet printer 1. In the present embodiment, a head module 20 including a plurality of print heads 30 is mounted on the carriage 18.
When the image data is supplied from an external host computer, the control module 10 prints an image defined by the image data on the medium P, specifically, each element in the inkjet printer 1, specifically, a print head. 30, the transport mechanism 80 and the moving mechanism 90 are controlled.

  The transport mechanism 80 transports the medium P in the Y direction. Specifically, the transport mechanism 80 includes a transport roller 81 whose rotation axis is parallel to the X direction, and a drive unit (for example, a motor) 82 that rotates the transport roller 81 under the control of the control module 10. Note that a mechanism that rotates a roll around which the medium P is wound and supplies the roll to the inside of the housing 12 may be used, or a mechanism that winds the medium P discharged from the housing 12 may be used.

The carriage 18 carries the head module 20 and reciprocates along the X direction by the moving mechanism 90. Specifically, the moving mechanism 90 includes the endless belt 94 installed along the X direction, the guide shaft 96 that restricts the movement of the carriage 18 in a direction substantially parallel to the X direction, and the endless belt 94. And a drive unit (for example, a motor) 92 that is driven under the control of the above.
The head module 20 is supplied with various drive signals and control signals from the control module 10 via a flexible FFC (Flexible Flat Cable) 190. Since the inkjet printer 1 according to this embodiment supports large format printing as described above, the working area of the carriage 18 is lengthened.
When the operating area of the carriage 18 becomes longer, the FFC 190 needs to be made longer. In the present embodiment, the size of the medium P that can be printed by the inkjet printer 1 is set to A3 or more, but the upper limit is set to 75 inches. When the size of the medium P exceeds 75 inches, the impedance component of each wiring in the FFC 190 becomes too large, the voltage drop of the drive signal becomes large, the printing accuracy and printing stability are lowered, and ink is erroneously discharged. This is because the possibility increases.
In addition to the FFC 190, the head module 20 is supplied with ink of each color from the liquid container 16 through a tube, which is not shown.

FIG. 3 is a diagram illustrating a configuration when the ink ejection surface of the head module 20 is viewed from the medium P. As shown in this figure, the head module 20 has a plurality of print heads 30 arranged side by side along the X direction. When viewed from the medium P, one print head 30 has two nozzle rows L1 and L2 that are long in the Y direction and are spaced apart in the X direction, and one nozzle row L1 or L2 is Y The nozzles N are arranged at a pitch Py along the direction.
In the example shown in the figure, the nozzles N belonging to the nozzle row L1 and the nozzles N belonging to the nozzle row L2 have a configuration in which the coordinates in the Y direction are shifted by almost half of the pitch Py, but the positions in the Y direction are almost the same. It may be a sequence that matches.
If the number of nozzles N in one nozzle row L1 or L2 is m (m is an integer of 2 or more), the number of nozzles N in one print head 30 is “2 m”.

  Here, in this embodiment, the nozzles N in one nozzle row L1 or L2 are actually provided with a density of 300 or more per inch and a length of 1 inch or more. For this reason, in one print head 30, 600 or more nozzles N are provided in two rows of nozzle rows L1 and L2.

  For example, one color of black, cyan, magenta, and yellow is assigned to the plurality of print heads 30, and one print head 30 ejects the assigned one color ink from the nozzles N. A configuration in which different colors of ink are ejected from the nozzles N in the nozzle rows L1 and L2 in one print head 30 may be employed.

  When viewed electrically, one print head 30 is roughly divided into an actuator module including a piezoelectric element and the like, and an IC module that selects a drive signal to each piezoelectric element, as will be described later. First, the actuator module in the print head 30 will be described.

FIG. 4 is a cross-sectional view showing the structure of the actuator module 40. Specifically, FIG. 4 is a diagram showing a cross section (a cross section fractured substantially along the ZX plane) when the actuator module of the print head 30 in FIG. 3 is broken along the line gg.
As shown in FIG. 4, in the actuator module 40, the pressure chamber substrate 44, the diaphragm 46, the sealing body 52, and the support body 54 are provided on the negative side surface in the Z direction of the flow path substrate 42. On the other hand, it is a structure in which the nozzle plate 62 and the compliance portion 64 are installed on the positive side surface in the Z direction. Similarly to the print head 30, the actuator module 40 is also a substantially flat member that is long in the Y direction, and is fixed to each other using, for example, an adhesive. The flow path substrate 42 and the pressure chamber substrate 44 are formed of, for example, a silicon single crystal substrate.

  The nozzle N is formed on the nozzle plate 62. As schematically described in FIG. 3, in the print head 30, the nozzle N belonging to the nozzle row L1 and the structure corresponding to the nozzle N belonging to the nozzle row L2 have a relationship shifted by half the pitch Py in the W1 direction. However, since it is formed substantially symmetrically in other cases, the following description will focus on the nozzle row L1.

  The flow path substrate 42 is a flat plate material that forms an ink flow path, and an opening 422, a supply flow path 424, and a communication flow path 426 are formed. The supply channel 424 and the communication channel 426 are formed for each nozzle, and the opening 422 is formed so as to be continuous over a plurality of nozzles that eject the same color ink.

A support body 54 is fixed to the surface of the flow path substrate 42 on the negative side in the Z direction. The support 54 is formed with an accommodating portion 542 and an introduction channel 544. The accommodating portion 542 is a concave portion (dent) having an outer shape corresponding to the opening 422 of the flow path substrate 42 in a plan view (that is, viewed from the Z direction), and the introduction flow path 544 communicates with the accommodating portion 542 It is.
A space in which the opening 422 of the flow path substrate 42 and the accommodating portion 542 of the support 54 communicate with each other functions as a liquid storage chamber (reservoir) Sr. The liquid storage chamber Sr stores the ink that has passed through the liquid container 16 (see FIG. 1) and the introduction flow path 544. Note that the liquid storage chamber Sr may be formed independently for each color of ink, but in the present embodiment, for simplicity of explanation, one print head 30 (actuator module 40) The ink of the same color is stored in common over 2 m nozzles N.

  The element that constitutes the bottom surface of the liquid storage chamber Sr and suppresses (absorbs) ink pressure fluctuations in the liquid storage chamber Sr and the internal flow path is the compliance section 64. The compliance part 64 includes a flexible member formed in a sheet shape, for example. Specifically, the compliance part 64 has a flow path so as to close the opening 422 and each supply flow path 424 in the flow path substrate 42. It is fixed to the surface of the substrate 42.

A diaphragm 46 is installed on the surface of the pressure chamber substrate 44 opposite to the flow path substrate 42. The vibration plate 46 is a plate-like member that can elastically vibrate, and is configured by stacking an elastic film formed of an elastic material such as silicon oxide and an insulating film formed of an insulating material such as zirconium oxide. Is done. The diaphragm 46 and the flow path substrate 42 are opposed to each other with an interval inside each opening 442 of the pressure chamber substrate 44. A space sandwiched between the flow path substrate 42 and the diaphragm 46 inside each opening 442 functions as a pressure chamber Sc that applies pressure to the ink. Each pressure chamber Sc communicates with the nozzle N via the communication channel 426 of the channel substrate 42.
A piezoelectric element Pzt corresponding to the nozzle N (pressure chamber Sc) is formed on the surface of the diaphragm 46 opposite to the pressure chamber substrate 44.

  The piezoelectric element Pzt includes a driving electrode 72 formed individually for each piezoelectric element Pzt on the surface of the diaphragm 46, a piezoelectric body 74 formed on the surface of the driving electrode 72, and a surface of the piezoelectric body 74. And a common drive electrode 76 formed on the substrate. A region facing the piezoelectric body 74 with the drive electrodes 72 and 76 functions as the piezoelectric element Pzt.

  The piezoelectric body 74 is formed by a process including heat treatment (firing), for example. Specifically, the piezoelectric material applied on the surface of the diaphragm 46 on which the plurality of drive electrodes 72 are formed is fired by heat treatment in a firing furnace and then shaped for each piezoelectric element Pzt (for example, using plasma). The piezoelectric body 74 is formed by milling.

A part of the drive electrode 72 is exposed from the sealing body 52 and the support body 54, and one end of the wiring substrate 34 is fixed to the exposed portion with an adhesive.
The wiring board 34 is obtained by patterning a plurality of wirings 344 on an insulating and flexible base film 342 such as polyimide, and a semiconductor chip (not shown) is mounted thereon. The IC module is configured with a semiconductor chip mounted on the wiring board 24.

Further, the drive electrode 72 is electrically connected to the wiring 344 of the wiring board 34, and by this connection, a drive signal Vout described later is individually applied to one end of the piezoelectric element Pzt.
On the other hand, although not shown in detail in FIG. 4, the drive electrode 76 is connected in common across the plurality of piezoelectric elements Pzt, and is routed from the sealing body 52 and the support body 54 to the exposed portion to be connected to the wiring board 34. Is electrically connected to another wiring 344. With this connection, a voltage VBS, which will be described later, is commonly applied to the other ends of the plurality of piezoelectric elements Pzt.

  In the piezoelectric element Pzt having such a configuration, in FIG. 4, the central portion of the piezoelectric element Pzt has a central portion with respect to the periphery in addition to the driving electrodes 72 and 76 and the diaphragm 46 according to the voltage applied by the driving electrodes 72 and 76. Bends upward or downward with respect to both end portions. Specifically, in this embodiment, when the applied voltage to the piezoelectric element Pzt (voltage of the drive signal Vout with respect to the voltage VBS) is low, the piezoelectric element Pzt bends upward, gradually becomes flat as the applied voltage increases, and further applied. When the voltage becomes high, it is configured to bend downward.

Here, if the ink is bent upward, the internal volume of the pressure chamber Sc is expanded, so that the ink is drawn from the liquid storage chamber Sr. On the other hand, if the ink is bent downward, the internal volume of the pressure chamber Sc is reduced. Depending on the degree of reduction, ink droplets are ejected from the nozzle N.
As described above, when an appropriate drive signal is applied to the piezoelectric element Pzt, ink is ejected from the nozzle N due to the displacement of the piezoelectric element Pzt.

FIG. 5 is a block diagram showing an electrical configuration of the inkjet printer 1.
As shown in this figure, the inkjet printer 1 has a configuration in which a head module 20 is connected to a control module 10 via an FFC 190.

The control module 10 includes a control unit 110, a plurality of driving units 120, and a constant voltage generation circuit 130.
The control unit 110 is a kind of microcomputer having a CPU, RAM, ROM, and the like, and executes predetermined programs to control each unit when image data to be printed is supplied from a host computer or the like. Various control signals are output.
The drive unit 120 is provided, for example, in one-to-one correspondence with the print head 30.
The constant voltage generation circuit 130 generates a constant voltage signal of the voltage VBS and supplies it to the head module 20 via the FFC 190.
Note that the control unit 110 also outputs a signal for controlling the transport mechanism 80 and the moving mechanism 90, but the configuration for the control is known and will be omitted.

In the inkjet printer 1, a plurality of sets of the drive unit 120 and the print head 30 are independently controlled in accordance with the main scanning of the carriage 18 by the moving mechanism 90 and the sub-scanning of the medium P by the transport mechanism 80.
Since a plurality of sets of operations do not differ except for the color of ink to be ejected and the ejection timing, the following description will be given focusing on the one set of drive unit 120 and print head 30 for convenience.

FIG. 6 is a block diagram showing a configuration for one set of the drive unit 120 and the print head 30.
Drive unit 120 includes drive circuits 122a and 122b.
Although described in detail later, the drive circuit 122a generates a drive signal Com-A based on the data dA supplied from the control unit 110, the signal Xflt-A, and the like. The data dA digitally defines the voltage of the drive signal Com-A having a trapezoidal waveform, and the signal Xflt-A becomes, for example, H level when the voltage of the drive signal Com-A is increased or decreased, and the drive signal Com− When the voltage of A is made constant in time (including a state that can be regarded as being almost constant), it becomes L level.
The drive circuit 122b generates a drive signal Com-B based on the data dB supplied from the control unit 110, the signal Xflt-B, and the like. The data dB digitally defines the voltage of the drive signal Com-B having a trapezoidal waveform, and the signal Xflt-B becomes, for example, H level when the voltage of the drive signal Com-B is raised or lowered, and the drive signal Com− It becomes L level when the voltage of B is made constant over time.

The drive signal Com-A generated by the drive circuit 122a, the drive signal Com-B generated by the drive circuit 122b, and the control signal Ctr supplied from the control unit 110 are supplied to the print head 30 via the FFC 190. Is done.
The drive signal Com-A supplied to the print head 30 via the FFC 190 is returned again from the node Na in the print head 30 to the drive circuit 122a via the FFC 190. As will be described later, the drive circuit 122a reflects the signal returned from the node Na and generates the drive signal Com-A.
Similarly, the drive signal Com-B supplied to the print head 30 through the FFC 190 is returned from the node Nb in the print head 30 to the drive circuit 122b through the FFC 190 again. The drive circuit 122b reflects the signal returned from the node Nb and generates a drive signal Com-B.

The control signal Ctr includes a print signal SI, signals LAT, CH, a clock signal, and the like.
Among these, the print signal SI is data defining the size of dots formed by ink ejection for each nozzle N. In the present embodiment, the size of dots is defined by four nozzles by one nozzle N, that is, four gradations of large dots, medium dots, small dots, and non-recording (no dots). For this reason, the print signal SI will be described assuming that gradation is performed with 2 bits for one of the nozzles N.
Signals LAT and CH are signals that define the control period and timing of printing in the print head 30.

The print head 30 includes an actuator module 40 and an IC module 50. The IC module 50 includes a selection control unit 510 and a selection unit 520 corresponding to the piezoelectric element Pzt on a one-to-one basis.
Among these, the selection control unit 510 controls selection in each of the selection units 520. Specifically, the selection control unit 510 temporarily accumulates the print signal SI supplied from the control unit 110 in synchronization with the clock signal by 2m that is the number of nozzles N (piezoelectric elements Pzt) in the print head 30. At the same time, the selection unit 520 is caused to select the drive signal Com-A or Com-B in accordance with the accumulated print signal SI for each print control period defined by the signals LAT and CH.

The selection unit 520 selects one of the drive signals Com-A and Com-B according to an instruction from the selection control unit 510 (or neither is selected), and selects the selected drive signal in the actuator module 40. It is applied to one end of the piezoelectric element Pzt (drive electrode 72, see FIG. 4). Note that the voltage of the drive signal selected by the selection unit 520 and applied to one end of the piezoelectric element Pzt is denoted as Vout.
In this way, the drive signals Com-A and Com-B are applied to one end of the piezoelectric element Pzt via the wiring and circuits in the FFC 190, the IC module 50, and the actuator module 40.
In the actuator module 40, one piezoelectric element Pzt is provided for each nozzle N as described above. The drive electrode 76 which is the other end of each piezoelectric element Pzt is connected in common, and the voltage VBS generated by the constant voltage generation circuit 130 is commonly applied to the other end.

In the present embodiment, with respect to one dot, the largest number of inks are ejected from one nozzle N twice, so that four gradations of large dots, medium dots, small dots, and non-printing are expressed. In order to express these four gradations, in this embodiment, two types of drive signals Com-A and Com-B are prepared, and one cycle of the drive signals Com-A and Com-B is a first half period, respectively. It is divided into the second half period. In one period, the driving signal Com-A or Com-B is selected (or not selected) according to the gradation to be expressed in the first half period and the second half period, and is applied to one end of the piezoelectric element Pzt. It is the composition which becomes.
Accordingly, the drive signals Com-A and Com-B will be described, and then the details of the drive circuit 122a (122b) that generates the drive signal Com-A (Com-B) will be described.

FIG. 10 is a diagram illustrating waveforms of the drive signals Com-A and Com-B. Note that the voltage of the drive signal Com-A (Com-B) actually generated by the drive circuit 122a (122b) oscillates as will be described later, so the waveform shown here is ideal.
As shown in FIG. 10, the drive signal Com-A includes a trapezoidal waveform Adp1 arranged in the control period T1 from the output of the signal LAT to the output of the signal CH in the print cycle Ta, and the print cycle. Of Ta, the trapezoidal waveform Adp2 arranged in the control period T2 from the output of the signal CH to the output of the next signal LAT is a repeated waveform.
The trapezoidal waveforms Adp1 and Adp2 are substantially identical to each other. If each is applied to the drive electrode 72 which is one end of the piezoelectric element Pzt, the trapezoidal waveforms Adp1 and Adp2 are moderate from the nozzle N corresponding to the piezoelectric element Pzt. This is a waveform for ejecting an amount of ink respectively.

The drive signal Com-B has a waveform in which a trapezoidal waveform Bdp1 arranged in the control period T1 and a trapezoidal waveform Bdp2 arranged in the control period T2 are repeated.
The trapezoidal waveforms Bdp1 and Bdp2 are different from each other. Among these, the trapezoidal waveform Bdp1 is a waveform for finely vibrating the ink near the nozzle N to prevent the ink viscosity from increasing. For this reason, even if the trapezoidal waveform Bdp1 is applied to one end of the piezoelectric element Pzt, ink droplets are not ejected from the nozzle N corresponding to the piezoelectric element Pzt. Further, if the trapezoidal waveform Bdp2 is applied to one end of the piezoelectric element Pzt, a small amount of ink smaller than the medium amount is ejected from the nozzle N corresponding to the piezoelectric element Pzt. It is a waveform.
The intermediate and small levels here are relative concepts and do not define the amount of ink as an absolute value.

The voltage at the start timing and the voltage at the end timing of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all common to the voltage Vcen. That is, each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 has a waveform that starts with the voltage Vcen and ends with the voltage Vcen.
For convenience, the maximum values of the voltages of the trapezoidal waveforms Adp1 and Adp2 are expressed as Vmax, and the minimum value of the voltages of the trapezoidal waveforms Adp1 and Adp2 are expressed as Vmin.

When formation of a large dot is specified for a certain nozzle N by the print signal SI, the selection control unit 520 selects the drive signal Com-A in the control periods T1 and T2, for example, in the selection unit 520 corresponding to the nozzle N. 510 controls. When the trapezoidal waveform Adp1 and the trapezoidal waveform Adp2 selected by this control are applied to one end of the piezoelectric element Pzt, a medium amount of ink is ejected in two from the nozzle N corresponding to the piezoelectric element Pzt. The For this reason, the inks land on the medium P and coalesce, and as a result, large dots as defined by the print signal SI are formed.
When medium dot formation is specified for a certain nozzle N by the print signal SI, the selection unit 520 corresponding to the nozzle N selects the drive signal Com-A in the control period T1, for example, the subsequent control period T2. The selection control unit 510 performs control so as to select the drive signal Com-B in FIG. When the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 selected by this control are applied to one end of the piezoelectric element Pzt, medium and small amounts of ink are divided twice from the nozzle N corresponding to the piezoelectric element Pzt. Discharged. Therefore, the respective inks land on the medium P and coalesce, and as a result, medium dots as defined by the print signal SI are formed.
When formation of small dots is specified for a certain nozzle N by the print signal SI, the selection unit 520 corresponding to the nozzle N selects, for example, either the drive signal Com-A or the drive signal Com-B in the control period T1. Instead, the selection control unit 510 controls to select the drive signal Com-B in the subsequent control period T2. When only the trapezoidal waveform Bdp2 selected by this control is applied to one end of the piezoelectric element Pzt, a small amount of ink is ejected only once from the nozzle N corresponding to the piezoelectric element Pzt. For this reason, as a result, small dots as defined by the print signal SI are formed on the medium P.
Note that when neither the drive signal Com-A nor the drive signal Com-B is selected, one end of the piezoelectric element Pzt is not electrically connected to any part, but the piezoelectric element Pzt has its own capacitance. Since the voltage (Vcen−VBS) is maintained depending on the sex, it is not indefinite.
When non-recording is specified for a certain nozzle N by the print signal SI, the selection unit 520 corresponding to the nozzle N drives in the subsequent control period T2 so as to select the drive signal Com-B in the control period T1, for example. The selection control unit 510 controls so that neither the signal Com-A nor the drive signal is selected. When only the trapezoidal waveform Bdp1 is applied to one end of the piezoelectric element Pzt by this control, the ink near the nozzle N only slightly vibrates and the ink is not ejected. As a result, as defined by the print data SI. Become unrecorded.
The control unit 110 outputs the signals Xflt-A and Xflt-B at the logic level as described above, as described above.

  Next, the drive circuits 122a and 122b have the same configuration except that the input signal and the output signal are different. Therefore, the drive circuit 122a will be described as a representative.

FIG. 7 is a diagram illustrating the configuration of the drive circuit 122a and the like. As shown in FIG. 7, the drive circuit 122a includes a DAC (Digital to Analog Converter) 1202, an amplification unit 200a, a constant potential circuit 202a, a switch control circuit 204a, a capacitor C31, and a resistance element R31.
The DAC 1202 converts the data dA supplied from the control unit 110 into an analog original drive signal Ca. When the signal FLsa is at the H level, the amplifying unit 200a switches and amplifies the voltage of the original drive signal Ca by, for example, 10 times, and outputs the drive signal Com-A from the node U1.

When the signal FLsa is at the L level, the constant potential circuit 202a linearly amplifies the voltage of the original drive signal Ca by 10 times and outputs it from the node U1 as the drive signal Com-A.
The node U1 is a common connection portion between the output end of the amplification unit 200a and the output end of the constant potential circuit 202a, and is connected to the node Na in the print head 30 via the wiring 192a of the FFC 190.

The node Na is a current detection point of the drive signal Com-A supplied to the print head 30 and is positioned before the input terminal of the selection unit 520 as viewed from the drive circuit 122a. The node Na is connected to one end of the capacitor C31 in the drive circuit 122a through the wiring 192b of the FFC 190. The other end of the capacitor C31 is connected to one end of the resistance element R31 and the input end of the switch control circuit 204a.
Therefore, the capacitor C31 and the resistor element R31 function as a differentiating circuit that differentiates the drive signal Com-A fed back from the node Na via the wiring 192b.
Note that a connection point between the other end of the capacitor C31 and one end of the resistor element R31 is denoted as a node N31, and a differential signal appearing at the node N31 is denoted as Fba.
In addition, a voltage Vcm serving as a reference for determining the differential signal is applied to the other end of the resistance element R31.

The switch control circuit 204a outputs a signal FLsa based on the signal Xflt-A and the signal Fba.
In the figure, of the wiring 192a from the node U1 to the node Na, the resistance component is R91 and the inductance component is L91. Similarly, in the wiring 192b from the node Na to one end of the capacitor C31, the resistance component is R92 and the inductance component is L92.

FIG. 8 is a diagram showing a detailed configuration of the drive circuit 122a.
The original drive signal Ca is supplied to the negative input terminal (−) of the comparator 1204. A signal obtained by stepping down the drive signal Com-A at the node U1 to 1/10 which is the inverse ratio of the voltage amplification factor by the resistance elements R1 and R2 is fed back to the positive input terminal (+) of the comparator 1204. That is, a signal obtained by stepping down the voltage of the drive signal Com-A output from the notebook U1 to 1/10 is fed back to the positive input terminal (+) of the comparator 1204 as a feedback signal.

The comparator 1204 outputs an H level signal Cmp when the voltage at the positive input terminal (+) is equal to or higher than the voltage at the negative input terminal (−), and the voltage at the positive input terminal (+) is the negative input terminal (−). ), An L level signal Cmp is output.
Although details will be described later, the control signal generation circuit 126 controls the gate signal (first control signal) Gp for controlling the switching operation of the transistor 231 and the switching operation of the transistor 232 if the signal FLsa is at the H level. A gate signal (second control signal) Gn is generated based on the signal Cmp. If the signal FLsa is at L level, the control signal generation circuit 126 sets the gate signal Gp to H level and the gate signal Gn to L level regardless of the signal Cmp.

A transistor pair is configured by the transistor (first transistor) 231 and the transistor (second transistor) 232. Among them, the high-side transistor 231 is, for example, a field-effect transistor of P-channel type, high-side voltage V _D of the power source terminal is applied, the gate signal Gp is supplied to the gate terminal. The low-side transistor 232 is, for example, an N-channel field effect transistor. A gate signal Gn is supplied to a gate terminal, and a source terminal is grounded to a ground Gnd that is on the lower side of the power source.
The drain terminals of the transistors 231 and 232 are connected to the node U1, and the drive signal Com-A is output from the node U1.

Since the highest voltage of the drive signal Com-A is a degree for example 40V (volts), the high side voltage _{V D} of the power source of the transistor pair is for example, about 42V.
Therefore, the power of the comparator 1204 and the control signal generating circuit 126 in FIG. 7, although not particularly shown, the high side is a voltage V _D.
Further, as described above, the drive circuit 122a is configured to amplify the original drive signal Ca by 10 times and output it as the drive signal Com-A, so that the voltage range of the original drive signal Ca is 0 to 4.2V. Degree.

The constant potential circuit 202a includes a linear amplifier 222 and a switch 293.
In the present embodiment, the linear amplifier 222 amplifies the voltage of the signal Ca by 10 times the same as the amplification unit 200a and outputs the amplified signal.
The linear amplifier 222 is preferably a linear amplifier (class A, class AB) or a linear amplifier such as an operational amplifier, instead of switching amplification of a transistor as in the amplification unit 200a.
The switch 293 is turned on when the signal FLsa is at the L level between the output terminal of the linear amplifier 222 and the node U1, and turned off when the signal FLsa is at the H level.

  The switch control circuit 204a includes reference power supplies E11 and E12, resistance elements R11, R12, R21, and R22, operational amplifiers 241 and 242, NOT circuits 242 and 261, a NOR circuit 263, and a D flip-flop (hereinafter “ 265) (abbreviated as “DFF”).

Reference power source E11 outputs a voltage V ₁₁ between the positive and negative terminals. In the reference power supply E11, the voltage Vcm is applied to the negative terminal, and the positive terminal is connected to the positive input terminal (+) of the operational amplifier 241 via the resistance element R11. The voltage Vcm is, for example, 1.5V.
On the other hand, the signal Fba is input to the negative input terminal (−) of the operational amplifier 241. The output terminal of the operational amplifier 241 is positively fed back to the positive input terminal (+) of the operational amplifier 241 through the resistance element R12.
Therefore, the operational amplifier 241 functions as a hysteresis comparator that compares the voltage of the signal Fba with the voltage (Vcm + V ₁₁ ). Specifically, a voltage obtained by dividing the output voltage of the operational amplifier 241 by the resistance elements R11 and R12 has a hysteresis width, and the voltage of the signal Fba becomes higher or lower than the voltage (Vcm + V ₁₁ ) by the hysteresis width. The output voltage of the operational amplifier 241 is inverted.
However, to simplify the description here, the operational amplifier 241 outputs an L level when the voltage of the signal Fba becomes equal to or higher than the voltage (Vcm + V ₁₁ ), and the signal Fba becomes lower than the voltage (Vcm + V ₁₁ ). H level is output when
The output terminal of the operational amplifier 241 is connected to the input terminal of the NOT circuit 242, and the output terminal of the NOT circuit 242 is connected to one of the two input terminals of the NOR circuit 263.

Reference power source E12 outputs a voltage V ₁₂ between the positive and negative terminals. In the reference power supply E12, the voltage Vcm is applied to the positive terminal, and the negative terminal is connected to the positive input terminal (+) of the operational amplifier 251 via the resistance element R21.
On the other hand, the signal Fba is input to the negative input terminal (−) of the operational amplifier 251. The output terminal of the operational amplifier 251 is positively fed back to the positive input terminal (+) of the operational amplifier 251 through the resistance element R22.
Therefore, the output voltage of the operational amplifier 251 functions as a hysteresis comparator that is inverted when the voltage of the signal Fba becomes higher or lower than the voltage (Vcm−V ₁₂ ) by the hysteresis width.
However, in order to simplify the description here, the operational amplifier 251 outputs an L level when the voltage of the signal Fba becomes equal to or higher than the voltage (Vcm−V ₁₂ ), and the signal Fba has the voltage (Vcm−V _12). H level is output when the value becomes less than.
The output terminal of the operational amplifier 251 is connected to the other of the two input terminals of the NOR circuit 263.

The output terminal of the NOR circuit 263 is connected to the clock input terminal Clk of the DFF 265.
A signal Xflt-A is supplied to the input terminal of the NOT circuit 261, and the output terminal of the NOT circuit 261 is connected to the negative logic reset input terminal R in the DFF 265. An H level is supplied to the input terminal D and the negative logic set input terminal S of the DFF 265. The signal FLsa is output from the inverted output terminal / Q of the DFF 265. Note that the signal FLsa is as described above in terms of controlling on / off of the switch 293 in the constant potential circuit 202a.

When the signal input to the clock input terminal Clk rises to H level, the DFF 265 outputs an inverted signal of the level of the input terminal D from the output terminal / Q, while the set input terminal S is at H level, When the reset input terminal R becomes L level, the signal output from the output terminal / Q is set to H level.
Therefore, the DFF 265 sets the signal FLsa output from the output terminal / Q to the H level when the signal Xflt-A changes to the H level, turns off the switch 293, and thereafter the NOR circuit 263. The signal FLsa is inverted to L level and the switch 293 is turned on when the negative logical sum signal output from H rises to H level.

Here, the case where the NOR signal by the NOR circuit 263 is at the H level is when the output signal of the NOT circuit 242 is at the L level (that is, when the output signal of the operational amplifier 241 is at the H level). In addition, the output signal of the operational amplifier 251 is at the L level. The case where the output signal of the former operational amplifier 241 is at the H level is when the voltage of the signal Fba is less than the voltage (Vcm + V ₁₁ ) as described above, and the case where the output signal of the latter operational amplifier 251 is at the L level. Is the case where the voltage of the signal Fba is equal to or higher than the voltage (Vcm−V ₁₂ ) as described above.
On the other hand, the signal Fba is a differential signal in which the direct current component of the drive signal Com-A is cut by the capacitor C31 and biased to the voltage Vcm via the resistance element R31.
Therefore, the case where the NOR signal of the NOR circuit 263 changes from the L level to the H level means that the signal Fba is changed to the voltage after the drive signal Com-A is changed from the increase or decrease period to the constant period. This means a case where it is less than (Vcm + V ₁₁ ) and within a range of voltage (Vcm−V ₁₂ ) or more.

  The drive circuit 122b is the same as the drive circuit 122a except for a supplied signal and an output signal. Specifically, the drive circuit 122b converts the data dB supplied from the control unit 110 into an analog original drive signal Cb by the DAC 1202, amplifies the original drive signal Cb by 10 times, and outputs it as a drive signal Com-B. It is the composition to do.

FIG. 9 is a diagram illustrating an example of the control signal generation circuit 126 in the drive circuit 122a. As shown in FIG. 8, the control signal generation circuit 126 includes two buffer circuits B1 and B2 and a switch Sw1. Among these, the switch Sw1 has two poles of double throw switches having input terminals a and b and a common connection terminal c.
The buffer circuit B1 reinverts the inverter (NOT circuit) 1261 that inverts the signal Cmp from the comparator 1204 and the inverted signal from the inverter 1261, and supplies it to one input terminal a of the two poles in the switch Sw1. And an inverter 1262.
The buffer circuit B2 includes an inverter 1263 that inverts the signal Cmp, and an inverter 1264 that reinverts the inverted signal from the inverter 1263 and supplies it to the other input terminal a of the two poles of the switch Sw1.
As described above, each of the buffer circuits B1 and B2 performs an operation (buffering) for outputting a logic signal having the same level as the input signal Cmp.

In each of the two poles of the switch Sw1, if the signal FLsa is at the H level, the input terminal a and the common connection terminal c are connected as shown in FIG. 9, and if the signal FLsa is at the L level, the input terminal b and The common connection end c is connected. In addition, in one of the two poles of the switch Sw1, the input terminal b is supplied with the H level, and the common connection terminal c is connected to the gate terminal of the transistor 231. On the other of the two poles of the switch Sw 1, the L level is supplied to the input terminal c, and the common connection terminal c is connected to the gate terminal of the transistor 232.
Therefore, in the control signal generation circuit 126, if the signal FLsa is at the H level, the signal obtained by buffering the signal Cmp by the buffer circuit B1 is output as the gate signal Gp, and the signal obtained by buffering the signal Cmp by the buffer circuit B2 is the gate. Output as signal Gn.
On the other hand, in the control signal generation circuit 126, if the signal FLsa is at the L level, the H level is output as the gate signal Gp and the L level is output as the gate signal Gn regardless of the signal Cmp.

  In the present embodiment, the buffer circuits B1 and B2 have different reference voltages (threshold values) for switching to the same logic level with respect to the voltage change of the signal Cmp.

FIG. 11 is a diagram showing how the levels of the gate signals Gp and Gn as a result of buffering change with respect to the voltage change of the signal Cmp when the signal FLsa is at the H level. In FIG. 10, the horizontal axis represents time.
In FIG. 10, B1_th is a threshold value in the buffer circuit B1, and B2_th is a threshold value in the buffer circuit B2.
In the present embodiment, the height relationship of each threshold is set as follows.
B2_th <B1_th

Thus the threshold is set, when the signal FLsa is H level, when the signal Cmp is gradually falling from the voltage V _D corresponding to the H level to the ground Gnd corresponding to the L level (zero voltage) The gate signal Gn changes from the H level to the L level before the gate signal Gp. Conversely, when the signal Cmp gradually rises from the voltage zero corresponding to the L level to the voltage V _D corresponding to the H level, the gate signal Gp changes from the L level to the H level before the gate signal Gn.

The transistor 231 is turned on when the gate signal Gp is L level, and the transistor 232 is turned on when the gate signal Gn is H level.
Therefore, when the signal Cmp gradually falls from the H level to the L level, the gate signal Gp becomes the L level and the transistor 231 is turned on after the gate signal Gn becomes the L level and the transistor 232 is turned off. . On the other hand, when the signal Cmp gradually rises from the L level to the H level, after the gate signal Gp becomes the H level and the transistor 231 is turned off, the gate signal Gn becomes the H level and the transistor 232 is turned on. .

For this reason, in this embodiment, when the voltage of the signal Cmp changes, after one of the transistors 231 or 232 is switched from on to off, the other is switched from off to on, and the transistors 231 and 232 are simultaneously switched. Never turn on.
In other words, when the logic level of the signal Cmp changes, there exists a state where both the transistors 231 and 232 are turned off. In a state where both the transistors 231 and 232 are turned off, it means that the voltage at the node U1 (voltage of the drive signal Com-A) is not controlled in the upward or downward direction. For this reason, the voltage range of the signal Cmp in which both the transistors 231 and 232 are turned off will be referred to as a dead band (or dead band) in the sense that the voltage of the drive signal Com-A is not controlled.
In the present embodiment, since the transistors 231 and 232 are not turned on at the same time, it is possible to prevent a through current from flowing.

  FIG. 10 is a diagram showing how the levels of the gate signals Gp and Gn change with respect to the voltage change of the signal Cmp with the horizontal axis as time. In this embodiment, the signal Cmp is actually Does not mean changing as shown in the figure.

FIG. 12 is a diagram showing voltage waveforms at various portions for explaining the operation of the drive circuit 122a.
As described above, since the drive signal Com-A (original drive signal Ca) is a waveform in which two identical trapezoidal waveforms Adp1 and Adp2 are repeated in the printing cycle Ta, the drive signal Com-A will be described as a representative of the trapezoidal waveform Adp1. To do. Further, since the drive signal Com-A has a relationship obtained by amplifying the voltage of the original drive signal Ca by 10 times, the voltages Vcen, Vmax, Vmin of the drive signal Com-A are the voltages Vcen / V in the original drive signal Ca, respectively. 10, Vmax / 10, and Vmin / 10.

  In FIG. 12, a period K1 is a period during which the original drive signal Ca falls from the voltage Vcen / 10 to the voltage Vmin / 10. A period K2 following the period K1 is constant at the voltage Vmin / 10. The period K3 following the period K2 is a period during which the original drive signal Ca rises from the voltage Vmin / 10 to the voltage Vmax / 10. The period K4 following the period K3 is a period during which the original drive signal Ca is constant at the voltage Vmax / 10, and the period K5 following the period K4 is when the original drive signal Ca is changed from the voltage Vmax / 10 to the voltage Vcen /. A period K6 following the period K5 is a period in which the original drive signal Ca is constant at the voltage Vcen / 10.

First, the period K1 is a voltage drop period of the original drive signal Ca.
In the period K1, since the signal Xflt-A is at the H level, the signal FLsa is set to the H level. Therefore, the gate signals Gp and Gn are signals obtained by buffering the signal Cmp with the buffer circuits B1 and B2, and the switch 293 (see FIG. 8) is turned off. Therefore, the drive signal Com-A The signal is amplified by the amplifier 200a.

Here, it is assumed that the voltage obtained by dividing the voltage of the drive signal Com-A by 1/10, that is, the voltage of the feedback signal is lower than the voltage of the original drive signal Ca. Under this assumption, since the signal Cmp is at the L level, both the gate signals Gp and Gn are at the L level. Therefore, since the transistor 231 is turned on and the transistor 232 is turned off, control for increasing the voltage of the drive signal Com-A is executed.
As a result of the control for increasing the voltage of the drive signal Com-A, the signal Cmp rises from the L level to the H level in the process in which the voltage of the feedback signal becomes higher than the voltage of the original drive signal Ca. In this rising process, as described above, after the gate signal Gp becomes H level and the transistor 231 is turned off, the gate signal Gn becomes H level and the transistor 232 is turned on, so this time, the drive signal Com-A Control for lowering the voltage of is performed.
In the process in which the voltage of the feedback signal becomes lower than the voltage of the original drive signal Ca as a result of the control to lower the voltage of the drive signal Com-A, the signal Cmp drops from the H level to the L level. In the descending process, as described above, after the gate signal Gn becomes L level and the transistor 232 is turned off, the gate signal Gp becomes L level and the transistor 231 is turned on. Control for increasing the voltage is executed.
After all, in the period K1, the transistors 231 and 232 are alternately turned on, so that the voltage of the feedback signal is controlled to follow the voltage drop of the original drive signal Ca. As a result of such control, in the period K1, the voltage of the drive signal Com-A falls while oscillating with respect to the target voltage 10 times the original drive signal Ca.

  In the period K1, the voltage of the drive signal Com-A oscillates when viewed microscopically, but decreases at a substantially constant rate when viewed macroscopically, so that the signal Fba is negative with respect to the voltage Vcm. Will swing to the side. In the period K1, since the switch 239 is off, the output of the linear amplifier 222 does not affect the drive signal Com-A at the node U1.

The period K2 is a period in which the original drive signal Ca is constant at the voltage Vmin / 10.
In the period K2, the signal Xflt-A is at the L level, but the signal FLsa is maintained at the H level at the start timing of the period K2. For this reason, in the period K2, initially, the transistors 231 and 232 are alternately turned on so as to follow the voltage of the original drive signal Ca.
Here, in the period K2, the voltage of the drive signal Com-A oscillates when viewed microscopically, but is substantially constant when viewed macroscopically, and therefore the signal Fba goes to the voltage Vcm. At this time, when the signal Fba is less than the voltage (Vcm + V ₁₁ ) and within the voltage (Vcm−V ₁₂ ) or more, the signal FLsa output from the output terminal / Q of the DFF 265 falls to the L level. . As a result, the switch 293 is turned on, so that the linear amplifier 222 outputs a signal having a voltage Vmin obtained by amplifying the voltage Vmin / 10 of the original drive signal Ca ten times.
On the other hand, when the signal FLsa becomes L level, the gate signal Gp becomes H level and the gate signal Gn becomes L level, so that both the transistors 231 and 232 are turned off.
Therefore, the drive signal Com-A output from the node U1 is an output signal from the linear amplifier 222.

Next, the period K3 is a voltage rise period of the original drive signal Ca.
In the period K3, since the signal Xflt-A is at the L level, the signal FLsa is set to the H level. Therefore, the gate signals Gp and Gn are signals obtained by buffering the signal Cmp, and the switch 293 is turned off. Therefore, the drive signal Com-A is a signal obtained by voltage amplification of the original drive signal Ca by the amplifying unit 200a.

Here, when the voltage of the feedback signal is lower than the voltage of the original drive signal Ca, the signal Cmp is at the L level, and thus the gate signals Gp and Gn are both at the L level. Therefore, since the transistor 231 is turned on and the transistor 232 is turned off, control for increasing the voltage of the drive signal Com-A is executed.
As a result of the control for increasing the voltage of the drive signal Com-A, the signal Cmp rises from the level to the H level in the process in which the voltage of the feedback signal becomes higher than the voltage of the original drive signal Ca. In this increasing process, after the gate signal Gp becomes H level and the transistor 231 is turned off, the gate signal Gn becomes H level and the transistor 232 is turned on, so this time the voltage of the drive signal Com-A is lowered. Control is executed.
In the process in which the voltage of the feedback signal becomes lower than the voltage of the original drive signal Ca as a result of the control to lower the voltage of the drive signal Com-A, the signal Cmp drops from the H level to the L level. In this descending process, after the gate signal Gn becomes L level and the transistor 232 is turned off, the gate signal Gp becomes L level and the transistor 231 is turned on, so that the voltage of the drive signal Com-A is increased again. Is executed.
Eventually, in the period K3, the transistors 231 and 232 are alternately turned on, whereby the voltage of the feedback signal is controlled to follow the voltage increase of the original drive signal Ca. As a result of such control, in the period K3, the voltage of the drive signal Com-A rises while oscillating with respect to the target voltage.

  In the period K3, the voltage of the drive signal Com-A oscillates when viewed microscopically, but increases at a substantially constant rate when viewed macroscopically, so that the signal Fba is positive with respect to the voltage Vcm. Will swing to the side. In the period K3, since the switch 239 is off, the output of the linear amplifier 222 does not affect the drive signal Com-A at the node U1.

The period K4 is a period in which the original drive signal Ca is constant at the voltage Vmax / 10, and therefore there is no difference from the operation of the period K2 except for the voltage of the original drive signal Ca. Specifically, in the period K4, initially, the transistors 231 and 232 are alternately turned on to control the voltage Vmax of the original drive signal Ca.
In the period K4, since the voltage of the drive signal Com-A is substantially constant when viewed macroscopically, the signal Fba goes to the voltage Vcm. At this time, when the signal Fba is less than the voltage (Vcm + V ₁₁ ) and falls within the range of the voltage (Vcm−V ₁₂ ) or more, the signal FLsa falls to the L level. As a result, the switch 293 is turned on, so that the linear amplifier 222 outputs a signal having a voltage Vmax obtained by amplifying the voltage Vmax / 10 of the original drive signal Ca ten times. On the other hand, when the signal FLsa becomes L level, both the transistors 231 and 232 are turned off.
Therefore, the drive signal Com-A output from the node U1 is an output signal from the linear amplifier 222.

Since the period K5 is the voltage drop period of the original drive signal Ca, the operation is the same as that of the period K1. That is, in the period K5, the voltage of the drive signal Com-A decreases while oscillating with respect to the target voltage due to the transistors 231 and 232 being alternately turned on.
The period K6 is a period in which the original drive signal Ca is constant at the voltage Vcen / 10, and therefore, the operation of the periods K2 and K4 is not different from the voltage of the original drive signal Ca. That is, in the period K <b> 6, the drive signal Com-A becomes the voltage Vcen output from the linear amplifier 222.

As described above, in the present embodiment, in the periods K1, K3, and K5 in which the voltage of the drive signal Com-A is changed among the periods K1 to K6, the transistors 231 and 232 are alternately turned on, whereby the target voltage is increased. The voltage of the drive signal Com-A is controlled while vibrating.
In addition, in the periods K2, K4, and K6 in which the voltage of the drive signal Com-A is constant among the periods K1 to K6, the signal obtained by amplifying the voltage of the original drive signal Ca 10 times by the linear amplifier 222 is the drive signal Com. Output as -A.
Here, before describing the effect of the present embodiment, a conventional drive circuit will be described.

FIG. 19 is a diagram showing a configuration of a conventional drive circuit described in Patent Document 3, and FIG. 20 is a diagram for explaining an operation in the drive circuit.
The drive circuit shown in FIG. 19 is different from the drive circuit 122a shown in FIG. 8 mainly in that it does not have the constant potential circuit 202a and the switch control circuit 204a, and in a portion corresponding to the amplification unit 200a. The comparator 1204 in FIG. 8 is replaced with a differential amplifier 271 and the control signal generation circuit 126 is replaced with a selector 273 and the signal OCa is supplied. For convenience, the gate signal to the transistor 231 is renamed Gt1, and the gate signal to the transistor 232 is renamed Gt2.
In FIG. 19, only one drive circuit is shown in a simplified manner for comparison. In addition, the drive circuit shown in FIG. 19 does not include the resistance elements R1 and R2, but if the signal CA is multiplied by 10 in the DAC and is supplied to the negative input terminal (−) of the differential amplifier 271. Good.

The differential amplifier 271 outputs a signal Op corresponding to the voltage difference of the signal CA with respect to the feedback signal (driving signal Com) from the node U1 supplied to the positive input terminal (+). That is, the differential amplifier 271 is not a comparator that outputs a comparison result, but an operational amplifier that outputs a signal corresponding to the voltage difference.
As shown in FIG. 20, the signal OCa is at the L level during the period in which the voltage of the signal CA rises and during the period in which the signal CA is constant at a voltage equal to or higher than the voltage Vth, and is at the H level in other periods.
The voltage Vth, the resistance element Ra, roughly equal to the divided voltage of the power supply voltage _{V D} determined by Rb.
If the signal OCa is at the L level, the selector 273 selects the output signal of the differential amplifier 271 as the gate signal Gt1, supplies it to the gate terminal of the transistor 231, and selects the L level as the gate signal Gt2. Is supplied to the gate terminal. On the other hand, if the signal OCa is at the H level, the selector 273 selects the H level as the gate signal Gt1, supplies it to the gate terminal of the transistor 231, and selects the output signal of the differential amplifier 271 as the gate signal Gt2. This is supplied to the gate terminal of the transistor 232.

Since the signal OCa is at the L level during the voltage increase period of the signal CA, the selector 273 selects the L level as the gate signal Gt2, so that the transistor 232 is turned off. Further, in the voltage rising period of the signal CA, the selector 273 selects the signal Op as the gate signal Gt1.
In the voltage rise period of the signal CA, the voltage of the signal CA rises ahead of the voltage at the node U1, so that the voltage of the output signal of the differential amplifier 271 selected as the gate signal Gt1 depends on the difference voltage between them. It becomes low and swings to almost L level. When the gate signal Gt1 becomes L level, the transistor 231 is turned on, so that the voltage at the node U1 rises. Note that the voltage at the node U1 does not actually rise to the voltage V _D at a stretch, but rises slowly due to the capacitive element Pzt or the like.
When the voltage of the node U1 becomes equal to or higher than the voltage of the signal CA, the gate signal Gt2 becomes H level and the transistor 231 is turned off. When the transistor 231 is turned off, the voltage increase at the node U1 is stopped, but since the voltage of the signal CA is increased, the voltage of the node U1 becomes lower than the voltage of the signal CA again. For this reason, the gate signal Gt1 becomes L level, and the transistor 231 is turned on again.
For this reason, in the voltage rising period of the signal CA, the transistor 231 is repeatedly turned on / off with the transistor 232 being turned off, that is, a switching operation is performed. By this switching operation, the control of causing the voltage of the node U1, that is, the voltage of the drive signal Com to follow the increase of the voltage of the signal CA is executed.
Note that the transistor 231 may perform a linear operation instead of a switching operation depending on conditions.

Since the signal OCa is at the H level during the voltage fall period of the signal CA, the selector 273 selects the H level as the gate signal Gt1, and as a result, the transistor 231 is turned off. Further, in the voltage falling period of the signal CA, the selector 273 selects the signal Op as the gate signal Gt1.
Therefore, in the voltage falling period of the signal CA, contrary to the voltage increasing period, the transistor 232 is repeatedly turned on / off with the transistor 231 turned off, that is, performs a switching operation. By this switching operation, control for causing the voltage of the drive signal Com to follow the decrease in the voltage of the signal CA is executed.
Note that the transistor 232 may perform a linear operation instead of a switching operation depending on conditions.

If the signal CA is less than the threshold value Vth in FIG. 20 and is in a certain period, the signal OCa is at the H level, so the selector 273 selects the H level as the gate signal Gt1 and the signal Op as the gate signal Gt2.
During this period, if the voltage of the node U is higher than the voltage of the signal CA, the output voltage of the differential amplifier 271 also increases, so that the voltage of the gate signal Gt2, that is, the resistance between the source and drain of the transistor 232 decreases. , To lower the voltage at the node U1. On the other hand, if the voltage of the node is lower than the voltage of the signal CA, the voltage of the gate signal Gt2 is also lowered, so that the resistance between the source and drain of the transistor 232 increases, and the voltage of the node U1 approaches the voltage Vth. Work in the direction to raise. That is, the transistor 232 performs a linear operation.
Therefore, during this period, control is performed such that the direction in which the voltage at the node U1 is lowered and the direction in which the voltage is raised are balanced, specifically, control is performed so that the voltage Vmin or Vcen of the signal CA is constant.

If the signal CA is equal to or higher than the threshold value Vth in FIG. 20 and is in a certain period, the signal OCa is at L level, so the selector 273 selects the signal Op as the gate signal Gt1 and selects the L level as the gate signal Gt2.
In this period, if the voltage of the node U is higher than the voltage of the signal CA, the voltage of the gate signal Gt1 is also increased. Therefore, the resistance between the source and drain of the transistor 231 is reduced, and the voltage of the node U1 is changed to the voltage Vth. It works in the direction of descending so as to approach.
On the other hand, if the voltage of the node is lower than the voltage of the signal CA, the voltage of the gate signal Gt1 is also lowered, so that the resistance between the source and drain of the transistor 231 is increased and works to increase the voltage of the node U. That is, the transistor 231 performs a linear operation.
Therefore, even during this period, control is performed so that the voltage Vmax of the signal CA becomes constant.

However, it has been pointed out that in the conventional drive circuit, when the load is large, the waveform accuracy of the drive signal Com is lowered, which adversely affects ink ejection. In particular, in recent years, there has been an increasing demand for high-speed printing and high-definition printing, and it is necessary to greatly increase the number of nozzles in order to meet the demand. As a result, the number of piezoelectric elements that are driven simultaneously is also greatly increased. Will increase. When the number of driven piezoelectric elements Pzt is large, the current I flowing between the drive circuit and the piezoelectric element group for the drive circuit increases significantly.
Further, in the LFP that can print on the medium-sized medium P, the FFC 190 becomes longer. For this reason, the parasitic inductance L of the FFC 190 and the substrate wiring is increased.

In a situation where the current I increases and the parasitic inductance L of the substrate wiring is large, the drive signal Com for driving the piezoelectric element is proportional to the product of the parasitic inductance L and the rate of change of the current I (L × dI / dt). A large amount of noise is superimposed and a large ripple is generated.
Specifically, in the conventional drive circuit, immediately after the transistor 231 changes from on to off during the voltage rise period of the original drive signal CA, the current I does not immediately become zero due to the influence of the parasitic inductance L, and Immediately after the transistor 231 changes from off to on, the current I does not begin to flow instantaneously due to the influence of the parasitic inductance L.
For this reason, during the voltage increase period of the original drive signal CA, the current of the drive signal does not immediately reflect the on / off with respect to the on / off of the transistor 231. The same applies to the voltage drop period of the original drive signal CA, and the voltage of the drive signal does not immediately reflect the on / off state with respect to the on / off state of the transistor 232.
As described above, in the conventional drive circuit, the current of the drive signal Com does not flow in the on / off state of the transistor 231 or 232, and as a result, the drive signal Com has a large ripple.

In the conventional driving circuit, the transistor 231 or 232 performs a linear operation instead of an on / off switching operation in a certain period of the voltage of the original driving signal CA. For this reason, an error is likely to occur immediately after the original drive signal CA shifts from the voltage change period to the constant voltage period.
Specifically, when the voltage rises from the voltage increase period of the original drive signal CA to the constant voltage period, the voltage of the drive signal Com is accompanied by an error ΔV1 as shown in FIG. 21, and the original drive signal CA falls. When the period changes from a period to a certain period, the voltage of the drive signal Com is accompanied by an error ΔV2 as shown in FIG.

  For this reason, in the conventional drive circuit, when the number of piezoelectric elements driven simultaneously is large, or when the FFC 190 is lengthened, the waveform accuracy of the drive signal Com is lowered, which adversely affects ink ejection. Become.

On the other hand, in the present embodiment, the transistors 231 and 232 are alternately turned on during the voltage change period of the original drive signal Ca.
Specifically, also in the drive circuit 122a of this embodiment, if the parasitic inductance L is large, the current I does not immediately become zero immediately after the transistor 231 (232) changes from on to off. However, after the transistor 231 (232) is turned off, the transistor 232 (231) is turned on and tends to flow in the opposite direction, so that the current I can be quickly reduced.
Therefore, in this embodiment, the voltage of the drive signal Com-A follows the voltage of the original drive signal Ca 10 times with high accuracy, so that the number of piezoelectric elements that are driven simultaneously is large, or the FFC 190 is lengthened. Even in this case, the waveform accuracy of the drive signal Com-A can be kept high. Therefore, in the present embodiment, ink can be ejected with high accuracy.

Further, in the drive circuit 122a, in the periods K2, K4, and K6 in which the voltage of the original drive signal Ca does not change, the transistors 231 and 232 are not alternately turned on, but the signal obtained by voltage amplification of the original drive signal Ca by the linear amplifier 222 is used as the drive signal. Com-A is output.
For this reason, in this embodiment, the error with respect to the target voltage (10 times the voltage of the original drive signal Ca) can be reduced for the drive signal Com-A in the constant voltage period of the original drive signal Ca.

In the drive circuit 122a, when the voltage of the drive signal Com-A changes from rising or falling to a constant value, the switch 293 is not immediately turned on, but the signal Fba is less than the voltage (Vcm + V ₁₁ ) and the voltage ( It is configured to turn on when it falls within the range of Vcm−V ₁₂ ).
Hereinafter, the reason for adopting such a configuration will be described.

  As described above, the resistance component R91 and the inductance component L91 are parasitic on the wiring 192a from the node U1 to the node Na in the drive circuit 122a. Among these components, the inductance component L91 acts in a direction that delays the current waveform of the drive signal Com-A with respect to the voltage waveform, so that a relatively large current still flows immediately after the transistors 231 and 232 are both turned off. There may be. In such a case, if the switch 293 is turned on, spike noise may be superimposed on the drive signal Com-A, which may deteriorate the liquid ejection accuracy.

  Note that the spike noise can be overcome by increasing the driving capability of the linear amplifier 222. However, the original purpose of the linear amplifier 222 is to provide a capacitive load such as the piezoelectric element Pzt even when both the transistors 231 and 232 are turned off when the voltage of the drive signal Com-A is kept constant. It is to supply voltage. For this reason, increasing the driving capability of the linear amplifier 222 not only deviates from the original purpose but also causes enlargement of the circuit itself and deterioration of power consumption.

Therefore, the switch 293 is turned on after the voltage of the drive signal Com-A changes from rising or falling to a constant value and the current flowing through the node Na becomes equal to or less than the threshold value. However, since the drive signal Com-A swings at a maximum voltage of about 40 V, the configuration for directly detecting the current flowing through the node Na causes an increase in size and complexity, and generally there is a strong demand for downsizing. It is difficult to adopt for a liquid ejection device.
For this reason, in the drive circuit 122a of the present embodiment, focusing on the fact that the magnitude of the current flowing through the node Na reflects the degree of waveform dullness when the drive signal Com-A is differentiated, the dullness of the waveform is reduced. When the current falls within a predetermined level, it is determined that the current flowing through the node Na is equal to or less than a threshold value.
Specifically, in the drive circuit 122a, the drive signal Com-A at the node Na is fed back via the wiring 192b of the FFC 190, and differentiated with respect to the voltage Vcm by the capacitor C31 and the resistor element R31, and the differentiated waveform is obtained. When the voltage falls within a predetermined range with respect to the reference voltage Vcm, it is determined that the current flowing through the node Na is as follows, and the signal FLsa is set to L level to turn on the switch 293.
In this manner, in the drive circuit 122a, when the current flowing through the node Na becomes equal to or less than the threshold value, the signal FLsa is set to L level to turn on the switch 293, so that spike noise is superimposed on the drive signal Com-A as described above. Therefore, the liquid discharge accuracy can be kept good.
Note that, if downsizing or the like is not required, a configuration in which the current flowing through the node Na is directly detected may be used.

For convenience of explanation, as shown in FIG. 12, the waveform portion of the drive signal Com-A in the period K3 during which the voltage of the original drive signal Ca rises is defined as the first region. Since the voltage of the drive signal Com-A oscillates with respect to the target voltage as described above, the first region can be rephrased as a region where the oscillation center value of the voltage in the drive signal Com-A increases.
Further, the waveform portion of the drive signal Com-A in the period K1 during which the voltage of the original drive signal Ca falls is defined as the second region. In other words, the second region is a region in which the oscillation center value of the voltage in the drive signal Com-A decreases.
Of the waveform portion of the drive signal Com-A, the drive signal Com when the voltage of the original drive signal Ca is constant after the second region is defined as the third region between the first region and the second region. The waveform portion of −A is set as the fourth region.
Note that the waveform portion of the drive signal Com-A is in the order of the second region, the third region, the first region, and the fourth region in time series.

  13 and 14 are enlarged views of part of the waveform of the drive signal Com-A in FIG. Specifically, FIG. 13 is an enlarged view of a portion of the waveform portion of the drive signal Com-A that changes from the first region to the fourth region, and FIG. 14 illustrates a portion of the waveform portion of the drive signal Com-A. FIG. 5 is an enlarged view of a portion that changes from a second region to a fourth region.

As shown in FIG. 13, in the first region, the transistors 231 and 232 are alternately turned on so that the voltage of the drive signal Com-A is 10 times the voltage of the original drive signal Ca (denoted as “10Ca”). It rises while vibrating against.
Here, even immediately after the original drive signal Ca changes to a constant voltage and the signal Xflt-A becomes L level, the transistors 231 and 232 are alternately turned on, so the voltage of the drive signal Com-A is kept at a constant target. Vibrates against voltage. In this oscillation process, when the signal Fba falls below the voltage (Vcm + V ₁₁ ) and falls within the voltage (Vcm−V ₁₂ ) or more at the timing ts1, for example, the signal FLsa falls to the L level. While the switch 293 is turned on, the transistors 231 and 232 are both turned off. For this reason, the voltage of the drive signal Com-A is a signal obtained by multiplying the original drive signal Ca by 10 times by the linear amplifier 222, and therefore substantially matches the target voltage.

As shown in FIG. 14, in the second region, the voltage of the drive signal Com-A drops while oscillating with respect to the target signal due to the transistors 231 and 232 being alternately turned on.
Here, even immediately after the original drive signal Ca changes to a constant voltage and the signal Xflt-A becomes L level, the transistors 231 and 232 are alternately turned on, so the voltage of the drive signal Com-A is kept at a constant target. Vibrates against voltage. In this oscillation process, at this time, for example, at the timing ts2, when the signal Fba is less than the voltage (Vcm + V ₁₁ ) and falls within the voltage (Vcm−V ₁₂ ) or more, the signal FLsa falls to the L level. While the switch 293 is turned on, the transistors 231 and 232 are both turned off. For this reason, the voltage of the drive signal Com-A is a signal obtained by multiplying the original drive signal Ca by 10 times by the linear amplifier 222, and therefore substantially matches the target voltage.

In the drive signal Com-A, the waveform accuracy when the voltage oscillation center value shifts from a region where the voltage oscillation center value falls or rises to a constant region is likely to affect ink ejection. Specifically, the ink is ejected at the timing when the drive signal Com-A changes from the first region to the fourth region. Therefore, if the angle of the trapezoidal waveform at the timing is not as designed, the ink ejection accuracy This is because of a decrease.
When the drive signal Com-A oscillates with respect to the target voltage due to the transistors 231 and 232 being alternately turned on, if the error shifts from a region where the voltage of the drive signal Com-A changes to a certain region, Waveform accuracy tends to decrease.
According to the present embodiment, in the third region or the fourth region, since the drive signal Com-A substantially matches the target voltage by the linear amplifier 222 within a relatively short time, the trapezoidal waveform in the drive signal Com-A. The accuracy can be increased as compared with the configuration without the linear amplifier 222. Therefore, in the present embodiment, it is possible to suppress a decrease in ink ejection accuracy.

  Here, the drive circuit 122a that outputs the drive signal Com-A has been described, but the configuration of the drive circuit 122b that outputs the drive signal Com-B is the same as that of the drive circuit 122a, and only the input / output signals are different. . That is, the drive circuit 122b receives the data dB instead of the data dA and the signal Xflt-B instead of the signal Xflt-A, while the drive signal Com-B is output from the node U1, and the node The drive signal Com-B supplied to Nb is fed back via the FFC 190.

  For the constant potential circuit 202a, various configurations can be applied in addition to the linear amplifier 222 shown in FIG. Therefore, another example of the constant potential circuit 202a will be described next.

FIG. 15 is a diagram illustrating an example of a drive circuit 122a including another configuration of the constant potential circuit 202a.
The constant potential circuit 202a shown in FIG. 15 is different from the configuration shown in FIG. 8 in that the linear amplifier 222 is replaced with a switch 295.
The switch 295 is a three-throw type in which any one of the three contacts is selected and electrically connected to one end of the switch 293. Of the three contacts, the first contact is connected to the feeder K1 to which the voltage Vmax is applied, the second contact is connected to the feeder K2 to which the voltage Vcen is applied, and the third contact is the voltage It is connected to the power supply line K3 to which Vmin is applied.
Which contact is selected for the switch 295 is specified by the data Vsel. The data Vsel specifies that the third contact is selected in the period K2, specifies that the first contact is selected in the period K4, and specifies that the second contact is selected in the period K6. To do. Note that the data Vsel is supplied by the control unit 110 in accordance with the data dA, for example.
Similarly to the configuration having the linear amplifier 222 as shown in FIG. 8, the drive signal Com can be obtained by the configuration as shown in FIG. The accuracy of the signal waveform of -A can be increased.
In addition, according to the constant potential circuit 202a that is switched to one of the power supply lines K1, K2, and K3 by the switch Sw1, since the linear amplifier 222 is not used, the configuration can be simplified.

The driving circuit 122a (122b) described above has a configuration in which the pair of transistors 231 and 232 operate with the power supply voltage (V _D -Gnd) in order to generate the driving signal Com-A (Com-B). As described above, since the voltage V _{D is set} to 42 volts, a high breakdown voltage is required for the control signal generation circuit 126 and the like. This is because it is necessary to supply the gate signal Gp to the gate terminal of the transistor 231 and supply the gate signal Gn to the gate terminal of the transistor 232.
Then, the drive circuit which improved this point is demonstrated next.

FIG. 16 is a diagram illustrating a configuration of a drive circuit according to the first application example.
As shown in this figure, the drive circuit 122a according to the first application example includes a DAC 1202, a comparator 1204, a linear amplifier 222, a switch 293, a switch control circuit 204a, four reference power supplies E, a level shifter 270a, 270b, 270c, 270d, selector 280, four transistor pairs, and capacitors C1 and C2.
In the first application example, the voltages E, 2E, 3E, and 4E output the voltages V _A , V _B , V _C , and V _D by the four-stage series connection of the reference power supplies that output the voltage E, respectively. When the reference power source E outputs 10.5V, for example, the voltages V _A , V _B , V _C , and V _D are 10.5V, 21.0V, 31.5V, and 42.0V, respectively.
In the first application example, a voltage range as defined by the voltages V _A , V _B , V _C , and V _D is defined.
That is, as shown in FIG. 17, a range between the ground Gnd of zero voltage and less than the voltage V _A / 10 is defined as the first range, and a range between voltage V _A / 10 and more than the voltage V _B / 10 is the second range. A range of voltage V _B / 10 or more and less than voltage V _C / 10 is defined as the third range, and a range of voltage V _C / 10 or more and less than voltage V _D / 10 is defined as the fourth range.

In FIG. 16, the signal Ca is supplied to the negative input terminal (−) of the comparator 1204, while the voltage of the drive signal Com-A output from the node U1 is applied to the positive input terminal (+). A signal stepped down to 1/10 by the element R1 and the resistance element R2 is fed back as a feedback signal.
The control signal generation circuit 126 generates gate signals Gp and Gn based on the signal Cmp from the comparator 1204.
In the first application example, the power supply voltage of the comparator 1204 is different from that of the embodiment (see FIG. 8), and the higher side is the voltage _VA . Therefore, each H level of the gate signals Gp and Gn becomes the voltage _VA .

The selector 280 determines the voltage range of the original drive signal Ca from the data dA supplied from the control unit 110, and outputs selection signals Sa, Sb, Sc, and Sd as follows according to the determination result, respectively. To do.
Specifically, when the voltage of the original drive signal Ca defined by the data dA is included in the first range, the selector 280 indicates that the drive signal Com-A obtained by amplifying the original drive signal Ca by 10 times the voltage is the ground. When it is in the range of Gnd or more and less than voltage _VA , only the selection signal Sa is set to H level, and the other selection signals Sb, Sc, Sd are set to L level.
In addition, when the voltage of the original drive signal Ca is included in the second range, that is, when the drive signal Com-A is in the range of the voltage V _A or more and less than the voltage V _B , the selector 280 selects only the selection signal Sb as H. The other selection signals Sa, Sc, Sd are set to L level. Similarly, the selector 280, when the voltage of the original drive signal Ca is included in the third range, i.e., when the driving signal Com-A is in the range of less than voltage V _B over voltage V _C, only the selection signal Sc The other selection signals Sa, Sb, and Sd are set to L level. In addition, when the voltage of the original drive signal Ca is included in the fourth range, that is, when the drive signal Com-A is in the range of the voltage V _C or more and less than the voltage V _D , the selector 280 selects only the selection signal Sd as H. The other selection signals Sa, Sb, and Sc are set to L level.

For convenience of explanation, four transistor pairs will be described.
In this example, the four transistor pairs include a pair of transistors 231a and 232a, a pair of transistors 231b and 232b, a pair of transistors 231c and 232c, and a pair of transistors 231d and 232d.
Among the transistor pairs, the high-side transistors 231a, 231b, 231c, and 231d are, for example, P-channel field effect transistors, and the low-side transistors 232a, 232b, 232c, and 232d are, for example, N-channel field effect transistors. It is.

As for the high-side transistor 231a, the voltage _VA is applied to the source terminal, and the drain terminal is connected to the node U1. As for the low-side transistor 232a, the source terminal is grounded to the ground Gnd, and the drain terminal is connected to the node U1. Similarly, for the high-side transistor 231b (231c, 231d), the voltage V _B (V _C , V _D ) is applied to the source terminal, and the drain terminal is connected to the node U1. As for the low-side transistor 232b (232c, 232d), the voltage V _A (V _B , V _C ) is applied to the source terminal, and the drain terminal is connected to the node U1.

  For example, when the transistor 231a is the first transistor, the transistor 232a is the second transistor, and the transistors 231a and 232a are the first transistor pair, the transistor 231b is the third transistor, the transistor 232b is the fourth transistor, The transistors 231b and 232b form a second transistor pair.

Although details will be described later, when the level shifter 270a is enabled, the transistors 231a and 232a output the drive signal Com-A using the voltage _VA and the ground Gnd as power supply voltages, and the transistors 231b and 232b When the shifter 270b is enabled, the drive signal Com-A is output using the voltage V _B and the voltage V _A as power supply voltages. Similarly, when the level shifter 270c is enabled, the transistors 231c and 232c output the drive signal Com-A using the voltage V _C and the voltage V _B as power supply voltages, and the transistors 231d and 232d have the level shifter 270d When enabled, the drive signal Com-A is output using the voltage V _D and the voltage V _C as power supply voltages.
In this configuration, the power supply voltage of the transistors 231a and 232a, the power supply voltage of the transistors 231b and 232b, the power supply voltage of the transistors 231c and 232c, and the power supply voltage of the transistors 231d and 232d are 10.5V, respectively.

The level shifter 270a sets the H level of the gate signals Gp and Gn output from the control signal generation circuit 126 to the voltage _VA when the selection signal Sa supplied to the input terminal Enb is enabled at the H level. The L level is shifted to the ground Gnd and supplied to the gate terminals of the transistors 231a and 232a. Note that if limited to the level shifter 270a, the H and L levels of the signals Gp and Gn coincide with the voltage _VA and the ground Gnd. Therefore, when enabled, the signals Gp and Gn are directly used as the transistors 231a and 232a. Is supplied to the gate terminal.
When the level shifter 270b is enabled by the H level of the selection signal Sb, the H level of the gate signals Gp and Gn is level-shifted to the voltage V _B and the L level to the voltage V _C , respectively, so that the transistors 231b and 232b Is supplied to the gate terminal. That is, if limited to the level shifter 270b, when enabled, the signals Gp and Gn are each added with 10.5V and supplied to the gate terminals of the transistors 231b and 232b.
Similarly, when the level shifter 270c is enabled by the H level of the selection signal Sc, when the selection signal Sb supplied to the input terminal Enb is set to the H level and is enabled, the level shifter 270c has the H of the gate signals Gp and Gn. the level voltage _{V C,} the voltage _{V B} to L level, and each level-shift supply transistor 231c, the gate terminal of 232c. That is, if it is limited to the level shifter 270c, when it is enabled, 21.0V is added to the signals Gp and Gn and supplied to the gate terminals of the transistors 231c and 232c.
Similarly, the level shifter 270d, when enabled by the H level of the selection signal Sd, the gate signal Gp, the H level of Gn voltage _{V D,} the L level voltage _{V C,} and each level-shifted, transistor 231d and 232d are supplied to the gate terminals. That is, if it is limited to the level shifter 270d, when it is enabled, 31.5V is added to the signals Gp and Gn and supplied to the gate terminals of the transistors 231c and 232c.

The level shifters 270a, 270b, 270c, and 270d are signals that turn off two corresponding transistors when the selection signal supplied to each input terminal Enb is disabled at an L level. Output. That is, when the level shifters 270a, 270b, 270c, and 270d are disabled, the signal Gp is forcibly converted to the H level and the signal Gn is forcibly converted to the L level.
The H and L levels here are the high-side voltage and the low-side voltage of the power supply voltage in each of the level shifters 270a, 270b, 270c, and 270d. For example, since the level shifter 270b uses the voltage V _B and the voltage V _A as power supply voltages, the higher voltage V _B is at the H level and the lower voltage V _A is at the L level.

Note that the capacitor C2 connected in parallel to the resistor element R1 and the capacitor C1 connected in parallel to the resistor element R2 are provided to compensate the phase when the drive signal Com-A is fed back.
The diodes d1 and d2 are provided to prevent backflow. The forward direction of the diode d1 is a direction from the drain terminals of the transistors 231a, 231b, and 231c to the node U1, and the forward direction of the diode d2 is a direction from the node U1 to the drain terminals of the transistors 231b, 231c, and 231d. Here, since the voltage of the node U1 does not become higher than the voltage V _D , there is no need to consider backflow. For this reason, the transistor 231d is not provided with the diode d1. Similarly, since the voltage of the node U1 does not become lower than the ground Gnd having zero voltage, the transistor 232a is not provided with the diode d2.

  Next, the operation of the drive circuit of the first application example will be described on the assumption that the voltage waveform of the original drive signal Ca belongs to the range as shown in FIG.

  First, when the selector 280 determines from the data dA that the voltage of the original drive signal is in the third range before the timing t1, only the selection signal Sc is set to the H level and the other selection signals Sa, Sb, and Sd are set. Set to L level. Therefore, since the level shifter 270c is enabled and the other level shifters 270a, 270b, 270d are disabled, the voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231c, 232c, or The output signal of the linear amplifier 222 is used.

  Next, when the voltage of the drive signal Ca becomes the second range over the period from the timing t1 to the timing t2, the selector 280 sets only the selection signal Sb to the H level and sets the other selection signals Sa, Sc, and Sd to L. Level. For this reason, the level shifter 270b is enabled and the other level shifters 270a, 270c, 270d are disabled, so that the voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231b, 232b. In the example of FIG. 17, the output signal of the linear amplifier 222 is not used in the second range.

  When the voltage of the original drive signal Ca becomes the first range over the period from timing t2 to timing t3, the selector 280 sets only the selection signal Sa to the H level, and as a result, only the level shifter 270a is enabled. The voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231a and 232a, or the output signal of the linear amplifier 222 is used.

  Briefly described below, in the period from timing t3 to timing t4, only the level shifter 270b is enabled, so that the voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231b and 232b. In the period from timing t4 to timing t5, only the level shifter 270c is enabled, so that the voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231c and 232c. In the period from timing t5 to timing t6, only the level shifter 270d is enabled, so that the voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231d and 232d or the output signal of the linear amplifier 222 Will be used. Since only the level shifter 270c is enabled from timing t6, the voltage of the drive signal Com-A is controlled by alternately turning on the transistors 231c and 232c, or the output signal of the linear amplifier 222 is used. Become.

Also in the first application example, the voltage of the dynamic signal Com-A is controlled by alternately turning on the transistors 231c and 232c in the voltage change period, and the output of the linear amplifier 222 by turning on the switch 293 in the constant voltage period. Since the signal is used, it is possible to increase the accuracy of the trapezoidal waveform in the drive signal Com-A, and it is possible to suppress a decrease in the ink ejection accuracy.
In the first application example, there are four transistor pairs. However, since one transistor pair is alternately turned on and the other transistor pair is turned off, power consumption can be reduced. Furthermore, according to the first application example, the comparator 1204 and the control signal generation circuit 126 operate at a relatively low voltage ( _VA- Gnd) as the power source, and therefore the breakdown voltage is lower than that of the embodiment. Thus, enlargement of the size of the constituent elements can be suppressed.

In the first application example, the signal FLsa is supplied to the control signal generation circuit 126. Instead, the signal FLsa may be supplied to the level shifters 270a, 270b, 270c, and 270d close to the transistor pair.
Specifically, the level shifters 270a, 270b, 270c, and 270d preferably output a signal for forcibly turning off each transistor pair if the signal FLsa is at the L level.

  In the first application example, the drive circuit 122a that generates the drive signal Com-A has been described as an example. However, the drive circuit 122b that generates the drive signal Com-B also has the same configuration and operation. The following signal Xflt-B is supplied from the control unit 110 to the drive circuit 122b of the first application example. That is, the signal Xflt-B is at the H level during the period in which the voltage of the signal Cb changes, and is at the L level during the period in which the voltage of the signal Cb is constant.

FIG. 18 is a diagram illustrating an example of a characteristic of the displacement S with respect to the voltage V in the piezoelectric element Pzt. The voltage V is a voltage difference applied to the drive electrodes 72 and 76 (see FIG. 4) in the piezoelectric element Pzt, that is, (Vout−VBS), and the displacement S gives a constant voltage change when the voltage V is applied. The displacement amount (Z direction) of the piezoelectric element Pzt at the time.
In the characteristics shown in FIG. 18, the displacement S of the piezoelectric element Pzt is obtained larger as the applied voltage is lower. In other words, when the applied voltage is low, the piezoelectric element Pzt can obtain a large displacement with a minute voltage change. For this reason, when the piezoelectric element Pzt is driven by the drive signal Com-A (Com-B), the lower the voltage of the drive signal Com-A (Com-B), the higher the waveform accuracy is required. Conversely, high waveform accuracy is not required for the drive signal Com-A in a region where the voltage is high.

For this reason, the signal Xflt-A may be set to the L level only when the voltage of the original drive signal Ca is in the first range, as indicated by a broken line in FIG.
When such a signal Xflt-A is used, the signal Fba is less than the voltage (Vcm + V ₁₁ ) and within the voltage (Vcm−V ₁₂ ) or more in the period in which the original drive signal Ca is constant in the first range. When the signal falls within the range, the signal FLsa becomes L level, and the output signal of the linear amplifier 222 is output as the drive signal Com-A.
Therefore, the piezoelectric element Pzt having the characteristics as shown in FIG. 18 is required and can be driven with sufficient accuracy.

  In the first application example, the number of transistor pairs has been described as “4”. However, from the viewpoint of lowering the withstand voltage, it may be “2” or more. Further, the power supply voltages in each transistor pair need not be equal to each other.

  Thus, according to the inkjet printer 1 according to the present embodiment or the first application example (hereinafter referred to as an embodiment or the like), the drive signal Com-A (Com-B) with respect to the voltage of the original drive signal Ca (Cb). Since the voltage followability is high and the voltage error is reduced, the waveform accuracy of the drive signal Com-A (Com-B) is improved, and the liquid can be ejected with high accuracy.

In the embodiment and the like, since the print head 301 has 600 or more nozzles N arranged at a density of 300 or more per inch, the pitch Py (see FIG. 3) of the nozzles N becomes very narrow. ing. Specifically, as described above, in the nozzle rows L1 and L2 provided in each nozzle plate 632, the nozzles N arranged at a density of 300 or more per inch are half the pitch Py in the sub-scanning direction Y. This is a shifted relationship, and high-definition printing of 600 dpi or more can be performed. In this embodiment, since the pitch Py is very narrow, the lateral width (width in the direction along the direction Y) of the pressure chamber Sc provided corresponding to the nozzle N must be narrow. Since the pressure chamber Sc is narrow in width, it is difficult to deform in the vertical direction, and in order to eject a predetermined amount of ink from the nozzle N, the vertical width of the pressure chamber (the width in the direction along the main scanning direction X) is set. It must be large enough. In order to eject a predetermined amount of ink from the nozzle N, the area (horizontal width × vertical width) of the pressure chamber Sc becomes larger as the lateral width becomes narrower (the pitch Py becomes narrower), and accordingly, the piezoelectric element Pzt. The area S is also increased. Furthermore, in order to eject a predetermined amount of ink from the nozzle N, it is necessary to increase the displacement amount of the piezoelectric element Pzt, so the thickness of the piezoelectric element Pzt in the Z direction must be reduced. In short, the higher the density of the nozzles N arranged for high-definition printing, the larger the area S of the piezoelectric element Pzt and the smaller the thickness, and the larger the capacity of the piezoelectric element Pzt. As a result, the load capacity of the drive circuit 122a (122b) increases and the current I increases, so that the drive signal Com-A (Com-B) changes in the parasitic inductance L of the wiring and the load current I in the FFC 190 or the like. Noise with a magnitude proportional to the product of the rate (L × dI / dt) is superimposed, and a large ripple is likely to occur.
If a large ripple occurs in the drive signal Com-A (Com-B), not only does the liquid ejection accuracy decrease, but in the worst case, the voltage of the drive signal Com-A (Com-B) exceeds the allowable range. As a result, the amount of displacement of the piezoelectric element Pzt may become abnormally large and the diaphragm 46 (see FIG. 4) may be damaged.
On the other hand, according to the present embodiment, the drive signal Com-A (Com-B) corresponding to the voltage of the original drive signal Ca (Cb) even during the period when the voltage of the original drive signal Ca (Cb) rises or falls. Therefore, even if the load capacity increases, the magnitude of the ripple generated in the drive signal Com-A (Com-B) can be kept small. As described above, the ink jet printer 1 according to the present embodiment has a particularly remarkable effect when performing high-definition printing.

  Note that in the embodiment and the like, the transistor 231 is a P-channel type and the transistor 232 is an N-channel type; however, any channel may be used. The logic levels of the gate signals Gp and Gn are closely related to the channel types of the transistors 231 and 232. For this reason, in the control signal generation circuit 126 shown in FIG. 9, the number of inverters (NOT circuits) is appropriately changed depending on the channel type of the transistors 231 and 232.

The signal Xflt-A (Xflt-B) is not supplied by the control unit 110, but a detection circuit is provided separately, and the detection circuit detects a change in voltage defined by the data dA (dB). However, the signal Xflt-A (Xflt-B) may be output in accordance with the presence or absence of the change.
Further, the determination may be made not by the data dA (dB) but by the signal Ca (Cb) converted into analog.

  DESCRIPTION OF SYMBOLS 1 ... Inkjet printer, 30 ... Print head, N ... Nozzle, Pzt ... Piezoelectric element, 190 ... FFC, 202a ... Constant potential circuit, 204a ... Switch control circuit, 1204 ... Comparator, 126 ... Control signal generation circuit, 231 ... Transistor (First transistor), 232... Transistor (second transistor).

Claims (8)

A print head that includes a nozzle and a piezoelectric element that is displaced when a drive signal is applied, and that discharges liquid from the nozzle by the displacement of the piezoelectric element;
A comparator that compares the voltage of the original drive signal and the voltage of the feedback signal, which is a signal obtained by feeding back the drive signal;
A transistor pair including a first transistor having a first gate terminal and a second transistor having a second gate terminal and outputting the drive signal;
A first control signal for controlling a switching operation of the first transistor and a second control signal for controlling a switching operation of the second transistor are input to the first transistor and the second transistor. And a control signal generation circuit that generates the signals to alternately turn on,
A constant potential circuit electrically connected to the piezoelectric element via a switch;
With
The drive signal is
A first region in which the first transistor and the second transistor are alternately turned on to increase the voltage of the drive signal;
A second region in which the first transistor and the second transistor are alternately turned on, and the voltage of the driving signal decreases;
A third region that is between the first region and the second region, and that follows the second region, wherein the first transistor and the second transistor are turned off;
A fourth region that is between the first region and the second region, and that follows the first region, wherein the first transistor and the second transistor are turned off;
Have
The liquid discharge apparatus according to claim 3, wherein the constant potential circuit outputs a drive signal having a voltage corresponding to the original drive signal when the switch is turned on in the third region or the fourth region. The constant potential circuit is
The liquid ejection apparatus according to claim 1, further comprising an amplifier that outputs a voltage corresponding to the original drive signal. The constant potential circuit is
The liquid ejection apparatus according to claim 1, further comprising a power supply line to which a voltage according to the original drive signal is applied. The switch control circuit according to any one of claims 1 to 3, further comprising a switch control circuit that turns on the switch when a current of the drive signal becomes a threshold value or less during a period in which the voltage of the original drive signal is constant. The liquid ejection device according to any one of the above. A print head that includes a nozzle and a piezoelectric element that is displaced when a drive signal is applied, and that discharges liquid from the nozzle by the displacement of the piezoelectric element;
A comparator that compares the voltage of the original drive signal and the voltage of the feedback signal, which is a signal obtained by feeding back the drive signal;
A first transistor pair including a first transistor having a first gate terminal and a second transistor having a second gate terminal, the first transistor pair outputting the drive signal when the voltage of the original drive signal is in a first range; ,
Including a third transistor having a third gate terminal and a fourth transistor having a fourth gate terminal, the voltage of the original drive signal being in a second range higher than the first range, the drive signal being A second transistor pair for output;
An output signal of the comparator is input, and a first control signal for controlling a switching operation of the first transistor or the third transistor and a second control signal for controlling a switching operation of the second transistor or the fourth transistor are provided. A control signal generation circuit for generating the first transistor and the second transistor or the third transistor and the fourth transistor alternately turning on;
A constant potential circuit electrically connected to the piezoelectric element via a switch;
With
The constant potential circuit outputs a drive signal having a voltage corresponding to the original drive signal when the switch is turned on in a period when the voltage of the original drive signal is in the first range and is constant. A liquid discharge apparatus characterized by that. The liquid ejecting apparatus according to claim 1, wherein the first transistor and the second transistor are alternately turned on during a period in which the voltage of the original drive signal increases. 3. The liquid ejection apparatus according to claim 1, wherein the first transistor and the second transistor are alternately turned on during a period in which the voltage of the original drive signal decreases. The liquid ejecting apparatus according to claim 1, wherein the print head includes 600 or more nozzles arranged at a density of 300 or more per inch.

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