JP2019134116A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To achieve a semiconductor device having a high wiring reliability even in a case where a cavity is formed in a connection part.SOLUTION: A first opening 23a formed on a first insulating film 19, 20 is embedded with a first conductive material 26. A cavity 27 formed in the first conductive material is exposed from an upper surface of the first conductive material 26 embedding the first opening 23a. A second insulating film 28 is formed on the first insulating film 19, 20. A second opening 23b communicated with the first opening 23a is formed on the second insulating film 28. An inner wall surface of the second opening 23b is covered with a second conductive material 29 by a sputtering method to close the cavity 27. The inside of the second opening 23b is embedded with a third conductive material 31 via the second conductive material 29.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Recently, contact holes and via holes (hereinafter collectively referred to as connection holes) that are narrow and deep, that is, have a large aspect ratio, are formed due to demands for miniaturization accompanying higher integration of semiconductor devices. It is becoming.

Japanese Patent Laid-Open No. 10-74710 JP 2001-223342 A

  When the conductive material is embedded inside the connection hole, the growth rate of the conductive material is faster near the entrance of the connection hole than at the bottom. It is blocked by the material, and a cavity (void: so-called “su”) is formed in the connection hole. When the conductive material is removed by performing chemical mechanical polishing (CMP) or the like in order to expose the entrance of the connection hole in the subsequent steps, the above-described cavity may be exposed. If another connection hole or wiring is formed on the connection hole with this cavity, contact failure may occur, or wiring material may enter the cavity from the top of the cavity, resulting in reduced wiring reliability. There is.

  An object of the present invention is to provide a semiconductor device with high wiring reliability and a method for manufacturing the same even when a cavity is formed in a conductive material in an opening.

  In one aspect, a method of manufacturing a semiconductor device includes a step of filling a first opening formed in a first insulating film with a first conductive material, and an upper surface of the first conductive material filling the first opening. A step of exposing a cavity formed in one conductive material; a step of forming a second insulating film on the first insulating film; and forming a second opening communicating with the first opening in the second insulating film. And a step of covering the inner surface of the second opening with the second conductive material by a sputtering method and closing the cavity, and the inside of the second opening with the third conductive material via the second conductive material. And an embedding process.

  In one aspect, a semiconductor device is formed in a first conductive material having a first opening formed in a first insulating film and having a cavity therein, and a second insulating film on the first insulating film, A first conductive material that covers an inner wall surface of the second opening that communicates with the first opening and closes the cavity; and a third conductive material that fills the second opening with the second conductive material. Yes.

  In one aspect, a semiconductor device with high wiring reliability can be realized even when a cavity is formed in the conductive material in the opening.

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in order of processes following FIG. 2. It is a schematic sectional drawing which expands the part of a contact plug and shows the main processes in a 1st embodiment. FIG. 5 is a schematic cross-sectional view showing the main process in the first embodiment by enlarging the contact plug portion following FIG. 4. FIG. 6 is a schematic cross-sectional view showing the main process in the first embodiment by enlarging the contact plug portion following FIG. 5. It is a figure which shows the relationship between the aspect-ratio of an upper via hole, and a maximum permissible angle. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor device by 2nd Embodiment. It is a schematic sectional drawing which expands the part of a contact plug and shows the main processes in 2nd Embodiment. FIG. 10 is a schematic cross-sectional view showing the main process in the second embodiment by enlarging the contact plug portion following FIG. 9. FIG. 11 is a schematic cross-sectional view showing main steps in the second embodiment by enlarging a contact plug portion, following FIG. 10.

  Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof will be described in detail with reference to the drawings. In the following embodiments, a semiconductor device including a ferroelectric capacitor is illustrated, and the structure thereof will be described together with a manufacturing method.

[First Embodiment]
1 to 3 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. In each drawing, the same reference numerals are given to the same or equivalent components.

First, as shown in FIG. 1A, after forming an element isolation region 2 in a semiconductor substrate 1, a gate insulating film 3 and a gate electrode 4 are formed.
Specifically, first, the element isolation region 2 is formed in the surface layer portion of the P-type semiconductor substrate 1 by using, for example, STI (shallow trench isolation) technology.
Next, ion implantation for forming a well, a channel stop diffusion layer, and the like is performed in the element formation region of the semiconductor substrate 1 defined by the element isolation region 2.

Then, for example, by a thermal oxidation method, SiO ₂ film is formed as a gate insulating film on the surface of the semiconductor substrate 1, for example, by CVD method to form a polysilicon film serving as a gate electrode on the SiO ₂ film.

Next, the SiO ₂ film and the polysilicon film are patterned by lithography and etching. As described above, the gate electrode 4 is formed on the element formation region via the gate insulating film 3.

Subsequently, as shown in FIG. 1B, an LDD region 5, a sidewall insulating film 6, a source / drain region 7, and a silicide layer 8 are formed.
Specifically, first, in order to form an LDD (lightly doped drain) region, N-type impurities such as P and As are formed on both sides of the gate electrode 4 in the element formation region of the semiconductor substrate 1 using the gate electrode 4 as a mask. Ion implantation is relatively shallow.

Next, after an insulator such as SiO ₂ is deposited on the semiconductor substrate 1 so as to cover the gate electrode 4 by, for example, CVD, the entire surface of the insulator is etched back to form the gate insulating film 3 and the gate electrode 4. Leave insulation only on the sides. Thus, the sidewall insulating film 6 is formed on the side surfaces of the gate insulating film 3 and the gate electrode 4.

  Next, in order to form the source / drain regions, N-type impurities such as P and As are relatively formed on both sides of the sidewall insulating film 6 in the element forming region of the semiconductor substrate 1 using the sidewall insulating film 6 as a mask. Deep ion implantation. Then, the semiconductor substrate 1 is heat-treated to activate the introduced N-type impurity. Thus, the LDD region 5 and the source / drain region 7 partially overlapping therewith are formed.

Next, a salicide process is performed. A silicide metal, such as W or Ti, is deposited on the entire surface of the semiconductor substrate 1 by sputtering or the like, and the semiconductor substrate 1 is heat-treated to cause the upper surface of the gate electrode 4 and the upper surface of the source / drain region 7 to react with the silicide metal. . Unreacted silicide metal is removed by a predetermined wet treatment. Thus, the silicide layer 8 is formed on the upper surface of the gate electrode 4 and the upper surface of the source / drain region 7. By forming the silicide layer 8, the contact resistance of the gate electrode 4 and the source / drain region 7 can be reduced.
As a result, a MOS transistor is formed on the semiconductor substrate 1.

Subsequently, as shown in FIG. 1C, a cover film 9, an interlayer insulating film 10, and contact plugs 11A and 11B are formed.
Specifically, first, an insulating material such as Si ₃ N ₄ is deposited on the entire surface of the semiconductor substrate 1 by, eg, CVD, and a cover film 9 having a thickness of, eg, about 70 nm is formed.
Next, an insulator such as SiO ₂ is deposited on the cover film 9 by, eg, CVD, and the surface thereof is planarized by, eg, CMP. Thus, the interlayer insulating film 10 is formed.

Next, the interlayer insulating film 10 is patterned by lithography and etching to form a contact hole 11a that exposes a part of the surface of each source / drain region 7.
Next, a barrier conductive material such as TiN or TaN is deposited on the interlayer insulating film 10 so as to cover the inner wall surface (side surface and bottom surface) of the contact hole 11a, thereby forming the barrier film 11b.

  Next, a refractory metal such as W (tungsten) 11c is deposited on the barrier film 11b so as to fill the contact hole 11a via the barrier film 11b by, for example, the CVD method.

  Next, excess barrier film 11b and W11c existing on the surface of interlayer insulating film 10 are polished and removed by, for example, CMP. Thus, contact plugs 11A and 11B are formed to fill the contact hole 11a with W11c through the barrier film 11b.

Subsequently, as shown in FIG. 1D, an antioxidant film 12 and a buffer film 13 are formed.
Specifically, first, an insulating material such as Si ₃ N ₄ is deposited on the interlayer insulating film 10 by, eg, CVD, and the antioxidant film 12 having a thickness of, eg, about 100 nm is formed.
Next, an insulator such as SiO ₂ is deposited on the antioxidant film 12 by, eg, CVD, and a buffer film 13 having a thickness of, eg, about 130 nm is formed.

Subsequently, as shown in FIG. 2A, a ferroelectric capacitor is formed.
Specifically, first, for example, an Al ₂ O ₃ film serving as an adhesion layer is formed on the buffer film 13. Next, for example, a Pt film serving as a lower electrode is formed on the Al ₂ O ₃ film. Next, for example, a PZT film to be a ferroelectric film is formed on the Pt film. Thereafter, a rapid heat treatment is performed on the ferroelectric film. Thereby, the ferroelectric film is crystallized. Next, an IrO ₂ film to be an upper electrode is formed on the ferroelectric film. Then, the PZT film and the IrO ₂ film, and the Al ₂ O ₃ film and the Pt film are patterned by lithography and etching, respectively. As a result, a ferroelectric capacitor is formed on the buffer film 13 with the lower electrode 15 and the upper electrode 17 sandwiching the ferroelectric film 16 via the adhesion layer 14.

Subsequently, as shown in FIG. 2B, a hydrogen barrier film 18 and interlayer insulating films 19 and 20 are formed.
Specifically, first, an insulating material such as Al ₂ O ₃ is deposited so as to cover the upper surface and side surfaces of the ferroelectric capacitor by, eg, CVD, and the hydrogen barrier film 18 having a thickness of, for example, about 50 nm is formed. As a material for the hydrogen barrier film, for example, TiO ₂ can be used.

Next, for example, a plasma CVD method using a mixed gas containing TEOS (Tetraethyl Orthosilicate), oxygen, and helium is used to form an interlayer insulating film 19 having a thickness of, for example, about 1400 nm mainly containing SiO ₂ on the hydrogen barrier film 18. Form. The interlayer insulating film 19 is preferably formed under conditions that can eliminate hydrogen and moisture in the interlayer insulating film 19 in order to prevent deterioration of the characteristics of the ferroelectric capacitor. Specifically, it can be realized by measures such as increasing the film formation temperature, increasing the gas pressure, and increasing the oxygen flow rate. After the formation of the interlayer insulating film 19, the surface of the interlayer insulating film 19 is planarized using, for example, a CMP method. Thereafter, heat treatment is performed with respect to the N ₂ O gas or N ₂ gas, etc. interlayer insulating film 19 in a plasma atmosphere generated by using the. By this heat treatment, moisture contained in the interlayer insulating film 19 is removed, the film quality of the interlayer insulating film 19 is changed, and entry of hydrogen and moisture into the interlayer insulating film 19 is suppressed.

Next, an interlayer insulating film 20 having a thickness of about 250 nm mainly containing SiO ₂ is formed on the interlayer insulating film 19 by plasma CVD using a mixed gas containing silane, N ₂ O gas, or N ₂ . After the film formation, the interlayer insulating film 20 is preferably heat-treated in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. By this heat treatment, moisture contained in the interlayer insulating film 20 is removed and the film quality of the interlayer insulating film 20 is changed, and entry of hydrogen and moisture into the interlayer insulating film 20 is suppressed.

Subsequently, as shown in FIG. 2C, lower via holes 21a, 22a, 23a, and 24a are formed.
Specifically, first, the hydrogen barrier film 18 and the interlayer insulating films 19 and 20 are patterned by lithography and etching. As a result, lower via holes 21a and 22a are formed to expose part of the surface of the upper electrode 17 and part of the surface of the lower electrode 15 of the ferroelectric capacitor.
Next, the antioxidant film 12, the buffer film 13, the hydrogen barrier film 18, and the interlayer insulating films 19 and 20 are formed by lithography and etching. As a result, lower via holes 23a and 24a exposing the surfaces of the contact plugs 11A and 11B are formed.

  Subsequently, as shown in FIG. 3A, the contact plug 21 connected to the upper electrode 17 of the ferroelectric capacitor, the contact plug 22 connected to the lower electrode 15, and the source / drain regions 17a of the MOS transistor, Contact plugs 23 and 24 connected to 17b are formed. Among these contact plugs, for example, the contact plugs 23 and 24 are formed in the interlayer insulating film 19 or the like having a ferroelectric capacitor, so that the aspect ratio thereof is much larger than other contact plugs. Therefore, the lower via hole is not sufficiently filled with, for example, W, and a cavity is formed inside. In this embodiment, as will be described below, this cavity is effectively covered to prevent contact failure.

  The contact plug 23 has a via to via structure of a lower contact plug 23A having a large aspect ratio and an upper contact plug 23B having a smaller aspect ratio. Similarly, the contact plug 24 has a via to via structure of a lower contact plug 24A having a large aspect ratio and an upper contact plug 24B having a smaller aspect ratio. In order to be compatible with the contact plug 23, the contact plug 21 is similarly composed of lower and upper contact plugs 21A, 21B. Similarly, the contact plug 22 includes lower and upper contact plugs 22A and 22B.

  4 to 6 are schematic cross-sectional views showing the main steps in the present embodiment by enlarging the contact plug 23 portion. Hereinafter, although the process of forming the contact plug 23 will be described, the contact plug 24 is formed in the same manner as the contact plug 23. It is assumed that the contact plugs 21 and 22 do not have cavities formed therein. Even in this case, the contact plugs 21 and 22 are formed in the same formation process as the contact plug 23.

As shown in FIG. 4A, a barrier film 25 and W (tungsten) 26 are formed.
Specifically, first, for example, TiN or TaN, which is a barrier conductive material, is deposited on the interlayer insulating film 20 so as to cover the inner wall surface (side surface and bottom surface) of the lower via hole 23a by, for example, the CVD method. Form. The same applies to the lower via holes 21a, 22a, and 24a.
Next, a refractory metal such as W26 is deposited on the barrier film 25 so as to fill the lower via hole 23a via the barrier film 25. At this time, the lower via holes 21a and 22a are satisfactorily filled with W26, but since the lower via holes 23a and 24a have a larger aspect ratio than the lower via holes 21a and 22a, a cavity 27 is generated inside.

  Subsequently, as shown in FIG. 4B, the excess barrier film 25 and W26 existing on the surface of the interlayer insulating film 20 are polished and removed by, for example, CMP. Thus, the contact plug 23A is formed. In the contact plug 23A, the cavity 27 is exposed from the upper surface of W26 by CMP polishing. Similarly, contact plugs 24A having cavities inside the cavities 27 exposed from the upper surface of W26 and contact plugs 21A and 22A in which no cavities are formed are formed.

Subsequently, as shown in FIG. 4C, an interlayer insulating film 28 is formed.
Specifically, the interlayer insulating film 28 mainly containing SiO ₂ is formed on the interlayer insulating film 20 by plasma CVD using a mixed gas containing silane, N ₂ O gas, or N ₂ . The interlayer insulating film 28 is formed to a thickness of about 200 nm, for example. After the film formation, the interlayer insulating film 28 is preferably heat-treated in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. By this heat treatment, moisture contained in the interlayer insulating film 28 is removed and the film quality of the interlayer insulating film 28 is changed, and entry of hydrogen and moisture into the interlayer insulating film 28 is suppressed.

Subsequently, as shown in FIG. 5A, an upper via hole 23b is formed.
Specifically, first, the interlayer insulating film 28 is patterned by lithography and etching. As a result, an upper via hole 23b communicating with the lower via hole 23a and exposing the upper surface of the contact plug 23A is formed. The upper via hole 23b is formed with a smaller aspect ratio than the lower via hole 23a. Similarly, upper via holes 21b, 22b, and 24b are formed.

Subsequently, as shown in FIG. 5C, a barrier film 29 is formed.
Specifically, by sputtering, for example, using TiN as a barrier conductive material, the semiconductor substrate 1 is inclined with respect to the sputtering surface 30a (the normal direction thereof) of the sputtering target 30 as shown in FIG. The sputter film formation is performed while the semiconductor substrate 1 is rotated. In this case, with respect to the sputtering surface, the bottom surface is set to an angle at which a part of the bottom surface of the upper via hole 23b is exposed in plan view (an angle larger than an angle at which the entire bottom surface can be seen and smaller than an angle at which the bottom surface cannot be seen at all). Tilt. This inclination angle varies depending on the aspect ratio of the upper via hole. In order to arrange a part of the bottom surface of the upper via hole 23b so that it can be seen from the sputtering surface 30a, it is necessary to be smaller than the maximum allowable angle defined by the following equation.

θ = (π / 2) −arctan (a / b)
φ = θ × (180 / π)
θ: Maximum allowable angle (radian) from the horizontal plane (sputtering plane)
φ: Maximum allowable angle (°) from the horizontal plane (sputtering surface)
a: upper via hole depth b: upper via hole diameter a / b: aspect ratio

FIG. 7 is a diagram ((a): table, (b): graph) showing the relationship between the aspect ratio of the upper via hole and the maximum allowable angle.
In the present embodiment, the inclination angle α with respect to the sputtering surface 30a of the semiconductor substrate 1 is
0 ° <α ≦ φ
It is necessary to. If the bottom surface of the upper via hole 23b is not visible with respect to the sputtering surface 30a, a barrier film is not formed on the bottom surface of the upper via hole 23b, and burying defects are likely to occur in the subsequent W film formation. Therefore, the bottom surface of the upper via hole 23b must be set to an angle that can be seen from the sputtering surface 30a.

  Further, although the rectilinearity of the sputtered particles in the sputtering is not questioned, the rectilinear sputtering method is preferable for the upper via hole having a large aspect ratio. On the other hand, for an upper via hole having a low aspect ratio, a straight sputtering thin sputtering method is preferable.

  As shown in FIG. 5B, the sputtering particles 30b of TiN are deposited by the sputtering so as to cover the inner wall surfaces (side surfaces and bottom surface) of the upper via hole 23b, and the barrier film 29 is formed. Here, with respect to the bottom surface of the upper via hole 23 b, the sputtered particles 30 b do not enter the cavity 27, but cover the upper surface of the bottom W 26 and close the cavity 27. The barrier film 29 is formed on the bottom surface of the upper via hole 23b so as to gradually decrease from the central portion toward the end portion.

  The barrier film 29 is also formed in the upper via holes 21b, 22b, and 24b so as to cover these inner wall surfaces (side surfaces and bottom surface). It is also possible to form a mask covering the upper via holes 21b and 22b and forming the mask for opening the upper via holes 23b and 24b, and performing the above sputtering to form a barrier film only on the upper via holes 23b and 24b. In this case, a barrier film having a substantially uniform thickness can be formed on the side and bottom surfaces of the upper via holes 21b and 22b by normal sputtering without providing an inclination angle.

  Subsequently, as shown in FIG. 6A, a refractory metal such as W31 is deposited on the barrier film 29 so as to fill the upper via hole 23b via the barrier film 29 by, eg, CVD. Similarly, the upper via holes 21 b, 22 b and 24 b are also filled with W 31 through the barrier film 29. Since the upper via hole 23b has an aspect ratio smaller than that of the lower via hole 23a, the upper via hole 23b is completely filled with W31 and no cavity is generated inside. The same applies to the upper via holes 21b, 22b, and 24b.

  Subsequently, as shown in FIG. 6B, excess barrier film 29 and W31 existing on the surface of the interlayer insulating film 28 are removed by polishing, for example, by CMP. As a result, the upper contact plug 23B filling the upper via hole 23b with W31 via the barrier film 29 is formed. Similarly, upper contact plugs 21B, 22B, and 24B that fill the inside of the upper via holes 21b, 22b, and 24b with W31 through the barrier film 29 are formed. Thus, contact plugs 21, 22, 23, and 24 are formed.

Then, as shown in FIG. 3B, each wiring 35 is formed.
Specifically, first, the lower barrier film 32 including the Ti film 32a and the TiN film 32b, the aluminum copper alloy film 33, the Ti film 34a, and the entire surface on the interlayer insulating film 28 so as to cover the contact plugs 21 to 24, The upper barrier film 34 including the TiN film 34b is sequentially stacked.
The lower barrier film 32, the aluminum copper alloy film 33, and the upper barrier film 34 are patterned by lithography and etching. As described above, each wiring 35 connected to the contact plugs 21 to 24 is formed.
Thereafter, the semiconductor device according to the present embodiment is formed through the formation of further interlayer insulating films and upper layer wirings.

  In the present embodiment, in the upper contact plugs 23 </ b> B and 24 </ b> B, the upper portion of the cavity 27 is reliably closed by the barrier film 29. Cavities are not generated in the upper contact plugs 21B to 24B, which are connection portions of the contact plugs 21 to 24 with the wiring 35 (only the periphery of the contact plug 23 is shown in FIG. 6C). Therefore, the wiring 35 is held in a good state on the upper contact plugs 21B to 24B without the wiring material falling into the cavity. Thus, according to the present embodiment, a semiconductor device with high wiring reliability is realized even when the cavity 27 is formed in the contact plugs 23 and 24.

[Second Embodiment]
In the present embodiment, a semiconductor device including a ferroelectric capacitor is illustrated as in the first embodiment, but differs from the first embodiment in that the configuration of the contact plug is different. 8 to 9 are schematic cross-sectional views showing main steps of the semiconductor device manufacturing method according to the second embodiment. Note that the same constituent members as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, similarly to the first embodiment, the processes of FIGS. 1A to 2B are performed. At this time, a hydrogen barrier film 18 and interlayer insulating films 19 and 20 covering the ferroelectric capacitor are formed.

Subsequently, as shown in FIG. 8A, lower linear grooves 41a, 42a, 43a, and 44a are formed.
Specifically, first, the hydrogen barrier film 18 and the interlayer insulating films 19 and 20 are patterned by lithography and etching. In the patterning, for example, a linear groove extending in the depth direction of FIG. As a result, lower linear grooves 41a and 42a that expose a part of the surface of the upper electrode 17 and a part of the surface of the lower electrode 15 of the ferroelectric capacitor are formed.
Next, the antioxidant film 12, the buffer film 13, the hydrogen barrier film 18, and the interlayer insulating films 19 and 20 are formed by lithography and etching. Thus, lower linear grooves 43a and 44a that expose the surfaces of the contact plugs 11A and 11B are formed.

  In the present embodiment, the case where the lower linear grooves 41a, 42a, 43a, and 44a are formed is illustrated, but one of these is a lower linear groove and the other is the same as in the first embodiment. A lower via hole may be considered. Moreover, you may form the cyclic | annular groove | channel used as what is called a guard ring extended in the depth direction of Fig.8 (a), for example with these lower linear grooves (and lower via holes).

  Subsequently, as shown in FIG. 8B, a contact structure 41 connected to the upper electrode 17 of the ferroelectric capacitor, a contact structure 42 connected to the lower electrode 15, and a source / drain region 17a of the MOS transistor, Contact structures 43 and 44 connected to 17b are formed. Among these contact structures, for example, the contact structures 43 and 44 are formed in the interlayer insulating film 19 or the like having a ferroelectric capacitor, so that the aspect ratio is much larger than other contact structures. For this reason, the lower linear groove is not sufficiently filled with, for example, W, and a cavity is formed inside. In this embodiment, as will be described below, this cavity is effectively covered to prevent contact failure.

  The contact structure 43 is formed by connecting a lower contact structure 43A having a large aspect ratio and an upper contact structure 43B having a smaller aspect ratio. Similarly, the contact structure 44 is formed by connecting a lower contact structure 44A having a large aspect ratio and an upper contact structure 44B having a smaller aspect ratio. In order to be matched with the contact structure 43, the contact structure 41 is similarly composed of lower and upper contact structures 41A and 41B. Similarly, the contact structure 42 includes lower and upper contact structures 42A and 42B.

  9 to 11 are schematic cross-sectional views showing the main steps in the present embodiment by enlarging the portion of the contact structure 43. Hereinafter, although the formation process of the contact structure 43 will be described, the contact structure 44 is formed in the same manner as the contact structure 43. It is assumed that the contact structures 41 and 42 do not have cavities formed therein. Even in this case, the contact structures 41 and 42 are formed in the same formation process as the contact structure 43.

As shown in FIG. 9A, a barrier film 45 and W (tungsten) 46 are formed.
Specifically, first, a barrier conductive material such as TiN or TaN is deposited on the interlayer insulating film 20 so as to cover the inner wall surface (side surface and bottom surface) of the lower linear groove 43a by, for example, the CVD method. A film 45 is formed. The same applies to the lower linear grooves 41a, 42a, and 44a.
Next, a refractory metal, for example, W46 is deposited on the barrier film 45 so as to fill the lower linear groove 43a through the barrier film 45. At this time, the lower linear grooves 41a and 42a are satisfactorily filled with W46. However, since the lower linear grooves 43a and 44a have a larger aspect ratio than the lower linear grooves 41a and 42a, a cavity 47 is generated inside. Is done.

  Subsequently, as shown in FIG. 9B, excess barrier film 45 and W46 existing on the surface of the interlayer insulating film 20 are removed by polishing, for example, by CMP. As a result, the contact structure 43A is formed. In the contact structure 43A, the cavity 47 is exposed from the upper surface of W46 by CMP polishing. Similarly, contact structures 44A having cavities 47 in which the cavities 47 are exposed from the upper surface of W46, and contact structures 41A and 42A in which no cavities are formed are formed.

Subsequently, as shown in FIG. 9C, an interlayer insulating film 48 is formed.
Specifically, the interlayer insulating film 48 mainly containing SiO ₂ is formed on the interlayer insulating film 20 by using a plasma CVD method using a mixed gas containing silane, N ₂ O gas, or N ₂ . The interlayer insulating film 48 is formed to a thickness of about 200 nm, for example. After the film formation, the interlayer insulating film 48 is preferably heat-treated in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. By this heat treatment, moisture contained in the interlayer insulating film 48 is removed and the film quality of the interlayer insulating film 48 is changed, and entry of hydrogen and moisture into the interlayer insulating film 48 is suppressed.

Subsequently, as shown in FIG. 10A, an upper linear groove 43b is formed.
Specifically, first, the interlayer insulating film 48 is patterned by lithography and etching. As a result, the upper linear groove 43b communicating with the lower linear groove 43a and exposing the upper surface of the contact structure 43A is formed. The upper linear groove 43b is formed with a smaller aspect ratio than the lower linear groove 43a. Similarly, upper linear grooves 41b, 42b, and 44b are formed.

Subsequently, as shown in FIG. 10C, a barrier film 49 is formed.
Specifically, by using, for example, TiN as a barrier conductive material by sputtering, the semiconductor substrate 1 is inclined with respect to the sputtering surface 30a (normal direction) of the sputtering target 30 as shown in FIG. The sputter film formation is performed while the semiconductor substrate 1 is rotated. In this case, the angle at which a part of the bottom surface of the upper linear groove 43b is exposed in a plan view with respect to the sputtering surface (an angle larger than an angle at which the entire bottom surface can be seen and smaller than an angle at which the bottom surface cannot be seen at all). Tilt the bottom. This inclination angle varies depending on the aspect ratio of the upper via hole. In order to arrange a part of the bottom surface of the upper linear groove 43b so as to be visible from the sputtering surface 30a, it is necessary to be smaller than the maximum allowable angle defined by the following equation.

θ = (π / 2) −arctan (a / b)
φ = θ × (180 / π)
θ: Maximum allowable angle (radian) from the horizontal plane (sputtering plane)
φ: Maximum allowable angle (°) from the horizontal plane (sputtering surface)
a: upper via hole depth b: upper via hole diameter a / b: aspect ratio

In the present embodiment, the inclination angle α with respect to the sputtering surface 30a of the semiconductor substrate 1 is
0 ° <α ≦ φ
It is necessary to. If the bottom surface of the upper linear groove 43b is not visible with respect to the sputtering surface 30a, a barrier film is not formed on the bottom surface of the upper linear groove 43b, and burying defects are likely to occur in the subsequent W film formation. Therefore, the bottom surface of the upper linear groove 43b must be set to an angle that can be seen from the sputtering surface 30a.

  Further, although the rectilinearity of the sputtered particles in the sputtering is not questioned, the rectilinear sputtering method is preferable for the upper via hole having a large aspect ratio. On the other hand, for an upper via hole having a low aspect ratio, a straight sputtering thin sputtering method is preferable.

  As shown in FIG. 10B, the sputtering particles 30b of TiN are deposited by the sputtering so as to cover the inner wall surfaces (side surfaces and bottom surface) of the upper linear groove 43b, and the barrier film 49 is formed. Here, with respect to the bottom surface of the upper linear groove 43b, the sputtered particles 30b do not enter the cavity 27, but cover the upper surface of the bottom surface W26 and the cavity 47 is blocked. The barrier film 49 is formed on the bottom surface of the upper linear groove 43b so as to gradually decrease from the central portion toward the end portion. For example, the barrier film 49 closes the cavity 47 at the thickest portion of the central portion.

  The barrier film 49 is also formed in the upper linear grooves 41b, 42b, and 44b so as to cover these inner wall surfaces (side surfaces and bottom surface). It is also possible to form a mask covering the upper linear grooves 41b and 42b and forming the mask for opening the upper linear grooves 43b and 44b, and performing the above sputtering to form a barrier film only in the upper linear grooves 43b and 44b. is there. In this case, a barrier film having a substantially uniform thickness can be formed on the side and bottom surfaces of the upper linear grooves 41b and 42b by normal sputtering without providing an inclination angle.

  Subsequently, as shown in FIG. 11A, a refractory metal such as W51 is deposited on the barrier film 49 so as to fill the upper linear groove 43b via the barrier film 49 by, for example, the CVD method. Similarly, the upper linear grooves 41 b, 42 b and 44 b are also filled with W 51 through the barrier film 49. Since the upper linear groove 43b has a smaller aspect ratio than that of the lower linear groove 43a, the upper linear groove 43b is completely filled with W51 and does not generate a cavity inside. The same applies to the upper linear grooves 41b, 42b, and 44b.

  Subsequently, as shown in FIG. 11B, excess barrier film 49 and W51 existing on the surface of the interlayer insulating film 48 are removed by polishing, for example, by CMP. As a result, an upper contact structure 43B that fills the upper linear groove 43b with W51 through the barrier film 49 is formed. Similarly, upper contact structures 41B, 42B, and 44B that fill the upper linear grooves 41b, 42b, and 44b with W51 through the barrier film 49 are formed. Thus, contact structures 41, 42, 43, and 44 are formed.

Then, as shown in FIG. 8C, each wiring 55 is formed.
Specifically, first, the lower barrier film 32 including the Ti film 52a and the TiN film 52b, the aluminum copper alloy film 53, the Ti film 54a, and the entire surface on the interlayer insulating film 48 so as to cover the contact structures 41 to 44, The upper barrier film 54 including the TiN film 54b is sequentially stacked.
The lower barrier film 52, the aluminum copper alloy film 53, and the upper barrier film 54 are patterned by lithography and etching. As a result, the wirings 55 connected to the contact structures 41 to 44 are formed.
Thereafter, the semiconductor device according to the present embodiment is formed through the formation of further interlayer insulating films and upper layer wirings.

  In the present embodiment, in the upper contact structures 43B and 44B, the upper portion of the cavity 47 is reliably closed by the barrier film 49. Cavities are not generated in the upper contact structures 41B to 44B, which are connection parts of the contact structures 41 to 44 with the wiring 55 (FIG. 11C shows only the periphery of the contact structure 43). Therefore, the wiring 55 is held in a good state on the upper contact structures 41B to 44B without the wiring material falling into the cavity. Thus, according to the present embodiment, a semiconductor device with high wiring reliability is realized even when the cavity 47 is formed in the contact structures 43 and 44.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Element isolation region 3 Gate insulating film 4 Gate electrode 5 LDD region 6 Side wall 7 Source / drain region 8 Silicide layer 9 Cover film 10, 19, 20, 28, 48 Interlayer insulating film 11a Contact hole 11b, 25, 29, 45, 49 Barrier film 11c, 26, 31, 46, 51 W (tungsten)
11A, 11B Contact plug 12 Antioxidation film 13 Buffer film 14 Adhesion layer 15 Lower electrode 16 Ferroelectric film 17 Upper electrode 18 Hydrogen barrier films 21, 22, 23, 24 Contact plugs 21A, 22A, 23A, 24A Lower contact plug 21B , 22B, 23B, 24b Upper contact plugs 21a, 22a, 23a, 24a Lower via holes 21b, 22b, 23b, 24b Upper via holes 27, 47 Cavity 30 Sputter target 30a Sputtering surface 30b Sputtered particles 32, 52 Lower barrier films 34, 54 Upper Barrier films 32a, 34a, 52a, 54a Ti films 32b, 34b, 52b, 54b TiN films 33, 53 Aluminum copper alloy films 35, 55 Wiring 41, 42, 43, 44 Contact structures 41A, 42A, 43A, 4 A lower contact structure 41B, 42B, 43B, 44b upper contact structure 41a, 42a, 43a, 44a lower linear grooves 41b, 42b, 43b, 44b upper linear groove

Claims (7)

Filling the first opening formed in the first insulating film with a first conductive material;
Exposing a cavity formed in the first conductive material from an upper surface of the first conductive material filling the first opening;
Forming a second insulating film on the first insulating film and forming a second opening communicating with the first opening in the second insulating film;
A step of covering the inner surface of the second opening with a second conductive material and closing the cavity by a sputtering method;
Filling the second opening with a third conductive material through the second conductive material. A method for manufacturing a semiconductor device, comprising:   The second conductive layer is sputtered while the bottom surface is inclined at an angle at which a part of the bottom surface of the second opening is exposed in a plan view with respect to the sputtering surface of the sputtering target, and the bottom surface is rotated within the bottom surface. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a material is deposited.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductive material is formed to have a thickness that gradually decreases from a central portion toward an end portion of the bottom surface of the second opening.   The method for manufacturing a semiconductor device according to claim 1, wherein the second opening has an aspect ratio smaller than that of the first opening. A first conductive material filling a first opening formed in the first insulating film and having a cavity inside;
A first conductive material formed on a second insulating film on the first insulating film and covering an inner wall surface of a second opening communicating with the first opening and closing the cavity;
A semiconductor device comprising: a third conductive material that fills the second opening with the second conductive material interposed therebetween.   The semiconductor device according to claim 5, wherein the second conductive material has a thickness that gradually decreases from a central portion toward an end portion at a bottom surface of the second opening.   The semiconductor device according to claim 5, wherein the second opening has an aspect ratio smaller than that of the first opening.

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