JP2019126189A - Insulation synchronous rectification type dc/dc converter - Google Patents

Abstract

To provide an insulation synchronous rectification type DC/DC converter capable of resolving a problem related to a withstanding voltage of a drain terminal included in a synchronous rectification controller even for such a specification that a high positive voltage is generated as a drain voltage of a synchronous rectification transistor.SOLUTION: Provided is an insulation synchronous rectification type DC/DC converter that comprises: a synchronous rectification transistor arranged at a secondary side; and a synchronous rectification controller that controls drive of the synchronous rectification transistor. The insulation synchronous rectification type DC/DC converter has a transistor connected between a drain terminal included in the synchronous rectification controller and a drain of the synchronous rectification transistor.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an insulation synchronous rectification type DC / DC converter.

  A flyback type DC / DC converter is used for various power supply circuits including an AC / DC converter. FIG. 8 is a circuit diagram of a synchronous rectification type flyback converter 200S.

  The flyback converter 200S of FIG. 8 receives an input voltage Vin at its input terminal P1, generates a DC output voltage Vout stabilized at a predetermined target voltage, and is connected between the output terminal P2 and the ground terminal P3. Load (not shown). The switching transistor M1 is connected to the primary winding W1 of the transformer T1, and the synchronous rectification transistor M2 is connected to the secondary winding W2. The output capacitor C1 is connected to the output terminal P2.

  The feedback circuit 206 drives the light emitting element of the photocoupler 204 with a current according to the error between the output voltage Vout and its target voltage. A feedback current Ifb according to the error flows in the light receiving element of the photocoupler 204. The feedback signal Vfb corresponding to the feedback current Ifb is generated on the FB (feedback) pin of the primary side controller 202, and the primary side controller 202 generates a pulse signal having a duty ratio (or frequency) corresponding to the feedback signal Vfb To drive the switching transistor M1.

The flyback converter of a synchronous rectification type, the loss of the synchronous rectifier transistor M2 becomes Ron × Iout ^2. Ron is the on-resistance of the synchronous rectification transistor M2, and when Ron = 5 mΩ and Iout = 10 A, the loss is 0.5 W, which is much smaller than that of the diode rectification type. Therefore, theoretically, in the synchronous rectification type, the heat sink and the heat sink can be eliminated or simplified.

JP, 2009-159721, A

  The synchronous rectification controller 300S shown in FIG. 8 turns on the synchronous rectification transistor M2 when the switching transistor M1 is turned off, and the current in the secondary winding W2 becomes substantially zero (secondary side zero current), the synchronous rectification is performed. Turn off transistor M2. For this purpose, the synchronous rectification controller 300S monitors the drain voltage VDS2 of the synchronous rectification transistor M2, and detects the turn-off of the switching transistor M1 and the secondary side zero current based on the drain voltage VDS2.

  A pulse voltage is generated across the positive voltage and the negative voltage in the drain voltage VDS2 according to the on / off of the switching transistor M1. As the output voltage Vout is set higher, the turn ratio of the primary winding W1 to the secondary winding W2 is adjusted, and the positive voltage in the pulse voltage is higher. The drain voltage VDS2 is input to the drain terminal Td of the synchronous rectification controller 300S. However, when the positive voltage becomes high, there is a problem that the withstand voltage of the drain terminal Td is exceeded. For example, there is a case where the withstand voltage of the drain terminal Td is 120 V when the positive voltage is 150 V.

  In view of the above problems, according to the present invention, it is an insulation synchronous rectification type DC / DC that can solve the problem regarding the withstand voltage of the drain terminal of the synchronous rectification controller even if the specification is such that a high positive voltage is generated in the drain voltage The purpose is to provide a converter.

  The present invention is an isolated and synchronous rectification type DC / DC converter including a synchronous rectification transistor disposed on the secondary side and a synchronous rectification controller for controlling driving of the synchronous rectification transistor, wherein the synchronous rectification controller And a transistor connected between the drain terminal of the transistor and the drain of the synchronous rectification transistor (first configuration).

  In the first configuration, a predetermined power supply voltage from a power supply may be applied to the gate of the transistor (second configuration).

In the first configuration, a Zener diode and a resistor connected in series between the gate of the transistor and the drain of the synchronous rectification transistor;
Power supply,
A diode connected between the power supply and the gate of the transistor may be further included (third configuration).

  In the third configuration, a capacitor connected in parallel with the connection configuration of the zener diode and the resistor may be further provided between the gate of the transistor and the drain of the synchronous rectification transistor ( Fourth configuration).

In the third or fourth configuration, the power supply includes a resistor and a second Zener diode connected in series between the output terminal of the isolated synchronous rectification type DC / DC converter and the ground terminal;
An FET having a gate connected to a connection node between the resistor and the second Zener diode, and a drain connected to the output terminal;
And a second capacitor connected between the source of the FET and the ground terminal,
The diode may be connected to a connection node between the second capacitor and the FET (fifth configuration).

In the fifth configuration, the synchronous rectification controller includes an LDO regulator connected to a connection node between the second capacitor and the FET.
The power supply includes a bipolar transistor connected between the gate of the FET and the ground terminal.
A control signal may be applied to the base of the bipolar transistor (sixth configuration).

  The transistor may be an FET, a source of the transistor may be connected to the drain terminal, and a drain of the transistor may be connected to a drain of the synchronous rectification transistor (a seventh configuration).

  Moreover, it is preferable that the insulation synchronous rectification type DC / DC converter of any one of the said structures is a flyback converter.

  According to the insulation synchronous rectification type DC / DC converter of the present invention, even in the specification that a high positive voltage is generated in the drain voltage of the synchronous rectification transistor, the problem regarding the withstand voltage of the drain terminal of the synchronous rectification controller can be solved.

FIG. 1 is a circuit diagram of a DC / DC converter according to a first embodiment of the present invention. It is a circuit diagram showing an example of a pulse generator. It is a circuit diagram of a DC / DC converter concerning a 2nd embodiment of the present invention. It is a timing chart which shows the operation example of the DC / DC converter concerning a 2nd embodiment of the present invention. It is a circuit diagram of the DC / DC converter concerning a 3rd embodiment of the present invention. It is a timing chart which shows an example of shutdown control in a DC / DC converter concerning a 3rd embodiment of the present invention. It is a circuit diagram of the DC / DC converter concerning a 4th embodiment of the present invention. It is a circuit diagram of the DC / DC converter which concerns on a prior art example.

  An embodiment of the present invention will be described below with reference to the drawings.

First Embodiment
FIG. 1 is a circuit diagram of the isolated DC / DC converter 200A according to the first embodiment. The DC / DC converter 200A is a flyback converter (insulated synchronous rectification type DC / DC converter), receives an input voltage Vin at its input terminal P1, and generates a DC output voltage Vout stabilized at a predetermined target voltage Supply to a load (not shown) connected to the output terminal P2.

  The transformer T1 has a primary winding W1 and a secondary winding W2. One end of the primary winding W1 is connected to the input terminal P1 and receives a DC input voltage Vin. The drain of the switching transistor M1 is connected to the other end of the primary winding W1. The source of the switching transistor M1 is grounded.

  The synchronous rectification transistor M2 and the secondary winding W2 of the transformer T1 are provided in series between the output terminal P2 and the ground terminal P3. The output capacitor C1 is connected between the output terminal P2 and the ground terminal P3.

  The feedback circuit 206 drives the light emitting element of the photocoupler 204 with a current according to the error between the output voltage Vout and its target voltage. A feedback current Ifb according to the error flows in the light receiving element of the photocoupler 204. The feedback signal Vfb corresponding to the feedback current Ifb is generated on the FB (feedback) pin of the primary side controller 202, and the primary side controller 202 generates a pulse signal having a duty ratio (or frequency) corresponding to the feedback signal Vfb To drive the switching transistor M1.

  The synchronous rectification controller 300A controls the synchronous rectification transistor M2. The diode D2 is a body diode of the synchronous rectification transistor M2. The synchronous rectification controller 300A generates a control pulse based on the drain voltage VDS2 of the synchronous rectification transistor M2, and supplies a gate pulse corresponding to the control pulse to the gate of the synchronous rectification transistor M2.

  The synchronous rectification controller 300A is housed in one package, and has at least a drain terminal Td, a source terminal Ts, a gate terminal Tg, and a power supply terminal Tvcc. The source terminal Ts is a ground terminal of the synchronous rectification controller 300A.

  The synchronous rectification controller 300A drives the synchronous rectification transistor M2 based on the voltage VS1 generated at the drain terminal Td. The drain terminal Td is connected to the drain of the synchronous rectification transistor M2 via the FET 305, as described later. The voltage VS1 is the source voltage of the FET 305.

  More specifically, the synchronous rectification controller 300A includes a driver 302 and a pulse generator 301. The pulse generator 301 generates a pulse signal S11 based on the voltage VS1 at the drain terminal Td. The pulse generator 301 detects the turn-off of the switching transistor M1 and the zero current at which the current Is of the secondary winding W2 becomes substantially zero based on the voltage VS1 of the drain terminal Td, and turns off the switching transistor M1. The pulse signal S11 is caused to transition to the on level with the trigger of T.sub.t as a trigger, and the pulse signal S11 is caused to transition to the off level with the zero current as a trigger.

  FIG. 2 is a circuit diagram showing one configuration example of the pulse generator 301. As shown in FIG. As shown in FIG. 2, the pulse generator 301 includes a first comparator 301A, a second comparator 301B, and a flip flop 301C. The first comparator 301A compares the voltage VS1 of the drain terminal Td with a predetermined first threshold voltage VthA, and outputs an ON signal Son as a comparison result to the set terminal of the flip flop 301C. The second comparator 301B compares the voltage VS1 of the drain terminal Td with a predetermined second threshold voltage VthB, and outputs the off signal Soff as a comparison result to the reset terminal of the flip flop 301C. The pulse signal S11 output from the Q output terminal of the flip flop 301C is input to the driver 302. The driver 302 outputs a gate drive signal S12 from the gate terminal Tg to the gate of the synchronous rectification transistor M2 based on the pulse signal S11.

  When the switching transistor M1 is turned off, the voltage VS1 becomes negative together with the drain voltage VDS2, and the first comparator 301A detects that the voltage VS1 is lower than the negative first threshold voltage VthA (for example, -150 mA), The on signal Son is asserted. As a result, the flip flop 301 C is set, the pulse signal S 11 becomes High, the gate drive signal S 12 becomes on level, and the synchronous rectification transistor M 2 is turned on.

  During the on period of the synchronous rectification transistor M2, the current Is flows from the source to the drain of the synchronous rectification transistor M2, the drain voltage VDS2 becomes a negative voltage, and its absolute value is proportional to the amount of the current Is. When the current Is decreases and the drain voltage VDS2 increases in the positive direction, and the comparator 301B detects that the voltage VS1 has become higher than the negative second threshold voltage VthA (for example, -10 mA), the off signal Soff is asserted. As a result, the flip flop 301 C is reset, the pulse signal S 11 becomes Low, the gate drive signal S 12 becomes an off level, and the synchronous rectification transistor M 2 is turned off.

  Here, the drain terminal Td is connected to the drain of the synchronous rectification transistor M2 via the FET 305 formed of an n-channel MOSFET. The source of the FET 305 is connected to the drain terminal Td. The drain of the FET 305 is connected to the drain of the synchronous rectification transistor M2. A predetermined gate voltage Vg1 from the power supply 306 is applied to the gate of the FET 305.

  In the drain voltage VDS2, a pulse voltage is generated across the positive voltage and the negative voltage according to the on / off of the switching transistor M1. When a positive voltage is generated in the drain voltage VDS2, the voltage VS1 generated at the source of the FET 305, that is, the drain terminal Td is clamped by the FET 305 to a voltage lower than the gate voltage Vg1 to the threshold voltage Vth of the FET 305.

  For example, when the positive voltage is 150 V, the gate voltage Vg1 is 12 V, and the threshold voltage Vth is 3 V, the voltage VS1 is clamped at 12 V-3 V = 9 V. At this time, since the withstand voltage of the drain terminal Td is, for example, 120 V, there is no problem even if 9 V is applied. Furthermore, assuming that the withstand voltage of the FET 305 is, for example, 200 V, the drain-source voltage of the FET 305 is 150 V-9 V = 141 V, which is 200 V or less.

  Further, when a negative voltage is generated in the drain voltage VDS2, the FET 305 is turned on, so that the voltage VS1 becomes the same as the negative voltage of the drain voltage VDS2.

  As described above, according to this embodiment, even if the positive voltage generated in the drain voltage VDS2 is increased by setting the output voltage Vout higher, the drain terminal Td withstands the withstand voltage due to the voltage clamp by the FET 305. Voltage VS1 can be applied.

Second Embodiment
FIG. 3 is a circuit diagram of a DC / DC converter 200B according to a second embodiment. The difference between the DC / DC converter 200B and the first embodiment (FIG. 1) described above is the configuration of the FET 307 connected to the drain terminal Td.

  The source of the FET 307 which is an n-channel MOSFET is connected to the drain terminal Td. The drain of the FET 307 is connected to the drain of the synchronous rectification transistor M2. The gate of the FET 307 is connected to one end of the capacitor C2 together with one end of the resistor R1. The other end of the resistor R1 is connected to the anode of the zener diode Z1. The cathode of the Zener diode Z1 is connected to the drain of the synchronous rectification transistor M2. The other end of the capacitor C2 is connected to the drain of the synchronous rectification transistor M2. That is, the resistor R1 and the Zener diode Z1 are connected in series between the gate of the FET 307 and the drain of the synchronous rectification transistor M2, and the resistor R1 and the Zener diode Z1 are connected between the gate of the FET 307 and the drain of the synchronous rectification transistor M2. A capacitor C2 is connected in parallel with the connection configuration according to.

  The cathode of the diode D1 is connected to the gate of the FET 307. The output voltage V308 of the power supply 308 is applied to the anode of the diode D1. The power supply 308 specifically includes a resistor R2, a zener diode Z2, an FET 308A, and a capacitor C3. One end of the resistor R2 is connected to the output terminal P2. The other end of the resistor R2 is connected to the cathode of the zener diode Z2. The anode of the Zener diode Z2 is grounded. The drain of the FET 308A, which is an n-channel MOSFET, is connected to the output terminal P2. The source of the FET 308A is connected to one end of the capacitor C3. The other end of the capacitor C3 is grounded. The gate of the FET 308A is connected to the connection node between the resistor R2 and the zener diode Z2.

  For example, assuming that the output voltage Vout is 24V and the Zener voltage of the Zener diode Z2 is 15V, the connection node between the resistor R2 and the Zener diode Z2 is clamped at 15V. Thus, 15V is applied to the gate of FET 308A, 24V is applied to the drain of FET 308A, and the source of FET 308A is clamped to a voltage lowered from 15V by the threshold voltage of FET 308A. When the threshold voltage is 2 V, for example, the source of the FET 308A is 13 V. In this case, an output voltage V308 occurs as 13 V at the connection node between the source of the FET 308A and the capacitor C3.

  Here, the operation of the DC / DC converter 200B will be described using the timing chart shown in FIG. FIG. 4 shows the drain voltage VDS2, the pulse drive signal S12, the current Is, the gate voltage Vg2 of the FET 307, the source voltage Vs2 of the FET 307, and the drain-source voltage Vds of the FET 307 in this order from the top. In addition, although demonstrated below based on the specific example of the voltage value shown by FIG. 4, the voltage value here is only an example.

  Before the timing t0, the switching transistor M1 is on, the gate drive signal S12 is off, the synchronous rectification transistor M2 is off, and the current Is does not flow. At this time, 150 V which is a positive voltage is generated in the drain voltage VDS2. Assuming that the Zener voltage of the Zener diode Z1 is 47V, for example, the gate voltage Vg2 is 150V−47V = 103V due to the breakdown of the Zener diode Z1. Then, the source voltage Vs2 is clamped by the FET 307 to a voltage that is reduced from the gate voltage Vg2 by the threshold voltage Vth of the FET 307. When the threshold voltage Vth is 3 V, for example, the source voltage Vs2 is clamped at 103 V-3 V = 100 V. Therefore, a voltage that can withstand the withstand voltage 120 V of the drain terminal Td is applied to the drain terminal Td. Further, at this time, the drain-source voltage Vds is 150V-100V = 50V, and the withstand voltage of the FET 307 can withstand even if it is 60V, for example. That is, as in the first embodiment, it is not necessary to use a high breakdown voltage FET having a breakdown voltage of, for example, 200 V for clamping, which makes it possible to reduce the cost.

  Also, when the switching transistor M1 is turned off at timing t0, the drain voltage VDS2 becomes a negative voltage. At this time, the diode D1 is turned on, and the gate voltage Vg2 is a voltage obtained by reducing the output voltage V308 by Vf (forward voltage) of the diode D1. Assuming that Vf is 1V, 13V-1V = 12V. The FET 307 is turned on, the source voltage Vs2 becomes the same as the drain voltage VDS2, and becomes a negative voltage. Then, the pulse signal S11 is set to High by the pulse generator 301, and the gate drive signal S12 is turned on. Thus, the synchronous rectification transistor M2 is turned on and the current Is starts to flow.

  As the current Is gradually decreases, the drain voltage VDS2 and the source voltage Vs2 of the negative voltage rise, and when the zero current is reached at the timing t1, the pulse signal S11 is made Low by the pulse generator 301 and the gate drive signal S12 is At the off level, the synchronous rectification transistor M2 is turned off. Thereafter, when the switching transistor M1 is turned on, the drain voltage VDS2 becomes 150 V which is a positive voltage again.

  The capacitor C2 is configured to pass an AC component of the drain voltage VDS2. Thus, for example, when the drain voltage VDS2 changes from a negative voltage to a positive voltage, the gate voltage Vg2 remains at a voltage lowered from the output voltage V308 by Vf of the diode D1, and a large voltage is generated between the drain and source of the FET 307 It can be suppressed to be applied.

Third Embodiment
FIG. 5 is a circuit diagram of a DC / DC converter 200C according to a third embodiment. The difference between the DC / DC converter 200C and the above-described second embodiment (FIG. 3) is the configuration relating to the power supply terminal Tvcc and the power supply 308 of the synchronous rectification controller 30A.

  Specifically, the power supply terminal Tvcc is connected to the connection node of the FET 308A in the power supply 308 and the capacitor C3. Further, in the power supply 308, the collector of the bipolar transistor Tr1 is connected between the connection node of the resistor R2 and the Zener diode Z2 and the gate of the FET 308A. The emitter of the bipolar transistor Tr2 is grounded. A control terminal P4 is connected to the base of the bipolar transistor Tr1. A control signal S4 for switching on level and off level is applied to the control terminal P4 from a microcomputer (not shown).

  In the synchronous rectification controller 300A, an LDO (Low Dropout) regulator 350 is included. The LDO regulator 350 receives an input voltage applied to the power supply terminal Tvcc, and the LDO regulator 350 generates and outputs an internal voltage Vreg based on the input voltage.

  When the control signal S4 of the on level (Low) is applied to the control terminal P4 by the microcomputer, the bipolar transistor Tr1 is turned off, and the output voltage V308 (for example, 13 V) is applied to the power supply terminal Tvcc by the clamp by the FET 308A. Thereby, LDO regulator 350 generates internal voltage Vreg based on output voltage V308.

  Since the internal voltage Vreg is a power supply of the driver 302, as in the timing chart shown in FIG. 6, while the control signal S4 is on level, the gate drive signal S12 is repeatedly off and on level by the internal voltage Vreg. Become.

  When the control signal S4 is turned off (high) by the microcomputer, the bipolar transistor Tr1 is turned on, and the gate of the FET 308A is grounded. As a result, the FET 308A is turned off and discharge of the capacitor C3 is started. As the output voltage V308 decreases due to the discharge, the internal voltage Vreg also decreases. Thereby, as shown from the timing t11 of FIG. 6, the on level of the gate drive signal S12 decreases. Then, when the output voltage V308 falls below the UVLO detection voltage, the LDO 350 stops the output of the internal voltage Vreg. Thereby, the gate drive signal S12 is turned off at timing t12 shown in FIG.

  As described above, in the present embodiment, the on / off control of the internal power supply 308 by the microcomputer enables shutdown control of the synchronous rectification controller 300A.

Fourth Embodiment
Although the flyback converter has been exemplified in the above embodiments, the present invention is also applicable to an LLC converter. FIG. 7 is a circuit diagram of a DC / DC converter 200D according to a fourth embodiment. On the primary side, transistors M11 and M12 and a resonant capacitor Cs are provided.

  The primary side controller 202D drives the transistors M11 and M12 based on the feedback signal Vfb. The primary side controller 202D may be configured using a known technique.

  The transformer T2 has secondary windings W22 and W22. On the secondary side, two synchronous rectification transistors M21 and M22 are provided. The synchronous rectification controller 300D drives the synchronous rectification transistor M21 based on the drain voltage VD1 of the synchronous rectification transistor M21, and drives the synchronous rectification transistor M22 based on the drain voltage VD2 of the synchronous rectification transistor M22. The synchronous rectification controller 300D includes two synchronous rectification controllers (CH1, CH2).

  As shown in FIG. 7, the first drain terminal Td1 of the synchronous rectification controller 300D is connected to the drain of the synchronous rectification transistor M21 via the FET 351, and the second drain terminal Td2 of the synchronous rectification controller 300D is an FET 352. Are connected to the drain of the synchronous rectification transistor M22. A predetermined voltage is applied to the gate of the FETs 351 and 352 by a predetermined power supply.

  Thus, even if positive voltages are generated in the drain voltages VD1 and VD2, as in the first embodiment described above, the source voltages of the FETs 351 and 352 (ie, applied to the first drain terminal Td1 and the second drain terminal Td2) The voltage) is clamped at a voltage which is lowered by a threshold voltage of the FET from a predetermined voltage by the power supply. Accordingly, it is possible to withstand the withstand voltage of the first drain terminal Td1 and the second drain terminal Td2.

  As another embodiment, it is also possible to apply a clamp configuration using an FET as in the second embodiment described above to the LLC converter.

  Further, the present invention is more effective because the flyback converter tends to have a higher positive voltage generated in the drain voltage of the synchronous rectification transistor than the LLC converter.

<Others>
As mentioned above, although embodiment of this invention was described, within the range of the meaning of this invention, embodiment can be variously changed.

  The present invention can be used, for example, in a flyback converter.

200A to 200D, 200S DC / DC converter P1 input terminal P2 output terminal P3 ground terminal T1, T2 transformer W1 primary winding W2, W21, W22 secondary winding M1 switching transistor M2 synchronous rectification transistor D2 body diode C1 output capacitor 202 primary Side controller 204 photocoupler 206 feedback circuit 300A, 300D, 300S synchronous rectification controller 301 pulse generator 302 driver 305 FET
306 Power supply Td Drain terminal Tvcc Power supply terminal Tg Gate terminal Ts Source terminal 307 FET
308 Power supply Tr1 Bipolar transistor 350 LDO regulator P4 control terminal M11, M12 transistor M21, M22 synchronous rectification transistor 300D synchronous rectification controller Td1 first drain terminal Td2 second drain terminal 351, 352 FET

Claims (8)

A synchronous rectification transistor disposed on the secondary side,
An isolated synchronous rectification type DC / DC converter comprising: a synchronous rectification controller for controlling driving of the synchronous rectification transistor;
An isolated synchronous rectification type DC / DC converter comprising a transistor connected between a drain terminal of the synchronous rectification controller and a drain of the synchronous rectification transistor.   The isolated synchronous rectification type DC / DC converter according to claim 1, wherein a predetermined power supply voltage from a power supply is applied to a gate of the transistor. A zener diode and a resistor connected in series between the gate of the transistor and the drain of the synchronous rectification transistor;
Power supply,
The isolated synchronous rectification type DC / DC converter according to claim 1, further comprising: a diode connected between the power supply and a gate of the transistor.   The isolated synchronous rectification type DC / DC according to claim 3, further comprising: a capacitor connected in parallel with the zener diode and the connection configuration by the resistor between the gate of the transistor and the drain of the synchronous rectification transistor. converter. The power supply includes a resistor and a second Zener diode connected in series between the output terminal of the isolated synchronous rectification type DC / DC converter and the ground terminal;
An FET having a gate connected to a connection node between the resistor and the second Zener diode, and a drain connected to the output terminal;
And a second capacitor connected between the source of the FET and the ground terminal,
The isolated synchronous rectification type DC / DC converter according to claim 3 or 4, wherein the diode is connected to a connection node between the second capacitor and the FET. The synchronous rectification controller includes an LDO regulator connected to a connection node between the second capacitor and the FET.
The power supply includes a bipolar transistor connected between the gate of the FET and the ground terminal.
The isolated synchronous rectification type DC / DC converter according to claim 5, wherein a control signal can be applied to a base of the bipolar transistor. The transistor is a FET,
The isolated synchronous rectification type DC according to any one of claims 1 to 6, wherein a source of the transistor is connected to the drain terminal, and a drain of the transistor is connected to a drain of the synchronous rectification transistor. / DC converter.   The isolated synchronous rectification type DC / DC converter according to any one of claims 1 to 7, which is a flyback converter.

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