JP2019125236A - Control apparatus - Google Patents

Abstract

To allow data from first and second computer to be output to an outside with being smoothly switched to each other if both of them are normal in an apparatus having the first and second computers for monitoring abnormality.SOLUTION: A control apparatus according to the present invention has an AND circuit input with signals from first and second computers, and a switching unit for switching a state among a first state for transmitting an output of the AND circuit to the outside, a second state for transmitting only an output of the first computer to the outside, and a third state for transmitting only an output of the second computer to the outside. Further, the control apparatus has a switching control unit for controlling the switching unit to switch the state to the first state if both of the first and second computers are normal with respect to the AND circuit, for controlling the switching unit to switch the state to the second state if the second computer is not normal, and for controlling the switching unit to switch the state to the third state if the first computer is not normal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a control device.

  Conventionally, as a control device of this type, first and second CPUs that mutually monitor abnormality using run pulses, control data from the first CPU and control data from the second CPU are selected and peripheral circuits are selected. There has been proposed one having a data selector for outputting to the outside (see, for example, Patent Document 1). In this control device, when an abnormality occurs in one of the first and second CPUs, the data selector selects control data from the other CPU (normal CPU) and outputs it via the peripheral circuit. Do.

Japanese Patent Application Laid-Open No. 11-53207

  In the control device described above, when the first and second CPUs are both normal and the control data from the first and second CPUs are switched to the outside through the peripheral circuit while switching the control data, the data selector makes it possible to It is necessary to switch between the first state connecting the circuit and the second state connecting the second CPU and the peripheral circuit. Therefore, when switching between the first state and the second state by the data selector, a delay may occur in the output of control data from the first and second CPUs to the outside.

  The control device according to the present invention is provided with the first and second computers that mutually monitor abnormality, and when both are normal, the data from the first and second computers can be output to the outside while switching smoothly. The main purpose is to

  The control device of the present invention adopts the following means in order to achieve the above-mentioned main object.

The control device of the present invention is
A control device comprising a first and a second computer that mutually monitor abnormalities and communicating with the outside,
An AND circuit to which signals from the first and second computers are input;
A first state for transmitting the output of the AND circuit to the outside, a second state for transmitting only the output of the first computer to the outside, and a third state for transmitting only the output of the second computer to the outside And a switching unit capable of switching
When both the first and second computer sides viewed from the AND circuit are normal, the switching unit is made to be in the first state, and when the second computer side is abnormal, the switching unit is in the second state A switching control unit for causing the switching unit to be in the third state when the first computer side is abnormal;
The gist is to have

  In the control device according to the present invention, an AND circuit to which signals from the first and second computers are input, a first state for transmitting an output of the AND circuit to the outside, and an output of only the first computer to the outside And a switching unit capable of switching between the two states and a third state in which only the output of the second computer is transmitted to the outside. Furthermore, when the first and second computers as viewed from the AND circuit are normal, the switching unit is brought to the first state, and when both the second computers are abnormal, the switching unit is brought to the second state. The switching control unit is configured to cause the switching unit to be in the third state when the side is abnormal. As a result, when both the first and second computers are normal, the data from the first computer and the data from the second computer are compared with those in which the second state and the third state are switched as needed. And can be sent to the outside while switching smoothly. Further, data from the first computer can be transmitted to the outside even when an abnormality occurs in the second computer side, and data from the second computer can be transmitted to the outside even when an abnormality occurs in the first computer side. be able to.

  Here, the first computer side viewed from the AND circuit corresponds to the first computer and the first wiring between the first computer and the AND circuit, and the second computer side viewed from the AND circuit includes the second computer and the second computer. The second wiring of the computer and the AND circuit corresponds.

  In the control device according to the present invention, the switching control unit, when receiving a reset request for the second computer from the first computer, brings the switching unit into the second state and resets the second computer. When the reset request for the first computer is received from the second computer, the switching unit may be brought into the third state and the first computer may be reset. In this way, data from the first computer can be transmitted to the outside even when the second computer is reset. Further, even when the first computer is reset, data from the second computer can be transmitted to the outside.

  Further, in the control device of the present invention, a first abnormality detection unit for detecting an abnormality in the first wiring between the first computer and the AND circuit, an abnormality in the second wiring between the second computer and the AND circuit, The switching control unit further causes the switching unit to be in the third state when an abnormality in the first wiring is detected by the first abnormality detecting unit. (2) When the abnormality of the second wiring is detected by the abnormality detection unit, the switching unit may be brought into the second state. In this way, data from the second computer can be transmitted to the outside even when an abnormality occurs in the first wiring. Further, even when an abnormality occurs in the second wiring, data from the first computer can be transmitted to the outside. In this case, the first abnormality detection unit may occupy the first wiring as a first dominant timeout circuit, and the second abnormality detection unit may be a second dominant timeout circuit.

It is a block diagram which shows the outline of a structure of the electronic control unit (ECU) 20 as a control apparatus which is one Example of this invention. FIG. 7 is an explanatory view showing a state when the first and second microcomputers 21 and 23 transmit data to an external electronic control unit when the selector 32 is in the first state. It is a flowchart which shows an example of a sequence when abnormality arises in the 1st microcomputer. It is a flowchart which shows an example of a sequence when abnormality arises in the 2nd microcomputer. FIG. 10 is a flowchart showing an example of a sequence when an abnormality occurs in the first wiring 25. FIG. It is a flowchart which shows an example of a sequence when abnormality generate | occur | produces in 2nd wiring 26. FIG. It is a block diagram which shows the outline of a structure of the electronic control unit 20B of a modification.

  Next, modes for carrying out the present invention will be described using examples.

  FIG. 1 is a block diagram schematically showing the configuration of an electronic control unit (ECU) 20 as a control device according to an embodiment of the present invention. As illustrated, the electronic control unit 20 of the embodiment performs CAN communication with an external electronic control unit (an electronic control unit connected via the CAN communication line 10), and the first and second microcomputers (Hereinafter referred to as a "microcomputer") 21, 23, first and second dominant timeout circuits 27, 28, an AND circuit 30, a selector 32 as a switching unit, a selector controller 34, a reset controller 36, a transceiver And 38. The electronic control unit 20 is mounted on an electric car or a hybrid car equipped with a motor. For example, the first microcomputer 21 is configured as a microcomputer that communicates with the main electronic control unit and drives and controls the first motor. Reference numeral 23 is configured as a microcomputer that communicates with the main electronic control unit and controls driving of the second motor.

  Although not shown, the first and second microcomputers 21 and 23 are each configured as a microprocessor centering on a CPU, and in addition to the CPU, temporarily store ROM for processing programs and data. It has RAM, I / O port and communication port. Data from an external electronic control unit is input to the first and second microcomputers 21 and 23 through the receiver 38 a of the transceiver 38, and the data from the first and second microcomputers 21 and 23 are the first and second microcomputers 21 and 23. The signal is output to the second wires 25 and 26. Data is input / output (transmission / reception) in a binary number of 0 (dominant) or 1 (recessive). Examples of data received by the first and second microcomputers 21 and 23 from an external electronic control unit include, for example, torque commands of the first and second motors. Further, as data to be transmitted from the first and second microcomputers 21 and 23 to the external electronic control unit, for example, the number of rotations of the first and second motors can be mentioned.

  The first and second microcomputers 21 and 23 are communicably connected to each other. The first and second microcomputers 21 and 23 include monitoring units 22 and 24 as functional blocks. The monitoring units 22 and 24 monitor the other microcomputer by the run pulse (watchdog timer) or the calculated value comparison (so-called homework answer or SUM check) and detect an abnormality in the other microcomputer, the other microcomputer The reset request signal is output to the reset controller 36. When receiving the reset instruction signal from the reset controller 36, the first and second microcomputers 21 and 23 reset (initialize).

  The first dominant timeout circuit 27 is provided in the first wiring 25 connecting the first microcomputer 21 to the AND circuit 30 and the selector 32, and detects occupancy of the first wiring 25, specifically, 0 (dominant When a continuation over a time corresponding to a predetermined number of bits (e.g., 5 bits) is detected, the first abnormality signal is output to the selector controller 34 on the assumption that the first wiring 25 is abnormal.

  The second dominant timeout circuit 28 is provided in the second wiring 26 connecting the second microcomputer 23 to the AND circuit 30 and the selector 32, and detects occupancy of the second wiring 26, specifically, 0 (dominant When a continuation over a time corresponding to a predetermined number of bits (e.g., 5 bits) is detected, the second abnormality signal is output to the selector controller 34 on the assumption that the second wiring 26 is abnormal.

  The AND circuit 30 has input terminals connected to the first and second wires 25 and 26 and an output terminal connected to the selector 32. When both the first and second wires 25 and 26 are 1 (recessive) 1 (recessive) is output, and 0 (dominant) is output when at least one of the first and second wires 25 and 26 is 0 (dominant).

  The selector 32 has a first state for connecting the output terminal of the AND circuit 30 and the transmitter 38 b of the transceiver 38, a second state for connecting the first wire 25 and the transmitter 38 b, a second wire 26 and a transmitter It is configured to be switchable from the third state in which it is connected to 38b.

  The selector controller 34 receives signals from the reset controller 36 regarding the states of the first and second microcomputers 21 and 23 (hereinafter referred to as "microcomputer state signals") and the first and second abnormalities from the first and second dominant timeouts. The selector 32 is set to any one of the first state, the second state, and the third state based on the presence or absence of a signal.

  The reset controller 36 outputs a reset instruction signal to the second and first microcomputers 23 and 21 when the reset request signal for the second and first microcomputers 23 and 21 from the first and second microcomputers 21 and 23 is input. Do. Further, the reset controller 36 outputs a microcomputer state signal to the selector controller 34 based on the presence or absence of the reset request signal of the second and first microcomputers 23 and 21. The microcomputer status signal is a signal indicating that both the first and second microcomputers 21 and 23 are normal, a signal indicating that the first microcomputer 21 is abnormal, and a signal indicating that the second microcomputer 23 is abnormal. It becomes either.

  The transceiver 38 manages communication between the first and second microcomputers 21 and 23 and an external electronic control unit (an electronic control unit connected via the CAN communication line 10). Specifically, the transceiver 38 has a receiver 38a and a transmitter 38b, transmits data from an external electronic control unit to the first and second microcomputers 21 and 23 through the receiver 38a, and the selector 32 Data from the above are transmitted to an external electronic control unit via the transmission unit 38b.

  In the electronic control unit 20 of the embodiment thus configured, when the first and second microcomputers 21 and 23 as viewed from the AND circuit 30 are normal, the selector controller 34 causes the selector 32 to be in the first state. When the first and second microcomputers 21 and 23 are normal, the first and second abnormal signals are not output from the first and second dominant timeout circuits 27 and 28 to the selector controller 34, and The reset request signal of the second and first microcomputers 23 and 21 is not output from the microcomputers 21 and 23 to the reset controller 36, and the first and second microcomputers 21 and 23 are sent as microcomputer state signals to the selector controller 34 from the reset controller A signal indicating that all are normal is output.

  FIG. 2 is an explanatory view showing how the first and second microcomputers 21 and 23 transmit data to an external electronic control unit when the selector 32 is in the first state. As illustrated, when neither of the first and second microcomputers 21 and 23 transmits data, the first and second microcomputers 21 and 23 set the first and second wires 25 and 26 to 1 (recessive). Hold on. Thus, the output of the AND circuit 30 is held at 1. When data is transmitted from the first microcomputer 21, the second microcomputer 23 holds the second wiring 26 at 1 (recessive), and the first microcomputer 21 sets the first wiring 25 to 0 (dominant based on the data). Or 1 (recessive). Thus, the output of the AND circuit 30 has a value corresponding to the data from the first microcomputer 21. Furthermore, when transmitting data from the second microcomputer 23, the first microcomputer 21 holds the first wiring 25 at 1 (recessive), and the second microcomputer 23 sets the second wiring 26 to 0 (dominant based on the data). Or 1 (recessive). Thus, the output of the AND circuit 30 has a value corresponding to the data from the second microcomputer 23. In the embodiment, data from the first and second microcomputers 21 and 23 are alternately transmitted via the transceiver 38 by communication between the first and second microcomputers 21 and 23 or according to a predetermined schedule. Send to

  FIG. 3 is a flowchart showing an example of the sequence when an abnormality occurs in the first microcomputer 21. FIG. 4 is a flowchart showing an example of the sequence when an abnormality occurs in the second microcomputer 23. FIG. 6 is a flowchart showing an example of the sequence when an abnormality occurs in the first wiring 25. FIG. 6 is a flowchart showing an example of the sequence when an abnormality occurs in the second wiring 26. The following will be described in order.

  As shown in FIG. 3, when an abnormality occurs in the first microcomputer 21, the monitoring unit 24 of the second microcomputer 23 detects an abnormality in the first microcomputer 21 (step S 100), and the second microcomputer 23 transmits a reset controller 36. A reset request signal of the first microcomputer 21 is output (step S110). When the reset request signal of the first microcomputer 21 is input, the reset controller 36 outputs a reset instruction signal to the first microcomputer 21 to reset (initialize) the first microcomputer 21 (step S120), and the selector controller A signal indicating that the first microcomputer 21 is abnormal is output to the microcomputer 34 as a microcomputer status signal (step S130). When a signal indicating that the first microcomputer 21 is abnormal is input as the microcomputer state signal, the selector controller 34 causes the selector 32 to be in the third state (a state in which the second wiring 26 and the transmission unit 38 b are connected). (Step S140). As a result, even when an abnormality occurs in the first microcomputer 21, data can be transmitted from the second microcomputer 23 to an external electronic control unit.

  As shown in FIG. 4, when an abnormality occurs in the second microcomputer 23, the monitoring unit 22 of the first microcomputer 21 detects an abnormality in the second microcomputer 23 (step S 200), and the first microcomputer 21 transmits a reset controller 36. A reset request signal of the second microcomputer 23 is output (step S210). When the reset request signal of the second microcomputer 23 is input, the reset controller 36 outputs a reset instruction signal to the second microcomputer 23 to reset (initialize) the second microcomputer 23 (step S220), and the selector controller A signal indicating that the second microcomputer 23 is abnormal is output to the microcomputer 34 as a microcomputer status signal (step S230). When a signal indicating that the second microcomputer 23 is abnormal is input as the microcomputer state signal, the selector controller 34 causes the selector 32 to be in the second state (a state in which the first wiring 25 and the transmission unit 38 b are connected). (Step S240). As a result, even when an abnormality occurs in the second microcomputer 23, data can be transmitted from the first microcomputer 21 to an external electronic control unit.

  As shown in FIG. 5, when an abnormality (an abnormality in which the dominant continues) occurs in the first wiring 25, the first dominant timeout circuit 27 detects an abnormality in the first wiring 25 (step S300), and the first abnormality is generated. A signal is output to the selector controller 34 (step S310). When the first abnormality signal is input, the selector controller 34 causes the selector 32 to be in the third state (the state in which the second wiring 26 and the transmission unit 38 b are connected). Thus, even when an abnormality occurs in the first wiring 25, data can be transmitted from the second microcomputer 23 to an external electronic control unit.

  As shown in FIG. 6, when an abnormality (an abnormality in which the dominant continues) occurs in the second wiring 26, the second dominant timeout circuit 28 detects an abnormality in the second wiring 26 (step S400), and the second abnormality occurs. A signal is output to the selector controller 34 (step S410). When the second abnormality signal is input, the selector controller 34 causes the selector 32 to be in the second state (a state in which the first wiring 25 and the transmission unit 38 b are connected). As a result, even when an abnormality occurs in the second wiring 26, data can be transmitted from the first microcomputer 21 to an external electronic control unit.

  In the electronic control unit 20 of the embodiment described above, the AND circuit 30 whose input terminal is connected to the first and second microcomputers 21 and 23 via the first and second wires 25 and 26, and the output of the AND circuit 30 The first state connecting the terminal and the transmitter 38b of the transceiver 38, the second state connecting the first wire 25 and the transmitter 38b, and the third state connecting the second wire 26 and the transmitter 38b are switchable. Selector 32 and a selector controller 34 for controlling the selector 32. The selector controller 34 causes the selector 32 to be in the first state when both the first and second microcomputers 21 and 23 as viewed from the AND circuit 30 are normal, and the second microcomputer 23 (the second microcomputer 23 or the second When the second wiring 26) is abnormal, the selector 32 is brought into the second state, and when the first microcomputer 21 (the first microcomputer 21 and the first wiring 25) is abnormal, the selector 32 is brought into the third state. As a result, when the first and second microcomputers 21 and 23 as viewed from the AND circuit 30 are all normal, the first microcomputer 21 performs switching from the first microcomputer 21 as compared to switching between the second state and the third state as needed. And the data from the second microcomputer 23 can be transmitted to the outside while being switched smoothly. In addition, data from the second microcomputer 23 can be transmitted to the outside even when an abnormality occurs in the first microcomputer 21 side, and data from the first microcomputer 21 can be transmitted even when an abnormality occurs in the second microcomputer 23 side. It can be sent to the outside.

  The electronic control unit 20 of the embodiment includes the first and second dominant timeout circuits 27 and 28. However, the first and second dominant timeout circuits 27 and 28 may not be provided. Further, as shown in the electronic control unit 20B of the modified example of FIG. 7, in place of the first and second dominant timeout circuits 27 and 28, first and second communication monitoring units 27B and 28B may be provided. Here, the first and second communication monitoring units 27B and 28B monitor the communication content and communication cycle of the data (communication data) from the first and second microcomputers 21 and 23, and detect an abnormality. The first abnormality signal is output to the selector controller 34.

  The correspondence between the main elements of the embodiment and the main elements of the invention described in the section of "Means for Solving the Problems" will be described. In the embodiment, the first microcomputer 21 corresponds to a "first computer", the second microcomputer 23 corresponds to a "second computer", the AND circuit 30 corresponds to an "AND circuit", and the selector 32 "switching unit The selector controller 34 and the reset controller 36 correspond to the "switching control unit".

  In addition, the correspondence of the main elements of the embodiment and the main elements of the invention described in the section of the means for solving the problem implements the invention described in the column of the means for solving the problem in the example. The present invention is not limited to the elements of the invention described in the section of “Means for Solving the Problems”, as it is an example for specifically explaining the mode for carrying out the invention. That is, the interpretation of the invention described in the section of the means for solving the problem should be made based on the description of the section, and the embodiment is an embodiment of the invention described in the section of the means for solving the problem. It is only a specific example.

  As mentioned above, although the form for implementing this invention was demonstrated using the Example, this invention is not limited at all by these Examples, In the range which does not deviate from the summary of this invention, it becomes various forms Of course it can be implemented.

  The present invention is applicable to the manufacturing industry of control devices and the like.

  DESCRIPTION OF SYMBOLS 10 CAN communication line, 20 electronic control units, 21 1st microcomputer, 22, 24 monitoring part, 23 2nd microcomputer, 25 1st wiring, 26 2nd wiring, 27 1st dominant timeout circuit, 28 2nd dominant timeout circuit, 30 AND circuits, 32 selectors, 34 selector controllers, 36 reset controllers, 38 transceivers, 38a receivers, 38b transmitters.

Claims (1)

A control device comprising a first and a second computer that mutually monitor abnormalities and communicating with the outside,
An AND circuit to which signals from the first and second computers are input;
A first state for transmitting the output of the AND circuit to the outside, a second state for transmitting only the output of the first computer to the outside, and a third state for transmitting only the output of the second computer to the outside And a switching unit capable of switching
When both the first and second computer sides viewed from the AND circuit are normal, the switching unit is made to be in the first state, and when the second computer side is abnormal, the switching unit is in the second state A switching control unit for causing the switching unit to be in the third state when the first computer side is abnormal;
Control device comprising:

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