JP2019117900A - Multilayer electronic component - Google Patents

Abstract

To provide a multilayer electronic component capable of preventing peeling of an underlying electrode layer at a solder bonding temperature of 300°C to 400°C.SOLUTION: A multilayer electronic component includes a ceramic body in which a ceramic layer and an internal electrode layer are alternately laminated, and an external electrode, and the external electrode includes a base electrode layer formed directly on the end face of the ceramic body so as to be electrically connected to at least a part of the internal electrode layer, a first intermediate electrode layer formed on the outer surface of the base electrode layer, a second intermediate electrode layer formed on the outer surface of the first intermediate electrode layer, and an upper electrode layer formed on the outer surface of the second intermediate electrode layer, and the first intermediate electrode layer includes Ni and P, and the second intermediate electrode layer includes Pd, and the upper electrode layer includes Au.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a multilayer electronic component in which external electrodes are formed.

  In recent years, a large number of electronic components such as ceramic electronic components have come to be mounted on a wiring substrate mounted inside an electronic device.

  Conventionally, Pb-containing solders have generally been used for mounting these electronic components on wiring boards, but in recent years electronic components using Sn-Ag-Cu-based solder have been used from the viewpoint of reducing environmental load. The implementation of has been done. Alternatively, mounting of electronic parts has been carried out using a conductive adhesive or the like in which conductive fine particles such as metal fillers are added to a thermosetting resin such as an epoxy-based thermosetting resin.

  However, since inverter circuits using SiC power semiconductors, which are actively researched and developed recently, are expected to have an operating environment exceeding 200 ° C., bonding materials used so far, for example, Sn—Ag -A conductive adhesive containing a filler of Ag in Cu-based solder or epoxy-based thermosetting resin can often not be used from the viewpoint of heat resistance.

  For this reason, high temperature characteristics evaluation of a module that achieves a stable bonding state at 200 ° C. to 250 ° C. is carried out by using a high melting point Au based high temperature solder such as Au-Ge solder or Au-Sn solder. There is.

  In Patent Document 1, an external electrode of a ceramic component compatible with solder, a metal base conductor layer composed of a metal and a glass component, a Ni plating layer formed on the outer surface of the metal base conductor layer, and an outer surface of the Ni plating layer It is described that the Pd plated layer formed in the above is made to be an Au plated upper layer electrode layer formed on the outer surface of the Pd plated layer. Patent Document 1 discloses a technology for providing a high-reliability ceramic electronic component that prevents excessive solder buildup on the external electrode by such a configuration of the external electrode, and does not cause cracks due to unnecessary stress. Have been described.

JP 2003-109838 A

  However, in Patent Document 1, when using Au-based solder at a temperature of 300 ° C. to 400 ° C. during bonding, the thickness of the side of Ni is large, so the problem is that Cu of the base electrode layer is easily peeled off during bonding. there were. Furthermore, when Pd is used as the upper electrode layer, there is a problem that the solder wettability is poor.

  The present invention has been made in view of the above problems, and it is an object of the present invention to provide a laminated electronic component which prevents peeling of a base electrode layer at a solder bonding temperature of 300 ° C. to 400 ° C. and has good solder wettability. It is.

  The present inventors diligently studied to achieve the above object, and completed the present invention.

That is, the multilayer electronic component according to the present invention is a ceramic element in which ceramic layers and internal electrode layers substantially parallel to a plane including the first axis and the second axis are alternately stacked in the direction of the third axis. Body,
And an external electrode formed on a pair of end faces facing each other in the direction of the first axis of the ceramic body.
The external electrode is
An underlying electrode layer formed directly on an end face of the ceramic body so as to be electrically connected to at least a part of the internal electrode layer;
A first intermediate electrode layer formed on the outer surface of the base electrode layer;
A second intermediate electrode layer formed on the outer surface of the first intermediate electrode layer;
An upper electrode layer formed on the outer surface of the second intermediate electrode layer;
The first intermediate electrode layer contains Ni,
The upper electrode layer contains Au,
The external electrode is
An external electrode end face portion covering end faces facing each other in the direction of the first axis of the ceramic body;
An external electrode extension that covers a part of the side surfaces facing each other in the direction of the second axis of the ceramic body and a part of the main surfaces facing each other in the direction of the third axis of the ceramic body; Have
The maximum thickness of the first intermediate electrode layer formed in the external electrode extension portion is T1.
When the maximum thickness of the first intermediate electrode layer formed on the external electrode end face portion is T2,
The relationship between T1 and T2 is 0.75 ≦ T1 / T2 <1.00.
The thickness of the second intermediate electrode layer is 0.15 μm to 1.0 μm,
The multilayer electronic component in which the thickness of the upper layer electrode layer is 30 nm to 80 nm.

  By having the above features, it is possible to provide a laminated electronic component capable of preventing peeling of the base electrode layer at a solder bonding temperature of 300 ° C. to 400 ° C.

  Preferably, the relationship between T1 and T2 of the multilayer electronic component is 0.80 ≦ T1 / T2 ≦ 0.95.

FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the external electrode of the multilayer ceramic capacitor according to one embodiment of the present invention.

  First, a multilayer ceramic capacitor will be described as an embodiment of the present invention. FIG. 1 shows a cross-sectional view of a general laminated ceramic capacitor.

  Multilayer ceramic capacitor 1 has ceramic layer 2 and internal electrode layer 3 substantially parallel to a plane including X axis and Y axis, and ceramic layer 2 and internal electrode layer 3 alternate along the direction of Z axis. The ceramic body 10 is laminated on the

  Here, "substantially parallel" means that most of the portions are parallel but may have portions that are not parallel, and the ceramic layer 2 and the internal electrode layer 3 have some unevenness The idea is that they may or may be inclined.

  The shape of the ceramic body 10 is not particularly limited, but it is preferable that the external dimensions (L0, W, T dimensions) be larger than 3.2 mm × 1.6 mm × 1.6 mm. The larger the outer dimensions, the higher the effect of preventing peeling of the base electrode layer.

  The internal electrode layers 3 are laminated so that each end is alternately exposed on the surfaces of the two opposing end faces of the ceramic body 10. The pair of external electrodes 4 are formed on both end surfaces of the ceramic body 10 and connected to the exposed ends of the alternately arranged internal electrode layers 3 to constitute a capacitor circuit.

  The thickness of the ceramic layer 2 is not particularly limited, but is preferably 100 μm or less, more preferably 30 μm or less per layer. The lower limit of the thickness is not particularly limited, and is, for example, about 0.5 μm.

  The number of laminated layers of the ceramic layer 2 is not particularly limited, but is preferably 20 or more, and more preferably 50 or more.

The material of the ceramic layer 2 is, for example, a dielectric comprising a main component such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ , (K _1-x Na _x ) Sr ₂ Nb ₅ O ₁₅ , Ba ₃ TiNb ₄ O ₁₅ or the like. Body ceramic can be used. Moreover, you may use what added secondary components, such as Mn compound, Mg compound, Cr compound, Co compound, Ni compound, rare earth elements, Si compound, Li compound, etc. to these main components. In addition, piezoelectric ceramic such as PZT ceramic, semiconductor ceramic such as spinel ceramic, magnetic ceramic such as ferrite, etc. can also be used.

  The conductive material contained in the internal electrode layer 3 is not particularly limited, but is preferably Ni, a Ni-based alloy, Cu or a Cu-based alloy. In addition, about 0.1 mass% or less of various trace components, such as P, may be contained in Ni, a Ni-type alloy, Cu, or a Cu-type alloy. Alternatively, the internal electrode layer 3 may be formed using a commercially available electrode paste. The thickness of the internal electrode layer 3 may be appropriately determined according to the application and the like.

  More preferably, the conductive material contained in the internal electrode layer 3 is Ni or a Ni-based alloy because the constituent material of the ceramic layer 2 has reduction resistance. It is more preferable to use this Ni or Ni-based alloy as a main component and to this one or more kinds of internal electrode subcomponents selected from Al, Si, Li, Cr, and Fe.

  By incorporating one or more types of internal electrode subcomponents selected from Al, Si, Li, Cr, and Fe into the Ni or Ni-based alloy that is the main component of the internal electrode layer 3, Ni becomes oxygen in the atmosphere and Before reacting to NiO, the subcomponent for internal electrode and oxygen react to form an oxide film of the subcomponent for internal electrode on the surface of Ni. That is, since it becomes impossible to react with Ni if oxygen in the outside air does not pass through the oxide film of the subcomponent of the internal electrode, Ni becomes difficult to oxidize. As a result, even when continuously used at a high temperature of 250 ° C., the deterioration of the continuity due to the oxidation of the internal electrode layer containing Ni as the main component is unlikely to occur and the conductivity is not likely to occur.

  As shown in FIG. 2, in the external electrode 4 of the present embodiment, the external electrode end face portions 4 a formed on both end surfaces 10 a in the X axis direction of the ceramic element body 10 and both side surfaces in the Y axis direction of the ceramic element body 10 And an external electrode extension 4b that covers both ends in the X-axis direction and both ends in the X-axis direction of both main surfaces of the ceramic body 10 in the Z-axis direction.

  The external electrode 4 of the present embodiment has a base electrode layer 40 formed directly on the end face 10 a of the ceramic body 10 so as to be electrically connected to at least a part of the inner electrode layer 3 and an outer surface of the base electrode layer 40. A second intermediate electrode layer 42 formed on the outer surface of the first intermediate electrode layer 41, and an upper electrode layer 43 formed on the outer surface of the second intermediate electrode layer 42; Have.

  Although one external electrode 4 is shown in FIG. 2, the other external electrode also has a similar configuration.

  Base electrode layer 40 contains a glass component and a metal component. As a metal used for base metal layer 40, Cu, Ag, Pd, an Ag-Pd alloy, Au etc. can be used, for example.

  The thickness of the base electrode layer 40 is preferably 5 μm to 25 μm on the lower surface side (for example, the main surface side of the ceramic body 10) at the time of mounting.

  The first intermediate electrode layer 41 contains Ni, and is preferably formed by Ni plating. Even if the second electrode layer 42 formed on the first intermediate electrode layer 41 is immersed in the Pd plating bath by forming Ni plating, the base electrode layer 40 is formed in the Pd plating bath for the second electrode layer 42. It is possible not to blend in. The first intermediate electrode layer 41 may include P, B, and the like.

  Further, by forming Ni plating as the first intermediate electrode layer 41, it is possible to cover poor plating portions such as uneven portions of the surface of the base electrode layer 40 and segregation portions of the glass component, and the surface is smoothed. Can be For this reason, it becomes possible to improve the winding of the second electrode layer 42.

  Assuming that the maximum thickness of the first intermediate electrode layer 41b formed in the external electrode extension portion 4b is T1, and the maximum thickness of the first intermediate electrode layer 41a formed in the external electrode end face portion 4a is T2, The relationship is 0.75 ≦ T1 / T2 <1.00. Thereby, the stress concerning base electrode layer 40 can be reduced. Therefore, it is possible to prevent the peeling failure of the base electrode layer 40 of the multilayer ceramic capacitor 1 at 300 ° C. or higher. Therefore, when the multilayer ceramic capacitor 1 is mounted on the wiring substrate by Au-based solder, it is possible to obtain the multilayer ceramic capacitor 1 in which the occurrence of connection failure is difficult.

  The portion of the maximum thickness (T1) of the first intermediate electrode layer 41b formed in the external electrode extension portion 4b may be the central portion of the external electrode extension portion 4b shown as 1/2 L in FIG. It is good.

  The portion of the maximum thickness (T2) of the first intermediate electrode layer 41a formed on the external electrode end face portion 4a may be the central portion of the external electrode end face portion 4a or may be off.

  Note that, as shown in FIG. 2, the first intermediate electrode layer 41b of the external electrode extension portion continues continuously to the end of the central portion of the external electrode extension portion 4b along the X-axis direction.

  The thickness of the first intermediate electrode layer 41a formed on the external electrode end face portion 4a is preferably 5 μm to 20 μm. Moreover, it is preferable that the thickness of the 1st intermediate electrode layer 41b formed in the external electrode extension part 4b is 3-15 micrometers.

  The second intermediate electrode layer 42 contains Pd and is preferably formed by Pd plating. Oxidation and diffusion of the first intermediate electrode layer can be suppressed by forming Pd plating.

  The thickness of the second intermediate electrode layer 42 is 0.15 μm to 1.0 μm. Thereby, oxidation and diffusion of the first intermediate electrode layer can be suppressed. From the above viewpoint, the thickness of the second intermediate electrode layer 42 is preferably 0.30 μm to 1.00 μm, and more preferably 0.30 μm to 0.50 μm.

  The upper electrode layer 43 contains Au and is preferably formed by Au plating. When the upper layer electrode layer 43 is the outermost layer of the external electrode 4, by forming the outermost layer of the external electrode 4 by Au plating, the reliability of the electrical connection with the Au-based solder material for mounting on the wiring substrate is improved. It can be secured. When a base metal such as Sn is used for plating the upper electrode layer 43, it is difficult to obtain bonding reliability due to the problem of galvanic corrosion and oxidation.

  The thickness of the upper electrode layer 43 is 30 nm to 80 nm. This can improve the wettability with the solder. From the above viewpoint, the thickness of the upper electrode layer 43 is preferably 50 nm to 80 nm.

  In the multilayer ceramic capacitor 1 of the present embodiment, the thickness T1 of the intermediate electrode layer 41a formed in the external electrode extension portion 4b is smaller than the thickness T2 of the intermediate electrode layer 41b formed in the external electrode end surface portion 4a. The thickness of the external electrode 4 on the substrate mounting surface can be reduced.

  Further, by setting the ratio of the thickness T1 of the intermediate electrode layer 41b of the external electrode extension portion 4b to the thickness T2 of the intermediate electrode layer 41a of the external electrode end face portion 4a within a predetermined range, the ceramic element due to the stress of the external electrode 4 The occurrence of cracks in the body 10 can be suppressed. Therefore, it is possible to obtain a laminated electronic component that is unlikely to cause a short circuit failure.

  Further, in the laminated ceramic capacitor 1 of the present embodiment, the stress applied to the base electrode layer 40 can be reduced at a bonding temperature of 300 ° C. to 400 ° C., and peeling of the base electrode layer 40 can be prevented. Therefore, when the multilayer ceramic capacitor 1 is mounted on the wiring board by Au-based solder, connection failure hardly occurs.

  For this reason, the multilayer ceramic capacitor 1 of the present embodiment is required to be used for electronic components for automotive applications where use in a low temperature range of -55 ° C to about 150 ° C is required, and further to a high temperature of about 250 ° C. It can be used as a snubber capacitor for power devices using a SiC or GaN-based semiconductor, a capacitor used for removing noise in an engine room of a car, or the like.

  Next, an example of a method of manufacturing the multilayer ceramic capacitor 1 shown in FIG. 1 will be described.

  In order to manufacture the multilayer ceramic capacitor 1 as shown in FIG. 1, a ceramic green sheet containing a ceramic material for forming the ceramic body 10 is prepared.

As the ceramic material, ceramic materials composed mainly of BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ , (K _1-x Na _x ) Sr ₂ Nb ₅ O ₁₅ , Ba ₃ TiNb ₄ O ₁₅ or the like may be used. it can.

  Next, a conductive paste is applied on the ceramic green sheet to form a conductive pattern corresponding to the internal electrode layer 3. The application of the conductive paste can be performed by, for example, various printing methods such as screen printing. The conductive paste may contain known binders and solvents in addition to the conductive particles. As the conductive fine particles, Ni, Ni-based alloy, Cu or Cu-based alloy can be used.

  A plurality of ceramic green sheets not having a conductive pattern formed thereon, a ceramic green sheet having a conductive pattern formed thereon, and a plurality of ceramic green sheets not having a conductive pattern formed thereon are laminated in this order and pressed in the laminating direction. , And a mother laminate is produced.

  A plurality of green ceramic bodies are produced by cutting the mother laminate along virtual cut lines on the mother laminate. The cutting of the mother laminate can be performed by dicing or die cutting. Furthermore, barrel grinding etc. may be performed with respect to a green ceramic body, and a ridgeline part and a corner part may be rounded.

  The ceramic body 10 is obtained by firing the green semimic body. The firing temperature at this time can be, for example, 1100 ° C. to 1400 ° C.

  A metal paste is applied by a method such as dipping or printing method so as to cover both main surfaces and both side surfaces of ceramic body 10 from both end faces of ceramic body 10 after firing, and base electrode layer 40 is formed by baking. Is formed. It is preferable that the baking temperature of a metal paste is 700-900 degreeC.

  The first intermediate electrode layer 41 is formed on the base electrode layer 40. The method of forming the first intermediate electrode layer 41 is not particularly limited, and is formed by barrel plating or the like.

  Hereinafter, a method of forming the first intermediate electrode layer 41 by barrel plating will be described.

  The filling amount of the ceramic body 10 is 40% or less of the total amount of the ceramic body 10 to be filled and the metal medium, and the filling is 1/3 or less of the barrel container. Thus, the thickness of the first intermediate electrode layer 41b of the external electrode extension 4b can be reduced by reducing the filling amount of the ceramic body 10 in the barrel container. A base electrode layer 40 is formed on the ceramic body 10 at this time.

  In this state, when the barrel container is rotated at a medium speed of 20 rpm or more, the probability of plating in parallel in the X axis direction of the ceramic body 10 in the barrel decreases, and the main surface of the ceramic body 10 and The amount of plating adhesion on the side surface is reduced. Therefore, the thickness of the first intermediate electrode layer 41b of the external electrode extension 4b with respect to the first intermediate electrode layer 41a of the external electrode end face portion 4a can be reduced.

  Furthermore, the second intermediate electrode layer 42 is formed on the first intermediate electrode layer 41. The method of forming the second intermediate electrode layer 41 is not particularly limited, and is formed by electrolytic plating or the like.

  Furthermore, the upper electrode layer 43 is formed on the second intermediate electrode layer 42, whereby the multilayer ceramic capacitor 1 is manufactured. The method for forming the upper electrode layer 43 is not particularly limited. . In the present embodiment, since Au plating is used as the upper electrode layer 43 of the external electrode 4, a good bond is formed with the Au-based solder.

    Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments in any way, and various modifications can be made without departing from the scope of the present invention.

  The multilayer electronic component of the present invention is applicable not only to multilayer ceramic capacitors but also to other multilayer electronic components. Other multilayer electronic components are all electronic components in which a ceramic layer is stacked via an internal electrode layer. For example, a band pass filter, an inductor, a multilayer three terminal filter, a piezoelectric element, a PTC thermistor, an NTC thermistor, a varistor Etc.

    Hereinafter, the present invention will be described in more detail by way of examples of the present invention, but the present invention is not limited to these examples.

As a ceramic body 10 for a multilayer ceramic capacitor, it has a ceramic layer 2 mainly composed of CaZrO ₃ or an inner electrode layer 3 containing Ni, and a chip size L0 × W × T = 1.6 mm × 0. Ceramic body of 8 mm x 0.8 mm, Chip size L0 x W x T = 3.2 mm x 1.6 mm x 1.6 mm Ceramic body, Chip size L0 x W x T = 4.5 mm x 3.2 mm x A ceramic body 10 for four kinds of multilayer ceramic capacitors of different chip sizes of a 2.0 mm ceramic body and a chip size L0 × W × T = 5.7 mm × 5.0 mm × 2.0 mm ceramic body Got ready. The chip size of each capacitor sample is as shown in Tables 1 and 2.

  The base electrode layer 40 was formed by applying and baking a metal paste containing Cu so as to apply to both main surfaces and both side surfaces of the ceramic element 10 from both end surfaces of the ceramic element 10 after firing. The baking temperature of the metal paste was 700 ° C to 900 ° C.

  The thickness of the base electrode layer 40 was 20 μm to 30 μm in the central portion of the external electrode end face portion 4a, and 5 μm to 10 μm in the external electrode extension portion 4b.

  Next, an intermediate electrode layer 41 which is a Ni plating layer was formed by barrel plating with a media size: φ1.0 mm and a plating time of 30 to 60 minutes using a watt bath. The thickness of the intermediate electrode layer 41 was 5 μm at the central portion of the external electrode end face portion 4 b.

  Next, as a second intermediate electrode layer 42, a Pd plating layer was formed with a media size of φ 1.0 mm and a plating time of 10 to 20 minutes using a Pd bath for electrolytic plating.

  Next, an Au plating layer was formed as the upper electrode layer 43 by electroless plating.

  As shown in Tables 1 and 2, a capacitor sample (multilayer ceramic capacitor 1) was produced in which the chip size of the ceramic body, T1 / T2, the thickness of the second intermediate electrode layer, and the thickness of the upper electrode layer were changed.

Each capacitor sample, the first containing the Cu, were implemented using Au-Ge solder on the wiring substrate in which the second land is made of Si ₃ N ₄ formed on the upper surface. As the Au-Ge solder, an Au-Ge solder containing 12 wt% Ge was used. Au-Ge solder was applied onto the first and second lands, and then each capacitor sample was taken and heated at a temperature of 400 ° C. for 30 minutes to mount the capacitor sample on the wiring substrate.

  Each of the capacitor samples in Tables 1 and 2 was polished along the Y-axis direction of the sample, parallel to the ZX plane, and to the central portion in the Y-axis direction of the capacitor samples.

  Next, of the first intermediate electrode layer 41b formed on the external electrode extension 4b of the external electrode 4 on one side in the cross section, the central portion of the length L along the X axis of the external electrode extension 4b on the mounting surface side The thickness (T1) (maximum thickness) at 1/2 L was measured by an optical microscope. Further, the thickness (T2) (maximum thickness) of the center portion of the external electrode end face portion 4a in the first intermediate electrode layer 41a formed on the external electrode end face portion 4a was measured by an optical microscope. The ratio of these T1 and T2 was calculated. In the same cross section, the thicknesses of the second intermediate electrode layer and the upper electrode layer were measured in the same manner as in T1 and T2. The results are shown in Tables 1 and 2.

<Base electrode peeling>
About the capacitor | condenser sample of Table 1 and Table 2, base electrode peeling was confirmed. Specifically, 100 samples were subjected to resin filling and polishing, and samples having peeling at the interface between the base electrode and the first intermediate electrode layer were judged to be defective, and the number thereof was examined. The results are shown in Tables 1 and 2.

<Solder wettability>
The solder wettability of each of the capacitor samples in Tables 1 and 2 was confirmed. Specifically, 100 samples were immersed in the solder, and when 80% or more of the surface was covered with the solder, it was evaluated as ○, and otherwise, it was evaluated as ×. The results are shown in Tables 1 and 2.

<Thermal shock test (Thermal shock cycle test)>
As a thermal shock cycle test, the cycle of holding the air tank at 55 ° C. for 30 minutes and repeating the air tank holding at 200 ° C. for 30 minutes is repeated 2000 cycles, the air tank at 55 ° C. for 30 minutes and the air tank at 250 ° C. Twenty capacitor samples were prepared in which 2000 cycles of 30 minutes of repetition were performed. The thermal shock cycle test was conducted in a state where the capacitor sample was mounted on the wiring board.

  After the thermal shock cycle test, the capacitor sample was polished to the center of the capacitor sample in the Y-axis direction in a direction perpendicular to the substrate mounting surface and along the Y-axis direction of the capacitor sample and parallel to the ZX plane. .

  Next, the polished surface is observed at a magnification of 100 to 500 times with a metallographic microscope to confirm the presence or absence of a crack extending from the edge of the boundary between the external electrode end face 4a and the external electrode extension 4b to the ceramic body did. The results are shown in Tables 1 and 2.

  In the thermal shock cycle test at −55 ° C. to 200 ° C., it was judged as good that the crack generation rate was 0% after 2000 cycles.

  In the thermal shock cycle test at −55 ° C. to 250 ° C., it was judged that the crack generation rate is 20% or less after 2000 cycles.

  From Table 1 and Table 2, when the relationship of T1 and T2 satisfy | fills 0.75 <= T1 / T2 <1.00 (sample number 3-8, 12-15, 18-20, 23-25, 27-34) As compared with the case where the relationship between T1 and T2 does not satisfy 0.75 ≦ T1 / T2 <1.00 (sample numbers 1, 2, 9, 22 and 26), the number of defects in base electrode peeling is better. It was confirmed (less).

  From Tables 1 and 2, when the thickness of the second intermediate electrode layer is 0.15 μm to 1.0 μm (sample numbers 3 to 8, 12 to 15, 18 to 20, 23 to 25, 27 to 34), It was confirmed that the defect rate in the thermal shock test is better (less) than in the case where the thickness of the second intermediate electrode layer is less than 0.15 (Sample Nos. 10 and 11).

  From Table 1 and Table 2, when the thickness of the upper layer electrode layer is 30 nm to 80 nm (sample numbers 3 to 8, 12 to 15, 18 to 20, 23 to 25, 27 to 34), the thickness of the upper layer electrode layer is 30 nm In the case of less than (Sample Nos. 16 and 17), it can be confirmed that the solder wettability is better.

  From Table 1 and Table 2, when the thickness of the upper layer electrode layer is 30 nm to 80 nm (sample numbers 3 to 8, 12 to 15, 18 to 20, 23 to 25, 27 to 34), the thickness of the upper layer electrode layer is 80 nm It was confirmed that the defect rate of the thermal shock test is better (less) than the thicker case (Sample No. 21).

DESCRIPTION OF SYMBOLS 1 ... laminated ceramic capacitor 2 ... ceramic layer 3 ... internal electrode layer 4 ... external electrode 4a ... external electrode end face portion 4b ... external electrode extension portion 40 ... base electrode layer 41 ... first intermediate electrode layer 41a ... third of external electrode end surface portion 1 middle electrode layer 41b ... 1st middle electrode layer of external electrode extension part 42 ... 2nd middle electrode layer 43 ... top layer electrode layer 10 ... ceramic body

Claims (2)

A ceramic body in which a ceramic layer substantially parallel to a plane including the first axis and the second axis and an internal electrode layer are alternately stacked along the direction of the third axis;
And an external electrode formed on a pair of end faces facing each other in the direction of the first axis of the ceramic body.
The external electrode is
An underlying electrode layer formed directly on an end face of the ceramic body so as to be electrically connected to at least a part of the internal electrode layer;
A first intermediate electrode layer formed on the outer surface of the base electrode layer;
A second intermediate electrode layer formed on the outer surface of the first intermediate electrode layer;
An upper electrode layer formed on the outer surface of the second intermediate electrode layer;
The first intermediate electrode layer comprises Ni and P,
The second intermediate electrode layer contains Pd,
The upper electrode layer contains Au,
The external electrode is
An external electrode end face portion covering end faces facing each other in the direction of the first axis of the ceramic body;
An external electrode extension that covers a part of the side surfaces facing each other in the direction of the second axis of the ceramic body and a part of the main surfaces facing each other in the direction of the third axis of the ceramic body; Have
The maximum thickness of the first intermediate electrode layer formed in the external electrode extension portion is T1.
When the maximum thickness of the first intermediate electrode layer formed on the external electrode end face portion is T2,
The relationship between T1 and T2 is 0.75 ≦ T1 / T2 <1.00.
The thickness of the second intermediate electrode layer is 0.15 μm to 1.0 μm,
The multilayer electronic component in which the thickness of the upper layer electrode layer is 30 nm to 80 nm.   The laminated electronic component according to claim 1, wherein the relationship between T1 and T2 is 0.80 ≦ T1 / T2 ≦ 0.95.

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