JP2019117835A - Display device - Google Patents

Abstract

To provide a display device with reduced display unevenness.SOLUTION: A display device includes a substrate, a light emitting element, a first transistor in which one of a source and a drain is electrically connected to the light emitting element and the other one is connected to a drive power supply line, and a second transistor in which one of a source and a drain is connected to the gate of the first transistor, and the first transistor includes a first insulating layer on the substrate, a second insulating layer disposed on the first insulating layer and thinner than the first insulating layer, a first semiconductor layer between the first insulating layer and the second insulating layer, a first gate electrode disposed between the substrate and the first insulating layer and having a region overlapping the first semiconductor layer, and a first control electrode disposed on the second insulating layer and having a region overlapping the first semiconductor layer.SELECTED DRAWING: Figure 3

Description

  One embodiment of the present invention relates to a display device. In particular, it relates to the configuration of the pixels of the display device.

  Organic electroluminescent (hereinafter referred to as organic EL) display devices are actively studied from the viewpoints of high viewing angle, high-speed response, and advantages that can be used as sheet displays. In the organic EL display device, a light emitting element is provided in each pixel, and an image is displayed by individually controlling light emission. The light emitting element has a structure in which a layer containing an organic EL material (hereinafter, also referred to as a “light emitting layer”) is interposed between a pair of electrodes, one of which is distinguished as an anode and the other of which is a cathode. Electrons are injected from the cathode into the light emitting layer, and when holes are injected from the anode, the electrons and holes recombine. The light emitting molecule in the light emitting layer is excited by the excess energy released by this, and then light is emitted by de-excitation.

  Since the organic EL display device is driven by current, thin film transistors used in the array substrate require at least two types of transistors for current control in addition to selection transistors for writing.

  Since the current flowing through the source and drain of the transistor affects the luminance of the organic EL element, the threshold voltage Vth and the mobility of the transistor greatly affect the light emission of the organic EL. Therefore, if the characteristics of the transistors vary in the substrate plane, the current value output when an arbitrary signal voltage is input fluctuates with each transistor, causing uneven light emission of the organic EL element. As a result, display unevenness occurs on the display device.

  In order to take advantage of the high speed response characteristic of the organic EL element, it is preferable that the selection transistor has a small S value. On the other hand, in order to suppress variations in current due to variations in transistor characteristics, it is preferable that the drive transistor has a large subthreshold swing value (hereinafter referred to as S value).

  Patent Document 1 describes an organic EL display device in which the variation in light emission luminance is reduced between pixels while the switching characteristic is maintained by adjusting the S value by optimizing the film thickness of the semiconductor layer of the transistor. It is disclosed.

JP 2000-307119 A

  In the transistor of Patent Document 1, since the structures of the selection transistor and the drive transistor are the same, the characteristics required for each transistor can not be fully utilized. In order to fully utilize the characteristics required for the selection transistor and the drive transistor, it is preferable to provide a plurality of transistors having a structure according to the characteristics required for one pixel. However, it is difficult to provide a plurality of transistors having a structure according to the characteristics required in one pixel.

  In view of the above problems, it is an object to provide a display device in which display unevenness is reduced by providing a transistor having a plurality of structures in one pixel.

  In a display device according to an embodiment of the present invention, a first transistor in which one of a substrate, a light emitting element, and a source and a drain is electrically connected to the light emitting element and the other of the source and the drain is connected to a driving power supply line And a second transistor in which one of the source and the drain is connected to the gate of the first transistor, the first transistor being disposed on the first insulating layer on the substrate and the first insulating layer, A second insulating layer thinner than the insulating layer, a first semiconductor layer between the first insulating layer and the second insulating layer, and a portion between the substrate and the first insulating layer overlapping the first semiconductor layer A second gate electrode having a region, and a first control electrode disposed on the second insulating layer and having a region overlapping the first semiconductor layer, wherein the second transistor includes a first insulating layer, a second insulating layer, and Between the second semiconductor layer and the second insulating layer, It includes a second gate electrode which has a region overlapping with the second semiconductor layer, and a second control electrode having a substrate and a region overlapping with the first semiconductor layer is disposed between the first insulating layer.

It is a top view explaining the composition of the display concerning one embodiment of the present invention. It is a circuit diagram of a pixel of a display concerning one embodiment of the present invention. It is a top view explaining the composition of the pixel of the display concerning one embodiment of the present invention. It is a top view explaining the composition of the pixel of the display concerning one embodiment of the present invention. It is a sectional view explaining the composition of the pixel of the display concerning one embodiment of the present invention. It is a sectional view explaining the composition of the pixel of the display concerning one embodiment of the present invention. It is a top view explaining the composition of the pixel of the display concerning one embodiment of the present invention. It is a sectional view explaining the composition of the pixel of the display concerning one embodiment of the present invention. It is a sectional view explaining the composition of the display concerning one embodiment of the present invention. It is a sectional view explaining the composition of the transistor concerning one example of the present invention. It is an Id-Vg curve of a transistor concerning one example of the present invention. It is an Id-Vg curve of a transistor concerning one example of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in many different modes, and is not construed as being limited to the description of the embodiments exemplified below. In addition, the drawings may be schematically represented as to the width, thickness, shape, etc. of each portion in comparison with the actual embodiment in order to clarify the description, but this is merely an example, and the interpretation of the present invention is not limited. It is not limited. In the specification and the drawings, the same elements as those described above with reference to the drawings already described may be denoted by the same reference numerals, and the detailed description may be appropriately omitted.

First Embodiment
The display device according to the present embodiment will be described with reference to FIGS. 1 to 5.

[Display device configuration]
FIG. 1 is a plan view showing the configuration of the display device according to the present embodiment. The display device 100 includes a substrate 101, a display area 103, and a peripheral area 110.

  The display area 103 is provided on the substrate 101. The display area 103 includes a plurality of pixels 109. The plurality of pixels 109 are arranged in a matrix. The arrangement number of the plurality of pixels 109 is arbitrary. For example, m pixels in the row direction and n pixels 109 in the column direction are arranged (m and n are integers). Although not illustrated in FIG. 1, each of the plurality of pixels 109 includes a pixel circuit including at least a selection transistor, a driving transistor, and a light emitting element.

  The peripheral area 110 is provided to surround the display area 103. The peripheral area 110 is an area from the display area 103 to the end of the substrate 101. In other words, the peripheral area 110 is an area other than the area on which the display area 103 is provided on the substrate 101 (that is, the area outside the display area 103). The peripheral region 110 includes a drive circuit 104 and a terminal 107. The drive circuit 104 is provided to sandwich the display area 103. Also, in the peripheral area 110, a driver IC 106 may be provided. The driver IC 106 is connected to the terminal 107. The terminal 107 is connected to the flexible printed circuit board 108 (FPC).

  The driver circuit 104 is connected to the scan line 111 connected to the pixel 109 and functions as a scan line driver circuit. In addition, the driver IC 106 is connected to the signal line 112 connected to the pixel 109, and incorporates a signal line drive circuit. Although FIG. 1 shows an example in which the driver IC 106 incorporates the signal line drive circuit, the signal line drive circuit may be provided on the substrate 101 separately from the driver IC 106.

  The driver IC 106 may be disposed on the substrate 101 in the form of an IC chip. Further, although not shown, the driver IC 106 may be provided on the flexible printed circuit board 108.

  A video signal is given to each pixel 109 from the driver IC 106 through the signal line 112. Further, each pixel 109 is supplied with a signal for selecting each pixel 109 from the driver IC 106 through the driving circuit 104 and the scanning line. With these signals, a transistor included in the pixel 109 can be driven to perform screen display in accordance with the video signal.

[Pixel circuit]
FIG. 2 shows a pixel circuit included in each of the plurality of pixels 109 of the display device 100 according to the present embodiment.

  Each of the plurality of pixels 109 includes at least a transistor 210, a transistor 220, a capacitor 230, and a light emitting element 240.

  The transistor 210 functions as a selection transistor. That is, the transistor 210 controls the conduction state with the gate of the transistor 210 by the scan line 111. The transistor 210 has a gate connected to the scan line 111, a source connected to the signal line 112, a drain connected to the gate of the transistor 220, and a back gate connected to a threshold voltage control line 113 that controls threshold voltage. .

  The transistor 220 functions as a drive transistor. That is, they are transistors which are connected to the light emitting element 240 and control the emission luminance of the light emitting element 240. In the transistor 220, the gate is connected to the source of the transistor 210, the source is connected to the driving power supply line 114, the drain is connected to the anode of the light emitting element 240, and the back gate is connected to the threshold voltage control line 115 controlling threshold voltage. Be done.

  In the capacitor 230, one of the capacitor electrodes is connected to the gate of the transistor 220 and to the drain of the transistor 220.

  The light emitting element 240 has an anode connected to the drain of the transistor 220 and a cathode connected to the reference power supply line 116.

  In order to take advantage of the high speed response characteristic of the organic EL element, it is preferable that the transistor 210 functioning as a selection transistor has a small S value. On the other hand, it is preferable that the transistor 220 functioning as a driving transistor has a large S value in order to suppress the variation in current due to the variation in transistor characteristics.

  Therefore, it is preferable to provide a plurality of transistors having a structure in accordance with the characteristics required in one pixel. However, it is difficult to provide a plurality of transistors having a structure according to the characteristics required in one pixel.

  Therefore, in the present embodiment, electrodes are formed above and below the semiconductor layer, and the film thickness of the gate insulating film between the upper electrode and the semiconductor layer and the film of the gate insulating film between the lower electrode and the semiconductor layer Form transistors with different thicknesses. Then, by making the film thickness of the gate insulating film of the driving transistor thicker than that of the selecting transistor, two kinds of transistors with different S values can be provided in one pixel.

[Pixel structure]
The pixel structure of the display device 100 shown in FIG. 1 will be described with reference to FIGS. 3 to 5B. FIG. 3 is a diagram for explaining three pixels 109R, 109G, and 109B arranged in the display device 100 shown in FIG. FIG. 4 is an enlarged view of the pixel 109R shown in FIG. 5A is a cross-sectional view of the pixel 109R shown in FIG. 4 taken along line A1-A2. FIG. 5B is a cross-sectional view of the pixel 109R shown in FIG. 4 taken along line B1-B2. is there. Note that FIG. 3 and FIG. 4 show the conductive layer and the semiconductor layer that constitute the pixels 109R, 109G, and 109B, and the insulating film is not shown.

  The pixels 109R, 109G, and 109B emit different colors, for example, the pixel 109R emits red, the pixel 109G emits green, and the pixel 109B emits blue. Each of the pixels 109R, 109G, and 109B includes a transistor 210, a transistor 220, a capacitor 230, and a light emitting element (not shown). Further, in the pixels 109R, 109G, and 109B, the wiring layers 211 to 217 and the conductive layer 219 are provided.

  In FIGS. 3 and 4, semiconductor layers 221 and 222 are provided over the wiring layer 211, the wiring layer 212, and the wiring layer 217. Further, wiring layers 213 and 214 and a conductive layer 218 are provided over the semiconductor layers 221 and 222. Further, wiring layers 215 and 216 and a conductive layer 219 are provided over the wiring layers 213 and 214 and the conductive layer 218.

  As shown in FIG. 5B, the wiring layer 211 is connected to the conductive layer 265 through the opening 264, and the conductive layer 265 is connected to the conductive layer 248 and the semiconductor layer 221 through the opening 231. As illustrated in FIG. 5B, by arranging the semiconductor layer 221, the conductive layer 265, and the conductive layer 248, the conductive layer 248 can be connected to the semiconductor layer 221 and the conductive layer 265 through one opening 264. . Further, as shown in FIG. 4, the wiring layer 217 is connected to the conductive layer 267 through the opening 266, and the conductive layer 267 is connected to the conductive layer 249 and the semiconductor layer 222 through the opening 233. The wiring layer 217 is also connected to the conductive layer 218 through the opening 235. Further, the wiring layer 211 is connected to the wiring layer 215 through the opening 236. Note that the conductive layer 219 is connected to the pixel electrode of the light emitting element through the opening 237 of the planarization film provided over the conductive layer 219.

  In FIGS. 3 to 5B, the wiring layer 214 functions as the scan line 111, the wiring layer 216 functions as the signal line 112, and the wiring layer 212 functions as the threshold voltage control line 113 of the transistor 210. The wiring layer 215 functions as a drive power supply line 114. The wiring layer 215 is connected to the wiring layer 211 and supplies power to the transistors 220 of the pixels 109R, 109G, and 109B. The wiring layer 213 also functions as the threshold voltage control line 115 of the transistor 220.

  The transistor 210 illustrated in FIG. 4 overlaps the wiring layer 214 and the wiring layer 217 on the substrate 101, the gate insulating film 241 on the wiring layer 212 and the wiring layer 217, and the gate insulating film 241, A semiconductor layer 222 connected to the layer 217, a semiconductor layer 221 over the semiconductor layer 222, and a wiring layer 212 overlapping with the semiconductor layer 222 over the semiconductor layer 221 are included.

  The transistor 220 illustrated in FIG. 4 overlaps with the wiring layer 217 over the wiring layers 211 and 217 of the substrate 101, the gate insulating film 241 over the wiring layers 211 and 217, and the gate insulating film 241, and is connected to the wiring layer 211. And a wiring layer 213 which overlaps with the semiconductor layer 221 over the semiconductor layer 221.

  FIG. 5A is a cross-sectional view of the transistor 210 and the transistor 220. As the transistors 210 and 220, n-channel transistors are illustrated.

  The transistor 210 shown in FIG. 5A has a top gate structure. The wiring layer 214 functions as a gate electrode. The wiring layer 216 is connected to one of the source electrode and the drain electrode, and the wiring layer 217 is connected to the other of the source electrode or the drain electrode. In the wiring layer 212, a region overlapping with the semiconductor layer 222 functions as a control electrode. In the semiconductor layer 222, a region overlapping with the wiring layer 214 is a channel 222a, a region connected to the wiring layers 216 and 217 is a high concentration impurity region 222b, and provided between the channel 222a and the high concentration impurity region 222b. The region is the low concentration impurity region 222c.

  The transistor 220 shown in FIG. 5A has a bottom gate structure. The conductive layer 217 functions as a gate electrode. In the semiconductor layer 221, a region overlapping with the wiring layer 217 functions as a channel. The wiring layer 211 is connected to one of the source electrode and the drain electrode. The conductive layer 219 is connected to the other of the source electrode and the drain electrode. Further, in the wiring layer 213, a region overlapping with the semiconductor layer 221 functions as a control electrode. In the semiconductor layer 221, a region overlapping with the wiring layer 213 is a channel 221a, a region connected to the wiring layers 211 and 217 is a high concentration impurity region 221b, and provided between the channel 222a and the high concentration impurity region 221b. The region is the low concentration impurity region 221c.

  An interlayer insulating layer 243 is provided over the wiring layers 213 and 214 and the conductive layer 218. A wiring layer 216 and a conductive layer 219 are provided over the interlayer insulating layer 243. The wiring layer 215 functioning as a driving power supply line is connected to the semiconductor layer 221 through the wiring layer 211. The wiring layer 216 is connected to the semiconductor layer 222 through the opening 234. In addition, the conductive layer 219 is connected to the semiconductor layer 221 through the opening 232. A planarization film 244 is provided over the interlayer insulating layer 243, the wiring layer 216, and the conductive layer 219. Note that the opening 237 shown in FIGS. 3 and 4 is an opening of the planarization film 244, the conductive layer 219 is connected to the semiconductor layer 221, and the light emitting element 240 is connected through the opening 237 of the planarization film 244. Connected with (not shown).

  A capacitor 230 is formed by the conductive layer 218 provided over the gate insulating film 242, the interlayer insulating layer 243, and the conductive layer 219. The conductive layer 218 and the conductive layer 219 function as a capacitor electrode of the capacitor 230.

  In FIG. 5A, the thickness of the gate insulating film 241 of the driving transistor 220 is larger than the thickness of the gate insulating film 242 of the selecting transistor 210. Accordingly, the S value of the driving transistor 220 can be larger than the S value of the selection transistor 210. Therefore, two kinds of transistors having different S values can be provided in one pixel.

  Therefore, since the selection transistor 210 can reduce the S value, high-speed response can be improved. Further, since the S value of the driving transistor 220 can be increased, variation in threshold voltage of the driving transistor in the substrate surface can be reduced. Thus, the variation in the current value output when the input voltage is applied is also reduced, so that the light emission unevenness of the light emitting element can be reduced. Therefore, display unevenness of the display device can be reduced.

  In the case of making the gate insulating film different in film thickness with a transistor having the same structure, the gate insulating film is formed and then partially removed by etching, or after the gate insulating film is formed, In addition, it is necessary to further form a gate insulating film. In this embodiment, by using the top gate transistor and the bottom gate transistor, gate insulating films having different film thicknesses can be easily formed.

  Further, the wiring layer 213 functioning as a control electrode can be formed simultaneously with the formation of the wiring layer 214, and the wiring layer 212 functioning as a control electrode can be formed simultaneously with the wiring layer 217. As a result, two types of transistors, top gate transistor and bottom gate transistor, can be easily formed without increasing the process even if the area is as small as one pixel.

  In addition, by applying an arbitrary voltage to the wiring layer 212 and the wiring layer 213, the threshold voltage of the transistor 210 and the transistor 220 can be controlled.

  In the present embodiment, an example in which the transistor 210 functioning as a selection transistor has a top gate structure and the transistor 220 functioning as a driving transistor has a bottom gate structure has been described. However, one embodiment of the present invention is limited thereto I will not. The transistor 210 functioning as a selection transistor may have a bottom gate structure, and the transistor 220 functioning as a driving transistor may have a top gate structure. Even in this case, the thickness of the transistor 220 is preferably larger than that of the transistor 210.

  Further, although an example in which n-channel transistors are used as the transistors 210 and 220 has been described, one embodiment of the present invention is not limited to this. As the transistors 210 and 220, p-channel transistors may be used.

Second Embodiment
In the present embodiment, a pixel structure which is partially different from the pixel structure shown in the first embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 is an enlarged view of the pixel 109R. FIG. 7 is a cross-sectional view of the pixel 109R shown in FIG. 6 taken along the line C1-C2.

  The pixel 109R illustrated in FIG. 6 further includes wiring layers 248 and 249 provided in the same layer as the wiring layers 215 and 216. The wiring layer 248 is connected to the wiring layer 211 through the opening 238, and is connected to the semiconductor layer 221 through the opening 239. The conductive layer 216 is connected to the semiconductor layer 221 through the wiring layer 211 and the wiring layer 248. The wiring layer 249 is connected to the wiring layer 217 through the opening 261, and is connected to the semiconductor layer 221 through the opening 262. The wiring layer 249 is connected to the conductive layer 218 through the opening 263. That is, the wiring layer 217 is connected to the semiconductor layer 222 through the wiring layer 249.

  With the configuration shown in FIGS. 6 and 7, it is not necessary to connect the semiconductor layer 221 and the semiconductor layer 222 formed over the gate insulating film 241 with the wiring layers 211 and 217 in the lower layer.

  In FIG. 6, the thickness of the gate insulating film 241 of the driving transistor 220 is larger than the thickness of the gate insulating film 242 of the selection transistor 210. Accordingly, the S value of the driving transistor 220 can be larger than the S value of the selection transistor 210. Therefore, two kinds of transistors having different S values can be provided in one pixel.

  Therefore, since the selection transistor 210 can reduce the S value, high-speed response can be improved. Further, since the S value of the driving transistor 220 can be increased, variation in threshold voltage of the driving transistor in the substrate surface can be reduced. Thus, the variation in the current value output when the input voltage is applied is also reduced, so that the light emission unevenness of the light emitting element can be reduced. Therefore, display unevenness of the display device can be reduced.

Third Embodiment
In the present embodiment, the cross-sectional configuration of the display device 100 shown in FIG. 1 will be described. FIG. 8 is a cross-sectional view of the display device 100 shown in FIG. 1 taken along the line D1-D2.

[Cross-sectional configuration of display device]
Next, a cross-sectional configuration of the display device 100 in a range including the region from the display region 103 to the terminal 107 illustrated in FIG. 1 will be described with reference to FIG.

  As shown in FIG. 8, a base film 201 is provided on the substrate 101. A glass substrate, a quartz substrate, a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, triacetyl cellulose, cyclic olefin copolymer, cycloolefin polymer, or other flexible resin substrate) may be used as the substrate 101. it can.

  The base film 201 is an insulating layer formed of an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide. The base film 201 is not limited to a single layer, and may have a stacked structure in which a silicon oxide layer and a silicon nitride layer are combined, for example. This structure may be appropriately determined in consideration of adhesion to the substrate 101 and gas barrier properties to the transistors 210 and 220.

  The transistor 210 and the transistor 220 are provided over the base film 201. FIG. 8 shows a transistor 220 which functions as a driving transistor. In FIG. 8, the transistor 220 includes a wiring layer 217 provided over the base film 201, a gate insulating film 241, a semiconductor layer 221, a gate insulating film 242, and a wiring layer 213. The transistor 220 is a bottom gate transistor, the wiring layer 217 functions as a gate electrode, and the wiring layer 213 functions as a control electrode.

  Note that the base film 201 is not necessarily provided, and the gate insulating film 241 may double as the base film.

  Next, each layer constituting the transistor 220 shown in the display region 103 will be described. As the semiconductor layer 221, polysilicon, amorphous silicon, or an oxide semiconductor can be used. As the gate insulating film 242, silicon oxide or silicon nitride can be used. As the wiring layer 213 and the wiring layer 217, metal materials such as copper, molybdenum, tantalum, tungsten, and aluminum can be used.

  Further, an interlayer insulating layer 243 covering the wiring layer 213 is provided over the transistor 220, and a contact hole is provided in the interlayer insulating layer 243. A conductive layer 219 and a wiring layer 248 are provided over the interlayer insulating layer 243, and are connected to the semiconductor layer 221 through the contact holes of the interlayer insulating layer 243. As the interlayer insulating layer 243, silicon oxide or silicon nitride can be used. The conductive layer 219 and the wiring layer 248 are each formed of a metal material such as copper, titanium, molybdenum, or aluminum, or an alloy material of these.

  Although not shown in FIG. 8, in the same layer as the wiring layer 213, the scanning line 111 made of the same metal material as the metal material of the wiring layer 213 can be provided. The scan line 111 is connected to the drive circuit 104. In the same layer as the source or drain electrodes 207 and 208, the signal line 112 can be provided to extend in a direction intersecting with the scan line 111. The signal line 112 is connected to the driver IC 106.

  A planarization film 244 is provided on the interlayer insulating layer 243. As the planarization film 244, for example, an organic material such as polyimide, polyamide, acrylic, or epoxy can be used. These materials can be formed by a solution coating method and have a high planarization effect. Although not shown in particular, the planarizing film 244 is not limited to a single layer structure, and may be a laminated structure of an organic insulating layer and an inorganic insulating layer.

  A protective film 245 is provided on the planarization film 244. The protective film 245 preferably has a barrier function to moisture and oxygen, and is preferably formed using, for example, a silicon nitride film or an aluminum oxide film.

  Contact holes are provided in the planarizing film 244 and the protective film 245. The conductive layer 219 is connected to the light emitting element 240 through the contact hole. Specifically, the pixel electrode 251 is provided on the protective film 245, and the pixel electrode 251 and the conductive layer 219 are connected to each other through the contact hole. In the display device 100 according to the present embodiment, the pixel electrode 251 functions as an anode that constitutes the light emitting element 240. The configuration of the pixel electrode 251 differs depending on whether it is a top emission type or a bottom emission type. In the case of the top emission type, a metal having high reflectance is used as the pixel electrode 251, or a work such as an indium oxide-based transparent conductive layer (for example, ITO) or a zinc oxide-based transparent conductive layer (for example, IZO or ZnO) A laminated structure of a transparent conductive layer having a high function and a metal film is used. In the case of the bottom emission type, the above-described transparent conductive layer is used as the pixel electrode 251. In the present embodiment, the case of the top emission type will be described.

  An insulating layer 246 is provided over the pixel electrode 251. For the insulating layer 246, polyimide, polyamide, acrylic, epoxy, siloxane, or the like can be used. The insulating layer 246 has an opening on a part of the pixel electrode 251. A part of the pixel electrode 251 exposed from the insulating layer 246 serves as the light emitting area LA of the light emitting element 240.

  In addition, the insulating layer 246 is provided between the pixel electrodes 251 adjacent to each other so as to cover an end portion (edge portion) of the pixel electrode 251, and functions as a member separating the adjacent pixel electrodes 251. Therefore, the insulating layer 246 is also generally referred to as "partition wall" or "bank". The opening of the insulating layer 246 preferably has a tapered inner wall. Thereby, the coverage defect at the time of formation of the organic layer mentioned later can be reduced.

  An organic layer is provided on the pixel electrode 251. The organic layer includes at least a light emitting layer 223 formed of an organic material, and functions as a light emitting portion of the light emitting element 240. The light emitting layer 223 emits light of a desired color. That is, by providing organic layers including different light emitting layers 223 on the pixel electrodes 251 for the plurality of pixels 109, each color of RGB can be displayed.

  In the organic layer, in addition to the light emitting layer 223, a hole injecting layer and / or a hole transporting layer 252, and an electron injecting layer and / or an electron transporting layer 224 are provided. Note that the hole injection layer and / or the hole transport layer 252, and the electron injection layer and / or the electron transport layer 224 extend over a plurality of pixels. In addition, the light emitting layer 223 is provided for each of the plurality of pixels 109.

  A counter electrode 255 is provided on the electron injection layer and / or the electron transport layer 224 and the insulating layer 246. The counter electrode 255 functions as a cathode (cathode) which constitutes the light emitting element 240. The display device 100 of the present embodiment is a top emission type, and thus a transparent conductive layer is used as the counter electrode 255. As the transparent conductive layer, for example, an MgAg thin film, ITO, IZO, ZnO or the like can be used. The counter electrode 255 extends over a plurality of pixels. The counter electrode 255 is electrically connected to the terminal 107 through the lower conductive layer in the peripheral region of the display region 103. In FIG. 8, a region where the pixel electrode 251, the hole injecting layer and / or the hole transporting layer 252, the light emitting layer 223, the electron injecting layer and / or the electron transporting layer 224, and the counter electrode 255 overlap is called a light emitting element 240. .

  A sealing film 260 is provided on the light emitting element 240. By providing the sealing film 260 over the light-emitting element 240, entry of water or oxygen into the light-emitting element 240 can be suppressed; therefore, deterioration of the light-emitting element 240 can be reduced. Thereby, the reliability of the display device 100 can be improved.

  Also, the wire 275 is exposed near the end of the peripheral region 110. Specifically, the flexible printed circuit board 108 is connected to the conductive layer 277 provided in the contact hole 276 provided in the protective film 245 and the planarization film 244 and the anisotropic conductive film 278.

  In the peripheral region 110, a bank 247 is provided on the protective film 245. The bank 247 is provided so as to surround at least the display area 103. The bank 247 may be provided so as to surround the display area 103 and the drive circuit 104. The bank 247 functions to prevent the organic insulating layer 272 from spreading. In addition, when the inorganic insulating layer 271 and the inorganic insulating layer 273 are in contact with each other over the bank 247, entry of moisture or oxygen from the organic insulating layer 272 can be suppressed. Thus, entry of moisture or oxygen into the light emitting element 240 can be suppressed, so that deterioration of the light emitting element 240 can be reduced. As a result, the reliability of the display device 100 can be improved.

  An adhesive 274 is provided to cover the inorganic insulating layer 273. The adhesive 274 may be, for example, an acrylic, rubber, silicone, or urethane adhesive. In addition, the adhesive 274 may contain a water absorbing substance such as calcium or zeolite. By including a water absorbing substance in the adhesive material 274, even when moisture intrudes into the display device 100, the moisture can be delayed from reaching the light emitting element 240.

  A circularly polarizing plate 228 is provided on the adhesive 274. Specifically, the circularly polarizing plate 283 is provided on the inorganic insulating layer 273 with the adhesive 274 interposed therebetween. The circularly polarizing plate 283 has a laminated structure including a 1⁄4 wavelength plate 281 and a linear polarizing plate 282. With this configuration, light from the light emitting area LA can be emitted from the surface on the display side of the substrate 102 to the outside.

  In this embodiment, bottom gate transistors and top gate transistors having different gate insulating film thicknesses are formed over the same substrate, and the results of evaluation of the characteristics of the respective transistors will be described.

  A bottom gate transistor 320 and a top gate transistor 310 manufactured in this embodiment will be described with reference to FIG. Note that the transistors 310 and 320 are n-channel transistors.

  First, the gate electrode 317 and the control electrode 312 are formed on the substrate 301. Next, a gate insulating film 341 is formed over the gate electrode 317 and the control electrode 312. Next, a semiconductor layer 321 overlapping with the gate electrode 317 and a semiconductor layer 322 overlapping with the control electrode 312 are formed over the gate insulating film 341. Next, the gate insulating film 342 is formed over the semiconductor layer 321 and the semiconductor layer 322. Next, a control electrode 313 which overlaps with the semiconductor layer 321 and a gate electrode 314 which overlaps with the semiconductor layer 322 are formed over the gate insulating film 342. Next, the interlayer insulating layer 343 is formed over the control electrode 313 and the gate electrode 314. Next, contact holes are formed in the interlayer insulating layer 343, and source and drain electrodes connected to the semiconductor layer 321 and source and drain electrodes connected to the semiconductor layer 322 are formed.

  Through the above steps, the bottom gate transistor 320 and the top gate transistor 310 are manufactured.

  Next, the Id-Vg characteristics of the bottom gate transistor 320 and the top gate transistor 310 were measured. The measurement of an Id-Vg characteristic applied as a voltage (Vg) applied to the gate electrode of each transistor in -0.1V steps from -5V to + 10V. The voltage (Vs) applied to the source electrode was 0 V, and the voltages (Vd) applied to the drain electrode were 0.1 V and 5 V. In addition, the back gate voltage was set to 0V.

  FIG. 10 shows the result of the Id-Vg characteristic of the transistor 310. FIG. 11 is a result of Id-Vg characteristics of the transistor 320. In FIG. 10, the solid line 401 is the result of the Id-Vg characteristic of Vd = 0.1 V, and the solid line 402 is the result of the Id-Vg characteristic of Vd = 0.1 V. Further, in FIG. 11, the solid line 411 is the result of the Id-Vg characteristic of Vd = 0.1 V, and the solid line 412 is the result of the Id-Vg characteristic of Vd = 0.1 V.

  The results in FIG. 10 indicate that the S value of the transistor 310 is 0.2 V / dec, and the results in FIG. 11 indicate that the S value of the transistor 320 is 0.5 V / dec.

  10 and 11 show that the S value of the transistor 320 is larger than the S value of the transistor 310. This is because the thickness of the gate insulating film 341 of the transistor 320 is larger than the thickness of the gate insulating film 342 of the transistor 310.

  Also, the first control electrode can be formed simultaneously with the formation of the second gate electrode, and the second control electrode can be formed simultaneously with the first gate electrode. As a result, two types of transistors, top gate transistor and bottom gate transistor, can be easily formed without increasing the process even if the area is as small as one pixel.

  Those skilled in the art appropriately add, delete, or change design of components based on the display devices described as the embodiments and examples of the present invention, or add, omit, or change conditions of processes. It is also included in the scope of the present invention as long as it includes the subject matter of the present invention. Moreover, each embodiment mentioned above can be mutually combined in the range which a technical contradiction does not arise.

  In addition, even if other effects or effects different from the effects brought about by the aspects of the embodiment described above are apparent from the description of the present specification, or those which can be easily predicted by those skilled in the art, it is natural. It is understood that the present invention provides.

100: display device, 101: substrate, 102: substrate, 103: display region, 104: drive circuit, 107: terminal, 108: flexible printed circuit board, 109: pixel, 109B: pixel, 109G: pixel, 109R: pixel, 110: peripheral area, 111: scanning line, 112: signal line, 113: threshold voltage control line, 114: driving power supply line, 115: threshold voltage control line, 116: reference power supply line, 201: base film, 207: drain electrode , 208: drain electrode, 210: transistor, 211: wiring layer, 212: wiring layer, 213: wiring layer, 214: wiring layer, 215: wiring layer, 216: wiring layer, 217: wiring layer, 218: conductive layer, 219: conductive layer, 220: transistor, 221: semiconductor layer, 222: semiconductor layer, 223: light emitting layer, 224: electron transport layer, 228: circularly polarized Plate 230: capacitive element 231: opening 232: opening 233: opening 234: opening 235: opening 236: opening 237: opening 238: opening 238: opening 239: opening Part, 240: light emitting element, 241: gate insulating film, 242: gate insulating film, 243: interlayer insulating layer, 244: planarization film, 245: protective film, 246: insulating layer, 247: bank, 248: wiring layer, 249: wiring layer, 251: pixel electrode, 252: hole transport layer, 255: counter electrode, 260: sealing film, 261: opening, 262: opening, 263: opening, 264: opening, 265: Conductive layer, 266: opening, 267: conductive layer, 271: inorganic insulating layer, 272: organic insulating layer, 273: inorganic insulating layer, 274: adhesive, 275: wiring, 276: contact hole, 277: conductive layer, 2 8: anisotropic conductive film, 281: 1⁄4 wavelength plate, 282: linear polarization plate, 283: circular polarization plate, 301: substrate, 310: transistor, 312: control electrode, 313: control electrode, 314: gate electrode , 317: gate electrode, 320: transistor, 321: semiconductor layer, 322: semiconductor layer, 341: gate insulating film, 342: gate insulating film, 343: interlayer insulating layer

Claims (9)

A substrate,
A light emitting element,
A first transistor in which one of a source and a drain is electrically connected to the light emitting element and the other of the source and the drain is connected to a drive power supply line;
A second transistor having one of a source and a drain connected to the gate of the first transistor,
The first transistor is
A first insulating layer on the substrate;
A second insulating layer disposed on the first insulating layer and thinner than the first insulating layer;
A first semiconductor layer between the first insulating layer and the second insulating layer;
A first gate electrode disposed between the substrate and the first insulating layer and having a region overlapping the first semiconductor layer;
A first control electrode having a region disposed on the second insulating layer and overlapping the first semiconductor layer;
Including
The second transistor is
A second semiconductor layer between the first insulating layer and the second insulating layer;
A second gate electrode having a region disposed on the second insulating layer and overlapping the second semiconductor layer;
A second control electrode disposed between the substrate and the first insulating layer and having a region overlapping the first semiconductor layer;
including,
Display device. A first capacitance electrode on the second insulating layer,
The first control electrode, the second gate electrode, and a third insulating layer on the first capacitance electrode;
The display device according to claim 1, further comprising: a capacitive element including a second capacitive electrode on the third insulating layer. The first capacitance electrode is connected to the gate of the first transistor,
The display device according to claim 2, wherein the second capacitance electrode is connected to one of the source and the drain of the first transistor.   The display device according to claim 3, wherein the second capacitance electrode is connected to one of the source and the drain of the first transistor and the light emitting element. Further comprising a signal line on the third insulating layer,
The display device according to claim 4, wherein the signal line is connected to the other of the source and the drain of the second transistor. A first wire on the same surface as the first gate electrode;
A driving power supply line on the third insulating layer;
The display device according to claim 5, wherein the drive power supply line is connected to the other of the source and the drain of the first transistor via the first wiring. A first wire on the same surface as the first gate electrode;
A driving power supply line and a second wiring on the third insulating layer;
The display device according to claim 5, wherein the drive power supply line is connected to the other of the source and the drain of the first transistor via the first wiring and the second wiring. It further has a third wiring on the third insulating layer,
The display device according to claim 7, wherein the gate of the first transistor is connected to one of the source and the drain of the second transistor via the third wiring.   The display device according to claim 8, wherein the third wiring is connected to the first capacitance electrode.

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