JP2019117680A5

JP2019117680A5 -

Info

Publication number: JP2019117680A5
Application number: JP2018220520A
Authority: JP
Filing date: 2018-11-26
Publication date: 2020-01-16
Anticipated expiration: 2038-11-26

Claims

A device,
A discharge transistor;
A first discharge path configured to connect a selected bit line to the discharge transistor;
A second discharge path configured to connect a sense node to the discharge transistor;
Setting the gate voltage of the discharge transistor at the voltage level of the first discharge path, and subsequently interrupting the first discharge path while leaving the gate voltage of the discharge transistor floating at the voltage level A bias circuit configured to sense a memory cell connected to the selected bit line by discharging the sense node via the second discharge path via the discharge transistor; An apparatus comprising:

A current source configured to provide an auxiliary current via the discharge transistor, wherein the bias circuit disconnects the first discharge path and discharges the sense node before the sense node discharges the sense node. Turning on a source to provide the auxiliary current through the discharge transistor, and to continue to provide the auxiliary current through the discharge transistor while discharging the sense node through the discharge transistor. The device of claim 1 further configured.

A capacitor having a first plate connected to a gate of the discharge transistor, wherein the bias circuit is further configured to apply a voltage level to the second plate of the capacitor according to an operating condition. The apparatus of claim 1.

A device,
Transistors and
A first switch and a second switch connected in series between a selected memory cell and the transistor, wherein a control gate of the transistor is connected between the first switch and the second switch. And the first switch and the second switch are configured to discharge the selected memory cell via the transistor when the first switch and the second switch are on at the same time. Setting the control gate of the transistor to float at the voltage level of the node between the first switch and the second switch when the switch and the second switch are off simultaneously. A first switch and a second switch, which are configured;
A third switch connected between a sense node and the transistor, wherein the third switch is configured to float at the voltage level of the node between the first switch and the second switch. A third switch configured to discharge the sense node through the transistor using the control gate of the transistor.

Further comprising an auxiliary current source configured to provide an auxiliary current through the transistor after turning off the first and second switches and before turning on the third switch. Item 5. The apparatus according to Item 4 .

The apparatus of claim 4, further comprising a decoupling capacitor having a first plate connected to the control gate of the transistor.

A voltage level corresponding to an operating condition is applied to the second plate of the decoupling capacitor after turning off the first and second switches and before turning on the third switch. The apparatus of claim 6, further comprising a bias circuit configured.

A bit line, wherein the selected memory cell is connected to the first and second switches via the bit line;
A source line, wherein the selected memory cell is connected between the source line and the bit line;
The apparatus of claim 4 , further comprising: a bias circuit configured to set the source line to a higher voltage than the bit line during a sensing operation.

A word line connected to a control gate of the selected memory cell, wherein the bias circuit performs a sensing operation for a negative threshold voltage condition by applying a non-negative voltage to the word line. 9. The apparatus of claim 8, further comprising a word line configured as:

The device of claim 9, wherein the bias circuit is further configured to perform a sensing operation for a positive threshold voltage condition by discharging the bit line to the source line through the memory cell. .

5. The apparatus of claim 4, wherein the apparatus includes a memory array of a monolithic three-dimensional semiconductor memory device, wherein the memory cells including the selected memory cells are located at a plurality of physical levels on a silicon substrate and include a charge storage medium. The described device.

The apparatus of claim 4, wherein the selected memory cell comprises a phase change memory material.

The method,
Discharging the selected memory cell via the first discharge path via the sense amplifier;
Setting a voltage of a control gate of a discharge transistor to a voltage level along the first discharge path, wherein the voltage level is determined by a data state of the selected memory cell;
Subsequently, providing an auxiliary current through the discharge transistor;
Using the control gate of the discharge transistor set to the voltage level according to the data state of the selected memory cell while providing the auxiliary current through the discharge transistor, through the discharge transistor Discharging the sense node.

Providing the auxiliary current to the discharge transistor via a clamp transistor from which the sense node is discharged;
14. The method of claim 13 , further comprising: biasing the clamp transistor to maintain a constant voltage level at a node between the clamp transistor and the discharge transistor.

A device,
A first transistor;
A first switch connected between a selected memory cell and a gate of the first transistor, wherein a voltage of the gate of the first transistor corresponding to a data state of the selected memory cell; A first switch configured to set a level;
The first transistor is connected between a sense node and the first transistor and is set to the voltage level corresponding to the data state of the selected memory cell by using the gate of the first transistor; A second switch configured to discharge the sense node through the transistor of
After setting the voltage level of the gate of the first transistor corresponding to the data state of the selected memory cell, and before discharging the sense node through the first transistor, A current source configured to provide an auxiliary current through one of the transistors.

A bit line, wherein the selected memory cell is connected to the first switch via the bit line;
A source line, wherein the selected memory cell is connected between the source line and the bit line;
The apparatus of claim 15, further comprising: a bias circuit configured to set the source line to a higher voltage than the bit line during a sensing operation.

A word line connected to a control gate of the selected memory cell, wherein the bias circuit performs a sensing operation for a negative threshold voltage condition by applying a non-negative voltage to the word line. 17. The apparatus of claim 16, further comprising a word line configured.

A word line connected to a control gate of the selected memory cell, wherein the bias circuit applies one of a plurality of corresponding non-negative voltages to the word line to generate a plurality of threshold voltages. 17. The apparatus of claim 16, further comprising a word line configured to perform a state sensitive operation.

A second transistor, wherein the auxiliary current is supplied to the first transistor via the second transistor, and the sense node is supplied via the first transistor via the second transistor. Further comprising a second transistor, which is discharged at a predetermined voltage, wherein the bias circuit is configured to maintain a constant voltage level at a node between the first transistor and the second transistor. Item 17. The apparatus according to Item 16.

A sense amplifier circuit,
A transistor connected to the discharge node;
Means for discharging a selected memory cell via a discharge path of the sense amplifier circuit;
Means for setting a control gate of the transistor to a voltage level according to a data state of the selected memory cell at a node of the discharge path while discharging the selected memory cell;
Means for discharging a sense node via the transistor while the control gate of the transistor is set to the voltage level according to the data state of the selected memory cell. circuit.