JP2019114764A - Semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device with fast address access time.SOLUTION: A semiconductor storage device comprises a plurality of memory cells, and a word line connected to the plurality of memory cells. The word line is arranged in a first direction. Each of the plurality of memory cells includes a gate electrode arranged in a second direction crossing the first direction.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a semiconductor memory device, and in particular, is applicable to a semiconductor memory device including static memory cells and a semiconductor device including the same.

  Some semiconductor devices include volatile semiconductor memory devices such as static type semiconductor memory devices (SRAM: Static Random Access Memory). A layout of elongated memory cells has been proposed as a memory cell of an SRAM generated by a miniaturized semiconductor process (see US Patent Application Publication No. 2002/0117722). This elongated memory cell has a horizontally long layout in which the gate wiring is arranged in the lateral direction and the diffusion layer is arranged in the vertical direction, and the word lines are arranged along the same direction as the gate wiring, and the bit lines are arranged in the same direction as the diffusion layer. Arranged along.

  Further, as an SRAM, there has been proposed a configuration in which bit lines are shared between adjacent memory cells (refer to Japanese Patent Laid-Open No. 5-290577).

U.S. Patent Application Publication No. 2002/0117722 Unexamined-Japanese-Patent No. 5-290577

The present inventors have found that there are the following cases with respect to an SRAM employing an elongated memory cell layout as described in US Patent Application Publication No. 2005/014696.
That is, in the layout of elongated memory cells, the rectangular shape of the memory array is a layout that is very long along the arrangement direction of the word lines. When there are many memory cells connected to one word line (multi-bit width), the wiring length of the word line becomes long, and parasitic resistance and parasitic capacitance parasitic on the word line increase. Therefore, since the rising of the word line to the selection level is delayed, the address access time of the SRAM may be delayed.
An object of the present disclosure is to provide a semiconductor memory device having a fast address access time.
Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

The outline of typical ones of the present disclosure will be briefly described as follows.
That is, the semiconductor memory device has a plurality of memory cells and a word line coupled to the plurality of memory cells. The word lines are arranged along a first direction. Each of the plurality of memory cells includes a gate electrode disposed along a second direction intersecting the first direction.

  According to the semiconductor memory device, it is possible to provide a semiconductor memory device having a fast address access time.

It is a figure explaining the memory array of the semiconductor memory device concerning an embodiment. FIG. 2 schematically shows a layout of the memory cell of FIG. 1; It is a figure explaining the memory array of the semiconductor memory device concerning a comparative example. FIG. 2 is a view for explaining an example of the configuration of a semiconductor memory device according to the first embodiment; It is a figure which shows the example of a circuit of two memory cells. FIG. 6 is a diagram for explaining a configuration example of layout arrangement of two memory cells shown in FIG. 5. It is a figure which shows the layout arrangement | positioning of the memory cell in which the 1st layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell in which the 2nd-layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell in which the 3rd-layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell in which the 4th-layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell which concerns on a modification. It is a figure which shows the layout arrangement | positioning of the memory cell in which the 2nd-layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell in which the 3rd-layer metal wiring was formed. It is a block diagram showing composition of a semiconductor device concerning an application example. FIG. 7 is a diagram for explaining a configuration example of a semiconductor memory device according to a second embodiment. It is a figure which shows the example of a circuit of a TCAM cell. It is a figure which shows the layout arrangement | positioning of the TCAM cell in which the 1st layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the TCAM cell in which the 2nd layer metal wiring and the 3rd layer metal wiring were formed. FIG. 18 is a diagram for explaining a configuration example of a semiconductor memory device according to a modification 2; FIG. 18 is a diagram illustrating an example of a circuit of a TCAM cell according to a modification 2; FIG. 6 is a diagram showing an example of configuration and an example of operation of a match line control circuit. It is a figure which shows the layout arrangement | positioning of the TCAM cell in which the 1st layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the TCAM cell in which the 2nd layer metal wiring and the 3rd layer metal wiring were formed. FIG. 7 is a diagram showing an example of a configuration of a semiconductor memory device according to a third embodiment. FIG. 18 is a diagram illustrating an example of a circuit of a memory cell of BCAM according to a third embodiment; It is a figure which shows the layout arrangement | positioning of the memory cell of BCAM in which 1st layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell of BCAM in which 2nd layer metal wiring was formed. FIG. 18 is a diagram showing an example of a circuit of a memory cell of BCAM according to Modification 3; It is a figure which shows the layout arrangement | positioning of the memory cell of BCAM in which 1st layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the memory cell of BCAM in which 2nd layer metal wiring was formed. FIG. 18 is a view showing a layout arrangement of memory cells of a BCAM in which a first-layer metal interconnection is formed according to a modification 4; FIG. 17 is a diagram showing a layout arrangement of memory cells of a BCAM in which a second-layer metal interconnection is formed according to a modification 4; It is a figure which shows the layout arrangement | positioning of the memory cell of BCAM in which the 1st layer metal wiring which concerns on the modification 5 was formed. FIG. 33 is a view showing a layout arrangement of memory cells of a BCAM in which a first layer metal interconnection is formed according to modification 5 and is a view showing a layout arrangement of memory cells adjacent to the memory cell shown in FIG. . It is a figure which shows the layout arrangement | positioning of the memory cell of BCAM in which the 2nd layer metal wiring which concerns on the modification 5 was formed. FIG. 18 is a view showing a layout arrangement of memory cells of TCAM in which a first-layer metal interconnection is formed according to a fourth embodiment. FIG. 18 is a view showing a layout arrangement of memory cells of TCAM in which second-layer metal interconnections are formed according to a fifth embodiment; FIG. 18 is a diagram illustrating a circuit example of a two-port memory cell according to a fifth embodiment. It is a figure which shows the layout arrangement | positioning of 2 port type | mold memory cell in which 1st layer metal wiring was formed. It is a figure which shows the layout arrangement | positioning of the 2 port type | mold memory cell in which the 2nd layer metal wiring and the 3rd layer metal wiring were formed. FIG. 21 is a diagram showing a layout arrangement of memory cells of BCAM in which first-layer metal interconnections are formed according to a sixth embodiment. FIG. 18 is a view showing a layout arrangement of memory cells of a BCAM in which second-layer metal interconnections are formed according to a sixth embodiment.

  Hereinafter, embodiments, examples, comparative examples, and applied examples will be described using the drawings. However, in the following description, the same components may be assigned the same reference numerals and repeated descriptions may be omitted. Note that the drawings may be schematically represented as to the width, thickness, shape, etc. of each portion in comparison with the actual embodiment in order to clarify the description, but this is merely an example, and the interpretation of the present invention is not limited. It is not limited.

Embodiment
FIG. 1 is a diagram for explaining a memory array of a semiconductor memory device according to an embodiment. FIG. 2 is a diagram schematically showing the layout arrangement of the memory cell of FIG. In each memory cell MC shown in FIG. 1, one of four gate electrodes G1-G4 shown in FIG. 2 is exemplified as gate electrode G in order to facilitate simplification and understanding of the drawing. It is drawn.

  Memory array 2 of semiconductor memory device 1 illustratively has memory cells MC in 5 rows and 5 columns. Each of the memory cells MC is a static memory cell, and as shown in FIG. 2, has a rectangular layout pattern whose outer shape is elongated in the lateral direction in plan view. The layout pattern of the rectangular shape has a short side A in the longitudinal direction (X direction or first direction) and a long side B in the lateral direction (Y direction or second direction). The length Lcx of the side A along the X direction is shorter than the length Lcy of the side B along the Y direction orthogonal to or crossing the X direction (Lcx <Lcy). As exemplarily shown in FIG. 2, the memory cell MC has four gate electrodes (or gate interconnections) G1, G2, G3 and G4 arranged to extend in the direction along the Y direction. The first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 are provided separately from each other, and have a linear shape without bending. A fourth gate electrode G4 is disposed laterally to the first gate electrode G1. The first gate electrode G1 and the third gate electrode G3 are arranged to run in parallel in the X direction. A second gate electrode G2 is disposed laterally of the third gate electrode G3. The first gate electrode G1 and the fourth gate electrode G4 are arranged in a straight line in the Y direction, and the third gate electrode G3 and the second gate electrode G2 are arranged in a straight line in the Y direction.

  Therefore, in the elongated rectangular memory cell MC, two MOS transistors are formed vertically in the X direction. On the other hand, in the elongated rectangular memory cell MC, three MOS transistor can be formed side by side in the Y direction. This will be described in detail in FIG. 6 described later.

  FIG. 1 exemplarily depicts one word line WL and one bit line BT. Word lines WL are arranged to extend in a direction along the X direction, and bit lines BT are arranged to extend in a direction along the Y direction. In FIG. 1, the arrangement direction of the word lines WL is a direction crossing the arrangement direction of the gate electrodes G of the memory cells MC, and the arrangement direction of the bit lines BT is the same as the arrangement direction of the gate electrodes G of the memory cells MC. It is assumed. In other words, the arrangement direction of the word line WL is a direction along the direction of the side A which is the short side of the rectangular shaped layout pattern of the memory cell, and the arrangement direction of the bit line BT is the rectangular shape of the memory cell It is a direction along the direction of the side B which is the long side of the layout pattern. Further, in the layout pattern of a rectangular memory cell whose outer shape is elongated in the lateral direction, the length of word line WL corresponding to one memory cell MC is the same as the length (Lcx) of short side A, and one memory Since the length of bit line BT corresponding to a cell is the same as the length of long side B (Lcy), the length (Lcx) of word line WL per memory cell MC is the bit line BT per memory cell. Less than the length of Lc (Lcx) (Lcx <Lcy).

  In FIG. 1, word line WL is arranged in the X direction so as to be connected to five memory cells arranged in the X direction, and therefore the length of word line WL on memory array 2 is 5 Lcx. On the other hand, bit line BT is arranged in the Y direction so as to be connected to five memory cells arranged in the Y direction, so the length of bit line BT on memory array 2 is 5 Lcy. That is, since the elongated rectangular memory cell shown in FIG. 2 is used, the length (5 Lcx (WL)) of word line WL is shorter than the length (5 L cy (BT)) of bit line BT in FIG. It has been shortened (5Lcx (WL) <5Lcy (BT)).

  FIG. 3 is a diagram for explaining a memory array of the semiconductor memory device according to the comparative example, and in the same manner as FIG. 1, memory cells MC in 5 rows and 5 columns are described. Also in this case, it is assumed that each memory cell MC uses the elongated rectangular memory cell shown in FIG. The arrangement direction of the word line wl is the same as the arrangement direction of the gate electrode G of the memory cell MC. On the other hand, the arrangement direction of the bit lines is a direction intersecting the arrangement direction of the gate electrodes G of the memory cells MC. The length of the word line wl on the memory array 2 is 5 Lcy (wl), and the length of the bit line bt on the memory array 2 is 5 Lcx (bt). Therefore, the length (5 Lcy (wl)) of the word line wl is longer than the length (5 Lcx (bt)) of the bit line bt in FIG. 3 (5 Lcy (wl)> 5 Lcx (bt)).

  Comparing FIG. 1 with FIG. 3, under the condition that the same number of memory cells are connected, the length of the word line WL (5Lcx (WL)) is the length of the word line wl (5Lcy (wl)) Because of shorter (5Lcx (WL) <5Lcy (wl)), the parasitic resistance and parasitic capacitance of the word line WL shown in FIG. 1 are reduced more than the parasitic resistance and parasitic capacitance of the word line wl shown in FIG. .

  Although FIG. 1 and FIG. 3 show the configuration example of the memory cell MC in 5 rows and 5 columns, it has 8 word lines and 64 or 128 memory cells are connected to one word line. When a semiconductor memory device having a multi-bit configuration is considered, the length of the word line WL shown in FIG. 1 is the same between the arrangement method of word line WL shown in FIG. 1 and the arrangement method of word line wl shown in FIG. As compared with the length of the word line wl shown in FIG.

  According to the embodiment, in the semiconductor memory device in which the memory cells of the layout pattern of the rectangular shape having a long and thin outer shape are arranged in a matrix, the arrangement direction of the word lines WL is orthogonal to the arrangement direction of the gate electrodes G1 to G4 of the memory cells. Alternatively, the parasitic resistance and the parasitic capacitance of the word line WL can be reduced because of the crossing direction. Therefore, the rising of the word line WL to the selection level is quickened. Therefore, the address access time for reading data in the semiconductor memory device can be shortened.

  In addition, since the falling from the selection level of the word line WL to the non-selection level is also quick, the interval between address accesses for continuous data reading or data writing can be shortened, thereby providing a high-speed semiconductor memory.

  FIG. 4 is a diagram for explaining a configuration example of the semiconductor memory device according to the first embodiment.

  The semiconductor memory device 1a, which is a static semiconductor memory device SRAM (Static Random Access Memory), is formed on the surface of a semiconductor substrate such as single crystal silicon, for example, by a known CMOS semiconductor manufacturing method. Semiconductor memory device 1a has a memory array 2a including eight memory cells (MC00 to MC31) arranged in two rows and four columns, as exemplarily shown. Each of the memory cells (MC00 to MC31) includes a static memory cell. The memory array 2a is not limited to memory cells in two rows and four columns, but may include a plurality of memory cells arranged in a matrix of two rows and four columns or more. Each layout pattern of each memory cell MC is, as described later, formed into a rectangular layout pattern elongated in the Y direction as described in FIG. 2, and has gate electrodes G1 to G4.

  Memory cells MC00 and MC01 are connected to bit line pair BL0 and BL1, and memory cells MC10 and MC11 are connected to bit line pair BL1 and BL2. The memory cells MC20 and MC21 are connected to the bit line pair BL2 and BL3, and the memory cells MC30 and MC31 are connected to the bit line pair BL3 and BL4. That is, the bit lines BL1, BL2, and BL3 are shared by the memory cells arranged above and below.

  Memory cells MC00 and MC20 are connected to word line WLe0, and memory cells MC10 and MC30 are connected to word line WLo0. The memory cells MC01 and MC21 are connected to the word line WLe1, and the memory cells MC11 and MC31 are connected to the word line WLo1.

  The bit lines (BT0 to BT4) are provided to extend along the Y direction, and the word lines (WLe0, WLo0, WLe1, WLo1) are provided to extend along the X direction intersecting the Y direction. That is, the arrangement direction of the word lines (WLe0, WLo0, WLe1, WLo1) and the bit lines (BT0 to BT4) in FIG. 4 is similar to the arrangement direction of the word lines WL and the bit lines BL shown in FIG. Is set.

  Bit line pair BL0, BL1 is connected to common data line pair CD0, CD1 via N channel MOS transistors YS00, YS01 for selection. Bit line pair BL1 and BL2 are connected to common data line pair CD0 and CD1 via N channel MOS transistors YS10 and YS11 for selection. Bit line pair BL2, BL3 is connected to common data line pair CD0, CD1 via N channel MOS transistors YS20, YS21 for selection. Bit line pair BL3 and BL4 are connected to common data line pair CD0 and CD1 via N channel MOS transistors YS30 and YS31 for selection.

  The row selection circuit (row decoder) RDC sets one of the word lines WLe0, WLo0, WLe1, and WLo1 to a selection level according to a row address signal such as a first selection signal.

  Column selection circuit (column decoder) CDC includes a common gate of N channel MOS transistors YS10 and YS11, a common gate of N channel MOS transistors YS20 and YS21, a common gate of N channel MOS transistors YS30 and YS31, and an N channel MOS transistor YS40. , YS41 is coupled to the common gate. The column decoder CDC generates a pair of N channel MOS transistors ((YS10, YS11), (YS20, YS21), (YS30, YS31), or (YS30, YS41) according to a column address signal such as a second selection signal. Is selected, a pair of bit lines ((BL0, BL1), (BL1, BL2), (BL2, BL3), or (one) is turned on via a pair of N channel MOS transistors in an on state. Connect BL3, BL4)) to the common data line pair CD0, CD1.

  Input / output circuit IOC is coupled to common data line pair CD0, CD1 and is used when writing data to the memory cell, and a read circuit having a sense amplifier and a latch circuit used when reading data from the memory cell. And a write circuit. The read circuit selects a selected word line (WLe0, WLo0, WLe1, or WLo1) and a selected bit line pair ((BL0, BL1), (BL1, BL2), (BL2, BL3), or (BL3). , BL4)) as an input signal through common data line pair CD0, CD1 and amplifies the input signal and outputs the amplified signal to the outside of semiconductor memory device 1a. The write circuit selects a data line input from the outside of semiconductor memory device 1a as a selected word line (WLe0, WLo0, WLe1 or WLo1) via common data line pair CD0, CD1. Write to the memory cell connected to the pair (BL0, BL1), (BL1, BL2), (BL2, BL3), or (BL3, BL4).

  Next, a circuit example and a layout example of memory cells MC00 and MC10 surrounded by a dotted line V in FIG. 4 will be described.

  FIG. 5 is a diagram showing a circuit example of two memory cells. Each of memory cells MC00 and MC10 is a single port memory cell (6T SP SRAM cell) including six MOS transistors.

  Memory cell MC00 includes first and second P-channel MOS transistors PM1 and PM2 and first to fourth N-channel MOS transistors NT1, NT2, ND1 and ND2. Source-drain paths of P-channel MOS transistors PM1 and PM2 as first and second load transistors are connected between a supply line of power supply voltage VDD and first and second storage nodes MB1 and MT1, respectively. The gates are connected to the second and first storage nodes MT1 and MB1, respectively. Source / drain paths of N channel MOS transistors ND1 and ND2 as first and second drive transistors are connected between first and second storage nodes MB1 and MT1 and a supply line of ground potential VSS, respectively. The gates are connected to the second and first storage nodes MT1 and MB1, respectively. The source-drain paths of N-channel MOS transistors NT1 and NT2, which are first and second transfer transistors, are connected between first and second storage nodes MB1 and MT1 and bit lines BL1 and BL0, respectively. Both gates are connected to word line WLe0.

  The MOS transistors PM1 and ND1 form a first inverter that provides an inverted signal of the signal of the second storage node MT1 to the first storage node MB1. The MOS transistors PM2 and ND2 form a second inverter that provides an inverted signal of the signal of the first storage node MB1 to the second storage node MT1. The inputs and outputs of the two inverters are connected in anti-parallel between the first and second storage nodes MB1 and MT1 to form a latch circuit.

  Memory cell MC10 includes first and second P-channel MOS transistors PM3 and PM4 and first to fourth N-channel MOS transistors NT3, NT4, ND3 and ND4. Source-drain paths of P-channel MOS transistors PM4 and PM4 as first and second load transistors are respectively connected between a supply line of power supply voltage VDD and first and second storage nodes MB2 and MT2, The gates are connected to the second and first storage nodes MT2 and MB2, respectively. Source-drain paths of N-channel MOS transistors ND3 and ND4 as first and second drive transistors are respectively connected between first and second storage nodes MB2 and MT2 and a supply line of ground potential VSS, The gates are connected to the second and first storage nodes MT2 and MB2, respectively. The source-drain paths of N channel MOS transistors NT3 and NT4, which are first and second transfer transistors, are connected between first and second storage nodes MB2 and MT2 and bit lines BL2 and BL1, respectively. Both gates are connected to the word line WLo0.

  The MOS transistors PM3 and ND3 form a first inverter that provides an inverted signal of the signal of the second storage node MT2 to the first storage node MB2. The MOS transistors PM4 and ND4 form a second inverter that provides an inverted signal of the signal of the first storage node MB2 to the second storage node MT2. The inputs and outputs of the two inverters are connected in anti-parallel between the first and second storage nodes MB2 and MT2 to form a latch circuit.

  FIG. 6 is a diagram for explaining a configuration example of the layout arrangement of two memory cells shown in FIG. In FIG. 6, connections to the power supply potential VDD and the ground potential VSS are omitted for simplicity of the drawing but will be described in detail later.

  The memory cells MC00 and MC10 are vertically disposed on the surface of the semiconductor substrate in plan view. The formation region of each of the memory cells MC00 and MC10 is a region surrounded by an alternate long and short dash line, and the alternate long and short dash line indicates a cell boundary. The formation region of one memory cell is, as described in FIG. 2, a layout pattern of a rectangular shape whose outer shape is elongated in the lateral direction (Y direction) in plan view. Bit lines BL0, BL1, BL3 are arranged to extend along the Y direction, and word lines WLe0, WLo0 are arranged to extend along the X direction. Bit line BL0 is arranged along the upper cell boundary of memory cell MC00, bit line BL1 is arranged along the cell boundary between memory cell MC00 and memory cell MC10, and bit line BL3 is a memory cell It is arranged along the lower cell boundary of MC10.

  In each formation region of memory cells MC00 and MC10, N-type well regions provided between two P-type well regions PW1 and PW2 provided along the X direction and two P-type well regions PW1 and PW2 An NW is formed on the surface of the semiconductor substrate. The P-type well regions PW1 and PW2 are semiconductor regions into which P-type impurities are introduced, and the N-type well regions NW are semiconductor regions into which N-type impurities are introduced.

  In each of the formation regions of memory cells MC00 and MC10, as described in FIG. 2, the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 are Y. Arranged along the direction. The arrangement of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 has been described with reference to FIG. 2, and thus the description thereof is omitted here.

  In the formation region of memory cell MC00, gate electrode G1 constitutes a gate electrode of N channel MOS transistor NT1. Gate electrode G2 constitutes a gate electrode of N channel MOS transistor NT2. Gate electrode G3 constitutes a gate electrode of P channel MOS transistor PM1 and N channel MOS transistor ND1. Gate electrode G4 constitutes a gate electrode of P channel MOS transistor PM2 and N channel MOS transistor ND2. On the other hand, in the formation region of memory cell MC10, gate electrode G1 constitutes the gate electrode of N channel MOS transistor NT4. Gate electrode G2 constitutes a gate electrode of N channel MOS transistor NT3. Gate electrode G3 constitutes a gate electrode of P channel MOS transistor PM4 and N channel MOS transistor ND4. Gate electrode G4 constitutes a gate electrode of P channel MOS transistor PM3 and N channel MOS transistor ND3.

  In the P-type well region PW1, an N-type impurity region N1 is provided along the X direction. N-type impurity region N1 constitutes the source or drain of N-channel MOS transistors ND1, NT1, NT4, and ND4. In the P-type well region PW2, an N-type impurity region N2 is provided along the X direction. N-type impurity region N2 constitutes the source or drain of N-channel MOS transistors NT2, ND2, ND3, and NT3. The N-type impurity regions N1 and N2 are semiconductor regions into which N-type impurities are introduced.

  P-type impurity regions P1, P2, and P3 are provided in the N-type well region NW along the X direction. The P-type impurity regions P1, P2, and P3 are semiconductor regions into which P-type impurities are introduced. P-type impurity region P1 constitutes the source or drain of P-channel MOS transistor PM1. P-type impurity region P2 constitutes the source or drain of P-channel MOS transistor PM2 in the formation region of memory cell MC00. P-type impurity region P2 constitutes the source or drain of P-channel MOS transistor PM3 in the formation region of memory cell MC10. P-type impurity region P3 constitutes the source or drain of P-channel MOS transistor PM4.

  Word line WLe0 is connected to gate electrodes G1 and G2 formed in the formation region of memory cell MC00, and is arranged to extend between gate electrode G2 and gate electrode G3 along the X direction. The word line WLo0 is connected to the gate electrodes G1 and G2 formed in the formation region of the memory cell MC10, and is arranged to extend between the gate electrode G1 and the gate electrode G4 along the X direction. That is, the word lines WLe0 and WLo0 are arranged to extend along a direction orthogonal to or intersecting with the gate electrodes G1, G2, G3 and G4. The word lines WLe0 and WLo0 are arranged to extend along the same direction as the extending direction of the N-type well region NW and the P-type well regions PW1 and PW2. The word lines WLe0 and WLo0 are arranged to extend along or orthogonal to the direction in which the N-type impurity regions N1 and N2 and the P-type impurity regions P1 and P2 extend.

  Bit line BL0 is provided to extend along the Y direction above the cell boundary above the formation region of memory cell MC00, and is connected to N-type impurity region N2 which is the source or drain of NT2 at connection portion CT0 doing. Bit line BL1 is provided to extend along the Y direction over the cell boundary between the formation region of memory cell MC00 and the formation region of memory cell MC10, and N which is the source or drain of NT1 and NT4 It connects with the type | mold impurity region N1 in the connection part CT1. Bit line BL3 is provided to extend along the Y direction above the cell boundary below the formation region of memory cell MC10, at N-type impurity region N2 which is the source or drain of NT3 and at connection portion CT2. Connected

  As shown in FIG. 6, for example, in the formation region of the memory cell MC00, two MOS transistor transistors are formed side by side in the X direction like NT1 and ND1 or NT2 and ND2. On the other hand, in the Y direction, three MOS transistor transistors are formed side by side like NT1, PM2 and ND2 or ND1, PM1 and NT2. The same applies to the formation region of the memory cell MC10.

  Next, the configuration of the memory cell of FIG. 6 will be described in more detail with reference to FIGS. 7 to 10.

  FIG. 7 is a diagram showing a layout arrangement of memory cells in which first-layer metal interconnections are formed.

  As described in FIG. 6, P-type well regions PW1 and PW2, N-type well region NW, gate electrodes G1-G4, N-type impurity regions N1 and N2, and P-type impurities are formed on the surface of the semiconductor substrate. Regions P1, P2 and P3 are formed.

  FIG. 7 further shows first layer metal interconnections M11 to M19 and M110 to M117 and contacts shown by dotted lines in the formation regions of memory cells MC00 and MC10.

  M11 is connected to an N-type impurity region N1 forming the source of ND1 via a contact. M11 is connected to the ground potential VSS. M12 is connected to P-type impurity region P1 forming the source of PM1 via a contact. M12 is connected to the power supply potential VDD. M13 is connected to an N-type impurity region N2 constituting the source or drain of NT2 via a contact. M13 will be connected to bit line BL0. M14 is connected to the gate electrode G1 via a contact. M14 is connected to word line WLe0. One end of M15 is connected to the N-type impurity region N1 constituting the drain of ND1 or the source or drain of NT1 through a contact. The other end of M15 is connected to a P-type impurity region P1 forming the drain of PM1 via a contact. The other end of M15 is also connected to the gate electrode G4 via a contact. One end of M16 is connected via a contact to the N-type impurity region N2 that constitutes the drain of ND2 or the source or drain of NT2. The other end of M16 is connected to a P-type impurity region P2 forming the drain of PM2 via a contact. The other end of M16 is also connected to the gate electrode G3 via a contact. M17 is connected to the gate electrode G2 via a contact. M17 is connected to word line WLe0. M18 is connected to an N-type impurity region N1 constituting the source or drain of NT1 and NT4 via a contact. M18 is to be connected to bit line BL1. M19 is connected to a P-type impurity region P2 constituting a source of PM2 and PM3 via a contact. M19 is connected to the power supply potential VDD.

  M110 is connected to an N-type impurity region N2 forming the source of ND2 and ND3 via a contact. M110 is connected to the ground potential VSS. M111 is connected to the gate electrode G1 via a contact. M111 is connected to word line WLo0. One end of M112 is connected via a contact to the N-type impurity region N1 constituting the drain of ND4 or the source or drain of NT4. The other end of M112 is connected to a P-type impurity region P3 forming the drain of PM4 via a contact. The other end of M112 is also connected to the gate electrode G4 via a contact. One end of M113 is connected through a contact to the N-type impurity region N2 that constitutes the drain of ND3 or the source or drain of NT3. The other end of M113 is connected to a P-type impurity region P2 forming a drain of PM3 via a contact. The other end of M113 is also connected to the gate electrode G3 via a contact. M114 is connected to the gate electrode G2 via a contact. M114 is connected to word line WLo0. M115 is connected to an N-type impurity region N1 constituting the source of ND4 via a contact. M115 is connected to the ground potential VSS. M116 is connected to the P-type impurity region P3 forming the source of PM4 via a contact. M116 is connected to the power supply potential VDD. M117 is connected to an N-type impurity region N2 constituting the source or drain of NT3 via a contact. M117 will be connected to bit line BL3.

  FIG. 8 is a diagram showing a layout arrangement of memory cells in which second-level metal interconnections are formed. In FIG. 8, second-layer metal wirings M21 to M29, M210, and 211, and a first via electrode (via 1) are illustrated. The via electrode is an electrode for connecting the first layer metal interconnection and the second layer metal interconnections M21 to M29, M210, and 211. Note that, in FIG. 8, reference symbols of the first layer metal wiring are not drawn for the sake of simplification of the drawing.

  M21 is connected to M11 via the first via electrode. M21 is connected to the ground potential VSS. M22 is connected to M12 via the first via electrode. M22 is connected to the power supply potential VDD. M23 is connected to M13 via the first via electrode. M23 is to be connected to bit line BL0. M24 is connected to M14 and M17 via the first via electrode. M24 is connected to word line WLe0. M25 is connected to M18 via the first via electrode. M25 is to be connected to bit line BL1. M26 is connected to M19 via the first via electrode. M26 is connected to the power supply potential VDD. M27 is connected to M110 via the first via electrode. M27 is connected to the ground potential VSS. M28 is connected to M111 and M114 via the first via electrode. M28 is connected to word line WLe0. M29 is connected to M115 via the first via electrode. M29 is connected to the ground potential VSS. M210 is connected to M116 via the first via electrode. M210 is connected to the power supply potential VDD. M211 is connected to M117 via the first via electrode. M211 is connected to the bit line BL3.

  FIG. 9 is a diagram showing a layout arrangement of memory cells in which third-layer metal interconnections are formed. In FIG. 9, third layer metal interconnections M31 to M38 arranged to extend along the X direction and a second via electrode (via 2) are drawn. The second via electrode is an electrode that connects the second layer metal wiring and the third layer metal wiring M31 to M38. In FIG. 9, the reference symbols of the second layer metal wiring are not drawn for the sake of simplification of the drawing.

  M31 is a wiring to which the ground potential VSS is supplied, and is connected to M21 and M29 via a second via electrode. M32 is a word line WLo0, and is connected to M28 via a second via electrode. M33 is a wiring to which the power supply potential VDD is supplied, and is connected to M22, M26 and M210 via a second via electrode. M34 is a word line WLe0, and is connected to M24 via a second via electrode. M35 is a wiring to which the ground potential VSS is supplied, and is connected to M27 via a second via electrode. M36 is connected to M23 via the second via electrode. M36 is connected to bit line BL0. M37 is connected to M25 via the second via electrode. M37 will be connected to bit line BL1. M38 is connected to M211 via the second via electrode. M38 is to be connected to bit line BL2.

  FIG. 10 is a diagram showing a layout of a memory cell in which a fourth-layer metal interconnection is formed. In FIG. 10, fourth-layer metal wires M41 to M45 arranged to extend along the Y direction and a third via electrode (via 3) are drawn. The third via electrode is an electrode that connects the third layer metal wiring and the fourth layer metal wiring M41 to M45. In FIG. 10, reference symbols of the third layer metal wiring are not drawn for the sake of simplification of the drawing.

  M41 is a bit line BL0, and is connected to M36 via a third via electrode. M42 is a power supply wiring to which the power supply potential VDD is supplied, and is connected to M33 via the third via electrode. M43 is a bit line BL1 and is connected to M37 via a third via electrode. M44 is a power supply wiring to which the ground potential VSS is supplied, and is connected to M31 and M35 via a third via electrode. M45 is a bit line BL2 and is connected to M38 via a third via electrode.

  Thereby, as shown in FIG. 7 to FIG. 10, the memory cell using the first layer metal interconnection to the fourth layer metal interconnection is formed.

  In the first embodiment, the word lines WLo0 and WLe0 are formed by the third layer metal interconnection, and the bit lines BL0, BL1 and BL2 are formed by the fourth layer metal interconnection, but the present invention is not limited thereto. . The bit lines BL0, BL1, and BL2 may be formed of third-layer metal interconnections, and the word lines WLo0 and WLe0 may be formed of fourth-layer metal interconnections.

  According to the first embodiment, even when a rectangular memory cell elongated in the Y direction can be used in plan view, the length of the word line can be shortened. Therefore, as in the embodiment, the parasitic resistance and parasitic capacitance of the word line WL Can be reduced. Therefore, the rising of the word line WL to the selection level can be made faster. Therefore, the address access time for reading data in the semiconductor memory device can be shortened.

  In addition, since the falling from the selection level of the word line WL to the non-selection level is also quick, the interval between address accesses for continuous data reading or data writing can be shortened, thereby providing a high-speed semiconductor memory.

(Modification)
A modification is demonstrated using FIGS. 11-13. The modified example makes it possible to form the memory cell from the first layer metal wiring to the third layer metal wiring by using a local interconnect (local wiring, LIC, local interconnect).

  FIG. 11 is a diagram showing a layout arrangement of memory cells according to a modification. FIG. 11 shows the case where two local interconnects (local wiring, LIC1, LIC2. LIC3, LIC4) are used in each of the regions MC00 and MC01. In FIG. 11, parts different from FIG. 7 are as follows.

  The first layer metal wiring M15 and the contacts in FIG. 7 are changed to the local interconnect LIC1 in FIG. The first layer metal interconnection M16 and the contacts in FIG. 7 are changed to the local interconnect LIC2 in FIG. The first layer metal wiring M112 and the contacts in FIG. 7 are changed to the local interconnect LIC3 in FIG. The first layer metal wiring M113 and the contacts in FIG. 7 are changed to the local interconnect LIC 4 in FIG. Further, based on this change, in the formation region of MC00, the first layer metal wires M14 and M15 in FIG. 7 are changed to the first layer metal wire M130 connecting the gate electrode G1 and the gate electrode G2 in FIG. It is done. Further, in the formation region of the memory cell MC10, the first layer metal interconnections M111 and M114 of FIG. 7 are changed to the first layer metal interconnection M131 connecting the gate electrode G1 and the gate electrode G2 in FIG. The other configuration is the same as that shown in FIG.

  FIG. 12 is a diagram showing a layout arrangement of memory cells in which second-level metal interconnections are formed. In FIG. 12, second layer metal interconnections M201 to M208 arranged to extend along the X direction and a first via electrode (via 1) are drawn. In FIG. 12, the reference symbols of the first layer metal wiring are not drawn for simplification of the drawing.

  M201 is a wiring to which the ground potential VSS is supplied, and is connected to M11 and M115 via a first via electrode. M202 is a word line WLo0, and is connected to M131 via a first via electrode. M203 is a wiring to which the power supply potential VDD is supplied, and is connected to M12, M19 and M116 via the first via electrode. M204 is a word line WLe0, and is connected to M130 via the first via electrode. M205 is a wiring to which the ground potential VSS is supplied, and is connected to M110 via the first via electrode. M206 is connected to M13 via the first via electrode. M206 will be connected to bit line BL0. M207 is connected to M18 via the first via electrode. M207 will be connected to bit line BL1. M208 is connected to M117 via the first via electrode. M208 will be connected to bit line BL2.

  FIG. 13 is a diagram showing a layout arrangement of memory cells in which third-layer metal interconnections are formed. In FIG. 3, third-layer metal wirings M301 to M305 arranged to extend along the Y direction and a second via electrode (via 3) are drawn. Incidentally, in FIG. 13, reference symbols of the second layer metal wiring are not drawn for simplification of the drawing.

  M301 is a bit line BL0, and is connected to M206 via a second via electrode. M302 is a power supply wiring to which the power supply potential VDD is supplied, and is connected to M203 via a second via electrode. M303 is a bit line BL1 and is connected to M207 via a second via electrode. M304 is a power supply wiring to which the ground potential VSS is supplied, and is connected to M201 and M205 via a second via electrode. M305 is a bit line BL2 and is connected to M208 via a second via electrode.

  In the modification, the word lines WLo0 and WLe0 are formed by the second layer metal interconnections, and the bit lines BL0, BL1 and BL2 are formed by the third layer metal interconnections. However, the present invention is not limited thereto. The bit lines BL0, BL1, and BL2 may be formed of the second-layer metal interconnections, and the word lines WLo0 and WLe0 may be formed of the third-layer metal interconnections.

  According to the modification, as shown in FIGS. 11 to 13, memory cells using first to third metal interconnections are formed. That is, as compared with the first embodiment, the memory cell is formed of the first to third metal interconnections without using four metal interconnections, so that the manufacturing process of the semiconductor memory device is reduced. it can. This makes it possible to reduce the manufacturing cost of the semiconductor memory device.

(Application example)
FIG. 14 is a block diagram showing the configuration of a semiconductor device according to an application example. FIG. 14 shows a microcomputer which is an example of a semiconductor device IC. The semiconductor device IC includes a single semiconductor chip (semiconductor substrate) 100 such as silicon single crystal, a central processing unit (CPU), a volatile semiconductor memory device SRAM, and a nonvolatile memory device such as a flash memory. NVM, peripheral circuit PERI, interface circuit I / F, and bus BUS interconnecting them are included. The volatile semiconductor memory SRAM is used as a storage area for storing temporary data of the central processing unit CPU. Nonvolatile storage device NVM is used as a storage area for storing a control program executed by central processing unit CPU.

  The semiconductor memory devices 1 and 1a described in the embodiments, examples, and modifications can be used for the volatile semiconductor memory device SRAM.

  Next, Example 2 will be described using the drawings. The second embodiment corresponds to a configuration example in which the first embodiment is applied to TCAM (Ternary Content Addressable Memory) which is one of the content addressable memories.

  FIG. 15 is a diagram for explaining a configuration example of the semiconductor memory device according to the second embodiment. The semiconductor memory device 1b is a TCAM, and is formed, for example, on the surface of a semiconductor substrate such as single crystal silicon by a known CMOS semiconductor manufacturing method. As exemplarily shown, it has a memory array 2b including eight memory cells (MC00 to MC31) arranged in 2 rows and 4 columns. Memory cells MC00 and MC10 constitute one TCAM cell TCEL. Similarly, memory cells MC20 and MC30 constitute one TCAM cell TCEL, memory cells MC01 and MC11 constitute one TCAM cell TCEL, and memory cells MC21 and MC31 constitute one TCAM cell TCEL.

  In FIG. 15, the write operation and the read operation for the memory cell (MC00 to MC31) of the semiconductor memory device 1b are the same as those of the semiconductor memory device 1a of FIG. The semiconductor memory device 1b differs from the semiconductor memory device 1a in FIG. 4 in the match line (ML0, ML1), the search line pair (SL0, / SL0, SL1, / SL1), the match line control circuit MLC, the search line driver This is the point at which the SLD is provided.

  Match line ML0 is connected to memory cells MC00, MC10, MC20, MC30 forming one row. Match line ML1 is connected to memory cells MC01, MC11, MC21 and MC31 forming one row. Match lines ML0 and ML1 are connected to match line control circuit MLC including match amplifier MA.

  Of search line pair SL0 and / SL0, search line / SL0 is connected to memory cells MC00 and MC01 forming one column, and search line SL0 is connected to memory cells MC10 and MC11 forming one column. Of the search line pair SL1 and / SL1, the search line / SL1 is connected to the memory cells MC20 and MC21 forming one column, and the search line SL1 is connected to the memory cells MC30 and MC31 forming one column. The search line pair (SL0, / SL0, SL1, / SL1) is connected to the search line driver SLD, and search data is supplied from the search line driver SLD to the search line pair (SL0, / SL0, SL1, / SL1).

  In FIG. 15, memory cells MC00, MC10, MC20 and MC30 forming one row store one entry data. Similarly, memory cells MC01, MC11, MC21 and MC31 forming one row store one entry data. In the search operation, search data supplied from the search line driver SLD is compared with each entry data to determine a match (match) or a mismatch (mismatch or miss). If the search data supplied from the search line driver SLD is identical to the entry data (match: match), the match lines (ML0, ML1) maintain a precharge level such as high level, for example. On the other hand, if the search data is different from the entry data (mismatch: mismatch or miss), the match line (ML0, ML1) changes, for example, from the precharge level to, for example, the low level. The match amplifier MA included in the match line control circuit MLC detects the potential of the match line (ML0, ML1) and outputs information on match or mismatch.

  FIG. 16 is a diagram showing a circuit example of the TCAM cell TCEL. 16 differs from FIG. 5 in that a data comparison circuit DCMP is provided. Data comparison circuit DCMP includes four N channel MOS transistors (NS0 to NS3). The source / drain path of N channel MOS transistor NS0 and the source / drain path of N channel MOS transistor NS1 are connected in series between match line ML0 and a supply line of ground potential VSS. The gate of N channel MOS transistor NS0 is connected to one (search line SL0) of search line pair (SL0, / SL0). The gate of N channel MOS transistor NS1 is connected to a first storage node MT2 of memory cell MC10. The source / drain path of N channel MOS transistor NS2 and the source / drain path of N channel MOS transistor NS3 are connected in series between match line ML0 and the supply line of ground potential VSS. The gate of N channel MOS transistor NS2 is connected to the other (search line / SL0) of search line pair (SL0, / SL0). The gate of N channel MOS transistor NS3 is connected to the second storage node MB1 of memory cell MC00.

  One TCAM cell TCEL can store three values of “0”, “1” and “*” (don't care) as TCAM data using a 2-bit SRAM cell. For example, when "0" is stored in storage node MB1 of MC00 and "1" is stored in storage node MT2 of MC10, it is assumed that "0" is stored in TCAM cell TCEL. When "1" is stored in the storage node MB1 of MC00 and "0" is stored in the storage node MT2 of MC10, it is assumed that "1" is stored in the TCAM cell TCEL. When "0" is stored in storage node MB1 of MC00 and "0" is stored in storage node MT2 of MC10, it is assumed that "*" (don't care) is stored in TCAM cell TCEL. When "1" is stored in the storage node MB1 of MC00 and "1" is stored in the storage node MT2 of MC10, it is not used.

  Search data is “1” (ie, search line SL0 is “1” and search line / SL0 is “0”), TCAM data is “0” (storage node MB1 is “0”, storage node When MT2 is "1", the MOS transistors NS0 and NS1 are turned on, and the potential of the precharged match line ML is pulled out to the ground potential.

  Search data is “0” (ie, search line SL is “0” and search line SL_n is “1”), TCAM data is “1” (storage node MB1 is “1”, storage node MT2 When “0” is “0”, the MOS transistors NS2 and NS3 are turned on, and the potential of the precharged match line ML is pulled out to the ground potential. That is, when the search data and the TCAM data do not match, the potential of the match line ML is pulled out to the ground potential.

  Conversely, when the input search data is "1" and the TCAM data is "1" or "*", or the search data is "0" and the TCAM data is "0" or In the case of “*” (that is, when both match), the potential (power supply potential VDD level) of the precharged match line ML is maintained.

  As described above, in TCAM, charges accumulated in match line ML are extracted unless data of all TCAM cells connected to match line ML corresponding to one entry (row) match the input search data. . Therefore, although the search in TCAM is fast, there is a problem that the current consumption is large.

  FIG. 17 is a diagram showing a layout arrangement of TCAM cells in which first-layer metal interconnections are formed. FIG. 18 is a diagram showing a layout arrangement of a TCAM cell in which a second layer metal wiring and a third layer metal wiring are formed. In the layout arrangement shown in FIGS. 17 and 18, the layout arrangement of memory cells shown in FIGS. 11 to 13 includes match line (ML0), search line pair (SL0, / SL0), and four N channel MOS transistors (NS0 to NS3). ) Is added. In the following description of FIGS. 17 and 18, parts different from FIGS. 11 to 13 will be mainly described. In FIGS. 17 and 18, the first via electrode (via 1) indicates an electrode connecting the first layer metal interconnection and the second layer metal interconnection, and the second via electrode (via 2) is the second layer metal. The electrode which connects wiring and the 3rd layer metal wiring is shown.

  Referring to FIG. 17, gate electrodes G5 are arranged in the Y direction in the formation regions of memory cells MC00 and MC10, corresponding to the provision of N channel MOS transistors (NS0 to NS3). In addition, the gate electrode G4 is extended along the Y direction. In the formation region of memory cell MC00, gate electrode G5 configures the gate electrode of N channel MOS transistor NS2, and extended gate electrode G4 configures the gate electrode of N channel MOS transistor NS3. In the formation region of memory cell MC10, gate electrode G5 constitutes a gate electrode of N channel MOS transistor NS0, and extended gate electrode G4 constitutes a gate electrode of N channel MOS transistor NS1.

  In the P-type well region PW2, an N-type impurity region N3 is provided along the X direction. N-type impurity region N3 constitutes the source or drain of N-channel MOS transistors NS0, NS1, NS2 and NS3. The N-type impurity region N3 is a semiconductor region into which an N-type impurity is introduced.

  First-layer metal interconnection M140 is connected to gate electrode G5 of N channel MOS transistor NS2 via a contact. M 140 is connected to search line / SL through via 1. First-layer metal interconnection M141 is connected to N-type impurity region N3 forming the source of N-channel MOS transistor NS2 via a contact. M 141 is connected to the ground potential VSS via the via 1. First-layer metal interconnection M142 is connected to N-type impurity region N3 forming the drain of N-channel MOS transistors NS3 and NS1 via a contact. M 142 is to be connected to match line ML via via 1. First-layer metal interconnection M143 is connected to gate electrode G5 of N-channel MOS transistor NS0 via a contact. M143 is connected to the search line SL via the via 1. First-layer metal interconnection M144 is connected to N-type impurity region N3 forming the source of N-channel MOS transistor NS0 via a contact. M 144 is connected to the ground potential VSS via the via 1.

  In FIG. 18, second-layer metal interconnections M209 to M212 and third-layer metal interconnections M306 and M307 are newly provided.

  The second layer metal interconnection M209 connects the gate electrode G5 of the N channel MOS transistor NS2 to the third layer metal interconnection M307 via the via 2. The third-layer metal wiring M307 is a search line / SL disposed between the third-layer metal wiring M302 and the third-layer metal wiring M303 and provided so as to extend along the Y direction. The second layer metal interconnection M210 connects the gate electrode G5 of the N channel MOS transistor NS0 to the third layer metal interconnection M306 via the via 2. The third layer metal wiring M306 is a search line SL disposed between the third layer metal wiring M303 and the third layer metal wiring M304 and provided so as to extend along the Y direction. Second-layer metal interconnection M211 is a match line ML provided to extend along the X direction. The second-layer metal wiring M212 is a ground wiring VSS provided so as to extend along the X direction. M 212 is connected to M 141 and M 144 through via 1, and is also connected to third-layer metal interconnection M 304 through via 2.

  According to the second embodiment, even when using a rectangular memory cell elongated in the Y direction in plan view, the length of the word line can be shortened. Therefore, as in the embodiment and the first embodiment, the parasitic of the word line WL Resistance and parasitic capacitance can be reduced. Therefore, the rising of the word line WL to the selection level can be made faster. Therefore, the address access time for reading data in the semiconductor memory device can be shortened.

  Further, match line ML is arranged in a direction orthogonal to or perpendicular to the arranging direction of gate electrodes (G1-G5), and source lines (SL0, / SL0, SL1, / SL1) are arranged in gate electrodes (G1-G5). And the arrangement direction of the gate electrode (G1-G5) of the memory cell MC. Thereby, the TCAM memory can be configured.

  Ground potential VSS is stabilized by wiring in a mesh shape by second layer metal interconnections M201, M205, and M212 provided in the X direction and third layer metal interconnection M304 provided in the Y direction. Be The power supply potential VDD is stabilized in a mesh shape by the second layer metal wiring M203 provided in the X direction and the third layer metal wiring M302 provided in the Y direction. Ru.

(Modification 2)
Next, a modification of the second embodiment will be described with reference to FIGS.

  In the second modification, the sources of the N-channel MOS transistors NS0 and NS2 included in the data comparison circuit DCMP are connected to the local ground line LVSS separated from the ground potential VSS. Thus, power consumption of the semiconductor memory device due to charging and discharging of match line ML can be reduced.

  FIG. 19 is a diagram for explaining a configuration example of a semiconductor memory device according to the second modification. FIG. 20 is a diagram showing an example of a circuit of a TCAM cell according to the second modification. FIG. 21 is a diagram showing a configuration example and an operation example of the match line control circuit. FIG. 22 is a diagram showing a layout arrangement of TCAM cells in which first-layer metal interconnections are formed. FIG. 23 is a diagram showing a layout arrangement of a TCAM cell in which a second layer metal wiring and a third layer metal wiring are formed.

  19 differs from FIG. 15 in that local ground lines LVSS0 and LVSS1 are provided in memory array 2c of semiconductor memory device 1c, and local ground lines LVSS0 and LVSS1 perform match line control. It is a point connected to the circuit MLCa. Local ground interconnection LVSS0 is connected to memory cells MC00, MC10, MC20, and MC30 forming one row, similarly to match line ML0. Local ground interconnection LVSS1 is connected to memory cells MC01, MC11, MC21, and MC31 forming one row, similarly to match line ML1. The other configuration is the same as that of FIG. 15, and the description will be omitted.

  In FIG. 20, FIG. 20 differs from FIG. 16 in that the sources of N channel MOS transistors NS0 and NS2 included in data comparison circuit DCMP are connected to local ground interconnection LVSS0 separated from ground potential (interconnection) VSS. It is a point. The other configuration is the same as that shown in FIG.

  Since the sources of the N-channel MOS transistors NS0 and NS2 are connected to the local ground wiring LVSS0, the following occurs when the search data and the TCAM data do not match.

  If the search data and the TCAM data do not match, the potential of the match line ML0, which has been precharged to the high level, is turned on by the on operation of the N channel MOS transistors N1 and NS0 or the on operation of the N channel MOS transistors N1 and NS0. , Transition to the low level side. Since the local ground wiring LVSS0 is separated from the ground potential (wiring) VSS, the charge of the match line ML0 raises the potential of the local ground wiring LVSS0 which has been precharged to a low level. That is, charge sharing (charge sharing) is performed between the match line ML0 and the local ground wiring LVSS0. For example, when the parasitic capacitance of match line ML0 and the parasitic capacitance of local ground interconnection LVSS0 are considered to be the same, the potential of match line ML0 and local ground interconnection LVSS0 is an intermediate potential between power supply potential VDD and ground potential VSS. It will be set to a potential such as (1/2) VDD.

  That is, even when the search data and the TCAM data do not match, the potential of the match line ML0 only transitions to a potential such as (1/2) VDD. Further, the potential of the local ground wiring LVSS0 transitions to a potential such as (1/2) VDD. Therefore, the power consumption of a semiconductor device such as an associative memory with many mismatches can be reduced. Also, the precharge of match line ML0 is from a potential such as (1/2) VDD to a power supply potential such as VDD, and the precharge of local ground wiring LVSS0 is from a potential such as (1/2) VDD to VSS With such a potential, it is also possible to reduce the power required for precharging the match line ML0 and the local ground wiring LVSS0. As a result, although the TCAM search is fast, the problem of large current consumption can be solved.

  FIG. 21 is a diagram for describing a configuration example of a match line control circuit. FIG. 21A is a circuit diagram showing a configuration example of a match line control circuit. FIG. 21B is a diagram showing an operation example of the match line control circuit.

  Match line control circuit MLCa is connected to match line ML0 connected to memory cells MC00, MC10, MC20 and MC30 forming one row and to local ground interconnection LVSS0, as exemplarily shown. Match line control circuit MLCa includes control circuit CNT, a pair of precharge MOS transistors Q1 and Q2, a pair of switches SW1 and SW2, a capacitive element C, match amplifier MA, and an output latch circuit LT. Including.

  The precharge MOS transistor Q1 is turned on by the low level precharge enable signal pce to precharge the match line ML0 to a precharge level such as a high level. The precharge MOS transistor Q2 is turned on by the low level precharge enable signal pce to precharge the local ground line LVSS0 to low level. The precharge MOS transistors Q1 and Q2 are turned off by the high level precharge enable signal pce.

  The switch SW1 connects the match line ML0 to the input wiring ctm of the match amplifier MA when turned on by the low level switch enable signal swe, and is turned off by the high level switch enable signal swe, The match line ML0 and the input wiring ctm are not connected. When the switch SW2 is turned on by the low level switch enable signal swe, the local ground wiring LVSS0 is connected to the input wiring cbm of the match amplifier MA, and the switch SW2 is turned off by the high level switch enable signal swe. When this is done, the local ground wiring LVSS and the input wiring cbm are not connected.

  One end of the capacitive element C is connected to the input wiring cbm, and the other end of the capacitive element C is adapted to receive the reference potential generation signal vrefg. When the reference potential generation signal vrefg is set to the high level, the potential of the input wiring cbm connected to one end of the capacitive element C is increased by the bootstrap effect.

  When the power switch transistors Q3 and Q4 of the match amplifier MA are turned on by the high level match amplifier enable signal mae, the match amplifier MA amplifies the level difference of the potentials of the input wirings ctm and cbm. The signal amplified by the match amplifier MA is taken into and held by the output latch circuit LT, and is output from the output latch circuit LT as a match line output signal MLO.

  Control circuit CNT includes inverters IV1 and IV2, and generates precharge enable signal pce based on a precharge control signal from timing control circuit TC. The precharge enable signal pce is generated from the output of the inverter IV2. Therefore, the output of inverter IV1 is the inverted signal of precharge enable signal pce.

  Control circuit CNT also includes delay circuit DL1, inverters IV3 and IV4, and delay circuit DL2, and generates switch enable signal swe and reference potential generation signal vrefg based on the switch control signal from timing control circuit TC. The switch enable signal swe is generated from the output of the inverter IV4. Therefore, the output of the inverter IV3 is the inverted signal of the switch enable signal swe. The reference potential generation signal vrefg is generated from the output of the delay circuit DL2. The input of the delay circuit DL2 is connected to the output of the inverter IV4. The reference potential generation signal vrefg corresponds to a signal obtained by delaying the switch enable signal swe by the delay circuit DL2.

  The control circuit CNT also includes a NOR circuit NOR and an inverter IN5, and generates a match amplifier enable signal mae. The match amplifier enable signal mae is generated from the output of the inverter IN5. The input of the inverter IN5 is an inverted signal of the match amplifier enable signal mae. The input of inverter IN5 is connected to the output of NOR circuit NOR, and the input of NOR circuit NOR receives reference potential generation signal vrefg and a switch control signal from timing control circuit TC.

  Next, the operation of the match line control circuit MLCa will be described with reference to FIG.

  First, the case of a match will be described.

  In the initial state, since the precharge MOS transistors Q1 and Q2 are turned on by the low level of the precharge enable signal pce, the match line ML0 is precharged to the high level, and the local ground wiring LVSS0 is precharged to the low level. It is charged.

  By the transition of the precharge enable signal pce to the high level, the precharge MOS transistors Q1 and Q2 are turned off, and the search data is compared with each entry data. If the search data matches, for example, a plurality of TCAM cells connected to match line ML0, match line ML0 maintains a precharge level such as high level, and local ground interconnection LVSS0 has a precharge level such as low level. maintain. Since the switches SW1 and SW2 are turned on by the low level switch enable signal swe, the potentials of the match line ML0 and the local ground line LVSS0 are transmitted to the input lines ctm and cbm of the match amplifier MA.

  Thereafter, the switch enable signal swe transitions from low level to high level. As a result, the switches SW1 and SW2 are turned off. Then, after a predetermined delay time has elapsed, the reference potential generation signal vrefg temporarily transitions from the low level to the high level. As a result, the potential level of the input wiring cbm temporarily rises from the low level, and then transitions to the low level again. However, the potential of the input wiring cbm does not exceed the high level potential of the input wiring ctm.

  Thereafter, when the match amplifier enable signal mae changes from low level to high level, the potential level of the input wiring ctm, cbm is taken in and amplified, and the output latch circuit TL outputs a match line output signal MLO of high level indicating coincidence. Do.

  Next, the case of non-coincidence (miss) will be described.

  In the initial state, since the precharge MOS transistors Q1 and Q2 are turned on by the low level of the precharge enable signal pce, the match line ML0 is precharged to the high level, and the local ground wiring LVSS0 is precharged to the low level. It is charged.

  By the transition of the precharge enable signal pce to the high level, the precharge MOS transistors Q1 and Q2 are turned off, and the search data is compared with each entry data. If the search data does not match, for example, a plurality of TCAM cells connected to match line ML0, match line ML0 makes a transition from a precharge level such as high level to a low level side, and local ground interconnection LVSS0 such as low level. Transition to the level side where the precharge level does not exist. Then, due to charge distribution (charge sharing) between the match line ML0 and the local ground line LVSS0, the potential of the match line ML0 is set to a potential such as (1/2) VDD and the local ground line LVSS0. The potential transitions to a potential such as (1/2) VDD. Since the switches SW1 and SW2 are turned on by the low level switch enable signal swe, the potentials of the match line ML0 and the local ground line LVSS0 are transmitted to the input lines ctm and cbm of the match amplifier MA.

  Thereafter, the switch enable signal swe transitions from low level to high level. As a result, the switches SW1 and SW2 are turned off. Then, after a predetermined delay time has elapsed, the reference potential generation signal vrefg temporarily transitions from the low level to the high level. As a result, the potential level of the input wiring cbm temporarily rises from a potential such as (1/2) VDD. That is, the potential level of the input wiring cbm becomes a potential exceeding the potential level of the input wiring ctm.

  Thereafter, when the match amplifier enable signal mae changes from low level to high level, the potential level of the input wiring ctm, cbm is taken in and amplified, and the output latch circuit TL outputs a low level match line output signal MLO indicating mismatch. Do.

  According to FIG. 21, even in the configuration in which charge sharing (charge sharing) is performed between match line ML0 and local ground wiring LVSS0, the potential level of input wiring cbm is temporarily verified by the bootstrap. Thus, the output of the match and mismatch can be accurately output from the output latch circuit LT.

  22 differs from FIG. 17 in that the first layer metal interconnections M141 and 144 are shortened in the Y direction and not shared with the adjacent TCAM cell, and each of the first layer metal interconnections M141 and 144 is different. This is a point to be connected to the local ground wiring LVSS0 through the via 1. The other configuration is the same as that shown in FIG.

  23, the difference between FIG. 23 and FIG. 18 is that the via 2 connecting the second-layer metal interconnection M212 and the third-layer metal interconnection M304 is deleted, and the second-layer metal interconnection M212 is different from the local ground interconnection LVSS0. It is the point that is done. The other configuration is the same as that shown in FIG.

  Next, Example 3 will be described using the drawings. The third embodiment corresponds to a configuration example in which the first embodiment or the second embodiment is applied to a binary content addressable memory (BCAM) which is one of the content addressable memories.

  FIG. 24 is a diagram of a configuration example of a semiconductor memory device according to the third embodiment. The semiconductor memory device 1d is BCAM, and is formed, for example, on the surface of a semiconductor substrate such as single crystal silicon by a known CMOS semiconductor manufacturing method. As exemplarily shown, it has a memory array 2d including eight memory cells (MC00 to MC31) arranged in 2 rows and 4 columns.

  In FIG. 24, FIG. 24 differs from FIG. 19 in that a pair of search lines is connected to each of the memory cells (MC00 to MC31). That is, search line pair SL0, / SL0 is connected to memory cells MC00, MC01 forming one column. Similarly, search line pair SL1 and / SL1 are connected to memory cells MC10 and MC11 forming one column, and search line pair SL2 and / SL2 are connected to memory cells MC20 and MC21 forming one column, search line pair SL3 and / SL3 are connected to memory cells MC30 and MC31 forming one column. The other configuration is the same as that of FIG.

  FIG. 25 is a diagram of a circuit example of a memory cell of BCAM according to the third embodiment. FIG. 25 exemplarily shows the configuration of memory cells MC00 and MC10. As shown in FIG. 25, data comparison circuit DCMP0 is provided in memory cell MC00, and data comparison circuit DCMP1 is provided in memory cell MC10.

  Data comparison circuit DCMP0 includes four N channel MOS transistors (NS0 to NS3). The source / drain path of N channel MOS transistor NS0 and the source / drain path of N channel MOS transistor NS1 are connected in series between match line ML0 and a supply line of ground potential VSS. The gate of N channel MOS transistor NS0 is connected to search line SL0. The gate of N channel MOS transistor NS1 is connected to a first storage node MB1 of memory cell MC00. The source / drain path of N channel MOS transistor NS2 and the source / drain path of N channel MOS transistor NS3 are connected in series between match line ML0 and the supply line of ground potential VSS. The gate of N channel MOS transistor NS2 is connected to search line / SL0. The gate of N channel MOS transistor NS3 is connected to the second storage node MT1 of memory cell MC00.

  Data comparison circuit DCMP1 includes four N channel MOS transistors (NS01 to NS31). The source / drain path of N channel MOS transistor NS01 and the source / drain path of N channel MOS transistor NS11 are connected in series between match line ML0 and a supply line of ground potential VSS. The gate of N channel MOS transistor NS01 is connected to search line SL1. The gate of N channel MOS transistor NS11 is connected to a first storage node MB1 of memory cell MC10. The source / drain path of N channel MOS transistor NS21 and the source / drain path of N channel MOS transistor NS31 are connected in series between match line ML0 and the supply line of ground potential VSS. The gate of N channel MOS transistor NS21 is connected to search line / SL1. The gate of N channel MOS transistor NS31 is connected to a second storage node MT2 of memory cell MC10.

  FIG. 26 is a diagram showing a layout arrangement of memory cells of the BCAM in which the first-layer metal interconnections are formed. FIG. 27 is a diagram showing a layout arrangement of a BCAM memory cell in which a second layer metal interconnection is formed. In the following description, the same reference symbols as in the embodiment, the first embodiment, the modification, the second embodiment, and the second modification may be used, but may be different.

  FIG. 26 exemplarily shows the layout configuration of memory cell MC00. The layout shown in FIG. 26 is also applicable to memory cells MC20, MC01, MC21.

  In the formation region of memory cell MC00, there are two P-type well regions PW1 and PW2 provided along the X direction, and an N-type well region NW provided between two P-type well regions PW1 and PW2. It is formed on the surface of a semiconductor substrate. The P-type well regions PW1 and PW2 are semiconductor regions into which P-type impurities are introduced, and the N-type well regions NW are semiconductor regions into which N-type impurities are introduced.

  Six gate electrodes (G1 to G6) are arranged in the Y direction in the formation region of memory cell MC00. Gate electrode G1 constitutes a gate electrode of N channel MOS transistor NT1. Gate electrode G2 constitutes a gate electrode of N channel MOS transistor NT2. Gate electrode G3 constitutes a gate electrode of P channel MOS transistor PM1, N channel MOS transistor ND1 and N channel MOS transistor NS3. Gate electrode G4 constitutes a gate electrode of P channel MOS transistor PM2, N channel MOS transistor ND2 and N channel MOS transistor NS1. Gate electrode G5 constitutes a gate electrode of N channel MOS transistor NS0. Gate electrode G6 constitutes a gate electrode of N channel MOS transistor NS2.

  In the P-type well region PW1, an N-type impurity region N1 is provided along the X direction. N-type impurity region N1 constitutes the source or drain of N-channel MOS transistors NT1, ND1, ND2, and NT1. In the P-type well region PW2, an N-type impurity region N2 is provided along the X direction. N-type impurity region N2 constitutes the source or drain of N-channel MOS transistors NS2, NS3, NS1, and NS0. The N-type impurity regions N1 and N2 are semiconductor regions into which N-type impurities are introduced.

  In the N-type well region NW, a P-type impurity region P1 is provided along the X direction. The P-type impurity region P1 is a semiconductor region into which a P-type impurity is introduced. P-type impurity region P1 constitutes the source or drain of P-channel MOS transistor PM1 and P-channel MOS transistor PM2.

  As shown in FIG. 26, first layer metal interconnections (M11 to M19, M110 to M112) are provided in the formation region of the memory cell MC00. The first-layer metal interconnection M11 configures a word line WLe0 provided along the X direction, and is connected to the gate electrodes G1 and G2 through contacts. The first-layer metal interconnection M12 configures a word line WLo0 provided along the X direction. The first-layer metal interconnection M12 is connected to the gate electrodes G1 and G2 through contacts in the formation region of the memory cell MC10. Although not shown, the layout of the formation region of memory cell MC10 is configured in the same manner as the layout shown in FIG. First-layer metal interconnection M13 is connected to the source or drain of N-channel MOS transistor NT2 via a contact. The first-layer metal interconnection M13 is connected to the bit line BL0. First layer metal interconnection M14 is connected to the source or drain of N channel MOS transistor NT1 via a contact. The first-layer metal interconnection M14 is connected to the bit line BL1. First-layer metal interconnection M15 constitutes match line ML0 provided along the X direction. The first-layer metal interconnection M15 is connected to the drains of the N-channel MOS transistors NS3 and NS4 through contacts. The first-layer metal interconnection M16 constitutes a ground potential interconnection VSS provided along the X direction. First layer metal interconnection M16 is connected to the sources of N channel MOS transistors NS2 and NS0 via a contact. The first-layer metal interconnection M17 is connected to the gate electrode G5 via a contact. The first-layer metal interconnection M17 is connected to the search line SL0. The first-layer metal interconnection M18 is connected to the gate electrode G6 via a contact. First layer metal interconnection M18 is connected to search line / SL0. The first-layer metal interconnection M19 is connected to the drain of the P-channel MOS transistor PM2, the drain of the N-channel MOS transistor ND2, and the gate electrode G3 through contacts. The first-layer metal interconnection M110 is connected to the drain of the P-channel MOS transistor PM1, the drain of the N-channel MOS transistor ND1, and the gate electrode G4 through contacts. The first-layer metal interconnection M111 is connected to the drains of the P-channel MOS transistors PM1 and PM2 through contacts. The first-layer metal interconnection M111 is connected to the power supply potential interconnection VDD. The first-layer metal interconnection M112 is connected to the drains of the N-channel MOS transistors ND1 and ND2 through contacts. The first-layer metal interconnection M112 is connected to the ground potential interconnection VSS.

  As shown in FIG. 27, second-layer metal interconnections (M20 to M25) are provided along the Y direction in the formation region of memory cell MC00. The second-layer metal interconnection M20 constitutes a bit line BL1. The second-layer metal wiring M20 is connected to the first-layer metal wiring M14 through the via 1. Second-layer metal interconnection M21 configures search line / SL0. The second layer metal wiring M21 is connected to the first layer metal wiring M18 via the via 1. The second-layer metal interconnection M22 constitutes a ground potential interconnection VSS. The second-layer metal interconnection M22 is connected to the first-layer metal interconnections M16 and M112 through the via 1. The second-layer metal wiring M23 constitutes a power supply potential wiring VDD. The second layer metal wiring M23 is connected to the first layer metal wiring M111 through the via 1. Second-layer metal interconnection M24 configures search line SL0. The second layer metal wiring M24 is connected to the first layer metal wiring M17 via the via 1. Second-layer metal interconnection M25 configures bit line BL0. The second-layer metal wiring M25 is connected to the first-layer metal wiring M13 via the via 1.

  According to the layout configuration of the third embodiment, the following effects can be obtained.

  The word lines WLe0 and WLo0 are wired in the Y direction (vertical direction) using the first-layer metal interconnections (M11 and M12). The search line pair (SL0, / SL0) and the bit line pair (BL0, BL1) are wired in the X direction (horizontal direction) using the second layer metal interconnections (M24, M21, M25, M20). The third-layer metal interconnection is not necessary in the configuration of the memory cell of FIGS. 24 and 25. Therefore, a memory cell can be realized with a small number of wiring layers. Therefore, for example, third-layer metal interconnections and metal interconnections such as fourth and fifth-layers higher than that can be used as interconnection regions (interconnections) for signals and the like.

  If necessary, the ground potential wiring VSS and the power supply potential wiring VDD may be formed of the third-layer metal wiring to stabilize the power supply potential and the ground potential.

  Further, since the match line ML0 and the search lines SL0 and / SL0 can be further wired in the lower layer, parasitic capacitance generated in the via portion for raising the upper layer can be reduced. Therefore, the total load capacitance of match line ML0 and search lines SL0 and / SL0 can be reduced. As a result, reduction in power and speeding up of the BCAM search operation can be expected.

(Modification 3)
Next, a modification of the third embodiment will be described with reference to FIGS. The third modification is a configuration example in which the configurations of the local ground wiring LVSS and the match line control circuit MLCa described in the second modification are applied to the BCAM of the third embodiment.

  FIG. 28 is a diagram showing a circuit example of a memory cell of BCAM according to the third modification. FIG. 29 is a diagram showing a layout arrangement of BCAM memory cells in which first-layer metal interconnections are formed. FIG. 30 is a diagram showing a layout arrangement of BCAM memory cells in which second-level metal interconnections are formed.

  In FIG. 28, FIG. 28 differs from FIG. 25 in that the sources of N channel MOS transistors NS0, NS2, NS01, NS21 are connected to the local ground line LVSS. The other configuration is the same as that shown in FIG.

  29, FIG. 29 is different from FIG. 26 in that the first-layer metal interconnection M16 is used as the local ground interconnection LVSS. The other configuration is the same as that shown in FIG.

  30 differs from FIG. 27 in that the second-layer metal interconnection M22 is connected only to the first-layer metal interconnection M112 (the second-layer metal interconnection M22 is a via 1). Point not connected to the first layer metal wiring M16). The other configuration is the same as that shown in FIG.

  According to the third modification, the effect of the third embodiment and the effect of the second modification of the second embodiment can be obtained.

(Modification 4)
Next, the modification of Example 3 is demonstrated using FIG. 31 and FIG. In the fourth modification, the two P-type well regions PW1 and PW2 described in FIG. 26 (Modification 2 of the third embodiment) are formed into one P-type well region PW and are formed in the P-type well region PW1. The N-type impurity region N1 which has been formed is formed in the P-type well region PW. FIG. 31 is a diagram showing a layout arrangement of memory cells of a BCAM in which a first-layer metal interconnection is formed according to the fourth modification. FIG. 32 is a diagram showing a layout arrangement of memory cells of a BCAM in which second-layer metal interconnections according to the fourth modification are formed.

  As shown in FIG. 31, in the formation region of memory cell MC00, N-type impurity regions N1 and N2 are arranged in parallel in the X direction in P-type well region PW. N-type impurity region N1 is arranged between P-type impurity region P1 and N-type impurity region N2. Therefore, N channel MOS transistors NT1, ND1, ND2 and NT1 are arranged between P channel MOS transistors PM1 and PM2 and N channel MOS transistors NS0 to NS3. The N-type well region NW is shared with a memory cell formed on the left side in plan view. In addition, the P-type well region PW is shared with a memory cell formed on the right in plan view. The other configuration is the same as that of FIG.

  32 differs from FIG. 27 in that the arrangement position of P channel MOS transistors PM1 and PM2 and the arrangement position of N channel MOS transistors NT1, ND1, ND2 and NT2 are changed. The connection position between layer metal interconnection M112 and second layer metal interconnection M22 (ground potential interconnection VSS), and the connection position between first layer metal interconnection M111 and second layer metal interconnection M23 (power supply potential interconnection VDD) are changed. ing. The other configuration is the same as that of FIG.

  According to the fourth modification, as shown in FIG. 31, the thin strip-shaped N-type well region NW shown in FIG. 26 (the second modification of the third embodiment) disappears, and a relatively thick N-type well shared with adjacent cells Region NW and P-type well region PW will be obtained. Therefore, since process control at the time of formation of the N-type and P-type well regions NW and PW becomes relatively easy, the manufacture of the N-type and P-type well regions NW and PW can be facilitated.

(Modification 5)
Next, the modification of Example 3 is demonstrated using FIG. 33A, FIG. 33B, and FIG. In the fifth modification, the configuration of the local ground wiring LVSS0 and the match line control circuit MLCa described in the second modification is applied to the layout arrangement of the memory cells of the fourth modification. FIGS. 33A and 33B are diagrams showing a layout arrangement of memory cells of the BCAM in which the first layer metal interconnections according to the fifth modification are formed. The memory cell shown in FIG. 33B corresponds to the memory cell MC10 adjacent to the memory cell MC00 shown in FIG. 33A in the X direction. FIG. 34 is a diagram showing a layout arrangement of memory cells of the BCAM in which the second-layer metal interconnections according to the fifth modification are formed.

  33A and 33B, FIGS. 33A and 33B differ from FIG. 31 in that the first-layer metal interconnection M16 is used as the local ground interconnection LVSS0. The other configuration is the same as that shown in FIG.

  In memory cell MC00 shown in FIG. 33A, first-layer metal interconnection M11, which is word line WLe0, is connected to gate electrodes G1 and G2 through contacts. On the other hand, in the memory cell MC10 shown in FIG. 33B, the first-layer metal interconnection M12 which is the word line WLo0 is connected to the gate electrodes G1 and G2 through the contacts.

  34 differs from FIG. 32 in that the second-layer metal interconnection M22, which is the ground potential interconnection VSS, is connected only to the first-layer metal interconnection M112 through the via 1 (the Second metal wiring M22 is not connected to first metal wiring M16 through via 1). The other configuration is the same as that of FIG. 32, so the description will be omitted.

  According to the fifth modification, the same effect as the second and fourth modifications can be obtained.

  A fourth embodiment will now be described with reference to FIGS. 35 and 36. In the second embodiment, the TCAM cell TCEL is configured using two memory cells MC00 and MC10. The fourth embodiment configures a TCAM cell TCEL using two memory cells MC00 and MC01. Also, the layout arrangement of the memory cells uses the fourth modification (FIG. 31). FIG. 35 is a diagram showing a layout arrangement of TCAM memory cells in which first-layer metal interconnections according to a fourth embodiment are formed. FIG. 36 is a diagram showing a layout arrangement of TCAM memory cells in which second-layer metal interconnections according to the fifth embodiment are formed.

  In FIG. 35, in the TCAM cell TCEL, two N-type well regions NW1 and NW2 provided along the X direction and a P-type well region PW provided between the N-type well regions NW1 and NW2 are semiconductors. It is formed on the surface of the substrate.

  In the formation region of memory cell MC00, five gate electrodes (G1-G5) are arranged along the Y direction. Gate electrode G1 constitutes a gate electrode of N channel MOS transistor NT1. Gate electrode G2 constitutes a gate electrode of N channel MOS transistor NT2. Gate electrode G3 constitutes a gate electrode of P channel MOS transistor PM1, N channel MOS transistor ND1 and N channel MOS transistor NS3. Gate electrode G4 constitutes a gate electrode of P channel MOS transistor PM2, N channel MOS transistor ND2 and N channel MOS transistor NS3. Gate electrode G5 constitutes a gate electrode of N channel MOS transistor NS2.

  Five gate electrodes (G1-G5) are arranged in the Y direction in the formation region of memory cell MC01. Gate electrode G1 constitutes a gate electrode of N channel MOS transistor NT1. Gate electrode G2 constitutes a gate electrode of N channel MOS transistor NT2. Gate electrode G3 constitutes a gate electrode of P channel MOS transistor PM1, N channel MOS transistor ND1 and N channel MOS transistor NS3. Gate electrode G4 constitutes a gate electrode of P channel MOS transistor PM2, N channel MOS transistor ND2 and N channel MOS transistor NS1. Gate electrode G5 constitutes a gate electrode of N channel MOS transistor NS0.

  In the P-type well region PW, N-type impurity regions N1, N2, and N3 are provided to be separated along the X direction. N-type impurity region N1 constitutes the source or drain of N-channel MOS transistors NT1, ND1, ND2, NT1 of memory cell MC00. N-type impurity region N2 configures the source or drain of N-channel MOS transistors NS2, NS3, NS1, and NS0 included in data comparison circuit DCMP. N-type impurity region N3 constitutes the source or drain of N-channel MOS transistors NT1, ND1, ND2, NT1 of memory cell MC01.

  In the N-type well region NW1, a P-type impurity region P1 is provided along the X direction. P-type impurity region P1 constitutes the source or drain of P-channel MOS transistor PM1 and P-channel MOS transistor PM2 of memory cell MC00.

  In the N-type well region NW2, a P-type impurity region P2 is provided along the X direction. P-type impurity region P2 constitutes the source or drain of P-channel MOS transistor PM1 and P-channel MOS transistor PM2 of memory cell MC01.

  As shown in FIG. 35, first layer metal interconnections (M11 to M19, M110 to M112, m11 to m14, m19, and m110 to m112) are provided in the formation regions of the memory cells MC00 and MC01.

  First, the first-layer metal interconnections (M11 to M19 and M110 to M112 will be described. The first-layer metal interconnection M11 constitutes the word line WLe0 provided along the X direction, and the gate electrodes G1 and G2 are formed. The first-layer metal interconnection M12 forms a word line WLo0 provided along the X direction, and the first-layer metal interconnection M12 is formed in the formation region of the memory cell MC10. First layer metal interconnection M13 is connected to the source or drain of N channel MOS transistor NT2 via a contact. Is connected to bit line BL 0. First layer metal interconnection M 14 is the source or drain of N channel MOS transistor NT 1. The first-layer metal interconnection M14 is connected to the bit line BL1 through a contact, and the first-layer metal interconnection M15 is a match line provided along the X direction. The first-layer metal interconnection M15 is connected to the drains of the N-channel MOS transistors NS3 and NS4 via contacts.The first-layer metal interconnection M16 is provided along the X direction. The first layer metal interconnection M16 is connected to the sources of the N channel MOS transistors NS2 and NS0 via a contact, and the first layer metal interconnection M17 forms the memory cell MC01. The first-layer metal interconnection M17 is connected to the gate electrode G5 in the region through a contact The first-layer metal interconnection M17 is connected to the search line SL0. 8 is connected via contact to gate electrode G5 in the formation region of memory cell MC01 First layer metal interconnection M18 is connected to search line / SL0 First layer metal interconnection M19 Is connected via a contact to the drain of P channel MOS transistor PM2, the drain of N channel MOS transistor ND2, and gate electrode G3 The first-layer metal interconnection M110 is the drain of P channel MOS transistor PM1, The first layer metal interconnection M111 is connected to the drains of P channel MOS transistors PM1 and PM2 through contacts. The first-layer metal wiring M111 is connected to the power supply potential wiring VDD. Will be The first-layer metal interconnection M112 is connected to the drains of the N-channel MOS transistors ND1 and ND2 through contacts. The first-layer metal interconnection M112 is connected to the ground potential interconnection VSS.

  Next, first-layer metal interconnections (m11 to m14, m19, and m110 to m112) in the formation region of the memory cell MC01 will be described. The first-layer metal interconnection m11 configures a word line WLe1 provided along the X direction, and is connected to the gate electrodes G1 and G2 through contacts. The first-layer metal interconnection m12 configures a word line WLo1 provided along the X direction. The first-layer metal interconnection m12 is connected to the gate electrodes G1 and G2 through contacts in the formation region of the memory cell MC11. First layer metal interconnection m13 is connected to the source or drain of N channel MOS transistor NT2 via a contact. The first-layer metal interconnection m13 is connected to the bit line BL0. First layer metal interconnection m14 is connected to the source or drain of N channel MOS transistor NT1 via a contact. The first-layer metal interconnection m14 is connected to the bit line BL1. The first-layer metal interconnection m19 is connected to the drain of the P-channel MOS transistor PM2, the drain of the N-channel MOS transistor ND2, and the gate electrode G3 through contacts. The first-layer metal interconnection m110 is connected to the drain of the P-channel MOS transistor PM1, the drain of the N-channel MOS transistor ND1, and the gate electrode G4 through contacts. The first-layer metal interconnection m111 is connected to the drains of the P-channel MOS transistors PM1 and PM2 through contacts. The first-layer metal interconnection m111 is connected to the power supply potential interconnection VDD. The first-layer metal interconnection m112 is connected to the drains of the N-channel MOS transistors ND1 and ND2 through contacts. The first-layer metal interconnection m112 is connected to the ground potential interconnection VSS.

  As shown in FIG. 36, second-layer metal interconnections (M20 to M25) are provided along the Y direction in the formation regions of memory cells MC00 and MC01.

  The second-layer metal interconnection M20 constitutes a bit line BL1. The second-layer metal wiring M20 is connected to the first-layer metal wirings M14 and m14 through the via 1. Second-layer metal interconnection M21 configures search line / SL0. The second layer metal wiring M21 is connected to the first layer metal wiring M18 via the via 1. The second-layer metal interconnection M22 constitutes a ground potential interconnection VSS. The second-layer metal interconnection M22 is connected to the first-layer metal interconnections M16, M112, and m112 through the vias 1. The second-layer metal wiring M23 constitutes a power supply potential wiring VDD. The second-layer metal wiring M23 is connected to the first-layer metal wirings M111 and m111 through the vias 1. Second-layer metal interconnection M24 configures search line SL0. The second layer metal wiring M24 is connected to the first layer metal wiring M17 via the via 1. Second-layer metal interconnection M25 configures bit line BL0. The second-layer metal wiring M25 is connected to the first-layer metal wirings M13 and m13 through the vias 1.

  When the configurations of the local ground wiring LVSS0 and the match line control circuit MLCa described in the second modification are applied, the first-layer metal wiring M16 is used as the local ground wiring LVSS0. In this case, the via 1 of the corresponding portion is deleted so that the first layer metal wiring M16 is not connected to the second layer metal wiring M22 via the via 1.

  Example 5 will be described next with reference to FIGS. 37 and 39. The fifth embodiment is an application example to the two-port memory cell 2PCEL. FIG. 37 is a diagram of a circuit example of a two-port memory cell according to a fifth embodiment. FIG. 38 shows a layout of a 2-port memory cell in which a first-layer metal interconnection is formed. FIG. 39 is a diagram showing a layout arrangement of a 2-port memory cell in which second-layer metal interconnections and third-layer metal interconnections are formed.

  37 differs from FIG. 5 in that two N channel MOS transistors (NS3 and NS2 or NS1 and NS0) for the read port are provided in the memory cells MC00 and MC10. Along with this, two word lines RWL0 and RWL1 for read ports and a bit line RBL for read ports are provided. Word lines WLo0 and WLe0 can be word lines for write ports.

  In memory cell MC00, the source / drain path of N channel MOS transistor NS2 and the source / drain path of N channel MOS transistor NS3 are connected in series between bit line RBL and ground potential interconnection VSS. The gate of the N channel MOS transistor NS2 is connected to the read port word line RWL1. The gate of N channel MOS transistor NS3 is connected to the second storage node MB1 of memory cell MC00.

  In memory cell MC10, the source / drain path of N channel MOS transistor NS0 and the source / drain path of N channel MOS transistor NS1 are connected in series between bit line RBL and ground potential interconnection VSS. The gate of N channel MOS transistor NS0 is connected to read port word line RWL0. The gate of N channel MOS transistor NS1 is connected to a first storage node MT2 of memory cell MC10.

  With the above configuration, a two-port memory cell 2PCEL is configured. For example, in memory cell MC00, when second storage node MB1 stores high level "1", N channel MOS transistors NS2 and NS3 are turned on when word line RWL1 is set to a selection level such as high level. Since the state is set, the potential of the bit line RBL precharged to the high level transitions to the low level side. Thereby, data stored in memory cell MC00 is read to bit line RBL. In the memory cell MC00, when the second storage node MB1 stores the low high level "0", when the word line RWL1 is set to the selection level such as the high level, the N channel MOS transistor NS2 is turned on. However, the N channel MOS transistor NS3 maintains the off state. Therefore, the potential of bit line RBL precharged to the high level is maintained. Thereby, data stored in memory cell MC00 is read to bit line RBL.

  In FIG. 38, FIG. 38 differs from FIG. 11 in that the gate electrode G4 is extended in the Y direction in the formation region of the memory cell MC00 and the memory cell MC10, and the gate electrode G5 is provided along the Y direction. The point is that the N-type impurity region N3 is formed in the P-type well region PW2 and the point that the first-layer metal interconnection M140-M144 is newly provided. Thereby, two N-channel MOS transistors (NS3 and NS2 or NS1 and NS0) for the read port are formed in the formation regions of the memory cell MC00 and the memory cell MC10. The other configuration is the same as that shown in FIG.

  In FIG. 38, N-type impurity region N3 constitutes the source or drain of N-channel MOS transistors (NS2, NS3, NS1, NS0). In the formation region of memory cell MC00, gate electrode G5 configures the gate of N channel MOS transistor NS2. In the formation region of memory cell MC10, gate electrode G5 constitutes the gate of N channel MOS transistor NS1.

  First-layer metal interconnection M140 is connected to N-type impurity region N3 forming the drain of N-channel MOS transistors NS3 and NS1 via a contact. The first-layer metal interconnection M140 is connected to the bit line RBL through the via 1. First layer metal interconnection M141 is connected to the gate of N channel MOS transistor NS2 via a contact. The first-layer metal interconnection M 141 is connected to the word line RWL 1 through the via 1. First-layer metal interconnection M142 is connected to N-type impurity region N3 forming the source of N-channel MOS transistor NS3 via a contact. The first layer metal interconnection M 142 is connected to the ground potential interconnection VSS through the via 1. First layer metal interconnection M143 is connected to the gate of N channel MOS transistor NS0 via a contact. The first-layer metal interconnection M143 is connected to the word line RWL0 via the via 1. First-layer metal interconnection M144 is connected to N-type impurity region N3 forming the source of N-channel MOS transistor NS0 via a contact. The first layer metal interconnection M 144 is connected to the ground potential interconnection VSS through the via 1.

  39 is different from FIG. 13 in that second layer metal interconnections M210 to M213 are provided along the Y direction, and third layer metal interconnections M306 to 307 are provided along the X direction. It is a point. The other configuration is the same as that shown in FIG.

  In FIG. 39, second-layer metal interconnection M210 forms word line RWL0. The second layer metal wiring M210 is connected to the first layer metal wiring M143 via the via 1. Second-layer metal interconnection M211 configures word line RWL1. The second layer metal wiring M211 is connected to the first layer metal wiring M143 via the via 1. The second-layer metal interconnection M212 is a ground potential interconnection VSS. The ground potential wiring VSS is connected to the first-layer metal wirings M142 and M144 via the via 1. The second layer metal wiring M213 is connected to the first layer metal wiring M140 via the via 1. Second layer metal interconnection M213 is connected to third layer metal interconnection M306 via via 2.

  Third-layer metal interconnection M306 configures bit line RBL. Third-layer metal interconnection M306 is disposed to run parallel between bit line BL1 (M303) and ground potential interconnection VSS (M304). The third-layer metal interconnection M307 is a passing interconnection, and is disposed to run parallel between the power supply potential interconnection VDD (M302) and the bit line BL1 (M303). The third-layer metal wiring M307 may not be provided.

  According to the fifth embodiment, it is possible to configure a two-port memory capable of obtaining the same effects as those of the embodiment and the first embodiment.

  A sixth embodiment will now be described with reference to FIGS. 40 and 41. In the sixth embodiment, the layout arrangement of memory cells of the BCAM according to the fourth modification of FIG. 31 is arranged using the structure of FinFET. FIG. 40 is a diagram showing a layout arrangement of memory cells of the BCAM in which the first-layer metal interconnections according to the sixth embodiment are formed. FIG. 41 is a diagram showing a layout arrangement of memory cells of the BCAM in which the second-layer metal interconnections according to the sixth embodiment are formed. The circuit configuration of the BCAM memory cell is the same as that shown in FIG.

  In FIG. 40, in the formation region of memory cell MC00, gate electrodes G1 to G6 provided along the Y direction, an N-type well region NW provided along the X direction, and an N-type well region NW are adjacent. And a P-type well region PW provided along the X direction. The N-type well region NW is shared with a memory cell formed on the left side in plan view. The P-type well region PW is provided along the Y direction, and is shared with a memory cell formed on the right in plan view. In the formation region of memory cell MC00, a local interconnect wiring (LIC1-LIC11) as a zeroth layer metal wiring provided along the Y direction, and a first layer metal wiring (along the X direction) M11-M19, M110-M112).

  Gate electrode G1 constitutes the gate of N channel MOS transistor NT1. Gate electrode G2 configures the gate of N channel MOS transistor NT2. Gate electrode G3 constitutes the gate of P channel MOS transistor PM1, N channel MOS transistor ND1 and N channel MOS transistor NS3. Gate electrode G4 constitutes the gate of P channel MOS transistor PM2, N channel MOS transistor ND2 and N channel MOS transistor NS1. Gate electrode G5 constitutes the gate of N channel MOS transistor NS0. Gate electrode G6 constitutes a gate of N channel MOS transistor NS2.

  In N-type well region NW, P-type impurity region P1 is arranged along the X direction. P-type impurity region P1 serves as the source or drain of P-channel MOS transistors PM1 and PM2.

  In the P-type well region PW, N-type impurity regions N11, N12, N21, N22 and N23 are arranged in parallel in the X direction. N-type impurity regions N11 and N12 are arranged between P-type impurity region P1 and N-type impurity region N21. N-type impurity regions N11 and N12 form the source or drain of N-channel MOS transistors NT1, ND1, ND2 and NT2. Each of the N-channel MOS transistors NT1, ND1, ND2 and NT2 has a configuration in which two transistors are connected in parallel.

  N-type impurity regions N21, N22 and N23 form the source or drain of N channel MOS transistors NS0 to NS3. Each of N-channel MOS transistors NS0 to NS3 is configured such that three transistors are connected in parallel. N channel MOS transistors NT1, ND1, ND2 and NT2 are arranged between P channel MOS transistors PM1 and PM2 and N channel MOS transistors NS0 to NS3.

  First-layer metal interconnection M11 configures word line WLe0. M11 is connected to the gate electrodes G1 and G2 through contacts. First-layer metal interconnection M12 configures word line WLo0. M12 is connected to gate electrodes G1 and G2 through contacts in the formation region of memory cell MC10. The first-layer metal wiring M13 is connected to the LIC 4 via a contact. The LIC 4 is connected to N-type impurity regions N11 and N12 that constitute the source of the N-channel MOS transistor NT2. M13 is to be connected to bit line BL1. The first-layer metal wiring M14 is connected to the LIC 5 via a contact. The LIC 5 is connected to N-type impurity regions N11 and N12 that constitute the source of the N-channel MOS transistor NT1. M14 is to be connected to bit line BL0. First-layer metal interconnection M15 constitutes match line ML0. M15 is connected to LIC 9 via a contact. The LIC 9 is connected to N-type impurity regions N21, N22 and N23 which constitute the drains of the N-channel MOS transistors NS1 and NS3. The first-layer metal wiring M16 is connected to the LIC 7 and the LIC 11 through contacts. The LIC 7 is connected to N-type impurity regions N21, N22, and N23 that constitute the source of the N-channel MOS transistor NS0. The LIC 11 is connected to N-type impurity regions N21, N22, and N23 that constitute the source of the N-channel MOS transistor NS2. M16 is connected to the ground potential wiring VSS. The first-layer metal interconnection M17 is connected to the gate electrode G5 via a contact. M17 is connected to search line SL0. The first-layer metal interconnection M18 is connected to the gate electrode G6 via a contact. M18 is to be connected to search line / SL0. The first-layer metal wiring M19 is connected to the gate electrode G3 and the LIC 3 through contacts. The LIC 3 is connected to a P-type impurity region P 1 forming the drain of the P-channel MOS transistor PM 2 and N-type impurity regions N 11 and N 12 forming the drain of the N-channel MOS transistor ND 2. The first-layer metal interconnection M110 is connected to the gate electrode G4 and the LIC 2 through contacts. The LIC 2 is connected to a P-type impurity region P 1 forming the drain of the P-channel MOS transistor PM 1 and N-type impurity regions N 11 and N 12 forming the drain of the N-channel MOS transistor ND 1. The first-layer metal wiring M111 is connected to the LIC 1 via a contact. The LIC1 is connected to a P-type impurity region P1 that constitutes a source of the P-channel MOS transistors PM1 and PM2. M111 is connected to the power supply potential wiring VDD. The first-layer metal wiring M112 is connected to the LIC 6 via a contact. The LIC 6 is connected to N-type impurity regions N11 and N12 that form the sources of the N-channel MOS transistors ND1 and ND2. The LIC 8 is connected to the drain of the N-channel MOS transistor NS 2 or N-type impurity regions N 21, N 22, N 23 constituting the source of the N-channel MOS transistor NS 3. The LIC 10 is connected to N-type impurity regions N21, N22, and N23 forming the drain of the N-channel MOS transistor NS0 or the source of the N-channel MOS transistor NS1.

  In FIG. 41, as shown in FIG. 27, second-layer metal interconnections (M20 to M25) are provided along the Y direction in the formation region of memory cell MC00.

  The second-layer metal interconnection M20 constitutes a bit line BL1. The second-layer metal wiring M20 is connected to the first-layer metal wiring M14 through the via 1. Second-layer metal interconnection M21 configures search line / SL0. The second layer metal wiring M21 is connected to the first layer metal wiring M18 via the via 1. The second-layer metal interconnection M22 constitutes a ground potential interconnection VSS. The second-layer metal interconnection M22 is connected to the first-layer metal interconnections M16 and M112 through the via 1. The second-layer metal wiring M23 constitutes a power supply potential wiring VDD. The second layer metal wiring M23 is connected to the first layer metal wiring M111 through the via 1. Second-layer metal interconnection M24 configures search line SL0. The second layer metal wiring M24 is connected to the first layer metal wiring M17 via the via 1. Second-layer metal interconnection M25 configures bit line BL0. The second-layer metal wiring M25 is connected to the first-layer metal wiring M13 via the via 1.

  When the configuration of the local ground wiring LVSS and the match line control circuit MLCa described in the modification 2 is applied to the sixth embodiment, that is, when the first layer metal wiring M16 is the local ground wiring LVSS, the second The layer metal wiring M22 is connected only to the first layer metal wiring M112 via the via 1 (not connected to the first layer metal wiring M16). In this case, the corresponding via 1 is removed so that the first-layer metal interconnection M16 is not connected to the second-layer metal interconnection M22 via the via 1. Thereby, the first-layer metal interconnection M16 can be made the local ground interconnection LVSS.

  According to the sixth embodiment, the following effects can be obtained.

  The wiring pitches of the first-layer metal wirings (M11 to M19, M110 to M112) are only linear patterns at equal intervals, which facilitates manufacture.

  Since the wiring pitch of the second-layer metal wiring (M20-M25) is only a linear pattern at equal intervals, the manufacture is facilitated.

  As in the fourth modification, the relatively thick N-type well region NW and the P-type well region PW shared with the adjacent cells are obtained. Therefore, since process control at the time of formation of the N-type and P-type well regions NW and PW becomes relatively easy, the manufacture of the N-type and P-type well regions NW and PW can be facilitated.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an example, the present invention is not limited to the above-mentioned embodiment and an example, and it can not be overemphasized that it can change variously .

1, 1a, 1b, 1c, 1d: Semiconductor memory devices 2, 2a, 2b, 2c, 2d: Memory arrays MC: Memory cells G, G1, G2, G3, G4: Gate electrodes (gate wiring)
WL: Word line BT: Bit line TCEL: TCAM cell ML0: Match line SL0, / SL0: Search line

Claims (19)

With multiple memory cells,
A word line connected to the plurality of memory cells,
The word line is disposed along a first direction,
A semiconductor memory device, wherein each of the plurality of memory cells includes a gate electrode arranged along a second direction intersecting the first direction. In the semiconductor memory device of claim 1,
And a plurality of bit lines connected to the plurality of memory cells.
The semiconductor memory device, wherein the plurality of bit lines are arranged along the second direction. In the semiconductor memory device of claim 2,
The gate electrode includes a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode.
The first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are provided apart from one another and have a straight shape without bending.
The first gate electrode and the third gate electrode are disposed to run in parallel in the first direction,
The first gate electrode and the fourth gate electrode are disposed in a straight line in the second direction,
The semiconductor memory device, wherein the third gate electrode and the second gate electrode are disposed in a straight line in the second direction. In the semiconductor memory device of claim 3,
Each of the plurality of memory cells has a rectangular pattern elongated in the second direction,
The semiconductor memory device, wherein the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are disposed in the elongated rectangular pattern. In the semiconductor memory device of claim 4,
The semiconductor memory device, wherein each of the plurality of memory cells is a static memory cell including six MOS transistors. In the semiconductor memory device of claim 2,
In each of the plurality of memory cells, the length of a word line corresponding to one memory cell is shorter than the length of a bit line corresponding to one memory cell. With multiple memory cells,
A word line connected to the plurality of memory cells;
And a plurality of bit lines connected to the plurality of memory cells.
The word lines are arranged to extend along a first direction,
The plurality of bit lines are arranged to extend along a second direction intersecting the first direction,
Each of the plurality of memory cells includes a plurality of gate electrodes arranged along the second direction,
Each of the plurality of memory cells includes six MOS transistors,
A semiconductor memory device, wherein two of the six MOS transistors are disposed one above the other in the first direction. In the semiconductor memory device of claim 7,
The plurality of memory cells are arranged along the first direction,
A semiconductor memory device, wherein in the plurality of memory cells arranged along the first direction, two memory cells arranged above and below share one of the plurality of bit lines. In the semiconductor memory device of claim 7,
The gate electrode includes a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode.
The first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are provided apart from one another and have a straight shape without bending.
The first gate electrode and the third gate electrode are disposed to run vertically in parallel in the first direction,
The first gate electrode and the fourth gate electrode are disposed in a straight line in the second direction,
The semiconductor memory device, wherein the third gate electrode and the second gate electrode are disposed in a straight line in the second direction. In the semiconductor memory device of claim 9,
The six MOS transistors include first and second P channel MOS transistors, and first, second, third and fourth N channel MOS transistors,
The first gate electrode is a gate of the first N channel MOS transistor,
The second gate electrode is a gate of the second N channel MOS transistor,
The third gate electrode is a gate of the first P-channel MOS transistor and a gate of the third N-channel MOS transistor.
The semiconductor memory device, wherein the fourth gate electrode is a gate of the second P-channel MOS transistor and a gate of the fourth N-channel MOS transistor. In the semiconductor memory device of claim 10,
The sources or drains of the first N-channel MOS transistor and the third N-channel MOS transistor are constituted by N-type impurity regions formed in a first P-type well region provided along the first direction. And
The sources or drains of the second N-channel MOS transistor and the fourth N-channel MOS transistor are formed of N-type impurity regions formed in a second P-type well region provided along the first direction. And
The sources or drains of the first and second P-channel MOS transistors are provided along the first direction, and in an N-type well region provided to be sandwiched between the first and second P-type well regions. A semiconductor memory device comprising a P-type impurity region formed in In the semiconductor memory device of claim 7,
The semiconductor memory device is formed using first, second, third and fourth layer metal interconnections.
The word line is formed by one of the third layer metal wiring and the fourth layer metal wiring.
The semiconductor memory device, wherein the plurality of bit lines are formed by the other of the third layer metal interconnection and the fourth layer metal interconnection. In the semiconductor memory device of claim 7,
The semiconductor memory device is formed using first, second and third layer metal interconnections,
The word line is formed by one of the second layer metal wiring and the third layer metal wiring.
The semiconductor memory device, wherein the plurality of bit lines are formed by the other of the second layer metal interconnection and the third layer metal interconnection. First and second word lines provided along the first direction;
A first bit line, a second bit line, and a third bit line provided along a second direction intersecting the first direction;
A first memory cell connected to the first word line and the first bit line and the second bit line;
A second memory cell connected to the second word line and the second bit line and the third bit line;
Each of the first memory cell and the second memory cell has a gate electrode provided along the second direction.
Semiconductor memory device. In the semiconductor memory device of claim 14,
The gate electrode includes a first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode.
The first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are provided apart from one another and have a straight shape without bending.
The first gate electrode and the third gate electrode are disposed to run vertically in parallel in the first direction,
The first gate electrode and the fourth gate electrode are disposed in a straight line in the second direction,
The semiconductor memory device, wherein the third gate electrode and the second gate electrode are disposed in a straight line in the second direction. In the semiconductor memory device of claim 15,
Each of the first memory cell and the second memory cell includes first and second P channel MOS transistors, and first, second, third and fourth N channel MOS transistors,
The first gate electrode is a gate of the first N channel MOS transistor,
The second gate electrode is a gate of the second N channel MOS transistor,
The third gate electrode is a gate of the first P-channel MOS transistor and a gate of the third N-channel MOS transistor.
The semiconductor memory device, wherein the fourth gate electrode is a gate of the second P-channel MOS transistor and a gate of the fourth N-channel MOS transistor. In the semiconductor memory device of claim 16,
The sources or drains of the first N-channel MOS transistor and the third N-channel MOS transistor are constituted by N-type impurity regions formed in a first P-type well region provided along the first direction. And
The sources or drains of the second N-channel MOS transistor and the fourth N-channel MOS transistor are formed of N-type impurity regions formed in a second P-type well region provided along the first direction. And
The sources or drains of the first and second P-channel MOS transistors are provided along the first direction, and in an N-type well region provided to be sandwiched between the first and second P-type well regions. A semiconductor memory device comprising a P-type impurity region formed in In the semiconductor memory device of claim 17,
The semiconductor memory device is formed using first, second, third and fourth layer metal interconnections.
The first and second word lines are formed by one of the third layer metal interconnection and the fourth layer metal interconnection,
The semiconductor memory device, wherein the first to third bit lines are formed by the other of the third layer metal interconnection and the fourth layer metal interconnection. In the semiconductor memory device of claim 17,
The semiconductor memory device is formed using first, second and third layer metal interconnections,
The first and second word lines are formed by one of the second layer metal interconnection and the third layer metal interconnection,
The semiconductor memory device, wherein the first to third bit lines are formed by the other of the second layer metal interconnection and the third layer metal interconnection.

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