JP2019114244A - Electronic control device - Google Patents

Abstract

To provide an electronic control device capable of shortening a startup time of a system while satisfying a function safety request.SOLUTION: A microcomputer provided at an electronic control device has a hardware self-text (BIST) function. The microcomputer has a plurality of BIST objects the BIST of each of which is executed. When the microcomputer is started up, an LBIST as the BIST with a logic circuit part as a diagnosis object is executed (step S10). When the microcomputer is shut down, an MBIST as the BIST with a memory part as a diagnosis object is executed (step S15). Thus, the BIST is not executed to all the plurality of BIST objects when the microcomputer is started up, but the BIST is executed separately during startup and shutdown.SELECTED DRAWING: Figure 2

Description

  The disclosure in this specification relates to an electronic control unit.

  In order to satisfy functional safety requirements such as ISO26262, there is known an electronic control device provided with a microcomputer having a hardware self-test function as disclosed in Patent Document 1. The hardware self test (Built In Self Test) is hereinafter referred to as BIST.

JP, 2016-126692, A

  In the conventional electronic control device, the diagnosis by BIST is executed at the time of activation of the microcomputer before the software operates. Since it takes several tens of ms for diagnosis by BIST, when BIST is performed, it takes a long time for the microcomputer to start normal control processing after the microcomputer is powered on. That is, there is a problem that the start-up time of the system including the electronic control device becomes long.

  This indication is made in view of such a subject, and it aims at providing the electronic control device which can shorten the starting time of a system, fulfilling a functional safety demand.

  The present disclosure employs the following technical means to achieve the above object. In addition, the code | symbol in a parenthesis shows correspondence with the specific means as described in embodiment mentioned later as one aspect, and does not limit a technical scope.

One of the present disclosures is an electronic control device including a microcomputer (11) having a hardware self test (hereinafter, BIST) function,
A plurality of BIST objects (21, 22, 31, 32, 40, 71, 72, 81, 82, 90, 100) on which BIST is executed,
A start-up execution unit (S10) that executes BIST on a part of a plurality of BIST objects when starting up the microcomputer;
And a shutdown time execution unit (S15) that executes BIST at shutdown for the remaining BIST objects for which BIST is not executed at startup.

  According to this electronic control device, the functional safety requirements can be satisfied by executing the BIST. In addition, the system startup time can be shortened because the BIST is executed separately for startup and shutdown, instead of executing BIST for all of the plurality of BIST targets. As described above, the system startup time can be shortened while satisfying the functional safety requirements.

It is a figure which shows schematic structure of the electronic control unit of 1st Embodiment. It is a flowchart which shows the process which a microcomputer performs. It is a flowchart which shows LBIST processing. It is a flowchart which shows a shutdown process. It is a flowchart which shows MBIST processing. It is a flow chart which shows software initialization processing. It is a timing chart which shows from power supply ON of a microcomputer to OFF.

  Hereinafter, embodiments will be described with reference to the drawings.

First Embodiment
First, a schematic configuration of an electronic control unit (ECU: Electronic Control Unit) will be described based on FIG.

  Electronic control device 10 shown in FIG. 1 is mounted, for example, on a vehicle. In the present embodiment, the electronic control unit 10 is configured as an engine ECU.

  The electronic control device 10 includes a microcomputer 11, an input circuit 12, an output circuit 13, and a power supply circuit 14. The microcomputer 11 is a microcomputer that executes predetermined processing by executing a program stored in a non-volatile memory.

  The input circuit 12 outputs a signal input from the outside to the microcomputer 11. A start signal is input as an input signal. In the present embodiment, an IG signal is input from the ignition switch 200 as a start signal. The input circuit 12 also outputs an IG signal (start signal) to the power supply circuit 14. For example, detection signals of a plurality of sensors 201 for detecting the condition of the vehicle or the surroundings of the vehicle are input to the input circuit 12. The sensor 201 includes, for example, a crank angle sensor, a cam angle sensor, and a vehicle speed sensor. The microcomputer 11 uses the detection signal of the sensor 201 acquired through the input circuit 12 to execute calculation for performing optimal fuel injection according to the state of the engine.

  The output circuit 13 outputs a control signal, which is the calculation result of the microcomputer 11, to the external actuator 202. The actuator 202 includes, for example, an injector for fuel injection. When it is determined that the result of BIST described later is abnormal, the output circuit 13 outputs a signal to be notified to the user to the external notification unit 203. For example, a warning light can be employed as the notification unit.

  The power supply circuit 14 supplies power to the microcomputer 11 when the IG signal is switched from off to on. Also, when the IG signal is switched from on to off, the processing of the microcomputer 11 at the time of shutdown is waited and the power supply to the microcomputer 11 is cut off.

  The microcomputer 11 has a hardware in self test (built in self test) function. The hardware self test is hereinafter referred to as BIST. The microcomputer 11 has, as functional blocks, a first core 20, a second core 30, a RAM 40, a ROM 50, a BIST controller 60, a DMA controller 70, a timer unit 80, a monitoring timer 90, an I / O port It has 100. The functional blocks are configured to be able to communicate with each other via the bus 110.

  The first core 20 has a logic circuit 21 including a CPU 210 and a register 211, and a cache memory 22. The cache memory 22 has a data cache 220 which is an area for temporarily storing data to be processed by a program, and an instruction cache 221 which is an area for temporarily storing a program. The instruction cache 221 is also referred to as an instruction cache. In the present embodiment, the data cache 220 is provided with a stack area 220a which is a temporary save area. CPU is an abbreviation for Central Processing Unit.

  The second core 30 is also configured similarly to the first core 20. The second core 30 has a logic circuit 31 including a CPU 310 and a register 311, and a cache memory 32. The cache memory 32 has a data cache 320 and an instruction cache 321. The data cache 320 is also provided with a stack area 320a.

  The RAM 40 has an area for storing a memory BIST request described later, and an area for storing an execution history of the memory BIST. The ROM 50 stores fixed data handled by the program and the program. The ROM 50 corresponds to a non-volatile memory. The ROM 50 also stores a BIST result described later. Note that ROM is an abbreviation of Read Only Memory. RAM is an abbreviation for Random Access Memory.

  The BIST controller 60 executes the BIST in cooperation with the first core 20. The BIST controller 60 executes BIST by controlling the content and timing of a BIST circuit (not shown). The BIST circuit is provided in each of the first core 20, the second core 30, the RAM 40, the DMA controller 70, the timer unit 80, the monitoring timer 90, and the I / O port 100.

  The DMA controller 70 controls data transfer between a memory such as the RAM 40 and an external device without passing through the first core 20 (CPU 210) and the second core 30 (CPU 310). DMA is an abbreviation for Direct Memory Access. The DMA controller 70 has a logic circuit 71 and a memory 72.

  The timer unit 80 is a processor having a function such as time management. The timer unit 80 is also referred to as a time processor unit. The timer unit 80 has a counter or the like to which a clock is input, and is configured to be able to measure time. The timer unit 80 has a logic circuit 81 and a memory 82.

  The monitoring timer 90 is also referred to as a watchdog timer. For example, a watchdog clear signal (hereinafter referred to as a WDC signal) is input to the monitoring timer 90 from the first core 20. When the WDC signal is not input within a predetermined time, the monitoring timer 90 outputs a reset instruction of the microcomputer 11 to a reset circuit (not shown). Thus, the reset circuit executes the WDC reset on the microcomputer 11.

  Next, processing executed by the microcomputer 11 will be described based on FIGS. 2 to 7.

  Here, the logic BIST is a BIST in which the logic circuit unit is a diagnostic area. The logic BIST is denoted LBIST. In the microcomputer 11, the logic circuits 21, 31, 71, 81 of the first core 20, the second core 30, the DMA controller 70, and the timer unit 80, the monitoring timer 90, the I / O port 100, the logic circuit unit It corresponds to Hereinafter, they are also referred to as logic circuit units 21, 31, 71, 81, 90, and 100.

  The memory BIST is a BIST that uses the memory unit as a diagnostic area. The memory BIST is denoted MBIST. In the microcomputer 11, the cache memories 22 and 32 of the first core 20 and the second core 30, the RAM 40, and the memories 72 and 82 of the DMA controller 70 and the timer unit 80 correspond to a memory unit (RAM). Hereinafter, the memory units 22, 32, 40, 72 and 82 are also referred to. The logic circuit unit and the memory unit correspond to the BIST target. The ROM 50 corresponds to a non-target memory of BIST.

  When the ignition switch 200 is turned on and the IG signal is switched from off to on, power is supplied from the power supply circuit 14 to the microcomputer 11, and PowerOn reset is performed. As a result, the microcomputer 11 is initialized, and execution is set in the execution history of PowerOn reset. For example, "1" is set when there is execution, and "0" is set when there is no execution. The execution history of the reset including the PowerOn reset is set in the reset area of the microcomputer 11, for example, the RAM 40 or a register (not shown). When the microcomputer 11 is initialized by PowerOn reset when the power is turned on, the microcomputer 11 executes the following processing.

  When the initialization is completed, as shown in FIG. 2, the microcomputer 11 first executes LBIST processing (step S10). The LBIST process corresponds to the startup execution unit. The LBIST process will be described with reference to FIG.

  When initialization of the microcomputer 11 is completed, as shown in FIG. 3, the CPU 210 of the first core 20 instructs the BIST controller 60 to execute LBIST, whereby the BIST controller 60 starts LBIST (step S20). . Next, the BIST controller 60 determines whether LBIST is completed (step S21). If it is determined that the LBIST is completed, the BIST controller 60 stores the LBIST result, which is the diagnostic result of LBIST, in a register in the BIST controller 60 (step S22), and outputs a signal indicating the end of LBIST to the CPU 210. The LBIST process shown in FIG. 2 ends when the above process is completed.

  Although illustration is omitted, since the initialized value is changed by the execution of LBIST, the microcomputer 11 is reinitialized. In this initialization, the execution history of PowerOn reset is maintained. Further, the LBIST result stored in the register in the BIST controller 60 is also held.

  Next, the microcomputer 11 executes software initialization processing (step S11). The software initialization process is a process executed upon PowerOn reset. The software initialization process will be described with reference to FIG. 6 together with the software initialization process after the MBIST process. When the process shown in FIG. 6 is completed, the software initialization process (step S11) shown in FIG. 2 ends. The contents of FIG. 6 will be described later.

  Next, the microcomputer 11 executes a normal control process (step S12). The CPU 210 executes, for example, a fuel injection control process as the normal control process.

  Next, the CPU 210 determines whether the IG signal has been switched from on to off (step S13). While it is determined that the switch is not switched off, the normal control process of step S12 is repeated. On the other hand, if it is determined that the IG signal has been switched off, the microcomputer 11 first executes shutdown processing to turn off the power supply of the microcomputer 11 (step S14). The shutdown process will be described with reference to FIG.

  If it is determined that the IG signal has been switched off, the CPU 210 determines whether or not execution is set in the MBIST execution history, as shown in FIG. 4 (step S40). In this embodiment, the MBIST execution history is read from the RAM 40, and it is determined whether the MBIST has been executed after the IG signal is turned on. For example, "1" is set when there is execution, and "0" is set when there is no execution.

  If it is determined in step S40 that there is no execution, the presence of a request is set in the MBIST request of the RAM 40 to execute MBIST in step S15 described later (step S41), and the shutdown processing is ended. On the other hand, when it is determined in step S40 that the MBIST is performed, the shutdown process is ended without executing the process of step S41. The shutdown process shown in FIG. 4 ends when the above process is completed.

  Next, the microcomputer 11 executes the MBIST process (step S15). The MBIST processing corresponds to the shutdown time execution unit. The MBIST process will be described with reference to FIG.

  As shown in FIG. 5, the CPU 210 first sets the I / O port 100 (step S60). Specifically, the setting of the I / O port 100 is set to a state after initialization of the microcomputer 11 by PowerOn reset. In other words, the I / O port 100 is set to the safe side, which limits the output to the actuator 202.

  Next, the CPU 210 determines whether or not the request is set in the MBIST request of the RAM 40 (step S61). For example, “1” is set when there is a request, and “0” is set when there is no request.

  If it is determined that there is a request, the CPU 210 executes the processing of steps S62 to S65. In step S62, the operation of the monitoring timer 90 is stopped. In step S63, the instruction caches 221 and 321 are invalidated. That is, the program instruction temporarily stored in the instruction caches 221 and 321 is invalidated. In step S64, the operation of the DMA controller 70 is stopped. In step S65, the operation of the timer unit 80 is stopped.

  When the process of step S65 is completed, the CPU 210 instructs the BIST controller 60 to execute MBIST, whereby the BIST controller 60 starts MBIST (step S66). Next, the BIST controller 60 determines whether MBIST is completed (step S67). If it is determined that the MBIST is completed, the BIST controller 60 stores the MBIST result, which is a diagnosis result of the MBIST, in a register in the BIST controller 60 (step S68).

  In the present embodiment, in order to invalidate the instruction cache 221, the CPU 210 directly reads a value from the ROM 50 and executes MBIST. In addition, the program that executes MBIST is configured as a program that does not use a function. That is, the program does not need to use the stack areas 220a and 320a. Therefore, the stack areas 220a and 320a can also be targets of MBIST.

  When the process of step S68 is completed, the reset circuit executes reset of the microcomputer 11 (step S69). By the reset (the MBIST reset) in the MBIST process, the microcomputer 11 is initialized, and the execution history of the MBIST reset is set to "yes". For example, "1" is set when there is execution, and "0" is set when there is no execution. The execution history of the reset is set in the area for reset of the microcomputer 11, for example, the register as described above. If it is determined in step S61 that the request is not set in the MBIST request, the process proceeds to the power off process of step S70, and the microcomputer 11 ends the series of processes. The MBIST process shown in FIG. 5 ends when the process described above is completed.

  Next, the microcomputer 11 executes software initialization processing (step S16). The software initialization process is a process executed upon MBIST reset. This software initialization process is also described in FIG. When the process shown in FIG. 6 is completed, the software initialization process of step S16 ends. The contents of FIG. 6 will be described later.

  Next, the CPU 210 instructs the power supply circuit 14 to turn off the power of the microcomputer 11 (step S17), and ends the series of processing.

  Next, software initialization processing will be described.

  As shown in FIG. 6, first, the microcomputer 11 determines whether the reset process executed before the software initialization process is a PowerOn reset or an MBIST reset (step S80). The CPU 210 reads the execution history of the reset and determines whether it is a PowerOn reset or an MBIST reset.

  In the case of the software initialization process of step S11, since execution is set in the execution history of PowerOn reset, the CPU 210 can determine that it is PowerOn reset. Note that the execution history of the MBIST reset is cleared by the initialization of the microcomputer 11 following the power-off or the PowerOn reset.

  In the case of the software initialization process of step S16, since execution is set in the execution history of the MBIST reset, the CPU 210 can determine that it is the MBIST reset. Note that the execution history of the PowerOn reset is cleared by the initialization of the microcomputer 11 or the power-off due to the MBIST reset.

  If YES in step S80, then the CPU 210 executes memory clear (step S81). The memory clear is, among the data of the memory unit (RAM) described above, clears the data held across the normal reset other than the PowerOn reset and the MBIST reset. In the present embodiment, reset by the monitoring timer 90, that is, WDC reset is included as the normal reset.

  After executing the memory clear, the CPU 210 determines whether the MBIST is reset (step S82). The CPU 210 can determine whether or not the MBIST is reset based on the execution history of the MBIST reset. If it is determined in step S80 that neither PowerOn reset nor MBIST reset is performed, that is, if it is determined that normal reset is performed, the process of step S82 is performed without executing the process of step S81.

  If the CPU 210 determines that the MBIST is reset, it sets execution to the MBIST execution history of the RAM 40 (step S83), and if it determines that the MBIST is not reset, sets no execution to the MBIST execution history (step S83). S84).

  Next, the CPU 210 reads the BIST result from the register of the BIST controller 16 and stores it in the ROM 50 (step S85). The BIST result of the ROM 50 is updated by the process of step S85.

  At the time of software initialization processing of step S11, the CPU 210 stores the LBIST result which is the diagnosis result of LBIST executed in step S10. Further, at the time of software initialization processing of step S16, the MBIST result which is the diagnosis result of MBIST executed in step S15 is stored. Therefore, even if the power is turned off in step S17 and the microcomputer 11 is initialized by PowerOn reset, the MBIST result is held.

  Next, the CPU 210 determines whether the IG signal is on (step S86). That is, it is determined whether the ignition switch 200 is turned on.

  In the case of the software initialization process of step S11, it is determined that the IG signal is on. Next, the CPU 210 determines whether the BIST result is abnormal (step S87). The CPU 210 reads the LBIST result and the MBIST result from the ROM 50, and determines whether or not it is abnormal. The LBIST result is the current value, and the MBIST result is the previous value.

  If it is determined that there is an abnormality, then the CPU 210 executes an abnormal process (step S88). The CPU 210 outputs a signal indicating abnormality to the notification unit 203 via, for example, the I / O port 100 and the output circuit 13. Thereby, the warning light which is the notification unit 203 is turned on. In this way, the notification unit 203 notifies the user of the abnormality. Note that the notification unit 203 is not limited to the warning light. It can also be notified by display on a vehicle monitor, voice and the like. In addition, abnormal treatment is not limited to notification. The CPU 210 may instruct, for example, the execution of the failsafe processing of the vehicle.

  When the abnormal state process is completed, the microcomputer 11 ends the software initialization process of step S11. If it is determined in step S87 that the BIST result is not abnormal, the series of processes is ended without executing the process of step S88. Further, in the case of the software initialization process of step S16, it is determined in step S86 that the IG signal is not on. In this case, the series of processes is ended without executing the processes of steps S87 and S88.

  Next, the effects of the electronic control unit 10 of the present embodiment will be described.

  In the present embodiment, the execution of the BIST can satisfy functional safety requirements. In addition, BIST is not executed at startup of the microcomputer 11 for all of the plurality of BIST targets, but BIST is executed separately at startup and shutdown. Therefore, the system startup time can be shortened. As described above, the system startup time can be shortened while satisfying the functional safety requirements.

  In particular, in the present embodiment, when the microcomputer 11 is activated, LBIST (logic BIST) in which the logic circuit units 21, 31, 71, 81, 90, and 100 are to be diagnosed is executed. Further, when the microcomputer 11 is shut down, the MBIST (memory BIST) which makes the memory units 22, 32, 40, 72, 82 a diagnosis target is executed. In this manner, the security can be enhanced because the LBIST is performed at startup before the normal control is performed. In addition, since MBIST is executed at the time of shutdown, the startup time can be shortened. Since the microcomputer 11 is reset by the memory BIST, the value of the RAM is rewritten. However, because it is executed at shutdown, many memory units can be BIST targets.

  FIG. 7 shows a timing chart showing from on to off of the power supply of the microcomputer 11. In the present embodiment, the ignition switch 200 is turned on to supply power to the microcomputer 11, and LBIST is started at time t1 when the microcomputer 11 is initialized by PowerOn reset. Also, after LBIST, software initialization is performed. Then, at time t2 when software initialization is completed, normal control is started.

  Further, when the ignition switch 200 is turned off at time t3, the shutdown process is performed. When the shutdown process is completed, MBIST is then executed, and after MBIST is completed, software initialization is performed. When the software initialization is completed, the power of the microcomputer 11 is turned off at time t4 after the power off process.

  Thus, only LBIST is executed at startup. Therefore, the start-up time can be shortened as shown in FIG. 7 as compared to the conventional configuration in which both LBIST and MBIST are performed at start-up. For example, if the time taken for LBIST is 15 ms and the time taken for MBIST is 15 ms, the startup time can be reduced by 15 ms.

  In the present embodiment, stack areas 220 a and 320 a are provided in the cache memories 22 and 32. The program that executes MBIST is configured as a program that does not use a function. As described above, since the program is not required to use the stack areas 220a and 320a, the stack areas 220a and 320a can also be targets of MBIST. Thereby, the failure detection rate can be improved. The stack area is not limited to the cache memories 22 and 32. The same effect can be obtained for the configuration provided in another memory unit.

  In the present embodiment, when executing MBIST, the instruction caches 221 and 321 are invalidated, values are read directly from the ROM 50, and MBIST is executed. Therefore, MBIST can be executed also for the cache memories 22 and 32, particularly the instruction caches 221 and 321. Thereby, the failure detection rate can be improved. In addition, since the instruction cache 221 that is the target of MBIST is invalidated, false detection can be suppressed.

  In the present embodiment, when performing the MBIST, the DMA controller 70 is stopped and then the MBIST is performed. For this reason, MBIST can also be performed on the memory 72 of the DMA controller 70. Since the DMA controller 70 that is the target of MBIST is stopped, false detection can be suppressed.

  In the present embodiment, when performing MBIST, the timer unit 80 is stopped and then MBIST is performed. Therefore, the MBIST can be executed also for the memory 82 of the timer unit 80. Since the timer unit 80 that is the target of MBIST is stopped, false detection can be suppressed.

  In the present embodiment, when executing MBIST, the monitoring timer 90 is stopped and then MBIST is performed. This can prevent the WDC reset from being performed erroneously.

  The disclosure of this specification is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and variations based on them by those skilled in the art. For example, the disclosure is not limited to the combination of elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosed technical scope is not limited to the description of the embodiments. The technical scopes disclosed are set forth by the description of the claims, and should be understood to include all the modifications within the meaning and scope equivalent to the descriptions of the claims. .

  The configuration of the microcomputer 11 is not limited to the example described above. Although the example in which the microcomputer 11 includes the monitoring timer 90 has been shown, the present invention is not limited to this. The electronic control unit 10 may be provided with a monitoring IC having a function of a monitoring timer separately from the microcomputer 11.

  Although the microcomputer 11 showed the example which has the 1st core 20 and the 2nd core 30 as a several calculating part, it is not limited to this. The multi-core configuration is not limited to this, and may have three or more cores. Moreover, it is not limited to a multi-core, The microcomputer 11 of a single-core structure is also employable.

  Although LBIST is executed at startup of the microcomputer 11 and MBIST is executed at shutdown, the present invention is not limited to this. Execute BIST at startup for some of the multiple BIST objects, and execute BIST at shutdown for the remaining BIST objects.

DESCRIPTION OF SYMBOLS 10 ... Electronic control apparatus, 11 ... Microcomputer, 12 ... Input circuit, 13 ... Output circuit, 14 ... Power supply circuit, 20 ... 1st core, 21 ... Logic circuit, 210 ... CPU, 211 ... Register, 22 ... Cache memory, 220 ... data cache, 220a ... stack area, 221 ... instruction cache, 30 ... second core, 31 ... logic circuit, 310 ... CPU, 311 ... register, 32 ... cache memory, 320 ... data cache, 320a ... stack area, 321 ... Instruction cache, 40 ... RAM, 50 ... ROM, 60 ... BIST controller, 70 ... DMA controller, 71 ... logic circuit, 72 ... memory, 80 ... timer unit, 81 ... logic circuit, 82 ... memory, 90 ... monitoring timer, 100 ... I / O port, 110 ... bus, 200 ... ignition switch, 20 ... sensor, 202 ... actuator, 203 ... notification unit

Claims (6)

An electronic control device comprising a microcomputer (11) having a hardware self test (hereinafter, BIST) function,
A plurality of BIST objects (21, 22, 31, 32, 40, 71, 72, 81, 82, 90, 100) on which BIST is executed,
A startup time execution unit (S10) that executes BIST on a part of the plurality of BIST objects when the microcomputer is started up;
An electronic control device comprising: a shutdown time execution unit (S15) that executes BIST at shutdown for the remaining BIST objects for which BIST is not executed at startup. The plurality of BIST objects include a logic circuit unit (21, 31, 71, 81, 90, 100) and a memory unit (22, 32, 40, 72, 82),
At the time of startup, the logic circuit unit is subjected to BIST,
The electronic control unit according to claim 1, wherein the memory unit is subjected to BIST at the time of the shutdown. The memory unit includes a memory provided with a stack area (220a, 320a),
3. The electronic control unit according to claim 2, wherein the shutdown time execution unit executes BIST on the memory unit including the stack area by a program not using a function. The program is stored and has non-targeted memory (50) which is not subject to BIST,
A cache memory (22, 32) including an instruction cache (221, 321) for temporarily storing the program and a data cache (220, 320) for temporarily storing data to be processed by the program as the memory unit. Including)
The shutdown execution unit invalidates the instruction cache at the shutdown time, directly reads the value of the non-target memory, and executes BIST on the memory unit including the cache memory. The electronic control unit according to 3. The logic circuit unit has a CPU (210, 310),
It has a memory area as the memory unit, and includes a direct memory access (hereinafter, DMA) controller (70) which transfers data without passing through the CPU.
The electronic control according to any one of claims 2 to 4, wherein the shutdown time execution unit executes the BIST on the memory unit including the memory area of the DMA controller after stopping the DMA controller at the shutdown time. apparatus. A timer unit (80) having a memory area as the memory unit and capable of measuring time;
The electronic control according to any one of claims 2 to 5, wherein the shutdown time execution unit executes BIST on the memory unit including the memory area of the timer unit after stopping the timer unit at the shutdown time. apparatus.

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