JP2019102705A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which inhibits breakdown voltage characteristic deterioration caused by disconnection of a field plate.SOLUTION: A semiconductor device SM comprises a semiconductor substrate SB, a first insulation film IF1 and a resistive filed plate FP. The resistive field plate FP is electrically connected with a p type well region PW and an n+ type region NS and faces a p type surface electric field reduction region RS via a first insulation film IF1. The resistive field plate FP includes a first part FP1, a second part FP2 and a third part FP3 connecting the first part FP1 and the second part FP2. The third part FP3 surrounds the first part FP1 in plan view and has a first pathway which extends from the second part FP2 to reach the first part FP1 and a second pathway which is branched off from the first pathway and runs from the second part FP2 to reach the first part FP1.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a field plate.

  International Publication No. 2012/157223 and Japanese Patent Laid-Open Publication No. 2017-139392 disclose a semiconductor device provided with a resistive field plate. In these semiconductor devices, one of two semiconductor regions to which a high potential difference is applied is arranged to surround the other. The above-described resistive field plate functions as a field plate by electrically connecting both semiconductor regions and supplying a weak current between the two regions, and contributes to the increase in breakdown voltage of the semiconductor device.

  Further, the resistive field plate is placed in a meandering manner between the two semiconductor regions to increase resistance. As a result, the current flowing between the two semiconductor regions via the resistive field plate is suppressed, and the breakdown voltage of the semiconductor device is increased.

  In the above semiconductor device, the width in the direction crossing the extending direction of the resistive field plate, and the narrowing of the spacing between adjacent portions arranged in a meandering manner are achieved, and the resistive field plates are arranged at a high density. It is done.

International Publication No. 2012/157223 JP, 2017-139392, A

  However, in the conventional resistive field plate, the function as the field plate is lost if it breaks even at one place.

  Such disconnection of the conventional resistive field plate is caused by an abnormality such as adhesion of foreign matter in the manufacturing process of the semiconductor device, but it is difficult to control them.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  A semiconductor device according to one embodiment includes a first semiconductor region, a second semiconductor region arranged to surround the first semiconductor region in plan view, and a first semiconductor region and a second semiconductor region in plan view. A semiconductor substrate including a third semiconductor region disposed to surround the first semiconductor region, an insulating film disposed on the third semiconductor region, and a first semiconductor region and a second semiconductor region. A field plate electrically connected to each other and opposed to the third semiconductor region through the insulating film is provided. The field plate includes a first portion having an annular shape in a plan view, a second portion surrounding the outside of the first portion in a plan view, and a third portion connecting the first portion and the second portion. The third part surrounds the periphery of the first part in a plan view, and a first path from the second part to the first part and a first path and a second path from the second part to the first part And.

  According to one embodiment, it is possible to realize a semiconductor device in which a decrease in withstand voltage characteristics is suppressed as compared to a semiconductor device provided with a conventional resistive field plate.

FIG. 2 is a plan view showing a field plate of the semiconductor device according to the first embodiment. FIG. 2 is a partial cross-sectional view of a peripheral region of the semiconductor device, as viewed from line segment II-II in FIG. 1; FIG. 2 is a cross-sectional view of the peripheral region of the semiconductor device, as viewed from line segment III-III in FIG. 1; FIG. 7 is a cross-sectional view showing a step of a method of manufacturing a semiconductor device in accordance with the first embodiment. FIG. 5 is a cross-sectional view showing a process after the process shown in FIG. 4 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing a process after the process shown in FIG. 5 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 7 is a cross-sectional view showing a process after the process shown in FIG. 6 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 8 is a cross-sectional view showing a process after the process shown in FIG. 7 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 9 is a cross-sectional view showing a process after the process shown in FIG. 8 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 10 is a cross-sectional view showing a process after the process shown in FIG. 9 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 11 is a cross-sectional view showing a process after the process shown in FIG. 10 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 12 is a cross-sectional view showing a process after the process shown in FIG. 11 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 13 is a cross-sectional view showing a process after the process shown in FIG. 12 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 14 is a cross-sectional view showing a process after the process shown in FIG. 13 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 15 is a cross-sectional view showing a process after the process shown in FIG. 14 in the method for manufacturing a semiconductor device in accordance with the first embodiment. FIG. 2 is a cross-sectional view showing a field plate and an inter-region insulating film of the semiconductor device according to the first embodiment. FIG. 20 is a cross-sectional view showing a field plate and an inter-region insulating film of a conventional semiconductor device. FIG. 16 is a plan view showing a field plate of the semiconductor device according to the second embodiment. FIG. 16 is a plan view showing a field plate of the semiconductor device according to Third Embodiment; FIG. 26 is a plan view showing a field plate of the semiconductor device concerning Embodiment 4;

  Hereinafter, the present embodiment will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

Embodiment 1
<Structure of Semiconductor Device>
The semiconductor device SM according to the first embodiment will be described with reference to FIGS. 1 and 2. As shown in FIG. 1, the semiconductor device SM mainly includes a semiconductor substrate SB and a resistive field plate FP. As shown in FIG. 2, the semiconductor substrate SB has a first surface PS1 and a second surface PS2 opposite to the first surface PS1. FIG. 1 is a plan view showing the structure of the resistive field and the resistive field plate FP when the semiconductor device SM is viewed in plan (hereinafter simply referred to as a plan) from the first surface PS1 side. The first direction X and the second direction Y in FIG. 1 are directions along the first surface PS1, and the first direction X is orthogonal to the second direction Y. In FIG. 1, two wavy lines illustrated in an annular shape inside the second part FP2 of the resistive field plate FP are omitted. In FIG. 1, the emitter electrode EE, the first collector electrode CES, the third insulating film IF3 and the like shown in FIG. 2 are not shown.

  As shown in FIG. 1, in plan view, the semiconductor device SM has, for example, a central region CR in which an IGBT element is disposed, and a peripheral region PR disposed so as to surround the central region CR. The resistive field plate FP is disposed on the first surface PS1 of the semiconductor substrate SB in the peripheral region PR. Details of the resistive field plate FP will be described later.

The outer shape of the central region CR in a plan view may be any shape, for example, a square shape. The outer shape of the peripheral region PR in plan view, that is, the planar shape of the semiconductor device SM may be any shape, but is, for example, a square shape. In plan view, one side forming the outline of the semiconductor device SM extends along the first direction X, and the other side intersecting the one side extends along the second direction Y.
<Configuration of Peripheral Region of Semiconductor Device>
As shown in FIGS. 1, 2 and 3, in the peripheral region PR, the semiconductor device SM includes the semiconductor substrate SB and the resistive field plate FP, the first insulating film IF1 as an electrical insulating film, and the second The semiconductor device further includes an insulating film IF2, a third insulating film IF3, an emitter electrode EE, a first collector electrode CES, and a second collector electrode CER.

As shown in FIGS. 2 and 3, in the peripheral region PR, the semiconductor substrate SB includes a p-type well region PW as a first semiconductor region and a p-type surface electric field relaxation region RS as a second semiconductor region. An n-type n + region NS as a third semiconductor region disposed to face the well region PW with the surface electric field relaxation region RS interposed therebetween, an n-type drift region ND, and a p-type p ++ Contact regions PC5 and PC7 and p ⁺ contact regions PC6 and PC8 are included. The well region PW, the surface electric field relaxation region RS, the n + region NS, and the p ++ contact regions PC5 and PC7 are disposed on the first surface PS1 of the semiconductor substrate SB.

  As shown in FIGS. 2 and 3, the well region PW is in contact with the surface electric field relaxation region RS. The surface electric field relaxation region RS and the n + region NS are in contact with the drift region ND. Well region PW is in contact with drift region ND via surface electric field relaxation region RS. Well region PW is connected to n + region NS via surface electric field relaxation region RS and drift region ND. In plan view, surface electric field relaxation region RS is arranged to surround well region PW. In plan view, n + region NS is arranged to surround well region PW and surface electric field relaxation region RS.

  The p ++ contact region PC5 is disposed above the p + contact region PC6. The p ++ contact region PC7 is disposed above the p + contact region PC8. The p ++ contact region PC5 and the p + contact region PC6 are connected to the well region PW. The p ++ contact region PC7 and the p + contact region PC8 are connected to the n + region NS.

  As shown in FIGS. 2 and 3, the first insulating film IF1 is in contact with the well region PW, the surface electric field relaxation region RS, the drift region ND, and the n + region NS. The second insulating film IF2 is disposed to cover the first insulating film IF1. The second insulating film IF2 is disposed to cover, for example, the first surface PS1 of the peripheral region PR. In the second insulating film IF2, for example, a contact hole for connecting the emitter electrode EE and the well region PW, and a contact hole for connecting the first collector electrode CES and the n + region NS are provided. .

  As shown in FIGS. 2 and 3, the resistive field plate FP is disposed on the second insulating film IF2 located on the first insulating film IF1. The resistive field plate FP is disposed at least on the surface field relaxation region RS and the drift region ND. A portion of the resistive field plate FP located on the central region CR side is connected to the emitter electrode EE. A portion of the resistive field plate FP located on the outer peripheral end side of the peripheral region PR is connected to the first collector electrode CES.

  As shown in FIGS. 2 and 3, the emitter electrode EE is connected to the well region PW via the p ++ contact region PC5 and the p + contact region PC6. The first collector electrode CES is connected to the n + region NS via the p ++ contact region PC7 and the p + contact region PC8. That is, the resistive field plate FP is connected to the well region PW via the emitter electrode EE, and is connected to the n + region NS via the first collector electrode CES. In plan view, the emitter electrode EE and the first collector electrode CES are, for example, annularly arranged.

  As shown in FIGS. 2 and 3, the third insulating film IF3 is disposed so as to cover the resistive field plate FP, the first insulating film IF1, and the second insulating film IF2. Contact holes CH1, CH2, CH3 and CH4 are provided in the third insulating film IF3.

  The contact hole CH1 is for connecting the emitter electrode EE and the resistive field plate FP, and is formed to reach the resistive field plate FP from the upper surface of the third insulating film IF3.

  The contact hole CH2 is for connecting the emitter electrode EE and the well region PW, and is continuous with the contact hole for connecting the emitter electrode EE provided in the second insulating film IF2 and the well region PW. Provided in

  The contact hole CH3 is for connecting the first collector electrode CES and the resistive field plate FP, and is formed to reach the resistive field plate FP from the upper surface of the third insulating film IF3.

  The contact hole CH4 is for connecting the first collector electrode CES and the n + region NS, and for connecting the first collector electrode CES provided in the second insulating film IF2 and the n + region NS. It is provided to be continuous with the contact hole.

The material forming the first insulating film IF1, the second insulating film IF2, and the third insulating film IF3 may be any material having electrical insulation, and includes, for example, silicon oxide (SiO ₂ ).

  The material constituting the resistive field plate FP may be any material as long as it can realize the electrical resistance value required for the resistive field plate FP, but a p-type impurity such as boron (B) is an example. It is polycrystalline silicon (doped polysilicon) introduced. The material constituting the emitter electrode EE and the first collector electrode CES may be any material having conductivity, and includes, for example, aluminum (Al). The impurity introduced into the resistive field plate FP may be an n-type impurity such as phosphorus (P), but is preferably a p-type impurity from the viewpoint of increasing the resistance.

  The emitter electrode EE and the first collector electrode CES may include, for example, a barrier metal layer BM. The barrier metal layer BM is disposed under each of the emitter electrode EE and the first collector electrode CES. The material which comprises barrier metal layer BM contains titanium tungsten (TiW), for example.

As shown in FIGS. 2 and 3, the semiconductor substrate SB further includes a p-type collector region PL and an n-type field stop region NL. Collector region PL is arranged on second surface PS2. Field stop region NL is arranged between collector region PL and drift region ND. The second collector electrode CER is disposed on the second surface PS2 of the semiconductor substrate SB. The first collector electrode CES and the second collector electrode CER are electrically connected to each other by a surface leakage current through the cut surface of the side surface of the semiconductor device SM.
<Specific configuration of field plate>
As shown in FIGS. 1 and 2, the resistive field plate FP includes a first portion FP1 connected to the well region PW via the emitter electrode EE, and an n + region NS via the first collector electrode CES. And a third part FP3 disposed between the first part FP1 and the second part FP2 and connecting the two. In a plan view, the first part FP1 is disposed to surround the central region CR. In a plan view, the second part FP2 is disposed so as to surround the central region CR on the outer peripheral side of the first part FP1.

The first portion FP1 of the resistive field plate FP has ap ⁺⁺ -type region PC1 and a p + region PC2 which have a higher impurity concentration than the other portions of the resistive field plate FP. The second part FP2 of the resistive field plate FP has ap ⁺⁺ -type region PC3 and a p + region PC4 which have a higher impurity concentration than the other parts of the resistive field plate FP. The p ⁺⁺ -type region PC1 is disposed on the p + -region PC2. The p ⁺⁺ -type region PC3 is arranged on the p + -region PC4. The p ⁺⁺ -type region PC1 and the p + region PC2 are connected to the emitter electrode EE in the contact hole CH1 of the third insulating film IF3. The p ⁺⁺ -type region PC3 and the p + -region PC4 are connected to the first collector electrode CES in the contact hole CH2 of the third insulating film IF3.

  As shown in FIGS. 1 and 2, in plan view, the third part FP3 of the resistive field plate FP has a plurality of surrounding portions arranged to surround the central region CR, and a plurality of surrounding portions And a plurality of connections to be connected. Thus, the third part FP3 surrounds the periphery of the first part FP1 in a plan view, and branches from the first path from the second part FP2 to the first part FP1 and the first path to the second part FP2. And the second path from the first part FP1.

  In plan view, the third part FP3 includes a first surrounding part FPS1 arranged to surround the central region CR, a second surrounding part FPS2 arranged to surround the first surrounding part FPS1, and a first surrounding part A plurality of first connection parts FPC1 for connecting between the surrounding part FPS1 and the second surrounding part FPS2, a third surrounding part FPS3 arranged to surround the second surrounding part FPS2, and a second surrounding part FPS2 And a plurality of second connection portions FPC2 for connecting the third enclosure portion FPS3. Furthermore, the third part FP3 includes a plurality of connection parts FPC which connect the first part FP1 and the first surrounding part FPS1.

  As shown in FIG. 1, the planar shapes of the first surrounding portion FPS1, the second surrounding portion FPS2 and the third surrounding portion FPS3 are annular, for example, a square ring (a square smaller than the center of the square is removed) Shape). Preferably, in plan view, the centers of the first surrounding portion FPS1, the second surrounding portion FPS2, and the third surrounding portion FPS3 are arranged to overlap. In plan view, the maximum width of the outer shape of the second surrounding portion FPS2 is larger than the maximum width of the outer shape of the first surrounding portion FPS1, and smaller than the maximum width of the outer shape of the third surrounding portion FPS3. In a plan view, the inner shape of the first part FP1 is, for example, a square shape. In plan view, the outer shape of the second part FP2, that is, the outer shape of the resistive field plate FP is, for example, a rounded square shape.

  As shown in FIG. 1, in a plan view, the first surrounding portion FPS1, the second surrounding portion FPS2, and the third surrounding portion FPS3 extend along the circumferential direction of the central region CR. The circumferential direction is in part along the first direction X, and in the other part along the second direction Y. In plan view, a part of the first enclosure FPS1, the second enclosure FPS2, and the third enclosure FPS3 extends along the first direction X, and the first enclosure FPS1, the second enclosure FPS2, and the third The other part of the surrounding portion FPS3 extends in the second direction Y.

  As shown in FIG. 1, the plurality of first connection portions FPC1 extend in a direction intersecting with the first surrounding portion FPS1 and the second surrounding portion FPS2, for example, extending in a direction orthogonal thereto. The plurality of second connection portions FPC2 extend in a direction intersecting with the second surrounding portion FPS2 and the third surrounding portion FPS3, and for example, extend in a direction perpendicular thereto. At least a portion of the plurality of first connection portions FPC1 extends in the radial direction from the center of the first surrounding portion FPS1 to the outer peripheral side of the semiconductor device SM in a plan view. At least a portion of the plurality of second connection portions FPC2 extends in a radiation direction from the center of the first surrounding portion FPS1 in plan view toward the outer peripheral side of the semiconductor device SM.

  As shown in FIG. 1, a plurality of first connection portions FPC1 are connected in parallel to each other between portions of the first surrounding portion FPS1 and the second surrounding portion FPS2 extending along the first direction X. Of the first connection portion FPC1 and a second group of first connection portions FPC1 in which the portions extending along the second direction Y of the first enclosure portion FPS1 and the second enclosure portion FPS2 are connected in parallel to each other. doing. The first connection portion FPC1 of the first group extends in the second direction Y. The first connection portion FPC1 of the second group extends along the first direction X.

  As shown in FIG. 1, the plurality of second connection portions FPC2 are a first group in which portions extending in the first direction X of the second surrounding portion FPS2 and the third surrounding portion FPS3 are connected in parallel to each other Of the second connection portion FPC2 and the second connection portion FPC2 of the second group in which the portions extending along the second direction Y of the second enclosure portion FPS2 and the third enclosure portion FPS3 are connected in parallel to each other. doing. The first connection portion FPC2 of the first group extends in the second direction Y. The second connection portion FPC2 of the second group extends along the first direction X. The plurality of second connection portions FPC2 of the first group are disposed to be continuous with the plurality of first connection portions FPC1 of the first group with the second surrounding portion FPS2 interposed therebetween. The plurality of second connection portions FPC2 of the second group are disposed to be continuous with the plurality of first connection portions FPC1 of the second group with the second surrounding portion FPS2 interposed therebetween.

  As shown in FIG. 1, in plan view, the resistive field plates FP are provided in a grid shape. In other words, in the resistive field plate FP, a plurality of openings having a rectangular outer shape in plan view are disposed. The plurality of openings are arranged side by side along the first direction X and the second direction Y at intervals. Each one side of the plurality of openings extends in the first direction X, and each other side extends in the second direction Y. Each opening is configured as a through hole in the resistive field plate FP.

  As shown in FIG. 1, the resistive field plate FP has, for example, four rotational symmetry (90-degree rotational symmetry) around the central region CR. The resistive field plate FP has, for example, mirror symmetry with respect to a cross section which bisects the semiconductor device SM in plan view.

  As shown in FIG. 1, the widths L1 of the first enclosure FPS1, the second enclosure FPS2, and the third enclosure FPS3 are, for example, equal to one another. The respective widths L2 of the first connection portion FPC1 and the second connection portion FPC2 are, for example, equal to each other. Each width L1 of the first surrounding portion FPS1, the second surrounding portion FPS2, and the third surrounding portion FPS3 is equal to, for example, each width L2 of the first connection portion FPC1 and the second connection portion FPC2. The width of each portion of the resistive field plate FP is the shortest distance between the two openings disposed so as to sandwich each portion. In addition, the two widths to be compared being equal means that the ratio of the difference between the two widths to one width is -5% or more and 5% or less. Each width L1 and L2 is 0.1 μm or more and 10 μm or less, for example.

  As shown in FIG. 1, an interval L3 between the first surrounding portion FPS1 and the second surrounding portion FPS2, that is, a length in the extending direction of each first connection portion FPC1, for example, is constant. The distance between the second surrounding portion FPS2 and the third surrounding portion FPS3, that is, the length in the extending direction of each second connection portion FPC2 is, for example, constant. The distance between the first surrounding portion FPS1 and the second surrounding portion FPS2 is equal to, for example, the distance between the second surrounding portion FPS2 and the third surrounding portion FPS3. That is, the length in the extension direction of each first connection portion FPC1 is equal to the length in the extension direction of each second connection portion FPC2.

  As shown in FIG. 1, an interval L4 between two adjacent first connection portions FPC1 is, for example, constant. The distance between two adjacent second connection parts FPC2 is, for example, constant. The distance between two adjacent first connection parts FPC1 is equal to, for example, the distance between two adjacent second connection parts FPC2. From different points of view, the dimensions of the plurality of openings in the resistive field plate FP are, for example, constant.

The sheet resistance value of the resistive field plate FP may be set based on the allowable leakage current value between the emitter electrode EE and the first collector electrode CES, but for example, 0.1 MΩ / □ or more and 10 MΩ / □ or less It is. The thickness of the resistive field plate FP is, for example, 10 nm or more and 300 nm or less, preferably 10 nm or more and 50 nm or less. The impurity amount (dose amount) introduced into the resistive field plate FP is, for example, 1E11 ions / cm ² or more and 1E14 ions / cm ² or less. For example, the sheet resistance value of the resistive field plate FP when the leak current value needs to be 10 μA or less is 1 MΩ / □ or more, and the thickness of the resistive field plate FP is 30 nm or less. The impurity amount (dose amount) introduced into the resistive field plate FP is, for example, 1 × 10 ¹² ions / cm ² or more.

  The third part FP3 of the resistive field plate FP includes, for example, a plurality of surrounding parts arranged to surround the central region CR in addition to the first surrounding part FPS1, the second part PFP2, and the third surrounding part FPS3. And a plurality of connecting portions connecting between two adjacent surrounding portions in the plurality of surrounding portions.

<Configuration of Central Region of Semiconductor Device>
In the semiconductor device SM, a trench gate type IGBT is disposed in the central region CR. As shown in FIG. 15A, the trench gate type IGBT has a p-type collector region PL, a field stop region NL, an n-type n-drift region ND, a p-type body region PB, and n Mainly includes an emitter region NE of the type, an emitter electrode EE, a gate electrode GE, and a second collector electrode CER.

  The collector region PL is disposed on the second surface PS2 of the semiconductor substrate SB. Field stop region NL is arranged on the side of first surface PS1 of collector region PL, and constitutes a pn junction with collector region PL. The second collector electrode CER is disposed on the second surface PS2 and connected to the collector region PL.

  The drift region ND is disposed on the first surface PS1 side of the field stop region NL, and is connected to the field stop region NL. Drift region ND has an n-type impurity concentration lower than that of field stop region NL. Collector region PL is arranged on the second surface PS2 side of drift region ND.

  Body region PB is disposed on the first surface PS1 side of drift region ND, and forms a pn junction with drift region ND.

  The emitter region NE is disposed on the first surface PS1 of the semiconductor substrate SB, and forms a pn junction with the body region PB. The emitter electrode EE is disposed on the first surface PS1 and connected to the emitter region NE.

  A gate trench TR1 and an emitter trench TR2 are formed in the first surface PS1 of the semiconductor substrate SB. The gate groove TR1 is formed to penetrate the emitter surface NE and the body region PB from the first surface PS1 of the semiconductor substrate SB to reach the drift region ND. The gate insulating layer GI is disposed along the inner peripheral surface of the gate trench TR1. The gate electrode GE is embedded in the gate trench TR1. The gate electrode GE is opposed to the body region PB with the gate insulating layer GI interposed.

  The emitter groove TR2 is formed to penetrate the emitter region NE from the first surface PS1 of the semiconductor substrate SB. Emitter region NE and body region PB are disposed on the inner side surface of emitter groove TR2. At the bottom of the emitter trench TR2, a p ++ region PD2 is arranged. The p + region PD1 appears between the p ++ region PD2 and the drift region ND. The barrier metal layer BM is disposed along the inner peripheral surface of the emitter groove TR2.

<Method of Manufacturing Semiconductor Device>
The method of manufacturing the semiconductor device SM will be described with reference to FIGS. 4 to 15. Each (a) of FIGS. 4-15 is a fragmentary sectional view of central region CR of semiconductor device SM. Each (b) of FIGS. 4 to 15 is a partial cross-sectional view of the peripheral region PR of the semiconductor device SM.

  First, as shown in FIGS. 4A and 4B, the semiconductor substrate SB is prepared. The material constituting the semiconductor substrate SB may be any semiconductor material, and includes, for example, silicon (Si). The semiconductor substrate SB may be formed by CZ (Czochralski Method) method, MCZ (Magnetic Field Applied Czochralski Method) method, FZ (Floating Zone Method) method, epitaxial growth method or the like, but is preferably formed by FZ method. There is. A drift region ND is formed in the entire semiconductor substrate SB. The semiconductor substrate SB has a first surface PS1 and a third surface PS3 opposite to the first surface PS1.

  Next, as shown in FIGS. 5A and 5B, in the peripheral region PR, the first insulating film IF1, the surface electric field relaxation region RS, and the well region PW are formed.

  Specifically, first, the first insulating film IF1 is formed on a part of the first surface PS1 of the semiconductor substrate SB. The first insulating film IF1 is formed, for example, by patterning an oxide film formed on the first surface PS1 by photolithography. In plan view, the first insulating film IF1 is annularly formed so as to surround the central region CR.

  Next, a p-type impurity is introduced into the first surface PS1 of the semiconductor substrate SB, whereby the surface electric field relaxation region RS is formed. In plan view, the surface electric field relaxation region RS is annularly formed to surround the central region CR. An outer peripheral portion of the surface electric field relaxation region RS is formed under the first insulating film IF1. The inner peripheral portion of the surface electric field relaxation region RS is formed closer to the central region CR than the first insulating film IF1.

  Next, a p-type impurity is introduced into the first surface PS1 of the semiconductor substrate SB, whereby the well region PW is formed in the surface electric field relaxation region RS. In plan view, well region PW is annularly formed to surround central region CR. The depth from the first surface PS1 of the well region PW is shallower than the depth from the first surface PS1 of the surface electric field relaxation region RS. The impurity concentration of the well region PW is higher than the impurity concentration of the surface electric field relaxation region RS. The method of introducing the p-type impurity is, for example, ion implantation. The p-type impurity is, for example, boron (B).

  Next, as shown in FIGS. 6A and 6B, trench TR is formed in central region CR. Specifically, first, a mask pattern (not shown) is formed covering the area other than the region where trench TR is to be formed. The entire peripheral region PR is covered by the mask pattern. Next, the semiconductor substrate SB is etched using the mask pattern to form a trench TR. After the trench TR is formed, the mask pattern is removed.

  Next, as shown in FIGS. 7A and 7B and FIGS. 8A and 8B, the gate electrode GE is formed in the central region CR. Specifically, first, as shown in FIGS. 7A and 7B, the gate insulating layer GI is formed on the entire surface of the first surface PS1 of the semiconductor substrate SB. The gate insulating layer GI is formed as a gate oxide film on the entire exposed surface on the first surface PS1 side including the inner peripheral surface of the trench TR, for example, by thermal oxidation processing. Next, doped polysilicon film DP1 is formed on gate insulating layer GI. Doped polysilicon film DP1 is formed to be embedded in trench TR.

  Next, as shown in FIGS. 8A and 8B, doped polysilicon film DP1 and gate insulating layer GI are etched back in central region CR and peripheral region PR. Thereby, gate electrode GE embedded in trench TR is formed.

  Next, as shown in FIGS. 9A and 9B, the second insulating film IF2 and the resistive field plate FP are formed in the peripheral region PR.

Specifically, first, the second insulating film IF2 is formed on the first surface PS1. The thickness of the second insulating film IF2 is thinner than the thickness of the first insulating film IF1. Next, a polycrystalline silicon (polysilicon) film is formed on the second insulating film IF2. The thickness of the polycrystalline silicon film is 30 nm or less. Next, p-type impurities or n-type impurities are introduced into the polycrystalline silicon to form a doped polysilicon film. The impurity introduction method is, for example, ion implantation. The p-type impurity is, for example, boron (B) and boron difluoride (BF 2). As for the implantation conditions, in the case of boron (B), the acceleration voltage is, for example, 1 to 50 KeV, and the impurity amount (dose amount) is, for example, 1.0E11 ions / cm ^{2 to} 1.0E14 ions / cm ² . In the case of boron difluoride (BF2), the acceleration voltage is, for example, 1 to 150 KeV, and the impurity (dose amount) is, for example, 1.0E11 ions / cm ^{2 to} 1.0E14 ions / cm ² . The n-type impurity is, for example, phosphorus (P), the acceleration voltage is, for example, 1 to 100 KeV, and the impurity (dose amount) is, for example, 1.0E11 ions / cm ^{2 to} 1.0E14 ions / cm ² . Next, the doped polysilicon film is patterned by photolithography to form resistive field plate FP.

  Next, as shown in FIGS. 10A and 10B, in central region CR, body region PB and emitter region NE are formed, and in peripheral region PR, n + region NS is formed. .

  Specifically, first, in the central region CR, a body region PB is formed by introducing a p-type impurity into the first surface PS1 of the semiconductor substrate SB. The depth of body region PB is shallower than the depth of trench TR. Next, in central region CR, an emitter region NE is formed by introducing an n-type impurity into first surface PS1 of semiconductor substrate SB. In parallel with this, in the peripheral region PR, the n + -type region NS is formed by introducing an n-type impurity into the first surface PS1 of the semiconductor substrate SB. The depth of the emitter region NE is shallower than the depth of the trench TR. The method for introducing the p-type impurity and the n-type impurity is, for example, ion implantation. The p-type impurity is, for example, boron (B). The n-type impurity is, for example, phosphorus (P).

  Next, as shown in FIGS. 11A and 11B, the third insulating film IF3 is formed on the first surface PS1. The third insulating film IF3 is formed to cover the resistive field plate FP. The thickness of the third insulating film IF3 on the first insulating film IF1 is, for example, 0.2 μm or more and 1.0 μm or less. That is, the thickness of the third insulating film IF3 is sufficiently thicker than the thickness of the resistive field plate FP.

  Next, as shown in FIG. 12A, in the central region CR, a portion of the third insulating film IF3, a portion of the emitter region NE, and a portion of the body region PB are removed to form a body region PB. Is exposed.

  In parallel to this, as shown in FIG. 12B, in the peripheral region PR, the contact hole CH1 for removing a part of the third insulating film IF3 to expose a part of the resistive field plate FP. , CH3, a contact hole CH2 exposing a part of the well region PW, and a contact hole CH4 exposing a part of the n + region NS.

  Next, as shown in FIGS. 12A and 12B, a p-type impurity is introduced into each portion exposed from the third insulating film IF3 using the third insulating film IF3 as a mask. Thus, in central region CR, P + region PD2 is formed in body region PB. In peripheral region PR, P + regions PC2 and PC4 are formed in resistive field plate FP, P + region PC6 is formed in well region PW, and P + region PC8 is formed in n + region NS. Ru. Thereafter, p-type impurities are further introduced into the respective portions exposed from the third insulating film IF3. P ++ regions PD1, PC1, PC3, PC5, and PC7 having impurity concentrations higher than that of the P + regions PD2, PC2, PC4, PC6, and PC8 are formed above these. The method of introducing the p-type impurity is, for example, ion implantation. The p-type impurity is, for example, boron (B).

  Next, as shown in FIGS. 13A and 13B, the barrier metal layer BM, the emitter electrode EE, and the first collector electrode CES are formed.

  Specifically, first, on the first surface PS1 of the semiconductor substrate SB, a conductive film to be the barrier metal layer BM, and a conductive film to be the emitter electrode EE and the first collector electrode CES are formed. Next, the stacked body of both conductive films is patterned by photolithography to form the barrier metal layer BM, the emitter electrode EE and the first collector electrode CES.

  Emitter electrode EE is connected to body region PB via P ++ region PD1 and P + region PD2 in central region CR, and resistive via peripheral region PR via P ++ region PC5 and P + region PC1. It is connected to the field plate FP and connected to the well region PW via the P ++ region PC6 and the P + region PC2. The first collector electrode CES is connected to the resistive field plate FP via the P ++ region PC7 and the P + region PC3 in the peripheral region PR, and is connected to the n + region NS via the P + region PC4. .

Next, as shown in FIGS. 14A and 14B, collector region PL is formed.
Specifically, first, a part of the semiconductor substrate SB including the third surface PS3 (see FIG. 13B) is removed to form the second surface PS2. The removal process is performed, for example, by polishing and spin etching. Next, in the central region CR and the peripheral region PR, an n-type impurity is introduced to the second surface PS2, thereby forming the field stop region NL. The method of introducing the n-type impurity is, for example, ion implantation. The n-type impurity is, for example, phosphorus (P). Next, in central region CR and peripheral region PR, collector region PL is formed by introducing a p-type impurity into second surface PS2. The method of introducing the p-type impurity is, for example, ion implantation. The p-type impurity is, for example, boron (B).

  Next, a laser annealing process is performed on the semiconductor substrate SB. Thereby, each impurity introduced into the semiconductor substrate SB is activated.

Next, as shown in FIGS. 15A and 15B, the second collector electrode CER is formed on the second surface PS2. Thus, the semiconductor device SM is formed.
<Function effect>
Next, the function and effect of the semiconductor device SM will be described. The semiconductor device SM includes a semiconductor substrate SB, a first insulating film IF1, and a resistive field plate FP. The semiconductor substrate SB has a well region PW, a surface electric field relaxation region RS arranged to surround the well region PW, and an n + arranged to face the well region PW with the surface electric field relaxation region RS interposed therebetween. And region NS. The first insulating film IF1 is disposed on the surface electric field relaxation region RS of the semiconductor substrate SB. The resistive field plate FP is disposed on the first insulating film IF1. The resistive field plate FP is disposed between the first part FP1 connected to the well region PW, the second part FP2 connected to the n + region NS, and the first part FP1 and the second part FP2. And a third part FP3 which connects them. The third part FP3 surrounds the periphery of the first part FP1 in a plan view, and branches from the second part FP2 to a first path from the second part FP2 to the first part FP1 and the first path. And a second route to the part FP1.

  Since the third part FP3 of the resistive field plate FP has the first path and the second path, for example, even when the second path is disconnected, the first path is the first part FP1 and the second part It can continue to function as a current path to and from FP2. In this case, the resistive field plate FP can continue to function as a field plate even after the disconnection of the second path. As a result, in the semiconductor device SM provided with the resistive field plate FP, the reduction in the withstand voltage characteristic caused by the disconnection is suppressed as compared with the semiconductor device provided with the conventional field plate.

  In the case where a short circuit occurs between the first surrounding portion FPS1, the second surrounding portion FPS2, and the plurality of first connection portions FPC1, the reduction width of the resistance value of the resistive field plate FP is adjacent to the above radiation direction Compared to a conventional field plate in which two ring parts are connected by only one connection, this is suppressed. As a result, in the semiconductor device SM provided with the resistive field plate FP, the decrease in the withstand voltage characteristic caused by the short circuit is suppressed as compared with the semiconductor device provided with the conventional field plate.

  In the semiconductor device SM, the first surrounding portion FPS1 and the second surrounding portion FPS2 have a portion extending along the first direction X and a portion extending along the second direction Y. The plurality of first connection portions FPC1 are a first group of first connection portions FPC1 which connect portions extending in the first direction X of the first surrounding portion FPS1 and the second surrounding portion FPS2 in parallel with each other, A second group of first connection portions FPC1 are connected in parallel to portions extending in the second direction of the first surrounding portion FPS1 and the second surrounding portion FPS2. The first connection portion FPC1 of the first group extends in the second direction Y. The first connection portion FPC1 of the second group extends along the first direction X.

  For example, in a field plate in which all the first connection portions FPC1 are disposed between the portions extending along the first direction X of the first surrounding portion FPS1 and the second surrounding portion FPS2, the second direction of the first surrounding portion FPS1 The fluctuation range of the resistance value of the field plate when a break or short occurs in the portion extending along Y is compared to that when the break occurs in the portion extending along the first direction X of the first surrounding portion FPS1 ,growing. And, since it is difficult to control the position where the disconnection or short occurs in the manufacturing process of the semiconductor device SM, it is difficult to control the fluctuation range of the resistance value of such a field plate.

  On the other hand, according to the resistive field plate FP, the plurality of first connection portions FPC1 include the first connection portion FPC1 of the first group and the first connection portion FPC1 of the second group. Compared to a field plate in which all the first connection portions FPC1 are disposed between the portions of the first enclosure FPS1 and the second enclosure FPS2 extending along the first direction X, the resistance value at the time of disconnection or short circuit The fluctuation is suppressed.

  Further, the potential distribution in the circumferential direction of the resistive field plate FP is arranged such that all of the plurality of first connection portions FPC1 extend along only one of the first direction X or the second direction Y. Compared to that of the resistive field plate FP, it is homogenized. As a result, in the semiconductor device SM including the resistive field plate FP, all the plurality of first connection portions FPC1 are arranged so as to extend along only one of the first direction X or the second direction Y. Compared with the semiconductor device provided with the field plate FP, the electric field distribution in the surface electric field relaxation region RS is made uniform in the circumferential direction.

  In the semiconductor device SM, the first surrounding portion FPS1 and the second surrounding portion FPS2 of the resistive field plate FP are arranged annularly.

  The potential distribution in the circumferential direction of such a resistive field plate FP is made uniform as compared with that of a conventional field plate arranged in a spiral. As a result, in the semiconductor device SM provided with the resistive field plate FP, the electric field distribution in the surface electric field relaxation region RS is made uniform in the circumferential direction as compared with the semiconductor device provided with the spirally or meanderingly arranged field plate. Ru.

  The planar shape of the semiconductor device SM is a quadrilateral. The resistive field plate FP is arranged to have a 90 degree rotational symmetry in plan view.

  The potential distribution in the circumferential direction of such a resistive field plate FP is made uniform as compared with that of a conventional field plate arranged in a spiral. As a result, in the semiconductor device SM provided with the resistive field plate FP, the electric field distribution in the surface electric field relaxation region RS is made uniform in the circumferential direction as compared with the semiconductor device provided with the spirally or meanderingly arranged field plate. Ru.

  In the semiconductor device SM, the resistive field plate FP connects between the third enclosure FPS3 disposed to surround the second enclosure FPS2, the second enclosure FPS2, and the third enclosure FPS3. And a plurality of second connection parts FPC2.

  In the resistive field plate FP, as the number of the surrounding portion and the connecting portion increases, the number of connection points between the surrounding portion and the connecting portion increases and the number of current paths increases, and the surrounding portion and the connecting portion The distance between the multiple connection points of Therefore, in the semiconductor device SM, as the number of the surrounding portions and the connecting portions increases, the decrease in the withstand voltage characteristic due to the disconnection, the short circuit, or the like is suppressed.

  The third part FP3 of the resistive field plate FP connects the first part FP1 and the second part FP2 with the shortest distance. The shortest distance between the first part FP1 and the second part FP2 is determined by the distance between the emitter electrode EE and the first collector electrode CES.

  The potential distribution of the resistive field plate FP in the radial direction is the same as that of the resistive field plate FP in which the third part FP3 does not connect the first part FP1 and the second part FP2 at the shortest distance. It changes continuously and gradually compared to the potential distribution in the direction. Therefore, the resistive field plate FP has a surface field relaxation region RS in comparison with the resistive field plate FP in which the third part FP3 does not connect the first part FP1 and the second part FP2 at the shortest distance. The electric field distribution in the above-mentioned radiation direction can be changed gradually and continuously. As a result, in the surface field relaxation region RS, the length in the radiation direction of the resistive field plate FP required to sufficiently reduce the electric field concentration in the radiation direction is the third portion FP3 is the first portion FP1. And the length in the radial direction of the resistive field plate FP which is not connected at the shortest distance between the second portion FP2 and the second portion FP2. That is, the resistive field plate FP has an electric field in the peripheral region PR as compared to the resistive field plate FP in which the third part FP3 does not connect the first part FP1 and the second part FP2 at the shortest distance. Concentration can be alleviated more effectively.

  Further, in the above-mentioned resistive field plate FP, it is necessary to increase or decrease the area of central region CR, but when changing the specification such that it is not necessary to increase or decrease the resistance value of resistive field plate FP from the viewpoint of withstand voltage It is assumed.

  For example, consider designing a second type semiconductor device SM having a specification different from that of the first type semiconductor device SM based on the first type semiconductor device SM. The second type semiconductor device SM is required to have a withstand voltage equivalent to that of the first type semiconductor device SM, but is required to increase the current of the IGBT more than the first type semiconductor device SM. . In the second type semiconductor device SM, the area of the central region CR is set to be relatively large compared to the first type semiconductor device SM in accordance with the demand for increasing the current. On the other hand, the width of the peripheral region PR in the radial direction contributing to the withstand voltage may be equal between the first type semiconductor device SM and the second type semiconductor device SM.

  When the design change is performed, when the area of the central region CR is increased, the circumferential length of the peripheral region PR is increased. Therefore, the resistance value of the resistive field plate FP in which the third part FP3 does not connect the first part FP1 and the second part FP2 at the shortest distance is added to the length in the radial direction of the third part FP3. It also depends on the length of the circumferential direction. Therefore, in such a resistive field plate FP, in order to suppress an increase or decrease in the resistance value in the above-described design change of the central region CR, a design change of the resistive field plate FP may also be required. For example, a design change is made such that the sheet resistance value of the field plate FP is reduced so as to cancel the increase in the resistance value of the field plate FP accompanying the increase of the circumferential length of the peripheral region PR. It may be required.

  On the other hand, in the resistive field plate FP in which the third part FP3 connects the first part FP1 and the second part FP2 with the shortest distance in the case of the design change, the circumferential length of the peripheral region PR in the circumferential direction The increase or decrease of the resistance due to the increase in length is suppressed compared to the resistive field plate FP in which the third part FP3 does not connect the first part FP1 and the second part FP2 at the shortest distance. There is. Therefore, in the above-described resistive field plate FP in which the third part FP3 connects the first part FP1 and the second part FP2 at the shortest distance, no change is necessary when changing the design of the central region CR as described above. It can be taken.

  The resistive field plate FP of the semiconductor device SM has a lattice shape in plan view.

  Such a resistive field plate FP can satisfy the entire configuration of the resistive field plate FP described above. Therefore, in the semiconductor device SM provided with the resistive field plate FP, the deterioration of the pressure resistance characteristic due to the disconnection or the short circuit is suppressed, and the pressure resistance characteristic is made uniform in the circumferential direction. In addition, the field plate FP can arrange the current paths at a high density on the peripheral region PR as compared with the conventional field plate.

  In the resistive field plate FP of the semiconductor device SM, the widths of the first surrounding portion FPS1, the second surrounding portion FPS2, and the plurality of first connection portions FPC1 are equal to one another.

  In such a resistive field plate FP, compared to the case where the respective widths of the first surrounding portion FPS1, the second surrounding portion FPS2, and the plurality of first connection portions FPC1 are provided to be different, the first surrounding portion The current values flowing through the FPS 1, the second surrounding portion FPS 2, and the plurality of first connection portions FPC 1 are equalized. Therefore, in the semiconductor device SM provided with the resistive field plate FP, the electric field distribution in the surface electric field relaxation region RS is uniformed as compared with the semiconductor device SM provided with the resistive field plate FP different in each width.

  In the semiconductor device SM, the sheet resistance value of the resistive field plate FP is 0.1 MΩ / □ or more and 10 MΩ / □ or less.

  The conventional resistive field plate is formed simultaneously with, for example, the gate electrode of the IGBT formed in the central region CR, and therefore has a thickness required for the gate electrode. Therefore, the thickness of the conventional resistive field plate is 600 nm or more, and its sheet resistance value is less than 1 MΩ / □.

  The sheet resistance of the resistive field plate FP is higher than that of the conventional field plate. The resistance value of the resistive field plate FP is determined by the sheet resistance value and the length of each current path in the third part FP3. Therefore, the sheet resistance value of the resistive field plate FP is increased compared to that of the conventional field plate, so that the length of each current path required to realize an arbitrary resistance value is It can be shortened compared to that of the field plate. Further, the sheet resistance value of the resistive field plate FP is made higher than that of the conventional field plate, so that the first required for realizing an arbitrary resistance value in the resistive field plate FP. The width of the enclosure FPS1, the first connection FPC1, etc. may be wider than that of the conventional field plate. Therefore, according to the field plate FP, the area occupied by one current path on the first surface PS1 can be made smaller than that of the conventional field plate. As a result, in the field plate FP, although the plurality of current paths are arranged at a higher density, the function as the field plate is less likely to be lost due to the disconnection.

  The length of each current path of the field plate FP having the sheet resistance value may be, for example, the shortest distance between the first part FP1 and the second part FP2. As a result, as described above, at the time of the design change, the design change for increasing or decreasing the length in the radial direction is unnecessary.

  In the semiconductor device SM, the thickness of the resistive field plate FP is 10 nm or more and 50 nm or less.

  That is, the thickness of the resistive field plate FP is thinner than the thickness of the conventional field plate. The sheet resistance value of the resistive field plate FP is determined by its thickness and dose. Therefore, the resistive field plate FP can have a higher resistance than the sheet resistance value of the conventional field plate while having the dose equivalent to that of the conventional field plate.

  In addition, as shown in FIG. 16, the thickness of the resistive field plate FP is sufficiently thin compared to the thickness of the third insulating film IF 3, thereby forming a third conductive field plate FP. The thickness of the insulating film IF3 is sufficiently thick also around the opening. On the other hand, since the thickness of the conventional resistive field plate FP shown in FIG. 17 is not sufficiently thinner than the thickness of the third insulating film IF3, it is formed to cover the resistive field plate FP. The thickness of the third insulating film IF3 is partially thin around the opening.

  As a result, in the semiconductor device SM provided with the above-described resistive field plate FP, the intrusion of water from the outside into the periphery of the resistive field plate FP is suppressed as compared with the semiconductor device provided with the resistive field plate FP. In the semiconductor device SM including the resistive field plate FP, the thin film of the third insulating film IF3 is formed in the ion implantation step (see FIGS. 12A and 12B) performed using the third insulating film IF3 as a mask. Ion implantation into the resistive field plate FP or the semiconductor substrate SB or the like through the portion is suppressed.

  In the semiconductor device SM, the resistive field plate FP has a plurality of extending portions linearly extending the first portion FP1 and the second portion FP2 in a plan view. The sheet resistance value of the resistive field plate FP is 0.1 MΩ / □ or more and 10 MΩ / □ or less.

Second Embodiment
As shown in FIG. 18, the semiconductor device SM2 according to the second embodiment basically has the same configuration as the semiconductor device SM according to the first embodiment, but in plan view, a plurality of resistive field plates FP The difference is that the openings OP of are arranged in a staggered manner. In the staggered configuration, a first opening OP group arranged to be spaced apart in the first direction X is arranged to be spaced apart from each other in the first direction X, and the first opening OP An arrangement state in which the second opening OP group adjacent to the group in the second direction Y is shifted in the first direction X by a distance less than the opening width of each opening OP. The shift amount is, for example, half the opening width of each opening OP.

  As shown in FIG. 18, each of the first surrounding portion FPS1 and the second surrounding portion FPS2 of the third portion FP3 of the resistive field plate FP has a portion linearly extending along the first direction X, and a second portion And a portion extending on the rectangular wave along the direction Y. The plurality of second connection portions FPC2 are arranged so as not to be linearly continuous with the plurality of first connection portions FPC1 on a partial region of the peripheral region PR arranged to sandwich the central region CR in the second direction Y It is done.

  Similar to the resistive field plate FP shown in FIG. 1, the resistive field plate FP shown in FIG. 18 also has a first surrounding portion FPS1, a second surrounding portion FPS2, and a plurality of first connection portions FPC1. There is. Therefore, the semiconductor device SM2 can exhibit the same effect as the semiconductor device SM described above.

Third Embodiment
As shown in FIG. 19, the semiconductor device SM3 according to the third embodiment basically has the same configuration as the semiconductor device SM according to the first embodiment, but the third part FP3 of the resistive field plate FP is The difference is that the first part FP1 and the second part FP2 are connected in excess of the shortest distance.

  In plan view, the plurality of first connection portions FPC1 extending along the first direction X are along the second direction Y in the plurality of second connection portions FPC2 extending along the first direction X and the second surrounding portion FPS2. It is connected via the part which extends. A plurality of first connection portions FPC1 extending along the second direction Y are a plurality of second connection portions FPC2 extending along the second direction Y, and portions extending along the first direction X in the second surrounding portion FPS2. Connected through.

  The length of a portion extending along the second direction Y in the second surrounding portion FPS2 connecting the plurality of first connection portions FPC1 extending along the first direction X and the plurality of second connection portions FPC2 is The length in the extending direction of the plurality of first connection portions FPC1 and the plurality of second connection portions FPC2 is longer than the length in the first direction X.

  In a plan view, the distance between the two first connection portions FPC1 adjacent in the circumferential direction among the plurality of first connection portions FPC1 is beyond the length in the extension direction of the first connection portion FPC1. In plan view, the extending direction of one first connection portion FPC1 adjacent in the circumferential direction intersects the extending direction of the other first connection portion FPC1, for example. The one first connection portion FPC1 adjacent in the circumferential direction extends along the first direction X, and the other first connection portion FPC1 extends along the second direction Y.

  For example, the portions of the first surrounding portion FPS1 and the second surrounding portion FPS2 extending linearly along the first direction X are connected by only one first connection portion FPC1, and the first surrounding portion FPS1 and the first surrounding portion FPS1 The portions of the two surrounding portions FPS2 extending linearly along the second direction Y are connected only by one other first connection portion FPC1.

  Similar to the resistive field plate FP shown in FIG. 1, the resistive field plate FP shown in FIG. 19 also has a first surrounding portion FPS1, a second surrounding portion FPS2, and a plurality of first connection portions FPC1. There is. Therefore, the semiconductor device SM2 can exhibit the same effect as the semiconductor device SM described above.

Embodiment 4
As shown in FIG. 20, the semiconductor device SM4 according to the fourth embodiment basically has the same configuration as the semiconductor device SM according to the first embodiment, but the third portion FP3 of the resistive field plate FP is It differs in that it has a spirally arranged pattern shape.

  The third part FP3 of the resistive field plate FP connects the first pattern and the second pattern spirally arranged between the first part FP1 and the second part FP2, and the first pattern and the second pattern. And a plurality of third patterns. The second pattern is spaced apart from the first pattern in the radial direction. In plan view, the third part FP3 has a rail-like structure.

  Each of the first pattern and the second pattern has a plurality of concentrically arranged surrounding portions and a plurality of connecting portions connecting in series the adjacent surrounding portions in the radial direction. The first pattern has a first enclosure FPS1, a third enclosure FPS3, and a fifth enclosure FPS5, and a third connection FPC3 and a fifth connection FPC5. The second pattern includes a second enclosure FPS2, a fourth enclosure FPS4, and a sixth enclosure FPS6, and a fourth connection FPC4 and a sixth connection FPC6. The third pattern includes a plurality of first connection portions FPC1, a plurality of seventh connection portions FPC7, and a plurality of eighth connection portions FPC8.

  The second surrounding portion FPS2 is disposed to surround the first surrounding portion FPS1. The third surrounding portion FPS3 is disposed to surround the second surrounding portion FPS2. The fourth surrounding portion FPS4 is disposed to surround the third surrounding portion FPS3. The fifth surrounding portion FPS5 is disposed to surround the fourth surrounding portion FPS4. The sixth surrounding portion FPS6 is disposed to surround the fifth surrounding portion FPS5.

  The third connection portion FPC3 connects the first surrounding portion FPS1 and the third surrounding portion FPS3 in series. The fifth connection portion FPC5 connects the third surrounding portion FPS3 and the fifth surrounding portion FPS5 in series. The first surrounding part FPS1, the third connecting part FPC3, the third surrounding part FPS3, the fifth connecting part FPC5, and the fifth surrounding part FPS5 are connected in series in order.

  The fourth connection portion FPC4 connects the second surrounding portion FPS2 and the fourth surrounding portion FPS4 in series. The sixth connection portion FPC6 connects the fourth surrounding portion FPS4 and the sixth surrounding portion FPS6 in series. The second surrounding portion FPS2, the fourth connecting portion FPC4, the fourth surrounding portion FPS4, the sixth connecting portion FPC6 and the sixth surrounding portion FPS6 are connected in series in order.

  The plurality of first connection portions FPC1 connect the first surrounding portion FPS1 and the second surrounding portion FPS2 in parallel to each other. The plurality of seventh connection portions FPC7 connect the third surrounding portion FPS3 and the fourth surrounding portion FPS4 in parallel to each other. The plurality of eighth connection portions FPC8 connect the fifth surrounding portion FPS5 and the sixth surrounding portion FPS6 in parallel to each other.

  One end of the first surrounding portion FPS1 is connected to the first portion FP1. The other end of the first surrounding portion FPS1 is connected to one end of the third surrounding portion FPS3 via the third connection portion FPC3. One end of the second surrounding portion FPS2 is connected to the first portion FP1. The other end of the second surrounding portion FPS2 is connected to one end of the fourth surrounding portion FPS4 via the fourth connection portion FPC4. The first surrounding portion FPS1 and the second surrounding portion FPS2 are connected by a plurality of first connection portions FPC1. The other end of the third surrounding portion FPS3 is connected to one end of the fifth surrounding portion FPS5 via the fifth connection portion FPC5. The other end of the fourth surrounding portion FPS4 is connected to one end of the sixth surrounding portion FPS6 via the sixth connection portion FPC6.

  Although the IGBT is disposed in the central region CR in the semiconductor devices SM, SM2, SM3, and SM4, the present invention is not limited to this. In the central region CR, any semiconductor element may be disposed, and for example, a MOSFET or a diode may be disposed. In the semiconductor devices SM, SM2, SM3 and SM4, the conductivity type of each region which is n-type may be p-type and the conductivity type of each region may be n-type. For example, the conductivity type of the first semiconductor region may be n-type, and the conductivity type of the second semiconductor region may be p-type.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

  BM barrier metal layer, CES first collector electrode, CER second collector electrode, CH1, CH2, CH3, CH4 contact hole, CR central region, DP1 doped polysilicon film, EE emitter electrode, FP resistive field plate, FP1 first 1 part, FP2 second part, FP3 third part, FPC connection part, FPC1 first connection part, FPC2 second connection part, FPC3 third connection part, FPC4 fourth connection part, FPC5 fifth connection part, FPC6 sixth Connection part, FPC7 seventh connection part, FPC8 eighth connection part, FPS1 first enclosure, FPS2 second enclosure, FPS3 third enclosure, FPS4 fourth enclosure, FPS5 fifth enclosure, FPS6 sixth enclosure , GE gate electrode, GI gate insulating layer, IF1 first insulating film, IF2 second insulating film, IF3 third Edge film, ND drift region, NE emitter region, NL field stop region, OP opening, PB body region, PL collector region, PR peripheral region, PS1 first surface, PS2 second surface, PS3 third surface, PW well region , RS surface electric field relaxation region, SB semiconductor substrate, SM, SM3, SM4 semiconductor device, trench for TR1 gate, trench for TR2 emitter.

Claims (12)

A first semiconductor region, a second semiconductor region arranged to surround the first semiconductor region in plan view, and the first semiconductor between the first semiconductor region and the second semiconductor region in plan view A semiconductor substrate including a third semiconductor region arranged to surround the region;
An insulating film disposed on the third semiconductor region;
A field plate electrically connected to each of the first semiconductor region and the second semiconductor region and facing the third semiconductor region through the insulating film;
The field plate is
A first portion having an annular shape in plan view;
A second part surrounding the outside of the first part in a plan view;
A third part connecting the first part and the second part,
The third part surrounds the periphery of the first part in a plan view, and branches from the second part to a first path extending from the second part to the first part and the first path. A semiconductor device having a second path leading to one part;   The third part is a first surrounding part surrounding the periphery of the first part in a plan view, a second surrounding part surrounding a periphery of the first surrounding part in a plan view, and the first surrounding part in a plan view The semiconductor device according to claim 1, further comprising: a plurality of first connection portions connecting the second enclosure portion. The first surrounding portion has a first portion extending along a first direction and a second portion extending along a second direction intersecting the first direction,
The second surrounding portion has a third portion extending in the first direction and a fourth portion extending in the second direction,
A part of the plurality of first connection parts connects the first part and the third part in parallel with each other, and another part of the plurality of first connection parts is the second The semiconductor device according to claim 2, wherein the portion and the fourth portion are connected in parallel to each other.   The semiconductor device according to claim 2, wherein the first surrounding portion and the second surrounding portion are annularly arranged.   The semiconductor device according to claim 2, wherein the widths of each of the first surrounding portion, the second surrounding portion, and the plurality of first connection portions are equal to one another. In plan view, the outer shape of the semiconductor device is a quadrilateral,
The semiconductor device according to claim 1, wherein the field plate is arranged to have a 90 degree rotational symmetry in a plan view.   The semiconductor device according to claim 1, wherein the third portion connects the first portion and the second portion at a shortest distance in a plan view.   The semiconductor device according to claim 1, wherein the third portion has a lattice shape in a plan view.   The semiconductor device according to claim 1, wherein the third portion has a zigzag shape in a plan view.   The semiconductor device according to claim 1, wherein a sheet resistance value of the field plate is 0.1 MΩ / □ or more and 10 MΩ / □ or less.   The semiconductor device according to claim 10, wherein a thickness of the field plate is 10 nm or more and 50 nm or less. A first semiconductor region, a second semiconductor region arranged to surround the first semiconductor region in plan view, and the first semiconductor between the first semiconductor region and the second semiconductor region in plan view A semiconductor substrate including a third semiconductor region arranged to surround the region;
An insulating film disposed on the third semiconductor region;
A field plate electrically connected to each of the first semiconductor region and the second semiconductor region and facing the third semiconductor region through the insulating film;
The sheet resistance value of the field plate is 0.1 MΩ / □ or more and 10 MΩ / □ or less,
The semiconductor device according to claim 1, wherein the field plate has a plurality of extending portions linearly extending between the first semiconductor region and the second semiconductor region in a plan view.

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