JP2019098092A - Game machine - Google Patents

Abstract

To provide a game machine capable of increasing fun of a game while appropriately managing a game state.SOLUTION: When it is determined to be shifted to an ART game state, it is determined to be shifted to an AT game state (ART shift) prior to the shift of the ART game state. When it is not determined to be shifted to the ART game state, it is determined to be shifted to the AT game state (ART non-shift). The probability in which information of stop operation advantageous to a player is notified exceeding a predetermined number of times (e.g. twice or more) in the AT game state (ART shift) is higher than the probability in which information of the stop operation advantageous to the player is notified exceeding a predetermined number of times in the AT game state (ART non-shift).SELECTED DRAWING: Figure 36

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachislot having a plurality of reels provided with a plurality of symbols on each surface, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit The machine is known. The start switch detects that the start lever has been operated by the player after game media such as medals and coins have been inserted into the gaming machine (hereinafter also referred to as "start operation"), and all reels are rotated. Output a signal requesting start. The stop switch detects that the player has pressed a stop button provided corresponding to each reel (hereinafter also referred to as “stop operation”), and outputs a signal requesting stop of rotation of the corresponding reel. Do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

  In such a gaming machine, when the start operation is detected, lottery processing using random numbers (hereinafter referred to as "internal lottery processing") is performed on the program, and the result of the lottery (hereinafter referred to as "internal winning combination") Stop the rotation of the reel based on the timing of the stop operation). Then, when the rotation of all the reels is stopped and the combination (display combination) of the symbols related to the establishment of the winning is displayed, a bonus corresponding to the combination of the symbols is given to the player. In addition, as an example of the privilege given to the player, the operation of the re-game (hereinafter, also referred to as "replay") in which the internal lottery process is performed again without paying out the game medium (medal and the like) and consuming the game medium. , Activation of a bonus game, etc., where the payout opportunities for gaming media are increased.

  In addition, in such a gaming machine, a function to notify the procedure of the stop operation which is advantageous for the player so that the probability of establishment of a specific combination (for example, the combination related to the payout of gaming media) is increased, , "AT") has a function. In addition, when a specific condition such as a specific symbol combination is displayed, the game state where the winning probability of replay is higher than normal is activated, that is, the replay time (hereinafter referred to as "RT") Some have functions. In addition, there are some which have a function of assist replay time (hereinafter referred to as "ART") in which AT and RT operate simultaneously.

  Such a game machine usually controls the main game operation of the game machine such as the determination of the internal winning combination, the rotation and stop of each reel, and the start and end of the above AT, RT, or ART ( A production control device (main control circuit) in which the main control circuit is mounted, and an effect control device (sub control circuit) in which the effect control circuit (sub control circuit) for controlling the rendering operation of the gaming machine such as displaying a video is mounted And the control circuit performs control of each of them to control the entire gaming machine.

  In a conventional gaming machine, a lottery as to whether or not to shift to an advantageous state (for example, an ART state) advantageous to the player is made, and based on the result of the lottery, a prognostic state (ie, transition to an advantageous state) It is known that it is possible to transition to a true precursor state if a decision is made) or a false precursor state (ie a false precursor state if it is not decided to transition to an advantageous state) (e.g. , Patent Document 1).

JP, 2015-39536, A

  By the way, in recent years, in such a gaming machine, in order to suppress excessive cheating of the player, a section (advantageous section) of a game advantageous to the player such as the above-mentioned advantageous state should be started. In principle, it was required to immediately shift to the advantageous section when

  However, if it is made to immediately shift to the advantageous section based on the fact that it is decided to start the advantageous section, there is an advantage that it is easy to manage the gaming state and it is easy for the player to recognize the success or failure. However, there is also a disadvantage that the fun of the game is reduced because the success or failure can be recognized immediately.

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of improving the fun of gaming while appropriately managing the gaming state.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state), a first advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state, a second advantageous state (for example, an AT gaming state (ART transition)), and a second 3 advantageous states (for example, AT gaming state (ART transition));
A first advantageous state of determining whether or not to shift to the first advantageous state when a specific condition is satisfied in the normal state (for example, when a specific role shown in FIGS. 33A and 33B is won) Determination means (for example, main CPU 101);
If the specific condition is satisfied in the normal state, and it is determined to shift to the first advantageous state by the first advantageous state determining means, prior to the transition to the first advantageous state Second advantageous state determining means (for example, the main CPU 101) capable of determining whether or not to shift to the second advantageous state;
In the case where the specific condition is satisfied in the normal state, and it is not determined to shift to the first advantageous state by the first advantageous state determining means, the mode is shifted to the third advantageous state And third advantageous state determination means (for example, the main CPU 101) capable of determining whether or not
The first advantageous state, the second advantageous state, and the third advantageous state are states in which information of stop operation advantageous to the player can be notified,
The second advantageous state and the third advantageous state can be ended when the information of the stop operation advantageous to the player is notified a predetermined number of times (for example, once),
The probability that the information of the stop operation which is advantageous to the player in the second advantageous state is notified more than the predetermined number is that the information of the stop operation which is advantageous to the player in the third advantageous state is more than the predetermined number A gaming machine characterized by having a higher probability than being notified.

  According to the gaming machine configured as described above, the benefits provided in the second advantageous state (for example, AT gaming state (ART transition)) and the third advantageous state (for example, AT gaming state (ART non transition)) become excessive. The expectation can be changed by the number of times the information of the stop operation which is advantageous to the player is notified while suppressing the occurrence of a drop. Therefore, the fun of the game can be improved while appropriately managing the gaming state.

When it is decided to shift to the second advantageous state by the second advantageous status determining means, and when it is decided to shift to the third advantageous state by the third advantageous status determining means, 2) A duration determining means (for example, the main CPU 101) for determining the duration (for example, the AT duration) of the two advantageous states or the third advantageous state
The second advantageous state and the third advantageous state end when the duration determined by the duration determining means has elapsed when the information on the stop operation advantageous to the player is notified the predetermined number of times If the information on the stop operation which is advantageous to the player is not notified the predetermined number of times, it does not end even if the duration determined by the duration determining means has elapsed. Gaming machine.

  According to the gaming machine configured as described above, the benefits provided in the second advantageous state (for example, AT gaming state (ART transition)) and the third advantageous state (for example, AT gaming state (ART non transition)) become excessive. Since it is possible for the player to obtain the minimum benefit in these gaming states while suppressing the game being over, the fun of the game can be further improved.

  In the first advantageous state, the second advantageous state, and the third advantageous state, there is provided a notification means (for example, a state indicator) for informing the player that the game section is advantageous for the game. The gaming machine described above.

  According to the gaming machine configured as described above, since the player is shown to be a series of advantageous sections, even when a plurality of gaming states having different degrees of advantageous constitute a series of advantageous sections, Can prevent the player from being overwhelmed.

  According to the gaming machine having the above configuration, it is possible to improve the fun of the game while appropriately managing the gaming state.

It is a figure for demonstrating the functional flow of the game machine in one Embodiment of this invention. It is a perspective view showing the appearance structure of the game machine in one embodiment of the present invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the structure of the selector with which the game machine of one Embodiment of this invention is equipped. FIG. 1 is a block diagram showing an entire configuration of a circuit included in a game machine according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram showing an internal configuration of a microprocessor in one embodiment of the present invention. It is a block diagram showing an internal configuration of a sub control circuit in an embodiment of the present invention. It is a block diagram of the various registers which the main CPU in one Embodiment of this invention has. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure explaining the security mode of the main control circuit in one embodiment of the present invention. FIG. 7 is a diagram showing a transition flow of the gaming state between the bonus state and the non-bonus state of the pachislot according to the embodiment of the present invention. FIG. 8 is a diagram showing a transition flow of the gaming state in the advantageous section and the normal section of the gaming machine according to the embodiment of the present invention. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination in the one embodiment of this invention, stop operation order (strike order), a display combination etc. It is a figure which shows the correspondence of the internal winning combination in the one embodiment of this invention, stop operation order (strike order), a display combination etc. It is a figure which shows the structure of the hit request | requirement flag storage area | region in one Embodiment of this invention, and a prize operation flag storage area | region. It is a figure which shows the structure of the carry-over combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the action | operation stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and a subflag in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the normal game state in one Embodiment of this invention. It is a figure which shows an example of the various tables referred in the normal game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in AT game state in one Embodiment of this invention. It is a figure which shows an example of the navi mode lottery table in one Embodiment of this invention. It is a figure which shows an example of the various tables referred in AT game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in ART preparation state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in ART1 game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in ART1 game state in one Embodiment of this invention. It is a figure which shows an example of the various tables referred in the ART1 game state in one Embodiment of this invention. It is a figure which shows an example of the various tables referred in the ART1 game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in ART2 game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in ART3 game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in ART4 game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in CZ1 game state in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in CZ2 game state in one Embodiment of this invention. It is a figure which shows the correspondence of each game state in one Embodiment of this invention, an internal winning combination, and navigation data. It is a flowchart which shows the example of a process at the time of the power activation (reset interruption) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flow chart which shows an example of game return processing in one embodiment of the present invention. It is a flowchart which shows the example of the setting change confirmation process in one Embodiment of this invention. It is a flow chart which shows an example of setting change command generation storage processing in one embodiment of the present invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of a power-off (external) process in one Embodiment of this invention. It is a flowchart which shows the example of the checksum generation process (outside of prescription | regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the thumb check process (outside of prescription | regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the thumb check process (outside of prescription | regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the main processing (main operation processing) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flow chart which shows an example of medal acceptance / start check processing in one embodiment of the present invention. It is a flow chart which shows an example of medal acceptance / start check processing in one embodiment of the present invention. It is a flow chart which shows an example of medal insertion processing in one embodiment of the present invention. It is a flowchart which shows the example of the medal input check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal input check process in one Embodiment of this invention. It is a flowchart which shows the example of the error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random value acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compression data storage process in one Embodiment of this invention. 6 is a flowchart illustrating an example of state-based control processing at the time of game start in one embodiment of the present invention. It is a flowchart which shows the example of a game start time advantageous area common process in one Embodiment of this invention. It is a flow chart which shows an example of processing during AT at the time of game start in one embodiment of the present invention. It is a flowchart which shows the example of a process in ART1 at the time of game start in one Embodiment of this invention. It is a flowchart which shows the example of a process in ART1 at the time of game start in one Embodiment of this invention. It is a flow chart which shows an example of processing during a game start at the time of the game start in one embodiment of the present invention. It is a flowchart which shows the example of the drawing-in priority storing process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the logical product operation process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing-in priority acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing-in priority acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control processing in one Embodiment of this invention. It is a flowchart which shows the example of the prize-winning search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of the prize-winning check / medal payout process in one Embodiment of this invention. It is a flow chart which shows an example of medal number-of-payouts check processing in one embodiment of the present invention. It is a flow chart which shows an example of BB check processing in one embodiment of the present invention. It is a flow chart which shows an example of RT check processing in one embodiment of the present invention. 7 is a flowchart showing an example of the game end state control process according to the embodiment of the present invention. It is a flow chart which shows an example of common processing at the time of game end in one embodiment of the present invention. It is a flow chart which shows an example of processing during AT at the time of game end in one embodiment of the present invention. It is a flowchart which shows the example of a process in ART1 at the time of the game end in one Embodiment of this invention. It is a flow chart which shows an example of processing usually at the time of game end in one embodiment of the present invention. It is a flowchart which shows the example of the interruption process performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the communication data transmission process in one Embodiment of this invention. It is a flowchart which shows the example of the WDT setting process in one Embodiment of this invention. It is a flow chart which shows an example of 7 segments LED drive processing in one embodiment of the present invention. It is a flow chart which shows an example of 7 segment display data generation processing in one embodiment of the present invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a timing chart which shows an example of operation at the time of power activation of a game machine in one embodiment of the present invention. It is a timing chart which shows an example of operation at the time of medal insertion of a game machine in one embodiment of the present invention. It is a figure for demonstrating the ending state of the game machine in one Embodiment of this invention.

  Hereinafter, as a gaming machine according to an embodiment of the present invention, a pachislot machine is taken as an example, and the configuration and operation thereof will be described with reference to the drawings. In the present embodiment, a pachislot equipped with a bonus operation function, an AT function, and an ART function will be described.

<Function flow>
First, referring to FIG. 1, the functional flow of the pachislot machine will be described. In the pachislot machine of the present embodiment, a medal is used as a game medium for playing a game. In addition to the medals, for example, coins, gaming balls, point data or tokens for gaming may be applied as gaming media. Also, game media may be referred to as "game value" or "game value".

  When a player inserts a medal into a pachislot and the start lever is operated, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value to determine an internal winning combination. The internal lottery means is one of various processing means (processing functions) provided in a main control circuit described later. By the determination of the internal winning combination, a combination of symbols permitting display along an effective line (winning determination line) described later is determined in advance. The types of combinations of symbols include those related to "winning" in which a player is given a benefit such as payout of medals, activation of replay (replay), activation of bonus, etc. Those concerned are provided. In the following, the role associated with the payout of medals is referred to as a “small role”, and the role associated with the operation of replay (replay) is referred to as a “replay role”. Further, the role associated with the activation of the bonus (bonus game) is also referred to as a "bonus role". Also, the part that can be won internally (ie, the combination of symbols for which establishment is permitted) may be simply referred to as a "part", and the internal winning combination may be "a winning combination", a "predetermined result", or It may be referred to as "a derivation permissible condition". In addition, the internal lottery means may be referred to as "combination determination means", "presence combination determination means", "pre-determination means", or "derivation permission condition determination means".

  In addition, when the start lever is operated, rotation of the plurality of reels is performed. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is one of various processing means (processing functions) provided in a main control circuit described later. The operation means for performing the start operation is not limited to one having a lever shape like the start lever, and may be any operation means as long as the player can perform the start operation. . Further, the operation means for performing the stop operation is not limited to one having a button shape like the stop button, and may be any operation means as long as the player can perform the stop operation. .

  In the pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec) after the stop button is pressed. In the present embodiment, the number of symbols moving with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. Then, in the present embodiment, when the prescribed period is 190 msec, the maximum number of sliding symbols (maximum sliding symbol number) is determined to be four symbols.

  When an internal winning combination that permits combination display of symbols relating to winning is determined, the reel stop control means normally sets the combination of symbols to the effective line within a prescribed time of 190 msec (for four symbols of symbols). Stop rotation of the reel so that it is displayed as much as possible. Also, the reel stop control means uses the specified time to stop the rotation of the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the effective line. The symbol displayed when the rotation of the reel is stopped may be referred to as "stop display" or "display result". In addition, the fact that the symbol is displayed on the effective line when the rotation of the reel is stopped may be expressed as "derivation of stop display" or "derivation of display result".

  Further, the reel stop control means automatically causes each reel to be stopped automatically even when the player does not perform the stop operation when a predetermined automatic stop time has elapsed after the reel rotates. Stop control may be performed. In this case, since the reel is stopped without the player's stop operation, the combination of symbols relating to any winning is effective even when any internal winning combination is determined. It is desirable to stop the rotation of the reel so that it is not displayed along the line.

  In this manner, when the rotations of the plurality of reels are all stopped, the winning combination determining means determines that the combination of symbols displayed along the activated line is related to winning (or other predetermined ones). It is determined whether there is any. That is, it is determined whether a combination of symbols relating to winning (or a combination of other predetermined symbols) is established. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. And, the combination of the displayed symbols is the one (or other predetermined one) related to the prize by the prize determination means (that is, the combination of the symbols pertaining to the prize (or the combination of the other predetermined figures) If it is determined that the player is awarded, a benefit such as the payout of medals is given to the player, or various controls are performed with it. In the pachislot, a series of such flows as described above are performed as one game (unit game).

  In addition, the prize determination means determines whether or not the combination of the symbols displayed along the effective line corresponds to any one of the combinations of a plurality of predetermined symbols. It may be determined whether or not it corresponds to a combination of symbols relating to the internal winning combination determined by the internal lottery means. That is, in the former, it may be determined separately from the internal winning combination whether or not it is a combination of symbols relating to winning. In this case, as long as the stop control is appropriately performed by the reel stop control unit, the prevention of the occurrence of the erroneous winning can be sufficiently secured, so that it is possible to reduce the control load related to the erroneous winning detection. On the other hand, in the latter case, it is also possible to determine whether or not the combination of symbols relating to winning is the combination of symbols for which winning is permitted, so that in the case where erroneous winning occurs due to a defect in the reel, etc. Can be detected, which makes it possible to improve security.

  Moreover, in the pachislot, various effects are displayed using the display of an image by a display device, the output of light by various lamps, the output of sound by a speaker, or a combination of these in the flow of the series of game operations described above. Is done.

  Specifically, when the start lever is operated, random numbers for presentation are extracted separately from the random numbers used to determine the internal winning combination described above. When the random number value for effect is extracted, the effect content determination means randomly determines the effect to be executed this time out of a plurality of types of effect content associated with the internal winning combination. The effect content determination means is one of various processing means (processing functions) included in the sub control circuit described later. In addition, when the main control circuit described later determines the contents of the effect, the effect content determining means may be one of various processing means (processing functions) included in the main control circuit described later.

  Next, when the effect content is determined by the effect content determining means, the effect executing means responds to each trigger at the start of rotation of the reel, at the time of rotation stop of each reel, at the time of determination of presence or absence of winning, etc. Run. Thus, in pachislot, for example, the opportunity to know or predict the determined internal winning combination (in other words, the combination of the symbols to be aimed at) is played by executing the presentation content corresponding to the internal winning combination. Provided to the player, and the player's interest can be improved.

<Structure of Pachislot>
Next, with reference to FIGS. 2 to 5, the structure of a pachi slot according to an embodiment of the present invention will be described.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi slot 1.

  The pachi slot 1 includes an exterior body (game machine main body) 2 as shown in FIG. The exterior body 2 has a cabinet (chassis) 2a for housing a reel, a circuit board and the like, and a front door (front door) 2b attached so as to be able to open and close the opening of the cabinet 2a.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variation display means, display rows) are arranged in a row. Hereinafter, the respective reels 3L, 3C, 3R (main reels) are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each of the reels 3L, 3C, 3R has a cylindrical reel body and a translucent sheet material mounted on the peripheral surface of the reel body. Then, on the surface of the sheet material, a plurality of (for example, twenty) symbols are drawn at predetermined intervals along the circumferential direction (rotational direction of the reel). The respective reels 3L, 3C, 3R may be expressed as "symbol display means", "variable display means", or "variable display". Moreover, the symbol display area 4 mentioned later may be included as these components. In addition, “pattern” may be information that can be identified by the player visually, and in that sense, it may be expressed as “identification information” or the like.

  The front door 2 b includes a door body 9, a front panel 10, a lumbar panel 12, and a pedestal 13. The door body 9 is attached to the cabinet 2a so as to be able to open and close using a hinge (not shown). The hinge is provided at the left side end of the door body 9 as viewed from the front side (player side) of the pachi slot 1. The cabinet 2a can be simply referred to as a "box", and the front door 2b can be simply referred to as a "door" or a "front door". Moreover, since the cabinet 2a functions as a frame which supports or fixes the front door 2b, it may be expressed as a "support body", a "support frame", or a "fixed frame". The front door 2b may be configured by a plurality of door members. For example, an upper door member attached to the upper side of the opening of the cabinet 2a and a lower door member attached to the lower side of the opening of the cabinet 2a may be used. The inner door member may be attached to the opening side of the cabinet 2a, and the outer door member may be attached to the front side of the gaming machine.

  The front panel 10 is provided on the top of the door body 9. The front panel 10 is formed of a frame-like member having an opening 10a. The opening 10a of the front panel 10 is closed by a display cover 30, and the display cover 30 is disposed to face a display 11 described later disposed inside the cabinet 2a.

  The display cover 30 is formed of a black translucent synthetic resin. Therefore, the player can visually recognize an image (image) displayed by the display device 11 described later via the display device cover 30. Further, in the present embodiment, by forming the display device cover 30 with a black semitransparent synthetic resin, the entry of external light into the cabinet 2a is suppressed, and an image (image) displayed by the display device 11 is obtained. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21 a and 21 b provided on the top of the front panel 10 as viewed from the player side. Each of the lamps constituting the lamp group 21 is constituted by an LED (Light Emitting Diode) or the like (see the LED group 85 in FIG. 6 described later), and turns on and off the light in a pattern corresponding to the contents of the effect.

  The waist panel 12 is provided substantially at the center of the door body 9. The waist panel 12 has a decorative panel on which an arbitrary image is drawn, and a light source (an LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal 13 is provided between the front panel 10 and the waist panel 12. The pedestal portion 13 includes a symbol display area 4 and various devices to be operated by the player (the medal insertion slot 14, the MAX bet button 15a, the 1 bet button 15b, the start lever 16, three stop buttons 17L, 17C, 17R, a settlement button (not shown), etc. are provided.

  The symbol display area 4 is an area overlapping the three reels 3L, 3C, 3R when viewed from the front, and is disposed at a position closer to the player than the three reels 3L, 3C, 3R. It has a size that makes 3L, 3C, 3R visible. The symbol display area 4 functions as a display window, and is configured to be able to visually recognize the respective reels 3L, 3C, 3R provided behind it. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  The reel display window 4 is, when the rotation of the three reels 3L, 3C, 3R provided behind it is stopped, 3 of the plurality of symbols provided on the circumferential surface of each reel, continuously arranged 3 One symbol is configured to be displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, in the frame of the reel display window 4, one symbol (three in total) in each of the upper, middle and lower areas for each reel Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). And in this embodiment, in the frame of the reel display window 4, whether the line (cross-up line) connecting the lower stage area of the left reel 3L, the middle stage area of the middle reel 3C, and the upper stage area of the right reel 3R is won It defines as an effective line which judges whether it is not.

  In the present embodiment, other lines, for example, a line connecting the upper stage area of the left reel 3L, an upper stage area of the middle reel 3C, and an upper stage area of the right reel 3R (top line), a middle stage area of the left reel 3L, A line connecting the middle stage area of the middle reel 3C and the middle stage area of the right reel 3R (center line), a lower stage area of the left reel 3L, a lower stage area of the middle reel 3C, and a lower stage area of the right reel 3R (bottom Even if any of the lines connecting the upper line area of the left reel 3L, the middle line area of the middle reel 3C, and the lower line area of the right reel 3R (crossdown line) is defined as an effective line Good. Also, among the above-mentioned lines including the cross-up lines, a plurality of lines may be defined as effective lines.

  The reel display window 4 is formed by the opening of the frame member 31 provided on the pedestal portion 13. Further, under the frame member 31 defining the reel display window 4, a pedestal region of a substantially horizontal surface is provided. When viewed from the player side, the medal insertion slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1 bet button 15b are provided on the left side.

  The medal insertion slot 14 is provided to receive a medal dropped from the outside into the pachislot 1 by the player. The medals received from the medal insertion slot 14 are used for one game with a predetermined number (for example, 3) set in advance as the upper limit, and the number of medals exceeding the predetermined number is deposited inside the pachislot 1 (So-called credit function (game media storage means)).

  The MAX bet button 15a and the 1 bet button 15b are provided to determine the number of medals to be used for one game from the medals deposited inside the cabinet 2a. In addition, inside the MAX bet button 15a, a bet button LED (not shown) is provided which lights up when medals can be inserted. Further, the settlement button is provided to pull out (discharge) the medal deposited inside the pachislot 1.

  When the player presses the MAX bet button 15a, medals of the bet number (3 pieces) of the unit game are inserted, and the activated line is activated. On the other hand, one medal is inserted each time the 1-bet button 15 b is pressed once. When the 1-bet button 15b is operated three times, medals of the bet number (3 pieces) of the unit game are inserted, and the activated line is activated.

  Hereinafter, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting medals into the medal insertion slot 14 (operation of inserting medals to play a game) are all referred to as "insertion operations".

  The start lever 16 is provided to start the rotation of all the reels (3L, 3C, 3R). The stop buttons 17L, 17C, 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as the left stop button 17L, the middle stop button 17C, and the right stop button 17R, respectively.

  Further, an information display 6 is provided substantially at the center of the pedestal area of the substantially horizontal surface below the reel display window 4. The information display 6 is covered by a transparent window cover (not shown).

  A two-digit seven-segment LED for digitally displaying (notifying) the player with information on the number of medals (hereinafter referred to as “the number of payouts”) to be paid out to the player as a benefit on the information display 6 Information for the player (hereinafter referred to as “7-segment LED”) and the number of medals deposited inside the pachislot 1 (hereinafter referred to as “number of credits”) is digitally displayed (notified) to the player A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) information on occurrence of errors and error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the payout number of medals switches from the display mode of the payout number to the display mode of the information of the error type.

  In addition, the information display 6 is provided with an instruction monitor (not shown) for notifying information on stop operation necessary to display the symbol combination according to the combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction indicator) is formed of, for example, a 2-digit 7-segment LED. Then, in the instruction monitor, the two-digit 7-segment LED is turned on, blinks, or is extinguished in a mode uniquely corresponding to the information on the stop operation to notify, thereby notifying the player of the information on the necessary stop operation. Do.

  In this case, the information corresponding to the information on the stop operation to be notified uniquely corresponds to, for example, the case where the push order “1st (performing the first stop operation to the left reel 3L)” is notified. When displaying the numerical value “1” on the instruction monitor and notifying the pushing order “2nd (performing the first stop operation to the middle reel 3C)”, the numerical value “2” is displayed on the instruction monitor, and the pushing order In the case of informing "3rd (performing the first stop operation to the right reel 3R)", it is an aspect such as displaying the numerical value "3" on the instruction monitor. Note that the notification mode (navidata determined by the main side described later) of the stop operation in the instruction monitor will be described later in detail with reference to FIGS. 23 and 24 described later.

  Further, the information display 6 is provided with a status display (not shown) for notifying that it is an advantageous section (see FIG. 14 described later) which is advantageous for the player. The status indicator is constituted of, for example, 7-segment LEDs. In principle, the status indicator lights up at a predetermined timing during the game (for example, any timing from the start of the game to the end of the game) determined to shift to the advantageous section, and the advantageous section continues. While it is on, its lighting continues. When the advantageous section ends, the lighting ends and the light turns off. In this way, it is possible to ensure the fairness of the game, as it is notified to all players that an advantageous section advantageous to the player is started, being in the advantageous section, and that the advantageous section is ended. .

  The information display 6 is electrically connected to the main control board 71 via the door relay terminal board 68 and the game operation display board 81 as shown in FIG. 6 described later, and the display operation of the information display 6 is mainly It is controlled by the below-mentioned main control circuit 90 in the control board 71. Moreover, the control system of various 7 segment LED mentioned above is dynamic lighting control.

  In addition to the instruction monitor controlled by the main control board 71, the pachi slot 1 of the present embodiment is provided with a configuration for notifying information on the stop operation using other means controlled by the sub control board 72. Specifically, information on the stop operation is notified by a display device 11 described later that is configured by a projector mechanism 211 described later and a display unit 212 (see FIG. 3 and FIG. 6 described later).

  When such a configuration is applied, the mode of notification in the instruction monitor and the mode of notification in the other means controlled by the sub control board 72 may be different from each other. That is, in the instruction monitor, notification may be made in a mode uniquely corresponding to the information of the stop operation to be notified, and it is not necessary to directly notify the information of the stop operation (for example, the numerical value "1" in the instruction monitor Even if is displayed, some players may not be able to specify the notification content, which is not a direct notification). On the other hand, in the notification on the sub side (sub control substrate side) by other means such as the display device 11 described later, the information on the stop operation may be notified directly. For example, when notifying the pushing order "1st", the instruction monitor displays the numerical value "1" that uniquely corresponds to the pushing order notified, but the other means (for example, the display device 11 etc.), the left reel 3L Alternatively, instruction information for causing the first stop operation to be issued may be notified directly.

  In the pachi slot 1 having such a configuration, not only the control of the sub control board 72 but also the control of the main control board 71 can notify the information of the necessary stop operation according to the internal winning combination. Moreover, the presence or absence of notification of such stop operation information can be controlled in accordance with the gaming state. For example, in the normal gaming state (normal section) described later, the information on the stopping operation can be notified in the ART gaming state (advantage section), not informing the information on the stopping operation.

  Also, a sub display 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand vertically from the pedestal region of the substantially horizontal surface of the pedestal portion 13 in the front surface portion of the door main body 9. The sub display device 18 is configured by a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various information.

  Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 6 described later). The touch sensor 19 operates according to a predetermined operation principle such as a capacitance method, and outputs a signal corresponding to the operation as touch input information when the operation of the player is received. And, the pachislot 1 of the present embodiment has a function of making it possible to switch the display of the sub display device 18 according to the operation of the player received via the touch sensor 19 (touch input information output from the touch sensor 19). Have. The sub display device 18 is controlled by a sub control board 72 (see FIG. 6 described later) based on touch input information output from the touch sensor 19.

  In the lower part of the door main body 9, a medal payout port 24, a medal receiving tray 25, two speaker holes 20L, 20R and the like are provided. The medal payout opening 24 guides a medal discharged by the driving of a hopper device 51 (a medal payout device) described later to the outside. The medal receiver 25 stores the medals discharged from the medal payout opening 24. Further, from the two speaker holes 20L and 20R, sounds such as sound effects and music corresponding to the contents of the effect are output.

[Internal structure]
Next, the internal structure of the pachi slot 1 will be described with reference to FIGS. 3 is a view showing the internal structure of the cabinet 2a, FIG. 4 is a view showing the internal structure of the back side of the front door 2b, and FIG. 5 is a view described later provided on the back side of the front door 2b. It is a figure which shows the structure of the selector 66. FIG.

  As shown in FIG. 3, the cabinet 2a has a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. And the display apparatus 11 is arrange | positioned by the upper part in the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection target member 212 a onto which the image light projected from the projector mechanism 211 is projected, and performs image display by projection mapping. Specifically, in the display device 11, video light is generated based on the position (projection distance, angle, etc.) and shape of the projection target member 212a to be a three-dimensional object, and the video light is projected by the projector mechanism 211. It is projected on the surface of 212a. By providing such a rendering function, sophisticated and powerful rendering can be performed. Further, although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and either projected member is provided depending on the gaming state. , It is used as a screen on which image light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the projection target members in accordance with the game state. Note that the display device 11 may use various other display devices (for example, liquid crystal display devices) as long as the device can display an image for the player.

  A medal payout device (hereinafter, referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply 53 are disposed at a lower portion in the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large amount of medals and discharging them one by one. The hopper device 51 pays out the medals, for example, when the stored medals exceed 50, or when the settlement button is pressed and the settlement of the medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout opening 24 (see FIG. 2).

  The medal auxiliary storage 52 stores the medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. Moreover, the medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 has a power switch 53a and a power supply substrate 53b (power supply means) (see FIG. 6 described later). The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the power of the AC voltage 100 V supplied from the sub power supply device (not shown) into the power of the DC voltage required by each part, and supplies the converted power to each part.

  Further, above the power supply device 53 in the cabinet 2a, a sub control board case 57 for accommodating a sub control board 72 (see FIG. 6 described later) is disposed. A sub control circuit 200 described later (see FIG. 9 described later) is mounted on the sub control substrate 72 housed in the sub control substrate case 57. The sub control circuit 200 is a circuit that controls execution of effects by displaying a video or the like. The specific configuration of the sub control circuit 200 will be described later.

  The sub relay board 61 is disposed above the sub control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which a wire connecting the sub control board 72 and a main control board 71 described later is mounted. Further, the sub relay board 61 is a relay board on which a wire for connecting the sub control board 72 and a board provided around the sub control board 72, various device units (units), and the like is mounted.

  Although not shown in FIG. 3, a cabinet side relay board 44 (see FIG. 6 described later) is disposed in the cabinet 2a. The cabinet side relay board 44 includes a main control board 71 (see FIG. 6 described later), a hopper device 51, a medal auxiliary storage switch 75 (see FIG. 6 described later), and a medal payout count switch (not shown). Is a relay board on which a wire for connecting is mounted.

  As shown in FIG. 4, a middle door 41 is disposed at the center on the back side of the front door 2b, and the reel display window 4 (see FIG. 2) is attached so as to be able to be opened and closed from the back. Although not shown in FIG. 4, three reels 3L, 3C, 3R are attached to the reel display window 4 side of the middle door 41, and the main control is performed on the side opposite to the reel display window 4 side of the middle door 41. A main control board case 55 in which a board 71 (see FIG. 6 described later) is accommodated is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, 3R via a gear having a predetermined speed reduction ratio.

  The main control board 71 housed in the main control board case 55 has a main control circuit 90 (see FIGS. 7 and 8 described later) described later. The main control circuit 90 (main control means) is a circuit for controlling the main flow of the game in the pachislot 1 such as determination of the internal winning combination, rotation and stop of each reel 3L, 3C, 3R, and determination of presence or absence of winning. . Further, in the present embodiment, the main control circuit 90 also controls, for example, processing related to determination regarding AT or ART, processing of displaying navigation information on an instruction monitor, processing of transmitting various test signals, and the like. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back side of the front door 2b. The speakers 65L and 65R are disposed at positions facing the speaker holes 20L and 20R (see FIG. 2).

  Further, a selector 66 and a door open / close monitoring switch 67 are disposed above the speaker 65L. The selector 66 is a device for detecting medals inserted into the medal insertion slot 14 and is a device for selecting whether or not the inserted medals are appropriate medals, and is classified as appropriate medals In this case, the medal is guided to the hopper device 51 side and driven so as to be accommodated in the hopper device 51, and when it is determined that the medal is not a proper medal, the medal is moved to the medal payout port 24 side. And driven so as to be discharged from the medal payout opening 24. That is, the selector 66 is also a device for distributing the medals inserted into the medal insertion slot 14 to the hopper device 51 side or the medal payout port 24 side.

  As shown in FIG. 5, the selector 66 has a base 803 provided with a medal rail (medal passage) 802 through which the medal passes, and a select plate for guiding the inserted medal to the hopper device 51 side or the medal payout port 24 side. 804, a medal pusher 805 for pushing the medal to the medal payout opening 24 side when the inserted medal is not a proper medal, an upstream medal sensor for detecting the inserted medal on the upstream side of the medal rail 802 (first A medal sensor) 806 and a downstream medal sensor (second medal sensor) 807 for detecting the inserted medal on the downstream side of the medal rail 802.

  Further, although not shown in FIG. 5, the selector 66 has a medal guide (that forms a flow path of medals from the selector 66 to the hopper device 51 when the medals are guided to the hopper device 51 by the select plate 804) (Not shown) and a cancel chute (not shown) for forming a flow path of the medal from the selector 66 to the medal payout opening 24 when the medal is placed on the medal payout opening 24 side by the select plate 804 is detachable It is attached.

  The select plate 804 is driven by a solenoid (not shown) included in the selector 66. The select plate 804 moves the guiding medal to a guiding position for guiding the passing medal to the hopper device 51 side when the solenoid is driving, but does not guide the passing medal to the hopper device 51 side when the solenoid is not driving. It moves to the discharge position (that is, it guides to the medal payout opening 24 side). Specifically, when the solenoid is driven, the select plate 804 moves toward the rear side of the pachi slot 1 to guide the upper side of the medal, while when the solenoid is not driven, the select plate 804 is pochi slot 1 It moves in the forward direction so as not to guide the upper side of the medal. In addition, the guide method of the medal | token by the select plate 804 is not restricted to this, For example, the movement of a guide position and a discharge position is enabled by setting it as the mechanism which can move to the up-down direction of pachislot 1 May be That is, the select plate 804 is moved by the solenoid or other drive source to a guide position on the medal rail 802 that does not prevent the passing medal from moving to the hopper device 51 side, and the passing medal to the hopper device 51 side Any mechanism can be adopted as long as it is a mechanism that is capable of shifting between the discharge position where it is guided to the medal payout opening 24 side and the movement thereof is prevented.

  For example, when the select plate 804 is moved to the guide position, the medal pusher 805 operates so as not to protrude in the rear direction of the pachi slot 1 and the select plate 804 is not moved to the guide position In the case of moving to the rear side of the pachi slot 1). That is, when the medal pusher 805 is at a position where it does not protrude in the rear side direction of the pachi slot 1, it becomes a guide position for guiding the passing medal to the hopper device 51 side, and when in a position where it protrudes in the rear side direction of the pachi slot 1. The passing medal is not guided to the side of the hopper device 51 (i.e., guided to the side of the medal payout opening 24), which is a discharge position.

  The upstream medal sensor 806 and the downstream medal sensor 807 constitute gaming medium detection means for detecting that the medal has passed. Each medal sensor is, for example, a reflection type sensor including a pair or a plurality of pairs of light emitting elements and light receiving elements, and the light emitting elements emit light to the medals and reflected light reflected from the medals When the light receiving element receives light, passage of the medal is detected. The configuration of the sensor can be changed as appropriate, and, for example, a transmission sensor or the like can be employed. Further, the passage of the medal may be detected only by the downstream side medal sensor 807 without providing the upstream side medal sensor 806. Moreover, the specific control based on the detection result (the medal sensor input state) of each medal sensor will be described later.

  The door open / close monitoring switch 67 is disposed obliquely downward to the left of the selector 66 when the front door 2 b is viewed from the back side. The door opening and closing monitoring switch 67 outputs a security signal for notifying the opening and closing of the front door 2 b to the outside of the pachi slot 1.

  Further, although not shown in FIG. 4, a door relay terminal plate 68 is disposed on the back of the front door 2b at the back side and in the area opened and closed by the middle door 41 and below the reel display window 4 (see FIG. 6). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a test machine, and the like. It is a relay board on which the wiring which connects with each of the second interface board 302 for a tester is mounted. Examples of the various buttons and switches include a MAX bet button 15a, a 1 bet button 15b, a door open / close monitoring switch 67, a bet switch 77 described later, and a start switch 79.

<Control system equipped with Pachislot>
Next, a control system included in the pachi slot 1 will be described with reference to FIG. FIG. 6 is a circuit block diagram showing a configuration of a control system of pachi-slot 1.

  The pachi slot 1 has a main control board 71 provided on the middle door 41 and a sub control board 72 provided on the front door 2b. The pachi slot 1 also has a reel relay terminal board 74, a setting key type switch 54 (setting switch) and a cabinet side relay board 44 connected to the main control board 71. Furthermore, the pachi slot 1 has an external concentrated terminal board 47 connected to the main control board 71 via the cabinet side relay board 44, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76 and a power supply device 53. In addition, since it mentioned above about the structure of the hopper apparatus 51, the description is abbreviate | omitted here.

  The reel relay terminal board 74 is disposed inside the reel body of each of the reels 3L, 3C, 3R. The reel relay terminal board 74 is electrically connected to stepping motors (not shown) of the respective reels 3L, 3C, 3R, and relays signals outputted from the main control board 71 to the stepping motors.

  The setting key type switch 54 is provided on the main control board case 55. The setting key type switch 54 is used when changing the setting value (setting 1 to setting 6) of the pachislot 1 or confirming the setting of the pachislot 1. The setting value indicates the degree of advantage of the player regarding the game, and generally, the lower the setting value (for example, the closer to setting 1), the relatively lower the degree of advantage of the player. The higher the setting value (eg, the closer to setting 6), the higher the degree of advantage of the player. In the present embodiment, the higher the set value, the higher the probability of winning the bonus combination described later, and the degree of advantage of the player can be varied. The higher the set value, the more AT and ART described later. It is also possible to change the degree of advantage of the player by increasing the probability of winning such a lottery.

  The cabinet side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external concentrated terminal plate 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. It is. The external concentrated terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachi-slot 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52, and detects whether the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachi slot 1.

  The power supply device 53 includes a power supply substrate 53 b and a power switch 53 a connected to the power supply substrate 53 b. The power switch 53 a is pressed to supply the necessary power to the pachi slot 1. The power supply substrate 53 b is connected to the main control substrate 71 via the cabinet side relay substrate 44, and is also connected to the sub control substrate 72 via the sub relay substrate 61.

  The pachi slot 1 is connected to the main control board 71 via the door relay terminal board 68 and the door relay terminal board 68, the selector 66, the door open / close monitoring switch 67, the BET switch 77, the settlement switch 78, It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub relay board 61, a first interface board for testing machine 301, and a second interface board for testing machine 302. Since the selector 66, the door open / close monitoring switch 67, and the sub relay board 61 have been described above, the description thereof is omitted here.

  The BET switch 77 (input operation detection means) detects that the MAX bet button 15a or the 1 bet button 15b has been pressed by the player. The settlement switch 78 detects that the settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detection means) detects that the player has operated the start lever 16 (start operation).

  The stop switch substrate 80 (stop operation detection means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stopable main reel by an LED or the like. In addition, the stop switch substrate 80 is provided with a stop switch (not shown). The stop switch detects that each stop button 17L, 17C, 17R has been pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. For example, three LEDs for displaying the number of inserted medals (hereinafter referred to as “first LED” to “the first LED”) are lighted corresponding to the number of medals inserted in the current game (hereinafter referred to as “inserted number”). Based on the signal input from the game operation display board 81), a mark indicating that the medal can be inserted, a mark indicating the start of the game, an LED to light the mark for performing the replay, etc. And so on. In the first to third LEDs (display means), when one medal is inserted, the first LED is turned on, and when two medals are inserted, the first and second LEDs are turned on, and three medals (game When the startable number of cards is inserted, the first to third LEDs light up. In addition, about the information display 6, since it mentioned above, those description is abbreviate | omitted.

  Both the first interface board for testing machine 301 and the second interface board for testing machine 302 are relay boards used when outputting various signals relating to the game to the testing machine in the verification test (test shooting test) of the pachislot 1 ( Since these relay boards are not mounted on the pachislot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for testing machine and the testing machine. The various electronic components required to connect to the second interface board 302 are also not mounted). For example, a test signal for controlling a main operation related to a game (for example, internal lottery, reel stop control, etc.) is output through the first interface board 301 for a test machine, and is determined by the main control board 71, for example. A test signal or the like relating to the push order navigation performed is output via the second interface board 302 for a tester.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. The pachi slot 1 also has a speaker group 84, an LED group 85, a 24 h door open / close monitoring unit 63, a touch sensor 19, and a display unit 212 connected to the sub control board 72 via the sub relay board 61. In addition, since the touch sensor 19 has been described above, the description thereof is omitted here.

  The speaker group 84 is configured to include the speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source for emitting light for illuminating the decorative panel of the waist panel 12 from the back side, and the like. The 24 h door opening and closing monitoring unit 63 stores history information of the opening and closing of the middle door 41. Further, when the middle door 41 is opened, the 24 h door opening / closing monitoring unit 63 outputs a signal for performing an error display by the display device 11 to the sub control board 72 (sub control circuit 200). The display unit 212 includes, for example, a projection target member 212a constituting the display device 11, and another projection target member having a curved display surface provided on the back side of the projection target member 212a.

  The pachi slot 1 also includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub control substrate 72. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are accommodated in the sub control substrate case 57 together with the sub control substrate 72.

  The ROM cartridge substrate 86 is a substrate for managing various control programs to be executed by the sub CPU 201, and images (videos) for presentation, audio (speaker group 84), light (LED group 85), and communication data. . The liquid crystal relay substrate 87 is a substrate that relays connection wiring between the sub control substrate 72, the projector mechanism 211 that constitutes the display device 11, and the sub display device 18. The projector mechanism 211 and the sub display device 18 have been described above, and thus the description thereof is omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 7 is a block diagram showing a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 functions as a game control unit for controlling the game operation, and the microprocessor 91, the clock pulse generation circuit 92, the power management circuit 93, the switching regulator 94 (power supply means), and the duty ratio monitor ( Not shown).

  The microprocessor 91 is a microprocessor with a security function for a gaming machine. In the microprocessor 91 of the present embodiment, various instruction codes (hereinafter referred to as "main CPU 101 dedicated instruction code") specific to the microprocessor 91 that can be defined on a program are provided. In the present embodiment, by using the main CPU 101 dedicated instruction code, processing efficiency, program capacity reduction, and the like are realized. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 8 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by the main control circuit described later. Do.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

  The power supply management circuit 93 manages fluctuations in the power supply voltage of DC 12 V supplied from the power supply substrate 53b (see FIG. 6). Then, the power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the start voltage value (10 V) from 0 V). When a power failure occurs (when the power supply voltage falls from 12 V to a power failure voltage value (10.5 V)), a power failure detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (start signal) to the microprocessor 91 when the power is turned on (starting means), and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as means for outputting (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of 5 V DC) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

  The duty ratio monitor (not shown) is, for example, a 4-digit 7-segment LED, and an arithmetic circuit 107 described later performs a predetermined ratio calculation on an aggregation result on gaming information aggregated by the main CPU 101 described later. , The result of the ratio calculation is displayed as ratio information. In the present embodiment, a plurality of types of ratio calculations are performed, and the combination ratio monitor sequentially displays a plurality of types of ratio information based on the result.

  In the upper two digits of the ratio monitor, “abbreviated”, which is type information indicating the type of the ratio information, is displayed, and in the lower two digits, “ratio”, which is ratio information corresponding to the type information, is displayed. It is supposed to be displayed. For example, when “7” is displayed in the first digit (digit 10) of the duty ratio monitor and “U” is displayed in the second digit (digit 1) (ie, abbreviation “7 U” ), The lower 2 digits of the parting ratio monitor, as ratio information, the ART function is activated during a predetermined total number of games (175,000 times) (ie stop operation advantageous to the player) The ratio of the number of games (of advantageous intervals) of the advantageous intervals for which the procedure of has been informed is displayed. Specifically, when the effective interval ratio is 10%, "1" is displayed in the third digit (the digit of the ratio 10), and "0" is displayed in the fourth digit (the digit of the ratio 1). Is displayed. The advantageous section ratio may display a ratio of the number of games in which the AT function and the ART function are activated.

  Also, for example, when “6” is displayed in the first digit (position 10) of the duty ratio monitor and “Y” is displayed in the second digit (position 1) (ie, the abbreviation “ 6Y ”is displayed, the lower 2 digits of the role ratio monitor, as ratio information, a continuous feature accounted for the number of payouts of gaming media paid out between a specific total number of games (6000 times) Actuating device (in this embodiment, BB, including a character continuous actuating device (MB) operated by a type II special character (CB) continuously, including it. The same applies hereinafter) The ratio of the number of game media paid out by being operated and paid out (medium-time continuous playing ratio) is displayed. Specifically, when the middle-time consecutive-income ratio is 59%, "5" is displayed in the third digit (digit of ratio 10), and "9" is displayed in the fourth digit (digit of ratio 1). "Is displayed.

  Also, for example, when “7” is displayed in the first digit (position 10) of the duty ratio monitor and “Y” is displayed in the second digit (position 1) (ie, the abbreviation “ 7Y ”is displayed in the lower two digits of the parting ratio monitor as ratio information, all the players occupying the number of payouts of gaming media paid out among a specific total number of games (6000 times) Objects (BB in this embodiment. In addition to the above-described MB, when the above-mentioned type-I special character (RB) alone is loaded, the above-mentioned second-type special character (CB) is alone If it is loaded, and if it is loaded on a regular combination (SB), it includes all of them. The same shall apply hereinafter. Ratio of the number of payouts of gaming media paid out Is displayed. Specifically, when the middle-time character ratio is 59%, "5" is displayed in the third digit (the ratio 10), and "9" is displayed in the fourth digit (the ratio 1). "Is displayed.

  Also, for example, when “6” is displayed in the first digit (digit 10) of the duty ratio monitor and “A” is displayed in the second digit (digit 1) (ie, abbreviated “ 6A ”is displayed in the lower 2 digits of the parting ratio monitor, as a ratio information, a bonus continuous in the payout number of gaming media paid out among a predetermined total number of games (175,000 times) The ratio of the number of payouts of the gaming media paid out by activating the actuating device (total interlocking ratio) is displayed. Specifically, when the total interlocking ratio is 25%, "2" is displayed in the third digit (the digit of the ratio 10), and "5" is displayed in the fourth digit (the symbol of the ratio 1). Is displayed.

  Also, for example, when “7” is displayed in the first digit (position 10) of the duty ratio monitor and “A” is displayed in the second digit (position 1) (ie, the abbreviation “ 7A ”is displayed in the lower two digits of the combination ratio monitor as ratio information, all the combinations of the game media paid out among the predetermined total number of games (175,000 times), all the combinations The ratio of the number of payouts of the game media paid out by activating the thing (total role ratio) is displayed. Specifically, when the gross character product ratio is 25%, "2" is displayed in the third digit (digit of ratio 10), and "5" in the fourth digit (digit of ratio 1). Is displayed.

  In the present embodiment, the main control circuit 90 directly describes the configuration in which the ratio monitor is taken as an example, but the display ratio of the ratio monitor is controlled by the main control circuit 90, and If it is necessary (for example, when the main control board case 55 is viewed) to recognize the display contents, it may be sufficient to adopt a configuration in which the main control circuit 90 is not directly provided. For example, the duty ratio monitor may be connected to the game operation display substrate 81, and the main control circuit 90 may control the display content via the game operation display substrate 81. In this case, the duty ratio monitor is also used as the information display 6, the LED 82, or the instruction monitor (instruction indicator), and one or more of them are used to display predetermined ratio information. You may do so.

  Further, in the present embodiment, as the predetermined ratio information displayed on the combination ratio monitor, an advantageous segment ratio, a medium time combination ratio, a medium time combination ratio, a total combination ratio, and a total combination ratio are exemplified as an example. Although described, other ratio information may be displayed. For example, the ratio of the number of payouts of gaming media paid out by the ART function to the number of payouts of gaming media paid out during a predetermined total number of games (175,000 times) (total advantageous section acquisition ratio) The ratio of the number of payouts of gaming media paid out by the ART function to the number of payouts of gaming media paid out during a specific total number of games (6000 times) (medium-time advantageous period acquisition ratio) The ratio of the number of games activated by the bonus continuous operation device (mid-time interlocking segment ratio) occupied during the specific total number of games (6000 times), occupied during the specific total number of games (6000 times), The ratio of the number of games in which all the items have been activated (mid-time character section ratio), the ratio of the number of games in which the continuous product operating device has been activated among the predetermined total number of games (175,000 times) Ratio), during a predetermined total number of games (175,000 times) Occupy all the character object is ratio of the number of game that activated (total character object section ratio) and the like can also be displayed by performing a predetermined ratio calculation.

  Further, in the present embodiment, the predetermined total game number is "175000 times" and the specific total game number is "6000 times", as the number (denominator) of the predetermined ratio information displayed on the winning ratio monitor. However, the predetermined total number of games and the specific total number of games are not limited thereto. For example, a predetermined total game number may be "17500 times" and a specific total game number may be "3000 times" as a base number (denominator) for calculating a part or all of the various ratios described above. . However, since various types of gaming machines are installed and operated in gaming arcades, and the number of games optimum for ratio calculation may differ, etc., each game number for calculating the various ratios described above is It is not limited to the above and can be changed as appropriate. In this case, among the various ratios, it is possible to arbitrarily set the number of games that can be the base number (denominator) and the number of children (numerator) for calculating a part or all of the various ratios on the game arcade side. Good.

  Also, in the present embodiment, although all features targeted by the medium-time feature ratio and the overall feature ratio do not include the ART function operation, the ART function operation It is also possible to calculate the ratio of the medium-time role ratio and the total role ratio as an operation of the Moreover, even if it is other than what was mentioned above, as long as it is useful information, two values are totaled and ratio calculation is performed, and it goes without saying that the result of the ratio calculation can be displayed as ratio information. Absent.

<Microprocessor>
Next, an internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 8 is a block diagram showing an internal configuration of the microprocessor 91. As shown in FIG.

  The microprocessor 91 includes a main CPU 101 (arithmetic processing unit), a main ROM 102 (first storage unit), a main RAM 103 (second storage unit), an external bus interface 104, a clock circuit 105, and a reset controller 106. The arithmetic circuit 107, the random number circuit 110, the parallel port 111, the interrupt controller 112, the timer circuit 113, the first serial communication circuit 114, and the second serial communication circuit 115 are included. The components constituting the microprocessor 91 are connected to one another via a signal bus 116.

  The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 to perform control related to the entire game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  The main CPU 101 counts the number of times the pulse is output to the stepping motor of each reel 3L, 3C, 3L (main reel) after detecting the reel index. Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many reels the symbol has rotated). The reel index is information indicating that the reel has made one rotation. The reel index includes, for example, an optical sensor having a light emitting portion and a light receiving portion, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting portion and the light receiving portion by rotation of each main reel. It is detected by the provided reel position detection unit (not shown).

  Here, management of the rotation angles of the respective reels 3L, 3C, 3L (main reels) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the pulse counter counts the output of a predetermined number of pulses necessary for the rotation of one symbol, the symbol counter provided in the main RAM 103 is incremented by one. A symbol counter is provided for each reel. The value of the symbol counter is cleared when a reel index is detected by a reel position detection unit (not shown).

  That is, in this embodiment, by managing the symbol counter, it is managed how many symbol rotations have been performed since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control instructions (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by the execution of the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG. 11 described later.

  The external bus interface 104 electrically connects the microprocessor 91 to an external signal bus (not shown) to which various components (for example, respective reels and the like) provided outside the microprocessor 91 are connected. It is an interface circuit. The clock circuit 105 includes, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is divided into other components (for example, timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or a WDT (watchdog timer) based on a reset signal input from the power management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when executing a "MUL (multiplication)" instruction on a program, the arithmetic circuit 107 executes multiplication processing based on this "MUL" instruction.

  The random number circuit 110 generates a random number (for example, 0 to 65535 or 0 to 255) within a predetermined range. Although not shown, the random number circuit 110 obtains a 1-byte soft latch random number, a random number register 0 for obtaining a 2-byte hard latch random number, a random number register 1 for obtaining a 2-byte soft latch random number, and The random number registers 2 to 7 of FIG. The main CPU 101 extracts one value from the random numbers in the predetermined range generated by the random number circuit 110 as, for example, a random number value for internal lottery. The parallel port 111 is a port (memory map I / O) of a signal input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93 etc.) provided outside the microprocessor 91. . The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is also connected to any input port of PI0 to PI4 of the parallel port 111, and is latched from the parallel port 111 to the random number register 0 of the random number circuit 110 at the timing (on edge) when the start switch 79 is turned on. A signal is output. Then, in the random number circuit 110, the random number register 0 is latched by inputting the latch signal, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs interrupt processing by the main CPU 101 based on the power failure detection signal input from the power management circuit 93 via the parallel port 111 or the time-out signal input from the timer circuit 113 in a cycle of 1.172 ms. Control the execution timing of When a power failure detection signal is input from the power supply management circuit 93, or when a time-out signal is input from the timer circuit 113, the interrupt controller 112 generates an interrupt request signal indicating an interrupt processing start command as the main CPU 101. Output to The main CPU 101 performs input port check processing, reel control processing, communication data transmission processing, 7 segment LED driving processing, timer based on an interrupt request signal input from the interrupt controller 112 in response to a time out signal from the timer circuit 113. Various interrupt processing such as update processing (see FIG. 92 described later) is performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal (clock pulse signal of a frequency obtained by dividing the clock pulse signal for operating the main CPU by a divider (not shown)) generated by the clock circuit 105 (a clock pulse signal). Count elapsed time). Then, the timer circuit 113 outputs a time-out signal (trigger signal) to the interrupt controller 112 in a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when transmitting data (various control commands (commands)) from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls the serial transmission operation when transmitting data from the main control board 71 to the second interface board 302 for a tester.

<Sub control circuit>
Next, with reference to FIG. 9, the configuration of the sub control circuit 200 (sub control means) mounted on the sub control substrate 72 will be described. FIG. 9 is a block diagram showing a configuration example of the sub control circuit 200 of the pachislot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of effects based on commands transmitted from the main control circuit 90. The sub control circuit 200 functions as an effect control unit that controls an effect operation, and basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge substrate 86. The driver 205 is connected to the liquid crystal relay substrate 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  The program storage area stores a control program to be executed by the sub CPU 201. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random value for effect are extracted, and effect registration (render data) is determined and registered. It contains various programs for performing tasks. Further, the control program includes a drawing control task for controlling the display of an image by the display device 11 based on the determined effect contents, a lamp control task for controlling light output by a light source such as the LED group 85, and a sound by the speaker group 84. Also included are various programs for executing a voice control task that controls the output of

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data relating to creation of a video. The data storage area also includes a storage area for storing sound data relating to BGM and sound effects, and a storage area for storing lamp data relating to a light on / off pattern.

  The sub RAM 202 is provided with a storage area for registering the determined effect content and presentation data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create an image according to the animation data specified by the effect contents, and the created image is displayed on the display device 11 (projector mechanism 211) Alternatively, it is displayed on the sub display 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM in accordance with the sound data designated by the contents of the effect. Further, the sub CPU 201 controls lighting and extinguishing of the LED group 85 in accordance with the lamp data designated by the contents of the effect.

<Various registers of the main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. FIG. 10 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 includes, as main registers, an accumulator A (hereinafter referred to as "A register"), a flag register F (flag register), a general purpose register B (hereinafter referred to as "B register"), and a general purpose register C (hereinafter referred to C register), general purpose register D (hereinafter referred to as "D register"), general purpose register E (hereinafter referred to as "E register"), general purpose register H (hereinafter referred to as "H register") and general purpose register L (hereinafter referred to , “L register”). The main CPU 101 also includes an accumulator A ′, a flag register F ′, a general purpose register B ′, a general purpose register C ′, a general purpose register D ′, a general purpose register E ′, a general purpose register H ′ and a general purpose register L ′ as sub registers. As a general purpose register. Each register is composed of a 1-byte register.

  Further, in the present embodiment, the B register and the C register are used as a pair register (hereinafter, referred to as "BC register"), and the D register and the E register are used as a pair register (hereinafter, referred to as "DE register"). Furthermore, in the present embodiment, the H register and the L register are used as a pair register (hereinafter referred to as "HL register").

  As shown in FIG. 10, predetermined flag information indicating the result of the arithmetic processing is set in each bit of the flag register F, F '. For example, data (zero flag) indicating whether the operation result is “0” in the determination processing of the operation result is set in bit 6 (D6). Specifically, when the operation result is "0", data "1" is set to bit 6, and when the operation result is not "0", data "0" is set to bit 6. Then, in the determination processing of the calculation result, the main CPU 101 performs determination (YES / NO) with reference to data “0” / “1” of bit 6.

  Further, the main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is configured of a 1-byte register. In the present embodiment, as will be described in the various processing flows to be described later, various main CPU 101 dedicated instruction codes for specifying addresses using this Q register are provided in the program. By the use, the processing efficiency and the capacity reduction of the main ROM 102 are realized. Note that, in various main CPU 101 dedicated instruction codes that perform addressing using the Q register, the Q register stores address data (address value) on the upper side of the address. Note that “F0H” is set in the Q register as an initial value immediately after the main CPU 101 is reset. Also, in the “LDQ, n (8-bit data)” instruction using the Q register, change the value of the Q register by setting an arbitrary 1-byte data to “n” and executing the instruction. Can.

  Furthermore, the main CPU 101 includes an interrupt page address register I and a memory refresh register R, which are configured by 1-byte registers, and an index register IX, an index register IY, which is configured by 2-byte registers. , A stack pointer SP and a program counter PC as dedicated registers.

<Internal Configuration of Main ROM and Main RAM (Memory Map)>
Next, with reference to FIGS. 11A to 11C, an internal configuration (hereinafter referred to as a “memory map”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described. 11A is a view showing a memory map of the entire memory, FIG. 11B is a view showing a memory map of the main ROM 102, and FIG. 11C is a view showing a memory map of the main RAM 103.

  In the memory map of the entire memory provided in the main control circuit 90 (microprocessor 91), as shown in FIG. 11A, from the top (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, The XCS decode areas are arranged at predetermined addresses in this order with non-use areas in between.

  In the memory map of the main ROM 102, as shown in FIG. 11B, the program area, the data area, the non-regulation area, the trademark recording area, the program management area and the security setting area are from the head (0000H) side of the address of the main ROM 102. In order, each is arranged at a predetermined address.

  In the program area, control programs of various processes to be executed by the main CPU 101 are stored in various control processes related to the playability of the game performed by the player. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, various data for the sub control circuit 200, and the like) in various control processes related to game playability implemented by the player. Data etc. for transmitting a control command (command) are stored. That is, in the gaming ROM area (game storage area) consisting of the program area and the data area, it is necessary for the control processing (processing related to the game property) related to the game property of the game actually played by the player in the game shop. Various programs and various data are stored.

  In addition, control programs and data of various processes (processes that do not affect the game property) that do not directly participate in the game property of the game performed by the player are stored in the non-regulation area. For example, programs and data used in pachislot 1 verification test (test injection test), control programs and data used in checksum generation processing at power failure, sum check processing at power recovery, etc., and anti-corruption program And the data etc. required for it are stored in the non-prescribed area.

  The program management area and the security setting area store various settings and management information regarding execution of the control program or security function. For example, setting and management information of start address and end address (that is, data range) of control program stored in the program area, setting and management information of address number of readable RAM area, reset setting and management information of WDT, Interrupt setting and management information, setting of permission / non-permission setting and management information of reading of control program stored in program area, setting and management information regarding activation of random number circuit 110, update method, etc., and setting of security mode described later The management information and the like are stored in the program management area and the security setting area. In the present embodiment, other settings and management information not related to the security function are stored in the program management area, and settings and management information related to the security function are stored in the security setting area. For example, the setting and management information may be stored as a single management area.

  In the memory map of the main RAM 103, as shown in FIG. 11C, from the top (F000H) side of the address of the main RAM 103, a gaming RAM area (predetermined storage area, gaming temporary storage area) and non-prescribed RAM area (non-prescribed temporary) Storage areas are arranged in this order at predetermined addresses.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the playability of the game performed by the player. . Then, each of the various data is stored in a work area of a predetermined address in the gaming RAM area.

  In the non-regulation RAM area, a non-regulation work area, which is a working area for various processes not directly involved in the gameplay of the game played by the player, and a non-regulation stack are provided. In the present embodiment, various processes that do not directly participate in the playability of the game performed by the player, such as a thumb check process, are executed using this non-specified RAM area.

  As described above, in the Pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes not directly involved in the playability of the game performed by the player in the main ROM 102 It is stored in a non-specified ROM area (non-specified storage area) arranged at an address different from the ROM area. In addition, various processes that do not directly participate in the playability of the game performed by such a player are performed in the main RAM 103 using a non-specified RAM area arranged at an address different from the game RAM area. .

  With such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are placed in the ROM area (non-specified ROM area) where the placement of programs and the like was not possible according to the conventional rules. can do. Therefore, in the present embodiment, compression of the capacity of the gaming ROM area can be avoided.

<Security mode>
Next, referring to FIG. 12, a security mode which is a part of the security function of the main control circuit 90 (microprocessor 91) will be described. FIG. 12 is a diagram for explaining the security mode.

  In the security mode, for example, when the power of the pachi slot 1 is turned on and a reset signal is input from the power management circuit 93, the microprocessor 91 operates. During this security mode, the activation of the main CPU 101 is delayed for a period corresponding to the setting stored in the security setting area (that is, execution of processing upon power on (see FIG. 48 described later) is started by the main CPU 101). Delay that). When the main CPU 101 is activated through this security mode, the security of the microprocessor 91 is secured, and a time necessary for activation control at power on is secured to activate the main CPU 101 stably.

  In the present embodiment, for example, the reset controller 106 can delay the start of the main CPU 101 by delaying the reset signal input at the time of power on for a predetermined period, or the interrupt controller 112 can It is also possible to delay the activation of the main CPU 101 by delaying the interrupt permission of the reset interrupt process (see FIG. 48 described later) at the time of power-on for a predetermined period. Further, each controller may cooperate to delay the activation of the main CPU 101. Further, for example, a delay circuit can be provided in the microprocessor 91 (or in the reset controller 106 or the interrupt controller 112), and the activation of the main CPU 101 can be delayed by this delay circuit. That is, the configuration (security unit) for executing the security function in the microprocessor 91 can be appropriately modified and applied according to the specification.

  As shown in FIG. 12, as the delay period in the security mode, a fixed extension time (fixed period) and a random extension time (variable period) can be set. In the present embodiment, for example, one of the plurality of fixed extension times is fixedly extended by selecting and setting one of the modes 1 to 8 in which different fixed extension times are associated with each other. A range of a plurality of random extension times can be set by selecting and setting one of the modes 1 to 4 in which the time can be set and the range of different random extension times is associated with each other. The range of one random extension time can be set from inside.

  For example, when “mode 4” is selected as the fixed extension time and “mode 4” is selected as the random extension time, and these settings are stored in the security setting area, the microprocessor 91 turns on the pachislot 1 power supply, When the reset signal is input from the power management circuit 93, first, the start of the main CPU 101 is delayed for about 4 seconds (4000 ms) as a fixed extension time, and then out of the range of 0 to 500 ms as a random extension time One extension time is randomly selected, and the start of the main CPU 101 is delayed for the selected time.

  Although the range of the fixed extension time and the random extension time can be set appropriately, in the present embodiment, the range of the random extension time is set from the viewpoint of shortening the time until the setting change becomes possible when the pachislot 1 is powered on. It is desirable to set "mode 1" in which the random extension time is always "0".

<Transition flow of gaming state>
Next, with reference to FIG. 13 and FIG. 14, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachislot 1 of the present embodiment and the transition flow thereof will be described. In addition, FIG. 13 is a transition flow diagram of the basic gaming state of the pachislot 1 and FIG. 14 takes into consideration the presence or absence of operation of the notification (AT. ART) function (that is, as a section of the game, a normal section and It is a transition flow diagram of the gaming state (differentiated from the advantageous section).

[Basic game state transition flow]
In the Pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") is provided as a type of bonus game. BB is a character continuously operating device according to a regular bonus (hereinafter referred to as "RB") called a first kind special character, and operates RB continuously.

  Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on the presence / absence (winning) of the bonus combination. Specifically, as shown in FIG. 13, the main control circuit 90 wins a bonus combination (internal winning combination of names “F_SBB”, “F_BB1”, “F_BB2”, “F_BB3”, “F_BB4” described later). Based on the presence / absence of operation (winning), three types of gaming states called "bonus not winning state", "between flags" and "bonus state" are managed.

  The bonus non-winning state is a state in which the bonus is not won and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, a state occurs in which the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, a state in which the bonus combination is won and the bonus is not activated.

  The presence or absence of a bonus combination is managed based on data stored in a hit request flag storage area (see FIG. 25 described later) and a carryover combination stored area (see FIG. 26 described later) provided in the main RAM 103. Be done. Further, the presence or absence of a bonus operation (winning) is managed based on data stored in a later-described game state flag storage area (see FIG. 27 described later) provided in the main RAM 103.

  Further, in the present embodiment, as shown in FIG. 13, in the gaming state in which the bonus is not activated (the bonus non-winning state and the state between flags), the types of internal winning combinations related to replay and their winning probability differ from each other. Five types of states (hereinafter, referred to as “RT0 state” to “RT4 state”, respectively) of RT0 gaming state to RT4 gaming state are provided. The RT0 state and the RT1 state are gaming states in which the probability that the replay combination is determined as an internal winning combination is low, and the RT2 state and the RT4 state are intermediate in the probability that the replay combination is determined as an internal winning combination It is a game state that becomes a middle probability. The RT3 state is a gaming state in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is any one of the RT0 state to the RT3 state, and the RT state in the inter-flag state is the RT4 state.

  Therefore, in the present embodiment, in the gaming state in which the bonus is not activated (bonus not won state and the state between the flags), the main control circuit 90 is further based on the type of internal winning combination related to replay and its winning probability. It also manages five types of states, RT0 state to RT4 state.

  The RT0 state to the RT4 state are managed based on data stored in a later-described game state flag storage area (see FIG. 27 described later) provided in the main RAM 103. Specifically, in the Pachislot 1 of the present embodiment, flags indicating the five RT states, that is, the RT0 state flag to the RT4 state flag, are provided, and the on / off states of these flags are managed by the main RAM 103 to control the RT state. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag in the on state as the current RT state. The RT0 state flag may not be provided, and when all the RT state flags are in the off state, the main control circuit 90 may specify that the current RT state is the RT0 state.

  As shown in FIG. 13, the bonus combination (names “F_SBB”, “F_BB1”, “F_BB2”, “F_BB3”, “F_BB4”) of the bonus combination is internal in the bonus non winning condition (RT0 to RT3 state). When the winning combination is determined (“bonus winning” in FIG. 13), the main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state (RT4 state). When the bonus combination is won in the inter-flag state ("Bonus formation" in FIG. 13), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

  Here, as the bonus state, SBB gaming state (SBB state), BB1 gaming state (BB1 state), BB2 gaming state (BB2 state), BB3 gaming state (BB3 state), and BB4 gaming state (BB4 state) are provided. Be As in the RT state, the main control circuit 90 performs the SBB state flag, the BB1 state flag, the BB2 state flag, the BB3 state flag, and the BB4 stored in a game state flag storage area (see FIG. 27 described later). The bonus state is managed by the on / off state of the state flag. Also, as described later, the RB1 gaming state (RB1 state) is always in the SBB and BB1 states, the RB2 gaming state (RB2 state) is always in the BB2 and BB3 states, and the RB3 gaming state (BB3) is always in the BB4 state. Since it becomes RB3 state, these are also managed by the ON / OFF state of RB1 state flag, RB2 state flag, and RB3 state flag stored in the below-mentioned game state flag storage area (see FIG. 27 described later) Do.

  In the bonus non winning condition, when the name “F_SBB” described later is determined as the internal winning combination, and the corresponding symbol combination “C_SBB_01” or “C_SBB_02” is displayed on the effective line in the inter-flag state, the main control circuit A step 90 shifts the gaming state from the inter-flag state to the SBB state. In the SBB state, it is always in the RB1 state, and when a medal exceeding the prescribed number "297" is paid out in the SBB state, the SBB state ends ("bonus end" in FIG. 13), and the main control circuit 90 Transition from the bonus state to the RT2 state.

  In addition, in the bonus non winning condition, when the name “F_BB1” described later is determined as the internal winning combination, and the corresponding symbol combination “C_BB1” is displayed on the effective line in the inter-flag state, the main control circuit 90 , Transition the gaming state from the flag state to the BB1 state. In the BB1 state, the RB1 state is always reached, and when the medal exceeding the prescribed number "297" is paid out in the BB1 state, the BB1 state ends ("bonus end" in FIG. 13), and the main control circuit 90 Transition from the bonus state to the RT2 state.

  In addition, in the bonus non winning condition, when the name “F_BB2” described later is determined as the internal winning combination, and the corresponding symbol combination “C_BB2” is displayed on the effective line in the inter-flag state, the main control circuit 90 The game state is shifted from the flag state to the BB2 state. In the BB2 state, it is always in the RB2 state, and in the BB2 state, when the medal exceeding the prescribed number "216" is paid out, the BB2 state ends ("bonus end" in FIG. 13), and the main control circuit 90 Transition from the bonus state to the RT2 state.

  In addition, in the bonus non winning condition, when the name “F_BB3” described later is determined as the internal winning combination, and the corresponding symbol combination “C_BB3” is displayed on the effective line in the inter-flag state, the main control circuit 90 The game state is shifted from the flag state to the BB3 state. In the BB3 state, it is always in the RB2 state, and in the BB3 state, when the medal exceeding the prescribed number "216" is paid out, the BB3 state ends ("bonus end" in FIG. 13), and the main control circuit 90 Transition from the bonus state to the RT2 state.

  In addition, in the bonus non winning condition, when the name “F_BB4” described later is determined as the internal winning combination, and the corresponding symbol combination “C_BB4” is displayed on the effective line in the inter-flag state, the main control circuit 90 The game state is shifted from the flag state to the BB4 state. In the BB4 state, it is always in the RB3 state, and in the BB4 state, when the medal exceeding the prescribed number "63" is paid out, the BB4 state ends ("bonus end" in FIG. 13), and the main control circuit 90 Transition from the bonus state to the RT2 state.

  In the RT0 state, any symbol combination of the symbol combination “R_transition point _01”, “R_ transition point _02”, “R_ transition point _03”, or “R_ transition point _04” described later is displayed on the effective line Then, the main control circuit 90 shifts the gaming state from the RT0 state to the RT1 state (FIG. 13 "transition point established" in FIG. 13). When the set value is changed, or when an initialization condition such as “RAM abnormality” described later is satisfied (“setting change / initialization condition satisfied” in FIG. 13), the game state is set as the initial state. Is in the RT0 state.

  In the RT1 state, any symbol combination of the symbol combination “C_ transition role _ 01”, “C_ transition role _ 02”, “C_ transition role _ 03”, or “C_ transition role _ 04” described later is displayed on the effective line When it is done (in FIG. 13, "transition combination is established"), the main control circuit 90 shifts the gaming state from the RT1 state to the RT0 state. Moreover, in RT1 state, when a combination of symbols of any of symbol combinations “C_RT2 transition _1_01” to “C_RT2 transition _1_08” or “C_RT2 transition _2” described later is displayed on the effective line (in FIG. 13, “in FIG. "RT2 transition ripple established", the main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

  In the RT2 state, any symbol combination of symbol combination “C_ transition role _ 01”, “C_ transition role _ 02”, “C_ transition role _ 03”, or “C_ transition role _ 04” described later is displayed on the effective line Then, the main control circuit 90 shifts the gaming state from the RT2 state to the RT0 state as shown in FIG. Also, in the RT2 state, a combination of symbols of any of the symbol combinations “R_transition point_01”, “R_transition point_02”, “R_transition point_03”, or “R_transition point_04” described later is on the effective line When the symbol combination “C_CUREP”, “C_RT1 transition_1_01” to “C_RT1 transition_1_04” or “C_RT1 transition_2” is displayed on the effective line, as shown in FIG. In 13, "transition point or RT1 transition ripple establishment", the main control circuit 90 shifts the gaming state from the RT2 state to the RT1 state. In addition, in the RT2 state, when any symbol combination of symbol combinations “C_RT3 transition_1_01” to “C_RT3 transition_1_04” to be described later is displayed on the effective line (in FIG. 13, “RT3 transition lip is established”) The main control circuit 90 shifts the gaming state from the RT2 state to the RT3 state.

  In the RT3 state, any symbol combination of symbol combination “C_ transition role _ 01”, “C_ transition role _ 02”, “C_ transition role _ 03”, or “C_ transition role _ 04” described later is displayed on the effective line Then, the main control circuit 90 shifts the gaming state from the RT3 state to the RT0 state as shown in FIG. Moreover, in the RT3 state, a combination of symbols of any of the symbol combinations “R_transition point_01”, “R_transition point_02”, “R_transition point_03”, or “R_transition point_04” described later is on the effective line When the symbol combination “C_CUREP”, “C_RT1 transition_1_01” to “C_RT1 transition_1_04” or “C_RT1 transition_2” is displayed on the effective line, as shown in FIG. In 13, "transition point or RT1 transition ripple establishment", the main control circuit 90 shifts the gaming state from the RT3 state to the RT1 state.

[Transition flow of the gaming state in consideration of the presence or absence of operation of the notification (AT · ART) function]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not the function (AT · ART function) for notifying a stop operation advantageous for the player is activated. Therefore, in the present embodiment, not only the bonus non-winning state, the inter-flag state, and the bonus state described above, but also the activated / deactivated state of the AT · ART function is managed as the gaming state. In the present embodiment, a section of the game in which the AT function or the ART function is activated is referred to as an "advantage section", and a section of the game in which neither the AT function nor the ART function is activated is referred to as a "normal section". .

  Further, in the present embodiment, when the bonus state is reached in the advantageous section, although the stop operation advantageous to the player is not notified in the bonus state, the bonus state is regarded as a section of a series of advantageous games for the player. Is included in the advantageous section, and when the bonus state is established in the normal section, the bonus state is included in the normal section. However, as will be described later, there is a case where a transition is made from a normal section to an advantageous section in the bonus state, and in this case, the bonus state is included in the advantageous section. Since the bonus state is a game state that is advantageous for the player as such, the bonus state may always be included in the advantageous section.

  In the pachislot 1 of the present embodiment, as shown in FIG. 14, the main control circuit 90 sets the gaming state of the normal section to the "normal gaming state", the gaming state of the advantageous section to the "AT gaming state", and the "ART preparation state". , "ART gaming state", and "CZ gaming state" to manage.

  The normal gaming state is a gaming state (non-AT, non-ART) in which information on stop operation advantageous to the player is not notified, and is a gaming state disadvantageous to the player. In the normal gaming state, winning the advantageous section transition lottery described later (in FIG. 14 "advantageous segment transition winning"), and also winning the ART stock lottery described later (in FIG. 14 "ART winning"). The main control circuit 90 shifts to an AT gaming state (ART transition) in which transition to an ART preparation state is made after the end of the AT gaming state. On the other hand, when not winning the ART stock lottery described later (in FIG. 14, "ART not won"), the main control circuit 90 basically does not shift to the ART preparation state after the end of the AT gaming state. Transition to the state (ART non transition). The details of the flow of the game in the normal gaming state will be described later with reference to FIG. 32 described later.

  The AT gaming state is a gaming state (AT) in which information of a stop operation which is advantageous for the player can be notified, and is a gaming state which is advantageous for the player as compared with the normal gaming state. In the AT gaming state, the main control circuit 90, the push order small part (described later "F_ left bell A", "F_ left bell B", "F_ left bell C", "F_ middle bell A", "F_ middle bell B), “F_Bell C”, “F_Right Bell A”, “F_Right Bell B”, “F_Right Bell C” internal winning combination) is determined to be an internal winning combination, It is determined whether to notify the information of the stop operation which is advantageous for the player, and when it is determined to notify, the information of the stop operation which is advantageous for the player (that is, the player can obtain the most medals) Information on the possible stop operation is notified (see FIG. 47 described later).

  In the AT gaming state, the main control circuit 90 performs push order replay (“F_RT2 transition_123”, “F_RT2 transition_132”, “F_RT2 transition_213”, “F_RT2 transition_231”, “F_RT2 transition_312”, and “F_RT2 transition_213” described later). F_RT2 transition _ 321 "," F_RT3 transition _ 123 "," F_RT3 transition _ 132 "," F_RT3 transition _ 213 "," F_RT3 transition _ 231 "," F_RT3 transition _ 312 "," F_RT3 transition _ 321 "," F_RT3 maintenance _1st "," F_RT3 It is not determined whether to notify information on stop operation advantageous to the player when any of internal maintenance of 中 維持 _2nd ’and 維持 F_RT3 中 __3rd’ is selected as an internal winning combination. , Information of stop operation advantageous to the player (ie, the player Taken is shifted to an advantageous RT state or not broadcast the information of the stop operation that can maintain a favorable RT state) (see FIG. 47 described later). In this sense, the RT function is not activated (except when accidental push order is correct), and only the AT function is activated.

  When the AT gaming state is the AT gaming state (ART transition), when the AT gaming state ends (in FIG. 14, "AT end"), the main control circuit 90 changes the gaming state from the AT gaming state (ART transition) to ART Move to preparation state. On the other hand, when the AT gaming state is the AT gaming state (ART non transition), when the AT gaming state ends ("AT end" in FIG. 14), the main control circuit 90 sets the gaming state to the AT gaming state (ART non Transition) to transition to the normal gaming state. The details of the flow of the game in the AT gaming state will be described later with reference to FIG. 34 described later.

  The ART preparation state is a gaming state (ART) in which information of a stop operation advantageous to the player can be notified, and is a gaming state advantageous to the player as compared with the normal gaming state and the AT gaming state. In the ART preparation state, the main control circuit 90 basically gives information of a stop operation which is advantageous for the player (ie, when any of the above-described push order small part and push order replay is determined as an internal winning combination (ie, The information on the stop operation that allows the player to obtain the most medals and to shift to the RT state advantageous to the player or to maintain the advantageous RT state is notified (see FIG. 47 described later) ).

  Here, when transitioning from the AT gaming state to the ART gaming state, in most cases, since the RT state in the AT gaming state is the RT1 state, the ART preparation state is determined to transition to the ART gaming state When the RT state is not the RT3 state, it is positioned as a preparation state for raising the RT state to the RT3 state corresponding to the ART gaming state. The main control circuit 90 basically shifts the gaming state from the ART preparation state to the ART gaming state when the RT state shifts to the RT3 state in the ART preparation state ("RT3 transition" in FIG. 14). The details of the flow of the game in the ART preparation state will be described later with reference to FIG. 37 described later.

  The ART gaming state is a gaming state (ART) in which information of a stop operation advantageous to the player can be notified, and is a gaming state advantageous to the player as compared with the normal gaming state and the AT gaming state. In the ART preparation state, the main control circuit 90 basically gives information of a stop operation which is advantageous for the player (ie, when any of the above-described push order small part and push order replay is determined as an internal winning combination (ie, The information on the stop operation that allows the player to obtain the most medals and to shift to the RT state advantageous to the player or to maintain the advantageous RT state is notified (see FIG. 47 described later) ). In addition, in the ART gaming state, the main control circuit 90 controls the ART 1 gaming state (ART 1), the ART 2 gaming state (ART 2), the ART 3 gaming state (ART 3), and the ART 4 gaming according to the winning type of ART stock type described later. Manage as any of the gaming states of the state (ART 4).

  In the ART gaming state (more specifically, the ART 1 gaming state), the ART gaming state ends (in FIG. 14, "ART ends"), and the CZ transition lottery described later is won (in FIG. 14, "CZ wins") The main control circuit 90 shifts the gaming state from the ART gaming state to the CZ gaming state. On the other hand, when not winning the CZ shift lottery described later (in FIG. 14, “CZ not won”), the main control circuit 90 shifts the gaming state from the ART gaming state to the normal gaming state. The details of the flow of the game in the ART gaming state (ART 1 to ART 4 gaming state) will be described later with reference to FIGS. 38, 39 and 42 to 44 described later.

  The CZ gaming state is a gaming state (ART) in which information of a stop operation advantageous to the player can be notified, and is a gaming state advantageous to the player as compared with the normal gaming state and the AT gaming state. In the CZ gaming state, basically, the main control circuit 90 receives information on a stop operation which is advantageous for the player when any of the above-described push order small part and push order replay is determined as an internal winning combination (ie, The information on the stop operation that allows the player to obtain the most medals and to shift to the RT state advantageous to the player or to maintain the advantageous RT state is notified (see FIG. 47 described later) ). In addition, in the CZ gaming state, the main control circuit 90 manages the gaming state as one of the CZ1 gaming state (CZ1) and the CZ2 gaming state (CZ2) according to the winning result of the CZ shift lottery which will be described later. .

  Here, the CZ gaming state is notified not only that the gaming state itself is an advantageous gaming state because information of a stop operation advantageous for the player can be informed, but also shifts to the ART gaming state after the termination of the ART gaming state ( Since it is determined whether or not to return, it is also a gaming state positioned as a so-called "chance zone".

  In the CZ gaming state (more specifically, the CZ1 gaming state), the main control circuit 90 starts the gaming state from the CZ gaming state when it wins the ART transition lottery described later (in FIG. 14, "ART winning" in FIG. 14). Move to ART gaming state. On the other hand, when the CZ gaming state ends ("CZ end" in FIG. 14) without winning the CZ shift lottery described later ("CZ not won" in FIG. 14), the main control circuit 90 The state is shifted from the CZ gaming state to the normal gaming state. The details of the game flow in the CZ gaming state (CZ1 and CZ2 gaming state) will be described later with reference to FIGS. 45 and 46 described later.

  Here, when transitioning to the bonus state in the normal gaming state, if winning an ART stock lottery described later performed during winning of the bonus combination or during the bonus state, transitioning to the ART preparation state is made after the bonus state ends. On the other hand, if the player does not win the ART stock lottery, which will be described later when the bonus combination is won or in the bonus state, the normal gaming state is maintained even after the end of the bonus state.

  In addition, when transitioning to the bonus state in the AT gaming state (ART transition), transitioning to the ART preparation state is made after the bonus state ends. Also, when transitioning to the bonus state in the AT gaming state (ART non transition), ART winning state after the end of the bonus state when winning the ART stock lottery described later performed during winning or bonus state of the bonus combination. Migrate to On the other hand, if the player does not win an ART stock lottery, which will be described later, which is performed when the bonus combination is won or in a bonus state, the AT gaming state (ART non-transition) is maintained even after the bonus state ends. In this case, the AT continuation possible period described later may be counted from the beginning, or may be returned to the count before winning the bonus.

  In addition, when transitioning to the bonus state in the ART preparation state, the ART preparation state is maintained even after the end of the bonus state. In addition, when transitioning to the bonus state in the ART gaming state, the ART gaming state before the transition is maintained even after the end of the bonus state. In this case, the ART stock is not newly released but returns to the ART gaming state before transition. Further, in this case, the ART continuation possible period described later may be counted from the beginning, or may be returned to the count before winning the bonus.

  In addition, if it is shifted to the bonus state in the CZ gaming state, and if it wins an ART stock lottery, which will be performed during the winning of the bonus combination or during the bonus state, it shifts to the ART preparation state after the bonus state ends. On the other hand, if the player does not win the ART stock lottery, which will be described later when the bonus combination is won or in the bonus state, the CZ gaming state is maintained even after the end of the bonus state. In this case, the CZ continuation possible period described later may be counted from the beginning, or may be returned to the count before winning the bonus. In addition, when the CZ gaming state is the CZ2 gaming state, regardless of the presence or absence of the ART stock lottery which will be performed during the winning of the bonus part or during the bonus state, transition to the ART preparation state after the end of the bonus state You may make it

  In the present embodiment, basically, a period in which each gaming state corresponding to the above-mentioned advantageous section is continued, or a period in which each gaming state is extended is managed by the number of games (number of games). The method of managing the period of the gaming state is not limited to this. For example, among the gaming states corresponding to the advantageous section described above, the period of one or more gaming states, the difference number obtained by subtracting the number of medals paid out during that period or the number of inserted medals therefrom It may be managed by (the net increase number), or may be managed by the number of times (the number of notices) that the notification which affects the payout of medals (that is, the notification when the above-mentioned push order small combination wins) .

<Structure of data table stored in main ROM>
Next, configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. In addition, the various data tables used in various lottery performed in each gaming state relating to the game nature described in FIG. 14 will be described later together with the description of each game nature separately.

[Symbol arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is data for specifying the position of each symbol in the rotational direction of each of the left reel 3L, middle reel 3C and right reel 3R and the type of symbol arranged at each position (hereinafter referred to as symbol code (FIG. 15) Define the correspondence with the symbol code table of

  In the symbol arrangement table, when the reel index is detected, the position of the symbol positioned in the middle region of each reel in the frame of the reel display window 4 is defined as “0”. Then, in each reel, the order corresponding to the value of the symbol counter in the order of proceeding in the direction of rotation of the reel (direction from symbol position "19" to symbol position "0" in FIG. 15) relative to symbol position "0" 0 "to" 19 "are assigned to each symbol as a symbol position.

  That is, by referring to the symbol counter values (“0” to “19”) and the symbol arrangement table, the symbols are displayed in the upper, middle and lower regions of each reel in the frame of the reel display window 4 It is possible to identify the type of symbol. In the present embodiment, “black 7”, “red 7”, “white BAR”, “black BAR 1”, “black BAR 2”, “cherry”, “bell”, “replay”, “watermelon” are used as symbols. And use 10 kinds of "blank" symbols.

  Further, in the present embodiment, as shown in the symbol code table, “00000001” is assigned as data to the symbol “black 7” (symbol code 1), and the symbol “red 7” (symbol code 2) is "00000010" is assigned as data. The symbol "White BAR" (symbol code 3) is assigned "00000011" as data, the symbol "black BAR 1" (symbol code 4) is assigned data "00000100", and the symbol "black BAR 2" "00000101" is assigned to the symbol code 5) as data.

  Data "00000110" is assigned to the symbol "cherry" (symbol code 6). The symbol "BELL" (symbol code 7) is assigned data "00000111", the symbol "REPLAY" (symbol code 8) is assigned data "0000 1000", and the symbol "watermelon" (symbol code 9) "00001001" is assigned as data, and "00001010" is assigned as data to the symbol "blank" (symbol code 10).

[Internal lottery table]
Next, with reference to FIGS. 16-18, the internal lottery table referred to when determining the internal winning combination will be described. FIGS. 16 and 17 show internal lottery tables referred to in the RT0 state to the RT4 state, respectively. FIG. 18 is an internal lottery table referred to in the bonus state.

  The internal lottery table is provided for each gaming state, and defines the correspondence between various internal winning combinations and lottery values when each internal winning combination is determined. The lottery value is defined for each setting value (settings 1 to 6) for adjusting an expected value of internal winnings such as a bonus combination and a small combination, which are set in advance. This setting is changed, for example, using the reset switch 76 and the setting key type switch 54 (see FIG. 7).

  In the internal lottery process of the present embodiment, first, random number values extracted from a predetermined numerical value range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 correspond to each internal winning combination. Add sequentially with the specified lottery value. Then, it is determined whether the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result has overflowed). Then, when the lottery result exceeds 65535 in a predetermined internal winning combination, it is determined that the internal winning combination has been won. In the internal lottery process of the present embodiment, an example is described in which the lottery value is added to the extracted random number value to perform the lottery, but the present invention is not limited to this, and the lottery value is subtracted from the random number value It is also possible to determine whether or not the internal lottery has won or not, by determining whether the subtraction result (lottery result) falls below “0” (whether or not the lottery result underflows).

  Therefore, in the internal lottery process of the present embodiment, the larger the internal winning combination defined as the lottery value is, the higher the probability of being determined. The winning probability of each internal winning combination can be represented by “lottery value defined for each winning number / number of all random values that may be extracted (random number denominator: 65536)”.

  In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, the type and the winning probability of the replay combination determined as the internal winning combination according to the type of the RT state. Changes. For example, the replay roles associated with the names “F_RT2 transition_123 (No. 21)” to “F_RT2 transition_321 (No. 26)” are not determined as internal winning combinations in the RT0 state, the RT2 state, and the RT3 state. It is decided as an internal winning combination in the state and the RT4 state.

  In FIG. 16 and FIG. 17, the internal winning combinations indicated by “No. 1” to “No. 19” are internal winning combinations in which the bonus combination and the replay combination or the small combination are simultaneously won. For example, "F_SBB + F_ middle row cherry lip (No. 1)" is a combination of symbols corresponding to the bonus combination "F_SBB", with the bonus combination "F_SBB" and the replay combination "F_ middle row cherry lip" being won in duplicate. Symbol combinations "REP 36" to "REP 54" and "REP 76" to "REP 80" (described later) corresponding to SBB 1 "and" SBB 2 "(see FIGS. 19 to 22 described later) and the replay role" F_ middle row cherry lip ". It is an internal winning combination in which the derivation of FIGS. 19 to 22) is permitted (a winning is permitted).

  In the present embodiment, in the inter-flag state (RT4 state), that is, in the state where the bonus combination has already been determined (carried over) as the internal winning combination, the bonus combination is not further determined. Therefore, in the inter-flag state (RT4 state), when the internal winning combinations indicated by "No. 1" to "No. 18" are determined as internal winning combinations, only the small combination or the replay combination corresponding to each is determined. It comes to win (see (* 1) in FIG. 16).

  Further, in FIGS. 16 and 17, the internal winning combinations indicated by “No. 19” to “No. 44” are internal winning combinations in which the replay role is won. For example, “F_normal REP A (No. 19)” is a combination of symbols “REP 36” to “REP 54” corresponding to the replay role “F_Normal Rep A” in which the replay role “F_Normal Rep A” is won. (See FIG. 19 to FIG. 22)) (the winning is permitted) is an internal winning combination.

  Moreover, in FIG.16 and FIG.17, the internal winning combination shown by "No. 45"-"No. 64" is an internal winning combination in which the small winning combination is won. For example, "F_ left bell A (No. 45)" is a combination of symbols "FRU 25" to "FRU 28", in which the small part "F_ left bell A" is won and the small part "F_ left bell A" corresponds. It is an internal winning combination that allows derivation of FRU 48 "to" FRU 51 "," FRU 56 "to" FRU 63 "and" FRU 72 "to" FRU 75 "(see FIGS. 19 to 22 described later). ing. The corresponding symbol combinations “HZR1” to “HZR4” are not a combination of symbols related to winning, but are a part of a combination of outlying symbols, but a symbol for shifting the gaming state from another RT state to the RT1 state It is a combination of symbols specified as a combination (transition point) of a symbol, and it is basically derived except when one of the internal winning combinations indicated by "No. 45" to "No. 53" is determined. As it is not permitted, it is described as a combination of corresponding symbols.

  Moreover, in FIG.16 and FIG.17, "No. 0" shows "disappearance" in which derivation | leading-out of the combination (refer FIGS. 19-22 mentioned later) of any of prescribed is also not permitted, The higher the “out of charge” allocation (lottery value), the more disadvantageous it is for the player. In the RT3 state, there is no case where "off" is determined. Also, in the RT4 state, although the probability that "off" is determined is described as "24414/65536", actually, one of the bonus combinations has already been determined as an internal winning combination (carried over and carried over) In this sense, there is no case where "out" is determined.

  In FIGS. 16 and 17, the internal lottery table in the case where the setting value is “1” (setting 1) is described as an example, but “No. 17”, “No. 18”, “No. For internal winning combinations other than the internal winning combinations shown in “20.” and “No. 55”, a common lottery value is set among the setting values. That is, they have the same winning probability. On the other hand, for the internal winning combinations shown in "No. 17", "No. 18", "No. 20" and "No. 55", between the setting values (or a predetermined setting value and a specific setting value) In the meantime, different lottery values are set. That is, they have different winning probabilities (see (* 2) and (* 3) in FIGS. 16 and 17).

  Specifically, for example, the internal winning combinations shown in "No. 17", "No. 18", and "No. 55" are "8", "72", respectively, when the set value is "1". When the set value is "6", while the extract value of "100" is set, the extract values of "18", "82", and "150" are set (that is, the set value is high) In the internal winning combinations shown in "No. 17" and "No. 18", the lottery value increases by "2" at every internal winning combination, and in the internal winning combination shown in "No. 55", the lottery value increases by "10" It has increased). Also, in the RT3 state, as the lottery value of the internal winning combination shown in "No. 17", "No. 18", and "No. 55" increases, the internal winning combination shown in "No. 20" , And the lottery value for that amount is set to decrease. For example, when the setting value is “1”, the extraction value of “1972” is set, whereas when the setting value is “6”, the extraction value of “1902” is set. In addition, these are examples which differ the winning probability of a specific internal winning combination among setting value.

  In FIG. 18, the internal winning combinations indicated by “No. 1” to “No. 6” are internal winning combinations in which the replay role is won, and the internal winning combinations indicated by “No. 7” and “No. 8”. The role is an internal winning role where a minor role wins. As described above, in the SBB and BB1 states, it is always controlled to the RB1 state, in the BB2 and BB3 states it is always controlled to the RB2 state, and in the BB4 state it is always controlled to the RB3 state, depending on each gaming state The internal winning combination is determined by the lottery value. Here, the lottery value of the replay combination is different between the RB1 state, the RB2 state, and the RB3 state. Therefore, in that sense, it may be said that the RB1 state, the RB2 state, and the RB3 state are different RT states.

[Symbol combination table]
Next, with reference to FIGS. 19-22, the symbol combination table which prescribes | regulates the combination of the symbol which concerns on a prize etc. in this embodiment is demonstrated. In the present embodiment, a symbol combination table is described as an example of data for predetermining combinations of a plurality of symbols, but the combination of symbols displayed on the main control circuit 90 side is identified. The data can also be defined in other ways, if possible. For example, the combination of symbol codes may be determined, and the combination of symbols displayed thereby may be identifiable.

  As shown in FIGS. 19 to 22, the symbol combination table defines in advance a combination of a plurality of symbols, and data indicating the type of combination of these symbols is defined as a display combination (winning operation flag). There is. In addition, the symbol combination table is formed of data of 22 bytes so as to correspond to the hit request flag storage area, the winning operation flag storage area (see FIG. 25 described later), and the symbol code storage area (see FIG. 30 described later). In addition, data indicating different display combinations (winning operation flag) is defined in each bit of each storage area.

  The display combination (prize operation flag) “HZR1” to “HZR4” is a symbol combination of an out of place, but when any combination of these symbols is displayed on the effective line, the RT condition is another It is a combination of symbols specified as a combination of symbols ("transition point") to shift from the RT gaming state to the RT1 state.

  The display combination (winning operation flag) "SBB1", "SBB2", "BB1", "BB2", "BB3" and "BB4" are combinations of symbols related to the bonus combination, and the combination of each symbol is display effective Activates the corresponding bonus state when displayed on the line. In addition, the combination of the symbol of "SBB1" and "SBB2" can be named generically as the combination of the symbol of "SBB".

  The display combination (prize operation flag) “REP1” to “REP6” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, re-play It is a combination of symbols defined as a combination of symbols (“RT1 transition lip”) that causes the RT state to shift from another RT state (for example, RT2 state and RT3 state) to the RT1 state while operating.

  The display combination (prize operation flag) “REP 7” to “REP 15” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, re-play It is a combination of symbols defined as a combination of symbols (“RT2 transition lip”) that causes the RT state to shift from another RT state (for example, the RT1 state) to the RT2 state while operating.

  The display combination (prize operation flag) “REP 16” to “REP 35” is a combination of symbols relating to the replay combination, and when the combination of any of these symbols is displayed on the effective line, re-play Activate. In addition, the combination of the symbols of "REP 16" to "REP 35" can be generically referred to as the combination of symbols of "Chance Lip".

  The display combination (prize operation flag) “REP 36” to “REP 54” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, re-play Activate. In addition, the combination of the symbols of "REP 36" to "REP 54" can be generically referred to as the combination of symbols of "normally rep".

  The display combination (prize operation flag) “REP 55” to “REP 58” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, re-play It is a combination of symbols defined as a combination of symbols (“RT3 transition lip”) that causes the RT state to shift from another RT state (for example, the RT2 state) to the RT3 state while operating.

  The display combination (prize operation flag) “REP 59” to “REP 62” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, re-play Activate. Note that “REP 59” and “REP 61” have two lines of “black BAR 1” and “black BAR 2” symbols (that is, “black BAR” symbols) if the timing of the stop operation is appropriate. It is a combination of symbols displayed side by side. On the other hand, if the timing of the stop operation is not appropriate, a combination of symbols of "REP 60" or "REP 62" is displayed, but basically "REP 59" to "REP 62" are used in various lottery etc. The role is common. Therefore, the combination of symbols “REP 59” to “REP 62” can be collectively referred to as “combination of WBAR aligned” or “black BAR double aligned”.

  The display combination (prize operation flag) “REP 63” to “REP 71” is a combination of symbols relating to the replay combination, and when the combination of any of these symbols is displayed on the effective line, re-play Activate. In addition, “REP 63”, “REP 64”, “REP 66”, “REP 68” and “REP 70” are the symbols of “black BAR 1” and “black BAR 2” described above if the timing of the stop operation is appropriate. , "Black BAR" symbol) is a combination of symbols displayed side by side in one line. On the other hand, if the timing of the stop operation is not an appropriate timing, a combination of other symbols is displayed, but basically, "REP 63" to "REP 71" share their roles such as various lottery described later ing. Therefore, the combination of symbols “REP 63” to “REP 71” can be collectively referred to as “SBAR aligned” or “black BAR single aligned” symbol combination.

  The display combination (prize operation flag) “REP 72” to “REP 75” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, re-play Activate. Note that “REP 72” and “REP 74” are the symbols of “black BAR 1” and “black BAR 2” described above (ie, “black BAR”) if the predetermined stop operation order and the timing of the stop operation are appropriate timings. A pattern is a combination of patterns that tempers but does not line up with any lines. On the other hand, even if it is a predetermined stop operation order, if the timing of the stop operation is not an appropriate timing, a combination of symbols of "REP 73" or "REP 75" is displayed, but basically "REP 72" to "REP 75" The role is common in various lottery etc. mentioned later. Therefore, the combination of the symbols “REP 72” to “REP 75” can be collectively referred to as “fake BAR aligned” or “black BAR aligned fake” symbol combination.

  The display combination (prize operation flag) “REP 76” to “REP 80” is a combination of symbols relating to the replay combination, and when any combination of these symbols is displayed on the effective line, the replay is performed Activate. In addition, the combination of the symbols of "REP 76" to "REP 80" can be generically referred to as the combination of "cherry lip" symbols.

  The display combination (prize operation flag) “JAC” is a combination of symbols relating to a small combination, and nine medals are paid out when the combination of the symbols is displayed on the effective line. In addition, the combination of the symbol of "JAC" can be called the combination of the symbol of "nine sheets JAC."

  The display combination (prize operation flag) “FRU1” to “FRU3” is a combination of symbols relating to the small combination, and when the combination of any of these symbols is displayed on the effective line, three pieces The medal is paid out. In addition, the combination of the symbol of "FRU1"-"FRU3" can be named generically the combination of the symbol of "weak cherry."

  The display combination (prize operation flag) “FRU 4” to “FRU 24” is a combination of symbols relating to a small combination, and when the combination of any of these symbols is displayed on the effective line, three pieces The medal is paid out. In addition, the combination of the symbol of "FRU4"-"FRU24" can be named generically as the combination of the symbol of "strong cherry."

  The display combination (prize operation flag) “FRU 25” to “FRU 28” is a combination of symbols relating to a small combination, and when a combination of any of these symbols is displayed on the effective line, nine The medal is paid out. In addition, the combination of the symbol of "FRU25"-"FRU28" can be named generically the combination of the symbol of "9 bells."

  Display combination (prize operation flag) "FRU29" and "FRU30" are a combination of symbols pertaining to a small combination, and when the combination of symbols of "FRU29" is displayed on the effective line, five medals are displayed. When the combination of symbols of "FRU 30" is displayed on the activated line, one medal is paid out. In addition, the combination of the symbol of "FRU29" and "FRU30" can be named generically as the combination of the symbol of "watermelon".

  The display combination (prize operation flag) “FRU 31” to “FRU 34” is a combination of symbols relating to a small combination, and when one of these symbol combinations is displayed on the effective line, It is a combination of symbols specified as a combination of symbols ("transition role") to shift the RT state from another RT state (e.g., RT1 to RT3 states) to the RT0 state while medals are paid out.

  The display combination (prize operation flag) “FRU 35” to “FRU 47” is a combination of symbols relating to a small combination, and when one of these symbol combinations is displayed on the effective line, The medal is paid out. In addition, the combination of the symbol of "FRU35"-"FRU47" can be named generically as the combination of the symbol of "the chance eyes."

  The display combination (prize operation flag) “FRU 48” to “FRU 75” is a combination of symbols relating to a small combination, and when one of these symbol combinations is displayed on the effective line, The medal is paid out. In addition, the combination of the symbol of "FRU48"-"FRU75" can be named generically as the combination of the symbol of "one sheet combination" or "control combination".

  The display combination (prize operation flag) “FRU 76” and “FRU 77” is a combination of symbols relating to a small combination, and when one of these symbol combinations is displayed on the effective line, The medal is paid out. The combination of symbols of "FRU 76" and "FRU 77" can be generically referred to as a combination of symbols of "special role".

[Correspondence between the internal winning combination, the stop operation sequence (strike) and the display combination etc.
Next, with reference to FIG. 23 and FIG. 24, the correspondence between the internal winning combination, the stop operation sequence (strike order), the display combination and the like will be described.

  In the pachislot 1 of the present embodiment, a combination of symbol combinations displayed according to the player's stop operation order (pushing order), a so-called "pushing order" (for example, the above-mentioned "pushing order small part" or "pushing order" Set up "order replay"). Since the stop buttons 17L, 17C, 17R corresponding to the reels 3L, 3C, 3R are provided, there are up to six stop operation orders (pushing order).

  In FIG.23 and FIG.24, it shows that the stop operation order (push order) is the order of "left, middle, right" as "strike order 1", and the stop operation order (push order) is "left, right, middle The order of "" is shown as "strike order 2", and that the stop operation order (push order) is "medium, left, right" order is shown as "strike order 3", and the stop operation order (push order) is The order of "middle, right, left" is indicated as "batting order 4", and that the stop operation order (pushing order) is in the order of "right, left, middle" as "bating order 5", the stop operation It is indicated as "strike order 6" that the order (push order) is in the order of "right, middle, left".

  As shown in FIG. 23 and FIG. 24, “F_Middle Cherry Lip” is a pushing order and if it is determined as an internal winning combination, if the stop operation order is “strike 1” to “strike 4” Regardless of the timing of the stop operation, if any of the winning "cherries" is established and the stop operation order is "strike order 5" and "strike order 6", regardless of the timing of the stop operation, One of the winning "normal ripples" is established. Note that “F_Middle Cherry Lip” is an internal winning combination in which the player's profit does not change depending on the stop operation order, though he is a push-on.

  Here, "regardless of the timing of the stop operation" means (in principle, when the effective line is one line of "cross-up line" and the maximum number of sliding symbols is "4") in each reel. It means that a symbol corresponding to 5 frames or less (within a range of 5 symbols) is disposed. In addition, for example, each of the combinations of symbols of "REP 76" to "REP 80" corresponding to "F_ middle row cherry lip" is independently arranged with symbols corresponding to 5 frames or less (within 5 symbols). There are no reels, but by allowing these winnings to be duplicated, the symbol corresponding to "F_ middle row cherry lip" is within 5 symbols in each reel as a whole internal winning combination (range for 5 symbols) In) is placed, and "regardless of the timing of the stop operation" is established. Hereinafter, the same applies to other display combinations (prize operation flag) and the like.

  When “F_normal_rip A” and “F_normal_rip B” are determined not to be a push order but to be an internal winning combination, the “normal case” is won regardless of the stop operation sequence and the timing of the stop operation. One of the two is established.

  “F_RT2 transition _ 123” is a pushing order, and when the internal winning combination is determined in the RT1 state, if the stop operation order is “strike order 1”, it is won regardless of the timing of the stop operation. One of the “RT2 transition ripples” is established, and the RT state shifts to the RT2 state. On the other hand, if the stop operation order is other than “strike order 1”, regardless of the timing of the stop operation, one of the other replay players who have won is established, and the RT state does not shift to the RT2 state, RT1 State is maintained (maintained).

  “F_RT2 transition _ 132” is a pushing executive, and when it is determined as an internal winning combination in the RT1 state, if the stop operation order is “strike order 2”, it has won regardless of the timing of the stop operation. One of the “RT2 transition ripples” is established, and the RT state shifts to the RT2 state. On the other hand, if the stop operation order is other than “striking order 2”, regardless of the timing of the stop operation, any one of the other replay players winning is established, and the RT state does not shift to the RT2 state, RT1 State is maintained (maintained).

  “F_RT2 transition _ 213” is a pushing bonus, and when it is determined as an internal winning combination in the RT1 state, if the stop operation order is “strike order 3”, it is won regardless of the stop operation timing. One of the “RT2 transition ripples” is established, and the RT state shifts to the RT2 state. On the other hand, if the stop operation order is other than “striking order 3”, one of the other replay players who have won is established regardless of the stop operation timing, and the RT state does not shift to the RT2 state, RT1 State is maintained (maintained).

  “F_RT2 transition _ 231” is a pushing executive, and when it is determined as an internal winning combination in the RT1 state, if the stop operation order is “strike order 4”, it is won regardless of the timing of the stop operation. One of the “RT2 transition ripples” is established, and the RT state shifts to the RT2 state. On the other hand, if the stop operation order is other than “striking order 4”, one of the other replay players who have won is established regardless of the stop operation timing, and the RT state does not shift to the RT2 state, RT1 State is maintained (maintained).

  “F_RT2 transition _ 312” is a pushing executive, and when it is determined as an internal winning combination in the RT1 state, if the stop operation order is “strike order 5”, it is won regardless of the timing of the stop operation. One of the “RT2 transition ripples” is established, and the RT state shifts to the RT2 state. On the other hand, if the stop operation order is other than the “striking order 5”, one of the other replay players who have won is established regardless of the stop operation timing, and the RT state does not shift to the RT2 state, RT1 State is maintained (maintained).

  “F_RT2 transition _ 321” is a pushing executive, and when it is determined as an internal winning combination in the RT1 state, if the stop operation order is “strike order 6”, it is won regardless of the timing of the stop operation. One of the “RT2 transition ripples” is established, and the RT state shifts to the RT2 state. On the other hand, if the stop operation order is other than the “striking order 6”, one of the other replay players who have won is established regardless of the stop operation timing, and the RT state does not shift to the RT2 state, RT1 State is maintained (maintained).

  “F_RT3 transition _ 123” is a pushing executive, and when it is determined as an internal winning combination in the RT2 state, if the stop operation order is “strike order 1”, it is won regardless of the stop operation timing. One of the “RT3 transition ripples” is established, and the RT state shifts to the RT3 state. On the other hand, if the stop operation order is other than “strike order 1”, one of the winning “RT1 transition rep” is established regardless of the stop operation timing, and the RT state shifts to the RT1 state.

  “F_RT3 transition _ 132” is a pushing executive, and when it is determined as an internal winning combination in the RT 2 state, if the stop operation order is “strike order 2”, it is won regardless of the timing of the stop operation. One of the “RT3 transition ripples” is established, and the RT state shifts to the RT3 state. On the other hand, if the stop operation order is other than “strike order 2”, regardless of the timing of the stop operation, one of the winning “RT1 transition reply” is established, and the RT state shifts to the RT1 state.

  “F_RT3 transition _ 213” is a pushing bonus, and when it is determined as an internal winning combination in the RT 2 state, if the stop operation order is “strike order 3”, it is won regardless of the timing of the stop operation. One of the “RT3 transition ripples” is established, and the RT state shifts to the RT3 state. On the other hand, if the stop operation order is other than “strike order 3”, regardless of the timing of the stop operation, one of the winning “RT1 transition rep” is established, and the RT state shifts to the RT1 state.

  “F_RT3 transition _ 231” is a pushing executive, and when it is determined as an internal winning combination in the RT 2 state, if the stop operation order is “strike order 4”, it is won regardless of the stop operation timing. One of the “RT3 transition ripples” is established, and the RT state shifts to the RT3 state. On the other hand, if the stop operation order is other than “strike order 4”, regardless of the timing of the stop operation, one of the winning “RT1 transition rep” is established, and the RT state shifts to the RT1 state.

  “F_RT3 transition _ 312” is a pushing executive, and when it is determined as an internal winning combination in the RT 2 state, if the stop operation order is “strike order 5”, it is won regardless of the timing of the stop operation. One of the “RT3 transition ripples” is established, and the RT state shifts to the RT3 state. On the other hand, if the stop operation order is other than "strike order 5", one of the winning "RT1 transition reply" is established regardless of the timing of the stop operation, and the RT state shifts to the RT1 state.

  “F_RT3 transition _ 321” is a pushing executive, and when it is determined as an internal winning combination in the RT2 state, if the stop operation order is “strike order 6”, it is won regardless of the timing of the stop operation. One of the “RT3 transition ripples” is established, and the RT state shifts to the RT3 state. On the other hand, if the stop operation order is other than “strike order 6”, regardless of the timing of the stop operation, one of the winning “RT1 transition reply” is established, and the RT state shifts to the RT1 state.

  "F_RT3 maintenance _1 st" is a pushing order, and when it is determined as an internal winning combination in the RT3 state, if the stop operation order is "strike 1" and "strike 2", regardless of the timing of the stop operation One of the replay roles other than the winning “RT1 transition ripple” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). On the other hand, if the stop operation order is other than “strike order 1” and “strike order 2”, regardless of the timing of the stop operation, one of the winning “RT1 transition reps” is established and the RT state is the RT1 state Migrate to

  “F_RT3 maintenance _2nd” is a pushing order, and when it is determined as an internal winning combination in the RT3 state, if the stop operation order is “strike 3” and “strike 4”, regardless of the stop operation timing One of the replay roles other than the winning “RT1 transition ripple” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). On the other hand, if the stop operation order is other than "strike order 3" and "strike order 4", regardless of the timing of the stop operation, one of the winning "RT1 transition reps" is established and the RT state is the RT1 state Migrate to

  "F_RT3 maintenance _3 rd" is a pushing order, and when it is determined as an internal winning combination in the RT3 state, if the stop operation order is "strike 5" and "strike 6", regardless of the timing of the halt operation One of the replay roles other than the winning “RT1 transition ripple” is established, the RT state does not shift to the RT1 state, and the RT3 state is maintained (maintained). On the other hand, if the stop operation order is other than "striking order 5" and "striking order 6", one of the winning "RT1 transition rep" is established regardless of the timing of the stopping operation, and the RT state is the RT1 state Migrate to

  If “F_WBAR Assortment A” and “F_WBAR Assortment B” are determined not to be a push order but to be an internal winning combination, the “Black BAR” symbol has two symbols if the timing of the stop operation is appropriate. Displayed alongside the line ("Black BAR Double Align"). In addition, if the timing of the stop operation is not the appropriate timing, the symbols of "black BAR" are not displayed side by side in two lines, but one of the combinations of symbols related to the other "black BAR double alignment" is established Do.

  If "F_SBAR Assemblies A" and "F_SBAR Assemblies B" are determined as internal winning combinations rather than push-to-stands, if the timing of the stop operation is appropriate, the symbol of "Black BAR" is one. Displayed alongside the line ("Black BAR Single Match"). In addition, if the timing of the stop operation is not a proper timing, the symbols of "black BAR" are not displayed side by side in one line, but one of the combinations of symbols related to the other "black BAR single match" is established Do.

  “F_NMLBRARA” and “F_NMLBRAB” are push-turns, and when the internal winning combination is determined, if the stop operation order is “strike 1” and “strike 2”, regardless of the stop operation timing, If one of the winning "RT3 Transition Rip" is established and the stop operation order is other than "strike order 1" and "strike order 2" and the timing of the stop operation is appropriate, "black BAR" The pattern is displayed on the screen ("Black BAR Match Fake"), and if the timing of the stop operation is not the appropriate timing, the "Black BAR" pattern is not displayed on the balance but other "Black BAR Match Fake" One of the combinations of symbols pertaining to Note that “F_NMLBRARA” and “F_NMLBRAB” can be determined as internal winning combinations in the RT3 state, RT4 state (inter-flag state), RB1 state and RB2 state (see FIGS. 16 to 18), but the RT4 state (between flags) In the RB1 and RB2 states, the gaming state does not shift even if the "RT3 transition reply" is established. Therefore, "F_NMLBRAA" and "F_NMLBRAB" are in the same order but they are stopped by the stop operation order. The profit is an internal winning combination that does not change.

  “F_chance lip _1st” is a pushing order, and when it is determined as an internal winning combination, if the stop operation order is “strike 1” and “strike 2”, winning regardless of the timing of the stop operation. If one of the "chance reps" being established is established, and the stop operation order is other than "strike order 1" and "strike order 2", the "normal rep" which has won, regardless of the timing of the stop operation. One of them is established, and the RT state does not change (maintain). Note that “F_chance lip_1st” is an internal winning combination in which the player's profit does not change depending on the stop operation order although the player is a substitute order.

  “F_chance lip _2nd” is a pushing order, and when it is determined as an internal winning combination, if the stop operation order is “strike order 3” and “strike order 4”, winning regardless of the timing of the stop operation. If one of the "chance reps" being established is established and the stop operation order is other than "strike order 3" and "strike order 4", the "normal rep" which is won regardless of the timing of the stop operation. One of them is established, and the RT state does not change (maintain). Note that "F_chance lip_2nd" is an internal winning combination in which the player's profit does not change depending on the stop operation order although he is a push-on.

  “F_chance lip _3 rd” is a pushing order, and when it is determined as an internal winning combination, if the stop operation order is “strike 5” and “strike 6”, the win is made regardless of the timing of the stop operation. If one of the "chance reps" being established is established and the stop operation order is other than "strike 5" and "strike 6", the winning "normal rep" is taken regardless of the timing of the stop operation. One of them is established, and the RT state does not change (maintain). Note that "F_chance lip_3rd" is an internal winning combination in which the player's profit does not change according to the stop operation order although he is a push-on.

  However, “F_Chance Rip_1st” to “F_Chance Rip_3rd” indicates that the combination of symbols of “Chance Rip” is displayed on the effective line if the stop operation order is appropriate, and the player is It is possible to recognize that you have won "Chance Lip" instead of "Rip", and you can enhance the sense of expectation in the various lottery etc. described later. Therefore, in “F_chance lip_1st” to “F_chance lip_3rd”, the game property that the feeling of expectation can be suggested or not suggested by the correctness of pushing order is added.

  “F_left bell A”, “F_left bell B” and “F_left bell C” are pushing side positions, and when determined as an internal winning combination, the stop operation order is “strike order 1” and “strike order 2 In the case of “”, regardless of the timing of the stop operation, any one of the winning “9-piece bell” is established, and nine medals are paid out. On the other hand, if the stop operation order is other than "striking order 1" and "striking order 2" and the timing of the stop operation is appropriate timing, any one of the winning "one sheet combination" (one sheet) is established. If the timing of the stop operation is not an appropriate timing, one of the associated “transition points” is established, and the medal is not paid out. In this case, if the RT state is the RT0 state, the RT2 state, and the RT3 state, the state shifts to the RT1 state.

  “F_Mei Bell A”, “F_Mei Bell B” and “F_Mei Bell C” are pushing seniors, and when determined as an internal winning combination, the stop operation order is “Striking order 3” and “Striking order 4 In the case of “”, regardless of the timing of the stop operation, any one of the winning “9-piece bell” is established, and nine medals are paid out. On the other hand, if the stop operation order is other than "striking order 3" and "striking order 4", and the timing of the stop operation is appropriate, any one of the winning "one-sheet combination" (one sheet) is established. If the timing of the stop operation is not an appropriate timing, one of the associated “transition points” is established, and the medal is not paid out. In this case, if the RT state is the RT0 state, the RT2 state, and the RT3 state, the state shifts to the RT1 state.

  “F_right bell A”, “F_right bell B”, and “F_right bell C” are pushing side positions, and when determined as an internal winning combination, the stop operation order is “strike order 5” and “strike order 6 In the case of “”, regardless of the timing of the stop operation, any one of the winning “9-piece bell” is established, and nine medals are paid out. On the other hand, if the stop operation order is other than "striking order 5" and "striking order 6", and the timing of the stop operation is appropriate timing, any one of the winning "one sheet combination" (one sheet) is established. If the timing of the stop operation is not an appropriate timing, one of the associated “transition points” is established, and the medal is not paid out. In this case, if the RT state is the RT0 state, the RT2 state, and the RT3 state, the state shifts to the RT1 state.

  In addition, in the pushing order small part ("F_ left bell A"-"F_ right bell C"), the stop operation is not the pushing order of the correct answer (that is, the pushing order that "9 sheets bell" holds) When the steps are sequentially performed, it is determined, for example, based on the timing of the stop operation at the time of the third stop operation whether or not the timing of the stop operation is an appropriate timing. Specifically, 2/3 timings of the timings of all the stop operations at the time of the third stop operation are determined as appropriate timings, and when the stop operation is performed at the relevant timing, “one sheet winning combination” ( When one sheet is established and the stopping operation is performed at the remaining 1/3 timing, the "transition point" is established because the timing of the stopping operation is not appropriate.

  When “F_common bell A” and “F_common bell B” are determined not to be a pushing order but to be an internal winning combination, “9” is winning regardless of the stop operation sequence and the timing of the stop operation. One of the "bells" is established, and nine medals are paid out.

  When "F _ weak cherry" is determined not to be a push on duty but to be an internal winning combination, if the timing of the stop operation is appropriate timing, any of the winning "weak cherry" is established. , 3 medals are paid out, and if the timing of the stop operation is not the appropriate timing, dropout of "weak cherry" occurs, and the combination of the pattern of the other than "transition" is displayed on the effective line Ru.

  "F _ strong cherries" is not a push 役 役, when it is determined as an internal winning combination, if the timing of the stop operation is appropriate timing, either of the winning "strong cherries" is established , 3 medals are paid out, and if the timing of the stop operation is not the appropriate timing, a dropout of "strong cherry" occurs, and the combination of the pattern of the off other than the "transition" is displayed on the effective line Ru.

  "F_ Watermelon" is not a pressing order but is determined as an internal winning combination, and if the timing of the stop operation is appropriate timing, the combination of the symbols of "FRU 29" described above is displayed on the effective line If the timing of the stop operation is not appropriate, the combination of the symbols of "FRU 30" described above is displayed on the effective line, and one medal is paid out.

  If “F_chance A” and “F_chance B” are determined not to be a push but an internal winning combination, if the timing of the stop operation is appropriate, the “chance has been won”. If one of the above is true, one medal is paid out, and the timing of the stop operation is not at the appropriate timing, a drop in “chance eye” will occur, and a symbol of a pattern other than “transition eye” The combination is displayed on the effective line.

  If “F_Transitioner A”, “F_Transitioner B”, “F_Transitioner C” and “F_Transitioner D” are determined not to be in-push order but be determined to be internal winning combinations, the timing of the stop operation is If the timing is appropriate, a drop of the "shifter" occurs, and combinations of symbols other than the "shift" are displayed on the effective line. In this case, although the medals are not paid out, since the current RT state is maintained, it is highly likely that the player is more advantageous to perform the stop operation of dropping the "transition player". Here, in that sense, it is described that it is the timing of the “proper” stop operation that the “transition player” has dropped. On the other hand, if the timing of the stop operation is not an appropriate timing, one of the winning "transition role" is established and one medal is paid out, but the RT state is the RT1 state, the RT2 state, and the RT3 state. If it is, it shifts to RT0 state.

  When “F_JAC Bell A” and “F_JAC Bell B” are determined not to be a push but to be an internal winning combination in the RB1 to RB3 states, a win is made regardless of the stop operation sequence and the timing of the stop operation. One of "9 sheets JAC" and "9 sheets bell" is established, and 9 medals are paid out.

  In the present embodiment, when the replay combination or the small combination and the bonus combination overlap and are determined as the internal winning combination (including the case where the bonus combination is carried over), the replay combination or the smaller combination than the bonus combination is included. The stop control may be performed to preferentially establish a bonus combination, but may be performed to set a bonus combination preferentially to a replay combination or a small combination.

  Here, stop control (determination method of stop symbol position) of the reel in the pachislot 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, stop control of the reel is performed such that the rotation of the corresponding reel is stopped within 190 msec. Specifically, it corresponds to the value obtained by adding one of the number of sliding symbols “0” to “4” to the value of the symbol counter corresponding to the relevant reel when the stop operation is detected. The symbol position is determined as a symbol position at which the rotation of the reel is stopped (hereinafter, referred to as "predetermined stop position"). The symbol position corresponding to the value of the symbol counter according to the corresponding reel when the stop operation is detected is the symbol position at which the stop of the rotation of the reel is started (hereinafter referred to as "stop start position").

  That is, the number of sliding symbols is the amount of rotation of the reel from when the stop operation is detected by the stop switch until when the rotation of the corresponding reel is stopped. In other words, it is the number of symbols passing through the middle region of the corresponding reel of the reel display window 4 in the period from when the stop operation is detected by the stop switch until when the rotation of the corresponding reel is stopped. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  Referring to the stop table (not shown), the number of sliding symbols is obtained according to the stop start position of each reel. In the present embodiment, the number of sliding symbols is acquired based on the stop table, but this is a temporary one, and the acquired number of sliding symbols does not immediately determine the planned stop position of the reel. In the present embodiment, when there is a more appropriate number of sliding symbols than the number of sliding symbols obtained based on the stop table (hereinafter referred to as “sliding number determination data”), a drawing priority table (not shown) is referred to. Change the number of sliding pieces. The sliding symbol number determination data is referred to determine the search order when comparing the priorities for each symbol from the stop start position to the symbol position four symbols ahead, which is the maximum sliding symbol number.

  In the reel stop control of the present embodiment, first, the number of sliding symbols is acquired based on a stop table (not shown). However, based on the priority, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces, it is changed to the appropriate number of sliding pieces. That is, in the present embodiment, the more appropriate number of sliding symbols is determined based on the priority of the symbol combination for permitting the stop display by the internal winning combination regardless of the number of sliding symbols acquired by the stop table.

<Configuration of Storage Area Provided in Main RAM>
Next, configurations of various storage areas provided in the main RAM 103 will be described with reference to FIGS.

[A hit request flag storage area and a winning operation flag storage area]
First, the configurations of the hit request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described with reference to FIG. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (prize flag data storage area) have the same configuration.

  In the present embodiment, the hit request flag storage area is composed of hit request storage areas 1 to 22 each represented by 1-byte data, and the winning operation flag storage area is a winning operation represented by 1-byte data. It is comprised by the storage areas 1-22. The data stored in each storage area of the hit request flag storage area and the winning operation flag storage area is only 1-byte data in the "data" column in FIG. 25. However, in FIG. "Combination" showing symbol combination of each reel corresponding to the bit of the storage area (denoted in the figure as symbol of left reel 3L, symbol of middle reel 3C and symbol of right reel 3R), and its The contents (see FIGS. 19 to 22) will also be described.

  When "1" is stored in the predetermined bit in each of the hit request flag storage areas 1 to 22, it indicates that the internal winning combination corresponding to the predetermined bit is internally won. Further, when “1” is stored in the predetermined bit in each of the winning operation storing areas 1 to 22, it indicates that the display combination (winning operation flag) corresponding to the predetermined bit is won. That is, when "1" is stored in a predetermined bit, it indicates that various symbol combinations of the internal winning combination corresponding to the predetermined bit are displayed on the effective line.

  The hit request flag storage area and the winning operation flag storage area may include one in which a plurality of symbol combinations are assigned to one bit (flag) in each storage area.

[Hold over part storage area]
Next, with reference to FIG. 26, the configuration of the carryover combination storage area will be described. In the present embodiment, the carryover combination storage area is configured of a 1-byte data storage area.

  When the internal winning combination "F_SBB", "F_BB1", "F_BB2", "F_BB3" or "F_BB4" is determined as a result of the internal lottery, the internal winning combination (BB combination) is a carryover holding area as a carryover role. Stored in The carryover combination stored in the carryover combination storage area is held without being cleared until the corresponding symbol combination is displayed on the effective line. While the carryover combination is stored in the carryover combination storage area, the carryover combination is stored in the hit request storage area in addition to the internal winning combination determined by the internal lottery.

  In addition, in the carryover combination storage area, although the areas of “SBB1” and “SBB2” are made different depending on that a plurality of combinations of symbols of “SBB” are defined, the area of “SBB” is simply 1 It is also possible to store data indicating that "F_SBB" is carried over.

[Playing state flag storage area]
Next, the configuration of the gaming state flag storage area will be described with reference to FIG. The gaming state flag storage area is configured by a 2-byte data storage area. In the present embodiment, as shown in FIG. 27, a unique bonus type or RT type is assigned to each bit of the gaming state flag storage area.

  In the gaming state flag storage area, when "1" is stored in a predetermined bit, it indicates that the bonus state or the RT state corresponding to the predetermined bit is being performed. For example, when "1" is stored in bit 0 of the gaming state flag storage area 1, it indicates that the gaming state is the SBB state. Also, for example, when "1" is stored in bit 0 of the gaming state flag storage area 2, it indicates that the gaming state is the RT0 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is formed of a 1-byte data storage area, and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

  For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, “1” is stored in bit 0 of the operation stop button storage area. Also, for example, in the case where the left stop button 17L is not yet pressed, that is, a valid stop button, “1” is stored in the bit 4. The main CPU 101 identifies the stop button pressed this time and the stop button not yet pressed, based on the data stored in the operation stop button storage area.

[Pressing order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The pressing order storage area is formed of a 1-byte data storage area, and stores a pressing order flag consisting of 1 byte.

  In the pressing order flag, the type of pressing order of the stop button is assigned to each bit. For example, when the pressing order of the stop button is “left, middle, right”, “1” is stored in bit 0 of the pressing order storage area.

[Symbol code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. In the present embodiment, the symbol code storage area is configured by symbol code storage areas 1 to 22 each represented by 1-byte data. The symbol code storage area has the same configuration as the hit request flag storage area and the winning operation flag storage area (see FIG. 25).

  In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the effective line. In addition, after all the reels stop, the symbol code corresponding to the display combination (winning operation flag) is stored in the symbol code storage areas 1 to 22.

[Relationship between internal winning combination and various sub-flags]
In the various game states related to the above-mentioned game characteristics, various data tables are referred to in various lottery by the main control circuit 90, but as parameters used at this time, in this embodiment, not only internal winning combinations but also internal winning combinations It also uses various parameters with different names (hereinafter referred to as "subflags"). Therefore, in the present embodiment, the main control circuit 90 performs processing for converting the internal winning combination into various sub-flags (see sub-flag conversion processing and the like in FIG. 69 described later). In the present embodiment, the sub flag is set in the start command as information (communication parameter) regarding the internal winning combination, and is transmitted from the main control circuit 90 to the sub control circuit 200.

  Here, with reference to FIG. 31, the correspondence between the internal winning combination and the various sub flags will be described. FIG. 31 is a diagram showing a basic correspondence relationship between the internal winning combination (more specifically, the type of the replay combination and the small combination) and the various sub-flags.

  As shown in FIG. 31, when the internal winning combination (abbreviation) is "off", the sub flag corresponds to "loss". Further, when the internal winning combination (abbreviation) is "F_ middle row cherry lip", the sub-flag corresponds to "middle row cherry". Further, when the internal winning combination (abbreviation) is "F_normal ripple A", the sub flag corresponds to "normal ripple A". In addition, when the internal winning combination (abbreviation) is "F_normal ripple B", the sub flag corresponds to "normal ripple B".

  In addition, the internal winning combination (abbreviation) “F_RT2 transition _123”, “F_RT2 transition _132”, “F_RT2 transition _213”, “F_RT2 transition _231”, “F_RT2 transition _312”, “F_RT2 transition _321”, “F_RT3 transition _123” , "F_RT3 transition _132", "F_RT3 transition _213", "F_RT3 transition _231", "F_RT3 transition _312", "F_RT3 transition _321", "F_RT3 maintenance _1 st", "F_RT3 maintenance _2nd" and "F_RT3 maintenance _3 rd" In the case, the sub-flag corresponds to "pushing order rep".

  When the internal winning combination (abbreviation) is “F_WBAR complete A”, the subflag corresponds to “WBAR complete A” when the BAR complete dip sub flag conversion lottery (see FIG. 40A described later) is successful. If not, the subflag corresponds to "normally Rip A". When the internal winning combination (abbreviation) is “F_WBAR complete B”, the subflag corresponds to “WBAR complete B” when winning the BAR complete dip sub flag conversion lottery described later (see FIG. 40A described later). If not, the subflag corresponds to "normally Rip A".

  When the internal winning combination (abbreviation) is “F_SBAR complete A”, the subflag corresponds to “SBAR complete A” when the BAR complete dip sub flag conversion lottery (see FIG. 40A described later) is successful. If not, the subflag corresponds to "normally Rip A". When the internal winning combination (abbreviation) is “F_SBAR complete B”, the subflag corresponds to “SBAR complete B” when winning the BAR complete dip sub flag conversion lottery (see FIG. 40A described later). If not, the subflag corresponds to "normally Rip A".

  Also, when the internal winning combination (abbreviation) is "F_NMLBRARA", the sub flag corresponds to "fake BAR full A". Also, when the internal winning combination (abbreviation) is "F_NMLBRAB", the sub flag corresponds to "fake bar alignment B". Also, when the internal winning combination (abbreviation) is "F_chance lip _1 st", the sub-flag corresponds to "chance lip A". Also, when the internal winning combination (abbreviation) is "F_chance lip _2nd", the sub-flag corresponds to "chance lip B". Also, if the internal winning combination (abbreviation) is "F_chance lip _3 rd", the sub-flag corresponds to "chance lip C".

  Further, when the internal winning combination (abbreviation) is "F_special role", the sub-flag corresponds to "chance lip C".

  Also, the internal winning combination (abbreviation) is "F_ left bell A", "F_ left bell B", "F_ left bell C", "F_ middle bell A", "F_ middle bell B", "F_ middle bell C" , “F_right bell A”, “F_right bell B”, and “F_right bell C”, the sub-flag corresponds to “push order bell”.

  When the internal winning combination (abbreviation) is "F_common bell A", the sub flag corresponds to "common bell A". Further, when the internal winning combination (abbreviation) is "F_common bell B", the sub flag corresponds to "common bell B". In addition, when the internal winning combination (abbreviation) is "F_ weak cherry", the sub-flag corresponds to "weak cherry". Also, when the internal winning combination (abbreviation) is "F_strong cherry", the sub-flag corresponds to "strong cherry".

  Also, when the internal winning combination (abbreviation) is "F_ watermelon", the sub-flag corresponds to "watermelon". Further, when the internal winning combination (abbreviation) is "F_chance A", the sub-flag corresponds to "Chance A". Also, when the internal winning combination (abbreviation) is "F_chance eye B", the sub-flag corresponds to "chance eye B".

  Also, when the internal winning combination (abbreviation) is "F_ transition combination A", "F_ transition combination B", "F_ transition combination C" and "F_ transition combination D", the sub-flag corresponds to "RT0 transition combination" . Further, when the internal winning combination (abbreviation) is "F_JAC bell A", the sub flag corresponds to "common bell A". Further, when the internal winning combination (abbreviation) is "F_JAC bell B", the sub flag corresponds to "common bell B".

  In the present embodiment, when the internal winning combination (abbreviation) is “F_normal ripple A”, the sub-flag is “normal ripple A”, and the internal winning combination (abbreviation) is “F_normal ripple B”. The sub-flag is configured to be “normally Rip B”, but in order to further improve the compressibility of the data, the internal winning combination (abbreviation) is either “F_normal ripple A” or “F_normal ripple B”. Even in the case of, it can be configured to correspond to the same sub-flag "normally ripple". “F_WBAR Match A” and “F_WBAR Match B”, “F_SBAR Match A” and “F_SBAR Match B”, “F_NMLBRA” and “F_NMLBRAB”, “F_Chance Lip _1st” to “F_Chance Lip _3rd”, “F Common Bell The same applies to A "and" F_common bell B "," F_chance eye A "and" F_chance eye B ", and" F_JAC bell A "and" F_JAC bell B ".

  Further, although in FIG. 31, the correspondence between the internal winning combination and the sub-flag is described as not considering the presence or absence of the winning combination of the bonus combination, it may be determined whether the bonus combination is overlapping or not, Alternatively, the correspondence between the internal winning combination and the sub-flag may be changed according to whether or not the bonus combination is carried over.

<Playability during normal gaming state>
Next, with reference to FIG. 32, the flow of the gaming in the normal gaming state will be described. FIG. 33 is a diagram showing an example of various tables referred to at least in the normal gaming state, and these data tables are stored in the main ROM 102.

  As shown in FIG. 32, when in the normal gaming state and in the bonus non-winning state, when winning the bonus combination (SBB, BB1 to BB3) in which the same winning probability is set among the set values (figure During the 32nd, "bonus win"), ART stock lottery is performed at the time of bonus win. Here, the ART stock is a right to start or extend (continue) the game period of the ART gaming state described later. In the case of winning a bonus combination (BB4) in which different winning probabilities are set among the set values, the ART stock lottery at the bonus winning time is not performed. Further, the drawing table referred to in the ART stock drawing at the bonus winning time is not shown.

  In addition, in the normal gaming state and the bonus not won state, when a specific bonus combination (SBB, BB1) is won, a special ART stock lottery at the time of bonus winning is performed. Specifically, with reference to the bonus winning special ART stock lottery table shown in FIG. 33D, whether ART stock is given based on the winning bonus type (SBB, BB1) and the lottery value, And when ART stock is given, the type (ART1 to ART4) is determined. If the winning combination is SBB, ART stock will always be awarded. In addition, when it is determined that ART stock is given in the lottery, a special effect different from the effect in the normal bonus state is performed during the bonus state. That is, it may be said that the lottery is a lottery as to whether or not to perform a special effect.

  In addition, when the bonus combination being won is in the normal gaming state and in the inter-flag state ("Bonus established" in FIG. 32), the ART stock lottery during the bonus is performed in the transitioned bonus state. To be done. Specifically, the ART stock lottery table during the bonus shown in FIG. 33E is referred to, and based on the internal winning combination (sub-flag) and the lottery value, whether ART stock is awarded and ART stock is awarded. If it is determined, the type (ART1 to ART4) is determined. However, in the bonus state based on the bonus combination (BB4) in which winning probabilities different among the set values are set, ART stock lottery during this bonus is not performed. In addition, when the internal winning combination is "WBAR match" and "SBAR match", ART stock is always provided. In the present embodiment, in the same manner, various lottery related to the game property is not performed in the inter-flag state (except for the game in which the bonus combination is won) in each gaming state in the advantageous section described later.

  Then, when the bonus status ends, if there is one or more ART stock according to the ART stock lottery when the bonus is won, the special ART stock lottery when the bonus is won, and the ART stock lottery during the bonus, as shown in FIG. 32. In the "stock" state, the bonus state is shifted to the ART preparation state. On the other hand, if any ART stock is 0 (“no stock” in FIG. 32), at the end of BB1 to BB3, the bonus state is shifted to the AT gaming state (ART non transition), If it is at the end of BB4, the state shifts from the bonus state to the non-bonus / non-flag state (that is, the bonus non-winning state in the normal game state).

  That is, in the present embodiment, in the normal gaming state, it is determined that the ART gaming state is always awarded when SBB is won, and when BB1 to BB3 are won, the above-described lottery (ART stock lottery) If it is won, it is determined that the ART gaming state is awarded, and if it is not won, the AT gaming state is decided to be awarded, and if BB4 is won, the ART gaming state and the AT gaming state are also awarded. It is supposed not to be decided. In addition, this shows an example of the playability of a normal game state, and the invention of this embodiment is not limited to this. For example, when the BB1 to BB3 gaming state ends and the ART gaming state is not determined to be granted, the AT transition lottery is performed, and if the lottery is won, the AT gaming state is shifted to When not winning this lottery, it may be made to shift to the bonus non-winning state of the normal gaming state. Further, when transitioning to the AT gaming state (ART non-transition) after the end of the bonus state, at that time, it is possible to perform lottery of the AT continuation possible period which will be described later.

  Further, when it is in the normal gaming state and in the bonus non-winning state, when a specific combination other than the bonus combination (specific small combination and replay combination) is won, advantageous section transition lottery is performed. Specifically, the advantageous section transition lottery table shown in FIG. 33A is referred to, and it is determined based on the internal winning combination (sub-flag) and the lottery value whether or not to shift to the advantageous section. When not winning this advantageous section transition lottery, the game in the bonus non-winning state of the normal gaming state will be repeated.

  On the other hand, when the advantageous section transition lottery is won (in FIG. 32, “transition win”), ART stock lottery is subsequently performed. Specifically, the ART stock lottery table shown in FIG. 33B is referred to, and whether ART stock is given or not is given based on the internal winning combination (sub-flag) and the lottery value. The degree (long and short) of the duration of the AT gaming state (AT period) is determined, and the type (ART1 to ART4) is determined when ART stock is given.

  That is, in the present embodiment, transition to both the AT gaming state and the ART gaming state by the advantageous section transition lottery and the ART stock lottery described above (that is, the result of the advantageous section transition lottery is “transition”, and the ART stock is The result of lottery is to shift to AT gaming state but not to transition to ART gaming state (that is, the result of advantageous section transition lottery is “transition”, and the result of ART stock lottery is “non-stock”) It is possible to decide not to shift to the AT gaming state or to the ART gaming state (that is, the result of the advantageous section transition lottery "does not to transition") and the AT gaming state or the AT gaming state. In addition, this shows an example of the playability of a normal game state, and the invention of this embodiment is not limited to this. For example, in ART stock lottery, not transitioning to AT gaming state but transitioning to ART gaming state (that is, the result of advantageous section transition lottery is "transition" and the result of ART stock lottery is "stock winning" However, it may be possible to decide to shift to the ART gaming state without going through the AT gaming state).

  Further, after the ART stock lottery is performed, subsequently, the AT continuation possible period lottery based on the result of the ART stock lottery is performed, and the gaming period in the AT gaming state is determined. Specifically, reference is made to the AT-continuous-period lottery table shown in FIG. 33C, and the AT-continuous period is determined based on the ART stock lottery result and the lottery value. That is, the game period in the AT gaming state is determined in accordance with whether or not the ART stock is provided, and the length of the AT period determined when the ART stock is not provided. In FIG. 33C, “1 to 8 games” have “1”, “2”, “3”, “4”, “5”, “6”, “7” and “8” as the AT continuation possible period. Indicates that the number of games is determined. The same applies to "9 to 16 games", "17 to 24 games" and "25 to 32 games". In order to determine a specific number of games, a lottery table may be provided separately (or a lottery value may be defined) to perform lottery, or each lottery value shown in FIG. 33C. Can be allocated equally to each game number to perform lottery.

  In the present embodiment, an example is described in which the advantageous section transition lottery table used for the advantageous section transition lottery and the ART stock lottery table used for the ART stock lottery are provided as separate tables, but the configuration of the lottery table Is not limited to this. For example, according to one lottery table, whether or not to shift to an advantageous section, and if it is further transitioned to an advantageous section, whether to add ART stock or not and its type (ART1 to ART4, as a type for ART stock, As a type in the case of not giving ART stock, the length of AT period may be determined.

<Playability during AT gaming state>
Next, with reference to FIG. 34, the flow of AT play state game will be described. 35 and 36 show an example of various tables referred to at least in the AT gaming state, and these data tables are stored in the main ROM 102. It is to be noted that, in the AT gaming state, when it is in the inter-flag state and in the bonus state, basically the same lottery and processing as those described in the game characteristics in the normal gaming state are performed, as shown in FIG. So, the explanation of the playability in these states is omitted.

  As shown in FIG. 34, in the AT gaming state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. Specifically, the navi-mode lottery table shown in FIG. 35 is referred to, and the advantageous interval duration described later, the current ART stock number (the total number of ART 1 to ART 4 regardless of ART stock type), and the lottery value , Navi mode is determined. Here, in the present embodiment, an upper limit ("1500" as the advantageous section duration) is provided to the number of games in which a series of advantageous sections can be continued, and in the navigation mode, the number of games up to the upper limit in the advantageous section And the number of ART stocks currently held, and used as data for changing various lottery results (for example, the success or failure of ART stock lottery in ART 1 described later) in the advantageous section.

  In this navi mode lottery, the navi mode of any of navi modes “0” to “3” is determined, but, for example, the more the remaining period of the advantageous section duration (ie, the less the number of games in the advantageous period) The navigation mode having a smaller value is more likely to be determined, and the navigation mode having a larger value is more likely to be determined as the remaining period of the advantageous period is smaller (that is, as the number of games in the advantageous period is larger). Also, the smaller the ART stock number, the easier the navigation mode with smaller value is determined, and the larger the ART stock number, the easier the navigation mode with a larger value is determined. And in this embodiment, when the value of navi mode is large, it is made for various lottery results in an advantageous section to be relatively disadvantageous compared with the case where the value of navi mode is small. This is because, for example, when the advantageous section is forcibly ended by the digestion of the advantageous section duration, if a large number of ART stocks remain, the player feels a sense of loss and the interest of the game is interesting. In view of such a point, there is a risk of lowering, and it is made from the viewpoint of suppressing giving the player the right to be wasted.

  Further, when the player is in the AT gaming state and the bonus is not won, in the case of winning the pushing order small part (pushing order bell), the bell navigation generation lottery is performed. Specifically, the bell navigation generation lottery table shown in FIG. 36A is referred to, and a notification of pushing order of the pushing order small combination is already performed in the AT gaming state type (ART non transition or ART transition) and the AT gaming state Whether or not to issue a push order notification of the push order small combination based on the number of times (the bell navigation has been generated) (the number of bell navigation occurrences) and the lottery value, and in the case of performing the push order notification It is determined whether or not. In the present embodiment, the occurrence probability of the bell navigation is higher in the AT gaming state (ART transition) than in the AT gaming state (ART non transition).

  In this bell navigation generation lottery, when it is not determined to perform the pushing order notification of the pushing order small combination (in FIG. 34, "Bell navigation occurrence non winning"), the pushing order notification of the pushing order small combination is not performed . In addition, in this bell navigation generation lottery, when it is determined to perform the pushing order notification of the pushing order small combination (in FIG. 34, "Bell navigation generation winning prize"), the pushing order notification of the pushing order small combination is performed ( In FIG. 34, "stop operation procedure notification"). That is, in the present embodiment, the AT gaming state is a gaming state in which information of an advantageous stop operation can be notified by the player, but whether or not information of the stop operation can be notified is determined by lottery. As a result of the lottery, the player's profit is also changed.

  Further, in the bell navigation generation lottery, it is determined that the pressing order notification of the pressing order small part is to be performed, and it is also determined that the freezing is to be performed (in FIG. 36A, “to win (freeze)”). A notification of pushing order of the small player is performed, and the game operation of the player is invalidated for a predetermined period at any timing of the start operation and the first stop operation to the third stop operation (for example, after the first stop operation). A freeze production is performed. Then, when this freeze effect is performed, if it is AT gaming state (ART non-transition), a specific ART stock (for example, ART 1) is given (in-AT promotion promotion lottery described later). In addition, in the case of AT gaming state (ART transition), the currently held ART stock is promoted to a more advantageous ART stock (a promotion lottery during AT described later). Therefore, even if it is AT gaming state (ART non transition), it is possible to shift to ART gaming state via ART preparation state after the end of AT gaming state, by winning in the bell navigation with this freeze. When freeze effect is performed in the AT gaming state (ART non-transition), the type of ART stock to be provided may be determined by lottery. In addition, when a freeze effect is performed in the AT gaming state (ART transition), ART stock may be additionally provided.

  In addition, when it is AT game state, when it is in bonus non winning state, when winning the specified part other than the bonus part (specific small part and replay part), or when the above-mentioned freeze production is done, A promotion lottery is performed during AT. Specifically, the AT-promoted lottery table shown in FIG. 36B is referred to, and based on the AT gaming state type (ART non-transition or ART transition), internal winning combination (sub-flag), etc., and lottery value, If AT period "short" in AT gaming state (ART non transition), "ART 1" is given as ART stock and promoted to AT gaming state (ART transition) whether to shift to AT period "long" or not It is determined whether or not to shift, and if it is AT gaming state (ART transition: a state in which any of “ART 1” to “ART 3” is given as ART stock), the ART stock given is more advantageous It is determined whether or not to promote the transition gradually as ART stock. In addition, if AT period “long” in AT gaming state (ART non transition), “ART 1” is given as ART stock and it is determined whether or not to be promoted to AT gaming state (ART transition) May be The winning probability in this case may be the same probability as in the case of AT period “short” in the AT gaming state (ART non transition) or may be a probability higher than this.

  In the present embodiment, four types of ART stock (right) of "ART 1", "ART 2", "ART 3" and "ART 4" are defined, and "ART 1" is the most advantageous for the player. The player's degree of advantage increases in the order of "ART 2", "ART 3", and "ART 4" in the low order. Therefore, in the AT-promoted lottery, if the "ART 4" is given as ART stock, the promoted lottery is not performed. When “ART 4” is given as the ART stock, whether or not to give “ART 1” as the ART stock may be determined in the AT-promoted lottery.

  Further, in the present embodiment, the priority (priority) to be used (released) preferentially for four types of ART stock (rights) “ART 1”, “ART 2”, “ART 3” and “ART 4” is defined. In this case, “ART 1” is used (released) with the lowest priority, and “ART 2”, “ART 3”, and “ART 4” are sequentially used (released) in this order. For example, when one "ART 1", one "ART 2" and one "ART 3" are given as ART stock, "ART 3" is first used (released) and then "ART 2" is used (Released) and then "ART 1" is to be used (released). Therefore, in the AT-promoted lottery, when a plurality of ART stocks are given, the ART stock with the highest priority is subjected to the promoted lottery. For example, when "ART 2" and "ART 3" are given one by one, "ART 3" with high priority is subject to promotion lottery, and "ART 3" is made "ART 4" in the promotion lottery during AT. A lottery will be conducted to decide whether to promote or not. In this case, the ART stock with the lowest priority can be the target of the promotion lottery, or all of the granted ART stock can be the target of the promotion lottery.

  Also, in the present embodiment, in the AT gaming state (in which ART transition: one of “ART 1” to “ART 3” is given as ART stock), whether or not to promote the ART stock given one by one I try to decide whether or not. That is, it is determined whether or not to promote promotion transition by one step, such as “ART 2” for “ART 1”, “ART 3” for “ART 2”, etc. If it is "ART 1", the decision whether to promote to "ART 2", the decision whether to promote to "ART 3", and the decision whether to promote to "ART 4" will be made You can also That is, it may be possible to determine whether or not to promote the granted ART stock in multiple stages.

  When the player is in the AT gaming state and the bonus is not won, the AT continuation possible period re-lottery is performed when one of the winnings in the AT-promoted lottery is won (in FIG. 34, "promotion win"). It will be. That is, the AT continuation possible period is determined again based on winning the promotion lottery. In this AT continuation possible period re-lottery, the AT continuation possible period may be newly determined by referring to the same table as the AT continuation possible period lottery table shown in FIG. 33C, for example, By referring to a table in which a plurality of parameters such as "What game extension" is defined, it is possible to determine a period for extending the AT continuation possible period determined at the transition of the AT gaming state. In the case of the former, it is recommended that an AT continuation possible period longer than the AT continuation possible period determined at the time of transition of the AT gaming state be newly determined, including the AT continuation possible period already digested. .

  Further, when in the AT gaming state and in the bonus non-winning state, the AT continuation possible period is updated every unit game. Specifically, “1” is subtracted from the number of games in the AT continuation possible period, and then it is determined whether the AT continuation possible period is digested (that is, whether the subtraction result is “0”) or not . In addition, in renewal of AT continuation possible period, the game frequency is added 1 at a time every unit game, subsequently, it is judged whether the addition result reaches the game frequency of AT continuation possible period, It may be determined whether the AT continuation possible period has been digested.

  As a result of updating the AT duration, if the AT duration is not digested (in FIG. 34, "period undigested"), and the AT duration is digested, the "number of bell navigation occurrences" is still "0". (Ie, in the AT gaming state, the pressing order notification has not been performed even once) (in FIG. 34, "Period to digest Bernavi = 0"), the AT gaming state continues, and the AT non-boning bonus non-playing state occurs. The game in winning condition will be repeated.

  In addition, as a result of the AT continuation possible period renewal, the AT continuation possible period is digested, “the number of bell navigation occurrence” is “1” or more (that is, at least one push order notification is performed in the AT gaming state) ( In FIG. 34, if there is one or more ART stocks in “Periodically digested Bernabi ≧ 1” (in FIG. 34, “stocks exist”), the AT gaming state is shifted to the ART preparation state. . On the other hand, if none of the ART stocks are (in FIG. 34, "no stock"), the AT gaming state is shifted to the normal gaming state.

  In addition, as a result of the AT continuation possible period renewal, “the number of bell navigator occurrence” is still “0” (ie, no push order notification has been made in the AT gaming state) and 32 games in the AT continuation possible period If a game is played (in FIG. 34, “32 G digestion Bernavi = 0”) and there is no ART stock (in FIG. 34, “no stock”), the AT gaming state is set. In addition to granting “ART 1” as ART stock as a remedy that could not enjoy the benefit, a promotion lottery is carried out on this granted “ART 1”, and if it wins the promotion lottery, it grants the ART stock after promotion If not won, "ART 1" is granted, and the AT gaming state is shifted to the ART preparation state. Here, the ART stock of any one of “ART 1” to “ART 4” may be provided by lottery simply without performing the promotion lottery. Furthermore, in this case, if "32" or more games are determined as the AT continuation possible period, and as a result that bell navigation did not occur although less than "32" games were determined as the AT continuation possible period. If the "32" game continues, ART stock will be awarded in each case, for example, ART stock will not be awarded in the former case, and ART stock will be awarded only in the latter case. It may be done.

  Although illustration is omitted in FIG. 34, when the bonus combination is won in the AT gaming state, ART stock lottery different from the normal gaming state is performed. In the normal gaming state, which is a normal section, ART stock lottery is carried out when winning a bonus combination (SBB, BB1 to BB3) in which the same winning probability is set among the set values, and differs among the set values Although it is assumed that ART stock lottery is not performed when winning a bonus combination (BB4) for which a winning probability is set (see FIG. 32 and FIG. 33), in the advantageous section including the AT gaming state, any bonus If the bonus is won, the ART stock lottery is also performed. That is, in the advantageous section, ART stock lottery is performed as common processing of the advantageous section regardless of the type of bonus combination. In addition to ART stock lottery at the time of winning a bonus when winning a bonus combination, ART stock lottery during bonus may be performed as common processing of an advantageous section even during a bonus state. In this case, the in-bonus ART stock lottery table shown in FIG. 33E may be referred to, or a different lottery table may be referred to.

  FIG. 36C shows an ART stock lottery table at the time of winning a bonus which is referred to when a bonus combination is won in an advantageous section including an AT gaming state. In the advantageous section including the AT gaming state, whether or not the ART stock is provided based on the gaming state type and the lottery value shown in FIG. If it is assigned, its type (ART1 to ART4) is determined. When the winning combination is "SBB" or "BB1", a special ART stock lottery at the bonus winning described with reference to FIG. 33D may be performed. In this case, the ART stock lottery may not be performed at the bonus winning time described here.

  In addition, when the bonus state ends in the AT gaming state, when there is one or more ART stocks (including the advantageous section lottery described above, the elevation lottery during AT, the ART stock lottery when the bonus is won, any lottery result is included) ) Transitions from the bonus state to the ART preparation state without returning to the AT gaming state. On the other hand, if any ART stock is zero, it returns to the AT gaming state. When returning to the AT gaming state, the AT continuation possible period may be determined again by lottery, and the determined AT continuation possible period may be newly set, or the AT continuation possible period already determined may be set. It may be taken over to return to the AT gaming state. Further, when returning to the AT gaming state, the bell navigation occurrence number may be returned to the initial value "0", or the bell navigation occurrence number already counted may be taken over to return to the AT gaming state. Good. When returning to the AT gaming state, the bell navigation generation lottery may not be performed in the returned AT gaming state. That is, in the AT gaming state, when it has once shifted to the bonus state, the push order notification may not be performed in the subsequent bonus non-winning state. In this case, various transition processes may be performed as in the case where the “number of bell navigation occurrences” is “1” or more.

  In the present embodiment, the termination condition of the AT gaming state as the advantageous section, the completion of the prescribed period (AT continuation possible period), and the occurrence of the bell navigation at least once ("the number of bell navigation occurrences is" 1 "or more However, the termination condition of the AT gaming state is not limited to this. For example, after winning a bonus combination in the AT gaming state and becoming a bonus state, if any ART stock is zero when the bonus state is over, the game state may be shifted to the normal gaming state. Good. That is, the operation of the bonus state may be used as the termination condition of the AT gaming state. Further, the number of times of the bell navigation set as the termination condition of the AT gaming state or the termination possible condition can be set as appropriate (for example, it may be at least two times or three times).

  In addition, the AT game state termination possible condition is that a bell navigation has occurred at least once ("the number of bell navigation occurrences" is "1" or more), and a predetermined termination condition is met after the termination possible condition is established. When it is determined, the AT gaming state may be ended. The predetermined termination condition may be the above-described duration of the defined period, or may be activation of a bonus state. In addition, after the establishment of the end possible condition, the end lottery may be performed for each unit game in the AT gaming state, and winning of the end lottery may be set as a predetermined end condition, or the AT gaming state is performed before the end possible condition is established. When the end lottery is performed for each unit game and the end lottery is won, the end information indicating that is stored and if the end information is stored when the bell navigation is generated once, it is determined If the end information is not stored when the bell navigation occurs once, the predetermined end condition may be that the end information is stored. That is, the termination condition of the AT gaming state may apply various conditions as long as it is ensured that the player is given some benefit as the advantageous section (a minimum benefit is secured). it can.

  As described above, in the present embodiment, the normal gaming state, the ART gaming state advantageous to the player than the normal gaming state, the AT gaming state (ART transition) and the AT gaming state (ART non transition) are included. Then, when a specific condition is satisfied in the normal gaming state (for example, when winning a specific combination shown in FIGS. 33A and 33B), it is determined whether or not to shift to the ART gaming state, and the ART gaming state If it is decided to shift (for example, in the case of advantageous section shift winning and stock winning), it is decided to shift to AT gaming state (ART transition) prior to transition of ART gaming state, and ART gaming state If it is not decided to shift to (for example, in the case of winning the advantageous segment shift and not winning the stock), it is decided to shift to the AT gaming state (ART non-transition) It has become the jar.

  Here, the ART gaming state, the AT gaming state (ART transition), and the AT gaming state (ART non transition) are states in which information of stop operation advantageous to the player can be notified, and the AT gaming state (ART transition) The AT gaming state (ART non transition) can be ended when information of a stop operation which is advantageous to the player is notified a predetermined number of times (for example, once), and the AT gaming state (ART non transition) It is possible to decide to shift to the ART gaming state when the information on the stop operation which is advantageous to the player is not notified a predetermined number of times in a predetermined period (for example, during 32 games).

  Thus, regardless of whether or not it is decided to shift to the ART gaming state advantageous to the player, the ART in both the AT gaming state (ART transition) and the AT gaming state (ART non transition). It is possible to have a sense of expectation regarding the transition of the game state, and to appropriately manage each game state. Therefore, the fun of the game can be improved while appropriately managing the gaming state.

  Further, in the present embodiment, when it is determined to shift to the AT gaming state (ART transition), and when it is determined to shift to the AT gaming state (ART non transition), the AT continuation possible period is determined. The AT gaming state (ART transition) and the AT gaming state (ART non transition) are ended when the information about the stop operation which is advantageous for the player is notified a predetermined number of times, when the AT continuation possible period has elapsed. If the information on the stop operation which is advantageous to the player is not notified a predetermined number of times, the termination is not completed even if the AT continuation possible period has passed.

  This makes it possible for the player to obtain the minimum benefit in these gaming states while suppressing excessive benefits given in the AT gaming state (ART transition) and the AT gaming state (ART non transition). In addition, since it is possible to increase the possibility that another benefit is given in the AT gaming state (ART non-transition), it is possible to further improve the fun of the game.

  Further, in the present embodiment, in the AT gaming state (ART transition), the probability that information of stop operation advantageous to the player is notified more than a predetermined number of times (for example, twice or more) is AT gaming state (ART non transition In the above, the probability that the information of the stop operation which is advantageous to the player is notified more than a predetermined number of times is higher than the probability. That is, if information on the stop operation which is advantageous to the player is notified more than a predetermined number of times, the expectation of ART gaming state transition is enhanced.

  Thereby, the number of times the information of the stop operation which is advantageous to the player is informed while suppressing the gain given in the AT gaming state (ART transition) and the AT gaming state (ART non transitioning) becoming excessive. Can change the sense of expectation. Therefore, the fun of the game can be further improved while appropriately managing the gaming state.

  Further, in the present embodiment, when a special condition is satisfied in the AT gaming state (ART transition) (for example, when a bonus combination is won and a combination of symbols relating to the bonus combination is displayed), the bonus state is When the bonus state is ended, the game is shifted to the ART gaming state instead of returning to the AT gaming state (ART transition).

  In this way, after the end of the bonus state transitioned in the AT gaming state (ART transition), the player is made to transition to the ART gaming state more advantageous to give the impression that the more advantageous gaming state continues continuously be able to. Therefore, the fun of the game can be further improved while appropriately managing the gaming state.

  Further, in the present embodiment, when the ART gaming state, AT gaming state (ART transition) and AT gaming state (ART non transitioning) are performed, and when the gaming state is controlled to the bonus state in these gaming states, it is advantageous for the player. It is notified by lighting of a state indicator that it is a special game section.

  As a result, the player is shown to be in a series of advantageous sections, and even if a plurality of gaming states with different degrees of advantage constitute a series of advantageous sections, the player can find it Can be prevented.

  In the present embodiment, in the normal gaming state, when winning the advantageous section transition lottery, when winning the ART stock lottery at bonus winning (including bonus ART special lottery at bonus winning), or during the bonus ART stock lottery When winning, the lighting of the status display is started, and thereafter, the lighting of the status display continues in the bonus non-winning status, between flag states and bonus status in the advantageous section, and the status when the advantageous section ends Although lighting of the indicator is finished and turned off, the lighting timing of the status indicator is not limited to this. For example, when a bonus winning ART stock lottery (including a bonus winning special ART stock lottery) is won, the lighting of the status indicator may be started when the winning bonus combination is won (established). .

  Further, in the present embodiment, the bell navigation generation lottery is always performed when the player wins the pushing order small combination (pushing order bell) in the AT gaming state, but the method of the bell navigation generation lottery in the AT gaming state is this It is not limited to. For example, it may be possible to provide a non-lottery section in which no bell navigator generation / lottery is performed in the AT gaming state. In addition, although this non-lottery section is disadvantageous to the player in the sense that the pushing order is not notified, for example, as described above, in the AT gaming state (ART non transition), for a predetermined period (for example, 32 games) If there is no bell navigator, it is decided to shift to the ART gaming state, so if there is a non-lottery section, the possibility of shifting to the ART gaming state is increased. Therefore, it can be said that it is advantageous to the player from such a viewpoint. Also, from this point of view, it is not possible to provide a non-lottery section in the AT gaming state (art transition), but it is possible to provide a non-lottering section in the AT gaming state (art non transition). It can also be done.

  This is a method of providing a non-lottery section, for example, the type of AT gaming state (ART non-transition or ART transition) when winning an advantageous section transition lottery or when transitioning from normal gaming state to AT gaming state; The non-lottery section lottery is performed based on the internal winning combination (sub flag) or the like and the lottery value, and when it is determined that the non-lottery section is given, the non-lottery section is set in the shifted AT gaming state It can be done. In addition, for example, the same non-lottery section lottery is performed during the AT gaming state, and when it is determined that the non-lottery section is to be awarded, the non-lottery section is set during the AT gaming state. Can.

  At this time, for example, the AT gaming state (ART non-transition) can make the award determination probability higher than the AT gaming state (ART transition). Also, for example, one of the plurality of games determined in advance as the number of games of the non-lottery section (for example, 0 games (that is, non winning), 10 games, 20 games, 30 games, 32 games) The number of games can be determined. In addition, in the case of performing the non-lottery section lottery when winning the advantageous section transition lottery, for example, a part of internal winning combinations among the internal winning combinations targeted for the lottery of the advantageous section transition lottery (for example, And “chance eye B”), the random lot free section lottery can be performed. In this case, in some internal winning combinations (e.g., "opportunity B"), it is also possible to make sure that a non-lottery section is provided. In addition, when performing a non-lottery section lottery during the AT gaming state, for example, if the “number of bell navigation occurrences” is “0”, the non-lottery section lottery may be performed for each unit game. When a winning combination (for example, "common bell A") is won, a random selection section lottery may be performed.

<Playability during ART preparation>
Next, with reference to FIG. 37, the flow of ART ready game will be described. In the ART preparation state, when it becomes an inter-flag state and when it becomes a bonus state, basically the same lottery and processing as those described in the game characteristics during the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be performed (the same as that in FIG. 37), and in FIG. It is omitted.

  As shown in FIG. 37, when in the ART preparation state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  Also, when in the ART preparation state, ending state transition control is performed. As described above, in the present embodiment, an upper limit ("1500" as the advantageous segment duration) is provided to the number of games in which the series of advantageous segments can continue, and in the state immediately before the upper limit is reached A predetermined effect (ending effect) is provided to indicate that the section is about to end. Further, in the present embodiment, as a state in which a predetermined effect (ending effect) can be performed, the transition condition is controlled to either the “ending state 1” or the “ending state 2” which is different. In addition, about the detail of ending state transfer control, in order to demonstrate later using FIG.70 and FIG.100, description here is abbreviate | omitted.

  Further, when the player is in ART preparation state and is not in a bonus winning state, ART stock lottery is being performed during ART preparation when winning a specific part (specific small part and replay part) other than the bonus part. A drawing table to be referred to in the ART stock drawing during the ART preparation is not shown. In addition, when the bonus combination is won, ART stock lottery is performed at the time of bonus winning (see FIG. 36C).

  In addition, when the ART is in the preparation state and the bonus is not won, the procedure of the stop operation which is advantageous for the player is informed at the winning of the push order small part and the push order replay during that period (see FIG. reference). That is, when the player wins the push order small part, the information of the stop operation in which the player can obtain the most medals is informed, and when the push order replay is hit, the player is in an RT state advantageous to the player. The information of the stop operation which can shift or maintain the advantageous RT state is informed. Note that when in the ART preparation state and in the inter-flag state, the procedure of the stop operation advantageous to the player is informed only when a part of the pushing order small part is won (see FIG. 47 described later). The same applies to the ART gaming state and the CZ gaming state.

  In addition, in the advantageous section, when it is the inter-flag state, by performing the stop operation to avoid that the combination of the symbols pertaining to the bonus combination is intentionally arranged, the inter-flag state is maintained to avoid capture such as increasing medals The specification may be such that the notification of the stop operation procedure advantageous to the player is not performed at all. In addition, when it is considered as a winning probability of internal winning combination in which increase in medals can not be expected even if the inter-flag state is extended without aligning combinations of symbols relating to bonus roles, such as high possibility of losing in inter-flag state. In the state of the push order small part establishment game, notification of the procedure of the stop operation which is advantageous to the player may be performed.

  In the ART preparation state, winning order replay (more specifically, “F_RT3 transition _123” to “F_RT3 transition _321”) is won, and as a result of notification of information on stop operation, “RT3 transition lip” is won (established) When the state is shifted from the RT2 state to the RT3 state ("ART transition condition satisfied" in FIG. 37), the stored ART stock is released in accordance with the above-mentioned priority order. Then, according to the ART stock to be released, the game state is shifted to any one of ART 1 to ART 4 game state.

  In the present embodiment, in the ART preparation state, the player wins the push order small combination, and even though the information on the stop operation is informed, the “transition” is established, or the push order Replay is hit. Even when the information on the stop operation is notified, the “ART transition condition” is satisfied even when the “RT1 transition ripple” is satisfied. That is, when the player performs the stop operation without following the information of the notified stop operation, the ART gaming state is started even when the state is not shifted to the RT3 state.

  Further, in the present embodiment, in the ART preparation state, the player wins the transition role (more specifically, “F_ transition role A”, “F_ transition role B”, “F_ transition role C” or “F_ transition role D”). Also, when the winning combination is won (established) and shifted to the RT0 state, the "ART transition condition" is satisfied. Therefore, in the present embodiment, the player is required to perform a stop operation (more specifically, performing the stop operation at the timing of causing a drop) to avoid winning (establishment) of the transition combination at the winning of the transition combination. . From such a point of view, when winning the transition combination in the ART preparation state, ART gaming state and CZ gaming state, a combination of winning combination symbols (or a stop that can cause a drop) The timing of the operation) may be notified as information on the stop operation.

  In addition, if the combination of symbols of the transition combination is directly notified, there is a possibility that the player may aim, so only the indication indicating that the transition combination has been won is displayed, and the specific combination of the transition combinations is notified. You may not do it. Here, as an example of the suggestion display, a notification such as “!!!” that can be recognized as a condition to be noted by display of an image not directly connected to a specific symbol combination, lighting of a predetermined lamp, etc. It may be done. In the reel arrangement of the present embodiment (see FIG. 15), a white BAR pattern with good visibility is arranged on the cherry pattern as a pattern serving as a guide for aiming the cherry pattern of the left reel 3L. When the white BAR symbol is stopped so as to be stopped within the frame of the reel display window 4, the black BAR 2 symbol and the blank symbol are both arranged not to stop on the effective line, If a white BAR is aimed at the left reel 3L, it is possible to avoid winning of the transition part (see FIG. 21). Therefore, the indication may be a indication that suggests the color of the symbol to be pressed, such as displaying the above “!!!” in white.

  In the ART preparation state, when the "ART transition condition" described above is not established, the ART preparation state is continued, and the game in the bonus non-winning state of the ART preparation state is repeated. In addition, since the ART preparation state is basically a preparation state until the ART gaming state is changed to the RT3 state, the gaming state may not be defined. In this case, in the ART1 to ART4 gaming state, each control shown in FIG. 37 is performed in a period until the above-mentioned "ART transition condition" is established, and in the period after the establishment of "ART transition condition" 38, 39 and 42 to 44 may be performed.

<Playability during ART 1 gaming state>
Next, with reference to FIGS. 38 and 39, the flow of games in the ART1 gaming state will be described. 40 and 41 are diagrams showing an example of various tables referred to at least in the ART1 gaming state, and these data tables are stored in the main ROM 102. In the ART1 gaming state, when it becomes an inter-flag state and when it becomes a bonus state, basically the same lottery and processing as those described in the game characteristics during the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be carried out are the same as in the above), and in FIG. 38 and FIG. Description of is omitted.

  First, ART1 gaming state is roughly classified into ART1 promotion lottery state when there is at least one ART stock during ART1 gaming state, and ART1 normal state when ART stock is 0 during ART1 gaming state. Ru. FIG. 38 describes the flow of gaming in the ART1 normal state, and FIG. 39 describes the flow of gaming in the ART1 promoted lottery state.

  As shown in FIG. 38, when the ART 1 is in the normal state and the bonus is not won, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  Also, when in the ART 1 normal state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG.

  Also, when ART 1 is in the normal state and bonus is not won, BAR complete lip ("F_WBAR perfect A", "F_WBAR perfect B", "F_SBAR perfect A" or "F_SBAR perfect B") In the case, the BAR match lip sub flag conversion lottery is performed. Specifically, the BAR complete reply sub flag conversion lottery table shown in FIG. 40A is referred to, and the sub flag is “WBAR complete” or “SBAR based on the type of gaming state, the internal winning combination (sub flag), and the lottery value. It is determined whether to set "match" or "normal RIP A". When it is determined that the sub flag is "WBAR complete" or "SBAR complete", in the subsequent lottery in the unit game, the lottery is performed on the assumption that the sub flag is "WBAR complete" or "SBAR complete".

  Further, when the player is in the ART 1 normal state and in the bonus non-winning state, the ART 1 promoted lottery is performed when a specific combination other than the bonus combination (specific small combination and replay combination) is won. In the ART 1 promotion lottery, it is determined whether or not the currently running ART 1 gaming state is to be promoted to ART 2 to 4 gaming state. Specifically, with reference to the ART1 promoted lottery table shown in FIG. 40B, whether or not to promote the currently running ART1 gaming state based on the internal winning combination (sub-flag) and the lottery value, and promoted In the case of causing the game to be made, it is determined which gaming state of ART 2 to 4 gaming state to be promoted.

  In ART 1 normal state, when it is determined to be promoted to any gaming state of ART 2 to ART 4 gaming state by the ART 1 promotion lottery (in FIG. 38, “promoted lottery winning”), it is a promotion destination from the next game. Move to ART gaming state (any of ART2 to ART4). In this case, even if there is a remaining period of the ART1 continuation possible period, the remaining period is discarded (cleared), and again according to each gaming state in the ART gaming state of the promotion destination (any of ART2 to ART4) The initial value of the period is set (set).

  In ART 1 normal state, when it is not determined to be promoted to any of the gaming states of ART 2 to ART 4 gaming state by the ART 1 promotion lottery (in FIG. 38, “promoted lottery non winning”), ART 1 in ART 1 continues. Stock lottery is conducted. Specifically, the ART stock lottery table in ART 1 shown in FIG. 40C is referred to, and whether ART stock is given based on the navi mode, the internal winning combination (sub-flag), and the lottery value, and When ART stock is given, its type (ART1 to ART4) is determined. In addition, when the bonus combination is won, ART stock lottery is performed at the time of bonus winning (see FIG. 36C).

  In ART 1 normal state, if it is decided to give any ART stock of ART 1 to ART 4 by ART stock lottery in ART 1 (in FIG. 38, “ART stock win” in FIG. 38), ART 1 promotion lottery status from next game Migrate to On the other hand, when it is not determined to give any ART stock of ART 1 to ART 4 by ART stock lottery during ART 1 (in FIG. 38, “ART stock not won”), ART 1 normal state is continued.

  Further, when the ART 1 is in the normal state and the bonus is not won, the ART 1 continuation possible period (in the present embodiment, the number of times of the initial value is “30”) is updated every unit game. Specifically, “1” is subtracted from the number of games played during the ART1 continuation possible period, and subsequently, it is determined whether or not the ART1 continuation possible period has been digested (that is, the subtraction result has become “0”) . In addition, in the renewal of the ART1 continuation possible period, the number of times of the game is added 1 each at every unit game, subsequently, addition result reaches the number of times of the ART1 continuation possible period ("30") or not It may be determined whether the ART1 continuation possible period has been digested or not.

  As a result of ART1 continuation possible period renewal, when ART1 continuation possible period has not been digested (in Figure 38 “period undigested”), ART1 normal condition continues, the game in the bonus non winning condition of ART1 normal condition is It will be repeated. In addition, if ART1 continuity period has been digested and ART1 continuity period has been digested, and there is more than one ART stock (in FIG. 38, "period digestion stock"), ART stock One is released, and it shifts to the ART gaming state according to the released ART stock (any ART gaming state continues). In addition, when ART1 continuation possible period is not digested, and even when there is one or more of any ART stock, the advantageous section continuation period (the value of the advantageous section counter which will be described later) is “1500” games If it does, the ART1 normal state is subject to regulation (limiter is activated) and is forcibly terminated. In this case, since "ending state 1" or "ending state 2" is set, in FIG. 38, it is shown as "at the end of the ending state". The same applies to the ART preparation state and the ART2 to ART4 gaming states.

  Also, if ART1 continuity period is renewed and ART1 continuity period is digested, and there is no ART stock (in FIG. 38, “period digestion no stock”), then, , CZ migration lottery is performed. Specifically, the CZ shift lottery table shown in FIG. 40D is referred to, and how many units in the series of relevant advantageous sections have been controlled to the ART gaming state (that is, how many ART stocks are acquired and released) ("" Whether or not to shift to the CZ gaming state, and the type (CZ1 or CZ2) to shift to the CZ gaming state are determined based on the number of ARTs "and the lottery value. In the present embodiment, only one ART stock (more specifically, "ART 1") can be acquired in the series of the advantageous sections, and based on the ART stock, the ART gaming state (more specifically, ART 1 game). If only one unit of state is completed and finished (that is, if "the number of ARTs" is "first time"), the CZ gaming state must be shifted to ensure that the player's interest does not deteriorate It is supposed to be decided.

  In the ART1 normal state, when it is not determined that the CZ shift lottery moves to any of the CZ1 gaming state and the CZ2 gaming state (in FIG. 38, "promoted lottery non-winning"), the ART1 normal state is normally selected. Transition to the gaming state (ie, the advantageous section ends). In addition, in the ART1 normal state, when it is determined to shift to the CZ1 gaming state by CZ shift lottery (in FIG. 38, "CZ1 win"), the ART1 normal state is shifted to the CZ1 gaming state (ie, advantageous) The section will continue). In addition, in the ART1 normal state, when it is determined to shift to the CZ2 gaming state by the CZ shift lottery (in FIG. 38, "CZ2 win"), the ART1 normal state is shifted to the CZ2 gaming state (ie, advantageous) The section will continue).

  In addition, when the ART1 gaming state starts, if there is already one or more ART stock (for example, ART1), it is assumed that the ART stock has not been won in the ART1 gaming state, so that the game is started from the ART1 normal state. It is also possible to start the game from ART1 promotion lottery status as there are already one or more ART stocks. In addition, if there are a plurality of ART stocks having different priorities, the ART stock to be a target of the promoted lottery in the ART1 promoted lottery status may be an ART stock with a high priority (priority).

  As shown in FIG. 39, when in the ART1 promoted lottery state and in the bonus not won state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  Also, when in the ART1 promoted lottery state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG. In the ART1 promotion lottery state, the BAR complete flip sub flag conversion lottery, the ART1 promotion lottery, and the ART stock lottery in ART1 are performed so that the player's profit does not become excessive because ART stock has already won. Although not supposed to be, the invention is not limited to this, and part or all of the lottery may be performed.

  When the player is in the ART1 promotion lottery state and is in the bonus non-winning state, ART stock promotion lottery in ART1 is performed when a specific combination other than the bonus combination (a specific small combination and a replay role) is won. Specifically, the ART stock promotion lottery table in ART 1 shown in FIG. 41A is referred to, and among the granted ART stock, the type (ART 1 to ART 3) of the ART stock to be targeted and the internal winning combination (subflag) Whether the target ART stock is to be promoted or not, if it is to be promoted, to which ART stock, and if it is not to be promoted, to transition to a pseudo precursor state based on the lottery value and It is determined whether or not. When the target ART stock is ART 4, ART 4 is the most advantageous ART stock for the player, so that ART stock promotion lottery in ART 1 is not performed. However, also in this case, it may be determined whether or not to shift to the pseudo precursor state with a predetermined probability.

  If it is decided to promote ART stock by ART stock promotion lottery during ART 1 in ART 1 promotion lottery status (in FIG. 39, “promotion win”), it is not decided to promote ART stock but it is pseudo If it is determined that the transition to a positive precursor state is made (in FIG. 39, “promotion non-precedence precursor wins”), the promotion precursor period will Do. Specifically, based on whether or not it is decided to promote ART stock with reference to the promotion aura period lottery table shown in FIG. 41B (“promotion win” or “precursor win”) and the lottery value. The number of games per game is determined as the number of games during the promotion sign period. The method of determining the specific number of games is the same as that of the AT continuation possible period lottery. Further, in this promotion signatory period lottery, the promotion signatory period may be determined in consideration of the number of remaining games of the ART1 continuous available period. In this case, one game number equal to or less than the remaining number of games of the ART1 continuous available period may be determined as the promotion early term (ie, the promotion early term does not exceed the remaining term of the ART1 continuous available period I hope)

  On the other hand, if it was decided to promote ART stock by ART stock promotion lottery during ART1, and it was not decided to promote ART stock if the promotion sign period was already determined in the ART1 promotion lottery status. Even if it is decided to shift to the pseudo precursor state, the promotion precursor period is not newly determined (ie, the promotion precursor period determined once is not overwritten), but the promotion precursor is It is possible to promote ART stock if winning an ART stock promotion lottery during ART 1 during the period.

  Here, when in the ART1 promotion lottery state and in the bonus non-winning state, if the promotion precursor period is set, the promotion precursor period is updated for each unit game. Specifically, the number of games in the promotion precursor period is subtracted by one, and then it is determined whether the promotion precursor period has been digested (that is, whether the subtraction result has become "0"). In addition, in the renewal of the promotion sign period, the number of games is incremented by one for each unit game, and subsequently, whether the addition result reaches the number of games played in the promotion sign period (“30”) or not The determination may be made as to whether or not the promotion precursor period has been digested.

  As a result of renewal of the promotion precursor period, if the promotion precursor period is not digested (in FIG. 39, “period undigested”), and if the promotion precursor period is digested, ART stock in ART stock promotion lottery during ART 1 If the player has not won the promotion of (in FIG. 39, “Period to save and not promote”), the ART1 promotion lottery state continues, and the game in the ART1 promotion lottery state bonus non-winning state is repeated. In addition, if the promotion precursor period is digested as a result of renewal of the promotion precursor period and the ART stock promotion lottery in ART 1 wins the promotion of ART stock (in FIG. 39, "Period of Digestion Promotion"). The player releases one of the promoted ART stock, and shifts to an ART gaming state according to the released ART stock (any ART gaming state continues). In this case, even if there is a remaining period of the ART1 continuation possible period, the remaining period is discarded (cleared), and it is again according to each gaming state in the transition destination ART gaming state (any of ART 2 to ART 4) The initial value of the period is set (set).

  In the ART1 promotion lottery status, it is not determined to promote ART stock, nor is it determined to shift to the pseudo precursor condition (“promotion not winning precursor not winning” in FIG. 39). As in the ART 1 normal state, the ART 1 continuation possible period is updated every unit game. Here, since the ART1 continuation possible period is not updated during the promotion sign period, if it is decided that only the transition to the pseudo sign state is decided and the shift to the promotion sign period is made, then the ART 1 gaming state is substantially Is to be extended.

  Then, as a result of updating ART1 continuous period, if ART1 continuous period is not digested ("Period not completed" in FIG. 39), ART1 promoted lottery status continues, and bonus of ART1 promoted lottery status is not won The game in the state will be repeated. In addition, if ART1 duration is digested as a result of ART1 duration renewal ("Periodically digested" in Fig. 39), one ART stock is released according to the priority and released to ART stock. It shifts to the corresponding ART gaming state (any ART gaming state continues).

  In this embodiment, in the ART1 gaming state, when winning a bonus combination, in the ART1 normal state, in the ART1 promotion lottery state, when acquiring the ART stock of “ART1”, and in the ART1 promotion lottery state The content of lottery for ART stock lottery at the bonus winning is different from when ART stock of “ART 2” or more is acquired (in FIG. 36C, “ART 1 (without stock)” and “ART 1 (with stock respectively) : ART 1) "," ART 1 (stocks: ART 2 or more) "column).

  As described above, in the present embodiment, it has the normal gaming state and the ART gaming state that is more advantageous to the player than the normal gaming state, and determines, for example, whether or not to give ART stock in the ART1 gaming state. It is possible, if ART stock has been granted, and if certain conditions are met (for example, if a particular role shown in FIG. 41A is won), then promote the ART stock granted. Whether or not to promote ART stock, it is possible to decide to shift to the promotion sign period, ART stock is granted, and ART stock is In the case where it is decided to promote and transitioning to the promotion sign period, the promotion sign period ends even before the expiration of the ART1 continuation possible period When the, so as to continue the ART game state based on the new ART stock in accordance with whether the determination result to elevate ART stock.

  As a result, the determination as to whether or not the ART gaming state is to be continued can be made rich in variations, and it is possible to improve the interest regarding the continuation of the state advantageous to the player. In addition, on the other hand, it is possible to suppress an excessive gain given to the player and to suppress an excessive revenge on the player.

  Further, in the present embodiment, the ART1 continuable period is not updated during the promotion precursor period. As a result, for example, even if it is determined that only the transition to the promotion precursor period is made and transition to the promotion precursor period, the ART 1 gaming state is substantially extended, which is an advantage for the player Interest on the continuation of the

  Further, in this embodiment, it is possible to determine whether to promote ART stock even during the promotion sign period. As a result, it is possible to have an expectation for the promotion of ART stock even during the promotion period of promotion, so it is possible to further improve the interest concerning the continuation of the state advantageous to the player.

<Playability during ART2 gaming state>
Next, with reference to FIG. 42, the flow of the ART2 gaming state game will be described. In the ART2 gaming state, when it becomes an inter-flag state and when it is in the bonus state, basically the same lottery and processing as those described in the game characteristics during the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be performed (the same as that in FIG. 42), and in FIG. It is omitted.

  As shown in FIG. 42, in the ART 2 gaming state, at least one “ART 1” is awarded as ART stock at the start. Therefore, basically, the ART gaming state never ends in the ART 2 gaming state. However, at the above-mentioned "end state end time", all such ART stock and ART 2 continuation possible period are also destroyed (cleared), and ART gaming state is forcibly ended.

  Further, when in the ART 2 gaming state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  Also, when in the ART 2 gaming state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG.

  In addition, when it is ART2 game state, and bonus is not winning condition, BAR perfect lip ("F_WBAR perfect A", "F_WBAR perfect B", "F_SBAR perfect A" and "F_SBAR perfect B") is won. In the case, the BAR match lip sub flag conversion lottery is performed. In addition, since the BAR complete lip sub flag conversion lottery has already been described, the description here is omitted.

  Further, when the player is in ART 2 gaming state and in the bonus non-winning state, ART stock lottery in ART 2 is performed when a specific combination other than the bonus combination (specific small combination and replay combination) is won. Although illustration is omitted about a lottery table referred to in ART stock lottery during ART 2, for example, based on an internal winning combination (sub-flag) and a lottery value, whether ART stock is given or not If the ART stock is given, the type (ART 1 to ART 4) may be determined. Further, when the bonus combination is won, if the winning combination is “SBB” or “BB1”, a special ART stock lottery at the bonus winning time is performed (see FIG. 33D). However, even when winning in any of the bonus roles including other bonus roles in the ART 2 gaming state, ART stock lottery may be performed at the time of bonus winning as described with reference to FIG. 36C. . The winning probability in this case can be set as appropriate.

  In the ART2 gaming state, if it is decided to grant ART stock by ART stock lottery in ART2, then ART stock decided to be added is added.

  Here, the ART2 gaming state includes two states: an ART2 normal state in which the ART2 continuous available period is updated and a stopped state in which the ART2 continuous available period is not updated. In the period stop state, since the ART 2 continuation possible period is not updated, basically the ART 2 gaming state does not end. That is, the period stop state is a period in which the ART 2 gaming state is substantially extended.

  In the ART 2 normal state and in the bonus non-winning state, when a specific combination other than the bonus combination (a specific small combination and a replay combination) is won, a period suspension transition lottery is performed. Although illustration is omitted about the lottery table referred to in this period stop state transition lottery, whether to shift to the period stop state based on the internal winning combination (sub-flag) and the lottery value, for example It is sufficient if the decision is made.

  In the ART2 normal state, when it is determined to shift to the period stop state by the period stop state shift lottery (in FIG. 42, “transition winning” in FIG. 42), the transition to the period stop state is made from the next game.

  On the other hand, when the period is stopped and the bonus is not won, the period stop end lottery is performed for each unit game. Although illustration is omitted about the lottery table referred to in this period stop state end lottery, for example, based on the number of games in the period stop state, the internal winning combination (sub-flag), and the lottery value. It may be determined whether to end the period stop state. In the period stop state, when it is determined that the period stop state is to be ended by the period stop state end lottery (in FIG. 42, “end winning” in FIG. 42), the transition to the ART 2 normal state is made from the next game. In addition, when it is not determined to end the period stop state by the period stop state end lottery (in FIG. 42, “end not won”), the period stop state is continued.

  Further, when the ART 2 is in the normal state and the bonus is not won, the ART 2 continuation possible period (the number of times of the initial value is "30" in this embodiment) is updated for each unit game. Specifically, “1” is subtracted from the number of games in the ART2 continuation possible period, and subsequently, it is determined whether or not the ART2 continuation possible period is digested (that is, the subtraction result becomes “0”) or not . In addition, in renewal of the ART2 continuation possible period, the number of times of the game is added 1 at a time every unit game, subsequently, addition result reaches the number of times of the ART2 continuation possible period ("30") or not It may be determined whether the ART2 continuation possible period has been digested or not.

  As a result of updating ART2 duration, if ART2 duration is not digested ("Period not yet completed" in Fig. 42), ART2 normal status continues, and the game in ART2 normal status bonus non-winning status is It will be repeated. In addition, when ART2 duration is digested as a result of ART2 duration renewal ("digestion in period" in Fig. 42), one ART stock is released and ART gaming state according to ART stock released. Transition to (any ART gaming state continues).

<Playability during ART3 gaming state>
Next, with reference to FIG. 43, the flow of gaming in the ART3 gaming state will be described. In the ART3 gaming state, when it becomes an inter-flag state and when it becomes a bonus state, basically the same lottery and processing as those described in the game characteristics during the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be performed (the same as that in FIG. 43), and in FIG. It is omitted.

  As shown in FIG. 43, in the ART 3 gaming state, the probability ("continuity rate (loop rate)") to be used for the lottery whether or not the ART 3 gaming state is to be continued at the start is determined by the lottery. Here, in the present embodiment, for example, three types of continuation rates of “50%”, “66%” and “80%” are provided, and one continuation rate is determined by the continuation rate lottery. For example, when the continuation rate "50%" is determined, at the lottery timing to determine whether or not to continue the ART3 gaming state, the total expected value for determining to continue the ART3 gaming state (ART3 described later The total winning probability) during the period of continuous lottery is 50%. In addition, illustration is abbreviate | omitted about the lottery table referred in this continuation rate lottery.

  In addition, in the ART 3 gaming state, at least one "ART 1" is awarded as ART stock at the start of the game. Therefore, basically, the ART gaming state never ends in the ART3 gaming state. However, at the above-mentioned "end state end", such ART stock, the first half period, the second half period and the grant period as ART 3 continuation possible period are all destroyed (cleared) and ART gaming state is compulsorily forced It is finished.

  Further, when in the ART 3 gaming state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  In addition, when in the ART 3 gaming state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG.

  Here, in the ART 3 gaming state, continuous lottery of the ART 3 gaming state is performed based on the above-mentioned continuation rate, and the length of the period is also variable, and the ART 3 game based on the above continuation rate The continuous lottery of the state is performed, but the length of the period includes three states of the second half period in which the fluctuation does not change, and the grant period of ART stock grant and the ART stock can be additionally granted. That is, roughly classified, it includes a first half period and a second half period in which it is determined whether to continue the ART3 gaming state, and a grant period in which it is determined whether to grant ART stock.

  In the first half period, at the beginning of the first half period, the number of games in the first half period is set to “5” times in the first half period when transitioning to ART 3 gaming state first. Further, when winning the ART 3 continuous lottery described later and the number of games in the first half period is set again, any one of "10" times, "20" times, and "30" times as the number of games in the first half period The number of games is determined by lottery, and the number of games in the determined first half period is set. In addition, illustration is abbreviate | omitted about the lottery table referred in this first half period lottery.

  In the first half period, when the bonus is not won, ART 3 continuous lottery is performed for each unit game. In addition, although illustration is abbreviate | omitted about the lottery table referred in this ART3 continuation lottery, whether ART3 gaming state is continued based on the lottery value according to the continuation rate mentioned above, and continued In this case, it may be determined whether to shift to the grant period. In the ART 3 continuous lottery, when it is decided to continue the ART 3 gaming state, information indicating that is stored, and further, when it is decided to shift to the grant period, information indicating that is also stored Be done. If it is determined that the ART3 gaming state is to be continued at least during the first half or the second half of the ART3 gaming state, the ART3 continuous lottery is not performed during the period after the ART3 gaming state, and the continued new In the ART 3 gaming state, ART 3 continuous lottery is performed again.

  In the first half period, when the bonus is not won, the first half period is updated every unit game. The same method as that in the update of the above-described continuable period may be appropriately adopted for the update of the first half period and the later half period described later. As a result of the first half period update, when the first half period is not digested, the first half period continues, and the game in the bonus non-winning state in the first half period is repeated. Also, if the first half period is digested as a result of the first half period update, transition to the second half period is made.

  In the second half period, at the start of the second half period, the number of games in the second half period is set to "6" times. Also, similar to the first half period, ART 3 continuous lottery is performed for each unit game. Further, as in the first half period, the second half period is updated every unit game. As a result of updating the second half period, when the second half period is not digested (“period not yet completed” in FIG. 43), the second half period continues and the game in the bonus non-winning condition in the second half period is repeated. Also, as a result of updating the second half period, the second half period is digested, and if it is not decided to continue the ART3 gaming state (in FIG. 43, “period digestion not continued win”), one ART stock is released. , It shifts to the ART gaming state according to the released ART stock (any ART gaming state continues).

  Further, as a result of updating the second half period, the second half period is digested, and it is determined that the ART 3 gaming state is to be continued, and it is also determined to shift to the grant period (in FIG. Transition to the grant period for “digestion continual winning + award winning”).

  When it is a grant period and a bonus not won condition, ART stock lottery in ART 3 is performed every unit game. Although illustration is omitted about the lottery table referred to in ART stock lottery during ART 3, for example, whether ART stock is given based on an internal winning combination (sub-flag) and lottery value If the ART stock is given, the type (ART 1 to ART 4) may be determined. In addition, in any period of ART 3 gaming state, when the bonus combination is won, if the winning combination is "SBB" or "BB1", a special ART stock lottery at the bonus winning time is performed (FIG. 33D) reference). However, even when winning in any of the bonus roles including other bonus roles in the ART 3 gaming state, ART stock lottery may be performed at the time of bonus winning as described with reference to FIG. 36C. . The winning probability in this case can be set as appropriate.

  If it is decided to grant ART stock by ART stock lottery during ART 3 during the grant period ("ART stock win" in FIG. 43), then ART stock decided to be added is added, Continue the grant period. On the other hand, when it is not determined to give ART stock by ART stock lottery in ART 3 (in FIG. 43, “ART stock not won”), the giving period is ended and the period is shifted to the first half period.

  As a result of updating the second half period, the second half period is digested, and it is determined that the ART 3 gaming state is to be continued, and it is not determined to shift to the grant period (in FIG. Only when the winning "), and when the grant period is over, it will be shifted to the first half period (ART3 gaming state will be played from the beginning again). The first half period lottery for determining the number of games in the first half period may be performed at this time, or may be performed when the first half period starts.

<Playability during ART4 gaming state>
Next, with reference to FIG. 44, the flow of the ART4 gaming state game will be described. In the ART4 gaming state, when it becomes an inter-flag state and when it is in the bonus state, basically the same lottery and processing as those described in the game characteristics in the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be performed (the same as that in FIG. 44), and in FIG. It is omitted.

  As shown in FIG. 44, in the ART 4 gaming state, at least one “ART 1” is awarded as ART stock at the start. Therefore, basically, in the ART4 gaming state, the ART gaming state never ends. However, at the above-mentioned "at the end of the ending state", all such ART stock and the ART4 continuation possible period are also destroyed (cleared), and the ART gaming state is forcibly ended.

  Further, when in the ART 4 gaming state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  In addition, when in the ART 4 gaming state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG.

  In addition, when it is ART 4 gaming state and bonus is not won, BAR complete rep ("F_WBAR complete A", "F_WBAR complete B", "F_SBAR complete A" and "F_SBAR complete B") is won. In the case, the BAR match lip sub flag conversion lottery is performed. In addition, since the BAR complete lip sub flag conversion lottery has already been described, the description here is omitted.

  When the player is in the ART 4 gaming state and in the bonus non-winning state, ART stock lottery in ART 4 is performed when a specific combination other than the bonus combination (specific small combination and replay combination) is won. Although illustration is omitted about a lottery table referred to in ART stock lottery during ART 4, for example, whether ART stock is given based on an internal winning combination (sub-flag) and lottery value If the ART stock is given, the type (ART 1 to ART 4) may be determined. Further, when the bonus combination is won, if the winning combination is “SBB” or “BB1”, a special ART stock lottery at the bonus winning time is performed (see FIG. 33D). However, even when winning in any of the bonus roles including other bonus roles in the ART 4 gaming state, ART stock lottery may be performed at the time of bonus winning as described with reference to FIG. 36C. . The winning probability in this case can be set as appropriate.

  In the ART 4 gaming state, if it is decided to grant ART stock by ART stock lottery during ART 4, the ART stock decided to be added is added. In addition, in the ART4 gaming state, the continuation possible period is longer than the other ART gaming states (ART1 to ART3 gaming state), and the probability that it is decided to give ART stock by ART stock lottery in ART4 is also other Is favored over ART stock lottery in ART gaming state (ART1 to ART3 gaming state). Therefore, the ART4 gaming state is the most advantageous ART gaming state.

  In addition, when in the ART 4 gaming state and in the bonus non-winning state, the ART 4 continuation possible period (in the present embodiment, the number of games of the initial value is “40”) is updated for each unit game. Specifically, “1” is subtracted from the number of games in the ART4 continuation possible period, and subsequently, it is determined whether or not the ART4 continuation possible period is digested (that is, whether the subtraction result is “0”) or not . In addition, in renewal of the ART4 continuation possible period, the number of times of the game is added 1 each at every unit game, subsequently, addition result reaches the number of times of the ART4 continuation possible period ("40") or not It may be determined whether the ART4 continuation possible period has been digested or not.

  As a result of ART4 continuation possible period renewal, when ART4 continuation possible period is not digested (in Figure 44 “period undigested”), ART4 game state continues, the game in the bonus non winning state of ART4 game state is It will be repeated. In addition, when ART4 duration is digested as a result of ART4 duration renewal ("digestion in period" in Fig. 44), one ART stock is released, and ART gaming state according to ART stock released. Transition to (any ART gaming state continues).

<Playability during CZ1 gaming state>
Next, with reference to FIG. 45, the flow of gaming in the CZ1 gaming state will be described. It should be noted that in the CZ1 gaming state, when it becomes an inter-flag state and when it is in the bonus state, basically the same lottery and processing as those described in the game characteristics during the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be performed (the same as that in the case where it is performed), and in FIG. It is omitted.

  As shown in FIG. 45, in the CZ1 gaming state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  Also, when in the CZ1 gaming state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG.

  In addition, in the CZ1 gaming state, when the bonus is not won, BAR complete rep ("F_WBAR complete A", "F_WBAR complete B", "F_SBAR complete A" and "F_SBAR complete B") was won In the case, the BAR match lip sub flag conversion lottery is performed. In addition, since the BAR complete lip sub flag conversion lottery has already been described, the description here is omitted.

  When the player is in the CZ1 gaming state and in the bonus non-winning state, ART stock lottery in CZ1 is performed when a specific combination other than the bonus combination (specific small combination and replay combination) is won. Although illustration is omitted about the lottery table referred to in ART stock lottery during CZ1, whether ART stock is given or not based on, for example, an internal winning combination (sub-flag) and lottery value. If the ART stock is given, the type (ART 1 to ART 4) may be determined. Further, when the bonus combination is won, if the winning combination is “SBB” or “BB1”, a special ART stock lottery at the bonus winning time is performed (see FIG. 33D). However, also when winning in any of the bonus roles including the other bonus roles in the CZ1 gaming state, the ART stock lottery may be performed at the time of the bonus winning as described with reference to FIG. 36C. . The winning probability in this case can be set as appropriate.

  In addition, when in the CZ1 gaming state and in the bonus non-winning state, the CZ1 continuation possible period (in this embodiment, the number of times of the initial value is "5") is updated for each unit game. Specifically, the number of games in the CZ1 possible period is decremented by one, and subsequently it is determined whether the CZ1 possible period has been digested (that is, whether the subtraction result has become zero) or not . In addition, in renewal of CZ1 continuation possible period, the game frequency is added 1 at a time every unit game, subsequently, addition result reaches the game frequency of CZ1 continuation possible period ("5") whether or not Whether or not the CZ1 possible period has been digested may be determined by the determination of

  As a result of CZ1 continuation possible period renewal, when CZ1 continuation possible period is not digested (in Figure 45, “period undigested”), CZ1 gaming state continues, the game in bonus non winning condition of CZ1 gaming state is It will be repeated. In addition, as a result of updating the CZ1 possible period, when the CZ1 possible period is digested and there is one or more of any ART stock (ie, when ART stock is given in the CZ1 gaming state) ( In FIG. 45, one ART stock is released in "Periodically digested ART stock win", and transition is made to the ART gaming state according to the released ART stock (CZ1 gaming state is returned to any ART gaming state ). Also, as a result of updating the CZ1 duration, if the CZ1 duration is digested and there is no ART stock (i.e., if the ART stock is not given in the CZ1 gaming state) ( In FIG. 45, in the "period digested ART stock not won", the CZ1 gaming state is shifted to the normal gaming state (the advantageous section ends and the normal section is shifted).

<Playability during CZ2 gaming state>
Next, with reference to FIG. 46, the flow of gaming in the CZ2 gaming state will be described. It should be noted that in the CZ2 gaming state, when it becomes an inter-flag state and when it is in the bonus state, basically the same lottery and processing as those described in the game characteristics in the AT gaming state are performed (AT gaming In the explanation of the gameplay in the state, the same lottery and processing as those described in the gameplay in the normal game state are assumed to be performed (the same as that in the case where the lottery is performed). It is omitted.

  As shown in FIG. 46, when in the CZ 2 gaming state and in the bonus non-winning state, the navigation mode lottery is performed for each unit game. In addition, since the navigation mode lottery has already been described, the description here is omitted.

  Also, when in the CZ 2 gaming state, ending state transition control is performed. As described above, since the details of the ending state transition control will be described later with reference to FIG. 70 and FIG.

  In addition, in the CZ2 gaming state, when the bonus is not won, BAR complete rep ("F_WBAR complete A", "F_WBAR complete B", "F_SBAR complete A" and "F_SBAR complete B") was won In the case, the BAR match lip sub flag conversion lottery is performed. In addition, since the BAR complete lip sub flag conversion lottery has already been described, the description here is omitted.

  When the player is in the CZ2 gaming state and in the bonus non-winning state, ART stock lottery in CZ2 is performed when a specific combination other than the bonus combination (specific small combination and replay combination) is won. Although illustration is omitted about the lottery table referred to in ART stock lottery during CZ2, whether or not ART stock is given based on, for example, an internal winning combination (sub-flag) and lottery value. If the ART stock is given, the type (ART 1 to ART 4) may be determined. Further, when the bonus combination is won, if the winning combination is “SBB” or “BB1”, a special ART stock lottery at the bonus winning time is performed (see FIG. 33D). However, also when winning in any of the bonus roles including the other bonus roles in the CZ2 gaming state, the ART stock lottery may be performed at the time of the bonus winning as described with reference to FIG. 36C. . The winning probability in this case can be set as appropriate.

  In addition, when in the CZ 2 gaming state and in the bonus non-winning state, the CZ 2 continuation possible period (in the present embodiment, the number of games of the initial value is “10”) is updated for each unit game. Specifically, the number of games in the CZ2 continuous available period is decremented by one, and then it is determined whether the CZ2 continuous available period has been digested (that is, whether the subtraction result has become 0). . In addition, in the update of the CZ2 possible continuation period, the number of times of the game is added one by one every unit game, and subsequently, the addition result reaches the number of times of the CZ2 possible continuation period ("10") or not It may be determined whether or not the CZ2 possible period has been digested by the determination of

  As a result of updating the CZ2 possible period, if the CZ2 possible period is not digested ("Period not completed" in FIG. 46), the CZ2 gaming state continues, and the game in the bonus non-winning state of the CZ2 gaming state is It will be repeated. In addition, as a result of updating the CZ2 possible period, when the CZ2 possible period is digested and there is one or more of any ART stock (that is, when ART stock is given in the CZ2 gaming state) ( In FIG. 46, one ART stock is released in "Periodically digested ART stock win", and transition is made to the ART gaming state according to the released ART stock (CZ2 gaming state is returned to any ART gaming state ). In addition, as a result of updating the CZ2 duration, if the CZ2 duration is digested and there is no ART stock (i.e., if the ART stock is not given in the CZ2 gaming state) ( In FIG. 46, “Periodically digested ART stock not won” is given “ART1” as ART stock. Therefore, basically, the CZ2 gaming state always returns to the ART gaming state, and the advantageous section never ends. However, at the above-mentioned "end state end time", all such ART stock and CZ2 continuation possible period are also destroyed (cleared), and as a result of the CZ2 game state being forcedly ended, the advantageous section ends.

  In this embodiment, in the lottery using the various data tables described above, the lottery for the lottery which is extracted from the predetermined numerical range (0 to 255) by the random number registers 2 to 7 of the random number circuit 110. Internally, by sequentially subtracting a random number value (rendering effect random number value) with a specified lottery value, and determining whether the result of the subtraction becomes negative (whether a so-called “scale” has occurred). Lottery is done. That is, although the winning / not winning is determined by subtracting the lottery value from the random value for lottery, the method of lottery is not limited to this, and the lottery value is added to the extracted random value for lottery, and the addition result is Whether or not 256 has been exceeded (whether so-called “overflow” has occurred) may be determined to determine winning / non-winning.

<Informing function by control on the main side>
In the conventional pachislot machine, it is determined by control on the sub (sub control board 72) side whether to notify information (stopping order etc.) of the stop operation which is advantageous to the player. However, since the presence or absence of this notification affects the player's profit (so-called, balls), in recent years, control by the main (main control board 71) side which manages the player's profit is required. . Therefore, in the pachislot 1 of the present embodiment, as described above, the information display 6 controlled on the main side is provided with an instruction monitor (not shown) for notifying information on the stop operation, and the control on the main side is performed. A function is provided to notify information on the reel stop operation.

  Here, FIG. 47 shows the correspondence between each gaming state controlled on the main side, the internal winning combination, and the navigation data in the pachislot 1 of the present embodiment. The navigation data “1” to “7” shown in FIG. 47 indicate numerical values displayed on the instruction monitor, and also indicate notification contents of information on stop operation. Also, navigation data “0” shown in FIG. 47 indicates that information on stop operation is not notified.

  In the normal gaming state, even when any internal winning combination shown in FIG. 47 is determined, navigation data "0" is set, and information on the stop operation is not notified. In the present embodiment, when the navigation data “0” is set, no numerical value is displayed on the instruction monitor in the present embodiment, but the present invention is not limited to this. For example, the numerical value “0” is displayed on the instruction monitor You may do so.

  In the AT gaming state (bonus non winning state), when the internal winning combination of "F_ left bell A" to "F_ left bell C" is determined, if the result of the bell navigation occurrence lottery is a winning, navigation data "7" is set. The navigation data "7" corresponds to "strike 1" and "strike 2" (that is, performing the first stop operation on the left reel 3L). On the other hand, if the result of the bell navigation generation lottery is not winning, navigation data "0" is set.

  In the AT gaming state (bonus non winning state), when the internal winning combination of any of "F_ medium bell A" to "F_ middle bell C" is determined, if the result of the bell navigation generation lottery is a winning, navigation data "8" is set. The navigation data "8" corresponds to "strike order 3" and "strike order 4" (that is, performing the first stop operation on the middle reel 3C). On the other hand, if the result of the bell navigation generation lottery is not winning, navigation data "0" is set.

  In the AT gaming state (bonus non winning state), when the internal winning combination of any of "F_ right bell A" to "F_ right bell C" is determined, if the result of the bell navigation occurrence lottery is a winning, navigation data "9" is set. The navigation data "9" corresponds to "strike 5" and "strike 6" (that is, performing the first stop operation on the right reel 3R). On the other hand, if the result of the bell navigation generation lottery is not winning, navigation data "0" is set.

  In the AT gaming state (RT4: state between flags), when the internal winning combination "F_left bell A" is determined, the navigation data "7" is set, and the internal winning combination "F_inner bell A" is determined. When the navigation data "8" is set, and when the internal winning combination "F_ right bell A" is determined, the navigation data "9" is set, and the other push order small combination is determined as the internal winning combination In the case, navigation data "0" is set. Also, in the bonus state, navigation data "0" is set basically even when any internal winning combination is determined.

  When the internal winning combination "F_RT2 transition _123" or "F_RT3 transition _123" is determined in the ART preparation state, ART gaming state and CZ gaming state (all except the bonus non-winning state and the RT0 state), the navigation data " 1 is set. The navigation data “1” corresponds to “strike order 1” (that is, performing the stop operation in the order of “left, middle, right”).

  When the internal winning combination "F_RT2 transition_132" or "F_RT3 transition_132" is determined in the ART preparation state, ART gaming state and CZ gaming state (all except the bonus non-winning state and the RT0 state), the navigation data " 2 "is set. The navigation data "2" corresponds to "batning order 2" (ie, performing the stop operation in the order of "left, right, middle").

  If the internal winning combination "F_RT2 transition_213" or "F_RT3 transition_213" is determined in the ART preparation state, ART gaming state and CZ gaming state (all except the bonus non-winning state and the RT0 state), the navigation data " 3 "is set. The navigation data "3" corresponds to "strike order 3" (ie, performing the stop operation in the order of "middle, left, right").

  When the internal winning combination "F_RT2 transition_231" or "F_RT3 transition_231" is determined in the ART preparation state, ART gaming state and CZ gaming state (all except the bonus non-winning state and the RT0 state), the navigation data " 4 "is set. The navigation data "4" corresponds to "batning order 4" (that is, performing the stop operation in the order of "middle, right, left").

  When the internal winning combination "F_RT2 transition_312" or "F_RT3 transition_312" is determined in the ART preparation state, ART gaming state and CZ gaming state (all except the bonus non-winning state and the RT0 state), the navigation data " 5 "is set. The navigation data “5” corresponds to “strike order 5” (ie, performing the stop operation in the order of “right, left, middle”).

  If the internal winning combination "F_RT2 transition_321" or "F_RT3 transition_321" is determined in the ART preparation state, ART gaming state and CZ gaming state (all except the bonus non-winning state and the RT0 state), the navigation data " 6 "is set. The navigation data “6” corresponds to “striking order 6” (ie, performing the stop operation in the order of “right, middle, left”).

  In the ART preparation state, the ART gaming state and the CZ gaming state (all except the bonus non-winning state and the RT0 state), any of "F_RT3 maintenance _1 st" and "F_ left bell A" to "F_ left bell C" When the internal winning combination is determined, navigation data "7" is set.

  In the ART preparation state, the ART gaming state and the CZ gaming state (all except the bonus non-earning state and the RT0 state), any one of "F_RT3 maintenance _2nd" and "F_Bell A" to "F_Bell C" When the internal winning combination is determined, navigation data "8" is set.

  In the ART preparation state, the ART gaming state and the CZ gaming state (all except the bonus non-winning state and the RT0 state), any one of “F_RT3 maintenance _3 rd” and “F_right bell A” to “F_right bell C” When the internal winning combination is determined, navigation data "9" is set.

  In the ART preparation state, ART gaming state and CZ gaming state (all are RT4: state between flags), the navigation data “7” is set when the internal winning combination “F_left bell A” is determined, and the internal winning The navigation data "8" is set when the role "F_BELL A" is determined, and the navigation data "9" is set when the internal winning combination "F_BELL A" is determined, and the other push order When the small winning combination is determined as the internal winning combination, navigation data "0" is set. Also, in the bonus state, navigation data "0" is set basically even when any internal winning combination is determined. Also, similar navigation data can be set in the AT gaming state.

  As described above, in the present embodiment, the main (main control board 71) side notifies the information on the stop operation of the reel by displaying numerical values of "1" to "9" on the instruction monitor. Further, the numerical values "1" to "9" displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

  Although the numbers “1” to “9” reported on the main side (instruction monitor) uniquely correspond to the contents of the stop operation to be reported, all the players clearly based on the figures. It is not always possible to grasp the contents of the notification. For example, the player may not be able to grasp the contents of the notification only by displaying the numerical value "6" on the instruction monitor on the main side.

  Therefore, in the pachislot machine 1 of the present embodiment, information on the stop operation of the stop button is notified on the sub side as well as the notification on the main side. Specifically, using the display device 11 (projector mechanism 211 and display unit 212) controlled on the sub side, notification of information related to the stop operation is performed by the control on the sub side.

  For example, when notifying the pressing order of performing the first stop operation on the left reel 3L, the main side displays the numerical value "7" on the instruction monitor, and the sub side displays the left reel in the display screen of the display device 11. The numerical value "1" is displayed above 3L to notify that the left reel 3L is the target of the first stop operation. In addition, when informing the pushing order “medium, left, right”, the main side displays the numerical value “3” on the instruction monitor, and the sub side indicates the numerical value above the middle reel 3C in the display screen of the display device 11. “1” is displayed, the numerical value “2” is displayed above the left reel 3L, and the numerical value “3” is displayed above the right reel 3R. This display shows the order of “middle, left, right” Informing that it is.

  In addition, the timing which alert | reports by the main side can be set to arbitrary timing if it is a period of one game which alert | reports at least. For example, the notification on the main side may be performed at the timing when the player's start operation is detected (received), or the notification on the main side may be performed at the start of rotation of the reel, or the first stop operation to third Notification on the main side may be performed at the timing at which one of the stop operations is detected. On the other hand, it is preferable that the timing which alert | reports by the sub side is a timing before at least 1st stop operation. Therefore, in the pachislot 1 of the present embodiment, in a game in which information on the stop operation during the advantageous section is notified, the reel stop control process (see FIG. 58 described later) after the internal lottery process (see S204 in FIG. 58 described later). Send a command including this navigation data (or equivalent information) as a parameter from the main (main control board 71) side to the sub (sub control board 72) side before S213 You should do it. In this case, parameters of navigation data (or information equivalent to this) may be included in an existing command (for example, start command or reel rotation start command), or navigation data (or equivalent thereof) Information) may be sent. As a result, it becomes possible to notify information on the stop operation in both the instruction monitor on the main side and the display device 11 on the sub side.

  Further, as another method, in a game in which information on stop operation during the advantageous section is notified, the internal winning combination number (for example, FIG. 16 to FIG. 18) can be specified as information that can identify the internal winning combination without transmitting navigation data. Information corresponding to "No." may be transmitted from the main side to the sub side. For example, when “F_left bell A” is established, information corresponding to “45” may be transmitted. According to this method, it is possible to reduce the amount of data to be transmitted since the sub side can specify the procedure of the stop operation which is advantageous to the player without sending the sub flag and the navigation data. Further, in the case of this method, since the sub-side does not need to receive the sub-flag, the sub-flag generation processing itself may not be performed on the main side during the advantageous section. However, if you want to increase the information that can be used for judgment on the sub side and efficiently proceed with debugging etc., generate a sub flag even during the advantageous section, and from the main side all internal winning combination number, sub flag, and navigation data It may be sent to the sub side.

<Description of operation of main control circuit>
Next, the contents of various processing executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS.

[Process at power on (reset interrupt)]
First, power-on (reset interrupt) processing of the pachislot 1 performed by the control of the main CPU 101 will be described with reference to FIG. FIG. 48 is a flow chart showing a procedure of power-on (reset interrupt) processing. When the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 has been started, the reset processing is performed by the microprocessor 91 at the time of power on (reset interrupt) shown in FIG. After being output to the “XSRST” terminal and subjected to a delay operation in the security mode, execution is performed based on an interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 performs initialization processing of the timer circuit 113 (PTC) (S1). In this process, the main CPU 101 performs initial setting of the timer circuit 113. Specifically, the main CPU 101 sets a division ratio in a timer prescaler register (not shown), performs interrupt enable setting in a timer control register (not shown), and the like. Set the initial count value.

  Next, the main CPU 101 executes initialization processing of the first serial communication circuit 114 (SCU1) for communication between the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. An initialization process is performed (S2). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S3). Next, the main CPU 101 performs a write test on the main RAM 103 (S4).

  Next, the main CPU 101 determines whether or not the writing to the main RAM 103 has been normally performed as a result of the writing test (S5).

  When the main CPU 101 determines in S5 that writing to the main RAM 103 has not been normally performed (when the determination in S5 is NO), the main CPU 101 performs the processing of S13 described later. On the other hand, when the main CPU 101 determines that the writing to the main RAM 103 has been normally performed in S5 (when the determination in S5 is YES), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. To obtain (S6).

  Next, the main CPU 101 determines, based on the acquired state of the timer control register, whether the current state is the occurrence timing of the interrupt processing (S7). Specifically, the main CPU 101 determines whether or not 1.1172 ms has elapsed since the start of the timer count, based on the acquired state of the timer control register.

  In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. Thereafter, the status of the timer circuit 113 can be acquired by reading information of the timer control register (not shown). Then, in the present embodiment, a bit (determination bit) capable of determining (referring) whether or not the current state is the occurrence timing of the interrupt processing (whether the timer is in the interrupt state) in the timer control register ) Is provided.

  Therefore, in the process of S6, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S7, the main CPU 101 turns on / off the determination bit in the timer control register. By referring to “1” / “0”), it is determined whether or not the current state is the occurrence timing of the interrupt processing. When 1.1172 ms has elapsed since the timer circuit 113 starts counting (if the count value of the timer circuit 113 is 0), the determination bit is turned on.

  When the main CPU 101 determines in S7 that the current state is not the occurrence timing of the interrupt processing (when the determination in S7 is NO), the main CPU 101 returns the processing to the processing of S6 and repeats the processing of S6 and subsequent steps.

  On the other hand, when the main CPU 101 determines in S7 that the current state is the occurrence timing of the interrupt processing (when the determination in S7 is YES), the main CPU 101 sets a command transmission start timer (S8). The command transmission start timer is a timer for managing an activation delay period described later (refer to FIG. 98 described later), and a period from when the command transmission start timer is set to 0 until the main control circuit 90 ( Command data is not transmitted from the main control board 71) to the sub control circuit 200 (sub control board 72) (see FIG. 93 described later). As a result, when the pachi slot 1 is powered on, the time required for the start control of the sub CPU 201 (the time until the command can be received) is secured. That is, by setting the command transmission start timer, transmission of communication data (command data) by communication data transmission processing is delayed for a period corresponding to this. In the present embodiment, “21801” (21801 × 1.1172 ms = about 24.3561 seconds) is set as the value of the command transmission start timer in S8. However, the value of the command transmission start timer can be appropriately changed according to the specifications of the sub control circuit 200 mounted at the same time.

  The command transmission start timer is a software timer allocated by 2 bytes in the gaming RAM area of the main RAM 103, and is arranged at an address which is not erased in a setting change confirmation process (see FIG. 50) described later.

  Next, the main CPU 101 performs a thumb check process (outside of specification) (S9). In this process, the main CPU 101 performs a thumb check process on the main RAM 103, but the work of this process is performed in an extra-specified work area (see FIG. 11C) in the main RAM 103. Also, the program used in the sum check process is stored in the non-prescribed area in the main ROM 102 (see FIG. 11B). The details of the thumb check process will be described later with reference to FIGS. 56 and 57 described later.

  After the process of S9, the main CPU 101 determines whether the setting key switch 54 is in the on state (S10).

  When the main CPU 101 determines in S10 that the setting key type switch 54 is in the on state (when the determination in S10 is YES), the main CPU 101 performs the processing of S15 described later. On the other hand, when the main CPU 101 determines that the setting key type switch 54 is not in the on state in S10 (when S10 is NO determination), the main CPU 101 determines a thumb check based on the result of the thumb check process of S9. It is determined whether the result is normal (S11).

  When the main CPU 101 determines in S11 that the sum check determination result is not normal (when the determination in S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S11 that the sum check determination result is normal (when the determination in S11 is YES), the main CPU 101 performs a game recovery process (S12). In this process, the main CPU 101 performs a process of returning the state of the game to the state before the detection of power interruption. The details of the game return processing will be described later with reference to FIG. 49 described later.

  If S5 or S11 is NO, the main CPU 101 displays a character string “88” indicating occurrence of an error on the information display 6 (7-segment LED display) (S13). Thereafter, the main CPU 101 repeats the WDT clear process (S14).

  Here, the process returns to step S10 again, and if the determination in step S10 is YES, the main CPU 101 performs setting change confirmation processing (S15). In this processing, the main CPU 101 mainly performs generation and storage processing of a setting change command at the start of the setting change. The details of the setting change confirmation process will be described later with reference to FIG. 50 described later.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address of "RAM abnormal or setting change start" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the game is started from the start address. The information up to the final address of the RAM area is erased (cleared). Then, after the processing of S16, the main CPU 101 starts main processing (see FIG. 58 described later) described later.

[Game return processing]
Next, with reference to FIG. 49, the game recovery processing performed in S12 in the power-on (reset interrupt) processing (see FIG. 48) will be described. FIG. 49 is a flowchart showing the procedure of the game return process.

  First, the main CPU 101 sets the stack pointer at power-off to the stack pointer (SP) (S21). Next, the main CPU 101 determines whether the command transmission start timer has counted up (S22). When the main CPU 101 determines in S22 that the command transmission start timer has not counted up (when the determination in S22 is NO), the main CPU 101 repeats the processing of S22.

  On the other hand, when the main CPU 101 determines in S22 that the command transmission start timer has counted up (when the determination in S22 is YES), the main CPU 101 determines the on-edge data before one interrupt processing of the input port and The set on-edge data is cleared (turned off) (S23). Next, the main CPU 101 reads backup data of the output port from an output port backup storage area (not shown) of the main RAM 103, and sets the backup data in the output port (S24). Next, the main CPU 101 reads the data of the input port, and stores the data in the data storage area (input port storage area 1 and input port storage area 2) before the current and one interrupt processing of the input port (S25) .

  Next, the main CPU 101 sets the address of the rotation control data storage area (S26). Next, the main CPU 101 sets the number of reels to be checked ("3" in the present embodiment) (S27).

  Next, the main CPU 101 acquires reel control management information of the predetermined reel (data related to fluctuation control of display row at the time of power failure) based on the set address of the spinning drum control data storage area (S28). The reel control management information (variation control management information of the display row) is information related to the control state (rotational state) of each reel, and is backed up and stored at power-off.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation state during constant speed waiting or constant speed while the reel is accelerating (S29).

  When the main CPU 101 determines in S29 that the condition of S29 is not satisfied (when the determination in S29 is NO), the main CPU 101 performs the processing of S32 described later. On the other hand, when the main CPU 101 determines in S29 that the condition of S29 is satisfied (when the determination in S29 is YES), the main CPU 101 clears the rotation control data (reel control management information) (S30). By this process, after the game is recovered, the rotation control of the reel is started from the acceleration process. Next, the main CPU 101 sets an operation timing value of the reel (execution start timing “1” of the drum control data) (S31). When “1” is set to the operation timing of the reel, the main CPU 101 accelerates the rotation control of the reel because the excitation change timing comes within the reel control processing (see S903 in FIG. 92 described later). Start from

  After the processing of S31 or when S29 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S32). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S33).

  When the main CPU 101 determines in S33 that the value of the number of reels after subtraction is not “0” (when the determination in S33 is NO), the main CPU 101 changes the reels to be checked, and the process proceeds to S28. Then, the processing after S28 is repeated.

  On the other hand, when the main CPU 101 determines in S33 that the value of the number of reels after subtraction is "0" (when the determination in S33 is YES), the main CPU 101 performs a RAM initialization process (S34). In this process, the main CPU 101 sets the "power return" address in the gaming RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the final address of the game RAM area is determined from the start address. Clear (clear) the information up to the address.

  Next, the main CPU 101 restores the data of all the registers saved at the time of the power failure detection to all the registers (S35). Then, after the processing of S35, the main CPU 101 ends the game recovery processing, and returns the processing to the processing at the time of the interruption detection.

  In the present embodiment, the game return processing is performed as described above. In the game recovery process of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management at power recovery. Information is acquired, and processing required to start re-rotation of the reels is also performed (see the processing in S26 to S33). Therefore, in the present embodiment, even when returning from the power interruption during the rotation of the spinning drum, the reel re-rotation control can be stably performed, and the player does not feel uncomfortable.

[Setting change confirmation process]
Next, with reference to FIG. 50, the setting change confirmation process performed in S15 in the process (see FIG. 48) at the time of power on (reset interrupt) will be described. FIG. 50 is a flowchart of the setting change confirmation process. If the setting key type switch 54 is turned on after the game machine is turned on (that is, in the case of "setting confirmation" for confirming the current setting value), the setting change confirmation is made from S44 described later. The process may be started.

  First, the main CPU 101 performs initialization processing of the non-specified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs a 1-interrupt wait process (S42). In this process, when the command transmission start timer is counting up, a non-operation command is transmitted to the sub control circuit 200 by a communication data transmission process (see FIG. 93) described later. If the command transmission start timer does not count up, no command is transmitted to the sub control circuit 200. Therefore, when the command transmission start timer does not count up, this process is omitted. May be

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address of "RAM abnormal or setting change start" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the game is started from the start address. The information up to the final address of the RAM area is erased (cleared).

  Next, the main CPU 101 determines whether the setting key switch 54 is in the on state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for setting the setting value (settings 1 to 6) of the pachislot 1 and is set when the setting key is turned on. The key type switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the on state (S44 is NO determination), the main CPU 101 ends the setting change confirmation processing, and powers on the processing (reset interrupt ) Processing (see FIG. 48) is transferred to the processing of S16. On the other hand, when the main CPU 101 determines in step S44 that the setting key type switch 54 is in the on state (when the determination in step S44 is YES), the main CPU 101 performs medal acceptance prohibition processing (S45). By this processing, the solenoid of the selector 66 (see FIG. 5) is not driven, and the inserted medal is discharged from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets setting change start or setting check start information (005H: first value) in the L register, and performs generation and storage processing of a setting change command (setting change / setting check start) (S46) . In this process, the main CPU 101 generates setting change command data (first command data) to be transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and the command data is generated. It is stored in a communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 51 described later. The setting change command (setting change / setting confirmation start) stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG.

  Next, the main CPU 101 sets the error count relay to the on state (S47). Next, the main CPU 101 performs 7-segment display setting processing of setting values (S48). By this processing, the current setting value can be displayed by the 7-segment LED in the information display 6.

  Next, the main CPU 101 determines which of setting change and setting confirmation has been performed (S49). When the main CPU 101 determines in S49 that the setting change has not been performed (setting confirmation has been performed) (when the determination in S49 is NO), the main CPU 101 performs the processing of S54 described later.

  On the other hand, when the main CPU 101 determines in S49 that the setting change has been performed (setting confirmation has not been performed) (if the determination in S49 is YES), the main CPU 101 determines whether the reset switch 76 is on It is determined whether or not it is (S50).

  In S50, when the main CPU 101 determines that the reset switch 76 is in the on state (when the determination in S50 is YES), the main CPU 101 updates the setting value (S51). That is, every time the reset switch 76 is operated, the main CPU 101 sequentially updates the set value within the range of “1” to “6”. After the processing of S51, the main CPU 101 returns the processing to the processing of S48, and repeats the processing of S48 and thereafter. On the other hand, when the main CPU 101 determines that the reset switch 76 is not in the on state in S50 (when the determination in S50 is NO), the main CPU 101 determines whether the start switch 79 is in the on state (S52) .

  In S52, when the main CPU 101 determines that the start switch 79 is not in the on state (when the determination in S52 is NO), the main CPU 101 returns the process to the process of S48 and repeats the processes after S48. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is on (when the determination in S52 is YES), the main CPU 101 sets the setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  If the determination in S49 is NO or after the processing in S53, the main CPU 101 determines whether the setting key switch 54 is in the off state (S54).

  When the main CPU 101 determines in S54 that the setting key type switch 54 is not in the off state (S54 is NO), the main CPU 101 repeats the processing of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (when the determination in S54 is YES), the main CPU 101 determines which of the setting change and the setting confirmation has been performed. (S55).

  When the main CPU 101 determines in S55 that the setting change has not been performed (setting confirmation has been performed) (when the determination in S55 is NO), the main CPU 101 performs the processing of S57 described later. On the other hand, when the main CPU 101 determines in S55 that the setting change has been performed (setting confirmation has not been performed) (if S55 is YES), the main CPU 101 performs a RAM initialization process (S56). . In this process, the main CPU 101 sets an address (following the setting value storage area) (not shown) in the game RAM area of the main RAM 103 shown in FIG. 11C to the start address of the initialization start. It sets and erases (clears) the information from the top address to the final address of the gaming RAM area.

  After the processing of S56 or when S55 is NO, the main CPU 101 sets the information on the end of setting change or setting confirmation end (004H: second value) in the L register, and the setting change command (setting change / setting confirmation end) ) Is generated (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process, and the command data is generated. It is stored in a communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 51 described later. The setting change command (setting change / setting confirmation end) stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 in the power-on (reset interrupt) processing (see FIG. 48).

[Setting change command generation and storage processing]
Next, the setting change command generation and storage process performed in S46 and S57 in the setting change check process (see FIG. 50) will be described with reference to FIG. FIG. 51 is a flowchart of the setting change command generation and storage process.

  First, the main CPU 101 sets information of set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets the information of the RT state in the C register (S62). Next, the main CPU 101 sets command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 performs communication data storage processing (S64). In this process, main CPU 101 performs the information set in each register in S61 to S63 and the information set in L register in S46 or S58 (see FIG. 50) (setting change start / setting change end / setting end as setting status / Setting confirmation start / setting confirmation end) is used to generate setting change command data, and the generated command data is stored in the communication data storage area. The details of the communication data storage process will be described later with reference to FIG. 52 described later.

  After the processing of S64, the main CPU 101 ends the setting change command generation and storage processing. When the setting change command generation and storage process performed in S46 in the setting change confirmation process (see FIG. 50) is ended, the main CPU 101 performs the process of the setting change confirmation process (see FIG. 50) after the process of S64. Transfer to the process of S47. When the setting change command generation and storage process performed in S57 in the setting change confirmation process (see FIG. 50) is ended, the main CPU 101 ends the setting change command generation and storage process after the process of S64 and performs setting. The change confirmation process (see FIG. 50) also ends.

[Communication data storage process]
Next, with reference to FIG. 52, for example, the communication data storage process performed in S64 in the setting change command generation and storage process (see FIG. 51) will be described. The communication data storage process is executed not only at the time of generation of the setting change command but also at the time of other command generation. FIG. 52 is a flowchart of the communication data storage process.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area in the main RAM 103 as parameters 1 and 2 of the communication command, respectively (S72).

  Next, the main CPU 101 stores the data set in the D register and the E register in the communication data temporary storage area in the main RAM 103 as parameters 3 and 4 of the communication command, respectively (S73). Next, the main CPU 101 stores the data set in the B register and C register in the communication data temporary storage area in the main RAM 103 as data of parameter 5 and RT state of the communication command, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

  After the process of S76, the main CPU 101 determines whether there is a space in the communication data storage area in the main RAM 103 (S77). In the present embodiment, a maximum of nine command data can be stored in the communication data storage area.

  In S77, when the main CPU 101 determines that there is no space in the communication data storage area (in the case of NO determination in S77), the main CPU 101 ends the communication data storage processing and, for example, the setting change command generation storage processing ( Also refer to FIG. 51).

  On the other hand, when the main CPU 101 determines in S77 that there is a vacancy in the communication data storage area (when the determination in S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the processing of S71 to S76 described above. Each data is stored (registered) in the communication data storage area as communication data (command data) (S78).

  Next, the main CPU 101 performs communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating a communication data pointer indicating a storage address of communication data in the communication data storage area. The details of the communication data pointer update process will be described later with reference to FIG. 53 described later.

  Then, after the process of S79, the main CPU 101 ends the communication data storage process, and also ends, for example, the setting change command generation and storage process (see FIG. 51).

  As described above, in the present embodiment, when creating communication data (command data) of one packet (8 bytes), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a command data creation method, data stored in each register at the time of command generation is stored as it is in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including an unused parameter is created, the value of the unused parameter becomes an indeterminate value at each creation time. This makes it difficult to analyze the communication data and can prevent fraudulent acts such as goth, and there is no need to add unnecessary goto processing, so the program of the main control circuit 90 by adding goto processing is necessary. The pressure on the volume can be suppressed.

[Communication data pointer update process]
Next, with reference to FIG. 53, the communication data pointer update process performed in S79 in the communication data storage process (see FIG. 52) will be described. FIG. 53 is a flowchart of the communication data pointer update process.

  First, the main CPU 101 acquires the value of the communication data pointer currently set (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer by one packet (8 bytes) (S82). In this process, when the value of the communication data pointer after update is equal to or more than the upper limit size of the communication data storage area, the main CPU 101 sets the value of the communication data pointer after update to “0”. As a result, all command data stored in the communication data storage area are invalidated (the same state as the discarded state).

  In the present embodiment, the amount of data (one packet) transmitted in one transmission operation is eight bytes. That is, in the present embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of nine command data can be stored in the communication data storage area, the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). Therefore, in the present embodiment, the range of the communication data pointer is "0" to "71", and the value of the communication data pointer after update (when the communication data pointer is updated +8) is "71 (in the process of S82). If the upper limit value is exceeded, set the value of the communication data pointer after updating to "0" (set the address of the communication data storage destination back to the top address), and store the communication data. Invalidate all command data stored in the area (make it the same state as the discarded state). If the value of the communication data pointer is set to “0”, the command data is stored from the start address of the communication data storage area when storing command data in the communication data storage area next time, so it is stored before that. The new command data will overwrite the new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds “71 (upper limit value)”.

  Then, after the processing of S82, the main CPU 101 ends the communication data pointer update processing and also ends the communication data storage processing (see FIG. 52).

[Power-off (external) processing]
Next, power-off (external) processing of the pachislot 1 performed by the control of the main CPU 101 will be described with reference to FIG. FIG. 54 is a flowchart of the power-off (external) process. In the power-off (external) processing shown in FIG. 54, when the power management circuit 93 detects a drop in power supply voltage supplied to the microprocessor 91 (power-off), the power-off detection signal is output to the microprocessor 91. , And is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads data set in the power failure detection port (S92).

  Next, the main CPU 101 determines whether the power failure detection port is in the on state (S93).

  When the main CPU 101 determines in S93 that the power failure detection port is not in the on state (when the determination in S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 ends the power-off (external) processing. Note that these processes performed when S 93 is NO determination correspond to the process of the measure against the instantaneous blackout that occurs when the power management circuit 93 momentarily detects the power failure.

  On the other hand, when the main CPU 101 determines that the power failure detection port is in the on state in S93 (when the determination in S93 is YES), the main CPU 101 sets the medal insertion prohibition and sets the hopper device 51 to stop. (S95).

  Next, the main CPU 101 stores the value of the stack pointer (SP) currently set in the stack area of the gaming RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 executes checksum processing of the main RAM 103 (S97). Note that this process is performed in an extra-specified work area (see FIG. 11C) in the main RAM 103. Also, the program used in the checksum generation process is stored in the non-prescribed area in the main ROM 102 (see FIG. 11B). The details of the checksum generation process will be described later with reference to FIG. 55 described later.

  Next, the main CPU 101 sets the access prohibition to the main RAM 103 (S98). Then, after the process of S98, an infinite loop process is performed until the power is stopped (until the power supply voltage reaches a voltage at which the main CPU 101 can not operate).

[Checksum generation processing (out of specification)]
Next, with reference to FIG. 55, the checksum generation process performed in S97 in the power-off (external) process (see FIG. 54) will be described. FIG. 55 is a flowchart showing the procedure of the checksum generation process.

  First, the main CPU 101 stores the current value of the stack pointer (SP) (in-use address of the stack area of the gaming RAM area) in the non-regulation stack area of the non-regulation RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the extra stack area to the stack pointer (S102). Next, the main CPU 101 sets the upper address value (F0H) of the RAM address (the address of the non-specified stack area) in the Q register (S103). Next, the main CPU 101 sets a power failure occurrence flag (S104).

  Next, the main CPU 101 sets the calculation start address of the sum value in the gaming RAM area to the stack pointer, and the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2" in the sum calculation counter It sets (S105). The sum calculation counter is a counter for determining an end trigger of the sum value calculation and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation processing of the game RAM area of the main RAM 103 is ended.

  Next, the main CPU 101 clears the HL register to 0 (sets the value "0") (S106). By this processing, the initial value "0" of the sum value is set.

  Next, the main CPU 101 executes an instruction code called "POP instruction", and sets the data (storage value) of a 2-byte area from the address of the storage area of the main RAM 103 set in the stack pointer (SP) to the DE register. Read out (S107).

  When the "POP" instruction is executed, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded to the lower register of the pair register and specified by the stack pointer The data (memory content) stored in the 1-byte area of the address obtained by updating the address by 1 is loaded into the upper register of the pair register. Also, when the “POP” instruction is executed, address update processing (processing to add “2” of address) is performed to the address set in the stack pointer (SP) by 2 bytes.

  Therefore, in the process of S107, the data (memory content) stored at the address specified by the stack pointer is loaded into the E register, and is stored at the address obtained by adding "1" to the address specified by the stack pointer. Data (memory contents) are loaded into the D register.

  After the process of S107, the main CPU 101 performs a process of calculating a sum value (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

  Next, the main CPU 101 subtracts one from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether the value of the sum calculation counter after the update is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination in S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the process of S107 and subsequent steps. That is, the processing of S107 to S110 is repeated until the sum value calculation processing of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (when the determination in S110 is YES), the main CPU 101 determines in the DE register the non-specified RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-specified sum count value is set in the sum calculation counter (S111). The nonstandard-use sum count value is the number of bytes of the nonstandard-use storage area. Therefore, if the sum calculation counter set in S111 becomes “0”, the sum value calculation process of the non-specified RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 is completed.

  Next, the main CPU 101 reads out data (stored value) of an area of 1 byte from the address of the non-specified RAM area set in the DE register to the A register (S112).

  Next, the main CPU 101 performs a process of calculating a sum value (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

  Next, the main CPU 101 adds one to the address stored in the DE register and subtracts one from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether the value of the sum calculation counter after the update is “0” (S115).

  In S115, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination in S115 is NO), the main CPU 101 returns the process to the process of S112 and repeats the processes after S112. That is, the process of S112 to S115 is repeated until the process of adding the sum value of the non-specified RAM area of the main RAM 103 to the sum value of the gaming RAM area is completed.

  On the other hand, when the main CPU 101 determines in S115 that the value of the sum calculation counter is "0" (when the determination in S115 is YES), the main CPU 101 generates a power failure when the value stored in the HL register is interrupted. Are stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the nonstandard stack area at S101 in the stack pointer (S117). Then, after the process of S117, the main CPU 101 ends the checksum generation process, and shifts the process to the process of S98 in the power-off (external) process (see FIG. 54).

[Sum check process (out of specification)]
Next, with reference to FIG. 56 and FIG. 57, the sum check process performed in S9 in the power-on process (see FIG. 48) will be described. 56 and 57 are flowcharts showing the procedure of the thumb check process.

  First, the main CPU 101 stores the current value of the stack pointer (SP) in the non-specified stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets a value obtained by dividing the number of bytes of the sum value calculation target storage area by “2” in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining an end trigger of the sum value calculation (subtraction process of the sum value), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this processing, the checksum (initial value before subtraction) generated at the time of power interruption is stored in the HL register.

  Next, the main CPU 101 executes the “POP” instruction, and reads out 2-byte data (stored value) (stored value) from the address of the storage area of the main RAM 103 set in the stack pointer (SP) into the DE register (S124) . At this time, data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register by execution of the "POP" instruction, and the address specified by the stack pointer is Data (memory contents) stored in the 1-byte area of the 1-updated address is loaded into the D register. Also, when the "POP" instruction is executed, address update processing (processing to add 2 addresses) of 2 bytes is performed on the address set in the stack pointer (SP).

  Next, the main CPU 101 performs calculation (subtraction) processing of the sum value (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial value of the sum value or the sum value after the previous subtraction processing), and the subtraction is performed. Store the value as a sum value in the HL register.

  Next, the main CPU 101 subtracts one from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether the value of the sum calculation counter after the update is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination in S127 is NO), the main CPU 101 returns the process to the process of S124 and repeats the processes after S124. That is, the processing of S124 to S127 is repeated until the sum value subtraction processing is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is “0” (when the determination in S127 is YES), the main CPU 101 determines in the DE register the non-specified RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-specified sum count value is set in the sum calculation counter (S128). Note that the non-specified sum count value is the number of bytes of the non-specified RAM area.

  Next, the main CPU 101 reads out data (stored value) of an area of 1 byte from the address of the non-specified RAM area set in the DE register into the A register (S129).

  Next, the main CPU 101 performs calculation (subtraction) processing of the sum value (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value.

  Next, the main CPU 101 adds one to the address stored in the DE register and subtracts one from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the value of the sum calculation counter after the update is “0” (S132).

  In S132, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination of S132 is NO), the main CPU 101 returns the process to the process of S129 and repeats the processes after S129. That is, the processing of S129 to S132 is repeated until the subtraction processing of the sum value is completed over the entire area of the non-specified RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is "0" (when the determination in S132 is YES), the main CPU 101 sets "sum error" in the determination result of the thumb check process. (S133). Next, the main CPU 101 determines whether the calculated sum value is “0” (S134).

  In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether the sum value is “0”. In the present embodiment, the sum value is “0” when the value of the sum calculation counter set in S128 becomes “0”, that is, when the subtraction process of the sum value is completed over the entire area of the main RAM 103. In this case, the zero flag of the flag register F is set to "1", and when the sum value is not "0", the zero flag of the flag register F is set to "0". Therefore, when the zero flag of the flag register F is set to “1 (on state)” at the time of the process of S134, the main CPU 101 determines that the sum value is “0”.

  When the main CPU 101 determines in S134 that the calculated sum value is not “0” (when the determination in S134 is NO), the main CPU 101 performs the processing of S139 described later. On the other hand, when the main CPU 101 determines in S134 that the calculated sum value is "0" (when the determination in S134 is YES), the main CPU 101 sets "power failure abnormality" in the determination result (S135). ).

  Next, the main CPU 101 acquires a power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power-off occurrence flag is in the non-power-off state (off state) (S137).

  In S137, when the main CPU 101 determines that the power interruption occurrence flag is in the state of no power interruption (when the determination in S137 is YES), the main CPU 101 performs the processing of S139 described later. On the other hand, when the main CPU 101 determines in S137 that the power interruption occurrence flag is not in the state of no power interruption (when the determination in S137 is NO), the main CPU 101 sets "normal" in the determination result (S138).

  After the process of S138, if S134 is NO or if S137 is YES, the main CPU 101 stores the determination result in the sum check determination result, and clears (turns off) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the nonstandard stack area at S121 in the stack pointer (S140). Then, after the process of S140, the main CPU 101 ends the sum check process, and shifts the process to the process of S10 of the power-on process (see FIG. 48).

[Pachislot main processing by control of main CPU]
Next, with reference to FIG. 58, the main processing (main operation processing) of the pachi slot 1 executed by the control of the main CPU 101 will be described. FIG. 58 is a flowchart showing the procedure of the main processing (hereinafter referred to as the main flow).

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address of “at the end of one game” in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and from the start address to the game RAM area. Clear (clear) the information up to the final address. Note that the storage area of this range is, for example, a storage area that requires data deletion for each unit game (game) such as an internal winning combination storing area and a display combination storing area.

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this process, the main CPU 101 performs an input check process and the like of each medal sensor (see FIG. 5), the start switch 79 and the like. The details of the medal acceptance / start check process will be described later with reference to FIGS. 59 and 60 described later.

  Next, the main CPU 101 performs random number value acquisition processing (S203). In this process, the main CPU 101 selects an internal winning combination random number value (0 to 65535: a value of the random number register 0 of the random number circuit 110 which becomes a hard latch random number) or a random number value for effect used in various lottery related to game characteristics 0 to 65535: values of the random number register 1 of the random number circuit 110 to be soft latch random numbers, 0 to 255: values of the random number registers 2 to 7 of the random number circuit 110 to be soft latch random numbers, etc. The random number value is stored in a random value storage area (not shown) provided in the main RAM 103. The details of the random value acquisition process will be described later with reference to FIG. 65 described later.

  Next, the main CPU 101 performs internal lottery processing (S204). In this processing, the main CPU 101 performs internal winning combination determination processing by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 66 described later.

  Next, the main CPU 101 performs symbol setting processing (S205). In this process, for example, the main CPU 101 generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag storage area. Etc. The details of the symbol setting process will be described later with reference to FIG. 67 described later.

  Next, the main CPU 101 performs start command generation and storage processing (S206). In this process, the main CPU 101 generates data of a start command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The start command is configured to include parameters (such as sub flags) for specifying the internal winning combination and the like.

  Next, the main CPU 101 performs second interface board control processing (S207). Note that the second interface board control process is executed in the non-specified work area of the main RAM 103. In this process, the main CPU 101 performs, for example, a process for outputting a test signal or the like related to the push order navigation determined by the main control board 71 via the second interface board 302 for a test machine.

  Next, the main CPU 101 performs control processing by state at the time of game start (S208). In this process, the main CPU 101 mainly performs each process at the start of the game according to the game state and the like. In addition, the details of the game start time state control process will be described later with reference to FIG. 69 described later.

  Next, the main CPU 101 performs reel stop initialization processing (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (not shown) and acquires the drawing priority order table selection table number, the drawing priority order table number, and the stop table number based on the internal winning combination and the gaming state. And the process of storing "3" in the stop button non-operation counter.

  Next, the main CPU 101 performs reel rotation start processing (S210). In this process, the main CPU 101 requests the start of rotation of all the reels. Then, when the start of rotation of all the reels is requested, the driving of three stepping motors (not shown) is performed by an interrupt process (see FIG. 92 described later) which is executed in a fixed cycle (1.1172 msec). The rotation of the left reel 3L, the middle reel 3C and the right reel 3R is started under control. Then, each reel is controlled to accelerate until its rotational speed reaches a constant speed, and thereafter, it is controlled to maintain the constant speed.

  Next, the main CPU 101 performs reel rotation start command generation and storage processing (S211). In this process, the main CPU 101 generates data of a reel rotation start command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The reel rotation start command is configured to include a parameter indicating that the reel rotation start operation has been started.

  Next, the main CPU 101 performs a drawing priority storage process (S212). In this process, the main CPU 101 acquires the pull-in priority data and stores it in the pull-in priority data storage area. The details of the leading priority storage process will be described later with reference to FIG. 75 described later.

  Next, the main CPU 101 performs reel stop control processing (S213). In this process, the main CPU 101 performs control to stop the rotation of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C and the right stop button 17R are pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 80 described later.

  Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores data of the symbol code storage area (see FIG. 30) in the winning operation flag storage area (see FIG. 25). Further, in this processing, the main CPU 101 determines whether or not the display combination is displayed on the activated line, and sets the number of medals to be paid out based on the determination result. The details of the winning search process will be described later with reference to FIG. 81 described later.

  Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 combines the hit request flag (internal winning combination) and the winning operation flag (display combination), and determines the presence or absence of an illegal hit error based on the combination result. The details of the illegal hit check process will be described later with reference to FIG. 82 described later. Further, as long as each reel is stopped without occurrence of an erroneous winning by the reel stop control process (see FIG. 80 described later), the illegal hit check process can be omitted from the viewpoint of control burden reduction.

  Next, the main CPU 101 performs winning check and medal payout processing (S216). In this process, the main CPU 101 performs a process of generating a winning operation command. Further, in this processing, the main CPU 101 performs driving of the hopper device 51 and updating of the number of credits based on the number of payouts of the display combination determined in S214, and performs medal payout processing. The details of the winning check and medal payout processing will be described later with reference to FIG. 83 described later.

  Next, the main CPU 101 performs BB check processing (S217). In this process, the main CPU 101 controls the activation and termination of the bonus state. The details of the BB check process will be described later with reference to FIG. 85 described later.

  Next, the main CPU 101 performs RT check processing (S218). In this process, the main CPU 101 performs transition control of the RT state based on the symbol combination stopped and displayed on the activated line. The details of the RT check process will be described later with reference to FIG. 86 described later.

  Next, the main CPU 101 performs a game-by-game state control process (S219). In this process, the main CPU 101 mainly performs each process at the end of the game according to the game state and the like. In addition, the details of the game end state state control process will be described later with reference to FIG. 87 described later. Then, after the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal acceptance and start check processing]
Next, with reference to FIG. 59 and FIG. 60, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 58) will be described. 59 and 60 are flowcharts showing the procedure of the medal acceptance / start check process.

  First, the main CPU 101 determines whether the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is “1” or more, the main CPU 101 determines that there is an automatic insertion request. Further, the automatic insertion medal counter is data for identifying whether or not a display combination relating to replay (replay) is established in the previous unit game. When the display combination relating to replay is established, medals for the number inserted in the previous unit game are automatically inserted into the automatic insertion medal counter.

  In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when the determination in S221 is YES), the main CPU 101 performs the processing of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not "0" (when the determination in S221 is NO), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a process of generating and storing a medal insertion command, an LED lighting control process of the number of inserted medals, and the like. The details of the medal insertion process will be described later with reference to FIG. 61 described later.

  Next, the main CPU 101 subtracts the value of the automatic insertion medal counter (S223). In this process, the main CPU 101 may subtract the value of the automatic insertion medal counter at one time (for example, “3”) or may subtract “1” at a time. Next, it is determined whether the value of the automatically inserted medal counter after subtraction is "0" (S224).

  In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not “0” (when the determination in S224 is NO), the main CPU 101 returns the process to the process of S222 and repeats the processes after S222.

  On the other hand, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" in S224 (when S224 is a YES determination), or when S221 is a YES determination, the main CPU 101 stores the medal assistance storage. A storage switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals, based on the on / off state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 performs medal input state check processing (S226). Next, the main CPU 101 determines whether or not the medal can be inserted, based on the result of the medal input state check process (S227).

  When the main CPU 101 determines that the medal can not be inserted in S227 (when the determination in S227 is NO), the main CPU 101 performs the processing of S231 described later.

  On the other hand, when the main CPU 101 determines that the medal can be inserted in S227 (when the determination in S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, for example, the main CPU 101 determines whether the medal has passed normally based on the medal sensor input state, or credits the medal when medal insertion is performed beyond the prescribed number. Perform processing etc. The details of the medal insertion check process will be described later with reference to FIGS. 62 and 63 described later.

  Next, the main CPU 101 determines, based on the result of the medal insertion check process, whether the medal insertion or credit is possible (S229).

  In S229, when the main CPU 101 determines that medals can be inserted or credited (in the case of YES in S229), the main CPU 101 performs the processing of S231 described later. On the other hand, when the main CPU 101 determines in S229 that the medal insertion or credit is not possible (in the case of NO determination in S229), the main CPU 101 performs medal acceptance prohibition processing (S230). By this processing, the solenoid of the selector 66 (refer to FIG. 5) is not driven (the solenoid which has been excited is de-energized), and the select plate 804 is shifted from the guide position to the discharge position. It will be discharged from the medal payout opening 24.

  After the processing of S230, if S227 is NO or S229 is YES, the main CPU 101 determines whether the current medal insertion number is the game start number (S231). In the present embodiment, regardless of the gaming state, the game startable number is three (that is, it becomes possible to start the game only when three sheets are inserted).

  In S231, when the main CPU 101 determines that the current medal insertion number is the game start number (when S231 is YES), the main CPU 101 performs the processing of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of medals inserted is not the game start number (when S231 is NO), the main CPU 101 determines whether or not medals are inserted (S232). ).

  In S232, when the main CPU 101 determines that medals have been inserted (when the determination of S232 is YES), the main CPU 101 returns the process to S226, and repeats the processes after S226. On the other hand, when the main CPU 101 determines that the medal has not been inserted in S232 (when the determination in S232 is NO), the main CPU 101 performs the setting change confirmation process described in FIG. 50 (S233). In this process, the main CPU 101 performs a process of generating and storing a setting change command at the start of setting confirmation. Thereby, regardless of whether or not the gaming state is the bonus state (special prize operating state), it is possible to check the setting value and the hole menu (various history data (error, power failure history, etc.)). Cheating can be suppressed. In the setting change confirmation process performed in S233, even if the setting key type switch 54 is in the OFF state, generation and storage processing of the setting change command (setting confirmation start) including at least information on the current setting value is performed. The command data may be stored in a communication data storage area provided in the main RAM 103. In this way, it may be possible to check whether the setting value is appropriate (within the range of settings 1 to 6) for each game.

  After the process of S233 or when the determination of S231 is YES, the main CPU 101 determines whether the start switch 79 is in the on state (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the on state (when S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines that the start switch 79 is in the on state in S234 (when the determination in S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this processing, the solenoid of the selector 66 (refer to FIG. 5) is not driven (the solenoid which has been excited is de-energized), and the select plate 804 is shifted from the guide position to the discharge position. It will be discharged from the medal payout opening 24.

  Next, the main CPU 101 sets a timer value ("72" in the present embodiment) in the medal monitoring timer (S236). The medal monitoring timer is a timer for monitoring the period until the energized solenoid is demagnetized in the selector 66 (that is, the period for the select plate 804 to move from the guide position to the discharge position). (See FIG. 99 described later.) For example, when the period until the energized solenoid is demagnetized is 80 ms, a timer value for measuring at least a longer period ("about 80.44 ms") Is set. That is, the medal monitoring timer is actually operated after the start lever 16 is operated (the start switch 79 is turned on) and medal acceptance prohibition control is started when medals for the game start number have been inserted. Monitor the specific period until the acceptance of medals is (physically) prohibited. As a result, together with the start lever ON flag described later, and the medal insertion check 2 process described later, when the medal is inserted during the specific period, the medal is swallowed by mistake (that is, the medal is inserted) However, they are prevented from being accommodated in the hopper device 51 without being counted. The value of the medal monitoring timer can be appropriately changed in accordance with the specification of the selector 66 (mainly solenoid). Further, as long as prevention of the medal's swallowing is secured, the period can be set to a period less than the period until the energized solenoid is completely demagnetized.

  Next, the main CPU 101 sets the start lever ON flag to ON (S237). The start lever ON flag is information for identifying whether or not the start lever 16 has been operated (the start switch 79 has been turned on) when medals for the game start number have been inserted. .

  Next, the main CPU 101 performs medal input check 2 processing (S238). In this process, the main CPU 101 basically performs the same process as the medal insertion check process. The details of the medal insertion check process and the medal insertion check 2 process will be described later with reference to FIGS. 62 and 63 described later.

  Next, the main CPU 101 determines whether the start lever ON flag is off (S239). In S239, when the main CPU 101 determines that the start lever ON flag is in the OFF state (when the determination in S239 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines that the start lever ON flag is not in the off state (that is, in the on state) in S239 (when S239 is NO), the main CPU 101 determines that the medal monitoring timer is "0". It is determined whether there is any (S240). When the main CPU 101 determines that the medal monitoring timer is not “0” (ie, is “1” or more) in S239 (when S240 is NO), the main CPU 101 returns the process to S238, and after S238. Repeat the process of

  On the other hand, when the main CPU 101 determines that the medal monitoring timer is "0" in S240 (if S240 is YES), the main CPU 101 ends the medal acceptance / start check processing, and the main flow of the process ( Move to S203 of FIG.

[Medal input processing]
Next, with reference to FIG. 61, medals are inserted in S222 in the medal reception / start check process (see FIGS. 59 and 60) and in S265 in the medal input check process described later (see FIGS. 62 and 63). The process will be described. FIG. 61 is a flowchart of the medal insertion process.

  First, the main CPU 101 adds "1" to the value of the medal counter (S241). The medal counter is a counter for counting (counting) the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 performs medal insertion command generation and storage processing (S242). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command is configured to include parameters for specifying the number of inserted cards and the like.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 6) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the medal insertion number based on the medal insertion number (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and for example, when the number of inserted medals is three In this case, LED lighting data for lighting all the first to third LEDs for displaying the number of inserted medals is calculated. The method of calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 lights up the corresponding LED for displaying the number of inserted medals, using the calculated LED lighting data (S245). Then, after the process of S245, the main CPU 101 ends the medal insertion process, and the process proceeds to S223 of the medal acceptance / start check process (see FIGS. 59 and 60) or the medal insertion check process described later (FIGS. 62 and 63). Move to S253 of reference).

[Medical input check process]
Next, with reference to FIGS. 62 and 63, the medal insertion check process performed at S228 in the medal reception / start check process (see FIGS. 59 and 60) and the medal reception / start check process (FIGS. 59 and 60). A medal input check 2 process performed in S238 in (refer to) will be described. 62 and 63 are flowcharts showing the procedure of the medal insertion check process. The medal insertion check 2 process starts from S253 of the medal insertion check process, and the processes of S253 to S268 are the same as those in the medal insertion check process. It will be described as the procedure of the input check process.

  First, the main CPU 101 determines whether or not re-playing is in progress (S251).

  In S251, when the main CPU 101 determines that replay is in progress (when S251 is a YES determination), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (FIG. 59 and FIG. Move to S229 of 60).

  On the other hand, when the main CPU 101 determines in S251 that the game is not being played back (when the determination in S251 is NO), the main CPU 101 performs medal acceptance permission (S252). In this process, the solenoid of the selector 66 (see FIG. 5) is driven (the de-energized solenoid is excited), and the select plate 804 is shifted from the discharge position to the guide position to insert from the medal insertion slot 14 The counted medals are counted and stored in the hopper device 51.

  Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines, based on the on / off state of the BET switch 77, whether or not the bet button (MAX bet button 15a or 1 bet button 15b) has been operated. Next, the main CPU 101 determines whether or not the bet operation has been completed based on the result of the bet button check process of S253 (S254).

  In S254, when the main CPU 101 determines that the bet operation has been completed (when S254 is a YES determination), the main CPU 101 ends the medal insertion check process (or the medal insertion check 2 process), and receives the medal reception process The process then proceeds to S229 of the start check process (see FIGS. 59 and 60) (or S239 of the medal acceptance / start check process (see FIGS. 59 and 60)).

  On the other hand, when the main CPU 101 determines that the bet operation is not completed in S254 (when S254 is NO), the main CPU 101 is in the medal sensor input state (gaming medium reception state) at the current processing time; The medal sensor input state at the time of the previous processing is acquired (S255). The medal sensor input state is information indicating the passing state of the medal received in the medal insertion slot 14 in the selector 66, and is generated by the detection result of each medal sensor (see FIG. 5) of the selector 66.

  In the present embodiment, the medal sensor input state is represented by data of 1 byte (8 bits), and the detection result of the upstream first medal sensor 806 provided at the exit of the selector 66 in the passage direction of the medal is The detection result of the second medal sensor 807 on the downstream side corresponds to the information (“0” or “1”) of the bit 1 corresponding to the information (“0” or “1”) of the bit 0. When passage of a medal is detected by the first medal sensor, "1" is set to bit 0, and when passage of a medal is detected by the second medal sensor, "1" is set to bit 1 Be done. Therefore, the medal sensor input state "00000000B" indicates the state before or after the medal passing (when passing), and the medal sensor input state "00000001B" indicates the state at the start of medal passing, and the medal sensor input state " "00000011B" indicates a state during medal passing, and a medal sensor input state "00000010B" indicates a state immediately before the medal passing completion.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the current processing time has changed from the medal sensor input state at the previous processing time (S256).

  In S256, when the main CPU 101 determines that the medal sensor input state at the current process has not changed from the medal sensor input state at the previous process (when S256 is NO), the main CPU 101 performs S262 described later. Do the processing.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state at the current process has changed from the medal sensor input state at the previous process (when S256 is YES), the main CPU 101 sets the start lever ON flag. Is ON, the start lever ON flag is set to OFF (S257). That is, in this process, main CPU 101 performs the start operation and performs medal insertion during a specific period until medal reception is actually prohibited (physically) after control of medal reception prohibition is started. If it is detected, processing for invalidating the start operation is performed.

  Next, the main CPU 101 generates a normal value (normal change value) of the medal sensor input state obtained at the current processing time by arithmetic processing based on the medal sensor input state at the previous processing time (S258).

  In this process, if the medal sensor input state at the time of the previous process is "00000000B" (when both the first and second medal sensors are not detected), the normal change value of the medal sensor input state is used. If "00000001B" (if the first medal sensor is medal detection and the second medal sensor is not detected) is generated, and the medal sensor input state at the time of the previous processing is "00000001B", then the medal sensor “00000011 B” (when both the first and second medal sensors detect medals) is generated as a normal change value of the input state. Also, in this process, when the medal sensor input state at the time of the previous process is "00000011B", "00000010B" (the first medal sensor is not detected with the medal, and the second is the normal change value of the medal sensor input state When the medal sensor is medal detection) is generated, and the medal sensor input state at the time of the previous processing is “00000010 B”, “00000000 B” (first and second medals) as a normal change value of the medal sensor input state If both sensors are not detected medals are generated.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing is the same as the normal change value generated in S258 (S259). In this determination process, it is determined whether or not a medal retrogression error has occurred, and if the determination condition of S259 is not satisfied, the main CPU 101 determines that a medal retrogression error has occurred.

  When the main CPU 101 determines in S259 that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S258 (when S259 is NO), the main CPU 101 performs the processing of S263 described later. Do.

  On the other hand, when the main CPU 101 determines in S259 that the medal sensor input state in the current process is the same as the normal change value generated in S258 (when the S259 is YES), the main CPU 101 performs the current process. It is determined whether or not the medal sensor input state is a state ("00000000B") at the time of passing the medal (S260). In S260, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is the state of passing medals (when the determination of S260 is YES), the main CPU 101 performs the processing of S264 described later.

  In S260, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the state at the time of medal passing (when S260 is NO determination), the main CPU 101 sets a medal passing check timer (S261). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether the medal has passed the selector 66 or not. Also, the timer value set in this process may be changed, for example, according to the medal sensor input state at the time of the current process.

  After the process of S261 or when S256 is NO, the main CPU 101 determines whether the medal sensor input state at the current process is in the medal passing state ("00000011 B") and the medal passing check timer is stopped. It is determined (S262). In this determination process, it is determined whether a medal passage error (inserted medal passage time error) has occurred, and if the determination condition of S262 is satisfied, the main CPU 101 determines that a medal passage error has occurred.

  In S262, when the main CPU 101 determines that the determination condition of S262 is not satisfied (in the case of NO determination of S262), the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines in S262 that the determination condition of S262 is satisfied (when S262 is a YES determination), or when S259 is a NO determination, that is, a medal passage error or a medal reverse error has occurred. If it is determined that the main CPU 101 determines that the error occurs (S263). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process, for example. The details of the error processing will be described later with reference to FIG. 64 described later. Then, after the process of S263, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  Here, returning to the processing of S260, if the determination of S260 is YES, the main CPU 101 determines whether or not a prescribed number (three in the present embodiment) of medals has been inserted (S264). .

  When the main CPU 101 determines that the defined number of medals have not been inserted in S264 (when the determination in S 264 is NO), the main CPU 101 performs the medal insertion process described in FIG. 61 (S 265). Then, after the process of S265, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines that the defined number of medals have been inserted in S 264 (if YES in S 264), the main CPU 101 adds “1” to the value of the credit counter (S 266). ). Next, the main CPU 101 performs medal insertion command generation and storage processing (S267). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG.

  Next, the main CPU 101 determines, based on the value of the credit counter, whether or not the number of credits of medals is the upper limit (50 in the present embodiment) (S268).

  In S268, when the main CPU 101 determines that the number of credits of medals is not the upper limit value (when the determination in S268 is NO), the main CPU 101 returns the process to the process of S253, and repeats the processes after S253. On the other hand, when the main CPU 101 determines in S268 that the number of credits of medals is the upper limit value (when the determination in S268 is YES), the main CPU 101 ends the medal insertion check process (or the medal insertion check 2 process). Then, the process proceeds to S229 of the medal acceptance / start check process (see FIGS. 59 and 60) (or S239 of the medal acceptance / start check process (see FIGS. 59 and 60)).

Error Handling
Next, with reference to FIG. 64, for example, error processing performed in S263 in the medal insertion check processing (see FIGS. 62 and 63) will be described. FIG. 64 is a flowchart showing the procedure of error processing.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops the driving of the solenoid of the selector 66 (see FIG. 5). Next, the main CPU 101 performs a save process of the medal display number display data (S272). Next, the main CPU 101 performs an error table setting process (S273).

  Next, the main CPU 101 acquires an error factor (S274). The error factor acquired in this process changes according to the process of reading out the error process currently being processed. As error factors targeted in the present embodiment, "hopper empty error", "hopper jam error", "inserted medal passage count error", "inserted medal passage check error", "inserted medal passage check error", An "inserted medal passing time error", an "inserted medal backward error", an "inserted medal auxiliary storage full error", and an "illegal hit error" are defined. For example, when the error process is read out after the process of S259 in the medal insertion check process, in this process, “inserted medal reverse error (Cr)” is acquired as an error factor. Also, for example, when the error process is read after the process of S262 in the medal insertion check process, in this process, “inserted medal passage time error (CE)” is acquired as an error factor.

  Next, the main CPU 101 acquires error display data from the error table and the error cause (S275). For example, when the error cause is "inserted medal retrogression error (Cr)", 1 byte data "01001110B" as error display data to be output to the 7-segment LED of the upper digit among the 2-digit 7-segment LED in this process. Is acquired, and 1-byte data "00001001 B" is acquired as error display data to be output to the lower digit 7-segment LED. In this case, two characters of “Cr” are displayed as error information on the 2-digit 7-segment LED.

  Next, the main CPU 101 performs an error command (occurrence) generation and storage process (S276). In this process, the main CPU 101 generates data of an error command at the time of error occurrence which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of error occurrence stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The error command upon occurrence of an error is configured to include a parameter indicating the occurrence of an error.

  Next, the main CPU 101 performs standby processing for one interruption time (1.1172 ms) (S277). Next, the main CPU 101 determines whether the error is canceled (S278).

  When the main CPU 101 determines in S278 that the error is not canceled (when the determination in S278 is NO), the main CPU 101 returns the process to the process of S277, and repeats the processes after S277.

  On the other hand, when the main CPU 101 determines that the error has been canceled in S278 (when the determination in S278 is YES), the main CPU 101 performs an error cause clear process (S279). Note that this process is performed in the extra operation area of the main RAM 103. Next, the main CPU 101 carries out return processing of the payout number display data of the medals evacuated in S272 (S280).

  Next, the main CPU 101 performs an error command (cancellation) generation and storage process (S281). In this process, the main CPU 101 generates data of an error command at the time of error cancellation, which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The error command at the time of error cancellation is configured to include a parameter indicating the error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and shifts the processing to S253 in the medal insertion check processing (see FIG. 62 and FIG. 63), for example. When the error is canceled, the cause of the generated error is canceled and the reset switch 76 is pressed to cancel the error state.

[Random value acquisition process]
Next, with reference to FIG. 65, random number value acquisition processing performed in S203 in the main flow (see FIG. 58) will be described. FIG. 65 is a flowchart showing the procedure of random number value acquisition processing.

  First, the main CPU 101 acquires a hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for internal winning combination lottery. Is stored (S291).

  Next, the main CPU 101 performs soft latch random number acquisition register setting processing for generating soft latch random numbers (0 to 65535 or 0 to 255) of the random number registers 1 to 7 of the random number circuit (S292). Next, the main CPU 101 sets the acquired number (for example, 7) of soft latch random numbers (S293). In addition, the acquired number can be appropriately increased or decreased according to the number of lottery which can be performed in one game.

  Next, the main CPU 101 acquires the number of acquired soft latch random numbers in a batch, and stores the number of acquired soft latch random numbers in the random number storage area (S294). At this time, the soft latch random numbers (rendering effect random number values) acquired from the random number registers 1 to 7 of the random number circuit 110 are hard latch random numbers (random number register 0) acquired from the random number register 0 of the random number circuit. It is stored in an area different from the area where the internal winning combination random number value) is stored. Then, after the processing of S294, the main CPU 101 ends the random number value acquisition processing, and shifts the processing to S204 of the main flow (see FIG. 58). In the present embodiment, in order to store one 2-byte random number (random number value for internal winning combination lottery) and six 1-byte random numbers (effect random number value), an 8-byte storage area is stored in the main RAM 103. Allocated as a random number storage area. Further, in the present embodiment, a soft latch random number of 2-byte random number is not used.

[Internal lottery process]
Next, with reference to FIG. 66, the internal lottery process performed in S204 in the main flow (see FIG. 58) will be described. FIG. 66 is a flowchart of the internal lottery process.

  First, the main CPU 101 performs check processing of set value and medal insertion number (S301). In this processing, the main CPU 101 performs check processing of the setting value (one of 1 to 6) of the current game and the number of inserted medals (three in the present embodiment).

  Next, the main CPU 101 sets an internal lottery table for general game (see the internal lottery table in the “RT0” state shown in FIGS. 16 and 17) and the number of times of lottery (64 times in this embodiment) (S302) .

  Next, the main CPU 101 determines whether the RB is in operation (S303). When the main CPU 101 determines in S303 that the RB is not in operation (when the determination in S303 is NO), the main CPU 101 performs the processing of S305 described later.

  On the other hand, when the main CPU 101 determines in S303 that the RB is in operation (when the determination in S303 is YES), the main CPU 101 selects an internal lottery table for RB (refer to the internal lottery table shown in FIG. 18) The number of lotteries (eight times in the present embodiment) is set (S304). In this processing, the internal lottery table and the number of lottery times for the normal game set in S302 are overwritten with the internal lottery table and the number of lottery times for RB.

  After the process of S304 or when the determination of S303 is NO, the main CPU 101 acquires the determination data (data related to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether the determination data is data classified by RT state (S306). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination in which the lottery value changes according to the RT state. Specifically, main CPU 101 determines whether or not the address defined in the currently acquired determination data of the lottery target combination is an address in the RT condition-based lottery value selection table (not shown). .

  In S306, when the main CPU 101 determines that the determination data is not the RT state-based data (S306 is NO determination), the main CPU 101 performs the processing of S308 described later. On the other hand, when the main CPU 101 determines in step S306 that the determination data is data by RT state (when the determination in step S306 is YES), the main CPU 101 selects data from the RT state lottery value selection table based on the determination data. Is acquired, and the acquired selected data is set as determination data (S307).

  After the process of S307 or when the determination of S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is data per setting (S308). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination in which the lottery value changes in accordance with the set value. Specifically, the main CPU 101 determines whether or not the address specified in the determination data of the lottery target combination currently acquired is an address in the setting-specific internal lottery value table (not shown).

  In S308, when the main CPU 101 determines that the determination data is not the setting data (when the determination in S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, when the main CPU 101 determines in step S308 that the determination data is data according to setting (when the determination in step S308 is YES), the main CPU 101 adds the set value data (0 to 5) to the determination data. Then, the added value is set as determination data (S309). The set value data added to the determination data in this process is data associated with the set value, but not the set value itself but set value data “0” to “5” It is data corresponding to setting 1 "to" setting 6 ".

  After the process of S309 or when the determination of S308 is NO, the main CPU 101 calculates the address of the area where the lottery value of the lottery subject is stored, based on the set determination data (address data), and The stored lottery value is acquired (S310).

  For example, in the case of an internal winning combination whose lottery value changes according to both the RT state and the setting value, the lottery value is referred to with reference to both the RT state lottery value selection table and the internal lottery value table by setting. Is acquired. That is, for example, in the internal lottery table for the general gaming state (see FIGS. 16 and 17), the internal winning combination (for example, No. “19”) in which the lottery value fluctuates when RT state is different based on RT0 state. For “44” replay role, the lottery value is varied according to the gaming state (RT1 to RT4), and the lottery value is varied when the set value is different (for example, No. 17). "," "18", "20" and "55", the lottery value is varied according to the set value (settings 1 to 6).

  Next, the main CPU 101 acquires a random number value (one of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 performs lottery processing (S312). In this process, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as the lottery result (winning / not winning of the lottery object combination). In this lottery execution process, when the sum of the lottery value and the random number exceeds 65535 (when it overflows), it is determined that the lottery object combination is won (the lottery object combination is determined as the internal winning combination). Ru.

  Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after lottery execution) as a new random value in the random number storage area (S313). Next, the main CPU 101 determines whether or not winning is performed in the lottery processing (whether or not an overflow occurs) (S314).

  When the main CPU 101 determines that the lottery execution process is won in S314 (when the determination in S314 is YES), the main CPU 101 refers to the internal lottery table, and the hit request flag status (corresponding to the internal winning combination won). For example, for the prize winning number (ie, information that can identify the type of bonus role won) corresponding to “No.” in FIG. The value of the information that can identify the type) is acquired (S315). Then, after the processing of S315, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 58).

  On the other hand, when the main CPU 101 determines in S314 that the lottery execution process has not won (S314 is NO determination), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table and performs lottery. The number is decremented by 1 (S316). Next, the main CPU 101 determines whether the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the number of lotteries after subtraction is not “0” (S317 is NO), the main CPU 101 returns the process to the process of S305, and repeats the process of S305 and subsequent steps.

  On the other hand, when the main CPU 101 determines in S317 that the number of lotteries after subtraction is “0” (when the determination in S317 is YES), that is, when the internal winning combination is “off”, the main CPU 101 The lost status is set (S318). The “lost status” corresponds to a hit request flag status in which both of the special prize winning number and the small bonus winning number become “0”. Then, after the processing of S318, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 58).

[Pattern setting process]
Next, with reference to FIG. 67, the symbol setting process performed in S205 in the main flow (see FIG. 58) will be described. FIG. 67 is a flowchart showing the procedure of symbol setting processing.

  First, based on the hit request flag status acquired in the internal lottery process, the main CPU 101 extracts the special award winning number and the small award winning number, and extracts the extracted special award winning number and the small award winning number in the main RAM 103. It stores in the winning number storage area (not shown) (S321).

  In the present embodiment, the internal winning combinations "F_SBB", "F_BB1", "F_BB2", "F_BB3" and "F_BB4" are associated with the special award winning numbers "1" to "5", respectively. In addition, the internal winning combination "F _ middle cherry lip" to "F _ chance lip _3 rd" is associated with the small winning combination "1" to "27", respectively (see Fig. 23), and the small winning combination "28". The internal winning combinations “F_left bell A” to “F_JAC bell B” are respectively associated with “to“ 50 ”(see FIG. 24). Then, the value of the hit request flag status is constituted by a value obtained by multiplying the value of the special award winning number by the special award number indicating these values and adding the small winning combination number. Therefore, in the process of S321, the main CPU 101 divides the value of the hit request flag status by the award number in the present embodiment in order to extract the prize winning number and the small winning symbol number from the value of the hit request flag status. This is an example of data compression for identifying an internal winning combination, and other data configurations can be adopted as appropriate, as long as a special award winning number and a minor winning number can be extracted.

  Next, the main CPU 101 determines whether or not the small winning combination (or the replay combination) has been won based on the extracted small winning combination number (S322). In this process, when the small winning combination number is any one of 1 to 50, the main CPU 101 determines that the small winning combination (or the replay combination) is won, and the small winning combination number is 0. The main CPU 101 determines that the small winning combination (or the replay combination) has not won.

  In S322, when the main CPU 101 determines that the small winning combination (or the replay combination) is not won (when the determination of S322 is NO), the main CPU 101 performs the processing of S331 described later. On the other hand, when the main CPU 101 determines that the small winning combination (or the replay combination) is won in S322 (when the determination in S322 is YES), the main CPU 101 sets the small winning combination number as the initial value of the subtraction result ( S323).

  Next, the main CPU 101 sets a hit request flag table (not shown) (S324). Next, the main CPU 101 subtracts one from the result of subtraction and updates the result of subtraction (S325). Next, the main CPU 101 determines whether the subtraction result is less than “0” (S326).

  In S326, when the main CPU 101 determines that the subtraction result is not less than “0” (when the determination in S326 is NO), the main CPU 101 performs bit number calculation processing (S327). In the bit number calculation process of S327, the number of blocks of the storage area of the hit request flag data corresponding to the small winning combination number defined in the hit request flag table is acquired.

  Next, the main CPU 101 performs bit number calculation processing (S328). In the bit number calculation process of S328, the number of bytes of the hit request flag data in block units defined in the hit request flag table is calculated.

  In addition, the process of S325-S328 mentioned above is repeated only the frequency | count of a small winning combination number. In addition, when the processing of S325 to S328 is repeated multiple times, the number of blocks obtained in the bit number calculation processing of S327 and S328 and the number of bytes of the request flag data per block are stored in different storage areas. Be done. Further, the number of blocks and the number of bytes of hit request flag data in block units obtained by the above-described processing of S325 to S328 become information (on-bit information) for specifying the storage destination of the hit request flag data.

  Here, returning to the processing of S326 again, when the main CPU 101 determines that the subtraction result is less than “0” in S326 (when S326 is YES determination), the main CPU 101 stores the hit request flag storage area ( The internal winning combination storing area) is set (S329). At this time, the main CPU 101 determines a hit request flag to be checked (updated) based on the number of blocks obtained by the above-described processing of S325 to S328 and the number of bytes of the hit request flag data in block units (on bit information). Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register.

  Next, the main CPU 101 performs compressed data storage processing (S330). In this process, the main CPU 101 mainly performs a process of transferring (developing) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). Details of the compressed data storage processing will be described later with reference to FIG. 68 described later.

  After the process of S330 or when the determination of S322 is NO, the main CPU 101 determines whether or not there is a carryover combination with reference to the carryover combination storage area (see FIG. 26) (S331). In S331, when the main CPU 101 determines that there is a carryover combination (when the determination in S331 is YES), the main CPU 101 performs the processing of S334 described later.

  On the other hand, when the main CPU 101 determines in S331 that there is no carryover combination (if S331 is NO), the main CPU 101 selects one of the bonus combinations (SBB, BB1) based on the winning prize number extracted in the process of S321. It is determined whether or not ~ BB4) is won (S332).

  In S332, when the main CPU 101 determines that the bonus combination is not won (S332 is NO determination), the main CPU 101 ends the symbol setting process, and the process proceeds to S206 of the main flow (see FIG. 58). Move.

  On the other hand, when the main CPU 101 determines that the bonus combination has been won in S332 (when the determination in S332 is YES), the main CPU 101 stores the won special prize winning number in the carryover combination storage area (S333).

  After the processing of S333 or when S331 is NO, the main CPU 101 sets the winning prize number in the winning number storage area (not shown), sets the hit request flag data in the hit request flag storage area, and RT4 the RT status. The state is set (S334). Then, after the processing of S334, the main CPU 101 ends the symbol setting processing, and shifts the processing to S206 of the main flow (see FIG. 58).

[Compressed data storage process]
Next, with reference to FIG. 68, for example, compressed data processing performed in S330 in the symbol setting processing (see FIG. 67) will be described. FIG. 68 is a flowchart of a procedure of compressed data storage processing.

  The compressed data storage process shown in FIG. 68 is executed not only at S330 in the symbol setting process (see FIG. 67) but also at S649 in the symbol code acquisition process (see FIG. 76 described later). In the compressed data storage process executed in S330 in the symbol setting process (see FIG. 67), the flag data to be processed is the hit request flag data (flag data related to the winning combination), but the symbol code acquisition process described later In the compressed data storage processing executed in S649 in (see FIG. 76 described later), flag data to be processed is winning operation flag data (flag data relating to a winning combination). The two processes are the same except that the type of flag data to be processed is different.

  Therefore, in the flowchart of FIG. 68, flag data to be processed is referred to as "processing target flag data", and a flag table to be processed is referred to as a "processing target flag table". Also, in line with this description, in the following description of compressed data storage processing, hit request flag data or winning operation flag data will be referred to as "processing target flag data", and a hit request flag table or a symbol corresponding winning operation table described later. (Not shown) is referred to as "processing target flag table".

  First, the main CPU 101 sets a storage destination check bit (S341). In this process, the storage destination check bit is stored in a register other than the A register.

  The storage destination check bit is 1-byte data for specifying a block as a storage destination (transfer destination) of the processing target flag data. In the present embodiment, both the hit request flag storage area and the winning operation flag storage area are configured of three blocks (blocks of storage areas 1 to 8, blocks of storage areas 9 to 16 and blocks of storage areas 17 to 22). Ru. Then, for example, when the internal winning combination "F_left bell A" is determined, the number of blocks in the storage destination is "3", so "00000111B" is set as the storage destination check bit in the process of S341. Be done. The value (1/0) of bit 0 of this 1-byte data corresponds to the presence or absence of the storage destination in the blocks of storage areas 1 to 8, and the value (1/0) of bit 1 is storage areas 9 to 16 The value (1/0) of the bit 2 corresponds to the presence or absence of the storage destination in the blocks of the storage areas 17 to 22 in accordance with the presence or absence of the storage destination in the block b.

  Next, the main CPU 101 sets the value of the transfer counter in byte units to "8" (S342). In this embodiment, since the number of bytes of each block is "8", "8" is set as the initial value of the transfer counter.

  Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the processing of S343, the storage destination check bit stored in the 1-byte register is shifted right (one bit) to the right. Thus, the transfer indication bit is extracted. Specifically, when the 1-byte register (register other than A register) storing the storage destination check bit is shifted right once, the data stored in bit 7 to bit 1 is changed to bit 6 to bit 0, respectively. While moving, the data of bit 0 before shift is output. Then, the data output by this shift processing becomes the value of the transfer instruction bit.

  Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000011B" is set as the storage destination check bit, the first (corresponding to the first block of the storage area) and the second (corresponding to the second block of the storage area) determination process of S344 transfers Although it is determined that there is an instruction, in the third and subsequent determination processes of S344, it is determined that there is no transfer instruction.

  In S344, when the main CPU 101 determines that there is no transfer instruction (when S344 is NO), the main CPU 101 performs the processing of S354 described later.

  On the other hand, when the main CPU 101 determines in S344 that there is a transfer instruction (when the determination in S344 is YES), the main CPU 101 acquires byte unit storage destination designation information from the processing target flag table (S345). In this process, as the byte unit storage destination designation information, 1 is shown at the head address of the area where the flag data of the processing target combination (a winning combination or a winning combination) in the processing target flag table is stored. Byte data is acquired.

  Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address referred to in the process target flag table (S346). Further, in this processing, the main CPU 101 sets an address specifying the head storage area of the block which is the storage (transfer) destination of the processing target flag data as an initial address. For example, in the processing of the first block, the address of storage area 1 is set as the initial address in the processing of S346, and in the processing of the second block, the address of storage area 9 is set as the initial address in the processing of S346. .

  Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage destination specification information (S347). Note that the transfer instruction bit here corresponds to bit 0 of the byte unit storage destination designation information, and in the process of S347, the byte unit storage destination designation information stored in the 1-byte register should be shifted right once. Thus, the value of the transfer instruction bit is extracted (data of bit 0 is output).

  Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, when the value of the extracted transfer indication bit is “1”, the main CPU 101 determines that there is a transfer indication. For example, when "00000010B" is set as byte unit storage destination designation information, data "1" of bit 1 in the second (the first block storage area 2 or the second block storage area 10) process of S347. Is output as the value of the transfer instruction bit and it is determined that there is a transfer instruction, but in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

  When the main CPU 101 determines in S348 that there is no transfer instruction (when the determination in S348 is NO), the main CPU 101 performs the processing of S351 described later.

  On the other hand, when the main CPU 101 determines in S348 that there is a transfer instruction (when the determination in S348 is YES), the main CPU 101 determines the processing target flag stored in the address in the processing target flag table currently set. The data (hit request flag data or winning operation flag data) is transferred (copied) to the designated storage area (S 349).

  Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address referred to in the process target flag table (S350).

  After the process of S350 or when the determination of S348 is NO, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address specifying the storage area to be the storage destination of the process target flag data (S351). Next, the main CPU 101 subtracts one from the value of the transfer counter (S352).

  Next, the main CPU 101 determines whether the value of the transfer counter is “0” (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not “0” (when the determination in S353 is NO), the main CPU 101 returns the process to the process of S347 and repeats the processes after S347.

  On the other hand, when the main CPU 101 determines in S353 that the value of the transfer counter is "0" (when the determination in S353 is YES), whether the main CPU 101 has a transfer instruction target remaining in the current storage destination check bit It is determined whether or not (S354). In this process, the main CPU 101 determines whether or not a bit for which “1” is stored remains in the storage destination check bit at the current process time. Then, when there is a bit for which "1" is stored in the storage destination check bit, that is, when there is a block to be processed, the main CPU 101 instructs transfer to the current storage destination check bit. It is determined that the target remains.

  In S354, when the main CPU 101 determines that the transfer instruction target remains in the current storage destination check bit (when the determination in S354 is YES), the main CPU 101 returns the process to the process of S342, and the processes after S342. repeat. On the other hand, when the main CPU 101 determines in S354 that no transfer instruction target remains in the current storage destination check bit (S354 is NO), the main CPU 101 ends the compressed data storage processing, and the processing is performed. For example, it moves to S331 in the symbol setting process (see FIG. 67).

[Control processing according to game start state]
Next, with reference to FIG. 69, control processing classified by game start state performed in S208 in the main flow (see FIG. 58) will be described. FIG. 69 is a flow chart showing the procedure of the game start state control process.

  First, the main CPU 101 performs sub-flag conversion processing (S401). In this process, the main CPU 101 performs a process of converting an internal winning combination into a sub flag (see FIG. 31). Note that, as described above, when the BAR complete flip sub flag conversion lottery is performed, a process of converting the internal winning combination into the sub flag is performed according to the lottery result.

  Next, the main CPU 101 determines whether the section of the current game is in an advantageous section (see FIG. 14) (S402). In S402, when the main CPU 101 determines that the section of the current game is not in the advantageous section (when the determination in S402 is NO), the main CPU 101 shifts the processing to S404 described later.

  On the other hand, when the main CPU 101 determines in S402 that the section of the current game is in the advantageous section (when the determination in S402 is YES), the main CPU 101 performs advantageous processing common processing at the game start (S403). In addition, the details of the game start time advantageous section common processing will be described later with reference to FIG. 70 described later.

  If S402 is NO, and after the processing of S403, the main CPU 101 determines whether the current gaming state is the AT gaming state (S404). In S404, when the main CPU 101 determines that the current gaming state is not the AT gaming state (S404: NO), the main CPU 101 shifts the processing to S406 described later.

  On the other hand, when the main CPU 101 determines in S404 that the current gaming state is the AT gaming state (when the determination in S404 is YES), the main CPU 101 performs an AT in-progress processing during game start (S405). Note that details of the process during AT at the time of game start will be described later with reference to FIG. 71 described later. Then, after the processing of S405, the main CPU 101 ends the control processing classified by game start state and shifts the processing to S209 of the main flow (see FIG. 58).

  If the determination in S404 is NO, the main CPU 101 determines whether the current gaming state is the ART preparation state (S406). In S406, when the main CPU 101 determines that the current gaming state is not the ART preparation state (when S406 is NO), the main CPU 101 shifts the processing to S408 described later.

  On the other hand, when the main CPU 101 determines in S406 that the current gaming state is the ART preparation state (when the determination in S406 is YES), the main CPU 101 performs ART preparation processing during game start (S407). In this process, the main CPU 101 executes various processes for executing various controls in the ART preparation state described using FIG. Then, after the process of S407, the main CPU 101 ends the game start time state control process, and shifts the process to S209 of the main flow (see FIG. 58).

  If the determination in S406 is NO, the main CPU 101 determines whether the current gaming state is the ART1 gaming state (S408). In S408, when the main CPU 101 determines that the current gaming state is not the ART 1 gaming state (S408: NO), the main CPU 101 shifts the processing to S410 described later.

  On the other hand, when the main CPU 101 determines in S408 that the current gaming state is the ART1 gaming state (when the determination in S408 is YES), the main CPU 101 performs an ART1 middle processing at the game start (S409). In addition, the details of the processing during ART1 at the game start time will be described later with reference to FIGS. 72 and 73 described later. Then, after the processing of S409, the main CPU 101 ends the control processing classified by game start state and shifts the processing to S209 of the main flow (see FIG. 58).

  If the determination in S408 is NO, the main CPU 101 determines whether the current gaming state is the ART2 to ART4 gaming state (S410). When the main CPU 101 determines in S410 that the current gaming state is not the ART2 to ART4 gaming state (when the determination in S410 is NO), the main CPU 101 shifts the processing to S412 described later.

  On the other hand, when the main CPU 101 determines that the current gaming state is the ART 2 to ART 4 gaming state in S 410 (when the determination in S 410 is YES), the main CPU 101 performs processing during ART 2 to 4 at the game start (S 411). ). In this process, the main CPU 101 executes various processes for executing various controls in the ART2 to ART4 gaming state described with reference to FIGS. Then, after the processing of S411, the main CPU 101 ends the control processing classified by game start state and shifts the processing to S209 of the main flow (see FIG. 58).

  If the determination in S410 is NO, the main CPU 101 determines whether the current gaming state is the CZ1 or CZ2 gaming state (S412). When the main CPU 101 determines in S412 that the current gaming state is not CZ1 or CZ2 gaming state (when the determination in S412 is NO), the main CPU 101 shifts the processing to S414 described later.

  On the other hand, when the main CPU 101 determines in S412 that the current gaming state is the CZ1 or CZ2 gaming state (when the determination in S412 is YES), the main CPU 101 performs the processing during CZ1 and CZ2 at the game start (S413) ). In this process, the main CPU 101 executes various processes for executing various controls in the CZ1 or CZ2 gaming state described with reference to FIGS. 45 and 46. Then, after the processing of S413, the main CPU 101 ends the control processing classified by game start state and shifts the processing to S209 of the main flow (see FIG. 58).

  If the determination in S412 is NO, the main CPU 101 performs processing during normal game start (S414). It should be noted that the details of the processing during the game start will be described later with reference to FIG. 74 described later. Then, after the process of S414, the main CPU 101 ends the game start time state control process, and shifts the process to S209 of the main flow (see FIG. 58).

[Process common to advantageous areas at the start of gaming]
Next, with reference to FIG. 70, the game start time advantageous section common process performed in S403 in the game start time state control process (see FIG. 69) will be described. FIG. 70 is a flow chart showing the procedure of common processing at the start of a game.

  First, the main CPU 101 determines whether the current gaming state is the AT gaming state (S421). In S421, when the main CPU 101 determines that the current gaming state is not the AT gaming state (S421: NO), the main CPU 101 shifts the processing to S423 described later.

  On the other hand, when the main CPU 101 determines in S421 that the current gaming state is the AT gaming state (YES in S421), the main CPU 101 performs bell navigator generation lottery (see FIG. 36A) (S422). That is, the main CPU 101 determines whether or not to inform the player of information of the stop operation which is advantageous to the player when the push order small combination is won in the AT gaming state.

  If the determination in S421 is NO, and after the processing in S422, the main CPU 101 performs navigation setting processing (S423). That is, when one of the push order small combination and the push order replay is determined as an internal winning combination, the main CPU 101 determines that the current gaming state is the ART preparation state, the ART gaming state, and the CZ gaming state, When the current gaming state is the AT gaming state and the bell navigation generation lottery is won, processing is performed to set navigation data (see FIG. 47) for informing the player of the procedure of the stop operation advantageous to the player.

  Next, the main CPU 101 updates (+1 adds) the advantageous segment counter (S424). The advantageous section counter is a counter for counting the number of games played in a series of advantageous sections. Next, the main CPU 101 performs navigation mode lottery (see FIG. 35) (S425).

  Next, the main CPU 101 determines whether it is in the ending state 1 or the ending state 2 (S426). When the main CPU 101 determines that the ending state 1 or the ending state 2 is in the S426 (when the S426 is determined as YES), the main CPU 101 ends the advantageous area common processing at the start of the game and the processing at the game start state It moves to S404 of another control process (see FIG. 69).

  On the other hand, when the main CPU 101 determines that the ending state 1 or the ending state 2 is not in S426 (when S426 is NO), the main CPU 101 determines whether the value of the advantageous segment counter has become "1400". (S427). In S427, when the main CPU 101 determines that the value of the advantageous segment counter is not "1400" (when the determination in S427 is NO), the main CPU 101 shifts the processing to S431 described later.

  On the other hand, when the main CPU 101 determines in S427 that the value of the advantageous segment counter has become "1400" (when the determination in S427 is YES), the main CPU 101 determines whether the ART stock number is "3" or more. (S428). In S428, when the main CPU 101 determines that the ART stock number is not “3” or more (when S428 is NO), the main CPU 101 ends the advantageous area common processing at the start of the game, and the processing at the game start state It moves to S404 of another control process (see FIG. 69).

  On the other hand, when the main CPU 101 determines in S428 that the ART stock number is “3” or more (when the determination in S428 is YES), the main CPU 101 sets the ending state 1 (S429). That is, when the number of games in the series of advantageous sections is "1400" and there are "3" or more ART stocks at that time, the main CPU 101 ends the advantageous section soon in the advantageous section. The first state (first ending effect) of the predetermined effects (ending effect) suggesting the is controlled to the ending state 1 that can be performed.

  Next, when the external signal 1 is in the off state, the main CPU 101 turns on the external signal 1 (S430). Here, in this embodiment, the external signal 1 basically turns from the off state to the on state when the ART gaming state of the advantageous section is started (in FIG. 37, “ART transition condition satisfied”), ART The on state continues during the gaming state. Then, when the ART gaming state ends (when transitioning from the ART gaming state to the normal gaming state or the CZ gaming state), the on state is switched to the off state (see FIG. 88 described later). Even in the case of being controlled, it is made to switch from the off state to the on state. That is, for example, when the ending state 1 is controlled also in the ART preparation state or the CZ gaming state, the output of the external signal 1 is started. The same applies to the case of controlling to the ending state 2 described later.

  If the determination in S427 is NO, the main CPU 101 determines whether the value of the advantageous segment counter has become "1450" (S431). When the main CPU 101 determines in S431 that the value of the advantageous section counter is not "1450" (when the determination of S431 is NO), the main CPU 101 ends the advantageous section common processing at the time of game start, and the processing Control is passed to step S404 of the control process (see FIG. 69) at the time of game start.

  On the other hand, when the main CPU 101 determines in S431 that the value of the advantageous segment counter has become “1450” (when the determination in S431 is YES), the main CPU 101 determines whether or not the ending state 1 is already controlled. (S432). In S432, when the main CPU 101 determines that the ending state 1 has already been controlled (when the determination in S432 is YES), the main CPU 101 ends the advantageous area common processing at the time of game start, and the process is performed at the time of game start It moves to S404 of another control process (see FIG. 69).

  On the other hand, if the main CPU 101 determines in S432 that the control is not yet controlled to the ending state 1 (if NO in S432), the main CPU 101 sets the ending state 2 (S433). That is, when the number of games in the series of advantageous sections is "1450" times and the main CPU 101 is not controlled to the ending state 1, the main CPU 101 indicates that the advantageous section is to end soon. The second state (second ending effect) of the second effects (ending effect) is controlled to an ending state 2 in which the second effect (second ending effect) can be executed.

  Next, when the external signal 1 is in the off state, the main CPU 101 turns on the external signal 1 (S434). Then, after the processing of S434, the main CPU 101 ends the game start time advantageous section common process and shifts the process to S404 of the game start time state control process (see FIG. 69).

[Process during AT at the time of game start]
Next, with reference to FIG. 71, the game start time AT process performed in S405 in the game start time state-specific control process (see FIG. 69) will be described. FIG. 71 is a flow chart showing a procedure of in-AT processing during game start.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S441). When the main CPU 101 determines in S441 that the current gaming state is the bonus state (when the determination in S441 is YES), the main CPU 101 performs various lottery in the bonus state (see, for example, FIG. 33E) (S442). ) Although not shown, when the bonus combination is determined as an internal winning combination, the main CPU 101 performs various lottery (see, eg, FIGS. 33D and 36C) at the time of winning a bonus. Then, after the processing of S 442 or after performing various lottery at the time of winning a bonus, the main CPU 101 ends the processing during AT at the time of game start, and also ends the control processing according to the state of game start.

  On the other hand, when the main CPU 101 determines in S441 that the current gaming state is not the bonus state (when the determination in S441 is NO), the main CPU 101 determines whether the current gaming state is the flag state. (S443). In S443, when the main CPU 101 determines that the current gaming state is the inter-flag state (when S443 is determined as YES), the main CPU 101 ends the processing during AT at the time of game start, and control according to the state of game start The process also ends.

  On the other hand, when the main CPU 101 determines in S443 that the current gaming state is not the flag state (that is, the bonus is not won) (in the case of NO determination in S443), the main CPU 101 determines whether a bell navigation has occurred. It is determined (S444). That is, the main CPU 101 wins the bell navigation generation lottery (see S422 in FIG. 70), and determines whether or not it is determined that the notification of the pushing order of the pushing order small combination is performed. When the main CPU 101 determines that the bell navigation has occurred in S 444 (when the determination in S 444 is YES), the main CPU 101 updates (+1 adds) the number of bell navigation occurrences (S 445)

  When the main CPU 101 determines that no bell navigation has occurred in S 444 (when S 444 is NO), and after the processing in S 445, the main CPU 101 performs an AT-promoted lottery (see FIG. 36B) (S 446). . Next, the main CPU 101 determines whether or not an AT-promoted lottery has been won (S447). In S447, when the main CPU 101 determines that an AT-promoted lottery has been won (if S447 is YES), the main CPU 101 re-lotteries the AT continuation period (S448), and further, the AT-promoted lottery lottery The ART stock counter is updated according to the result (S449). The ART stock counter is a counter for cumulatively storing the number of ART stock for each ART stock type (ART1 to ART4), and the upper limit of each stock number is 255 (one byte). There is.

  In S447, when the main CPU 101 determines that the in-AT promotion lottery has not won (when S447 is NO), and after the processing of S449, the main CPU 101 updates the AT continuation possible period counter (+1 addition) To do (S450). The AT continuation possible period counter is a counter for managing the number of games (AT continuation possible period) in the AT gaming state. Then, after the processing of S450, the main CPU 101 ends the processing during AT at the time of game start and also ends the control processing classified by game start state.

[Process during ART1 start processing]
Next, with reference to FIG. 72 and FIG. 73, the game start time ART1 in-progress process performed in S409 in the game start time state-specific control process (see FIG. 69) will be described. 72 and 73 are flowcharts showing the procedure of processing during ART 1 at the start of the game.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S451). In S451, when the main CPU 101 determines that the current gaming state is the bonus state (when S451 is a YES determination), the main CPU 101 performs various lottery in the bonus state (see, for example, FIG. 33E) (S452) ) Although not shown, when the bonus combination is determined as an internal winning combination, the main CPU 101 performs various lottery (see, eg, FIGS. 33D and 36C) at the time of winning a bonus. Then, after the processing of S452 or after performing various lottery at the time of winning a bonus, the main CPU 101 shifts the processing to S471 described later.

  On the other hand, when the main CPU 101 determines in S451 that the current gaming state is not the bonus state (when the determination in S451 is NO), the main CPU 101 determines whether the current gaming state is the flag state. (S453). When the main CPU 101 determines in S453 that the current gaming state is the inter-flag state (when the determination in S453 is YES), the main CPU 101 shifts the process to S471 described later.

  On the other hand, when the main CPU 101 determines in S453 that the current gaming state is not the state between flags (S453 is NO determination), whether the main CPU 101 is controlled to the ending state 1 or the ending state 2 It discriminates (S454). When the main CPU 101 determines that the ending state 1 or the ending state 2 is controlled in S454 (when the determination in S454 is YES), the main CPU 101 shifts the processing to S470 described later. When the ending state 1 or the ending state 2 is controlled, basically, various lottery related to game characteristics such as ART stock lottery in ART 1 and ART stock promotion lottery in ART 1 are not performed. This is the same in the ART2 to ART4 gaming state. Further, although illustration is omitted, the processing of S451 to S454 and the processing of S471 to S473 described later are similarly performed in the processing during ART 2 to 4 at the game start time.

  On the other hand, when the main CPU 101 determines that the ending state 1 or the ending state 2 is not controlled in S454 (when the determination in S454 is NO), the main CPU 101 determines whether or not the ART1 promotion lottery state. (S455). In S455, when the main CPU 101 determines that the state is not the ART1 promoted lottery state (when S455 is NO), the main CPU 101 shifts the processing to S462 described later.

  On the other hand, when the main CPU 101 determines in S455 that the state is the ART1 promoted lottery (if the determination in S455 is YES), the main CPU 101 performs ART stock promotion lottery (see FIG. 41A) in ART1 (S456). Next, the main CPU 101 determines whether the ART stock promotion lottery in ART 1 has been won (S 457). When the main CPU 101 determines that the ART stock promotion lottery in ART 1 has been won in S 457 (when the S 457 is determined as YES), if the promotion precursor period has not yet been determined, the main CPU 101 will sort out the promotion precursor period (FIG. (S458), and the ART stock counter is updated according to the lottery result of ART stock promotion lottery in ART 1 (S459).

  When the main CPU 101 determines that the ART stock promotion lottery in ART 1 is not won in S 457 (when S 457 is NO), and after the processing of S 459, the main CPU 101 determines whether or not it is a promotion precursor period. It discriminates (S460). In S460, when the main CPU 101 determines that it is in the promotion sign period (when S460 is determined as YES), the main CPU 101 updates (+1 adds) the promotion sign period counter (S461), and performs processing in S471 described later. Move. Note that the promotion precursor period counter is a counter for managing the number of games in the promotion precursor period in the ART 1 gaming state. On the other hand, when the main CPU 101 determines in S460 that it is not in the promotion sign period (when S460 is NO), the main CPU 101 shifts the processing to S462 described later.

  When the main CPU 101 determines in S455 that the state is not ART1 promoted lottery (that is, ART1 is in the normal state) (if S455 is NO), the main CPU 101 determines whether or not the current navigation mode is 1 or less. (S462). When the main CPU 101 determines in S462 that the current navigation mode is not 1 or less (that is, 2 or more) (in the case of NO determination in S462), the main CPU 101 shifts the processing to S466 described later. That is, when the current navigation mode is two or more, the ART1 promotion lottery for promoting the ART1 gaming state is not performed.

  On the other hand, when the main CPU 101 determines in S462 that the current navigation mode is 1 or less (when the determination in S462 is YES), the main CPU 101 performs the ART1 promotion lottery (see FIG. 40B) (S463). Next, the main CPU 101 determines whether or not the ART1 promoted lottery has been won (S464). In S464, when the main CPU 101 determines that the ART1 promotion lottery has been won (when the S464 is determined as YES), the main CPU 101 selects the ART gaming state of the promotion destination from the next game (for example, in this case, ART2 to ART4). It is set to shift to any of the gaming states) (S465). Then, after the process of S465, the main CPU 101 shifts the process to S471 described later.

  When the main CPU 101 determines that the current navigation mode is not 1 or less (i.e., 2 or more) in S 462 (when S 462 is NO), and in S 464, the main CPU 101 wins the ART1 promotion lottery. When it is determined that the main CPU 101 determines that it is not (in the case of NO determination in S464), the main CPU 101 performs ART stock lottery in ART 1 (see FIG. 40C) (S466). Next, the main CPU 101 determines whether or not the ART stock lottery in ART 1 has been won (S 467). When the main CPU 101 determines that the ART stock lottery in ART 1 has been won in S 467 (in the case of YES determination in S 467), it is set to shift to the ART 1 lottery state from the next game (S 468). The ART stock counter is updated according to the lottery result of the stock lottery (S469).

  If S454 is NO, S460 is NO, S467 is NO, and after S469, the main CPU 101 updates (+1 adds) the ART continuable period (ART1) counter (S470). The ART continuation possible period (ART1) counter is a counter for managing the number of games (ART1 continuation possible period) in the ART1 gaming state.

  After the processing of S452, if the determination of S453 is YES, after the processing of S461, after the processing of S465, and after the processing of S470, the main CPU 101 determines whether ART 3 or more is won in the current game (S471). That is, the main CPU 101 selects ART stock lottery during bonus, ART stock lottery when bonus is won, special ART stock lottery when bonus is won, ART stock promotion lottery during ART1, lottery among ART1 promotion lottery, and ART stock lottery during ART1. In the game, ART stock wins “ART 3” or “ART 4” as ART stock, ART stock is promoted to “ART 3” or “ART 4”, or currently running ART 1 gaming state is promoted to ART 3 or ART 4 gaming state It is determined whether or not it has been determined. In S471, when the main CPU 101 determines that ART 3 or more is not won in the current game (when S 471 is NO), the main CPU 101 ends the processing during ART 1 at the start of the game and controls according to the state at the game start The process also ends.

  In S471, when the main CPU 101 determines that ART 3 or more is won in the current game (when the determination in S 471 is YES), the main CPU 101 determines whether the value of the advantageous segment counter is "1000" or more. (S472). In S472, when the main CPU 101 determines that the value of the advantageous segment counter is not "1000" or more (when the determination in S472 is NO), the main CPU 101 ends the processing during ART 1 at the time of game start, and by state at the game start The control process also ends.

  On the other hand, when the main CPU 101 determines that the value of the advantageous segment counter is “1000” or more in S 472 (if S 472 is YES), the main CPU 101 converts ART 3 or ART 4 winning or promoted to ART 2 (S473). That is, when the main CPU 101 wins as "ART 3" or "ART 4" as ART stock, or when ART stock is promoted to "ART 3" or "ART 4", these ART stocks are converted to "ART 2" Update the ART stock counter. Further, when it is determined that the currently-running ART1 gaming state is promoted to ART3 or ART4 gaming state, the gaming state of the promotion destination is converted to the ART2 gaming state.

  The processes of S471 and S472 may be performed stepwise. For example, when ART3 or more wins when the advantageous section counter is "1000" or more, not only conversion to ART2 is possible, but when ART2 or more wins when the advantageous section counter is "1300", conversion to ART1 is made It is also good.

  Further, in the process of S472, the value of the navigation mode may be determined instead of the value of the advantageous segment counter. For example, in the process of S 472, as in the process of S 462, it is determined whether or not the current navigation mode is “1” or less, and if the current navigation mode is “1” or less In the case where the current navigation mode is not "1" or less (if it is "2" or more), the processing of S473 may be performed.

  Further, in the process of S471, the lottery result of ART stock lottery at bonus winning and during bonus is excluded from the target (that is, even when “ART 3” or “ART 4” is won in these lottery, NO determination is made in S471. As a matter of fact, it is possible to target only the winning results of ART stock in ART 1, promotion, or lottery results of ART promotion transition.

  As described above, in this embodiment, it is possible to determine which ART stock of a plurality of ART stocks (ART 1 to ART 4) having different degrees of advantage is to be provided, for example, in the ART 1 gaming state, normal termination The ART1 gaming state is ended if the condition is satisfied (for example, if the ART1 continuation possible period is digested and the ART stock is 0 pieces), and the special ending condition is satisfied (for example, in the advantageous interval counter) Even when the value becomes “1500”, the ART1 gaming state is ended, and when the value of the advantageous segment counter becomes “1000” or more, ART stock “ART 3” or ART stock having a high degree of advantage in the subsequent period If it is decided to give "ART 4", ART stock "ART 2" with a lower degree of advantage than this is given

  Thereby, when the ART gaming state is forcibly terminated due to the regulation, it is possible to prevent a large amount of the granted ART stock from remaining. That is, since it is possible to grant the rights regarding the ART gaming state within the range in which the player can digest, it is possible to reduce the decrease in the interest of the player even when the acquisition of game media is restricted. be able to.

[Process at the beginning of the game is usually in progress]
Next, with reference to FIG. 74, the game start time normal process performed in S414 in the game start time state-specific control process (see FIG. 69) will be described. FIG. 74 is a flow chart showing a procedure of normal process at the time of game start.

  First, the main CPU 101 determines whether the current gaming state is a bonus state (S481). In S481, when the main CPU 101 determines that the current gaming state is the bonus state (when S481 is YES), the main CPU 101 performs various lottery in the bonus state (see, for example, FIG. 33E) (S482) Note) Although not shown, when the bonus combination is determined to be an internal winning combination, the main CPU 101 performs various lottery (see, eg, FIGS. 32 and 33D) at the time of winning a bonus. Then, after the processing of S 482 or after performing various lottery at the time of winning a bonus, the main CPU 101 ends the processing during the start of the game at normal times, and also ends the control processing classified by the state of the game start.

  On the other hand, when the main CPU 101 determines in S481 that the current gaming state is not the bonus state (when S481 is NO), the main CPU 101 determines whether the current gaming state is the flag state or not. (S483). When the main CPU 101 determines in S483 that the current gaming state is the inter-flag state (when the determination in S483 is YES), the main CPU 101 ends the processing during normal game start and controls according to the start state of the game The process also ends.

  On the other hand, when the main CPU 101 determines in S483 that the current gaming state is not the flag state (that is, the bonus is not won) (in the case of NO determination in S483), the main CPU 101 selects the advantageous section transition lottery (see FIG. 33A) is performed (S484). Next, the main CPU 101 determines whether or not the advantageous section transition lottery has been won (S485). In S485, when the main CPU 101 determines that the advantageous section transition lottery has not been won (in the case of NO determination in S485), the main CPU 101 ends the processing during normal game start and the control processing according to the start state of the game Also ends.

  On the other hand, when the main CPU 101 determines in S485 that the advantageous section transition lottery has been won (when the determination in S485 is YES), the main CPU 101 performs ART stock lottery (see FIG. 33B) (S486). Next, the main CPU 101 performs random determination (see FIG. 33C) of the AT continuation possible period (S487). Next, the main CPU 101 updates the ART stock counter according to the lottery result of the ART stock lottery (S488).

  Next, the main CPU 101 determines whether the lottery result of the ART stock lottery is the ART stock winning or not (S489). In S489, when the main CPU 101 determines that the lottery result of ART stock lottery is ART stock winning (when S 489 is YES judgment), the main CPU 101 shifts from the next game to the AT gaming state (ART transition) Is set (S 490), and after the processing of S 490, the processing at the start of the game is ended normally, and the control processing classified by the state at the start of the game is also ended.

  On the other hand, when the main CPU 101 determines that the lottery result of ART stock lottery is not ART stock winning in S 489 (when S 489 is NO judgment), the main CPU 101 shifts from the next game to AT gaming state (ART non transition). After the processing of S491, the processing is ended during the game start, and the control processing classified by the game start state is also ended.

[Import priority storage process]
Next, with reference to FIG. 75, the drawing priority priority storage process performed in S212 in the main flow (see FIG. 58) will be described. FIG. 75 is a flow chart showing the procedure of the drawing priority storing process.

  First, the main CPU 101 sets "3" as the number of search reels (S621). Next, the main CPU 101 performs pull-in priority order table selection processing (S 622). In this process, a draw-in priority table (not shown) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 performs a drawing priority storage area selection process (S623). In this process, the pull-in priority data storage area of the search target reel is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs symbol code acquisition processing (S625). In this process, the symbol code is acquired with reference to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 76 described later.

  Next, the main CPU 101 performs an AND operation process (S626). In this process, the main CPU 101 performs a process of generating winning operation flag data. Details of the logical product operation processing will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 performs pull-in priority order acquisition processing (S627). In this process, the main CPU 101 sets the bit to "1" in the winning operation flag (winning combination) storing area (see FIG. 25) and sets the bit to "1" in the hit request flag storing area. With respect to the player, the drawing priority priority table (not shown) is referenced to acquire drawing priority data. The details of the pull-in priority order acquisition process will be described later with reference to FIGS. 78 and 79 described later.

  Next, the main CPU 101 stores the acquired drawing priority data in a drawing priority data storage area (not shown) in the main RAM 103 (S628). At this time, the drawing priority order data is stored in the drawing priority order data storage area so that the value of each priority order corresponds to the bit of the storage area.

  In the drawing priority order data storage area, a storage area of priority order data is provided for each type of main reel. In each drawing priority order data storage area, drawing priority order data determined according to each symbol position “0” to “19” of the corresponding main reel is stored. In the present embodiment, by referring to the pull-in priority data storage area, it is searched whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols determined based on the stop table.

  The content of the priority attraction-in data stored in the attraction priority data storage area differs depending on the type of the attraction priority table number in the attraction priority table referenced when determining the attraction priority data. Further, the higher the value of the attraction priority data, the higher the priority. By referring to the draw-in priority order data, it is possible to relatively evaluate the priorities among the symbols arranged on the circumferential surface of the main reel. That is, the symbol for which the largest value is determined as the attraction priority data is the symbol with the highest priority. Therefore, it can be said that the drawing priority order data indicates the order between the symbols arranged on the circumferential surface of the main reel. In addition, when two or more symbols with the same value of a drawing-in priority order data exist, one pattern is determined according to the priority order which a priority order table prescribes | regulates.

  Next, the main CPU 101 performs update processing of the lead-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts one from the number of symbol checks (S630). Next, the main CPU 101 determines whether the symbol check number is "0" (S631).

  In S631, when the main CPU 101 determines that the symbol check number is not “0” (when S631 is NO), the main CPU 101 returns the processing to the processing of S625, and repeats the processing of S625 and subsequent steps. On the other hand, when the main CPU 101 determines in S631 that the symbol check number is “0” (when the determination in S631 is “YES”), the main CPU 101 performs change processing of the search target reel (S632).

  Next, the main CPU 101 subtracts one from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the series of processes described above have been performed for all the main reels (S634).

  When the main CPU 101 determines in S634 that the number of search reels is not “0” (when the determination in S634 is “NO”), the main CPU 101 returns the process to the process of S622, and repeats the processes after S622. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (when the determination in S634 is “YES”), the main CPU 101 ends the drawing priority storing process and the process is a main flow (FIG. 58)).

[Symbol code acquisition processing]
Next, with reference to FIG. 76, the symbol code acquisition processing performed in S625 in the retraction priority storage processing (see FIG. 75) will be described. FIG. 76 is a flow chart showing a procedure of symbol code acquisition processing.

  First, the main CPU 101 clears the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all the storage areas in the winning operation flag storage area (see FIG. 25). Next, the main CPU 101 sets a first reel symbol arrangement table (not shown) (S642).

  Next, the main CPU 101 determines whether it is time to stop the first reel (left reel 3L) (S643).

  In S643, when the main CPU 101 determines that the first reel (the left reel 3L) is stopped (when the determination is YES in S643), the main CPU 101 performs the processing of S647 described later. On the other hand, when the main CPU 101 determines that the first reel (the left reel 3L) is not stopped at S643 (when S643 is NO), the main CPU 101 sets the second reel symbol arrangement table (not shown). (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten with the second reel symbol arrangement table.

  Next, the main CPU 101 determines whether it is time to stop the second reel (middle reel 3C) (S645).

  In S645, when the main CPU 101 determines that the second reel (the middle reel 3C) is stopped (when the determination in S645 is YES), the main CPU 101 performs the processing of S647 described later. On the other hand, when the main CPU 101 determines that the second reel (the middle reel 3C) is not stopped at S645 (when S645 is NO), the main CPU 101 sets the third reel symbol arrangement table (not shown). (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten with the third reel symbol arrangement table.

  After the processing of S646, or when S643 or S645 is determined as YES, the main CPU 101 performs symbol check processing at the time of execution of the stop operation on the reel of the stop control target, and corresponds to the symbol corresponding to the symbol acquired by the symbol check processing. A winning operation table (not shown) is obtained (S647). The symbol corresponding prize operation table is a table for making it possible to identify the type of a winning combination (symbol combination) which can be a prize if the corresponding symbol is stopped on the activated line in the stop control target reel.

  Next, the main CPU 101 sets a winning operation flag storage area (S648). Next, the main CPU 101 performs the compressed data storage processing described in FIG. 68 (S649). In this process, the main CPU 101 mainly carries out a process of transferring (expanding) the possible-to-win prize operation flag data stored in the symbol-corresponding prize actuation table to the corresponding storage area in the prize operation flag storage area.

  For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line at the time of the stop operation is "blank", symbol combinations that can be won are shown in FIGS. As shown in the figure, "C_SBB_01", "C_ transition role_03", "C_ transition role_04", and "C_CHA1".

  After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and the data length of the winning operation flag storage area (12 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and shifts the processing to S626 of the drawing priority storage processing (see FIG. 75).

Logical product operation processing
Next, with reference to FIG. 77, for example, the logical product operation process performed in S626 in the pull-in priority order storage process (see FIG. 75) will be described. FIG. 77 is a flow chart showing a procedure of logical product operation processing. The AND operation process shown in FIG. 77 is performed not only at S 626 in the pull-in priority order storage process (see FIG. 75) but also at S 686 in the pull-in priority order acquisition process described later (see FIG. Is also performed.

  In the AND operation process executed in S626 in the draw-in priority order storage process (see FIG. 75), the two data to be ANDed is stored in the winning operation flag set in S650 in the symbol code acquisition process described above. It is data of an area and data of a symbol code storage area. The former data corresponds to "logical AND destination data" described later, and the latter data corresponds to "logical AND source data" described later. Further, in this case, the number of bytes "22" of the data length (22 bytes) set in S650 during the symbol code acquisition processing described above corresponds to the "number of logical multiplications" described later.

  On the other hand, in the AND operation process executed in S686 in the pull-in priority order acquisition process (see FIG. 78 and FIG. 79 described later), the two data to be ANDed is the hit (pull-in) request flag storage area And data of the winning operation flag storage area. The former data corresponds to "logical AND destination data" described later, and the latter data corresponds to "logical AND source data" described later. Further, in this case, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag described later corresponds to “the number of logical multiplications” described later.

  First, the main CPU 101 acquires logical multiplication source data (for example, data of a symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, data of the winning operation flag storage area), and stores the calculation result as logical product destination data (S662).

  Next, the main CPU 101 adds one to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 adds one to the address of the logical multiplication destination data to be referred to (S664).

  Next, the main CPU 101 subtracts one from the number of logical products (S665). Next, the main CPU 101 determines whether the number of logical multiplications is “0” (S666).

  In S666, when the main CPU 101 determines that the number of logical multiplications is not “0” (when S666 is NO), the main CPU 101 returns the processing to the processing of S661, and repeats the processing of S661 and subsequent steps. On the other hand, when the main CPU 101 determines in S666 that the number of logical multiplications is “0” (when the determination in S666 is YES), the main CPU 101 ends the logical multiplication processing and stores the processing, for example, in the drawing priority storage. The process moves to step S627 in the process (see FIG. 75).

[Import priority acquisition process]
Next, with reference to FIG. 78 and FIG. 79, the drawing priority order acquisition process performed in S627 in the drawing priority order storing process (see FIG. 75) will be described. FIGS. 78 and 79 are flowcharts showing the procedure of the pull-in priority order acquisition process.

  First, the main CPU 101 determines whether it is time to check the right reel 3R (specific display row) (S671).

  When the main CPU 101 determines in S671 that it is not at the time of checking the right reel 3R (when the determination in S671 is NO), the main CPU 101 performs the processing of S674 described later. On the other hand, when the main CPU 101 determines in S671 that the right reel 3R is checked (when S671 is determined as YES), the main CPU 101 selects "ANY combination" in the symbol combination (winning combination) relating to the internal winning combination. It is determined whether (a predetermined combination of symbols) is included (S672). The term "ANY combination" as used herein refers to a combination in which winning is determined regardless of at least the stop symbol of the right reel 3R (a winning combination in which at least the stop symbol of the right reel 3R is an arbitrary symbol).

  When the main CPU 101 determines in S672 that the symbol combination relating to the internal winning combination does not include the "ANY combination" (when the determination of S672 is NO), the main CPU 101 performs the processing of S674 described later. On the other hand, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes the symbol "ANY combination" in S672 (when the determination of S672 is YES), the main CPU 101 selects "ANY in the prize operation flag storage area. The storage area corresponding to "combination" is masked (S673). Specifically, the main CPU 101 sets “1” to a bit corresponding to “ANY combination” in the winning operation flag storage area. In the case where the "ANY combination" is not defined in the symbol combination (winning combination) relating to the internal winning combination, the processing of S671 to S673 may be unnecessary. Also, when "ANY role" defines the stop symbol of the left reel 3L or the middle reel 3C as an arbitrary symbol, the processing of S672 and S673 is also performed when checking the left reel 3L or the middle reel 3C. It may be performed (the same applies to the processing of S681 to S683 described later).

  After the processing of S673 or when S671 or S672 is NO, the main CPU 101 adds “1” to the address of the last storage area as the address of the winning operation flag storage area (see FIG. 25). Is set, the stop prohibition data is set, and the prize operation flag data length (data length of the prize operation flag storage area: 22 bytes in the present embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which the stop operation has been detected. Also, the stop button operation state is obtained by referring to the operation stop button storage area (see FIG. 28).

  Next, the main CPU 101 subtracts one from the address of the winning operation flag storage area that has been set (-1 update) (S676). Next, the main CPU 101 generates hit request flag data from the winning operation flag storage area set and the corresponding hit request flag storage area (see FIG. 25), and based on the generated hit request flag data. A prohibited winning operation position is generated (S677).

  Next, the main CPU 101 determines whether the stop operation position is the prohibited winning operation position (S678).

  When the main CPU 101 determines in S678 that the stop operation position is not the prohibited winning operation position (when the determination in S678 is NO), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (when the determination in S678 is YES), the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop. It is determined whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when the determination of S679 is YES), the main CPU 101 performs the processing of S705 described later. On the other hand, when the main CPU 101 determines in S679 that the value of the stop button operation counter is not the value of the third stop (when S679 is NO), the main CPU 101 determines that the value of the stop button operation counter is the second stop. It is determined whether it is a value (S680).

  When the main CPU 101 determines in S680 that the value of the stop button operation counter is not the value of the second stop (when the determination in S680 is NO), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines that the value of the stop button operation counter is the value of the second stop in S 680 (when the determination in S 680 is YES), the main CPU 101 determines whether or not the right reel 3 R is stopped. It is determined (S681).

  When the main CPU 101 determines that the right reel 3R has been stopped in S681 (when the determination in S681 is YES), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines that the right reel 3R is not stopped in S681 (when the determination in S681 is NO), the main CPU 101 is a flag that may receive an interference of the hit request flag "ANY role". Whether or not (whether or not "ANY combination" is included in the symbol combination (winning combination) according to the internal winning combination) is determined (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may receive an interference of "ANY combination" (if S682 is YES), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines in S682 that the hit request flag is a flag that may receive an interference of "ANY combination" (S682: NO), the main CPU 101 determines that the current check is "ANY". It is judged whether it is at the time of the check of the hit request flag including the "combination" (S683).

  When the main CPU 101 determines in S683 that the current check is a check on the hit request flag including the "ANY combination" (when the determination in S683 is YES), the main CPU 101 performs the processing of S705 described later.

  On the other hand, when the main CPU 101 determines in S683 that the current check does not include a check on the hit request flag including "ANY combination" (S683 is NO), S678 or S680 is NO or S681. Alternatively, if the determination in S682 is YES, the main CPU 101 subtracts one from the winning operation flag data length (S684). Next, the main CPU 101 determines whether the winning operation flag data length is "0" (S685).

  In S685, when the main CPU 101 determines that the winning operation flag data length is not "0" (when the determination in S685 is NO), the main CPU 101 returns the process to the process of S676, and repeats the processes after S676.

  On the other hand, when the main CPU 101 determines that the winning operation flag data length is "0" in S685 (when S685 is YES), the main CPU 101 performs stop control pull-in request flag setting processing (S686) . In this process, for example, the main CPU 101 performs the logical product operation process described with reference to FIG. In the logical AND operation process executed in the process of S686, as described above, the data of the hit (pull-in) request flag storage area is set to the "logical AND destination data", and the data of the winning operation flag storage area is It is set in “conjunction source data”, and the number of bytes “1” of the data length (1 byte) of the RT operation combination indication flag is set in “the number of conjunctions”. The RT operation combination display flag is a storage area in which a symbol combination related to RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 1 as shown in FIG.

  Next, the main CPU 101 refers to the drawing priority order table address storage area to acquire a drawing priority order table (S687). In this process, the initial value “1 (001H)” of the drawing priority data is set to the currently set address, and any drawing priority table is acquired.

  Next, the main CPU 101 determines whether or not the data of the lead-in priority order table stored at the currently set address is the end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data of the pull-in priority order table stored at the currently set address is an end code (YES in S688), the main CPU 101 performs S705 described later. Perform the processing of On the other hand, when the main CPU 101 determines in S688 that the data in the pull-in priority order table stored at the currently set address is not an end code (S688: NO), the main CPU 101 performs a winning operation. The flag storage area is set (S689).

  Next, the main CPU 101 acquires retraction priority data based on the retraction priority table stored at the currently set address (S690). Next, the main CPU 101 sets a block counter of the pull-in priority order table (S691).

  Next, the main CPU 101 sets the number of checks in the lead-in priority order table, and adds 1 to the address of the lead-in priority order table to be referenced (+1 update) (S692).

  Next, the main CPU 101 acquires check data based on the updated address of the lead-in priority order table, and extracts check bits from the check data (S693).

  Next, the main CPU 101 determines whether the value of the extracted check bit is “1” (S694).

  When the main CPU 101 determines in S694 that the value of the extracted check bit is not “1” (when the determination in S694 is NO), the main CPU 101 performs the processing of S699 described later. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is “1” (when the determination in S694 is YES), the main CPU 101 adds 1 to the address of the lead-in priority table to be referred. The determination data is acquired from the lead-in priority order table based on the address after the update (S695).

  Next, based on the determination data acquired in S695, the main CPU 101 determines whether the currently-acquired winning operation flag data is a determination target (S696). In this process, the main CPU 101 compares the currently acquired winning operation flag data with the determination data, and determines whether the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently-acquired winning operation flag data is the determination target.

  When the main CPU 101 determines in S696 that the winning operation flag data is not a determination target (when the determination in S696 is NO), the main CPU 101 performs the processing of S699 described later. On the other hand, when the main CPU 101 determines that the winning operation flag data is the determination target in S 696 (when the determination in S 696 is YES), the main CPU 101 performs a drawing priority update data update process (S 697). In this process, the main CPU 101 updates (overwrites) the currently set attraction priority data with the attraction priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 performs check data update processing (S698). In this process, the main CPU 101 shifts the check data to the right (in the direction from bit 7 to bit 0) by one bit. In this process, "0" is set to bit 7 of the check data after shift.

  After the process of S698, or when S694 or S696 is NO, the main CPU 101 determines whether or not there is a bit to be checked (a bit for which “1” is set) in the check data (S699).

  When the main CPU 101 determines in S699 that there is no check target bit in the check data (when the determination in S699 is NO), the main CPU 101 performs the processing of S702 described later. On the other hand, when the main CPU 101 determines in S699 that there is a check target bit in the check data (if S699 is a YES determination), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update) And decrement the number of checks by one (S700).

  Next, the main CPU 101 determines whether the number of checks is “0” (S701). In S701, when the main CPU 101 determines that the number of checks is not “0” (when S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes of S698 and subsequent steps.

  On the other hand, when the main CPU 101 determines that the number of checks is "0" in S701 (when the determination in S701 is YES), the main CPU 101 checks the number of checks in the address of the prize operation flag storage area currently referenced. The address of the winning operation flag storage area is updated by addition, and the value of the block counter is decremented by 1 (S702). Next, the main CPU 101 determines whether the value of the block counter is “0” (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (when the determination in S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes of S692 and subsequent steps.

  On the other hand, when the main CPU 101 determines that the value of the block counter is “0” in S703 (when the determination in S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred (+1 update) ) (S704). Then, after the processing of S704, the main CPU 101 returns the processing to the processing of S688, and repeats the processing after S688.

  Here, returning to the processing of S679, S683 or S688 again, if S679, S683 or S688 is determined as YES, the main CPU 101 sets the retraction priority data set at this time as the final retraction priority data. It sets (S705). When the determination in S679 or S683 is YES, the main CPU 101 sets “0 (00H)” as the final lead-in priority data. In this case, since the end code is assigned to the loading priority data "0 (00H)", no loading data (stop prohibition) is set. Then, after the processing of S705, the main CPU 101 ends the drawing priority acquisition process, and shifts the processing to S628 of the drawing priority storing process (see FIG. 75).

[Reel stop control processing]
Next, with reference to FIG. 80, the reel stop control process performed in S213 in the main flow (see FIG. 58) will be described. FIG. 80 is a flowchart showing the procedure of the reel stop control process.

  First, the main CPU 101 performs a reel stop enable signal OFF process (S711). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal OFF data. Also, this process is performed using the non-specified work area of the main RAM 103.

  Next, the main CPU 101 determines whether or not the rotational speeds of all the reels have reached a predetermined constant speed (whether or not the "constant speed" has been reached) (S712). When the main CPU 101 determines in S712 that the rotational speeds of all the reels are not "constant speed" (when the determination in S712 is NO), the main CPU 101 repeats the processing of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotational speeds of all the reels have become "constant speed" (when the determination in S712 is YES), the main CPU 101 performs reel stop enable signal ON processing (S713). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal ON data. Also, this process is performed using the non-specified work area of the main RAM 103.

  Next, the main CPU 101 determines whether a valid stop button has been pressed (S714).

  When the main CPU 101 determines that the effective stop button has not been pressed in S714 (when the determination in S714 is NO), the main CPU 101 returns the process to the process of S713, and repeats the processes after S713. On the other hand, when the main CPU 101 determines that the effective stop button has been pressed in S714 (when the determination in S 714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 28). The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines a search target reel from the operation stop button (S716). Further, in this process, an address (head address) setting process of a spinning drum control data storage area in which reel control management information of a search target reel is stored is also performed.

  Next, the main CPU 101 performs reel stop enable signal OFF processing (S717). This process is performed using the non-specified work area of the main RAM 103 as in the above-described S711. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 performs reel stop selection processing (S719). Although the detailed description is omitted, in this process, the main CPU 101 performs a process of selecting the number of sliding symbols.

  Next, the main CPU 101 determines a planned stop position based on the stop start position and the number of sliding symbols determined in S719, and stores the determined planned stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding symbols to the stop start position, and sets the result of the addition as the planned stop position.

  Next, the main CPU 101 executes symbol code storage processing (S721). In this process, the symbol code corresponding to the planned stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether the reel to be controlled is the final stop (third stop) reel (S722). In this processing, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button inactivity counter, and the value of the stop button inactivity counter is When it is "0", it is determined that the reel to be controlled is the reel of the final stop.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stop reel (when the determination in S722 is NO), the main CPU 101 performs control change processing (S723). In this process, the stop information group used to stop the reel is updated when it is at the specific stop position. Next, the main CPU 101 performs the retraction priority storage process described with reference to FIG. 75 (S724).

  Next, the main CPU 101 performs stop interval remaining time standby processing (S725). In this process, the main CPU 101 performs a standby process until a predetermined predetermined reel stop interval time has elapsed. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing of S711 and thereafter.

  Here again, returning to the processing of S722, when the main CPU 101 determines that the reel to be controlled is the final stop reel in S722 (when the determination of S722 is YES), the main CPU 101 excites all the reels. It is determined whether or not is in the stop state (S726). When the main CPU 101 determines in S726 that the excitation of all the reels is not in the stop state (when the determination in S726 is NO), the main CPU 101 repeats the processing of S726.

  On the other hand, when the main CPU 101 determines in S726 that the excitation of all the reels is in the stop state (when the determination in S726 is YES), the main CPU 101 keeps the stop button subjected to the third stop operation in the on state. It is determined whether (the stop button has not been released) (S727). In S727, when the main CPU 101 determines that the stop button subjected to the third stop operation remains in the on state (when the determination in S 727 is YES), the main CPU 101 repeats the process of S 727. On the other hand, when the main CPU 101 determines in S727 that the stop button subjected to the third stop operation is not in the on state (when S727 is NO), the main CPU 101 ends the reel stop control processing and performs processing. Move to S214 in the main flow (see FIG. 58).

[Paid search process]
Next, with reference to FIG. 81, the winning search processing performed in S214 in the main flow (see FIG. 58) will be described. FIG. 81 is a flowchart showing the procedure of the winning search process.

  First, the main CPU 101 transfers and stores data of each storage area stored in the symbol code storage area (see FIG. 30) in the corresponding storage area of the winning operation flag storage area (see FIG. 25) (S761) . At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets the address of the number-of-payouts data table (not shown) that defines the number of payouts (see FIG. 25) of the winning combinations (symbol combination) in the HL register (S762). Next, the main CPU 101 sets the number-of-payouts table number (for example, “5” in the present embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

  Next, based on the address set in the HL register, the main CPU 101 sets data of the number of paid-out medals (in the present embodiment, one, three, five and nine sheets in the present embodiment) in the C register. Then, the judgment target data is set in the A register, and "2" is added (+2 updated) to the address set in the HL register (S764). In the payout number data table, data on the payout number of medals is defined as, for example, “the number of payouts (1, 3, 5 or 9) * 2 + 0”. Also, in the following, data "0" in the data "the number of payouts (1, 3, 5, or 9) * 2 + 0" of the number of medals paid out set in the C register is referred to as "determination bit". This determination bit is information indicating whether or not it is a determination target block of a winning search.

  Next, the main CPU 101 extracts the value of the determination bit from the data of the number of paid-out medals set in the C register (S765). Next, the main CPU 101 determines whether or not the block is a determination target block based on the value of the extracted determination bit (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is “1”. In the present embodiment, regardless of the number of medals paid out, the value of the determination bit is always defined as “0”, so the process of S766 always determines NO.

  In S766, when the main CPU 101 determines that the block is not a determination target block (in the case of NO determination in S766), the main CPU 101 performs the process of S768 described later. On the other hand, when the main CPU 101 determines in S766 that the block is a determination target block (when S766 is a YES determination), the main CPU 101 subtracts one from the address of the winning operation flag storage area set in the DE register (- 1) to update (S767).

  After the processing of S767 or when the determination of S766 is NO, the main CPU 101 extracts data of the storage area designated by the address of the winning operation flag storage area set in the DE register as determination data (S768).

  Next, the main CPU 101 determines whether or not the determination result is a winning based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, when the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a winning.

  In S769, when the main CPU 101 determines that the determination result is not a winning (in the case of NO determination in S769), the main CPU 101 performs the processing of S776 described later. On the other hand, when the main CPU 101 determines in S769 that the result of the determination is a winning (when the determination in S769 is YES), the main CPU 101 plays three games (the number of medal bets is three) It is determined whether or not (S 770).

  In S770, when the main CPU 101 determines that the current game is a three-card game (when the determination in S 770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, when the main CPU 101 determines in S770 that the current game is not a three-game game (when S770 is NO), the main CPU 101 pays out a two-card game (a game in which the number of medals bet is two). The number is set in the C register (S771). In addition, in this embodiment, since there is no 2 sheet game, the process of S770 and S771 becomes unnecessary.

  After the process of S771 or when the determination of S770 is YES, the main CPU 101 performs an update process of the number of dispensed sheets (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current value of the winning number counter, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether the value of the payout number is less than the maximum payout number “9” (S773).

  When the main CPU 101 determines in S773 that the value of the number of payouts is less than the maximum number of payouts “9” (when the determination in S773 is YES), the main CPU 101 performs the processing of S775 described later. On the other hand, when the main CPU 101 determines in S773 that the value of the number of payouts is not less than the maximum number of payouts “9” (when the determination of S773 is NO), the main CPU 101 sets the maximum number of payouts “9” as the number of payouts. (S774).

  After the processing of S774 or when the determination of S773 is YES, the main CPU 101 stores the number of payouts in the winning number counter (S775).

  After the processing of S775 or when S769 is NO, the main CPU 101 determines whether or not there is another winning (S776). In S776, when the main CPU 101 determines that there is another winning (if YES in S776), the main CPU 101 returns the process to S769, and repeats the processes of S769 and subsequent steps.

  On the other hand, when the main CPU 101 determines that there is no other winning in S776 (if NO in S776), the main CPU 101 subtracts 1 from the value of the winning search counter (-1 update) (S777). Note that, as in the present embodiment, when there is one valid line, a plurality of small winning combinations do not win in duplicate, so the determination processing in S776 is always determined as NO.

  Next, the main CPU 101 determines whether or not the value of the winning search counter is "0" (S778).

  In S778, when the main CPU 101 determines that the value of the winning search counter is not “0” (when the determination in S778 is NO), the main CPU 101 returns the process to the process of S764 and repeats the processes after S764. On the other hand, when the main CPU 101 determines in S778 that the value of the winning search counter is "0" (when the determination in S778 is YES), the main CPU 101 ends the winning search processing, and the main flow of processing (FIG. 58)) to the processing of S215 in FIG.

[Illegal hit check process]
Next, with reference to FIG. 82, the illegal hit check process performed in S215 in the main flow (see FIG. 58) will be described. FIG. 82 is a flowchart of an illegal hit check process. It should be noted that an illegal hit is a special prize winning number and a minor winning number (internal winning combination) which are extracted in the internal lottery process (see FIG. 66) and stored in the symbol number storing area in the symbol setting process (see FIG. 67). Based on this, it is a term indicating that the left reel 3L, the middle reel 3C and the right reel 3R are stopped on the effective line (symbol combination failure) by a combination of symbols that can not be established.

  First, the main CPU 101 sets the address of the winning operation flag storage area (see FIG. 25) (S781). Next, the main CPU 101 sets the size of the winning operation flag storage area (the number of bytes, “22” in the present embodiment) to the value of the check counter (S 782).

  Next, based on the address of the winning action flag storage area currently set, the main CPU 101 stores the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storing area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 combines data of the winning combination (winning operation flag data) stored in the address of the currently set winning operation flag storage area and data of the internal winning combination (hit request flag data) (see FIG. S784).

  In the combining process, first, the main CPU 101 obtains an exclusive OR of data of winning combination (winning operation flag data) and data of internal winning combination (hit request flag data). Next, the main CPU 101 obtains the logical product of the calculated exclusive OR calculation result and the winning combination data (prize operation flag data), and sets the logical calculation result as the synthesis result. When no illegal hit error has occurred, the value of the synthesis result is “0”.

  Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the combining process of S784 (S785).

  When the main CPU 101 determines in S785 that an illegal hit error has not occurred (when the determination in S785 is NO), the main CPU 101 updates the address of the winning operation flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts one from the value of the check counter (S787). Next, the main CPU 101 determines whether the value of the check counter is “0” (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (when the determination in S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes of S783 and subsequent steps. On the other hand, when the main CPU 101 determines that the value of the check counter is “0” in S 788 (when the determination in S 788 is YES), the main CPU 101 ends the illegal hit check processing, and the main flow of FIG. 58)) to the process of S216.

  Here, returning to the processing of S 785 again, when the main CPU 101 determines that an illegal hit error has occurred in S 785 (when the determination in S 785 is YES), the main CPU 101 performs the error processing described in FIG. (S 789). As a result of this processing, a two-character "EE" indicating the occurrence of an illegal hit error is displayed as error information on the 2-digit 7-segment LED (for both display of the number of payouts and error display) included in the information display 6. Error display data is output. The state of occurrence of an illegal hit error (error state) is canceled by pressing the reset switch 76 (see FIG. 6).

  Next, the main CPU 101 clears the value of the winning number counter and the data of the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 58).

  In the present embodiment, as shown in FIG. 25, since the configuration of the winning operation flag storage area (display combination storing area) is the same as that of the hit request flag storage area (internal winning combination storing area), the winning operation flag The hit request flag storage area and the winning operation flag storage area, which are disposed in the main RAM 103 at the time of combining processing of the combination of the storage area and the internal winning combination, can be configured identically. Therefore, the calculation result (combining result of the data of the winning combination and the data of the internal winning combination) in the illegal hit check process of the present embodiment is simply the logical product of the data of the winning combination and the data of the internal winning combination. (E.g., execute with an "AND" instruction). As a result, in the present embodiment, the illegal hit check process can be streamlined and simplified, the free space of the main control program can be secured (increased), and the playability can be increased using the increased free space. It becomes possible to raise.

[Paid check / medal payout process]
Next, with reference to FIG. 83, the winning check and medal payout process performed in S216 in the main flow (see FIG. 58) will be described. FIG. 83 is a flowchart showing the procedure of the winning check and medal payout process.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub control circuit 200. The winning operation command includes parameters for specifying a winning operation flag (display combination) and the like.

  Next, the main CPU 101 performs the communication data storage processing described in FIG. 52 (S802). By this processing, the winning operation command data is stored in the communication data storage area provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is “0” (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (in the case of YES determination in S803), the main CPU 101 ends the winning check and medal payout processing, and the main flow ( The process proceeds to step S217 in FIG.

  On the other hand, when the main CPU 101 determines in S803 that the value of the winning number counter is not "0" (in the case of NO determination in S803), the main CPU 101 determines that the credit number of medals (stored number) is the upper limit number In the embodiment, it is determined whether the number is 50 or more) (S804).

  In S804, when the main CPU 101 determines that the credit number of medals is not the upper limit or more (when S804 is NO), the main CPU 101 adds 1 to the value of the credit counter (+1 update) S 805). The added value of the credit counter is displayed by a 2-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs medal payout number check processing (S806). The details of the medal payout number check process will be described later with reference to FIG. 84 described later.

  Next, the main CPU 101 determines whether or not the payout of medals is completed (S807). In S807, when the main CPU 101 determines that the payout of medals is completed (S807: YES), the main CPU 101 ends the winning check and medal payout processing, and the processing is in the main flow (see FIG. 58). Transfer to the process of S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not been completed (S807: NO), the main CPU 101 performs payout interval standby processing (S808). In this process, the main CPU 101 continues until a preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt process (1.1172 msec cycle) described later with reference to FIG. 92) elapses. To wait. Then, after the processing of step S808, the main CPU 101 returns the processing to the processing of step S803, and repeats the processing of step S803 and subsequent steps.

  Here, returning to the processing of S804 again, when the main CPU 101 determines that the credit number of medals is equal to or more than the upper limit number (50) in S804 (in the case of YES determination in S804), the main CPU 101 A payout process of medals is performed (S809). As a result of this processing, medals which have not been stored as the number of credits are paid out. Also in the process of S809, the process of S806 to 806 may be repeated each time one medal is paid out, until the payout of the medal is completed. Then, after the processing of S809, the main CPU 101 ends the winning check and medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 58).

[Medal payout number check process]
Next, with reference to FIG. 84, the medal payout number check process performed in S806 in the prize check and medal payout process (see FIG. 83) will be described. FIG. 84 is a flow chart showing the procedure for checking the number of medals paid out.

  First, the main CPU 101 adds “1” (+1 update) to the value of the medal OUT counter (S811). The medal OUT counter is a counter for counting the number of medals paid out. Next, the main CPU 101 adds “1” (+1 update) to the value of the payout number counter (S812). The payout number counter is a counter for counting the payout number of medals.

  Next, the main CPU 101 performs a payout number 7SEG display process (S813). In this processing, the main CPU 101 performs control processing to display the value of the payout number counter using a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

  Next, the main CPU 101 performs update processing of the winning combination end number counter (S814). In addition, the bonus game end number counter is a bonus game by the bonus combination winning (combination of symbol combinations “C_SBB_01”, “C_SBB_02”, “C_BB1”, “C_BB2”, “C_BB3” or “C_BB4” is completed) When the game starts, the number of payouts that can be paid out in the bonus game is set (see FIG. 85 described later), and the remaining number of medals paid out during the bonus game is counted to determine the end of the bonus game (described later) 85 (see S822 in FIG. 85) of FIG. In this process, the main CPU 101 compares the value of the combination ending number counter with its lower limit "0", and if the value of the combination ending number counter is larger than the lower limit "0", the combination ending number The value of the counter is decremented by 1 (-1 update), and when the value of the combination ending sheet number counter is less than the lower limit value "0", the value of the combination ending sheet number counter is held at "0". The number of payouts set in the combination ending number counter does not necessarily become the number actually paid out to the player. For example, 216 combination ending number counters are set, and the combination ending number counter is 215. When the winning combination of nine is won, the actual number of payouts to be paid out is 225. The combination run number counter becomes “0” after 216 sheets are paid out, and thereafter, the lower limit “0” of the value of the combination run number counter is maintained.

  Next, the main CPU 101 subtracts 1 from the value of the winning number counter (-1 update) (S815).

  Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command to be transmitted to the sub control circuit 200. The credit information command is configured to include a parameter for specifying the number of credits of medals.

  Next, the main CPU 101 performs the communication data storage processing described in FIG. 52 (S817). By this processing, credit information command data is stored in the communication data storage area provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. Then, after the process of S817, the main CPU 101 ends the medal paid out number check process, and shifts the process to the process of S807 in the prize check and medal payout process (see FIG. 83).

[BB check processing]
Next, the BB check process performed in S217 in the main flow (see FIG. 58) will be described with reference to FIG. FIG. 85 is a flowchart of the BB check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). When the main CPU 101 determines in S821 that the current gaming state is not the bonus state (when the determination in S821 is NO), the main CPU 101 performs the processing of S831 described later.

  On the other hand, when the main CPU 101 determines in S821 that the current gaming state is the bonus state (when the determination in S821 is YES), the main CPU 101 determines whether the value of the combination ending number counter is "0" or less It is determined whether or not (S822). When the main CPU 101 determines in S822 that the value of the combination ending number counter is not “0” or less (S822 is NO), the main CPU 101 ends the BB check processing, and the main flow of processing (FIG. 58) in the processing of S218).

  On the other hand, when the main CPU 101 determines that the value of the combination ending number counter is less than or equal to “0” in S822 (if YES in S822), the main CPU 101 performs bonus end processing (S823). In this process, the main CPU 101 clears various information in the bonus state. Next, the main CPU 101 sets the RT2 state flag to the on state (S824). In this process, the main CPU 101 sets the RT state after the end of the bonus state to the RT2 state. Then, after the processing of S824, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 58).

  Here again, returning to the processing of S 821, if the determination of S 821 is NO, the main CPU 101 selects the symbol combination relating to the BB combination (combination “C_SBB_01”, “C_SBB_02”, “C_BB1”, “C_BB2”, “C_BB3” or It is determined whether or not the symbol combination "C_BB4" is displayed (S825). In S825, when the main CPU 101 determines that the symbol combination relating to the BB combination is not displayed (when S825 is NO), the main CPU 101 ends the BB check processing, and the main flow (see FIG. 58). Transfer to the processing of S218 in the inside.

  On the other hand, when the main CPU 101 determines in S825 that the symbol combination relating to the BB combination is displayed (when the determination in S825 is YES), the main CPU 101 performs bonus operation processing (S826). In this process, various processes necessary to start the operation of the bonus, such as setting the bonus state to the game state of the next game, are performed. Next, the main CPU 101 sets the value of the combination ending number counter to a predetermined value (the number of payouts serving as a bonus ending trigger: in this embodiment, "297" in SBB and BB1, "216" in BB2 and BB3, and "63" in BB4. ") Is set (S827). Next, the main CPU 101 sets the RT4 state flag to the off state (S828). In this process, the main CPU 101 clears the RT state before the start of the bonus state. Then, after the processing of S828, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 58).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 58) will be described with reference to FIG. FIG. 86 is a flowchart of the RT check process.

  First, the main CPU 101 determines whether the current gaming state is in the bonus state (S 831). When the main CPU 101 determines in S831 that the current gaming state is in the bonus state (when the determination in S831 is YES), the main CPU 101 ends the RT check processing, and the main flow (see FIG. 58). Move to the processing of S219 in the inside.

  On the other hand, when the main CPU 101 determines in S831 that the current gaming state is not in the bonus state (when the determination in S831 is NO), the main CPU 101 determines whether the RT state is the RT4 state (inter-flag state). (S832). When the main CPU 101 determines in S832 that the RT state is the RT4 state (when S832 is YES), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 58). Transfer to the processing of

  On the other hand, when the main CPU 101 determines in S832 that the RT state is not the RT4 state (in the case of NO determination in S832), the main CPU 101 selects a combination of symbols relating to the shifting combination (combination “C_shifting combination _01” to “C_ It is determined whether or not the symbol combination of the transition combination _04 is displayed (S833). When the main CPU 101 determines in S833 that the combination of symbols relating to the transition combination has been displayed (when the S833 is a YES determination), the main CPU 101 sets the RT0 state flag to the on state (S834). In this case, other RT state flags are set to the off state. By this processing, the RT state becomes the RT0 state. Then, after the processing of S834, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 58).

  On the other hand, when the main CPU 101 determines in S833 that the combination of symbols relating to the transition combination has not been displayed (S833 is NO determination), the main CPU 101 selects a combination of symbols relating to the transition (combination “R_ transition It is determined whether or not the symbol combination of "_01" to "R_transition eye_04" is displayed (S835). When the main CPU 101 determines that the combination of symbols relating to the transition has not been displayed in S 835 (when S 835 is NO determination), the main CPU 101 selects the combination of symbols relating to the RT1 transition lip (combination “C_CUREP”, “ It is determined whether or not the symbol combination of C_RT1 transition _1 _01 to “C_RT1 transition _1 _04” and “C_RT1 transition _2” is displayed (S 836).

  When the main CPU 101 determines that the combination of symbols relating to the transition is displayed in S 835 (when S 835 is a YES determination), and in S 836 the combination of symbols relating to the RT1 transition lip is displayed When the main CPU 101 determines (in the case where the determination of S 835 is YES), the main CPU 101 sets the RT 1 state flag to the on state (S 837). In this case, other RT state flags are set to the off state. By this processing, the RT state becomes the RT1 state. Then, after the processing of S837, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 58).

  On the other hand, when the main CPU 101 determines that the combination of symbols relating to the RT1 transition ripple is not displayed in S 836 (when S 835 is NO determination), the main CPU 101 selects the combination of symbols relating to the RT 2 transition ripple (combination “C_RT2 It is determined whether or not the combination of symbols of transition _1 _ 01 to C C_RT 1 transition _1 _ 08 'and' C_RT 2 transition _2 'is displayed (S 838). When the main CPU 101 determines in S838 that the combination of symbols relating to the RT2 transition ripple is displayed (when the determination in S838 is YES), the main CPU 101 sets the RT2 status flag to the on state (S839). In this case, other RT state flags are set to the off state. By this processing, the RT state becomes the RT2 state. Then, after the processing of S839, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 58).

  On the other hand, when the main CPU 101 determines that the combination of symbols relating to the RT2 transition ripple is not displayed in S838 (when S838 is NO determination), the main CPU 101 selects the combination of symbols relating to the RT3 transition ripple (combination “C_RT3 It is determined whether or not a combination of symbols of transition _1 _ 01 to “C_RT 3 transition _1 _ 04” is displayed (S 840). In S840, when the main CPU 101 determines that the combination of symbols relating to the RT3 transition ripple is displayed (when S840 is a YES determination), the main CPU 101 sets the RT3 state flag to the on state (S841). In this case, other RT state flags are set to the off state. By this processing, the RT state becomes the RT3 state. Then, after the processing of S841, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 58). On the other hand, when the main CPU 101 determines that the combination of symbols relating to the RT3 transition ripple is not displayed in S 840 (when S 840 is NO determination), the main CPU 101 ends the RT check processing, and the main flow of processing ( The process proceeds to step S219 in FIG.

[Control processing by end of game state]
Next, with reference to FIG. 87, the end-of-game state control processing executed in S219 in the main flow (see FIG. 58) will be described. Note that FIG. 87 is a flow chart showing the procedure of the game end state control process.

  First, the main CPU 101 performs common processing when the game is over (S851). In addition, the details of the game end common process will be described later with reference to FIG. 88 described later.

  Next, the main CPU 101 determines whether the current gaming state is the AT gaming state (S852). In S852, when the main CPU 101 determines that the current gaming state is not the AT gaming state (when S852 is NO), the main CPU 101 shifts the processing to S854 described later.

  On the other hand, when the main CPU 101 determines in S852 that the current gaming state is the AT gaming state (when the determination in S852 is YES), the main CPU 101 performs an AT-during-AT process (S853). In addition, the details of the in-AT processing during the game end will be described later with reference to FIG. 89 described later. Then, after the processing of S853, the main CPU 101 ends the control processing classified by game end state, and shifts the processing to S201 of the main flow (see FIG. 58).

  When the determination in S852 is NO, the main CPU 101 determines whether the current gaming state is the ART preparation state (S854). In S854, when the main CPU 101 determines that the current gaming state is not the ART preparation state (when S854 is NO), the main CPU 101 shifts the processing to S856 described later.

  On the other hand, when the main CPU 101 determines that the current gaming state is the ART preparation state in S 854 (if S 854 is a YES determination), the main CPU 101 performs ART preparation in progress processing at the game end (S 855). In this process, the main CPU 101 executes various processes for executing various controls in the ART preparation state described using FIG. Then, after the process of S855, the main CPU 101 ends the game end state control process and shifts the process to S201 of the main flow (see FIG. 58).

  If S854 is NO, the main CPU 101 determines whether the current gaming state is the ART1 gaming state (S856). In S856, when the main CPU 101 determines that the current gaming state is not the ART1 gaming state (when the determination in S856 is NO), the main CPU 101 shifts the processing to S858 described later.

  On the other hand, when the main CPU 101 determines that the current gaming state is the ART 1 gaming state in S 856 (when the determination in S 856 is YES), the main CPU 101 performs ART 1 inside processing when the game is over (S 857). In addition, the details of the processing during ART1 at the end of the game will be described later with reference to FIG. 90 described later. Then, after the process of S857, the main CPU 101 ends the game end state control process and shifts the process to S201 of the main flow (see FIG. 58).

  If S856 is NO, the main CPU 101 determines whether the current gaming state is ART2 to ART4 gaming state (S858). When the main CPU 101 determines in S858 that the current gaming state is not the ART2 to ART4 gaming state (when the determination in S858 is NO), the main CPU 101 shifts the processing to S860 described later.

  On the other hand, when the main CPU 101 determines in S858 that the current gaming state is the ART2 to ART4 gaming state (when the S858 is determined as YES), the main CPU 101 performs an ART2 to 4 processing at the game end (S859) ). In this process, the main CPU 101 executes various processes for executing various controls in the ART2 to ART4 gaming state described with reference to FIGS. Then, after the process of S859, the main CPU 101 ends the game end state control process, and shifts the process to S201 of the main flow (see FIG. 58).

  If the determination in S858 is NO, the main CPU 101 determines whether the current gaming state is the CZ1 or CZ2 gaming state (S860). When the main CPU 101 determines in S860 that the current gaming state is not the CZ1 or CZ2 gaming state (when the determination in S860 is NO), the main CPU 101 shifts the processing to S862 described later.

  On the other hand, when the main CPU 101 determines that the current gaming state is the CZ1 or CZ2 gaming state in S860 (when the S860 is determined as YES), the main CPU 101 performs the processing during CZ1 and CZ2 at the end of the game (S861) ). In this process, the main CPU 101 executes various processes for executing various controls in the CZ1 or CZ2 gaming state described with reference to FIGS. 45 and 46. Then, after the process of S861, the main CPU 101 ends the game end state control process, and shifts the process to S201 of the main flow (see FIG. 58).

  If the determination in S860 is NO, the main CPU 101 performs a normal middle processing at the end of the game (S862). In addition, the details of the processing at the end of the game will be described later with reference to FIG. 91 described later. Then, after the process of S 862, the main CPU 101 ends the game end state control process, and shifts the process to S 201 of the main flow (see FIG. 58).

[Common processing at the end of the game]
Next, with reference to FIG. 88, a game end common process performed in S851 in the game end state control process (see FIG. 87) will be described. FIG. 88 is a flowchart showing the procedure of the game end common process.

  First, the main CPU 101 determines whether the section of the current game is in an advantageous section (S871). When the main CPU 101 determines in S871 that the section of the current game is not in the advantageous section (when the determination in S871 is NO), the main CPU 101 shifts the processing to S876 described later.

  On the other hand, when the main CPU 101 determines in S871 that the section of the current game is in the advantageous section (when the determination in S871 is YES), the main CPU 101 determines whether the value of the advantageous section counter has become “1500”. It is determined (S872). When the main CPU 101 determines in S872 that the value of the advantageous section counter is not “1500” (when the determination of S872 is NO), the main CPU 101 shifts the processing to S876 described later.

  On the other hand, when the main CPU 101 determines in S872 that the value of the advantageous section counter has become “1500” (when the determination in S872 is YES), the main CPU 101 clears all the various counters and various states regarding the advantageous section ( S873). In this process, the main CPU 101 clears, for example, the ART stock counter, the counter for managing the number of times of various games, and information on various gaming states related to the game, and each gaming state in the advantageous section is forcibly ended in the game. Control to

  Next, when the external signal 1 is in the on state, the main CPU 101 turns off the external signal 1 (S874). Next, the main CPU 101 sets the normal gaming state from the next game (S875). That is, the main CPU 101 shifts the game section to an advantageous section or a normal section.

  If S871 is NO, if S872 is NO, and after S875, the main CPU 101 determines whether the ART gaming state has been started (S876). That is, the main CPU 101 determines whether or not the game in which the ART 1 to ART 4 gaming state has started (including the case where the ART stock is released and the new ART gaming state starts during the ART gaming state) is ended. Do. In S876, when the main CPU 101 determines that the ART gaming state has been started (S876: YES), the main CPU 101 switches the external signal 1 from the off state to the on state (S877), and common processing at the game end The process ends, and the process is transferred to S852 in the game-by-game state control process (see FIG. 87).

  On the other hand, when the main CPU 101 determines in S876 that the ART gaming state has not been started (when the determination in S876 is NO), the main CPU 101 determines whether the ART gaming state has ended (S878). That is, the main CPU 101 determines whether or not the game whose period is over in the ART1 to ART4 gaming state (when the ART stock is discharged and a new ART gaming state is started is ended) is ended. Do. In S878, when the main CPU 101 determines that the ART gaming state has ended (when S878 is determined as YES), the main CPU 101 switches the external signal 1 from the on state to the off state at the start of the next game (S879). The end time common process is ended, and the process is shifted to S852 in the game end time control process (see FIG. 87).

  That is, in the present embodiment, for example, when there is an ART stock of "ART 1" and the ART stock of the "ART 1" is released from the ART preparation state to shift to the ART 1 gaming state, the first gaming of the ART 1 gaming state At the end, the external signal 1 is controlled from the off state to the on state. Then, at the end of the last game of the ART1 gaming state, the external signal 1 is controlled from the on state to the off state at the start of the next game. Here, when none of the ART stocks are present, the external signal remains in the OFF state. On the other hand, when there is one or more ART stocks, the ART gaming state based on the ART stock being released from the next game of the ART1 gaming state is started, so the ART gaming state started At the end of the first game, the external signal is controlled from the off state to the on state. In this way, even when the ART gaming state occurs continuously (so-called "connected"), this is appropriately transmitted to the outside by using the control of the on / off state of the external signal 1. It is possible to

  On the other hand, when the main CPU 101 determines in S878 that the ART gaming state has not ended (when the determination in S878 is NO), the main CPU 101 determines whether the bonus state has been started (S880). That is, the main CPU 101 determines whether or not it is time to end the game in which the flag state has been shifted to the bonus state. In S880, when the main CPU 101 determines that the bonus state has been started (when S880 is YES), the main CPU 101 turns the external signal 2 from the off state to the on state (S881), and the external signal 1 is on. If there is, the external signal 1 is turned off (S 882). That is, when external signal 1 is in the on state (in the ART gaming state), main CPU 101 starts outputting external signal 2 and also outputs external signal 1 when it is in the bonus state. It will end once. The output of the external signal 1 is resumed (changed from the off state to the on state) when the state changes from the ART preparation state to the ART gaming state again after the end of the bonus state (if YES in S876). Then, after the process of S 880, the main CPU 101 ends the game end common process and shifts the process to S 852 of the game end state control process (see FIG. 87).

  On the other hand, when the main CPU 101 determines in S880 that the bonus state has not been started (when the determination in S 880 is NO), the main CPU 101 determines whether the bonus state has ended (S883). That is, the main CPU 101 determines whether or not it is at the end of the game which has shifted from the bonus state to the bonus non-winning state. When the main CPU 101 determines in S883 that the bonus state has ended (when the determination in S883 is YES), the main CPU 101 switches the external signal 2 from the on state to the off state (S884), and ends the common processing at the end of the game. Then, the process is transferred to S852 in the game-by-game state control process (see FIG. 87). On the other hand, when the main CPU 101 determines that the bonus status has not ended in S883 (when the determination in S883 is NO), the main CPU 101 ends the common processing when the game is over, and the processing is processed according to the game completion state Move to S852 of (see FIG. 87).

[At the end of game processing during AT]
Next, with reference to FIG. 89, the game end time AT process which is performed in S853 in the game end time state control process (see FIG. 87) will be described. FIG. 89 is a flow chart showing a procedure of in-AT processing during the game end.

  First, the main CPU 101 determines whether or not the bonus state has ended (S1001). That is, the main CPU 101 determines whether or not it is at the end of the game which has shifted from the bonus state to the bonus non-winning state. When the main CPU 101 determines that the bonus state has not ended in S1001 (when the determination in S1001 is NO), the main CPU 101 shifts the processing to S1004 described later. Although not shown, the main CPU 101 does not perform each processing being processed during AT at the end of the game when it is in the inter-flag state and the bonus state.

  On the other hand, when the main CPU 101 determines that the bonus state has ended in S1001 (when the determination in S1001 is YES), the main CPU 101 determines whether the ART stock number is 1 or more (S1002). That is, the main CPU 101 determines whether there is one or more ART stocks. When the main CPU 101 determines in S1002 that the ART stock number is not 1 or more (when S1002 is NO), the main CPU 101 ends the at-game end AT processing, and the end-of-game time-dependent control processing (FIG. See also 87). That is, the main CPU 101 shifts the gaming state to a bonus non-winning state of AT gaming state.

  On the other hand, when the main CPU 101 determines in S1002 that the ART stock number is 1 or more (when the determination in S1002 is YES), the main CPU 101 sets an ART preparation state from the next game (S1003). That is, the main CPU 101 shifts the gaming state to a bonus non-winning state of ART preparation state. Then, after the processing of S1003, the main CPU 101 ends the at-AT time AT processing, and the end-of-game control processing (see FIG. 87).

  When the main CPU 101 determines in S1001 that the bonus state has not ended (when the determination in S1001 is NO), the main CPU 101 determines whether the AT continuation possible period has been consumed (S1004). That is, in the AT gaming state, the main CPU 101 determines whether or not the number of games for the AT continuation possible period determined as a result of the AT continuation possible period lottery (or AT continuation period re-lottery) has been performed. In S1004, when the main CPU 101 determines that the AT continuation possible period has not been digested (S1004 is NO determination), the main CPU 101 ends the processing at the end of the game during AT, and the control processing according to the end of the game (See FIG. 87) also ends.

  On the other hand, when the main CPU 101 determines in S1004 that the AT continuation possible period has been consumed (YES in S1004), the main CPU 101 determines whether the number of bell navigation occurrences is 1 or more (S1005). . In S1005, when the main CPU 101 determines that the number of bell navigation occurrences is not 1 or more (that is, 0) (when S1005 is NO), the main CPU 101 shifts the processing to S1009 described later.

  On the other hand, when the main CPU 101 determines that the number of bell navigation occurrences is 1 or more in S1005 (when the determination in S1005 is YES), the main CPU 101 determines whether the ART stock number is 1 or more (S1006). ). In S1006, when the main CPU 101 determines that the ART stock number is 1 or more (when S1006 is determined as YES), the main CPU 101 sets an ART preparation state from the next game (S1007), and at the time of the game end AT The processing ends, and the game end state control processing (see FIG. 87) also ends. On the other hand, when the main CPU 101 determines in S1006 that the ART stock number is not 1 or more (S1006 is NO), the main CPU 101 sets the normal gaming state from the next game (S1008), and the AT at the game end. The middle processing ends, and the game end state control processing (see FIG. 87) also ends.

  In S1005, when the main CPU 101 determines that the number of bell navigation occurrences is not 1 or more (that is, 0) (when S1005 is NO), the main CPU 101 determines that the value of the AT continuation possible period counter is "32". It is determined whether it has become (S1009). That is, the main CPU 101 proceeds in the AT gaming state (more specifically, the AT gaming state (ART non transition)), and 32 games have passed without any notification of the pushing order (bell navigation) of the pushing order small part being performed. Determine if it has been. In S1009, when the main CPU 101 determines that the value of the AT continuation possible period counter is not "32" (when S1009 is NO), the main CPU 101 ends the processing during AT at the end of the game, and the game The end state control process (see FIG. 87) is also ended.

  On the other hand, when the main CPU 101 determines in S1009 that the value of the AT continuation possible period counter has become "32" (when the determination in S1009 is YES), the main CPU 101 adds one "ART1" as ART stock. (S1010). Next, the main CPU 101 performs ART stock promotion lottery to determine whether to promote the ART stock “ART1” given in S1010 to any of “ART2” to “ART4” (S1011). Next, the main CPU 101 determines whether the ART stock promotion lottery has been won (S1012).

  When the main CPU 101 determines that the ART stock promotion lottery has been won in S1012 (when the determination in S1012 is YES), the main CPU 101 updates the ART stock counter according to the lottery result of the ART stock promotion lottery (S1013) . On the other hand, when the main CPU 101 determines in S1012 that the ART stock promotion lottery has not won (when S1012 is NO), and after the processing of S1013, the main CPU 101 sets the ART preparation state from the next game. (S1014), the at-AT-AT end processing is ended, and the at-game end state control processing (see FIG. 87) is also ended.

[Process at ART end in ART1]
Next, with reference to FIG. 90, the game end time ART1 in-game processing performed in S857 in the game end state control process (see FIG. 87) will be described. FIG. 90 is a flow chart showing a procedure of processing during ART end during the game.

  First, the main CPU 101 determines whether or not the bonus state has ended (S1021). That is, the main CPU 101 determines whether or not it is at the end of the game which has shifted from the bonus state to the bonus non-winning state. When the main CPU 101 determines in S1021 that the bonus state has not ended (when the determination in S1021 is NO), the main CPU 101 shifts the processing to S1024 described later. Although not shown, the main CPU 101 does not perform the respective processes being processed during ART 1 at the end of the game when it is in the inter-flag state and the bonus state.

  On the other hand, when the main CPU 101 determines in S1021 that the bonus state has ended (when the determination in S1021 is YES), the main CPU 101 determines whether the ART stock number is 1 or more (S1022). That is, the main CPU 101 determines whether there is one or more ART stocks. In S1022, when the main CPU 101 determines that the ART stock number is not 1 or more (when S1022 is NO), the main CPU 101 ends the processing during ART 1 at the end of the game, and the control processing according to the state at the end of the game (FIG. See also 87). In this case, in order to resume the suspended ART1 gaming state, the gaming state may be shifted to the ART non-reserved bonus non-earning state, or the bonus combination in the ART1 gaming state may be bonused. If the ART stock number is 0 when this bonus state ends, the state is shifted to the state, and the ART1 gaming state is not resumed (the remaining ART1 continuation possible period when the bonus part is won is discarded), The gaming state may be transferred to the bonus non-winning state of the normal gaming state. In the case of the former, since the ART preparation state is set from the next game in any case, the processing of S102 is unnecessary. Also, in the latter case, when the processing of setting the normal gaming state from the next game is performed when S1022 is NO determination, the processing during ART1 at the end of the game may be ended.

  On the other hand, when the main CPU 101 determines in S1022 that the ART stock number is 1 or more (when the determination in S1022 is YES), the main CPU 101 sets an ART preparation state from the next game (S1023). That is, the main CPU 101 shifts the gaming state to a bonus non-winning state of ART preparation state. Then, after the processing of S1023, the main CPU 101 ends the processing during ART1 at the end of the game, and also ends the control processing classified by the state at the game end (see FIG. 87).

  In S1021, when the main CPU 101 determines that the bonus state has not ended (when S1021 is NO), the main CPU 101 determines whether or not the state in the ART1 gaming state is the ART1 promotion lottery state. (S1024). When the main CPU 101 determines in S1024 that the state is not the ART1 promoted lottery state (that is, the ART1 normal state) (in the case of NO determination in S1024), the main CPU 101 shifts the processing to S1029 described later.

  On the other hand, when the main CPU 101 determines in S1024 that the state is the ART1 promoted lottery (in the case of YES determination in S1024), the main CPU 101 determines whether or not the promotion warning period is in progress (S1025). When the main CPU 101 determines in S1025 that it is not in the promotion sign period (when S1025 is NO), the main CPU 101 shifts the processing to S1029 described later. On the other hand, when the main CPU 101 determines that the promotion warning period is in progress in S1025 (when the determination in S1025 is YES), the main CPU 101 determines whether the promotion warning period has been consumed (S1026). That is, the main CPU 101 determines whether or not the number of games for the promotion precursor period determined as a result of the lottery during the promotion precursor period has been played in the ART1 promotion lottery state.

  In S1026, when the main CPU 101 determines that the promotion precursor period has not been digested (when S1026 is NO), the main CPU 101 ends the processing during ART 1 at the end of the game, and the control processing by state at the end of the game ( See also FIG. 87). On the other hand, when the main CPU 101 determines in S1026 that the promotion precursor period has been consumed (when the determination in S1026 is YES), the main CPU 101 determines the ART stock to be released based on the priority order, The ART continuable period is set, and the ART continuable period (ART1) is cleared (S1027). For example, when there is one "ART 1" and one "ART 2" as the ART stock, the main CPU 101 determines "ART 2" as the ART stock to be released in this processing, and the ART 2 gaming state from the next game Is set, and "30" is set as the ART2 continuous available period. At that time, the remaining ART1 duration is discarded.

  Next, the main CPU 101 updates the ART stock counter (S1028). That is, the main CPU 101 subtracts the ART stock whose release is determined from the ART stock counter. Then, after the processing of S1028, the main CPU 101 ends the processing during ART1 at the end of the game, and also ends the control processing classified by the state at the game end (see FIG. 87).

  When the main CPU 101 determines that the state is not the ART1 promotion lottery state (that is, the state is the ART1 normal state) in S1024 (when S1024 is NO), and in S1025, the main CPU 101 determines that it is not in the promotion sign period When (S1025 is NO determination), the main CPU 101 determines whether or not the ART continuation possible period (ART1) has been digested (S1029). That is, in the ART 1 gaming state, the main CPU 101 determines whether or not the number of games for the number of games in the ART 1 continuation possible period has been played. In S1029, when the main CPU 101 determines that the ART1 continuation possible period has not been digested (S1029 is NO determination), the main CPU 101 ends the processing during ART 1 at the end of the game, and the control processing according to the state at the end of the game (See FIG. 87) also ends.

  On the other hand, when the main CPU 101 determines in S1029 that the ART1 continuation possible period has been consumed (S1029 is YES), the main CPU 101 determines whether the number of ART stock is 1 or more (S1030) . In S1030, when the main CPU 101 determines that the ART stock number is not 1 or more (when S1030 is NO), the main CPU 101 shifts the processing to S1033 described later.

  On the other hand, when the main CPU 101 determines that the ART stock number is 1 or more in S1030 (when S1030 is determined as YES), the main CPU 101 determines the ART stock to be released based on the priority order, and the corresponding ART game The state and the ART continuation possible period are set (S1031). Next, the main CPU 101 updates the ART stock counter (S1032). Then, after the processing of S1032, the main CPU 101 ends the processing during ART1 at the end of the game, and also ends the control processing classified by the state at the game end (see FIG. 87).

  In S1030, when the main CPU 101 determines that the ART stock number is not 1 or more (when S1030 is NO), the main CPU 101 performs CZ shift lottery (see FIG. 40D) (S1033). Next, the main CPU 101 determines whether or not the CZ shift lottery has been won (S1034).

  When the main CPU 101 determines that the CZ shift lottery has been won in S1034 (if S1034 is determined as YES), the main CPU 101 sets the CZ gaming state (that is, the CZ1 or CZ2 gaming state) won from the next game. (S1035), the game end processing in ART1 is ended, and the game end state control processing (see FIG. 87) is also ended. On the other hand, when the main CPU 101 determines that the CZ shift lottery has not been won in S1034 (when S1034 is NO), the main CPU 101 sets the normal gaming state from the next game (S1036), and the game is terminated when ART1 The middle processing ends, and the game end state control processing (see FIG. 87) also ends.

[At the end of the game Normal processing]
Next, with reference to FIG. 91, a description will be given of the processing at the time of game end which is normally performed at S862 in the control processing classified by game end (see FIG. 87). FIG. 91 is a flow chart showing the procedure of the normal process when the game is over.

  First, the main CPU 101 determines whether the bonus state has ended (S1041). That is, the main CPU 101 determines whether or not it is at the end of the game which has shifted from the bonus state to the bonus non-winning state. When the main CPU 101 determines that the bonus state has not ended in S1041 (when the determination in S1041 is NO), the main CPU 101 ends the processing at the end of the game in the normal state, and the control processing at the time of the game end (FIG. See also). Although not shown, the main CPU 101 does not perform the respective processes being processed normally during the end of the game when in the inter-flag state and the bonus state.

  On the other hand, when the main CPU 101 determines that the bonus state has ended in S1041 (when the determination in S1041 is YES), the main CPU 101 determines whether the ART stock number is 1 or more (S1042). That is, the main CPU 101 determines whether there is one or more ART stocks. When the main CPU 101 determines in S1042 that the ART stock number is 1 or more (when the determination in S1042 is YES), the main CPU 101 sets an ART preparation state from the next game (S1043). That is, the main CPU 101 shifts the gaming state to a bonus non-winning state of ART preparation state. Then, after the processing of S1043, the main CPU 101 ends the processing at the end of the game in the normal state, and also ends the control processing classified by the state at the game end (see FIG. 87).

  On the other hand, when the main CPU 101 determines in S1042 that the ART stock number is not 1 or more (S1042 is NO), is the main CPU 101 a game in which any one of the BB1 to BB3 bonus states is over? It is determined whether or not it is (S1044).

  When the main CPU 101 determines in S1044 that the bonus state in any of the BB1 to BB3 states is the end of the game (when the determination in S1044 is YES), the main CPU 101 starts the AT game state (ART non-transition from the next game). ) Is set (S1045). That is, the gaming state is transferred to the AT non-winning state of AT gaming state (ART non transition). Then, after the processing of S1045, the main CPU 101 ends the processing at the end of the game in the normal state, and also ends the control processing classified by the state at the game end (see FIG. 87).

  On the other hand, when it is determined in S1044 that the main CPU 101 is not a game in which any of the BB1 to BB3 bonus states has ended (that is, a game in which the BB4 state has ended) (when S1044 is NO), the main The CPU 101 sets the normal gaming state from the next game (S1046). That is, the gaming state is shifted to the bonus non-winning state of the normal gaming state. Then, after the processing of S1046, the main CPU 101 ends the processing at the end of the game in the normal state, and also ends the control processing classified by the state at the game end (see FIG. 87).

[Interrupt process under control of main CPU (1.1172 msec)]
Next, referring to FIG. 92, the interrupt processing performed by the main CPU 101 will be described in a cycle of 1.172 msec. FIG. 92 is a flowchart of the interrupt process. The interrupt process repeatedly executed in a cycle of 1.1172 msec is generated based on the output timing of the time-out signal of the timer circuit 113 set in the initialization process (see S2 in FIG. 48) of the timer circuit 113 (PTC). This processing is executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs register save processing (S901). Next, the main CPU 101 performs input port check processing (S902). In this process, various switches such as a start switch 79 and a stop switch connected via the external bus interface 104, index sensors (not shown) provided on the left reel 3L, the middle reel 3C and the right reel 3R, etc. The signals input from the various sensors are checked. In this embodiment, through the cabinet side relay board 44, the door relay terminal board 68, the reel relay terminal board 74, etc., these various switches and various sensors are connected to the input port IC (not shown) through the external bus interface 104. It is connected to the input terminal of the input IC connected to the output terminal of FIG. Further, in the main RAM 103, an input port storage area (not shown) for storing the state of the input port IC (in this embodiment, simply referred to as “input port”) connected to the external bus interface 104 by the main CPU 101. ) Is assigned. Here, the input port storage area includes, for example, an input port storage area 1 for storing the current state of the input port, and an input port storage area 2 for storing the state before one interrupt processing of the input port. It consists of Then, in this processing, the main CPU 101 first stores various information stored in the input port storage area 1 in the input port storage area 2 and then stores various information read from the input port in the input port storage area 1 Do. The connection configuration of the various switches and sensors and the configuration of the input port storage area are not limited to those described above. That is, the main CPU 101 only needs to be able to recognize the on / off states of various switches and various sensors.

  Next, the main CPU 101 performs reel control processing (S903). In this process, the main CPU 101 starts the rotation of the left reel 3L, the middle reel 3C and the right reel 3R when the start of rotation of all the reels is requested, and thereafter the respective reels rotate at a constant speed. Drive control of three stepping motors. When the number of sliding symbols is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the effective line of the display window), and for the corresponding reel. The drive control of the corresponding stepping motor is performed so that the rotation is decelerated and stopped.

  Next, the main CPU 101 performs communication data transmission processing (S904). In this process, various commands stored in the communication data storage area are mainly transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 8) of the main control circuit 90. The details of the communication data transmission process will be described later with reference to FIG. 93 described later.

  Next, the main CPU 101 performs an inserted medal passage check process (S905). In this process, the main CPU 101 performs a process of checking whether the inserted medal has passed the selector 66 based on the detection result (the medal sensor input state) of each medal sensor (see FIG. 5).

  Next, the main CPU 101 performs 7-segment LED drive processing (S906). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6, and displays, for example, the number of medals paid out, the number of credits, the pressing order data of the stop button, and the like. The details of the 7-segment LED driving process will be described later with reference to FIG. 95 described later.

  Next, the main CPU 101 performs timer update processing (S907). In this processing, the main CPU 101 performs count (subtraction) processing of the set various timers. The details of the timer update process will be described later with reference to FIG. 97 described later.

  Next, the main CPU 101 performs an error detection process (S908). Next, the main CPU 101 performs door open / close check processing (S909). In the door open / close check process, the main CPU 101 checks the open / close state of the front door 2b (see FIG. 2) by checking the on (door closed) / off (door open) state of the door open / close monitoring switch 67.

  Next, the main CPU 101 performs a shot test signal control process (S910). In this processing, control processing is performed when outputting various test signals to the tester via the second interface board or the like. Also, this process is performed using the extra-defined work area (see FIG. 11C) of the main RAM 103. In the present embodiment, this process is performed also at the time other than at the time of the trial shot test (after the pachislot 1 is installed in the game arcade), but at this time, the main control board 71 is via the second interface boat or the like. Since various test signals are generated, they are not output because they are not connected to the tester.

  Next, the main CPU 101 performs register restoration processing (S911). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[Communication data transmission process]
Next, with reference to FIG. 93, the communication data transmission process performed in S904 in the interrupt process (see FIG. 92) will be described. FIG. 93 is a flowchart of the communication data transmission process.

  First, the main CPU 101 performs WDT setting processing (S961). In this processing, the main CPU 101 performs processing such as restarting the WDT in the reset controller 106. The details of the WDT setting process will be described later with reference to FIG. 94 described later.

  Next, the main CPU 101 determines whether the command transmission start timer has counted up (S962). That is, the main CPU 101 determines whether or not transmission of communication data is being delayed. When the main CPU 101 determines in S 962 that the command transmission start timer has not been counted up (when S 962 is NO), the main CPU 101 ends the communication data transmission process and interrupts the process (FIG. 92). Move to the processing of S 905 in).

  On the other hand, when the main CPU 101 determines that the command transmission start timer has counted up in S 962 (when the determination in S 962 is YES), the main CPU 101 determines whether transmission of communication data is completed (S 963) . Specifically, the main CPU 101 refers to the data stored in the command status register (not shown) of the first serial communication circuit 114 (SCU1), and if the data indicating the transmission completion is stored, the communication data When it is determined that transmission has been completed, and data indicating transmission completion has not been stored, it is determined that transmission of communication data has not been completed.

  When the main CPU 101 determines in S963 that transmission of communication data has not been completed (S963 is NO), the main CPU 101 ends communication data transmission processing, and interrupts processing (see FIG. 92). Move to the processing of S 905 in. On the other hand, when the main CPU 101 determines in S963 that transmission of communication data has been completed (when the determination in S963 is YES), the main CPU 101 performs communication data acquisition processing (S964). In this process, the main CPU 101 performs a process of acquiring communication data (command data) from the communication data storage area of the main RAM 103.

  Next, the main CPU 101 determines whether or not there is unsent data in the acquired communication data (S965). When the main CPU 101 determines in S965 that there is unsent data in the acquired communication data (when the determination in S965 is YES), the main CPU 101 performs the processing of S969 described later.

  On the other hand, when the main CPU 101 determines in S965 that there is no unsent data in the acquired communication data (S965 returns no), the main CPU 101 sets non-operation command data in each register (S966). ). The non-operation command data is information (for example, these operations have been performed) related to a player's game operation (for example, an insertion operation, a start operation, and a stop operation as an operation for advancing a game). The respective parameters are set so as not to include information indicating... Or information indicating an internal winning combination determined based on the start operation, for example. For each parameter of the non-operation command data, for example, a parameter indicating the on / off state of each switch in pachislot 1 or a parameter indicating the on / off state of each sensor (for example, input port storage area 1) And the information stored in the input port storage area 2 may be set. As a result, the sub control circuit 200 may determine the possibility of malfunction or failure of these switches and sensors.

  Next, the main CPU 101 performs communication data storage processing (see FIG. 52) (S967). That is, the main CPU 101 performs processing for storing the non-operation command data generated in S966 in the communication data storage area of the main RAM 103. Next, the main CPU 101 performs communication data acquisition processing (S968). That is, the main CPU 101 performs processing to acquire the non-operation command data stored in the communication data storage area in S967.

  As described above, in the present embodiment, even when there is no communication data to be transmitted from the main control circuit 90 to the sub control circuit 200, at least a non-operation command is transmitted for each interrupt process (see FIG. 92). It is supposed to be. Therefore, it is possible to prevent transmission of unauthorized communication data from the outside due to the absence of communication data to be transmitted from the main control circuit 90 to the sub control circuit 200. From such a point of view, although the non-operation command data does not include information related to the player's game operation, the content of each parameter to be set is not limited to this, and can be appropriately changed. It is.

  After the processing of S968 or when the determination of S965 is YES, the main CPU 101 sets the buffer size of one packet in the transmission counter (S969). In the present embodiment, since one packet of transmission data is 8 bytes, the buffer size of one packet is similarly configured of 8 bytes. Further, in the present embodiment, when a plurality of communication data (command data) are stored in the communication data storage area, they are transmitted in the order of storage (FIFO format). .

  Next, the main CPU 101 acquires transmission data from the communication buffer and sets it in the transmission data register (S970). Specifically, the main CPU 101 sets transmission data in units of 1 byte in a transmission data register (not shown) of the first serial communication circuit 114 (SCU1). As a result, the set transmission data is transferred to the transmission shift register (not shown) of the first serial communication circuit 114 (SCU1) and is transmitted one packet at a time.

  Next, the main CPU 101 updates (+1) the address of the communication buffer by “1” (S971). Next, the main CPU 101 subtracts “1” from the transmission counter (S972). Next, the main CPU 101 determines whether the transmission counter is "0" (S973). That is, the main CPU 101 determines whether transmission of transmission data for one packet has been completed. In S973, when the main CPU 101 determines that the transmission counter is not “0” (when the determination in S973 is NO), the main CPU 101 returns the process to the process of S970, and repeats the processes after S970.

  On the other hand, when the main CPU 101 determines in S973 that the transmission counter is “0” (YES in S973), the main CPU 101 performs communication data pointer update processing (see FIG. 53, for example) (S974). ). Then, after the processing of S974, the main CPU 101 ends the communication data transmission processing, and shifts the processing to the processing of S905 in the interrupt processing (see FIG. 92).

[WDT setting process]
Next, with reference to FIG. 94, the WDT setting process performed in S961 in the communication data transmission process (see FIG. 93) will be described. FIG. 94 is a flowchart of the WDT setting process.

  First, the main CPU 101 sets the address of the WDT clear register (not shown) in the WDT in the reset controller 106 (S981). Next, the main CPU 101 sets clear data (for example, “55H”) to the set address (S982). Next, the main CPU 101 sets restart data (for example, “AAH”) at the set address (S983).

  Next, the main CPU 101 compares the command transmission start timer with its lower limit "0", and subtracts 1 from the command transmission start timer (-1 update) if the command transmission start timer is larger than the lower limit "0". If the command transmission start timer is less than or equal to the lower limit "0", the command transmission start timer is held at "0" (S984). Then, after the processing of S984, the main CPU 101 ends the WDT setting processing, and shifts the processing to the processing of S962 of the communication data transmission processing (see FIG. 93).

  As described above, in the present embodiment, the reset setting and management information of WDT (permission / prohibition of WDT, reference clock, timeout time (for example, 419.4 ms), etc.) is stored in the program management area. By performing the process of S983, the set timeout time is remeasured. If the reset signal is output due to a timeout and the main CPU 101 is restarted, the restart processing is performed without the power-off (external) processing (see FIG. 54) being performed, so checksum generation processing (FIG. 55 is not stored in the main RAM 103 (sum value storage area). Therefore, in this case, the result of the sum check determination in the power-on process (see S11 in FIG. 48) is not normal (that is, "RAM abnormal"), and an error occurs in the information display 6 (7 segment LED display). The character string "88" meaning occurrence is displayed.

[7 segment LED drive processing]
Next, with reference to FIG. 95, the 7-segment LED driving process performed in S906 in the interrupt process (see FIG. 92) will be described. FIG. 95 is a flowchart showing the procedure of the 7-segment LED drive process.

  First, the main CPU 101 adds “1” (+1 update) to the value of the interruption counter (S921). Next, the main CPU 101 determines whether the value of the interrupt counter is an odd number (S922).

  In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when S922 is NO), the main CPU 101 ends the 7-segment LED driving process and performs an interrupt process (see FIG. 92). Move to the process of S907 in). That is, in the present embodiment, the 7-segment LED driving process is performed every two interruption cycles. In the present embodiment, an example in which the 7-segment LED driving process is executed when the value of the interrupt counter is even is described, but the present invention is not limited to this. The 7-segment LED driving process is performed when the value of the interrupt counter is odd. The LED drive processing may be executed, or the execution timing of the 7-segment LED drive processing may be determined using the quotient or remainder obtained by dividing the value of the interrupt counter by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in step S922 that the value of the interruption counter is an odd number (when the determination in step S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets an address of a pressing order display data storage area for storing pressing order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 96 described later.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets an address of a credit display data storage area for storing credit display data to be output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs 7-segment display data generation processing (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 96 described later.

  Next, the main CPU 101 sets an address of a 7-segment common counter storage area for storing a value of a 7-segment common counter described later (S929). Next, the main CPU 101 adds “1” (+1 update) to the value of the 7-segment common counter (S930). In this process, when the value of the 7-segment common counter after updating becomes “8”, the main CPU 101 sets “0” to the value of the 7-segment common counter. In this embodiment, in order to perform dynamic control of the 7-segment LED, the value of the 7-segment common counter is updated in a cycle of eight times.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and the address of the target cathode data storage area (target storage area in push order display data storage area or credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed to temporarily turn off the 7-segment LED to eliminate the influence of an afterimage.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED driving processing, and shifts the processing to the processing of S907 in the interrupt processing (see FIG. 92).

[7 segment display data generation process]
Next, the 7-segment display data generation processing performed in S925 and S928 in the 7-segment LED driving processing (see FIG. 95) will be described with reference to FIG. FIG. 96 is a flowchart of the 7-segment display data generation process.

  Note that "display data" described later generated in the 7-segment display data generation processing performed in S925 during the 7-segment LED driving processing (see FIG. 95) corresponds to the pressing order display data, and the 7-segment LED driving processing ( The “display data” described later, which is generated in the 7-segment display data generation process performed in S928 in (see 95), corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, acquires the value of the quotient of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and performs division The remaining value of the result is acquired as display data of lower digits (S941). Next, the main CPU 101 determines whether to display the upper digit based on the acquired display data of the upper digit (S942).

  In S942, when the main CPU 101 determines that the upper digit display is to be performed (when the determination in S942 is YES), the main CPU 101 performs the processing of S944 described later. On the other hand, when the main CPU 101 determines in S942 that the upper digit display is not to be performed (S942 is NO), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when the determination of S942 is YES, the main CPU 101 refers to the 7-segment cathode table (not shown) and acquires display data of the upper digit (S944). Next, the main CPU 101 stores the display data of the upper digit acquired in the display data storage area (not shown) of the upper digit (S945).

  Next, the main CPU 101 acquires display data of lower digits with reference to a 7-segment cathode table (not shown) (S946). Next, the main CPU 101 stores the acquired lower digit display data in the lower digit display data storage area (not shown) (S947).

  Then, after the process of S947, the main CPU 101 ends the 7-segment display data generation process. At this time, when the executed 7-segment display data generation process is the process of S925 in the 7-segment LED drive process (see FIG. 95), the main CPU 101 executes the process to the process of S926 in the 7-segment LED drive process. Move. On the other hand, if the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 95), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. .

[Timer update processing]
Next, with reference to FIG. 97, the timer update process performed in S907 in the interrupt process (see FIG. 92) will be described. FIG. 97 is a flowchart of the timer update process.

  First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the 2-byte timer number in the B register (S951). The 2-byte timer storage area is used to manage time of 286 ms (256 × 1.1172 ms) or more (that is, a timer value exceeding 1 byte).

  Next, the main CPU 101 compares the 2-byte timer number with its lower limit "0", and subtracts "1" from the 2-byte timer number if the 2-byte timer number is greater than the lower limit "0". If the 2-byte timer number is less than or equal to the lower limit "0", the 2-byte timer number is held at "0" (S952). Furthermore, in the process of S952, the main CPU 101 subtracts 2 from the update start address of the 2-byte timer storage area set in the HL register (-2 update). Since, for example, the command transmission start timer is also a 2-byte timer, the update may be performed in this process (see FIG. 94).

  Next, the main CPU 101 subtracts one from the number of 2-byte timers set in the B register (update by -1) (S953). Next, the main CPU 101 determines whether the number of 2-byte timers set in the B register is “0” (S954).

  When the main CPU 101 determines in S954 that the number of 2-byte timers set in the B register is not “0” (S954 is NO), the main CPU 101 returns the processing to the processing of S952, and Repeat the process.

  On the other hand, when the main CPU 101 determines that the number of 2-byte timers set in the B register is "0" in S954 (when the determination in S954 is YES), the main CPU 101 stores the 1-byte timer storage area in the HL register. The update start address of is set, and the 1-byte timer number is set in the B register (S 955). The 1-byte timer storage area is used to manage time less than 286 ms (i.e., a timer value not exceeding 1 byte). For example, the medal monitoring timer is updated as a 1-byte timer.

  Next, the main CPU 101 compares the number of 1-byte timers with the lower limit “0”, and subtracts 1 from the number of 1-byte timers if the number of 1-byte timers is larger than the lower limit “0” (−1 updated) If the number of 1-byte timers is equal to or less than the lower limit value "0", the number of 1-byte timers is held at "0" (S956). Furthermore, in the process of S956, the main CPU 101 subtracts one from the update start address of the 1-byte timer storage area set in the HL register (−1 update).

  Next, the main CPU 101 subtracts one from the number of one-byte timers set in the B register (−1 update) (S957). Next, the main CPU 101 determines whether the number of 1-byte timers set in the B register is “0” (S958).

  In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not “0” (when the determination in S958 is NO), the main CPU 101 returns the processing to the processing of S956. Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is “0” (YES in S958), the main CPU 101 performs an electromagnetic counter control process (S959). ). In this process, an output control process at the time of outputting a signal indicating IN / OUT of the medal to the external concentrated terminal plate 47 is performed. Then, after the processing of S959, the main CPU 101 ends the timer update processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 92).

<Description of operation at power on>
Next, referring to FIG. 98, an operation of the pachi-slot according to the embodiment of the present invention at the time of powering on will be described. FIG. 98 is a timing chart showing an example of the operation when the Pachi-slot 1 is powered on.

  In FIG. 98, "Main CPU" indicates the main CPU 101 (main control circuit 90), and "Sub CPU" indicates the sub CPU 201 (sub control circuit 200).

  Further, in FIG. 98, the operation state "security mode" of "Main CPU" indicates the state in the security mode described above, and the operation state "start delay period" of "Main CPU" described above after the end of the security mode. Indicates the period until the command transmission start timer is set and the set command transmission start timer becomes “0” (that is, the period during which the setting change is possible but the transmission of communication data is delayed), The operation state “normal operation period” of the “Main CPU” indicates a state in which the transmission of communication data is completed and communication data can be transmitted to the sub CPU 201 (sub control circuit 200).

  Further, in FIG. 98, the operation state “initialization” of “SubCPU” is the initialization (startup) processing (hard start time, BIOS (driver) initialization, etc.) at power on of the sub CPU 201 (sub control circuit 200). (OS) Indicates a state in which activation is in progress (that is, a state in which reception of communication data transmitted from the main CPU 101 (main control circuit 90) is not possible), and an operation state "normal operation period" of "SubCPU" It shows a state in which the initialization (activation) process at the time of power-on is completed, and the reception of communication data transmitted from the main CPU 101 (main control circuit 90) becomes possible.

  Further, in FIG. 98, “setting operation A” starts setting change in the “startup delay period” (for example, the power of the pachi slot 1 is turned on with the setting key type switch 54 turned on), and then “normal "Transmission mode A" indicates the operation when setting change is completed in the "operation period", and the setting change command (setting change / setting check start) (COM1) in the case of "setting operation A", and setting change The transmission timing of the command (setting change / setting confirmation end) (COM2) is shown. In "Main CPU setting change processing" under "Transmission mode A", the setting change command indicates the communication of the main RAM 103 in the setting change confirmation process (see FIG. 50) by the main CPU 101 in the case of "Transmission mode A". It shows the timing (see also the setting change command generation and storage process of FIG. 51 and the communication data storage process of FIG. 52) stored (registered) in the data storage area.

  Further, in FIG. 98, “setting operation B” starts setting change in the “startup delay period” (for example, the power of the pachi slot 1 is turned on with the setting key type switch 54 turned on), and thereafter "Transmission mode B" indicates the operation when setting change is ended in the start delay period ", and the setting change command (setting change / setting check start) (COM1) in the case of" setting operation B "(COM1), and setting The transmission timing of the change command (setting change / setting confirmation end) (COM2) is shown. In "Main CPU setting change processing" under "Transmission mode B", the setting change command indicates the communication of the main RAM 103 in the setting change confirmation process (see FIG. 50) by the main CPU 101 in the case of "Transmission mode B". It shows the timing (see also the setting change command generation and storage process of FIG. 51 and the communication data storage process of FIG. 52) stored (registered) in the data storage area.

  When the power of the pachi slot 1 is turned on and a reset signal is input, the security unit (not shown) of the microprocessor 91 is controlled to the operation state of the security mode. In the security mode, activation of the main CPU 101 is delayed for a period corresponding to the setting stored in the security setting area. When the security mode ends, the main CPU 101 delays transmission of communication data for a predetermined period. Note that the main CPU 101 can change the setting even when the transmission of communication data is delayed.

  Here, as shown in “setting operation A”, when the setting change is started during the delay of transmission of communication data and the setting change is ended after the delay of transmission of communication data is ended, the main CPU 101 performs communication The setting change command (setting change / setting check start) (COM1) is sent to the sub control circuit 200 when the delay of data transmission ends, and the setting change command (setting Change / setting confirmation end) (COM 2) is sent to the sub control circuit 200.

  On the other hand, as shown in “setting operation B”, when the setting change is started during the delay of transmission of communication data and the setting change is ended during the delay of the transmission of communication data, the main CPU 101 When the delay of transmission ends, the setting change command (setting change / setting confirmation start) (COM1) and the setting change command (setting change / setting confirmation end) (COM2) are sequentially transmitted to the sub control circuit 200. . That is, when the delay of transmission of communication data ends, the setting change command (setting change / setting check start) (COM1) and the setting change command (setting change / setting check end) (COM2) are stored in the communication data storage area. If registered, these communication data are transmitted in the order of registration.

  As described above, according to the pachi slot 1 of the present embodiment, the main control circuit 90 can be stably started by delaying the start of the main CPU 101 when the pachi slot 1 is powered on. By delaying the transmission of communication data after the delay is completed, it is possible to secure the time required for activating the sub control circuit 200 and stably activate the sub control circuit 200.

  Then, after the delay of the activation of the main CPU 101 is finished, the setting can be changed even before the delay of transmission of communication data is ended. For example, when opening a store in a game arcade, When the power supply of 1 is turned on (that is, when the reset signal is input in connection with this), the setting change can be made in advance without waiting for the completion of activation of the sub control circuit 200. Work efficiency can be improved.

  Furthermore, when the setting change is performed before the delay of transmission of communication data ends, communication data indicating these is registered at the start of the setting change or at the end of the setting change, and the delay of the communication data transmission is Since these communication data are transmitted in the order in which they were registered when they are completed, even if the setting change is made in advance without waiting for the completion of activation of the sub control circuit 200, As a result, it is possible to prevent the occurrence of wrinkles in the information held between the main control circuit 90 and the sub control circuit 200. In addition, for example, even when the sub control circuit 200 is configured to make a determination such as an unauthorized action or an error according to the order of communication data transmitted from the main control circuit 90, the result of such determination It is possible to make an accurate determination without affecting the

  Further, according to the pachislot 1 of the present embodiment, at least the non-operation command data is transmitted even when the communication data is not registered when the communication data transmission process is performed. For example, it becomes possible to prevent transmission of communication data from the outside by an illegal means such as illegally accessing a connection line between the main control circuit 90 and the sub control circuit 200. In addition, since the registration / transmission of the non-operation command data is not performed before the delay of transmission of communication data is completed, it is possible to reduce the control load when the pachislot 1 is powered on. It should be noted that the non-operation command data may be configured so as not to include information related to the game operation of the player, from the viewpoint of mainly aiming at preventing fraudulent acts.

  Further, according to the pachi slot 1 of the present embodiment, the delay period of activation of the main CPU 101 is configured of a fixed period and a variable period, and these periods (or their ranges) can be appropriately selected and set. Thus, according to the specifications of the main control circuit 90 and the sub control circuit 200, it is possible to set an appropriate delay time. In addition, from the viewpoint of shortening the period until the setting change becomes possible, it is possible to set a range of a predetermined period (for example, “no setting” in the random extension period) in which 0 is necessarily determined as the variable period. In this case, the range of the predetermined period may be set.

  In this embodiment, an example in which setting operation (setting change operation) can be performed during a period in which transmission of communication data is delayed after the end of the security mode ("start delay period") will be described. However, the operation that can be performed in the period in which the transmission of communication data is delayed ("start delay period") is not limited to this. For example, the power of the pachi slot 1 is turned on with the setting key type switch 54 in the off state, and the setting key type switch 54 is in the on state during a period in which transmission of communication data is delayed ("start delay period"). In this case, the confirmation operation (setting confirmation operation) of the setting value may be enabled during the period. Thus, for example, when opening a store, the setting change is not performed, but even if it is desired to check the current set value, etc., the setting confirmation is made without waiting for the start of the sub control circuit 200 to complete. Since it can carry out, it becomes possible to improve the work efficiency at the time of power activation.

<Operation explanation at the time of medal insertion>
Next, with reference to FIG. 99, an operation at the time of medal insertion of a pachislot according to an embodiment of the present invention will be described. FIG. 99 is a timing chart showing an example of the operation of the pachi-slot 1 at the time of medal insertion.

  In FIG. 99, the “start switch” indicates the start switch 79, and the “medal sensor” indicates the detection states of the upstream medal sensor (first medal sensor) 806 and the downstream medal sensor (second medal sensor) 807. (Medal sensor input state) is shown, and the “medal acceptance signal” indicates that the on state (“ON”) is the state where medal acceptance is permitted (the medal acceptance permission), and the off state (“OFF”) is the medal The state in which the reception of the key is prohibited (the medal reception prohibition) is shown (see FIGS. 59 and 60).

  Further, in FIG. 99, “solenoid” indicates the solenoid of the selector 66 (drive source for shifting the select plate 804 to the guide position or the discharge position), and “monitoring timer” indicates the medal monitoring timer (FIGS. 60), “Operation state” is a state (“in game”) that allows the progress of the game after the start operation in the pachislot 1 (“playing in progress”) and a state that does not allow the progress of the game after the start operation ") And.

  When the number of medals for which the game start is possible (three in the present embodiment) is inserted, the main CPU 101 can accept the start operation to the start lever 16. As shown in FIG. 99, in this state, if medals can be stored as the number of credits (if the number of credits is less than 50), the start operation to the start lever 16 is performed (started by the start switch 79) Until the operation is detected), the state in which the reception of the medal is permitted (the state in which the medal reception signal is “ON”) continues. Although illustration is omitted, in this state, if it is not possible to store medals as the number of credits (if there are 50 credits), a state where reception of medals is prohibited (the medal acceptance signal is “OFF” State).

  In the main CPU 101, the medals of the game startable number (3 in the present embodiment) are inserted, and in the state where the medals can be stored as the credit number, the start operation by the start switch 79 (the first start of the left in FIG. 99) When an operation (transition from "OFF" to "ON" of start switch 79) is set to "start operation A", a state where reception of medals is permitted (a medal reception signal is "ON") It shifts from a certain state to a state where medal acceptance is prohibited (the medal acceptance signal is "OFF"), and starts to shift the solenoid of the selector 66 to the demagnetized state, and monitoring by the medal monitoring timer ( Start measurement). At this time, the above-described start lever ON flag is turned on.

  The main CPU 101 checks whether medals have been input (in other words, before the solenoid of the selector 66 has been completely shifted from the excited state to the de-energized state) during monitoring (measurement) by the medal monitoring timer (medal sensor input for each medal sensor) In the case where it is determined based on the state that the medal has been inserted), the inserted medal is counted by changing the solenoid of the selector 66 which has been in transition from the excitation state to the demagnetization state to the excitation state again It is guided in the hopper device 51. Further, in this case, although the "start operation A" is detected by the start switch 79, in the state ("in game") which enables the progress of the game after the operation start operation based on the detection Do not shift. At this time, the above-described start lever ON flag is turned off. That is, in this case, the "start operation A" is invalidated.

  When the main CPU 101 is monitoring (measuring) by the medal monitoring timer (that is, before the solenoid of the selector 66 becomes the transition from the excitation state to the demagnetization state), the medal is inserted (the medal of each medal sensor) In the case where it is determined that the medal has been inserted based on the sensor input state), the reception of the medal is further permitted from the state in which the reception of the medal is prohibited (the state in which the medal reception signal is "OFF") It may be made to shift to a state (a state in which the medal acceptance signal is “ON”).

  After that, the main CPU 101 performs the start operation again by the start switch 79 (in FIG. 99, the second start operation on the right side (transition from “OFF” to “ON” of the start switch 79 is “start operation B”) When is detected, the solenoid of the selector 66 is again changed from the energized state to the de-energized state, and monitoring (measurement) by the medal monitoring timer is started again. At this time, the above-described start lever ON flag is turned on again.

  Then, when the main CPU 101 monitors (measures) by the medal monitoring timer (that is, before the solenoid of the selector 66 becomes the transition from the excitation state to the demagnetization state), the medal is not inserted (for each medal sensor) In the case where it is not determined that the medal has been inserted based on the medal sensor input state), the operation state is performed after monitoring (measurement) by the medal monitoring timer ends (that is, after the solenoid of the selector 66 completes transition from the excitation state to the demagnetization state) Is changed to a state ("in game") which enables the progress of the game after the start operation and enables the progress of the game (ie, medal reception / start check process (see FIGS. 59 and 60)) Processing can be performed).

  Although illustration is omitted, the main CPU 101 detects medals “start operation A” by the start switch 79 and allows medal acceptance from the state where the medal acceptance is permitted (state where the medal acceptance signal is “ON”). Changed to a state where the acceptance of the medal is prohibited (the state that the medal acceptance signal is "OFF"), started to shift the solenoid of the selector 66 to the demagnetized state, and started monitoring (measurement) by the medal monitoring timer After that, during the monitoring (measurement) by the medal monitoring timer (that is, before the solenoid of the selector 66 becomes complete transition from the excitation state to the demagnetization state), when the medal is not inserted (the medal sensor input state of each medal sensor) Same as when start operation B is detected by start switch 79). A state that enables the progress of the game after the start operation of the operation state ("in game") after the monitoring (measurement) by the medal monitoring timer is completed (that is, after the solenoid of the selector 66 has been changed from the excitation state to the demagnetization state) To allow the game to proceed (that is, the processing after the medal acceptance / start check processing (see FIGS. 59 and 60) can be executed).

  As described above, according to the pachislot 1 of the present embodiment, when the game is started along with the player's start operation, for example, the medal monitoring timer for preventing the occurrence of the medal "snipping" etc. Is set. The medal monitoring timer causes the selector 66 to discharge the inserted medal to the outside of the gaming machine from a state where the inserted medal is stored inside the gaming machine (a state in which the select plate 804 is at the guide position due to the solenoid being excited). The time until the state physically shifts to the state (the state in which the select plate 804 is in the discharge position due to the demagnetization of the solenoid) is secured.

  When the medal is inserted during monitoring (measurement) by the medal monitoring timer, the start operation as the origin is invalidated, and the inserted medal is inserted into the gaming machine in the selector 66. It returns to the state of being stored. Therefore, it is possible to appropriately process the inserted medals by preventing the occurrence of the "snipping" of the medals and the like.

  Further, according to the pachislot 1 of the present embodiment, even when a medal is inserted during monitoring (measurement) by the medal monitoring timer, the medal is counted, so The omission of counting can be prevented, and the inserted medals can be processed more appropriately.

  Further, according to the pachislot 1 of the present embodiment, the timer value (for example, "72") of the medal monitoring timer is changed from the state where the inserted medal is stored inside the gaming machine to the state where it is discharged outside the gaming machine Since it is set to a period (for example, “72” × 1.1172 ms) or more (for example, 80 ms) before physical transition, generation of “slow-in” and the like of medals is reliably prevented. Therefore, it is possible to more appropriately process the inserted medals. In the case where the drive unit is a solenoid as in the present embodiment, such an effect is more remarkable.

<Description of ending state>
Next, referring to FIG. 100, an end state of a pachislot according to an embodiment of the present invention will be described. FIG. 100 is a view for explaining the ending state of the pachi slot 1.

  As described above, in the present embodiment, the ending effect may be performed from a predetermined time before the value of the advantageous segment counter becomes “1500” (that is, the number of games in a series of advantageous segments is 1,500). It is controlled to be in the ending state (see, for example, FIG. 70).

  As shown in FIG. 100, if the value of the advantageous segment counter is "1400" (ie, the number of games in a series of advantageous segments has reached 1400), if any ART stock is 3 or more While being controlled to the ending state 1, the execution of the first ending effect is started. Further, when the value of the advantageous segment counter becomes “1450” (ie, the number of games in a series of advantageous segments has reached 1450 times) when not controlled to the ending state 1, the control to the ending state 2 is performed At the same time, execution of the second ending effect is started.

  In addition, when it is controlled to ending state 1 or ending state 2, various lottery concerning the game characteristic (for example, ART stock lottery etc.) is not done at all during the following advantageous section (during ART gaming state), it is simply The game is performed until the value of the advantageous segment counter reaches "1500" by consuming the remaining ART stock and ART continuous available period.

  Here, the first ending effect and the second ending effect are started when being controlled to the ending state 1 or the ending state 2 regardless of what effect is currently being performed. It has become.

  In this embodiment, for example, in the ART1 gaming state, if it is the ART1 promotion lottery state and is in the promotion foreboding period, continuous effects for enhancing the expectation of promotion of ART stock may be performed over a plurality of games. However, if it is controlled to the ending state 1 or the ending state 2 during the continuous rendition, it is forcibly ended even if the continuous rendition is halfway, and the first ending effect or the second ending The execution of the presentation is to be started. However, the opportunity for continuous rendering is not limited to this. For example, in the ART 1 normal state, when winning the winning combination role of ART stock lottery in ART 1 (refer to FIG. 40C), continuous rendition to enhance expectation of winning of ART stock is performed with a predetermined probability. It is also good. Also in this case, the execution of the first ending effect or the second ending effect is prioritized.

  Further, in this embodiment, for example, in the ART 2 gaming state, when the period is in the stop state, continuous effects for notifying that the period is in the stop state is repeated over multiple games until the period stop is ended. Although it can be performed, if it is controlled to the ending state 1 or the ending state 2 during the continuous rendition, it is forcibly ended even if the continuous rendition is halfway, the first ending effect or The execution of the second ending effect is to be started. However, the opportunity for continuous rendering is not limited to this. For example, in the ART 2 gaming state, when winning the winning combination role of ART stock lottery in ART 2, continuous rendering may be performed with a predetermined probability to increase the expectation of winning of ART stock. Also in this case, the execution of the first ending effect or the second ending effect is prioritized.

  Further, in the present embodiment, for example, in ART 3 gaming state, continuous effects for notifying that it is during the first half period, the second half period, or the grant period can be performed over a plurality of games. However, when being controlled to the ending state 1 or the ending state 2 during the continuous rendition, it is forcibly ended even if the continuous rendition is halfway, and the execution of the first ending rendition or the second ending rendition is It is supposed to be started. However, the opportunity for continuous rendering is not limited to this. For example, in the ART 3 gaming state, when winning the lottery subject role of ART 3 continuous lottery, a continuous effect for enhancing expectation of the ART 3 gaming state continuation may be performed with a predetermined probability. Also in this case, the execution of the first ending effect or the second ending effect is prioritized.

  Further, in the present embodiment, for example, in the ART 4 gaming state, when winning the lottery object role of ART stock lottery in ART 4, continuous rendition for enhancing expectation of winning of ART stock may be performed with a predetermined probability. However, if it is controlled to the ending state 1 or the ending state 2 during the continuous rendition, it is forcibly ended even if the continuous rendition is halfway, and the first ending effect or the second ending The execution of the presentation is to be started. However, the opportunity for continuous rendering is not limited to this. For example, in the ART4 gaming state, continuous effects may be performed until the ART4 gaming state ends, in which the ART4 gaming state indicates that the grant of ART stock is most advantageous. Also in this case, the execution of the first ending effect or the second ending effect is prioritized.

  In addition, as shown in FIG. 100, the first ending effect and the second ending effect end in accompaniment with the case where the value of the advantageous section counter is "1500" and the advantageous section is forcibly terminated. The first ending effect and the second ending effect may be such that the effect content proceeds regardless of the number of remaining games.

  For example, the time required for unit game is temporarily defined as "6 seconds" (this value is arbitrary), and the first ending effect is defined as a series of effects of "6 seconds x 100 games = 600 seconds", and the ending state This series of effects is started at the timing controlled to 1. Also, the second ending effect is defined as a series of effects of “6 seconds × 50 games = 300 seconds”, and is controlled to the ending state 2 This series of effects may be started at the right timing. In this way, since it is not necessary to advance the ending effect in accordance with the number of games, the control load relating to the effect can be reduced. Further, in this case, when the execution of the series of effects described above ends at the timing before the end of the advantageous section, the screen at the end is displayed as it is until the advantageous section ends. It is also possible that the series of effects described above may be started from the beginning (or from the middle) again (that is, they may be executed in a loop). In this case, when the advantageous section ends at the timing before the execution of the series of effects described above ends, the above-described series of effects may be forcibly ended even in the middle Alternatively, the series of effects described above may be performed to the end.

  In addition, although the contents of the effects of the first ending effect and the second ending effect can be set as appropriate, as described above, in the ending state 1 or the ending state 2, various lottery concerning the game property is not performed at all Therefore, it is desirable for the player to set a high-value presentation content. For example, if an animation or character is used as a pachislot 1 motif, in the first ending effect, a special image of an animation that can not normally be viewed or a special image of a character is displayed on the display device 11 do it. In this case, in the second ending effect, the contents of these images are to be displayed on the display device 11 shorter than the first ending effect (for example, summarized, halfway or otherwise). Just do it. However, instead of these, or along with these, it is also possible to perform each ending effect by the music and sound outputted from the speaker group 84 and the light emission mode by the LED group 85.

  Further, in the present embodiment, when any ART gaming state is started, when ART gaming state is ended (when transitioning to CZ gaming state, ART gaming state is not returned to ART gaming state in CZ gaming state) If it is decided to shift to the ART gaming state during the advantageous section (when the bonus combination is won, or during the bonus state), the display device 11 decides to shift to the ART gaming state until the state ends. Although the number of games played and the increased number of medals (total number of obtained medals) of the bonus state can be appropriately displayed, when the first ending effect or the second ending effect is started, these may be displayed. Display may be terminated in advance (ie, these displays are not performed during the ending state), or the first ending effect or Even during the execution of the second ending effect may be displayed, these are displayed in a properly updated.

  Further, as shown in FIG. 100, when the value of the advantageous section counter becomes “1500” and the advantageous section is forcibly ended, the specific end screen is displayed on the display device 11. On the specific end screen, for example, a total acquisition number in the final advantageous section, a message for calling attention to the prevention of game stagnation, etc. are displayed. However, the display content of the specific end screen is merely an example, and other display contents can be appropriately displayed. Specifically, the total number of games during the final advantageous section, the number of transitions to the bonus state, the breakdown of the transitioned bonus state (for example, SBB: 1 time, BB1: 1 times, BB2: 2 times, BB3: 2 Times, BB4: Display of 6 times etc.) Breakdown of transitioned ART gaming state (eg ART1: 4 times, ART2: 3 times, ART3: 2 times, ART4: 1 time etc.) Message to congratulate you (for example, a message such as “Congratulations on ART completion!”), Or a message for notifying that the advantage section has been forcibly terminated (for example Or the like may be displayed. In addition, as a message for alerting the player to prevent the game from getting stuck, for example, it may be made to display a message such as "Pachislot is a modestly enjoyable play. In addition, a display for other alerting (for example, prevention of lost items, prevention of placement, etc.) may be made.

  The timing at which the specific end screen is displayed is not limited to the one described above. For example, when the first ending effect and the second ending effect are configured as a series of effects described above, when the execution of the series of effects described above ends at a timing before the advantageous section ends, at that timing It may be displayed.

  In the present embodiment, immediately before the value of the advantage section counter becomes “1500” and the advantage section is forcibly ended (that is, when being controlled to the ending state 1 or the ending state 2), the bonus state is set. In transition to the bonus state, the value of the advantageous segment counter may be "1500" and the advantageous segment may be forcibly terminated. In this case, as shown in FIG. 100, a specific end screen may be displayed when the bonus state ends.

  Also, in the present embodiment, when the value of the advantageous section counter is "1500" and the advantageous section is forcibly ended, the external signal 1 is switched from the on state to the off state when the game is ended. (Refer to FIG. 88), but the value of the advantageous section counter becomes “1500” immediately before the advantageous section is forcibly ended (that is, when controlled to the ending state 1 or the ending state 2) In the bonus state, when the value of the advantageous segment counter becomes “1500” during the bonus state, the external signal 1 is not switched from the on state to the off state at that time, and the bonus state is ended. The external signal 1 may be switched from the on state to the off state.

  Thus, in the present embodiment, it is possible to determine whether or not to grant ART stock in the ART gaming state, for example, when a normal ending condition is satisfied in the ART1 gaming state (for example, ART1 continuation possible period) If the ART1 is 0, the ART1 gaming state is ended, and the special end condition is satisfied (for example, when the value of the advantageous segment counter becomes “1500”), A specific number (for example, 3 or more) of ART stock is given when the value of the advantageous section counter reaches "1400" before the ART1 gaming state is ended and the value of the advantageous section counter becomes "1500". If it is, the first ending effect execution is started regardless of the effect being executed, and the value of the advantageous segment counter becomes “1450”, the first ending Effect is when it is not running, and starts the execution of the second ending effect regardless effect of running.

  As a result, even when the ART gaming state is forcibly terminated due to a restriction, a privilege that a predetermined effect is executed can be provided, and this predetermined effect is set to the ART stock number. Since the timing and content when execution is started can be made different accordingly, it is possible to indicate the end of the ART gaming state as well as the award of execution of a predetermined effect. Therefore, even in the case of restricting the acquisition of game media, it is possible to reduce the deterioration of the player's interest.

  Further, in the present embodiment, when the first ending effect or the second ending effect is being executed (that is, when being controlled to the ending state 1 or the ending state 2), whether or not to provide ART stock Is not determined.

  Thereby, when the ART gaming state is forcibly terminated due to the regulation, it is possible to prevent a large amount of the granted ART stock from remaining. That is, since the player is not given the right regarding the ART gaming state which can not be digested, it is possible to reduce the deterioration of the player's interest even when restricting the acquisition of game media. Can.

  Also, in the present embodiment, during the advantageous section, the value of the advantageous section counter is also updated during the bonus state (that is, the number of games in the bonus state is also counted as the number of games in the advantageous section) It has become. Thereby, it is possible to appropriately manage a series of advantageous sections in which a state advantageous to the player continues.

  In the present embodiment, when the ART gaming state is started, the output of the external signal 1 is set to the first state (on state). For example, when the normal ending condition is satisfied in the ART1 gaming state (for example, , The ART1 continuable period is digested, and when the ART stock is 0, the output of the external signal 1 is brought to the second state (off state) and the special termination condition is satisfied (for example, in the advantageous interval counter When the value is “1500” and the bonus state is not controlled, the output of the external signal 1 is set to the second state (off state) at this time and the bonus state is controlled. In this case, it is possible to set the output of the external signal 1 to the second state (off state) when the bonus state ends.

  Thereby, when the ART gaming state is forcibly ended due to the regulation, when the bonus state which is not affected by this continues, it is appropriately informed to the outside that the series of advantageous sections are still continuing. can do. Therefore, for example, various external devices (for example, a data display) can appropriately notify the player to that effect via signal output means (for example, the external concentrated terminal plate 47). Therefore, even in the case of restricting the acquisition of game media, it is possible to reduce the deterioration of the player's interest.

<Various modifications>
The configuration and operation of the gaming machine of the invention according to the present embodiment have been described above including the effects and advantages thereof. However, the invention according to the present embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention according to the present embodiment.

[Application to other game machines]
Further, in the above embodiment, the pachislot machine has been described as an example of the gaming machine, but the gaming machine to which the invention according to the present embodiment can be applied is not limited to this. For example, features other than pachislo-specific features, such as features relating to reel stop control based on stop operation, are also applicable to gaming machines called "pachinko", and similar effects can be obtained.

[Scalability of gaming machine according to the other embodiment]
In the pachislot 1 of the present embodiment, the player's medal insertion operation (i.e., an operation of inserting a hand-held medal into the medal insertion slot 14 or a credited medal is the MAX bet button 15a or 1 bet button 15b). When the game is started by the operation to insert and the operation is inserted, and there is a payout of the medal when the game is over, the hopper device 51 is driven and the medal is paid out from the medal payout opening 24, or the credit Although the embodiment has been described, the present invention is not limited to this.

  For example, the game medium necessary for the game is inserted by the player, the game is performed based thereon, and the present invention is applied to all the modes in which a privilege is given (for example, medals are paid out) based on the result of the game. be able to. That is, the game control medium 90 (main control board 71) itself is a game medium owned by the player as well as a mode in which the game medium is inserted (hanged) by the operation of the physical player and the game medium is paid out. May be electromagnetically managed to enable games without medals. In addition, the game medium management device installed in (connected to) the main control circuit 90 (main control board 71) to manage game media held by the player electromagnetically may be a game medium management device that manages game media. .

  In this case, the gaming medium management device is a device provided in the gaming machine, having ROM and RWM (or RAM), and bi-directional communication with an external gaming medium handling device (not shown) via a predetermined interface. It is possible to be connected, and the lending operation of gaming media (that is, the operation of providing the necessary gaming media when the player performs the operation of inserting the gaming media) or the prize for winning the role related to the payout of gaming media ( The game media payout operation when the role is established (that is, the operation of acquiring the necessary game media when the player is paid out the game media), or the game media to be used for the game It is sufficient that the operation of recording electromagnetically can be performed. In addition, the gaming media management device displays the number of gaming media held on the front of the pachislot 1 based on not only management of the actual number of gaming media but also, for example, management results of the number of gaming media. A number display device (not shown) may be provided to manage the number of game media displayed on the stored game media number display device. That is, the gaming media management device may be capable of recording and displaying the total number of gaming media that the player can use for gaming by an electromagnetic method.

  Also, in this case, the gaming media management device has the capability of allowing the player to freely transmit a signal indicating the number of gaming media recorded to the external gaming media handling device, and the player In addition to the case of direct operation, the number of recorded game media can not be reduced, and when an external connection terminal board (not shown) is provided between an external game medium handling device It is desirable that the player can not transmit a signal indicating the recorded number of game media without using the external connection terminal board.

  In addition to the above, the gaming machine is provided with a lending operation means operable by the player, a return (settlement) operation means, and an external connection terminal board, and the gaming medium handling device is a slot for inserting valuable values such as bills, a recording medium (For example, an IC card) insertion slot, a non-contact communication antenna for receiving electronic money etc. from a portable terminal, etc., other operation means such as lending operation means, return operation means, game medium handling device side external connection terminal board It may be provided (all not shown).

  As the flow of the game at that time, for example, the player deposits a valuable value to the game medium handling device by any method, and subtracts a predetermined number of valuable values based on the operation of any one of the lending operation means described above. The game media corresponding to the valuable value subtracted from the game media handling device to the game media management device is increased. Then, the player plays a game, and when the game medium is required, the above operation is repeated. Thereafter, a predetermined number of game media are obtained as a result of the game, and the game media management device transmits the number of game media from the game media management device to the game media handling device by operating any return operation means when ending the game. The medium handling device ejects a recording medium recording the number of game media. The gaming media management device clears the number of gaming media stored by itself when transmitting the number of gaming media. The player brings the discharged recording medium to a prize counter or the like to exchange prizes, or moves the game platform to play a game based on the game medium recorded on another platform.

  In the above example, all gaming media are transmitted to the gaming media handling apparatus, but the gaming machine or gaming media handling apparatus transmits only the number of gaming media desired by the player and the gaming media possessed by the player It may be divided and processed. In addition to discharging the recording medium, cash or cash equivalents may be discharged, or may be stored in a portable terminal or the like. Further, the gaming medium handling device may insert a member recording medium of the game arcade, and store the member recording medium in the member recording medium so as to be able to play again later.

  Further, in the gaming machine or game medium handling apparatus, it is possible to execute the lock operation for locking the data communication of the game medium or the valuable value to the game medium handling apparatus or the game medium management apparatus by operating the predetermined operation means (not shown). It is also good. At that time, the player may be stored by setting information which can be known only to the player such as a one-time password, or by an imaging means provided in the gaming machine or the gaming medium handling apparatus.

  In addition, as described above, this gaming media management device may be capable of playing a game only without medals, or gaming media may be inserted (hanged) by the action of a physical player. It may be possible to play the game in a form in which money is paid out, and a form in which the game can be made without medals, or in both forms. In this case, the game medium management device may adopt a method of directly controlling the selector 66 and the hopper device 51 described above, which are controlled by the main control circuit 90 (main control board 71), Adopting a method that enables control to perform control to record and display the total number of game media that the player can use for gaming based on the transmission of the control result by an electromagnetic method. You can also.

  Further, although the above describes the case of applying the gaming media management device to the pachislot 1, the gaming media management device is similarly provided in the slot machine and the enclosed type gaming machine using the gaming ball described above, and the player Game media can be controlled.

  As described above, by providing the above-described gaming medium management device, it is possible to reduce the number of selectors 66 and the hopper device 51 inside the gaming machine compared to the case where the gaming medium is physically provided for gaming. Not only can reduce the cost and production cost of the game, but also prevent the player from directly contacting the game media, and the game environment can be improved, noise can be reduced, and the number of devices has been reduced. It also reduces the power consumption of In addition, it is possible to prevent fraudulent acts through the insertion slot and the payout opening of the game media and the game media. That is, it is possible to provide a gaming machine capable of improving various environments surrounding the gaming machine.

<Supplementary Note (Summary of the Invention)>
[The game machine of the 1st-3rd composition]
In a conventional gaming machine, a lottery as to whether or not to shift to an advantageous state (for example, an ART state) advantageous to the player is made, and based on the result of the lottery, a prognostic state (i.e., transition to an advantageous state) It is known that it is possible to transition to a true precursor state if a decision is made) or a false precursor state (ie a false precursor state if it is not decided to transition to an advantageous state) (e.g. , JP-A-2015-39536)).

  By the way, in recent years, in such a gaming machine, in order to suppress excessive cheating of the player, a section (advantageous section) of a game advantageous to the player such as the above-mentioned advantageous state should be started. In principle, it was required to immediately shift to the advantageous section when

  However, if it is made to immediately shift to the advantageous section based on the fact that it is decided to start the advantageous section, there is an advantage that it is easy to manage the gaming state and it is easy for the player to recognize the success or failure. However, there is also a disadvantage that the fun of the game is reduced because the success or failure can be recognized immediately.

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of improving the fun of gaming while appropriately managing the gaming state.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following first configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state), a first advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state, a second advantageous state (for example, an AT gaming state (ART transition)), and a second 3 advantageous states (for example, AT gaming state (ART transition));
A first advantageous state of determining whether or not to shift to the first advantageous state when a specific condition is satisfied in the normal state (for example, when a specific role shown in FIGS. 33A and 33B is won) Determination means (for example, main CPU 101);
If the specific condition is satisfied in the normal state, and it is determined to shift to the first advantageous state by the first advantageous state determining means, prior to the transition to the first advantageous state Second advantageous state determining means (for example, the main CPU 101) capable of determining whether or not to shift to the second advantageous state;
In the case where the specific condition is satisfied in the normal state, and it is not determined to shift to the first advantageous state by the first advantageous state determining means, the mode is shifted to the third advantageous state And third advantageous state determination means (for example, the main CPU 101) capable of determining whether or not
The first advantageous state, the second advantageous state, and the third advantageous state are states in which information of stop operation advantageous to the player can be notified,
The second advantageous state and the third advantageous state can be ended when the information of the stop operation advantageous to the player is notified a predetermined number of times (for example, once),
The first advantageous state determining means further determines that the information on the stop operation advantageous to the player is not notified the predetermined number of times during a predetermined period (for example, 32 games) of the third advantageous state. A game machine characterized in that it is possible to decide to shift to an advantageous state.

  According to the gaming machine configured as described above, regardless of whether or not it is decided to shift to the first advantageous state (for example, ART gaming state) which is advantageous for the player, the second advantageous state (for example, AT gaming state) In any of the states (eg, ART transition) and the third advantageous state (for example, AT gaming state (ART non transition)), it is possible to have an expectation regarding the first advantageous state transition, and each gaming state Can be properly managed. Therefore, the fun of the game can be improved while appropriately managing the gaming state.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide the following gaming machine of the second configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state), a first advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state, a second advantageous state (for example, an AT gaming state (ART transition)), and a second 3 advantageous states (for example, AT gaming state (ART transition));
A first advantageous state of determining whether or not to shift to the first advantageous state when a specific condition is satisfied in the normal state (for example, when a specific role shown in FIGS. 33A and 33B is won) Determination means (for example, main CPU 101);
If the specific condition is satisfied in the normal state, and it is determined to shift to the first advantageous state by the first advantageous state determining means, prior to the transition to the first advantageous state Second advantageous state determining means (for example, the main CPU 101) capable of determining whether or not to shift to the second advantageous state;
In the case where the specific condition is satisfied in the normal state, and it is not determined to shift to the first advantageous state by the first advantageous state determining means, the mode is shifted to the third advantageous state And third advantageous state determination means (for example, the main CPU 101) capable of determining whether or not
The first advantageous state, the second advantageous state, and the third advantageous state are states in which information of stop operation advantageous to the player can be notified,
The second advantageous state and the third advantageous state can be ended when the information of the stop operation advantageous to the player is notified a predetermined number of times (for example, once),
The probability that the information of the stop operation which is advantageous to the player in the second advantageous state is notified more than the predetermined number is that the information of the stop operation which is advantageous to the player in the third advantageous state is more than the predetermined number A gaming machine characterized by having a higher probability than being notified.

  According to the gaming machine configured as described above, the benefits provided in the second advantageous state (for example, AT gaming state (ART transition)) and the third advantageous state (for example, AT gaming state (ART non transition)) become excessive. The expectation can be changed by the number of times the information of the stop operation which is advantageous to the player is notified while suppressing the occurrence of a drop. Therefore, the fun of the game can be improved while appropriately managing the gaming state.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following third configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state), a first advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state, a second advantageous state (for example, an AT gaming state (ART transition)), and a second 3 advantageous states (for example, AT gaming state (ART transition));
A first advantageous state of determining whether or not to shift to the first advantageous state when a specific condition is satisfied in the normal state (for example, when a specific role shown in FIGS. 33A and 33B is won) Determination means (for example, main CPU 101);
If the specific condition is satisfied in the normal state, and it is determined to shift to the first advantageous state by the first advantageous state determining means, prior to the transition to the first advantageous state Second advantageous state determining means (for example, the main CPU 101) capable of determining whether or not to shift to the second advantageous state;
In the case where the specific condition is satisfied in the normal state, and it is not determined to shift to the first advantageous state by the first advantageous state determining means, the mode is shifted to the third advantageous state Third advantageous state determination means (for example, the main CPU 101) capable of determining whether or not
When a special condition is satisfied (for example, when a bonus combination is won and a combination of symbols relating to the bonus combination is displayed), control is made to a special game state (for example, bonus state) advantageous to the player Special game state control means (for example, main CPU 101);
The first advantageous state, the second advantageous state, and the third advantageous state are states in which information of stop operation advantageous to the player can be notified,
The second advantageous state and the third advantageous state can be ended when the information of the stop operation advantageous to the player is notified a predetermined number of times (for example, once),
A gaming machine characterized by transitioning to the first advantageous state when the special gaming state is ended, when the special condition is satisfied and the special gaming state is controlled in the second advantageous state.

  According to the gaming machine having the above configuration, after the end of the special gaming state (for example, the bonus state) shifted from the second advantageous state (for example, AT gaming state (ART transition)), the first advantageous state more advantageous for the player By shifting to (for example, ART gaming state), it is possible to give the impression that the more advantageous gaming state continues continuously. Therefore, the fun of the game can be improved while appropriately managing the gaming state.

In the gaming machine of the first to third configurations,
When it is decided to shift to the second advantageous state by the second advantageous status determining means, and when it is decided to shift to the third advantageous state by the third advantageous status determining means, 2) A duration determining means (for example, the main CPU 101) for determining the duration (for example, the AT duration) of the two advantageous states or the third advantageous state
The second advantageous state and the third advantageous state end when the duration determined by the duration determining means has elapsed when the information on the stop operation advantageous to the player is notified the predetermined number of times If the information on the stop operation which is advantageous to the player is not notified the predetermined number of times, it does not end even if the duration determined by the duration determining means has elapsed. Gaming machine.

  According to the gaming machine configured as described above, the benefits provided in the second advantageous state (for example, AT gaming state (ART transition)) and the third advantageous state (for example, AT gaming state (ART non transition)) become excessive. Allow the player to obtain minimum benefits in these gaming states while suppressing the possibility of being thrown away, and further increase the possibility that another benefit will be provided in the third advantageous state Can further improve the fun of the game.

In the gaming machine of the first and second configurations,
In the first advantageous state, the second advantageous state, and the third advantageous state, there is provided a notification means (for example, a state indicator) for informing the player that the game section is advantageous for the game. The gaming machine described above.
Further, in the gaming machine of the third configuration,
In the first advantageous state, the second advantageous state, and the third advantageous state, and when the special gaming state is controlled in these states, it is informed that it is a game zone advantageous to the player The gaming machine as described above, characterized in that it comprises notifying means (for example, a status indicator).

  According to the gaming machine configured as described above, since the player is shown to be a series of advantageous sections, even when a plurality of gaming states having different degrees of advantageous constitute a series of advantageous sections, Can prevent the player from being overwhelmed.

[Fourth configuration game machine]
In a conventional gaming machine, when it is not in an advantageous state (for example, ART state) advantageous to the player, a lottery is performed to determine whether or not to shift to the advantageous state, and the advantageous state is What made it possible to perform lottery of whether to continue is known (for example, refer Unexamined-Japanese-Patent No. 2010-240017).

  However, in the gaming machine shown in Japanese Patent Application Laid-Open No. 2010-240017, there is a point that the variation is scarce in determining whether or not to continue the advantageous state, and it is required to devise devices for further enhancing interest. .

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of improving the interest concerning the continuation of a state advantageous to a player.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the fourth configuration as described below.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
It has a normal state (for example, a normal gaming state) and an advantageous state (for example, an ART1 gaming state) that is more advantageous to the player than the normal state.
Advantageous state transition determining means (for example, main CPU 101) for determining whether or not to shift to the advantageous state in the normal state;
An advantageous state continuation determining unit (for example, the main CPU 101) for determining whether or not to continue the advantageous state in the advantageous state;
An advantageous state control unit (for example, the main CPU 101) for controlling the advantageous state;
The said advantageous state continuation determination means is
Enforcement means capable of determining whether or not to grant a right (for example, ART stock) to continue the advantageous state in the advantageous state (for example, execution of ART stock lottery in ART 1 by the main CPU 101);
In the advantageous state, the right is granted by the right granting means, and is granted when a specific condition is satisfied (for example, when a specific combination shown in FIG. 41A is won). (E.g., execution of ART stock promotion lottery in ART1 by the main CPU 101) which can determine whether or not to promote the rights to the more advantageous rights.
Said advantageous state control means
In the advantageous state, the special state (e.g., promotion) is made regardless of the result of determination by the right promotion means when the right is given by the right giving means and the specific condition is satisfied. Including special state control means (for example, execution of a promotion precursor period lottery by the main CPU 101) capable of determining transition to the precursor period),
In the advantageous state, when the right is not granted by the right granting means, the advantageous state is ended when a predetermined period (for example, ART1 continuation possible period) has elapsed,
In the advantageous state, the right is granted by the right granting means, and it is determined that the right is promoted by the rights promoting means, and the special state is entered. A game machine characterized by continuing the advantageous state based on a new right according to the determination result by the right promotion means even when the special state is finished even before the lapse of a predetermined period.

  According to the gaming machine configured as described above, the determination as to whether or not to continue the advantageous state (for example, the ART gaming state) can be made rich in variations, and the enjoyment of the continuation of the advantageous state for the player can be improved. Can be In addition, on the other hand, it is possible to suppress an excessive gain given to the player and to suppress an excessive revenge on the player.

The advantageous state control means includes a game number counting means (for example, updating of an ART1 continuation possible period counter by the main CPU 101) for counting a predetermined number of games (for example, 30 games) corresponding to the predetermined period,
In the advantageous state, when the right is not granted by the right giving means, the advantageous state is ended when the predetermined number of times of playing is counted by the game number counting means.
The gaming machine according to the above, wherein the game number counting means does not count the predetermined number of games in the special state.

  According to the gaming machine configured as described above, for example, even when it is determined that only the transition to the special state (for example, promotion promotion period) is made and the transition to the special state is made, the substantially advantageous state (for example, ART1 gaming) Since the state is extended, it is possible to further improve the interest concerning the continuation of the state advantageous to the player.

  It is characterized in that the right promotion means can decide whether or not to elevate the granted right to the more advantageous right even when the specific condition is satisfied in the special state. A gaming machine as described above.

  According to the gaming machine configured as described above, since it is possible to have a sense of expectation for the promotion of the right (for example, ART stock) even during the special state (for example, the promotion sign period), the continuation of the state advantageous to the player Interest can be further improved.

[The game machine of the 5th-8th composition]
In a conventional gaming machine, when the number of game media acquired reaches a predetermined number during a state (for example, ART) where information on stop operation advantageous to the player is notified may be performed, the state is Further, there is known one that makes it possible to regulate the acquisition of game media by controlling so that the notification effect is not performed even when the continuation is possible (for example, JP-A-2014-91005). See the official gazette).

  By the way, restricting the acquisition of gaming media as in the gaming machine shown above is a useful function from the viewpoint of suppressing excessive cheating of the player, but such a function In the case of provision, it is required to devise a device for reducing the decrease in the player's interest.

  The present invention has been made in view of such a point, and provides a gaming machine capable of reducing deterioration of the player's interest even when the acquisition of gaming media is restricted. The purpose is to

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following fifth configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state) and an advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state;
Advantageous state transition determining means (for example, main CPU 101) for determining whether or not to shift to the advantageous state in the normal state;
An advantageous state continuation determining unit (for example, the main CPU 101) for determining whether or not to continue the advantageous state in the advantageous state;
The said advantageous state continuation determination means is
In the advantageous state, the right to continue the advantageous state (e.g., ART stock "ART 1" to "ART 4"), which one of a plurality of the above different rights with different degrees of advantage is to be granted or not Right-determining means (for example, execution of ART stock lottery by the main CPU 101), and
A normal termination means for terminating the advantageous state when the normal termination condition is satisfied in the advantageous state;
Special termination means for terminating said advantageous state if a special termination condition is satisfied in said advantageous state;
The normal ending condition is satisfied when the right is not granted by the right granting means, and a game is played for a predetermined period (for example, an ART continuation possible period) in the advantageous state. ,
The special termination condition may be, for example, when the right is granted by the right granting means, and even if the game is not performed for the predetermined period in the advantageous state, the defined period in the advantageous state (for example, It is satisfied when the game is played until the value of the advantageous section counter reaches "1500",
When the game is performed in the advantageous state before the specified period (e.g., until the value of the advantageous segment counter reaches "1000") before the specified period in the advantageous state, the degree of advantage in the subsequent period is If it is decided to grant a high first right (for example, “ART 3” or “ART 4”), a second right (for example, “ART 2”) having a lower degree of advantage than the first right is A gaming machine characterized by giving.

  According to the gaming machine configured as described above, when an advantageous state (for example, ART gaming state) is forcibly terminated due to a regulation, a large amount of granted rights (for example, ART stock) will remain. It can prevent. That is, since it is possible to grant the right regarding the advantageous state within the range in which the player can digest, it is possible to reduce the deterioration of the player's interest even when restricting the acquisition of game media. Can.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following sixth configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state) and an advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state;
Advantageous state transition determining means (for example, main CPU 101) for determining whether or not to shift to the advantageous state in the normal state;
An advantageous state continuation determining unit (for example, the main CPU 101) for determining whether or not to continue the advantageous state in the advantageous state;
An effect executing unit (for example, the display device 11) for executing an effect;
The said advantageous state continuation determination means is
In the advantageous state, it is possible to determine whether or not to grant the right to continue the advantageous state (for example, execution of ART stock lottery by the main CPU 101);
A normal termination means for terminating the advantageous state when the normal termination condition is satisfied in the advantageous state;
Special termination means for terminating said advantageous state if a special termination condition is satisfied in said advantageous state;
The normal ending condition is satisfied when the right is not granted by the right granting means, and a game is played for a predetermined period (for example, an ART continuation possible period) in the advantageous state. ,
The special termination condition may be, for example, when the right is granted by the right granting means, and even if the game is not performed for the predetermined period in the advantageous state, the defined period in the advantageous state (for example, It is satisfied when the game is played until the value of the advantageous section counter reaches "1500",
The effect executing means is
In the advantageous state, when a game is played for a first period (e.g., until the value of the advantageous segment counter reaches "1400") before the prescribed period has elapsed, the right granting means causes the specified number (for example, three) When the right of the above is granted, the execution of the first effect (for example, the first ending effect) is started regardless of the effect being executed,
In the advantageous state, when a game is performed after the first period has elapsed and before the prescribed period has elapsed, the second period (for example, until the value of the advantageous segment counter reaches “1450”), A game machine characterized by starting execution of a second effect (for example, a second ending effect) regardless of the effect being executed when the first effect is not executed.

  According to the gaming machine configured as described above, even when the advantageous state (for example, the ART gaming state) is forcibly ended due to the regulation, the predetermined effect (for example, the first ending effect or the second ending effect) Because it is possible to grant the privilege that is executed, and to make this predetermined effect different from the timing and content when execution is started according to the number of rights (for example, ART stock), Not only the award of the execution of a predetermined effect, but it is also possible to indicate the end of the advantageous state. Therefore, even in the case of restricting the acquisition of game media, it is possible to reduce the deterioration of the player's interest.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following seventh configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state) and an advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state;
Advantageous state transition determining means (for example, main CPU 101) for determining whether or not to shift to the advantageous state in the normal state;
An advantageous state continuation determining unit (for example, the main CPU 101) for determining whether or not to continue the advantageous state in the advantageous state;
An effect executing unit (for example, the display device 11) for executing an effect;
The said advantageous state continuation determination means is
In the advantageous state, it is possible to determine whether or not to grant the right to continue the advantageous state (for example, execution of ART stock lottery by the main CPU 101);
A normal termination means for terminating the advantageous state when the normal termination condition is satisfied in the advantageous state;
Special termination means for terminating said advantageous state if a special termination condition is satisfied in said advantageous state;
The normal ending condition is satisfied when the right is not granted by the right granting means, and a game is played for a predetermined period (for example, an ART continuation possible period) in the advantageous state. ,
The special termination condition may be, for example, when the right is granted by the right granting means, and even if the game is not performed for the predetermined period in the advantageous state, the defined period in the advantageous state (for example, It is satisfied when the game is played until the value of the advantageous section counter reaches "1500",
The effect executing means is
In the advantageous state, when a game is played for a first period (e.g., until the value of the advantageous segment counter reaches "1400") before the prescribed period has elapsed, the right granting means causes the specified number (for example, three) When the right of the above is granted, the execution of the first effect (for example, the first ending effect) is started regardless of the effect being executed,
In the advantageous state, when a game is performed after the first period has elapsed and before the prescribed period has elapsed, the second period (for example, until the value of the advantageous segment counter reaches “1450”), When the first effect is not executed, the execution of the second effect (for example, the second ending effect) is started regardless of the effect being executed,
When the first effect or the second effect is being executed by the effect executing means, the right giving means does not determine whether to grant the right or not. Machine.

  According to the gaming machine configured as described above, when an advantageous state (for example, ART gaming state) is forcibly terminated due to a regulation, a large amount of granted rights (for example, ART stock) will remain. It can prevent. In addition, even when the advantageous state (for example, the ART gaming state) is forcibly ended due to the regulation, the privilege that the predetermined effect (for example, the first ending effect or the second ending effect) is executed Since the predetermined effect can be given, and the predetermined effect can be made different according to the number of rights (for example, ART stock), the benefit of executing the predetermined effect Not only can it be given, but it is also possible to indicate the end of the advantageous state. Therefore, even in the case of restricting the acquisition of game media, it is possible to reduce the deterioration of the player's interest.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following eighth configuration.

It is a gaming machine (for example, pachislot 1) that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state (for example, a normal gaming state) and an advantageous state (for example, an ART gaming state) that is more advantageous to the player than the normal state;
Advantageous state transition determining means (for example, main CPU 101) for determining whether or not to shift to the advantageous state in the normal state;
An advantageous state continuation determining unit (for example, the main CPU 101) for determining whether or not to continue the advantageous state in the advantageous state;
When a special condition is satisfied (for example, when a bonus combination is won and a combination of symbols relating to the bonus combination is displayed), control is made to a special game state (for example, bonus state) advantageous to the player Special game state control means (for example, main CPU 101);
The said advantageous state continuation determination means is
In the advantageous state, it is possible to determine whether or not to grant the right to continue the advantageous state (for example, execution of ART stock lottery by the main CPU 101);
A normal termination means for terminating the advantageous state when the normal termination condition is satisfied in the advantageous state;
Special termination means for terminating said advantageous state if a special termination condition is satisfied in said advantageous state;
The normal ending condition is satisfied when the right is not granted by the right granting means, and a game is played for a predetermined period (for example, an ART continuation possible period) in the advantageous state. ,
The special termination condition may be, for example, when the right is granted by the right granting means, and even if the game is not performed for the predetermined period in the advantageous state, the defined period in the advantageous state (for example, It is satisfied when the game is played until the value of the advantageous section counter reaches "1500",
The specified period includes the period of game in the special game state,
The signal output means is
When the advantageous state is started, the output of the predetermined signal is set to a first state (for example, an on state),
Setting the output of the predetermined signal to a second state (e.g., an off state) when the normal termination condition is satisfied in the advantageous state;
When the special termination condition is satisfied by the special gaming condition control means when the special termination condition is satisfied in the advantageous state, the predetermined termination condition is satisfied when the special gaming condition is not controlled. The output of the signal is in the second state,
When the special game condition is controlled by the special game condition control means when the special termination condition is satisfied in the advantageous state, the predetermined signal is selected when the special game condition is ended. A game machine characterized by setting an output to the second state.

  According to the gaming machine configured as described above, when the advantageous state (for example, the ART gaming state) is forcibly ended due to the regulation, the special gaming state (for example, the bonus state) not affected by this is continued In addition, it can be appropriately informed to the outside that a series of advantageous sections are still continuing. Therefore, even in the case of restricting the acquisition of game media, it is possible to reduce the deterioration of the player's interest.

In the gaming machine of the fifth to seventh configurations,
When a special condition is satisfied (for example, when a bonus combination is won and a combination of symbols relating to the bonus combination is displayed), control is made to a special game state (for example, bonus state) advantageous to the player Special game state control means (for example, main CPU 101)
The gaming machine as described above, wherein the prescribed period includes a game period in the special gaming state.

According to the gaming machine configured as described above, it is possible to appropriately manage a series of advantageous sections in which a state advantageous to the player continues.
[The 9th-the 11th composition's game machine]
In the conventional gaming machine, it is known that the degree of advantage (setting value) of the player regarding the game can be changed by turning on the power with the setting key switch provided in the gaming control device ON. (See, for example, JP-A-2006-055444).

  In the conventional gaming machine, the effect control device reliably receives a command transmitted from the game control device by delaying the activation of the game control device more than the activation of the effect control device (subordinate control device). What was made to be able to do it is known (for example, refer to JP, 2012-205,773A).

  By the way, in recent years, for the purpose of further improving the interest about the effect, the high definition of the image quality of the effect image to be displayed and the sound quality of the BGM to be output has been advanced. For this reason, since the process at the time of start of the effect control device is also complicated, and the amount of data expanded at the time of start is also increased, there is a reality that the start time of the effect control device is longer than before.

  Under such circumstances, it is possible to change the setting value (setting change) if the game control device is to be started after waiting for the start of the effect control device as in the gaming machine of JP 2012-2055773. For example, when performing a store opening operation in a game arcade, a situation occurs in which the setting can not be easily changed even if the game machine is powered on, resulting in work efficiency. Problems such as lowering the

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of improving the work efficiency at the time of power on.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following ninth configuration.

A gaming machine (e.g., pachislot 1) including a game control unit (e.g., main control circuit 90) for controlling a game operation and an effect control unit (e.g., sub control circuit 200) for controlling an effect operation
The game control unit
An arithmetic processing unit (for example, the main CPU 101) that executes various processes for controlling the game operation;
A first storage unit (for example, the main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored;
A second storage unit (for example, the main RAM 103) in which information is stored based on execution of various processes by the arithmetic processing unit;
A security unit (eg, microprocessor 91) having a security function;
A serial communication unit (for example, the first serial communication circuit 114) for performing serial communication;
The first storage unit is
A program area (for example, a program area) in which a program for the arithmetic processing unit to execute various processes is stored;
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored;
A management area (for example, a program management area and a security setting area) in which settings and management information of the arithmetic processing unit and the security unit are stored;
The security unit includes startup delay means for delaying startup of the arithmetic processing unit based on the input of a reset signal,
The game control unit
Communication data registration means (for example, communication data storage processing shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit;
Communication data transmission means (for example, communication data transmission processing shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area via the serial communication unit to the effect control unit;
Transmission delay means (for example, a command transmission start timer) for delaying transmission of communication data by the communication data transmission means for a predetermined period;
Setting value setting means (for example, setting key type switch 54) capable of setting setting values (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game;
The activation delay unit delays activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays transmission of communication data by the communication data transmission means after the start delay of the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of the set value even when the transmission delay means delays transmission of communication data.
The communication data registration means may be arranged in the communication data storage area when setting of the setting value by the setting value setting means is started, even when transmission of communication data is delayed by the transmission delay means. The first communication data (for example, setting change command (setting change / setting confirmation start)) can be registered, and when setting of the setting value by the setting value setting unit is completed, the second communication data storage area Enables the registration of the communication data (for example, setting change command (setting change / setting confirmation end)) of
The communication data transmission unit is configured to register the first communication data and the second communication data in the communication data storage area when the transmission delay of the communication data by the transmission delay unit ends. A game machine characterized by transmitting these communication data in the registered order.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following tenth configuration.

A gaming machine (e.g., pachislot 1) including a game control unit (e.g., main control circuit 90) for controlling a game operation and an effect control unit (e.g., sub control circuit 200) for controlling an effect operation
The game control unit
An arithmetic processing unit (for example, the main CPU 101) that executes various processes for controlling the game operation;
A first storage unit (for example, the main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored;
A second storage unit (for example, the main RAM 103) in which information is stored based on execution of various processes by the arithmetic processing unit;
A security unit (eg, microprocessor 91) having a security function;
A serial communication unit (for example, the first serial communication circuit 114) for performing serial communication;
The first storage unit is
A program area (for example, a program area) in which a program for the arithmetic processing unit to execute various processes is stored;
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored;
A management area (for example, a program management area and a security setting area) in which settings and management information of the arithmetic processing unit and the security unit are stored;
The security unit includes startup delay means for delaying startup of the arithmetic processing unit based on the input of a reset signal,
The game control unit
Communication data registration means (for example, communication data storage processing shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit;
Communication data transmission means (for example, communication data transmission processing shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area via the serial communication unit to the effect control unit;
Transmission delay means (for example, a command transmission start timer) for delaying transmission of communication data by the communication data transmission means for a predetermined period;
Setting value setting means (for example, setting key type switch 54) capable of setting setting values (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game;
The activation delay unit delays activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays transmission of communication data by the communication data transmission means after the start delay of the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of the set value even when the transmission delay means delays transmission of communication data.
The communication data registration means may be arranged in the communication data storage area when setting of the setting value by the setting value setting means is started, even when transmission of communication data is delayed by the transmission delay means. The first communication data (for example, setting change command (setting change / setting confirmation start)) can be registered, and when setting of the setting value by the setting value setting unit is completed, the second communication data storage area Enables the registration of the communication data (for example, setting change command (setting change / setting confirmation end)) of
The communication data transmission means is for transmitting communication data registered in the communication data storage area at regular intervals,
When the first communication data and the second communication data are registered in the communication data storage area when the delay of transmission of communication data by the transmission delay means is completed, these communication data are used. Send in the registered order,
In the case where transmission of communication data is not delayed by the transmission delay means, and when communication data is not registered in the communication data storage area, the communication data registration area is placed in the communication data storage area by the third communication data registration area. A game machine characterized by registering communication data (for example, no operation command) and transmitting the registered third communication data.

  In the gaming machine of the tenth configuration, the third communication data does not include information related to the game operation of the player by the effect control unit.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following eleventh configuration.

A gaming machine (e.g., pachislot 1) including a game control unit (e.g., main control circuit 90) for controlling a game operation and an effect control unit (e.g., sub control circuit 200) for controlling an effect operation
The game control unit
An arithmetic processing unit (for example, the main CPU 101) that executes various processes for controlling the game operation;
A first storage unit (for example, the main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored;
A second storage unit (for example, the main RAM 103) in which information is stored based on execution of various processes by the arithmetic processing unit;
A security unit (eg, microprocessor 91) having a security function;
A serial communication unit (for example, the first serial communication circuit 114) for performing serial communication;
The first storage unit is
A program area (for example, a program area) in which a program for the arithmetic processing unit to execute various processes is stored;
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored;
A management area (for example, a program management area and a security setting area) in which settings and management information of the arithmetic processing unit and the security unit are stored;
The security unit includes startup delay means for delaying startup of the arithmetic processing unit based on the input of a reset signal,
The game control unit
Communication data registration means (for example, communication data storage processing shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit;
Communication data transmission means (for example, communication data transmission processing shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area via the serial communication unit to the effect control unit;
Transmission delay means (for example, a command transmission start timer) for delaying transmission of communication data by the communication data transmission means for a predetermined period;
Setting value setting means (for example, setting key type switch 54) capable of setting setting values (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game;
The activation delay unit delays activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays transmission of communication data by the communication data transmission means after the start delay of the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of the set value even when the transmission delay means delays transmission of communication data.
The communication data registration means may be arranged in the communication data storage area when setting of the setting value by the setting value setting means is started, even when transmission of communication data is delayed by the transmission delay means. The first communication data (for example, setting change command (setting change / setting confirmation start)) can be registered, and when setting of the setting value by the setting value setting unit is completed, the second communication data storage area Enables the registration of the communication data (for example, setting change command (setting change / setting confirmation end)) of
The communication data transmission unit is configured to register the first communication data and the second communication data in the communication data storage area when the transmission delay of the communication data by the transmission delay unit ends. Sends these communication data in the registered order,
A fixed period and a variable period can be set as a delay period of activation of the arithmetic processing unit by the activation delay means,
The fixed period can set one period out of a plurality of periods, and the variable period can set a range of one period out of a plurality of periods. Machine.

Further, in the gaming machine of the eleventh configuration, the variable period is at least at least a range of a first period in which 0 is necessarily determined as the variable period, and the variable period is random within a range from 0 to a predetermined period. The range of the second period to be determined can be set,
A game machine characterized in that a range of the first period is set as the variable period.

  According to the gaming machine having the ninth to eleventh configurations, the security unit can start the gaming control unit stably by delaying the activation of the arithmetic processing unit, and the delay of the activation of the arithmetic processing unit By delaying the transmission of the communication data after completion of the process, it is possible to secure the time required for activating the effect control unit and stably activate the effect control unit.

  Then, after the delay of the activation of the arithmetic processing unit is finished, the setting change can be made even before the delay of transmission of communication data is finished. For example, when opening a store in a game arcade, When the power of the gaming machine is turned on (that is, when the reset signal is input in connection with this), the setting can be changed in advance without waiting for the activation control unit to complete activation. Work efficiency can be improved.

  Furthermore, when the setting change is performed before the delay of transmission of communication data ends, communication data indicating these is registered at the start of the setting change or at the end of the setting change, and the delay of the communication data transmission is Since these communication data are transmitted in the order in which they were registered when the process ends, even if the setting change is made in advance without waiting for the start of the effect control unit to complete, Thus, it is possible to prevent the occurrence of wrinkles in the information held between the game control unit and the effect control unit. In addition, for example, even in the case where the effect control unit is configured to determine the injustice or error according to the order of the communication data transmitted from the game control unit, the effect of such determination is affected. It is possible to make an accurate determination without exerting

  Further, according to the gaming machine of the tenth configuration, at least the predetermined communication data (third communication data) is obtained even when the communication data is not registered when the transmission process of the communication data is performed. Is transmitted, for example, illegal access to the connection between the game control device and the effect control device, etc. to prevent communication data from being transmitted from the outside by unauthorized means, etc. It becomes possible. Further, since the registration and transmission of the predetermined communication data are not performed before the delay of the transmission of the communication data is completed, it is possible to reduce the control burden when the gaming machine is powered on. Note that from the viewpoint of mainly preventing fraudulent acts, the predetermined communication data may not include information related to the game operation of the player.

  Further, according to the gaming machine of the eleventh configuration, the delay period of activation of the arithmetic processing unit is constituted by the fixed period and the variable period, and these periods (or the range thereof) can be appropriately selected and set. Thus, it is possible to set an appropriate delay time according to the specifications of the game control device and the effect control device. If it is possible to set the range of the predetermined period (the range of the first period) in which 0 is necessarily determined as the variable period, from the viewpoint of shortening the period until the setting change becomes possible, The range of the predetermined period may be set.

[The game machine of the 12th-14th composition]
In the conventional gaming machine, when the medals can be accepted and the inserted medals are appropriate medals, the inserted medals are counted by the medal sensor and stored inside the gaming machine, and If the inserted medal is not a proper medal even if it is not in a state where medals can be received or medals can be received, the inserted medals are not counted by the medal sensor, and are outside the gaming machine. There is known one provided with a medal sorting device (selector) for being discharged (see, for example, Japanese Patent Application Laid-Open No. 2006-130213).

  In the medal sorting device (selector) shown in JP 2006-130213 A, when the member (regulating guide plate) whose position is shifted by the drive of the solenoid (regulation guide plate) is in a state where it is possible to receive medals, the inserted medals Is guided in the first direction stored inside the gaming machine by passing the medal sensor, and if the medals can not be received, the inserted medal is not guided in the first direction, and the gaming machine is not It is guided in a second direction discharged to the outside.

  By the way, since the solenoid utilizes magnetic force, it takes some time for excitation and demagnetization. Therefore, depending on the insertion timing of the medal, for example, the inserted medal is counted by the medal sensor because the switching of the guiding direction of the medal is not completed although the medal acceptance is not possible. There is a case where the game is stored inside the gaming machine (that is, the medal "spit-in" occurs).

  If such a situation occurs, not only will the player be given a loss, but also the reliability of the game will be reduced. Therefore, it is desirable to provide a gaming machine capable of properly processing the inserted medals by preventing the generation of the medals such as "spit-in".

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of properly processing inserted gaming media.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following twelfth configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, And state switching means (for example, medal acceptance / start check processing shown in FIGS. 75 and 76) for switching the control state from the receivable state to the unacceptable state when the game start detection unit detects the start operation. ,
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following thirteenth configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
Gaming medium counting means (for example, a credit counter) for counting gaming media when the detection unit detects gaming media;
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, A state switching means for switching the control state from the acceptable state to the unacceptable state when the predetermined number (for example, three) of gaming media is inserted and the gaming start detection unit detects the start operation For example, medal reception / start check processing shown in FIGS. 75 and 76),
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
The gaming medium counting means enables counting of gaming media even when the detection unit detects gaming media during the standby process.
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following fourteenth configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, And state switching means (for example, medal acceptance / start check processing shown in FIGS. 75 and 76) for switching the control state from the receivable state to the unacceptable state when the game start detection unit detects the start operation. ,
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
The drive unit control means shifts the drive unit from the second drive state to the first drive state when the detection unit detects a game medium during the standby process.
In the predetermined period, the distributing unit guides the game medium in the first direction in response to the drive unit controlling means shifting from the first drive state to the second drive state by the drive unit control means. A game machine characterized by being set to a period equal to or longer than a period from the position until the distribution unit moves to the position for guiding the game medium in the second direction.

  In the gaming machine of the fourteenth configuration, the drive unit is a solenoid, the first drive state is a state in which the solenoid is excited, and the second drive state is a demagnetization of the solenoid. A gaming machine characterized by being in a state.

  According to the gaming machine of the twelfth to fourteenth aspects, when the game is started along with the player's start operation, for example, the waiting period for preventing the generation of the medal "snipping" etc. It is set. By this waiting period, the game medium detection unit secures a time until the inserted medal is physically stored in the gaming machine from being physically discharged to the outside of the gaming machine.

  When the medal is inserted during the standby period, the original start operation is invalidated, and in the gaming medium detection unit, the inserted medal is stored inside the gaming machine. Return to Therefore, it is possible to appropriately process the inserted medals by preventing the occurrence of the "snipping" of the medals and the like.

  Further, according to the gaming machine of the thirteenth configuration, even when medals are inserted during the standby period, the medals are counted, thereby preventing the counting omission of the inserted medals. It is possible to process the inserted medals more appropriately.

  Further, according to the gaming machine of the fourteenth configuration, the standby period is equal to or longer than a period of time in which the inserted medal is physically stored in the gaming machine and physically discharged from the gaming machine. Since it is set to the period of (1), it becomes possible to prevent the occurrence of "spit-in" etc. of the medals reliably and to process the inserted medals more appropriately. In addition, when a drive part is a solenoid, such an effect becomes more remarkable.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information indicator, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72: secondary control board, 90: main control circuit, 91: microprocessor, 101: main CPU, 102: main ROM, 103: main RAM, 107: arithmetic circuit, 114: first serial communication circuit, 115: second serial Communication circuit, 200: secondary control circuit, 201: secondary CPU 201, 301: first interface board, 302: second interface board

Claims (3)

It is a gaming machine that plays a game by variably displaying a symbol based on a player's start operation and displaying a symbol based on the player's stop operation.
A normal state, and a first advantageous state, a second advantageous state, and a third advantageous state that are more advantageous to the player than the normal state;
First advantageous state determination means for determining whether or not to shift to the first advantageous state when a specific condition is satisfied in the normal state;
If the specific condition is satisfied in the normal state, and it is determined to shift to the first advantageous state by the first advantageous state determining means, prior to the transition to the first advantageous state Second advantageous state determining means capable of determining whether or not to shift to the second advantageous state;
In the case where the specific condition is satisfied in the normal state, and it is not determined to shift to the first advantageous state by the first advantageous state determining means, the mode is shifted to the third advantageous state And third advantageous state determination means capable of determining whether or not
The first advantageous state, the second advantageous state, and the third advantageous state are states in which information of stop operation advantageous to the player can be notified,
The second advantageous state and the third advantageous state can be ended when the information of the stop operation advantageous to the player is notified a predetermined number of times,
The probability that the information of the stop operation which is advantageous to the player in the second advantageous state is notified more than the predetermined number is that the information of the stop operation which is advantageous to the player in the third advantageous state is more than the predetermined number A gaming machine characterized by having a higher probability than being notified. When it is decided to shift to the second advantageous state by the second advantageous status determining means, and when it is decided to shift to the third advantageous state by the third advantageous status determining means, 2) means for determining the duration of the two advantageous states or the third advantageous state;
The second advantageous state and the third advantageous state end when the duration determined by the duration determining means has elapsed when the information on the stop operation advantageous to the player is notified the predetermined number of times If the information on the stop operation which is advantageous to the player is not notified the predetermined number of times, it does not end even if the duration determined by the duration determining means has passed. The gaming machine described.   3. The information processing apparatus according to claim 1, further comprising: notification means for notifying the player that the game section is an advantageous game section when in the first advantageous state, the second advantageous state, and the third advantageous state. The gaming machine according to Item 2.

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