JP6952556B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine.

Conventionally, a game called pachislot, which is provided with a plurality of reels having a plurality of symbols provided on their respective surfaces, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever is operated by the player (hereinafter, also referred to as "start operation") after the game medium such as a medal or coin is inserted into the game machine, and the rotation of all reels is rotated. Output a signal requesting a start. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting that the rotation of the corresponding reel be stopped. do. The stepping motor transmits its driving force to the corresponding reels. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

In such a gaming machine, when a start operation is detected, a lottery process using random numbers (hereinafter referred to as "internal lottery process") is performed on the program, and the result of the lottery (hereinafter, "internal winning combination") is performed. The rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and the combination of symbols (display combination) related to the establishment of the winning is displayed, the player is given a privilege corresponding to the combination of the symbols. As an example of the privilege given to the player, the payout of the game medium (medals, etc.) and the operation of the re-game (hereinafter, also referred to as "replay") in which the internal lottery process is performed again without consuming the game medium. , The operation of a bonus game that increases the chances of paying out game media can be mentioned.

Further, in such a gaming machine, a function of notifying a procedure of a stop operation advantageous to the player so as to increase the probability of establishment of a specific winning combination (for example, a winning combination related to paying out the gaming medium), that is, an assist time (hereinafter referred to as assist time). , "AT"). In addition, when a specific condition such as displaying a specific symbol combination is satisfied, a function in which a gaming state in which the winning probability of the replay is higher than the normal time is activated, that is, the replay time (hereinafter referred to as "RT") Some have functions. Further, some have an assist replay time (hereinafter referred to as "ART") function in which AT and RT operate at the same time.

Such a gaming machine usually has a gaming control circuit that controls the main gaming operations of the gaming machine, such as determining the internal winning combination, rotating and stopping each reel, and starting and ending the AT, RT, or ART described above. A game control device (main control board) on which a main control circuit is mounted, and an effect control device (sub control board) on which an effect control circuit (sub control circuit) that controls the effect operation of the game machine such as displaying an image is mounted. ), And these control circuits control each of them to control the entire gaming machine.

Conventionally, in such a game machine, the degree of advantage (set value) of the player regarding the game can be changed by turning on the power with the setting key switch provided in the game control device turned on. Is known (see, for example, Patent Document 1).

Further, conventionally, in such a gaming machine, by delaying the activation of the game control device from the activation of the effect control device (dependent control device), the effect control device ensures the command transmitted from the game control device. There is known one that can be received by (see, for example, Patent Document 2).

Japanese Unexamined Patent Publication No. 2006-055444 Japanese Unexamined Patent Publication No. 2012-205773

By the way, in recent years, high-definition such as the image quality of the displayed production image and the sound quality of the output BGM has been advanced for the purpose of further improving the interest in the production. For this reason, the processing at the time of starting the effect control device is complicated, and the amount of data developed at the time of activation is also increased, so that the start-up time of the effect control device is longer than before.

Under such circumstances, if the game control device is to be started after waiting for the start of the effect control device as in the game machine of Patent Document 2, the set value can be changed (setting change). Since the time is also increased, for example, when opening a pachinko / pachislot machine, it may be difficult to change the settings even if the power of the pachinko / pachislot machine is turned on, which reduces work efficiency. There will be a problem such as closing.

The present invention has been made in view of these points, and an object of the present invention is to provide a gaming machine capable of improving work efficiency when the power is turned on.

In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following first configuration.

A gaming machine (for example, pachislot machine 1) having a game control unit (for example, a main control circuit 90) for controlling a game operation and an effect control unit (for example, a sub control circuit 200) for controlling an effect operation.
The game control unit
An arithmetic processing unit (for example, main CPU 101) that executes various processes for controlling game operations, and
A first storage unit (for example, main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit (for example, main RAM 103) in which information is stored based on the execution of various processes by the arithmetic processing unit, and
A security unit having a security function (for example, a microprocessor 91) and
It is configured to include a serial communication unit (for example, a first serial communication circuit 114) that performs serial communication.
The first storage unit is
A program area (for example, a program area) in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and a management area (for example, a program management area and a security setting area) in which settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means (for example, the communication data storage process shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means (for example, a communication data transmission process shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit.
A transmission delay means (for example, a command transmission start timer) that delays the transmission of communication data by the communication data transmission means for a predetermined period, and
A setting value setting means (for example, a setting key type switch 54) capable of setting a setting value (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game is provided.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means sets the communication data storage area in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 (for example, a setting change command (setting change / setting confirmation start)) can be registered, and when the setting of the setting value by the setting value setting means is completed, the second communication data storage area is set. Communication data (for example, setting change command (setting change / setting confirmation end)) can be registered.
When the delay in transmission of communication data by the transmission delay means is completed, the communication data transmission means registers the first communication data and the second communication data in the communication data storage area. Is a gaming machine characterized by transmitting these communication data in a registered order.

Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following second configuration.

A gaming machine (for example, pachislot machine 1) having a game control unit (for example, a main control circuit 90) for controlling a game operation and an effect control unit (for example, a sub control circuit 200) for controlling an effect operation.
The game control unit
An arithmetic processing unit (for example, main CPU 101) that executes various processes for controlling game operations, and
A first storage unit (for example, main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit (for example, main RAM 103) in which information is stored based on the execution of various processes by the arithmetic processing unit, and
A security unit having a security function (for example, a microprocessor 91) and
It is configured to include a serial communication unit (for example, a first serial communication circuit 114) that performs serial communication.
The first storage unit is
A program area (for example, a program area) in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and a management area (for example, a program management area and a security setting area) in which settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means (for example, the communication data storage process shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means (for example, a communication data transmission process shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit.
A transmission delay means (for example, a command transmission start timer) that delays the transmission of communication data by the communication data transmission means for a predetermined period, and
A setting value setting means (for example, a setting key type switch 54) capable of setting a setting value (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game is provided.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means sets the communication data storage area in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 (for example, a setting change command (setting change / setting confirmation start)) can be registered, and when the setting of the setting value by the setting value setting means is completed, the second communication data storage area is set. Communication data (for example, setting change command (setting change / setting confirmation end)) can be registered.
The communication data transmission means transmits communication data registered in the communication data storage area at regular intervals.
When the delay in transmitting the communication data by the transmission delay means is completed and the first communication data and the second communication data are registered in the communication data storage area, these communication data are stored. Send in the registered order,
When the delay in transmitting the communication data by the transmission delay means is completed, the first communication data is registered in the communication data storage area, and if the second communication data is not registered, it is registered. The first communication data is transmitted, and then the registered second communication data is transmitted when the second communication data is registered in the communication data storage area.
When the transmission of communication data is not delayed by the transmission delay means and the communication data is not registered in the communication data storage area, the communication data registration means provides a third communication data storage area. A gaming machine characterized in that the communication data (for example, no operation command) of the above is registered and the registered third communication data is transmitted.

Further, in the gaming machine having the second configuration, the third communication data does not include information related to the gaming operation of the player.

Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following third configuration.

A gaming machine (for example, pachislot machine 1) having a game control unit (for example, a main control circuit 90) for controlling a game operation and an effect control unit (for example, a sub control circuit 200) for controlling an effect operation.
The game control unit
An arithmetic processing unit (for example, main CPU 101) that executes various processes for controlling game operations, and
A first storage unit (for example, main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit (for example, main RAM 103) in which information is stored based on the execution of various processes by the arithmetic processing unit, and
A security unit having a security function (for example, a microprocessor 91) and
It is configured to include a serial communication unit (for example, a first serial communication circuit 114) that performs serial communication.
The first storage unit is
A program area (for example, a program area) in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and a management area (for example, a program management area and a security setting area) in which settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means (for example, the communication data storage process shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means (for example, a communication data transmission process shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit.
A transmission delay means (for example, a command transmission start timer) that delays the transmission of communication data by the communication data transmission means for a predetermined period, and
A setting value setting means (for example, a setting key type switch 54) capable of setting a setting value (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game is provided.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means sets the communication data storage area in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 (for example, a setting change command (setting change / setting confirmation start)) can be registered, and when the setting of the setting value by the setting value setting means is completed, the second communication data storage area is set. Communication data (for example, setting change command (setting change / setting confirmation end)) can be registered.
When the delay in transmission of communication data by the transmission delay means is completed, the communication data transmission means registers the first communication data and the second communication data in the communication data storage area. Sends these communication data in the registered order,
A fixed period and a variable period can be set as the delay period for starting the arithmetic processing unit by the start delay means.
The game is characterized in that the fixed period can be set to one period from a plurality of periods, and the variable period can be set to a range of one period from a range of a plurality of periods. Machine.

Further, in the gaming machine having the third configuration, the variable period is at least a range of a first period in which 0 is always determined as the variable period and a range in which the variable period is 0 to a predetermined period at random. The range of the second period to be determined and can be set,
A gaming machine characterized in that a range of the first period is set as the variable period.

According to the gaming machines having the first to third configurations, the game control unit can be stably started by delaying the activation of the arithmetic processing unit when the power of the gaming machine is turned on, and the arithmetic processing unit can be started stably. By delaying the transmission of communication data after the delay in activation is completed, it is possible to secure the time required to activate the effect control unit and to stably activate the effect control unit.

Then, after the delay in starting the arithmetic processing unit is completed, the setting can be changed even before the delay in transmitting the communication data is completed. Therefore, for example, when opening a game in a game store, the setting can be changed. When the power of the gaming machine is turned on (that is, when a reset signal is input along with it), the setting can be changed in advance without waiting for the activation of the effect control unit to be completed. It is possible to improve the work efficiency in.

Further, if the setting change is made before the delay of the transmission of the communication data ends, the communication data indicating these is registered at the start of the setting change or the end of the setting change, and the delay of the transmission of the communication data is delayed. Since these communication data are transmitted in the order in which they are registered when the operation is completed, even if the setting is changed in advance without waiting for the activation of the effect control unit to be completed, it can be changed. It is possible to prevent a discrepancy in the information held between the game control unit and the effect control unit. Further, for example, even if the effect control unit is configured to determine fraudulent acts, errors, etc. according to the order of communication data transmitted from the game control unit, the result of such determination is affected. It is possible to make an accurate judgment without reaching the above.

Further, according to the gaming machine having the second configuration, at least predetermined communication data (third communication data) is used even when the communication data is not registered when the communication data transmission process is performed. Is transmitted, for example, it is possible to prevent communication data from being transmitted from the outside by an unauthorized means such as illegally accessing the connection line between the game control device and the effect control device. It becomes possible. Further, since the registration / transmission of the predetermined communication data is not performed before the delay in the transmission of the communication data is completed, it is possible to reduce the control load when the power of the gaming machine is turned on. From the viewpoint of preventing fraudulent activity, the predetermined communication data may not include information related to the player's game operation.

Further, according to the gaming machine having the third configuration, the delay period for starting the arithmetic processing unit is composed of a fixed period and a variable period, and these periods (or a range thereof) can be appropriately selected and set. Therefore, it is possible to set an appropriate delay time according to the specifications of the game control device and the effect control device. From the viewpoint of shortening the period until the setting can be changed, if it is possible to set a predetermined period range (the range of the first period) in which 0 is always determined as the variable period, it is possible to set. The range of the predetermined period may be set.

According to the gaming machine having the above configuration, it is possible to provide a gaming machine capable of improving work efficiency when the power is turned on.

It is a figure for demonstrating the functional flow of the gaming machine in one Embodiment of this invention. It is a perspective view which shows the appearance structure of the gaming machine in one Embodiment of this invention. It is a figure which shows the internal structure of the gaming machine in one Embodiment of this invention. It is a figure which shows the internal structure of the gaming machine in one Embodiment of this invention. It is a figure which shows the structure of the selector provided in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the whole structure of the circuit provided in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub-control circuit in one Embodiment of this invention. It is a block diagram of various registers which a main CPU has in one Embodiment of this invention. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure explaining the security mode of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the bonus state and the non-bonus state of pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the ART gaming state, the non-ART gaming state, and the bonus state of the gaming machine in one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows an example of the reel stop initial setting table in one Embodiment of this invention. It is a figure which shows an example of the pull-in priority table in one Embodiment of this invention. It is a figure which shows the structure (the 1) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure (the 2) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows (the 3) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the carry-over combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the correspondence table (the 1) of the internal winning combination and a sub-flag in one Embodiment of this invention. It is a figure which shows the correspondence table (the 2) of the internal winning combination and a sub-flag in one Embodiment of this invention. It is a figure for demonstrating the notification operation at the time of winning subflag EX "triple chili lip" or "reach eye lip" in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the general game state in one Embodiment of this invention. It is a figure which shows an example of the ordinary medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ lottery table in one Embodiment of this invention. It is a figure which shows an example of the mode-up lottery table in CZ1 in one Embodiment of this invention. It is a figure which shows an example of the point lottery table in CZ2 in one Embodiment of this invention. It is a figure which shows an example of the ART lottery table (for CZ1, CZ2) in CZ in one Embodiment of this invention. It is a figure which shows an example of the ART lottery table (for CZ3) in CZ in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in a normal ART in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table in ordinary ART in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the CT state in one Embodiment of this invention. It is a figure which shows an example of the table lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the lottery table which added the number of sets in CT in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the bonus state in one Embodiment of this invention. It is a figure which shows an example of the bonus type lottery table in one Embodiment of this invention. It is a figure which shows an example of the lottery table which added the number of ART games in the bonus in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table at the end of a bonus in one Embodiment of this invention. It is a figure for demonstrating the flow of the game (other) in a general game state in one Embodiment of this invention. It is a figure which shows an example of the non-ART flag conversion lottery table in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the main side navigation data and the sub side navigation data in one Embodiment of this invention. It is a flowchart which shows an example of the power-on (reset interrupt) processing executed by the main control circuit of the gaming machine in one Embodiment of this invention. It is a flowchart which shows the example of the game return processing in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation processing in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the (external) processing at the time of power failure in one Embodiment of this invention. It is a flowchart which shows the example of the checksum generation process (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the main processing (main operation processing) executed by the main control circuit of the gaming machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery processing in one Embodiment of this invention. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compressed data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the control processing by state in one Embodiment of this invention. It is a flowchart which shows the example of the sub-flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the navigation set processing in one Embodiment of this invention. It is a flowchart which shows the example of the flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the normal middle start processing in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start in CZ in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ3 in one Embodiment of this invention. It is a flowchart which shows the example of the processing at the time of a start in a normal ART in one Embodiment of this invention. It is a flowchart which shows the example of the start processing during CT in one Embodiment of this invention. It is a flowchart which shows the example of CT lottery processing in CT in one Embodiment of this invention. It is a flowchart which shows the example of the table data acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of 1 byte lottery processing in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start in BB in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of the logical product operation processing in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control processing in one Embodiment of this invention. It is a flowchart which shows the example of the prize search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of the winning check, medal payout processing in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the BB check process in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of the CZ / ART end processing in one Embodiment of this invention. It is a flowchart which shows the example of the interrupt process executed by the main control circuit of the gaming machine in one Embodiment of this invention. It is a flowchart which shows the example of the communication data transmission processing in one Embodiment of this invention. It is a flowchart which shows the example of the WDT setting process in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment LED drive processing in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment display data generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a timing chart which shows the example of the operation at the time of power-on of the gaming machine in one Embodiment of this invention. It is a timing chart which shows the example of the operation at the time of inserting a medal of the gaming machine in one Embodiment of this invention.

Hereinafter, a pachi-slot machine will be described as an example of a gaming machine according to an embodiment of the present invention, and its configuration and operation will be described with reference to the drawings. In this embodiment, a pachi-slot machine having a bonus operation function and an ART function will be described.

<Functional flow>
First, the functional flow of the pachislot machine will be described with reference to FIG. In the pachislot machine of the present embodiment, a medal is used as a game medium for playing a game. In addition to medals, coins, game balls, point data for games, tokens, and the like can also be applied as the game medium.

When a medal is inserted into the pachislot machine by the player and the start lever is operated, one value (hereinafter referred to as a random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

The internal lottery means draws a lot based on the extracted random number value, and determines the internal winning combination. This internal lottery means is one of various processing means (processing functions) included in the main control circuit described later. By determining the internal winning combination, the combination of symbols that are allowed to be displayed along the valid line (winning determination line) described later is determined in advance. The types of symbol combinations include those related to "winning" in which benefits such as medal payout, replay operation, bonus operation, etc. are given to the player, and other so-called "missing". Such things are provided. In the following, the role related to the payout of medals will be referred to as a "small role", and the role related to the operation of the replay (replay) will be referred to as a "replay role". In addition, the role related to the operation of the bonus (bonus game) is also referred to as a "bonus role".

Further, when the start lever is operated, a plurality of reels are rotated. After that, when the stop button corresponding to the predetermined reel is pressed by the player, the reel stop control means controls to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. conduct. This reel stop control means is one of various processing means (processing functions) included in the main control circuit described later.

In pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec) from the time when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the "number of sliding pieces". Then, in the present embodiment, when the specified period is 190 msec, the maximum number of sliding pieces (maximum number of sliding pieces) is set for four symbols.

When the internal winning combination that allows the combination display of the symbols related to the winning is determined, the reel stop control means usually sets the combination of the symbols to the effective line within the specified time of 190 msec (for 4 symbols). Stop the rotation of the reel so that it is displayed as much as possible along the line. In addition, the reel stop control means uses a predetermined time to stop the rotation of the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the effective line.

In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the effective line is related to winning. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. Then, when it is determined by the winning determination means that the combination of the displayed symbols is related to the winning, a privilege such as a medal payout is given to the player. In pachislot, the above series of flows is performed as one game (unit game).

Further, in pachislot, in the flow of the above-mentioned series of game operations, various effects are produced by displaying an image by a display device, outputting light by various lamps, outputting sound by a speaker, or a combination of these. Is done.

Specifically, when the start lever is operated, a random value for production is extracted in addition to the random value used for determining the internal winning combination described above. When the random value for the effect is extracted, the effect content determining means determines the effect to be executed this time from a plurality of types of effect contents associated with the internal winning combination by lottery. This effect content determining means is one of various processing means (processing functions) included in the sub-control circuit described later.

Next, when the effect content is determined by the effect content determining means, the effect execution means responds in conjunction with each opportunity such as when the reel starts rotating, when each reel stops rotating, and when it is determined whether or not there is a prize. To execute. In this way, in pachislot, for example, by executing the production content associated with the internal winning combination, the opportunity to know or anticipate the determined internal winning combination (in other words, the combination of symbols to be aimed at) is a game. It is provided to the player and can improve the interest of the player.

<Structure of pachislot>
Next, the structure of the pachislot machine according to the embodiment of the present invention will be described with reference to FIGS. 2 to 5.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachislot machine 1.

As shown in FIG. 2, the pachislot machine 1 includes an exterior body (game machine main body) 2. The exterior body 2 has a cabinet (housing) 2a for accommodating a reel, a circuit board, and the like, and a front door (front door) 2b to which an opening of the cabinet 2a can be opened and closed.

Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display row) are provided side by side in a horizontal row. Hereinafter, each reel 3L, 3C, 3R (main reel) is also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (rotation direction of the reel).

The front door 2b includes a door body 9, a front panel 10, a waist panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable by using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachislot machine 1.

The front panel 10 is provided on the upper part of the door body 9. The front panel 10 is composed of a frame-shaped member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is arranged to face the display device 11 which will be described later and is arranged inside the cabinet 2a.

The display device cover 30 is made of a black translucent synthetic resin. Therefore, the player can visually recognize the image (image) displayed by the display device 11 described later through the display device cover 30. Further, in the present embodiment, by forming the display device cover 30 with a black translucent synthetic resin, the entry of external light into the cabinet 2a is suppressed, and the image (image) displayed by the display device 11 is suppressed. Is clearly visible.

A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, the lamps 21a and 21b provided on the upper part of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is composed of an LED (Light Emitting Diode) or the like (see LED group 85 in FIG. 6 described later), and lights are turned on and off in a pattern corresponding to the effect content.

The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 has a decorative panel on which an arbitrary image is drawn, and a light source (LED included in the LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

The pedestal portion 13 is provided between the front panel 10 and the waist panel 12. The pedestal portion 13 has a symbol display area 4, various devices to be operated by the player (medal insertion slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, 3 stop buttons 17L, 17C, 17R, settlement button (not shown), etc.) are provided.

The symbol display area 4 is an area that overlaps the three reels 3L, 3C, 3R when viewed from the front, and is arranged at a position on the player side of the three reels 3L, 3C, 3R, and the three reels. It has a size that makes 3L, 3C, and 3R visible. The symbol display area 4 functions as a display window, and has a configuration in which the reels 3L, 3C, and 3R provided behind the symbol display area 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

The reel display window 4 is arranged continuously among a plurality of symbols provided on the peripheral surface of each reel when the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped. It is configured so that one symbol is displayed in the frame. That is, when the rotation of the three reels 3L, 3C, and 3R is stopped, one symbol is provided in each of the upper, middle, and lower regions for each reel in the frame of the reel display window 4 (three in total). ) Is displayed (in the frame of the reel display window 4, the design is displayed in the form of 3 rows × 3 columns). Then, in the present embodiment, in the frame of the reel display window 4, a pseudo line (center line) connecting the middle stage region of the left reel 3L, the middle stage region of the middle reel 3C, and the middle stage region of the right reel 3R is formed. It is defined as an effective line for determining whether or not a prize has been won.

The reel display window 4 is formed by the opening of the frame member 31 provided in the pedestal portion 13. Further, a pedestal region having a substantially horizontal plane is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, the medal insertion slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1-bet button 15b are provided on the left side.

The medal slot 14 is provided to receive medals dropped on the pachislot machine 1 from the outside by the player. The medals received from the medal slot 14 are used in one game up to a preset predetermined number (for example, 3), and the number of medals exceeding the predetermined number is deposited inside the pachislot machine 1. (So-called credit function (game medium storage means)).

The MAX bet button 15a and the 1-bet button 15b are provided to determine the number of medals to be used for one game from the medals deposited inside the cabinet 2a. Inside the MAX bet button 15a, a bet button LED (not shown) that lights up when a medal can be inserted is provided. In addition, the settlement button is provided to pull out (discharge) the medals deposited inside the pachislot machine 1 to the outside.

When the player presses the MAX bet button 15a, medals for the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, one medal is inserted each time the 1-bet button 15b is pressed once. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the effective line is activated.

In the following, the operation of the MAX bet button 15a, the operation of the 1-bet button 15b, and the operation of inserting medals into the medal insertion slot 14 (operations of inserting medals to perform a game) are all referred to as "insertion operations".

The start lever 16 is provided to start the rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

Further, an information display 6 is provided at substantially the center of the pedestal region on the substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

The information display 6 is a two-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player as a privilege (hereinafter referred to as "the number of payouts") to the player. For digitally displaying (notifying) information such as (hereinafter referred to as "7-segment LED") and the number of medals deposited inside the pachislot 1 (hereinafter referred to as "credit number") to the player. A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of medals to be paid out is a 2-digit 7-segment LED for digitally displaying (notifying) information on the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of medals to be paid out is switched from the display mode of the number of medals to be paid out to the display mode of the information of the error type.

Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on the stop operation necessary for displaying the symbol combination according to the winning combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a 2-digit 7-segment LED. Then, the instruction monitor notifies the player of the necessary stop operation information by turning on, blinking, or turning off the two-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. do. That is, for example, in the ART gaming state described later, which is advantageous for the player, information on the stop operation advantageous for the player (see FIG. 24, which will be described later) is notified.

The mode that uniquely corresponds to the information of the stop operation to be notified here is, for example, in the case of notifying the push order "1st (performing the first stop operation on the left reel 3L)". When the numerical value "1" is displayed on the instruction monitor and the push order "2nd (perform the first stop operation on the middle reel 3C)" is notified, the numerical value "2" is displayed on the instruction monitor and the push order is displayed. When notifying "3rd (performing the first stop operation on the right reel 3R)", the numerical value "3" is displayed on the instruction monitor.

As shown in FIG. 6 described later, the information display 6 is electrically connected to the main control board 71 via the door relay terminal board 68 and the game operation display board 81, and the display operation of the information display 6 is mainly performed. It is controlled by the main control circuit 90 described later in the control board 71. Further, the control method of the various 7-segment LEDs described above is dynamic lighting control.

In the pachi-slot machine 1 of the present embodiment, in addition to the instruction monitor controlled by the main control board 71, another means controlled by the sub-control board 72 is used to notify the information of the stop operation. Specifically, the information on the stop operation is notified by the display device 11 described later, which is composed of the projector mechanism 211 and the display unit 212 (see FIGS. 3 and 6 described later) described later.

When such a configuration is applied, the mode of notification in the instruction monitor and the mode of notification in other means controlled by the sub-control board 72 may be different from each other. That is, in the instruction monitor, the information of the stop operation to be notified may be notified in a manner uniquely corresponding to the information of the stop operation, and it is not always necessary to directly notify the information of the stop operation (for example, the numerical value "1" in the instruction monitor. Even if is displayed, it may not be possible to specify the content of the notification depending on the player, so it cannot be said to be a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, the information of the stop operation may be directly notified. For example, when the push order "1st" is notified, the instruction monitor displays a numerical value "1" that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11 or the like) display the left reel 3L. The instruction information for performing the first stop operation may be directly notified to the user.

In the pachi-slot machine 1 having such a configuration, it is possible to notify the information of the necessary stop operation according to the internal winning combination not only by the control of the sub control board 72 but also by the control of the main control board 71. Further, the presence / absence of notification of such stop operation information may be controlled according to the gaming state. For example, the stop operation information may be notified in the ART game state (see FIG. 14 described later) without notifying the stop operation information in the general game state (non-ART game state) described later.

Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub-display device 18 is provided so as to stand substantially perpendicular to the pedestal region of the pedestal portion 13 in a substantially horizontal plane in the front portion of the door body 9. The sub-display device 18 is composed of a liquid crystal display and an organic EL (Electro-Luminescence) display, and displays various information.

Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 6 described later). The touch sensor 19 operates according to a predetermined operating principle such as a capacitance method, and when it receives an operation of a player, it outputs a signal corresponding to the operation as touch input information. The pachi-slot machine 1 of the present embodiment has a function of enabling the display of the sub-display device 18 to be switched according to the player's operation (touch input information output from the touch sensor 19) received via the touch sensor 19. Has. The sub display device 18 is controlled by the sub control board 72 (see FIG. 6 described later) based on the touch input information output from the touch sensor 19.

At the lower part of the door body 9, a medal payout outlet 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout outlet 24 guides the medals discharged by driving the medal payout device 51, which will be described later, to the outside. The medal tray 25 stores medals discharged from the medal payout outlet 24. Further, sound effects such as sound effects and music corresponding to the contents of the production are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachi-slot machine 1 will be described with reference to FIGS. 3 to 5. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, FIG. 4 is a diagram showing the internal structure on the back surface side of the front door 2b, and FIG. 5 is a diagram showing the internal structure on the back surface side of the front door 2b, which will be described later. It is a figure which shows the structure of a selector 66.

As shown in FIG. 3, the cabinet 2a has a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. A display device 11 is arranged in the upper part of the cabinet 2a.

The display device 11 has a projector mechanism 211 and a box-shaped projected member 212a on which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, the display device 11 generates image light based on the position (projection distance, angle, etc.) and shape of the projected member 212a, which is a three-dimensional object, and the image light is emitted by the projector mechanism 211 to the projected member. It is projected on the surface of 212a. By providing such an effect function, it is possible to perform an advanced and powerful effect. Further, although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and one of the projected members is provided depending on the gaming state. , Used as a screen on which video light is projected. Therefore, the inside of the cabinet 2a is also provided with a function (not shown) for switching the projected member according to the gaming state.

A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged in the lower part of the cabinet 2a.

The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large number of medals and ejecting them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds, for example, 50, or when the settlement button is pressed and the settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. Further, the medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

The power supply device 53 includes a power supply switch 53a and a power supply board 53b (power supply means) (see FIG. 6 described later). The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the AC voltage 100V power supplied from the sub power supply device (not shown) into the DC voltage power required by each part, and supplies the converted power to each part.

Further, above the power supply device 53 in the cabinet 2a, a sub-control board case 57 for accommodating the sub-control board 72 (see FIG. 6 described later) is arranged. A sub-control circuit 200 (see FIG. 9 to be described later) described later is mounted on the sub-control board 72 housed in the sub-control board case 57. The sub-control circuit 200 is a circuit that controls the execution of an effect by displaying an image or the like. The specific configuration of the sub-control circuit 200 will be described later.

The sub-relay board 61 is arranged above the sub-control board case 57 in the cabinet 2a. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the main control board 71, which will be described later, is mounted. Further, the sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and a board arranged around the sub-control board 72, various device units (units), and the like is mounted.

Further, although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 6 described later) is arranged in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 6 described later), a hopper device 51, a medal auxiliary storage switch 75 (see FIG. 6 described later), and a medal payout count switch (not shown). It is a relay board on which the wiring for connecting the above is mounted.

As shown in FIG. 4, a middle door 41 is arranged at the center of the front door 2b on the back surface side, and a reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, and 3R are attached to the reel display window 4 side of the middle door 41, and the main control is on the side of the middle door 41 opposite to the reel display window 4 side. A main control board case 55 in which the board 71 (see FIG. 6 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R via gears having a predetermined reduction ratio.

The main control board 71 housed in the main control board case 55 has a main control circuit 90 (see FIGS. 7 and 8 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot machine 1, such as determining the internal winning combination, rotating and stopping the reels 3L, 3C, and 3R, and determining whether or not there is a prize. .. Further, in the present embodiment, for example, the main control circuit 90 also controls the lottery processing of whether or not the ART is determined, the display processing of the navigation information on the instruction monitor, the transmission processing of various test signals, and the like. The specific configuration of the main control circuit 90 will be described later.

Speakers 65L and 65R are arranged below the middle door 41 on the back surface side of the front door 2b. The speakers 65L and 65R are arranged at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

A selector 66 and a door open / close monitoring switch 67 are arranged above the speaker 65L. The selector 66 is a device that detects medals inserted into the medal insertion slot 14, and also is a device that selects whether or not the inserted medals are appropriate medals, and is selected as an appropriate medal. In that case, the medal is guided to the hopper device 51 side and driven so as to be housed in the hopper device 51, and if it is selected as not a proper medal, the medal is moved to the medal payout outlet 24 side. Is guided and driven so that the medal is discharged from the medal payout outlet 24. That is, the selector 66 is also a device that distributes the medals inserted into the medal insertion slot 14 to the hopper device 51 side or the medal payout outlet 24 side.

As shown in FIG. 5, the selector 66 includes a base 803 on which a medal rail (medal passage) 802 through which medals pass is formed, and a select plate that guides the inserted medals to the hopper device 51 side or the medal payout outlet 24 side. 804, a medal pusher 805 that pushes the inserted medal to the medal payout outlet 24 side when the inserted medal is not an appropriate medal, and an upstream medal sensor (first) that detects the inserted medal on the upstream side of the medal rail 802. It includes a medal sensor) 806 and a downstream medal sensor (second medal sensor) 807 that detects the inserted medal on the downstream side of the medal rail 802.

Further, although not shown in FIG. 5, the selector 66 has a medal guide (which forms a medal flow path from the selector 66 to the hopper device 51 when the medal is guided to the hopper device 51 side by the select plate 804. (Not shown) and a cancel chute (not shown) that forms a medal flow path from the selector 66 to the medal payout outlet 24 when the medal is placed on the medal payout outlet 24 side by the select plate 804 can be attached and detached. It is attached.

The select plate 804 is driven by a solenoid (not shown) included in the selector 66. The select plate 804 moves to a guide position that guides the passing medal to the hopper device 51 side when the solenoid is driven, but does not guide the passing medal to the hopper device 51 side when the solenoid is not driven. Move to the discharge position (that is, guide to the medal payout outlet 24 side). Specifically, when the solenoid is driven, the select plate 804 moves in the rearward direction of the pachislot 1 and guides the upper part of the medal, while when the solenoid is not driven, the select plate 804 moves toward the rear side of the pachislot 1 and guides the upper part of the medal. It is designed not to move forward and guide above the medal. The medal guide method using the select plate 804 is not limited to this, and for example, the guide position and the discharge position can be moved by using a mechanism that can move the pachislot 1 in the vertical direction. You may. That is, the select plate 804 has a guide position that does not prevent the passing medal from moving to the hopper device 51 side on the medal rail 802 by a solenoid or other drive source, and the passing medal moves to the hopper device 51 side. Any mechanism can be adopted as long as it is a mechanism that prevents the movement from being carried out and enables the transfer from the discharge position to be guided to the medal payout outlet 24 side.

For example, when the select plate 804 is moved to the guide position, the medal pusher 805 operates so as not to protrude in the rearward direction of the pachi-slot machine 1, and the select plate 804 is not moved to the guide position (discharge position). In the case of (moving to), it operates so as to project in the rearward direction of the pachislot machine 1. That is, when the medal pusher 805 is in a position where it does not protrude in the rearward direction of the pachislot 1, it becomes a guide position for guiding the passing medal toward the hopper device 51, and when it is in a position where it protrudes in the rearward direction of the pachislot 1. It is a discharge position that does not guide the passing medal to the hopper device 51 side (that is, guides it to the medal payout outlet 24 side).

The upstream medal sensor 806 and the downstream medal sensor 807 constitute a game medium detecting means for detecting that a medal has passed. Each medal sensor is composed of, for example, a pair or a plurality of pairs of light emitting elements and a reflective sensor composed of a light receiving element, irradiates the medal with light from the light emitting element, and emits the reflected light reflected from the medal. When the light receiving element receives light, the passage of the medal is detected. The configuration of the sensor can be changed as appropriate, and for example, a transmissive sensor or the like can be adopted. Further, the passage of medals may be detected only by the downstream medal sensor 807 without providing the upstream medal sensor 806. Further, specific control based on the detection result (medal sensor input state) of each medal sensor will be described later.

The door open / close monitoring switch 67 is arranged diagonally to the lower left of the selector 66 when the front door 2b is viewed from the back surface side. The door open / close monitoring switch 67 outputs a security signal for notifying the open / close of the front door 2b to the outside of the pachislot machine 1.

Further, although not shown in FIG. 4, a door relay terminal plate 68 is arranged on the back surface of the front door 2b, which is a region opened and closed by the middle door 41 and below the reel display window 4 (FIG. 4 described later). 6). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, and the like. This is a relay board on which wiring for connecting each of the second interface boards 302 for a testing machine is mounted. Examples of the various buttons and switches include the MAX bet button 15a, the 1-bet button 15b, the door open / close monitoring switch 67, the BET switch 77 described later, the start switch 79, and the like.

<Control system provided by pachislot>
Next, the control system included in the pachi-slot machine 1 will be described with reference to FIG. FIG. 6 is a circuit block diagram showing the configuration of the control system of the pachislot machine 1.

The pachi-slot machine 1 has a main control board 71 provided on the middle door 41 and a sub control board 72 provided on the front door 2b. Further, the pachi-slot machine 1 has a reel relay terminal board 74, a setting key type switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot machine 1 has an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via a cabinet-side relay board 44. Since the configuration of the hopper device 51 has been described above, the description thereof will be omitted here.

The reel relay terminal plate 74 is arranged inside the reel main body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R, and relays a signal output from the main control board 71 to the stepping motor.

The setting key type switch 54 is provided in the main control board case 55. The setting key type switch 54 is used when changing the setting value (setting 1 to setting 6) of the pachi-slot 1 or when confirming the setting of the pachi-slot 1. The set value indicates the degree of the player's advantage in the game, and usually, the lower the set value (for example, the closer to the setting 1), the lower the degree of the player's advantage. Therefore, the higher the set value (for example, the closer to the setting 6), the higher the degree of advantage of the player. In the present embodiment, the higher the set value, the higher the winning probability of the bonus combination described later, and the degree of the player's advantage can be changed. The higher the set value, the more ART or CT described later. It is also possible to change the degree of advantage of the player by increasing the winning probability of the lottery.

The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external centralized terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. Is. The external centralized terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52, and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot machine 1.

The power supply device 53 includes a power supply board 53b and a power supply switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot machine 1. The power supply board 53b is connected to the main control board 71 via the cabinet side relay board 44, and is also connected to the sub control board 72 via the sub relay board 61.

Further, the pachi-slot machine 1 has a selector 66, a door open / close monitoring switch 67, a BET switch 77, and a settlement switch 78, which are connected to the main control board 71 via the door relay terminal plate 68 and the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub-relay board 61, a first interface board 301 for a testing machine, and a second interface board 302 for a testing machine. Since the selector 66, the door open / close monitoring switch 67, and the sub-relay board 61 have been described above, their description will be omitted here.

The BET switch 77 (throwing operation detecting means) detects that the MAX bet button 15a or the 1-bet button 15b is pressed by the player. The settlement switch 78 detects that the settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

The stop switch board 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stoptable main reel by an LED or the like. Further, the stop switch board 80 is provided with a stop switch (not shown). The stop switch detects that each of the stop buttons 17L, 17C, 17R is pressed by the player (stop operation).

The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 is, for example, three LEDs for displaying the number of inserted medals (hereinafter, "first LED" to "", which are lit according to the number of medals inserted in this game (hereinafter referred to as "the number of inserted medals"). An LED that lights a mark indicating that medals can be inserted, a mark indicating the start of a game, a mark for replaying a game, etc., based on a signal input from the game operation display board 81 (referred to as "third LED"). Etc. are included. In the first LED to the third LED (display means), when one medal is inserted, the first LED lights up, and when two medals are inserted, the first and second LEDs light up, and three medals (game). When the number of startable medals is turned on, the first LED to the third LED are turned on. Since the information display 6 has been described above, the description thereof will be omitted here.

Both the first interface board 301 for the testing machine and the second interface board 302 for the testing machine are relay boards used when outputting various signals related to the game to the testing machine in the certification test (test firing test) of the pachislot 1 (test firing test). Since these relay boards are not mounted on the Pachislot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for the testing machine and the testing machine. Various electronic components required for connecting to the second interface board 302 for use are also not mounted). For example, a test signal for controlling a main operation related to a game (for example, internal lottery, reel stop control, etc.) is output via a first interface board 301 for a testing machine, and is determined by, for example, a main control board 71. The test signal and the like related to the pushed order navigation are output via the second interface board 302 for the testing machine.

The sub-control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub-relay board 61. Further, the pachi-slot machine 1 has a speaker group 84, an LED group 85, a 24h door open / close monitoring unit 63, a touch sensor 19 and a display unit 212 connected to the sub-control board 72 via the sub-relay board 61. Since the touch sensor 19 has been described above, the description thereof will be omitted here.

The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source that emits light for illuminating the decorative panel of the waist panel 12 from the back side, and the like. The 24h door open / close monitoring unit 63 stores the open / close history information of the middle door 41. Further, the 24h door open / close monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projected member 212a constituting the display device 11 and another projected member having a curved display surface provided on the back side of the projected member 212a.

Further, the pachi-slot machine 1 has a ROM cartridge board 86 and a liquid crystal relay board 87 connected to the sub-control board 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub-control board case 57 together with the sub-control board 72.

The ROM cartridge board 86 is a board for managing various control programs executed by the sub CPU 201, image (video) for production, audio (speaker group 84), light (LED group 85), and communication data. .. The liquid crystal relay board 87 is a board that relays the connection wiring between the sub-control board 72, the projector mechanism 211 constituting the display device 11, and the sub-display device 18. Since the projector mechanism 211 and the sub-display device 18 have been described above, their description will be omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. 7. FIG. 7 is a block diagram showing a configuration example of the main control circuit 90 of the pachislot machine 1.

The main control circuit 90 functions as a game control unit that controls game operations, and includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

The microprocessor 91 is a microprocessor with a security function for a gaming machine. The microprocessor 91 of the present embodiment is provided with various instruction codes (hereinafter, referred to as "main CPU 101 dedicated instruction codes") specific to the microprocessor 91 that can be specified in the program. In the present embodiment, the processing efficiency and the reduction of the program capacity are realized by using the instruction code dedicated to the main CPU 101. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 8 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by the main control circuit described later. do.

The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

The power supply management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 6). Then, the power supply management circuit 93 outputs a reset signal to the "XSRST" terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the starting voltage value (10V) from 0V). When a power failure occurs (when the power supply voltage falls below the power failure voltage value (10.5V) from 12V), the power failure detection signal is output to the "XINT" terminal of the microprocessor 91. That is, the power management circuit 93 is a means (starting means) for outputting a reset signal (starting signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means for outputting (power failure means).

The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of DC 5 V) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 8 is a block diagram showing an internal configuration of the microprocessor 91.

The microprocessor 91 includes a main CPU 101 (arithmetic processing unit), a main ROM 102 (first storage unit), a main RAM 103 (second storage unit), an external bus interface 104, a clock circuit 105, a reset controller 106, and the like. It has an arithmetic circuit 107, a random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115. Each of these parts constituting the microprocessor 91 is connected to each other via a signal bus 116.

The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 to perform control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

The main CPU 101 counts the number of times a pulse is output to the stepping motors of each reel 3L, 3C, 3L (main reel) after detecting the reel index. As a result, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. This reel index is, for example, an optical sensor having a light emitting unit and a light receiving unit, and a detection piece provided at a predetermined position on each reel and interposed between the light emitting unit and the light receiving unit by rotation of each main reel. It is detected by the provided reel position detection unit (not shown).

Here, the management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the output of a predetermined number of pulses required for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is added one by one. The symbol counter is provided according to each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detection unit (not shown).

That is, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub-control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by executing a control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG. 11 described later.

The external bus interface 104 is for electrically connecting the microprocessor 91 to an external signal bus (not shown) to which various components (for example, reels and the like) provided outside the microprocessor 91 are connected. It is an interface circuit. The clock circuit 105 is configured to include, for example, a frequency divider (not shown), and a clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is transmitted by another component (for example, a timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

The reset controller 106 resets the IAT (Illegal Address Trap) and the WDT (watchdog timer) based on the reset signal input from the power supply management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when executing a "MUL" instruction on a program, the arithmetic circuit 107 executes a multiplication process based on the "MUL" instruction.

The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 has random number registers 0 for obtaining 2-byte hard-latch random numbers, random number registers 1 to 3 for obtaining 2-byte soft-latch random numbers, and 1-byte soft-latch random numbers. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from the random numbers in a predetermined range generated by the random number circuit 110, for example, as a random number value for internal lottery. The parallel port 111 is a port (memory map I / O) of signals input / output between the microprocessor 91 and various circuits (for example, power management circuit 93, etc.) provided outside the microprocessor 91. .. The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is also connected to any of the input ports of PI0 to PI4 of the parallel port 111, and latches from the parallel port 111 to the random number register 0 of the random number circuit 110 at the timing (on-edge) when the start switch 79 is turned on. A signal is output. Then, in the random number circuit 110, the random number register 0 is latched by the input of the latch signal, and a 2-byte hard latch random number is acquired.

The interrupt controller 112 interrupts processing by the main CPU 101 based on a power failure detection signal input from the power management circuit 93 via the parallel port 111 or a timeout signal input from the timer circuit 113 at a cycle of 1.1172 ms. Controls the execution timing of. When a power failure detection signal is input from the power management circuit 93, or when a timeout signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. The main CPU 101 has an input port check process, a reel control process, a communication data transmission process, a 7-segment LED drive process, and a timer based on an interrupt request signal input from the interrupt controller 112 in response to a timeout signal from the timer circuit 113. Various interrupt processing such as update processing (see FIG. 114 described later) is performed.

The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (a clock pulse signal having a frequency obtained by dividing the clock pulse signal for operating the main CPU by a divider (not shown)) ( Count the elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) are transmitted from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls the serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Sub-control circuit>
Next, with reference to FIG. 9, the configuration of the sub-control circuit 200 (sub-control means) mounted on the sub-control board 72 will be described. FIG. 9 is a block diagram showing a configuration example of the sub-control circuit 200 of the pachi-slot machine 1.

The sub-control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of the effect content based on a command transmitted from the main control circuit 90. The sub-control circuit 200 functions as an effect control unit that controls the effect operation, and basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

The sub CPU 201 is connected to the ROM cartridge board 86. The driver 205 is connected to the liquid crystal relay board 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub-display device 18 via the liquid crystal relay board 87.

The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 90. The ROM cartridge board 86 is basically composed of a program storage area and a data storage area.

The control program executed by the sub CPU 201 is stored in the program storage area. For example, in the control program, the main board communication task for controlling the communication with the main control circuit 90 and the effect registration for extracting the random value for the effect and determining and registering the effect content (effect data). Contains various programs for executing tasks. Further, the control program includes a drawing control task that controls the display of an image by the display device 11 based on the determined effect content, a lamp control task that controls the output of light by a light source such as the LED group 85, and a sound by the speaker group 84. It also includes various programs for executing voice control tasks and the like that control the output of the LED.

The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to video creation. The data storage area also includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a pattern of turning on and off light, and the like.

The sub RAM 202 is provided with a storage area for registering the determined effect content and effect data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create an image according to the animation data specified by the effect content, and display the created image on the display device 11 (projector mechanism 211) and /. Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub-display device 18 are individually controlled by the sub-control board 72.

Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the effect content. Further, the sub CPU 201 controls the lighting and extinguishing of the LED group 85 according to the lamp data specified by the effect content.

<Various registers of the main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. Note that FIG. 10 is a schematic configuration diagram of various registers included in the main CPU 101.

As the main register, the main CPU 101 includes an accumulator A (hereinafter referred to as "A register"), a flag register F (flag register), a general-purpose register B (hereinafter referred to as "B register"), and a general-purpose register C (hereinafter referred to as "B register"). General-purpose register D (hereinafter referred to as "D register"), general-purpose register E (hereinafter referred to as "E register"), general-purpose register H (hereinafter referred to as "H register"), and general-purpose register L (hereinafter referred to as "H register"). , "L register"). Further, as sub-registers, the main CPU 101 includes an accumulator A', a flag register F', a general-purpose register B', a general-purpose register C', a general-purpose register D', a general-purpose register E', a general-purpose register H', and a general-purpose register L'. As a general-purpose register. Each register is composed of 1-byte registers.

Further, in the present embodiment, the B register and the C register are used as a pair register (hereinafter, referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter, referred to as “DE register”). Further, in the present embodiment, the H register and the L register are used as a pair register (hereinafter, referred to as "HL register").

As shown in FIG. 10, predetermined flag information indicating the result of arithmetic processing and the like is set in each bit of the flag registers F and F'. For example, bit 6 (D6) is set with data (zero flag) indicating whether or not the calculation result is "0" in the calculation result determination process. Specifically, when the calculation result is "0", the data "1" is set in the bit 6, and when the calculation result is not "0", the data "0" is set in the bit 6. Then, in the calculation result determination process, the main CPU 101 makes a determination (YES / NO) with reference to the bit 6 data “0” / “1”.

Further, the main CPU 101 has an expansion register Q (hereinafter, referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as described in various processing flows described later, various main CPU 101 dedicated instruction codes for specifying an address using this Q register are provided in the program, and the instruction code of this instruction code is provided. By using it, processing efficiency is improved and the capacity of the main ROM 102 is reduced. In various main CPU 101 dedicated instruction codes that specify an address using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. Immediately after the reset of the main CPU 101, "F0H" is set in the Q register as an initial value. Further, in the "LDQ, n (8-bit data)" instruction using the Q register, the value of the Q register is changed by setting arbitrary 1-byte data in "n" and executing the instruction. Can be done.

Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R composed of 1-byte registers, and an index register IX and an index register IY composed of 2-byte registers. , The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configurations (hereinafter referred to as “memory maps”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 11A to 11C. 11A is a diagram showing a memory map of the entire memory, FIG. 11B is a diagram showing a memory map of the main ROM 102, and FIG. 11C is a diagram showing a memory map of the main RAM 103.

In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 11A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, and The XCS decoding areas are arranged at predetermined addresses in this order with an unused area in between.

In the memory map of the main ROM 102, as shown in FIG. 11B, the program area, the data area, the non-standard area, the trademark recording area, the program management area, and the security setting area are displayed from the head (0000H) side of the address of the main ROM 102. In order, they are arranged at predetermined addresses.

In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to the playability of the game performed by the player are stored. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, and various types for the sub-control circuit 200 in various control processes related to the playability of the game performed by the player). Data for transmitting control commands (commands), etc.) are stored. That is, the game ROM area (game storage area) composed of the program area and the data area is necessary for the control process (process related to the game property) related to the game playability of the game actually performed by the player at the game store. Various programs and various data are stored.

Further, in the non-standard area, control programs and data of various processes (processes that do not affect the playability) that are not directly related to the playability of the game performed by the player are stored. For example, programs and data used in the pachislot 1 certification test (test firing test), control programs and data used in checksum generation processing at the time of power failure and thumb check processing at power recovery, and fraud countermeasure programs. And the data required for it are stored in the non-standard area.

Further, in the program management area and the security setting area, various settings and management information related to the execution of the control program or the security function are stored. For example, setting and management information of the start address and end address (that is, data range) of the control program stored in the program area, setting and management information of the number of addresses of the RAM area that can be read, WDT reset setting and management information, Interrupt setting and management information, read permission / non-permission setting and management information of the control program stored in the program area, setting and management information related to activation and update method of the random number circuit 110, and security mode setting described later. And management information and the like are stored in the program management area and the security setting area. In the present embodiment, other settings and management information not related to the security function are stored in the program management area, and settings and management information related to the security function are stored in the security setting area. For example, these settings and management information may be stored as a single management area.

In the memory map of the main RAM 103, as shown in FIG. 11C, the game RAM area (predetermined storage area, game temporary storage area) and the non-standard RAM area (non-standard temporary) from the head (F000H) side of the address of the main RAM 103. Storage areas) are arranged at predetermined addresses in this order.

The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by executing a control program related to the game playability performed by the player. .. Then, each of the various data is stored in the work area of a predetermined address in the game RAM area.

Further, the non-standard RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the playability of the game performed by the player, and a non-standard stack. In the present embodiment, using this non-standard RAM area, various processes that are not directly related to the playability of the game performed by the player, such as a checksum process, are executed.

As described above, in the pachi-slot machine 1 of the present embodiment, various programs and various data (tables) used for various processes not directly related to the playability of the game performed by the player are used for the game in the main ROM 102. It is stored in a non-standard ROM area (non-standard storage area) located at an address different from the ROM area. In addition, various processes that are not directly related to the playability of the game performed by such a player are performed in the main RAM 103 using an out-of-specification RAM area located at an address different from the game RAM area. ..

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in the ROM area (non-standard ROM area) where the program or the like cannot be arranged according to the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the gaming ROM area.

<Security mode>
Next, a security mode, which is a part of the security function of the main control circuit 90 (microprocessor 91), will be described with reference to FIG. Note that FIG. 12 is a diagram for explaining the security mode.

The security mode is, for example, an operating state in which the microprocessor 91 operates when the power of the pachi-slot machine 1 is turned on and a reset signal is input from the power management circuit 93. During this security mode, the startup of the main CPU 101 is delayed for a period corresponding to the setting stored in the security setting area (that is, the main CPU 101 starts execution of the power-on processing (see FIG. 64 described later). To delay). By starting the main CPU 101 through this security mode, the security of the microprocessor 91 is ensured, and the time required for the start control at the time of turning on the power is secured to stably start the main CPU 101.

In the present embodiment, for example, the reset controller 106 can delay the startup of the main CPU 101 by delaying the reset signal input when the power is turned on for a predetermined period, and the interrupt controller 112 can delay the startup of the main CPU 101. It is also possible to delay the startup of the main CPU 101 by delaying the interrupt permission of the reset interrupt process (see FIG. 64 described later) at the time of turning on the power for a predetermined period. It is also possible for each controller to work together to delay the startup of the main CPU 101. Further, for example, a delay circuit may be provided in the microprocessor 91 (or in the reset controller 106 or the interrupt controller 112), and the delay circuit may delay the startup of the main CPU 101. That is, the configuration (security unit) that executes the security function in the microprocessor 91 can be appropriately modified and applied according to the specifications.

As shown in FIG. 12, the delay period in the security mode can be set to a fixed extension time (fixed period) and a random extension time (variable period). In the present embodiment, for example, by selecting and setting one of the modes 1 to 8 in which different fixed extension times are associated with each other, one fixed extension from a plurality of fixed extension times is set. The time can be set, and by selecting and setting one of the modes 1 to 4 in which different random extension time ranges are associated with each other, a plurality of random extension time ranges can be set. It is possible to set a range of one random extension time from the inside.

For example, when "mode 4" is selected as the fixed extension time and "mode 4" is selected as the random extension time, and these settings are stored in the security setting area, the microprocessor 91 turns on the power of the pachislot 1. When the reset signal is input from the power management circuit 93, first, the start-up of the main CPU 101 is delayed for about 4 seconds (4000 ms) as the fixed extension time, and then the random extension time is in the range of 0 to 500 ms. One extension time is randomly selected to delay the startup of the main CPU 101 for the selected time.

The range of the fixed extension time and the random extension time can be set as appropriate, but in the present embodiment, the range of the random extension time is set from the viewpoint of shortening the time until the setting can be changed when the power of the pachislot machine 1 is turned on. It is desirable to set "mode 1" in which the random extension time is always "0".

<Transition flow of game state>
Next, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachi-slot machine 1 of the present embodiment and their transition flows will be described with reference to FIGS. 13 and 14. Note that FIG. 13A is a transition flow diagram of the basic gaming state of the pachislot machine 1, and FIG. 13B is a table summarizing the transition conditions of the gaming state. Further, FIG. 14A is a transition flow diagram of a gaming state in consideration of whether or not the notification (ART) function is activated, and FIG. 14B is a table summarizing the transition conditions of the gaming state.

[Basic game state transition flow]
In the pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") is provided as a type of bonus game. The BB is a continuous accessory actuating device for a regular bonus (hereinafter referred to as “RB”) called a first-class special accessory, and continuously operates the RB.

Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on the presence or absence of winning / operating (winning) of the bonus combination. Specifically, as shown in FIG. 13A, the main control circuit 90 is based on the presence or absence of a winning / operating (winning) of a bonus combination (internal winning combination of the names "F_BB1" and "F_BB2" described later). It manages three types of gaming states called "bonus non-winning state", "inter-flag state", and "bonus state".

The bonus non-winning state is a state in which the bonus is not winning and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, a state in which the bonus combination is won and the bonus is not activated.

Whether or not the bonus combination is won is determined by the data stored in the hit request flag storage area (see FIGS. 28 to 30 described later) and the carry-over combination storage area (see FIG. 31 described later) provided in the main RAM 103. It is managed based on. Further, whether or not the bonus is activated (winning) is managed based on the data stored in the game state flag storage area (see FIG. 32 described later) provided in the main RAM 103.

Further, in the present embodiment, as shown in FIG. 13A, in the gaming state in which the bonus is not activated (bonus non-winning state and inter-flag state), the types of internal winning combinations related to replay and the winning probabilities thereof are different from each other. Six types of states from the RT0 gaming state to the RT5 gaming state (hereinafter, referred to as "RT0 state" to "RT5 state", respectively) are provided. The RT0 state, RT2 state, and RT5 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is low, and the RT1 state has a medium probability that the replay combination is determined as the internal winning combination. It is a gaming state with a medium probability. Further, the RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is any of the RT0 state to the RT4 state, and the RT state in the inter-flag state is the RT5 state.

Therefore, in the present embodiment, the main control circuit 90 is based on the type of the internal winning combination related to the replay and the winning probability thereof in the gaming state (bonus non-winning state and inter-flag state) in which the bonus is not activated. It also manages six types of states, RT1 state to RT5 state.

The RT0 state to the RT5 state are managed based on the data stored in the game state flag storage area (see FIG. 32 described later) provided in the main RAM 103. Specifically, in the pachi-slot machine 1 of the present embodiment, flags indicating five RT states of the RT1 state flag to the RT5 state flag are provided, and the RT state is managed by managing the on / off states of these flags by the main RAM 103. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag that is in the ON state as the current RT state. When all the RT state flags are off, the main control circuit 90 identifies that the current RT state is the RT0 state.

As shown in FIGS. 13A and 13B, when the bonus combination (internal winning combination of the names "F_BB1" and "F_BB2" described later) is determined as the internal winning combination in the bonus non-winning state (when the transition condition (1) is satisfied). ), The main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. Further, when the bonus combination is won in the inter-flag state (when the transition condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

Further, when the number of medals exceeding the specified number (216) is paid out in the bonus state and the bonus state ends (when the transition condition (3) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the RT1 state (RT1 state). Shift to the bonus non-winning state).

When 20 games have elapsed in the RT1 state (when the transition condition (4) is satisfied), the main control circuit 90 shifts the gaming state from the RT1 state to the RT0 state. Further, in the RT1 state, if the symbol combination related to the abbreviation "bell spilled eyes" (see FIG. 28 described later) is displayed on the valid line before 20 games have elapsed (when the transition condition (5) is satisfied). , The main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

In the RT0 state, when the symbol combination related to the abbreviation "bell spilled eye" is displayed on the valid line (when the transition condition (5) is satisfied), the main control circuit 90 shifts the gaming state from the RT0 state to the RT2 state. Let me. In the RT2 state, when the symbol combination related to the abbreviation "RT3 transition lip" (see FIG. 28 described later) is displayed on the valid line (when the transition condition (6) is satisfied), the main control circuit 90 sets the gaming state. The RT2 state is changed to the RT3 state.

In the RT3 state, when the symbol combination related to the abbreviation "RT4 transition lip" (see FIG. 28 described later) is displayed on the valid line (when the transition condition (7) is satisfied), the main control circuit 90 sets the gaming state. The RT3 state is changed to the RT4 state. Further, in the RT3 state, when the symbol combination (see FIG. 28 described later) related to the abbreviation "bell spilled eye" or "RT2 transition lip" is displayed on the valid line (when the transition condition (8) is satisfied), the main The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Further, in the RT4 state, when the symbol combination related to the abbreviation "bell spilled eye" or "RT2 transition lip" is displayed on the valid line (when the transition condition (8) is satisfied), the main control circuit 90 is in the gaming state. Shifts the gaming state from the RT4 state to the RT2 state.

As for the symbol combination related to the abbreviation "bell spilled eyes", the internal winning combination (small combination) related to the names "F_3 selection bell_1st", "F_3 selection bell_2nd" or "F_3 selection bell_3rd" described later is determined. Moreover, it is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the push order determined for each type of the small winning combination (see FIG. 24 described later). As for the symbol combination related to the abbreviation "RT2 transition lip", the internal winning combination (replay combination) related to the names "F_maintenance lip_1st", "F_maintenance lip_2nd" or "F_maintenance lip_3rd" described later is determined, and This is a combination of symbols displayed when the order of stop operations is incorrect with respect to the push order determined for each type of replay combination.

As for the symbol combination related to the abbreviation "RT3 transition lip", the internal winning combination (replay combination) related to the names "F_RT3 lip_1st", "F_RT3 lip_213", "F_RT3 lip_231" or "F_RT3 lip_3rd" described later is determined. Moreover, it is a combination of symbols displayed when the order of the stop operation is the correct answer for the push order determined for each type of the replay combination. In addition, the symbol combination related to the abbreviation "RT4 transition lip" has an internal winning combination (replay role) related to the names "F_RT4 lip_123", "F_RT4 lip_132", "F_RT4 lip_2nd" or "F_RT4 lip_3rd" described later. It is a combination of symbols that are determined and displayed when the order of stop operations is the correct answer for the push order determined for each type of replay combination.

[Transition flow of game state considering whether or not the notification (ART) function is activated]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not a function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the activated / non-activated state of the ART function is also managed as the gaming state in the bonus non-operating state.

In the pachislot machine 1 of the present embodiment, as shown in FIG. 14A, the main control circuit 90 separates the "general game state" and the "ART game state" based on the presence or absence of notification (ART) in the non-bonus operating state. It is managed as the game state of. That is, in the management of the gaming state in consideration of the presence / absence of notification (ART), as shown in FIG. 14A, the main control circuit 90 is roughly classified into "bonus state", "general gaming state", and "ART gaming state". It manages three types of game states.

The general gaming state is basically a gaming state (non-ART) that does not notify information on a stop operation that is advantageous to the player, and is a gaming state that is disadvantageous to the player. Further, the general gaming state is any of the RT0 to RT4 states, and is an ART non-winning gaming state.

On the other hand, the ART gaming state is a gaming state that notifies information on a stop operation that is advantageous to the player, and is a gaming state that is advantageous to the player. Further, the ART gaming state is basically the RT4 state and the gaming state during the ART winning. In the present embodiment, when the RT state shifts to the RT4 state after winning the ART, the ART game is started.

Further, in the present embodiment, as shown in FIG. 14A, two types of states called "normal gaming state" and "CZ (chance zone)" are provided as general gaming states.

The normal game state is the most disadvantageous game state for the player, but in the game in the normal game state, a lottery for transition to CZ is performed. Then, as shown in FIGS. 14A and 14B, in the game in the normal game state, when the lottery for transition to CZ is won (when the transition condition (A) is satisfied), the main control circuit 90 changes the game state to the normal game state. To CZ.

The CZ is a gaming state (chance zone) in which the expectation for the transition to the ART gaming state is high, and a lottery for the transition to the ART is performed in the game during the CZ. Then, as shown in FIGS. 14A and 14B, in the game during CZ, when the lottery for transition to ART is not won (when the transition condition (B) is satisfied), the main control circuit 90 sets the game state. , CZ shifts to the normal gaming state. On the other hand, in the game during CZ, when the lottery for transition to ART is won (when the transition condition (C) is satisfied), the main control circuit 90 shifts the game state from CZ to the ART game state. At this time, although not shown in FIG. 14A, the main control circuit 90 shifts the gaming state from the CZ to the ART gaming state (normal ART or CT described later) via the ART preparation state described later.

As described above, the ART gaming state is started when the RT state shifts to the RT4 state after winning the ART. As shown in FIG. 13A, since the RT4 state shifts from the RT0 to RT2 states via the RT3 state, the ART gaming state is not started immediately even after winning the ART. Therefore, in the pachi-slot machine 1 of the present embodiment, the gaming state during the period from the winning of the ART to the transition from the RT state to the RT4 state is set as the ART preparation state. Then, in this game in the ART preparation state, information on the stop operation necessary for shifting the RT state to the RT4 state is notified.

Further, in the present embodiment, as shown in FIG. 14A, two types of ART gaming states, called "normal ART" and "CT (additional chance)", in which the playability is different from each other, are provided.

Normally, ART is a stop operation that is advantageous for the player for a predetermined number of games (for example, a stop operation for displaying a symbol combination with a large number of medals to be paid out, or a stop operation necessary for maintaining the RT4 state). Is the game state in which is notified. In addition, in a game during normal ART, a lottery for transition to CT is performed.

CT is a gaming state in which a player is notified of an advantageous stop operation and can add a normal ART duration for a specific period (a period of 8 games per set), and functions as an additional chance zone. It is a game state to play. Also, during CT, the game is usually played without digesting the duration of ART. The playability during CT will be described in detail later with reference to FIGS. 52A to 52C described later.

As shown in FIGS. 14A and 14B, in a game during normal ART, when the lottery for transition to CT is won (when the transition condition (D) is satisfied), the main control circuit 90 changes the game state from normal ART to CT. Shift the game state. Further, in the normal ART, when the duration of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the gaming state from the normal ART to the general gaming state (normal gaming state or CZ). Migrate. In the present embodiment, the duration of normal ART is managed by the number of games, but the present invention is not limited to this, and the method of managing the duration of normal ART is arbitrary. For example, the duration of normal ART may be managed by the number of medals paid out during normal ART or the difference number, or by the number of notifications (number of navigations) that affect the payout of medals during normal ART. You may manage it.

As shown in FIGS. 14A and 14B, in the game during CT, when the duration of CT (8 games per set) ends (when the transition condition (F) is satisfied), the main control circuit 90 sets the game state to CT. To normal ART.

Further, as shown in FIG. 14A, when the bonus combination is won in the general gaming state (normal gaming state or CZ) or ART gaming state (normal ART or CT) (transition condition (2) described in FIGS. 13A and 13B). When is established), the main control circuit 90 shifts the gaming state from the general gaming state or the ART gaming state to the bonus state.

In the game in the bonus state, as described above, the lottery for transition to ART is performed, and in the game in the bonus state, if the lottery for transition to ART is non-winning (when the transition condition (G) is satisfied). , The main control circuit 90 shifts the gaming state from the bonus state to the general gaming state (normal gaming state or CZ). However, when the ART game state (normal ART or CT) has been changed to the bonus state, the main control circuit 90 sets the game state even if the game in the bonus state does not win the ART transition lottery. Shift from the bonus state to the ART game state (normal ART or CT). On the other hand, in the game in the bonus state, when the lottery for transition to ART is won (when the transition condition (H) is satisfied), the main control circuit 90 changes the game state from the bonus state to the ART game state (normal ART or CT). Migrate. As described above, at the end of the bonus state, the RT state shifts to the RT1 state. Therefore, when shifting the gaming state from the bonus state to the ART gaming state, the main control circuit 90 shifts the gaming state to the ART. It shifts to the ART game state via the preparation state.

<Structure of data table stored in main ROM>
Next, the configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. 15 to 27. The various data tables used in various lottery related to the game performance (CZ, normal ART, CT game performance) during the general game state and the ART game state will be described later together with the explanation of each game property. ..

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is data that specifies the position of each symbol in each rotation direction of the left reel 3L, the middle reel 3C, and the right reel 3R, and the type of the symbol arranged at each position (hereinafter, symbol code (in FIG. 15). (Refer to the symbol code table of)) and stipulate the correspondence with.

In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle region of each reel in the frame of the reel display window 4 is defined as "0". Then, in each reel, in the order of proceeding in the reel rotation direction (direction from the symbol position "19" in FIG. 15 toward the symbol position "0") with reference to the symbol position "0", " "0" to "19" are assigned to each symbol as the symbol position.

That is, by referring to the value of the symbol counter ("0" to "19") and the symbol arrangement table, it is displayed in the upper region, the middle region, and the lower region of each reel in the frame of the reel display window 4. It is possible to specify the type of symbol. In this embodiment, as the symbols, "white 7", "blue 7", "chili top 1", "chili top 2", "chili bottom", "replay", "hat", "cactus 1", Ten kinds of symbols of "cactus 2" and "cactus 3" are used.

Further, in the present embodiment, as shown in the symbol code table, "00000001" is assigned as data to the symbol "white 7" (symbol code 1), and the symbol "blue 7" (symbol code 2) is assigned. "00000010" is assigned as the data. "00000011" is assigned as data to the symbol "Chile top 1" (symbol code 3), and "00000100" is assigned as data to the symbol "Chile top 2" (symbol code 4).

"00000011" is assigned as data to the symbol "Chile bottom" (symbol code 5), and "00000011" is assigned as data to the symbol "replay" (symbol code 6). The symbol "hat" (symbol code 7) is assigned "000000111" as data, and the symbol "cactus 1" (symbol code 8) is assigned "00001000" as data. Further, the symbol "cactus 2" (symbol code 9) is assigned "000001001" as data, and the symbol "cactus 3" (symbol code 10) is assigned "000001010" as data.

[Internal lottery table]
Next, the internal lottery table referred to when determining the internal winning combination will be described with reference to FIGS. 16 and 17. Note that FIG. 16 is an internal lottery table referred to in each of the RT0 state to the RT4 state. Further, FIG. 17A is an internal lottery table referred to in the RT5 state, and FIG. 17B is an internal lottery table referenced in the bonus state.

The internal lottery table is provided for each game state, and defines the correspondence between various internal winning combinations and the lottery value when each internal winning combination is determined. The lottery value is defined for each setting (settings 1 to 6) for adjusting the expected value of the internal winning such as a preset bonus combination or small combination. This setting is changed using, for example, a reset switch 76 and a setting key type switch 54 (see FIG. 7).

In the internal lottery process of the present embodiment, first, the random number register 0 of the random number circuit 110 sets a random number value extracted from a predetermined numerical range (for example, 0 to 65535) corresponding to each internal winning combination. Add in sequence at the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result overflows). Then, when the lottery result exceeds 65535 in the predetermined internal winning combination, it is determined that the internal winning combination has won. In the internal lottery process of the present embodiment, an example in which the lottery value is added to the extracted random number value to perform the lottery has been described, but the present invention is not limited to this, and the lottery value is subtracted from the random number value. It may be determined whether or not the subtraction result (lottery result) is less than "0" (whether or not the lottery result is underflowed), and the winning / non-winning of the internal lottery may be determined.

Therefore, in the internal lottery process of the present embodiment, the larger the numerical value defined as the lottery value, the higher the probability that the internal lottery combination will be determined. The winning probability of each internal winning combination can be expressed by "the lottery value specified in each winning number / the number of all random number values that may be extracted (random number denominator: 65536)".

In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, the type and winning probability of the replay combination determined as the internal winning combination according to the type of the RT state. Changes. For example, the replay combination related to the names "F_chili lip (No. 25)" to "F_reach eye lip D (No. 31)" is not determined as an internal winning combination in the RT0 state to RT3 state, and is in the RT4 state. Only determined as an internal winning role. In the pachislot machine 1 of the present embodiment, the replay combination related to the names "F_chili lip (No. 25)" to "F_reach eye lip D (No. 31)" was determined as the internal winning combination during the RT4 state. In this case, specific control (flag conversion described later) is performed. This flag conversion will be described in detail later.

Further, as shown in FIG. 16, in the RT0 state to the RT3 state, the respective internal winning combinations of the names "F_reach eye lip A" to "F_reach eye lip D" are related to the names "F_BB1" or "F_BB2". Although it may be decided in duplicate with the bonus combination (see Nos. 3 to 6 and 15 to 18), each internal winning combination (replay) of the names "F_reach eye lip A" to "F_reach eye lip D" The role) is not determined as an internal winning role alone. Therefore, in the present embodiment, when the replay combination related to the names "F_reach eye lip A" to "F_reach eye lip D" is determined as the internal winning combination during the RT0 state to the RT3 state (name from the player's point of view). When the symbol combination corresponding to the replay combination related to "F_reach eye lip A" to "F_reach eye lip D" is displayed), the bonus combination (name "F_BB1" or "F_BB2") is determined as the internal winning combination at the same time. It will be done.

Further, the RT5 state, which is the inter-flag state, is a gaming state in which the bonus combination is carried over as the internal winning combination as described above. Therefore, as shown in FIG. 17A, in the internal lottery table referred to in the RT5 state, the carry-over bonus combination is always determined as the internal winning combination. Further, as shown in FIG. 17B, in the internal lottery table referred to in the bonus state, the internal winning combination according to any of the names "F_RB combination 1" to "F_RB combination 4" is always won ( "Out of place" won't win).

[Correspondence table between internal winning combination and symbol combination (winning combination) (symbol combination determination table)]
Next, with reference to FIGS. 18 to 23, a correspondence table (symbol combination determination table) between the internal winning combination and the symbol combination will be described. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line (center line) associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the valid line (type of display combination that can win a prize) is uniquely determined.

The various data described in the symbol combination column in each symbol combination determination table is for identifying the symbol combination that is permitted to be displayed along the effective line set over the left reel 3L, the middle reel 3C, and the right reel 3R. It is data. The relationship between each name described in the symbol combination (display combination) column and the specific symbol combination is shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

Further, the "○" mark described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the effective line in the determined internal winning combination, that is, a display combination that can win a prize. For example, when the internal winning combination "F_chili lip" is determined, as shown in FIGS. 18 and 19, the combination names "C_maintenance lip A_01" to "C_maintenance lip G_01" and "C_chili lip A_01" to "C_chili lip" are determined. The symbol combination related to "D_01" can be stopped and displayed. It should be noted that the symbol combination determination table does not specify the case where the "internal winning combination" is "off", but this is all the symbols defined by the symbol combination tables shown in FIGS. 18 to 23. Indicates that the display of combinations is not allowed.

In the pachi-slot machine 1 of the present embodiment, the main control circuit 90 (main CPU 101) has different stop controls depending on the internal winning combination and the gaming state, and when a predetermined combination is determined as the internal winning combination, FIGS. The rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the corresponding symbol combinations shown in FIG. 23 can be displayed. In the correspondence table shown in FIGS. 18 to 23, all the symbol combinations that can be displayed for the determined internal winning combination are listed by "○", but the symbols marked with "○" are listed. Even if it is a combination, it may not be displayed.

In the present embodiment, there is a function of making the stop control (for example, the symbol to be preferentially drawn in) different according to the combination of symbols that can be stopped and displayed and the current game state, and because of the symbol to be preferentially drawn in, "○" Even the marked combination of symbols may not be displayed. The correspondence between the types of internal winning combinations and the actually displayed symbol combinations will be described with reference to FIGS. 24 and 25 described later.

[Correspondence between the winning combination in the non-flag state and the symbol combination displayed as stopped]
Here, with reference to FIG. 24, the correspondence between the internal winning combination and the symbol combination displayed as stopped in the game state (non-flag state) excluding the flag state will be described. Note that FIG. 24 shows the correspondence between various internal winning combinations that can be determined in the non-flag state and a symbol combination (abbreviation) that is stopped and displayed when each internal winning combination is determined (some combinations are omitted). It is a figure. The name of the symbol combination described in FIG. 24 is the “abbreviation” described in the content column shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

In the pachi-slot machine 1 of the present embodiment, a so-called “pushing order combination” is provided in which the symbol combinations displayed differ according to the order (pushing order) of the player's stop operations. The symbol combination associated with the "correct answer in push order" shown in FIG. 24 is a symbol combination that is advantageous for the player among the symbol combinations displayed according to the push order, and is referred to as "incorrect answer in push order". The associated symbol combination is a symbol combination that is disadvantageous to the player among the symbol combinations displayed according to the pressing order. When notifying a stop operation that is advantageous to the player, the correct push order is notified, and if the stop operation is performed according to the notification, the symbol combination associated with the "push order correct answer" is displayed. Further, even in the ART gaming state, an incorrect push order may be notified, but the details thereof will be described later.

In addition, in this embodiment, for a part of the push order combination, the push order that is the correct answer is shown at the end of the name. Specifically, the last "1st" in the name of the internal winning combination means that the correct push order is that the first stop operation (the first stop operation performed) is for the left reel 3L. The end "2nd" of the name of the internal winning combination means that the push order that is the correct answer is that the first stop operation is for the middle reel 3C, and the end "3rd" of the name of the internal winning combination is the correct answer. The push order means that the first stop operation is for the right reel 3R. In addition, the end "123" of the name of the internal winning combination means that the correct push order is "left, middle, right", and the end "132" of the name of the internal winning combination is the correct answer. Means that the push order is "left, right, middle", and the last "213" in the name of the internal winning combination means that the correct push order is "middle, left, right". The ending "231" of the name of the internal winning combination means that the correct push order is "left, right, middle".

Further, in the following, the stop operation order when the first stop operation is performed on the left reel 3L, specifically, the push order of "left, middle, right" and "left, right, middle" is changed to ". Also called "forward push". Further, in the following, the stop operation order when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, "middle, left, right", "middle, right, left", The pressing order of "right, middle, left" and "right, left, middle" is also referred to as "irregular pressing".

In the present embodiment, as shown in FIG. 24, the internal winning combination “F_Chillilip” is a pressing order combination in which the symbol combinations displayed according to the pressing order are different, and when the pressing order is the correct answer, the abbreviation “F_Chillilip” is used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to "Chillilip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed. When the internal winning combination "F_chililip" is determined, as shown in FIGS. 18 to 23, the combination names "C_chililip A_01", "C_chililip B_01" or "C_chililip C_01" (abbreviation "single chili lip") Alternatively, "double chili lip": corresponding to the abbreviation "chili lip (no triple)" in FIG. 28 described later) can be displayed, but the combination names "C_chili lip D_01" to "C_1 certain chili lip D_01" (abbreviation). "Triple chili lip": Corresponding to the abbreviation "chili lip (triple)" in FIG. 28, which will be described later), the symbol combination cannot be displayed. That is, the internal winning combination "F_chili lip" is a combination that cannot display the symbol combination related to the abbreviation "triple chili lip".

In addition, both the internal winning combinations "F_certain chili lip" and "F_1 certain chili lip" are push order combinations with different symbol combinations displayed according to the push order, and if the push order is correct, the abbreviation "chili lip" is used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIG. 28 described later) according to the above is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed. When the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, the symbol combination related to the abbreviation "triple chili lip" can be displayed as shown in FIGS. 18 to 23. That is, the internal winning combinations "F_certain chili lip" and "F_1 certain chili lip" are roles that can display the symbol combination related to the abbreviation "triple chili lip".

In addition, the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIGS. 28 and 29 described later) related to the "reach eye lip" is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In this embodiment, the order of pressing the correct answers at the time of winning the internal winning roles "F_chili lip", "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" Is to perform the first stop operation on the left reel 3L. Therefore, for example, in a game in which the internal winning combination "F_reach eye lip A" is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation is changed to "reach eye lip". The symbol combination is stopped and displayed. The present invention is not limited to this, and the internal winning combinations "F_chili lip", "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" are used at the time of winning. The order of pressing the correct answers can be set arbitrarily.

In addition, both the internal winning combinations "F_maintenance lip A" and "F_maintenance lip B" are not push order combinations, and are shown in the symbol combinations related to the abbreviation "replay" regardless of the push order (see FIG. 28 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

In addition, the internal winning combinations "F_maintenance lip_1st" to "F_maintenance lip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. Among the symbol combinations related to "replay" (see FIG. 28 described later), any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIG. 28 described later) related to the abbreviation "RT2 transition lip" is an effective line. It is displayed along with.

In addition, the internal winning combinations "F_RT3 rip_1st" to "F_RT3 rip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT3" is used. The symbol combination related to "Transition Lip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In addition, the internal winning combinations "F_RT4 rip_123" to "F_RT4 rip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT4" is used. The symbol combination related to "Transition Lip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In addition, the internal winning combinations "F_3 choice bell_1st" to "F_3 choice bell_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. The symbol combination related to the "bell" (see FIG. 19 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, the symbol combination related to the abbreviation "bell spilled eyes" (see FIG. 28 described later) or the symbol combination related to the abbreviation "first piece" (see FIG. 30 described later) is used. Is displayed.

Further, the internal winning combination "F_common bell" is not a pressing order combination, and can be displayed as shown in FIGS. 18 to 23 of the symbol combinations (see FIG. 29 described later) related to the abbreviation "bell" regardless of the pressing order. Any of the various symbol combinations is displayed along the effective line. Further, neither of the internal winning combinations "F_sabo 1" and "F_sabo 2" is a pushing order, and FIG. 18 of the symbol combination (see FIG. 30 described later) relating to the abbreviation "cactus" regardless of the pushing order. ~ Any of the displayable symbol combinations shown in FIG. 23 is displayed along the effective line.

Further, the internal winning combination "weak cherry" is not a pressing order, and can be displayed as shown in FIGS. 18 to 23 of the symbol combinations (see FIG. 30 described later) related to the abbreviation "weak cherry" regardless of the pressing order. Any of the various symbol combinations is displayed along the effective line. In addition, the internal winning combinations "F_strong chili 1" and "F_strong chili 2" are not push order combinations, and are among the symbol combinations related to the abbreviation "strong cherry" regardless of the push order (see FIG. 30 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

[Correspondence between the winning combination in the inter-flag state and the symbol combination displayed as stopped]
Next, with reference to FIG. 25, the correspondence between the internal winning combination and the symbol combination displayed as stopped in the inter-flag state will be described. Note that FIG. 25 is a diagram showing the correspondence between the internal winning combination and the symbol combination displayed as stopped in the inter-flag state (some combinations are omitted), and in particular, the bonus combination (some combinations are omitted) during the inter-flag state. It is a figure which shows whether or not it is possible to display the symbol combination (combination name "C_BB1" or "C_BB2") which concerns on BB combination).

In the correspondence table of FIG. 25, the "○" mark in the "whether or not BB is established" column indicates that the symbol combination related to the BB combination can be displayed, and the "x" mark indicates the symbol combination related to the BB combination. Indicates that is not displayable. If the symbol combination related to the BB combination cannot be displayed, the symbol combination related to the combination determined to overlap with the bonus combination as the internal winning combination is displayed. For example, when the internal winning combination "F_BB1 + F_Chillilip" is won (when the internal winning combination "F_BB1" and the internal winning combination "F_Chillilip" are duplicated), as shown in FIG. 25, the internal winning combination "F_BB1" It is possible to stop and display the symbol combination related to, and the symbol combination related to the internal winning combination "F_Chillilip" is stopped and displayed.

Further, in the inter-flag state, when the symbol combination related to the BB combination cannot be displayed and the symbol combination related to the combination determined to overlap with the bonus combination is displayed, the push described with reference to FIG. 24 Only the symbol combination at the time of correct answer may be displayed, or only the symbol combination at the time of incorrect answer may be displayed.

For example, when the internal winning combination "F_BB1 + F_3 selection bell_1st" is won, as shown in FIG. 25, the symbol combination related to the internal winning combination "F_BB1" cannot be stopped and displayed, so that the internal winning combination "F_3 selection bell_1st" cannot be stopped and displayed. The symbol combination related to "" is stopped and displayed, but at this time, only the symbol combination related to the abbreviation "bell" displayed when the push order is correct is displayed, and the abbreviation "bell spilled eye" displayed when the push order is incorrect is displayed. Alternatively, the symbol combination related to the "first piece" may not be displayed (see FIG. 24). Further, for example, when the internal winning combination "F_BB1 + F_RT3 rip_1st" is won, only the symbol combination related to the abbreviation "replay" displayed when the push order is incorrect can be displayed, and the abbreviation "RT3" displayed when the push order is correct is displayed. The symbol combination related to the "transition lip" may be disabled (see FIG. 24).

In the inter-flag state, as shown in FIG. 25, one of the bonus combination (BB combination) and the internal winning combination "off", "F_special 1", "F_special 2" and "F_special 3" If the determinations are duplicated, the symbol combination related to the BB combination can be stopped and displayed.

[Reel stop initialization table]
Next, the reel stop initial setting table will be described with reference to FIG. The reel stop initial setting table defines the correspondence between the internal winning combination and various data used in the reel stop control process described later.

The reel stop initial setting table shown in FIG. 26 defines the correspondence between the internal winning combination (small winning combination winning number) and the attraction priority table selection table number, attraction priority table number, and stop table number. In addition, in FIG. 26, the reference game state and the name of the internal winning combination are also shown.

The pull-in priority table selection table number and the pull-in priority table number are data used in the selection process of the pull-in priority table. For example, if the pull-in priority table number corresponding to the stop table number is specified in the reel stop initial setting table, it corresponds to the pull-in priority table number specified in the pull-in priority table (see FIG. 27 described later). Data related to the priority of the display combination can be acquired. On the other hand, if the attraction priority table number corresponding to the stop table number is not specified in the reel stop initialization table, the attraction priority table selection table (not shown) is referred to and the attraction priority table selection table number is set. The corresponding pull-in priority table number is determined.

Here, the reel stop control (method for determining the stop symbol position) in the pachi-slot machine 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel stops within 190 msec. Specifically, any one of the number of sliding pieces "0" to "4" is added to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected, and the value corresponds to the obtained value. The symbol position is determined as the symbol position at which the rotation of the reel stops (hereinafter, referred to as "scheduled stop position"). The symbol position corresponding to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected is the symbol position where the rotation of the reel is started (hereinafter, referred to as "stop start position").

That is, the number of sliding pieces is the amount of rotation of the reel from the time when the stop operation is detected by the stop switch until the rotation of the corresponding reel is stopped. In other words, it is the number of symbols that pass through the middle region of the corresponding reel of the reel display window 4 in the period from the detection of the stop operation by the stop switch to the stop of the rotation of the corresponding reel. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

With reference to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is tentative, and the acquired number of sliding pieces does not immediately determine the scheduled stop position of the reel. In the present embodiment, if there is a more appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter, referred to as “sliding piece number determination data”), the pull-in priority table (described later) will be described later. Refer to FIG. 27) to change the number of sliding pieces. Then, the sliding piece number determination data is referred to for determining the search order when comparing the priorities of each symbol from the stop start position to the symbol position four ahead, which is the maximum number of sliding pieces.

[Pull-in priority table]
Next, the pull-in priority table will be described with reference to FIG. 27. The attraction priority table is the attraction data (winning operation flag data) for each type of the winning operation flag storage area (see FIGS. 28 to 30 described later) in each of the drawing priority table numbers “00” to “05”. ) And its predetermined priority.

The pull-in priority table is used to search whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces obtained based on the stop table (not shown). The priority order is data that defines the order in which the symbols are preferentially stopped and displayed (pulled in) among the types of symbol combinations (winning operation flags) related to winning. Further, in FIG. 27, for convenience of explanation, the combination name of the winning operation flag is described in the column of the drawing data (winning operation flag data), but in the actual drawing priority table, each drawing data is the winning prize described later. As shown in the operation flag storage area (see FIGS. 28 to 30 described later), it is represented by 1-byte data, and a unique symbol combination (winning operation flag) is assigned to each bit in the 1-byte data. ..

In the reel stop control of the present embodiment, first, the number of sliding pieces is acquired based on the stop table (not shown). However, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces based on the priority, the number of sliding pieces is changed to the appropriate number. That is, in the present embodiment, the more appropriate number of sliding pieces is determined based on the priority of the symbol combination that allows the stop display by the internal winning combination, regardless of the number of sliding pieces acquired by the stop table.

In the present embodiment, the stop display (pull-in) of the symbol combination having the higher priority is performed with priority over the stop display of the symbol combination having the lower priority.

Further, in the present embodiment, as shown in FIG. 27, not only the priority of the symbol combination (winning operation flag) is different according to the attraction priority table number, but also the number of priority divisions is different. Specifically, when the attraction priority table number is "00", the number of priority divisions is 5, and when the attraction priority table number is "01" or "04", the priority is given. Let the number of divisions be 4. If the pull-in priority table number is "02" or "03", the number of priority divisions is 2, and if the pull-in priority table number is "05", the number of priority divisions is set. Let be 3.

Here, the priority when the pull-in priority table number is "00" will be described, and the description of the priority in the other pull-in priority table numbers will be omitted. When the pull-in priority table number is "00", the priority "1" (highest priority) includes the combination names "C_9 sheets A_01", "C_1 certain chili lip C_01", "C_1 certain chili lip D_01" and The pull-in data corresponding to "C_RT3 lip_01" is specified.

When the pull-in priority table number is "00", the priority "2" includes the combination names "C_strong 2 sheets C_01" to "C_strong 2 sheets C_09", "C_weak 2 sheets B_01" to "C_weak". Corresponds to "2 sheets B_03", "C_3 sheets E_01", "C_3 sheets E_02", "C_9 sheets F_01" to "C_9 sheets F_03", "C_1 certain chili lip B_01", "C_chili lip D_01" and "C_chili lip C_01". The pull-in data is specified.

When the pull-in priority table number is "00", the priority "3" includes the combination names "C_1 sure chili lip A_01", "C_chili lip A_01", "C_chili lip B_01" and "C_maintenance lip E_01" to "C_maintenance lip E_01". The pull-in data corresponding to "C_maintenance lip E_04" is specified.

When the pull-in priority table number is "00", the priority "4" includes the combination names "C_SP1_01", "C_SP2_01", "C_reach eye lip P_01", "C_reach eye lip P_02", and "C_reach". Eye Lip O_01 "," C_Reach Eye Lip O_02 "," C_Reach Eye Lip N_01 "," C_Reach Eye Lip N_02 "," C_Reach Eye Lip M_01 "," C_Reach Eye Lip M_02 "," C_Reach Eye Lip N_02 " L_01 "to" C_reach eye lip L_03 "," C_reach eye lip K_01 "to" C_reach eye lip K_03 "," C_reach eye lip J_01 "," C_reach eye lip I_01 "to" C_reach eye lip I_09 " , "C_reach eye lip H_01" to "C_reach eye lip H_03", "C_reach eye lip G_01", "C_reach eye lip F_01", "C_reach eye lip F_02", "C_reach eye lip E_01", " C_reach eye lip D_01 "," C_reach eye lip D_02 "," C_reach eye lip C_01 "to" C_reach eye lip C_03 "," C_reach eye lip B_01 "," C_reach eye lip B_02 "," C_reach Eye Lip A_01 "," C_Maintenance Lip F_01 "," C_Maintenance Lip F_02 "," C_Maintenance Lip D_01 "to" C_Maintenance Lip D_04 "," C_Maintenance Lip C_01 "to" C_Maintenance Lip C_03 "," C_Maintenance Lip C_03 " The pull-in data corresponding to "Rip B_01", "C_Maintenance Lip B_02" and "C_Maintenance Lip A_01" is specified.

Further, the attraction data corresponding to the combination names "C_BB1" and "C_BB2" are defined in the priority "5" (lowest priority) when the attraction priority table number is "00".

<Structure of storage area provided in main RAM>
Next, the configurations of various storage areas provided in the main RAM 103 will be described with reference to FIGS. 28 to 35.

[Hit request flag storage area and winning operation flag storage area]
First, the configuration of the winning request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described with reference to FIGS. 28 to 30. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (winning flag data storage area) have the same configuration.

In the present embodiment, the hit request flag storage area is composed of the hit request storage areas 0 to 11 each represented by 1 byte of data, and the winning operation flag storage area is each represented by 1 byte of data. It is composed of storage areas 0 to 11. The data stored in each storage area of the hit request flag storage area and the winning operation flag storage area is only the 1-byte data in the "data" column in FIGS. 28 to 30, but in FIGS. 28 to 30, , For convenience of explanation, the symbol combination of each reel associated with the bit of each storage area (in the figure, the symbol of the left reel 3L, the symbol of the middle reel 3C, and the symbol of the right reel 3R are described in this order). The name (combination name) and abbreviation, as well as the number of medals to be paid out are also described.

When "1" is stored in a predetermined bit in each of the hit request flag storage areas 0 to 11, it indicates that the internal winning combination corresponding to the predetermined bit has won the internal winning. Further, when "1" is stored in a predetermined bit in each of the winning operation storage areas 0 to 11, it indicates that the display combination (winning operation flag) corresponding to the predetermined bit has won a prize. That is, when "1" is stored in the predetermined bit, it indicates that various symbol combinations of the internal winning combinations corresponding to the predetermined bit are displayed on the effective line.

Further, in the hit request flag storage area and the winning operation flag storage area, as shown in FIGS. 28 to 30, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. Some are. That is, for such a flag, it means that there are a plurality of symbol combinations (combinations that can win a prize) that can be stopped and displayed.

For example, the winning request storage area 5 and the winning operation storage area 5 have a symbol combination "cactus 2"-"white 7"-"hat" (combination name "C_maintenance lip C_01") and a symbol combination "cactus 2". -"Chile Top 1"-"Hat" (combination name "C_maintenance lip C_02") and symbol combination "cactus 2"-"cactus 2-"-"hat" (combination name "C_maintenance lip C_03") Three symbol combinations are assigned. Therefore, when "1" is stored in bit 5 of the hit request storage area 5, it indicates that the combination of these three symbols can be stopped and displayed on the effective line. Further, when "1" is stored in bit 5 of the winning operation storage area 5, it indicates that any one of these three symbol combinations is displayed on the valid line.

[Carryover storage area]
Next, the configuration of the carry-over combination storage area will be described with reference to FIG. 31. In the present embodiment, the carry-over combination storage area is composed of a 1-byte data storage area.

When the internal winning combination "F_BB1" or "F_BB2" is determined as a result of the internal lottery, the internal winning combination (BB combination) is stored in the carry-over combination storage area as a carry-over combination. The carry-over combination stored in the carry-over combination storage area is retained without being cleared until the corresponding symbol combination is displayed on the valid line. Further, while the carry-over combination is stored in the carry-over combination storage area, the carry-over combination is stored in the winning request storage area in addition to the internal winning combination determined by the internal lottery.

[Game status flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. 32. The game state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 32, a unique bonus type or RT type is assigned to each bit in the game state flag storage area.

When "1" is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when "1" is stored in bit 0 of the game state flag storage area, the big bonus "BB" is being operated, indicating that the game state is the BB game state. Further, for example, when "1" is stored in bit 3 of the game state flag storage area, it indicates that the game state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. 33. The operation stop button storage area is composed of a 1-byte data storage area, and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, "1" is stored in bit 0 of the operation stop button storage area. Further, for example, when the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, "1" is stored in bit 4. The main CPU 101 distinguishes between the stop button pressed this time and the stop button that has not been pressed yet, based on the data stored in the operation stop button storage area.

[Press order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. 34. The press order storage area is composed of a 1-byte data storage area, and stores a press order flag consisting of 1 byte.

In the pressing order flag, each bit is assigned the type of pressing order of the stop button. For example, when the pressing order of the stop buttons is "left, middle, right", "1" is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. 35. In the present embodiment, each of the symbol code storage areas is composed of symbol code storage areas 0 to 11 represented by 1 byte of data. The symbol code storage area has the same configuration as the hit request flag storage area and the winning operation flag storage area (see FIGS. 28 to 30).

In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the effective line. After all the reels are stopped, the symbol code corresponding to the display combination (winning operation flag) is stored in the symbol code storage areas 0 to 11.

[Relationship between internal winning combination and various sub-flags]
In the general game state and the ART game state, various data tables are referred to in various lottery by the main control circuit 90, but as a parameter used at this time, in this embodiment, not only the internal winning combination but also the internal winning combination is supported. Various parameters having different names (hereinafter, referred to as "sub-flag (first sub-flag)", "sub-flag EX (second sub-flag)", and "sub-flag D") are also used. Therefore, in the present embodiment, the main control circuit 90 performs a process of converting the internal winning combination into various sub-flags (see the sub-flag conversion process, the flag conversion process, and the sub-flag compression process in FIG. 85 described later). In the present embodiment, a sub flag is set in the start command as information (communication parameter) regarding the internal winning combination, and is transmitted from the main control circuit 90 to the sub control circuit 200.

Here, with reference to FIGS. 36 and 37, the correspondence between the internal winning combination and various sub-flags will be described. FIG. 36 is a diagram showing the correspondence relationship between the internal winning combination (small winning combination winning number) and various sub-flags, and FIG. 37 is a diagram showing the correspondence relationship between the internal winning combination (special prize winning number) and the sub-flags.

In the flag conversion process of the present embodiment, first, a plurality of internal winning combinations belonging to the same type are combined into one sub-flag. In the present embodiment, as shown in FIG. 36, by this flag conversion process, 32 types of internal winning combinations (small winning combination winning numbers) related to the small winning combination and the replay winning combination are converted into 18 types of sub-flags (“01” to “18”. : Flag data) is converted. For example, the internal winning combination "F_maintenance rip_1st (10: small winning combination number)" to "F_maintenance rip_3rd (12)" are grouped into the sub-flag "pushing order rip 1 (09: flag data)". The sub-flag "Loss (00)" is assigned to the internal winning combination "Loss".

Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, 19 types of sub-flags ("00" to "18") including the sub-flag "loss (00)" are replaced with 9 types of sub-flag EX ("00"). "-" 08 ": flag data). Therefore, in this conversion process, the sub-flag data can be further compressed. At this time, in the present embodiment, the sub flag is converted into the sub flag EX by lottery (flag conversion lottery). Specifically, it is converted as follows.

The sub-flag "Loss (00)" is converted to the sub-flag EX "Loss (00)" regardless of the result of the flag conversion lottery, and the sub-flag "Double chili lip (01)" is converted to the sub-flag "Double chili lip (01)" regardless of the result of the flag conversion lottery. It is converted to the sub flag EX "replay (01)".

When the sub-flag "triple chili lip A (02)" and the sub-flag "triple chili lip B (03)" are won in the flag conversion lottery (in the case of "with conversion" described later), the sub-flag EX "fixed combination (06)" Or, it is converted to "triple chili lip (07)", and if it is not won in the flag conversion lottery (in the case of "no conversion" described later), it is converted to the sub flag EX "replay (01)".

The sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are converted to the sub-flag EX "fixed combination (06)" or "reach-eye lip (08)" when the flag conversion lottery is won. If the flag conversion lottery is not won, it is converted to the sub-flag EX "replay (01)".

The sub-flags "replay (08)" and "push order rip 1 (09)" to "push order rip 3 (11)" are converted to the sub-flag EX "replay (01)" regardless of the result of the flag conversion lottery. The sub-flags "push order bell (12)" and "common bell (13)" are converted to the sub-flag EX "bell (02)" regardless of the result of the flag conversion lottery.

The sub-flags "cactus (14)", "weak cherry (15)" and "strong cherry (16)" are the sub-flags EX "cactus (03)" and "weak cherry (04)" regardless of the result of the flag conversion lottery, respectively. "And" strong cherry (05) ". Further, the sub-flags "reach eye 1 (17)" and "reach eye 2 (18)" are converted into the sub-flag EX "miss (00)" regardless of the result of the flag conversion lottery.

As described above, in the present embodiment, the sub-flags "triple chili lip A (02)", "triple chili lip B (03)" and "reach eye lip 1 (04)" to "reach eye lip 4 (07)" are substantially used. ) ”Is the target of the flag conversion lottery. The lottery table used for the above-mentioned flag conversion lottery will be described in detail later.

Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, nine types of sub-flags EX (“00” to “08”) are converted into seven types of sub-flags D (“00” to “06”). NS. Therefore, in this conversion process, the sub-flag data can be further compressed. In this conversion process, the lottery is not performed, and the sub-flag EX and the sub-flag D are associated with each other for conversion as follows.

The sub-flag EX "loss (00)", "replay (01)" and "bell (02)" are converted into the sub-flag D "loss (00)". The sub-flag EX "cactus (03)" is converted to the sub-flag D "cactus (01)", the sub-flag EX "weak cherry (04)" is converted to the sub-flag D "weak cherry (02)", and the sub-flag EX "strong". "Cherry (05)" is converted to subflag D "strong cherry (03)".

Further, the sub flag EX "fixed combination (06)" is converted to the sub flag D "fixed combination (04)", and the sub flag EX "triple chili lip (07)" is converted to the sub flag D "triple chili lip (05)". Then, the sub flag EX "reach eye lip (08)" is converted into the sub flag D "reach eye lip (06)".

Further, in the flag conversion process of the present embodiment, as shown in FIG. 37, both the internal winning combination "F_BB1 (01: special prize winning number)" and "F_BB2 (02)" are converted into the sub-flag "BB". ..

[Gameability at the time of sub-flag EX conversion]
Here, a process of converting the above-mentioned internal winning combination into a sub-flag and a sub-flag EX, and an example of playability at the time of sub-flag EX conversion will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing a flag conversion process when the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined, and FIG. 38B is a diagram showing the internal winning combination “F_reach eye lip A” to “F_”. It is a figure which shows the flag conversion process when any of "reach eyes lip D" is determined.

In the pachislot machine 1 of the present embodiment, any one of the internal winning combinations "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" is independent during the RT4 game state. If it is determined as an internal winning combination, a flag conversion lottery will be performed. Then, in the present embodiment, when the flag conversion lottery is won, a special privilege (for example, addition of the number of ART games or CT winning) is given.

For example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, as shown in FIG. 38A, the internal winning combination "F_certain chili lip" and "F_1 certain chili lip" are each sub-flag "3 consecutive". It is converted into "chili lip A (02)" and "triple chili lip B (03)".

Next, the sub-flags "triple chili lip A (02)" and "triple chili lip B (03)" become the sub-flag EX "triple chili lip (07)" or "fixed combination (06)" when the flag conversion lottery is won. Will be converted. On the other hand, if the flag conversion lottery is not won, both the sub-flags "triple chili lip A (02)" and "triple chili lip B (03)" are converted to the sub-flag EX "replay (01)". ..

As described in FIG. 24, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, the symbol combination related to the abbreviation "triple chili lip" is displayed when the push order is correct, and the push order is irregular. When the answer is correct, the symbol combination related to the abbreviation "Replay" is displayed. Therefore, in the present embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined and the flag conversion lottery is won, the internal winning combination "F_certain chili lip" and "F_1 certain chili lip" Are all treated as the combination of the sub-flag EX "triple chili lip (07)" or "fixed combination (06)".

Then, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted into the sub-flag EX "triple chili lip (07)" or "fixed combination (06)" by this flag conversion process, the abbreviation "triple chili lip" is abbreviated. Information for displaying the symbol combination related to the "chili lip" is notified (for example, information to the player to aim at the chili symbol by pushing forward is notified). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted to the sub-flag EX "replay (01)", the abbreviation is changed to "replay". Information for displaying the symbol combination is notified (for example, a pressing order other than forward pressing (irregular pressing) is notified).

Further, for example, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined, as shown in FIG. 38B, the internal winning combinations “F_reach eye lip A” to “F_reach eye lip A” to “ "F_reach eye lip D" is converted into subflags "reach eye lip 1 (04)" to "reach eye lip 4 (07)", respectively.

Next, the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" become the sub-flag EX "reach-eye lip (08)" or "fixed combination (06)" when the flag conversion lottery is won. Will be converted. On the other hand, when the flag conversion lottery is not won, the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are converted into the sub-flag EX "replay (01)".

As described in FIG. 24, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, the symbol combination related to the abbreviation "reach eye lip" is used when the push order is correct. Is displayed, and when the push order is incorrect, the symbol combination related to the abbreviation "replay" is displayed. Therefore, in the present embodiment, when any one of the internal winning combination "F_reach eye lip A" to "F_reach eye lip D" is determined and the flag conversion lottery is won, the internal winning combination "F_reach eye" is determined. All of "Rip A" to "F_Reach-eye lip D" are treated as the roles of the sub-flag EX "Reach-eye lip (08)" or "Definite combination (06)".

Then, when the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are converted into, for example, the sub-flag EX "reach eye lip (08)" or "fixed combination (06)" by this flag conversion process. , Information for displaying the symbol combination related to the abbreviation "reach eye lip" is notified (for example, information to the player to aim at the symbol "white 7" by pushing forward is notified). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are converted to the sub-flag EX "replay (01)", it is abbreviated. Information for displaying the symbol combination related to "replay" is notified (for example, a pressing order other than forward pressing (irregular pressing) is notified).

Further, in the present embodiment, in the flag conversion process shown in FIG. 38A or 38B, when the player wins the flag conversion lottery and performs the stop operation according to the notification, it relates to the abbreviation "triple chili lip" or "reach eye lip". The symbol combination is stopped and displayed on the valid line, and a special privilege is given. In this granting process, a special privilege is given to the player according to the fact that the pachislot 1 wins the flag conversion lottery, but the abbreviation "3" is given to the player. By displaying the symbol combination related to "Ren Chiri Lip", it is possible to feel that a special privilege has been given.

In order to enhance the playability of pachislot, it may be preferable that the appearance frequency of the symbol combination to which the privilege is given is different depending on the state rather than being constant. Since the stop control (displayed symbol combination) differs depending on the type of internal winning combination, as a method of changing the appearance frequency of the symbol combination to which the privilege is given depending on the state, the winning probability of the internal winning combination is changed. A method is also conceivable (in pachislot 1, the winning probability of the internal winning combination can be different depending on the presence or absence of the bonus operation and the RT state. Therefore, for example, as the RT state corresponding to the ART game state, only the RT4 state is considered. Instead, a method of providing other RT states such as RT6 state and RT7 state is also conceivable). However, since the opportunity to make the winning probability of the internal winning combination different (the opportunity to shift to the RT state) is limited, this method lacks flexibility from the viewpoint of improving playability (interestingness).

On the other hand, in the pachislot machine 1 of the present embodiment, in addition to the internal lottery for determining the internal winning combination, the flag conversion lottery and the notification based on the lottery result are performed without changing the winning probability of the internal winning combination. , The appearance frequency of the symbol combination to which the privilege is given can be flexibly changed according to the state. That is, in a state where it is easy to win the flag conversion lottery, the appearance frequency of the symbol combination to which the privilege is given can be increased, and conversely, in a state where it is difficult to win the flag conversion lottery, the appearance of the symbol combination to which the privilege is given appears. The frequency can be reduced.

<Gameability during general game state>
Next, the flow of the game during the general game state will be described with reference to FIGS. 39A to 39C. In the pachislot machine 1 of the present embodiment, the gaming state shifts from the normal gaming state to the CZ during the general gaming state, and then the gaming state shifts from the CZ to the ART gaming state, whereby the general gaming state (non-ART gaming state) ) To the ART gaming state (see FIGS. 14A and 14B).

FIG. 39A is a diagram showing a flow of a game when the game state shifts from the normal game state to the CZ in the general game state. As shown in FIG. 39A, the normal gaming state has a low probability state and a high probability state as a lottery state of CZ. The low-probability state and the high-probability state are states in which the expectation of winning the CZ lottery performed during the normal game state is different from each other, the low-probability state is the state in which it is difficult to win the CZ lottery, and the high-probability state is the CZ. It is in a state where it is easy to win a lottery. Then, when the CZ lottery performed in the game during the normal game state is won, the game state shifts from the normal game state to the CZ.

In the pachislot machine 1 of the present embodiment, a plurality of chance zones of "CZ1", "CZ2" and "CZ3" are provided as CZs (chance zones). CZ1 to CZ3 are chance zones in which the expectations for winning the ART lottery performed in the game during CZ are different from each other, CZ3 is a chance zone in which the ART lottery is always won, and CZ1 and CZ2 have a predetermined probability. This is a chance zone to win the ART lottery. In the CZ lottery performed in the game during the normal game state, not only the winning / non-winning of the CZ but also the type of CZ (any of CZ1 to CZ3) to be transferred at the time of winning is determined (see FIG. 41 described later).

FIG. 39B is a diagram showing a flow of the game when the game state shifts from the general game state CZ1 and CZ2 to the ART game state. Both CZ1 and CZ2 are composed of a first half portion and a second half portion. The first half is a period for promoting the rank of the expectation of winning the ART lottery performed in the game during the CZ, and the second half is a predetermined production of the lottery result of the ART lottery based on the rank (in this embodiment, the character). It is a period to be notified by (battle production by).

In CZ1, six modes (modes 1 to 6) are prepared as ranks, and the higher the mode, the higher the expectation of winning the ART lottery. In the first half of CZ1, the game is continuously played for the period of the first predetermined number of games (for example, 12 games at the maximum), and the mode promotion lottery is performed based on the internal winning combination. Then, in the first game of the latter half of CZ1, the ART lottery is performed based on the mode promoted in the first half (the mode at the end of the first half).

In addition, in CZ2, points of 10 levels are prepared as ranks, and the higher the points, the higher the expectation of winning the ART lottery. In the first half of CZ2, games are continuously played for a period of a second predetermined number of games (for example, a maximum of 15 games), and points are promoted by lottery based on the internal winning combination. Then, in the first game of the second half of CZ2, the ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

In the latter half of CZ1, a battle effect in which the ally character and the enemy character A play against each other is performed, and in the latter half of CZ2, a battle effect in which the ally character and the enemy character B play against each other is performed. This battle effect is performed over a period of a third predetermined number of games (for example, a maximum of 4 games). In addition, the victory or defeat of the battle production is managed (determined) based on the result of the ART lottery, and if the ART lottery is won, the ally character wins in the battle production, and if it is not the ART lottery, the battle The enemy character wins in the production.

Further, in each latter half of CZ1 and CZ2 (during the battle production), an ART lottery is performed every game based on the internal winning combination. Then, when the ART lottery is won, the result of the battle effect is rewritten. For example, if a so-called "rare" role is determined as an internal winning role during a battle production, an ART lottery is performed, and the result of the battle production is rewritten based on the result.

In CZ1 and CZ2, if the ART is not won, the player is defeated in the battle effect in the latter half, and basically, the game state shifts to the normal game state after that. On the other hand, in CZ1 and CZ2, when the ART is won, the battle effect in the latter half is won, and then the game state shifts from the CZ to the normal ART via the ART preparation state. In addition, in this embodiment, a freeze may occur in the game of the first half of CZ1 and CZ2, and in that case, the game state is changed from CZ via the ART preparation state to CT (additional addition) instead of normal ART. Move to the chance zone).

FIG. 39C is a diagram showing a game flow when the game state shifts from the general game state CZ3 to the ART game state. The CZ3 is continuously played for a period of a fourth predetermined number of games (for example, 17 games at the maximum). Then, in CZ3, ART lottery is performed every game based on the internal winning combination.

The CZ3 ends when the ART lottery is won, and after the next game, the game state shifts from the CZ3 to the CT (additional chance zone) via the ART preparation state. Further, in CZ3, a freeze may occur, and even in that case, the game state shifts from CZ3 to CT (additional chance zone) via the ART preparation state after the next game. On the other hand, in CZ3, when the game period (fourth predetermined number of games) of CZ3 elapses without winning the ART lottery, the game state shifts from CZ3 to normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state is confirmed.

<Various data tables used during the general game state>
Subsequently, with reference to FIGS. 40 to 45, various data tables used in the lottery process relating to the playability performed during the general game state will be described. The various data tables described below are stored in the main ROM 102.

Further, in the various data tables shown below, the lottery value information is conceptually shown. "0" in the data table means that the lottery value corresponding to the winning probability "0%" is specified, and "extremely low" means the lottery corresponding to the winning probability "0% to less than 1%". It means that the value is specified, and "extremely low" means that the lottery value corresponding to the winning probability "1% to less than 10%" is specified. Further, "low" in the data table means that a lottery value corresponding to a winning probability of "10% to less than 30%" is specified, and "medium" means a winning probability of "30% to less than 60%". It means that the lottery value corresponding to "" is specified, and "high" means that the lottery value corresponding to the winning probability "60% to less than 80%" is specified. Further, "extremely high" in the data table means that a lottery value corresponding to a winning probability of "80% to less than 99%" is specified, and "extremely high" means a winning probability of "99% to less than 99%". It means that the lottery value corresponding to "less than%" is specified, and "confirmed" means that the lottery value corresponding to the winning probability "100%" is specified.

Then, in the various data tables shown below, the random number register 1 of the random number circuit 110 sequentially subtracts the lottery random number values extracted from the predetermined numerical value range (0 to 65535) by the specified lottery values. , Internal lottery is performed by determining whether or not the result of subtraction is negative (whether or not so-called "digits" have occurred). In the present embodiment, an example of determining winning / non-winning by subtracting the lottery value from the lottery random value in the lottery process related to game playability performed during the general game state has been described, but the present invention is limited to this. Instead, the lottery value is added to the extracted random number value for lottery, and it is determined whether or not the addition result exceeds 65536 (whether or not so-called "digit overflow" has occurred), and the winning / non-winning is determined. May be good.

[Normal medium and high probability lottery table]
First, the normal medium-high probability lottery table used in the transition lottery of the CZ lottery state (low probability and high probability) will be described with reference to FIGS. 40A and 40B. In the pachislot machine 1 of the present embodiment, not only the transition lottery of the lottery state of the CZ is performed based on the internal winning combination in each game, but also at the end of the bonus, the end of the CZ, the end of the ART, etc. Transition of lottery state A lottery is performed. FIG. 40A is a configuration diagram of a normal middle / high probability lottery table that is referred to every game during the normal game state, and FIG. 40B is a normal middle / high that is referred to at the time of setting change, bonus end, CZ, ART end, etc. It is a block diagram of a probability lottery table. The name of the internal winning combination shown in FIG. 40A corresponds to the name of the sub-flag described above.

The normal medium- and high-probability lottery table shown in FIG. 40A shows each combination of the current CZ lottery state and the internal winning combination, the lottery result (low probability / high probability) of the CZ lottery state after the transition, and each lottery result. Define the correspondence with the associated lottery value information.

As is clear from the normal medium-high probability lottery table shown in FIG. 40A, when the current lottery state of CZ is low probability, when the internal winning combination is the combination corresponding to the sub-flag "weak cherry", the CZ The lottery state is likely to shift to a high probability. On the other hand, when the current CZ lottery state has a high probability, when the internal winning combination corresponds to any of the sub-flags "common bell", "cactus", "weak cherry" and "strong cherry". In addition, the lottery state of CZ is maintained with high probability.

In the normal medium-high probability lottery table shown in FIG. 40B, each situation when referring to the table, the lottery result (low probability / high probability) of the lottery state of CZ after the transition, and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the normal medium-high probability lottery table shown in FIG. 40B, the lottery state of CZ always shifts to a high probability at the end of the bonus.

[CZ lottery table]
Next, the CZ lottery table used in the CZ lottery will be described with reference to FIGS. 41A and 41B. FIG. 41A is a block diagram of a CZ lottery table used when performing a CZ lottery based on an internal winning combination during a normal game state, and FIG. 41B shows a CZ pullback at the time of CZ failure or ART end, for example. It is a block diagram of the CZ lottery table used when performing the CZ lottery whether or not to perform. The name of the internal winning combination shown in FIG. 41A corresponds to the name of the sub-flag described above.

The CZ lottery table shown in FIG. 41A shows each combination of the current CZ lottery state and the internal winning combination, the winning / non-winning (lottery result) of CZ1, CZ2, and CZ3, and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the CZ lottery table shown in FIG. 41A, when the current CZ lottery state is in the high probability, the CZ lottery is won more than in the case where the current CZ lottery state is in the low probability. The probability is high.

In the CZ lottery table shown in FIG. 41B, the correspondence between the winning / non-winning (lottery result) of CZ1, CZ2, and CZ3 at the time of CZ failure or the end of ART and the information of the lottery value associated with each lottery result. To specify. At the time of CZ failure (when the ART lottery in CZ1 and CZ2 is not won) or at the end of the ART game state, the CZ pull-back lottery is performed using this CZ lottery table.

[CZ1 medium mode up lottery table]
Next, with reference to FIG. 42, the CZ1 medium mode-up lottery table used in the CZ1 mode-up lottery performed in the first half of CZ1 will be described. FIG. 42 is a configuration diagram of a mode-up lottery table in CZ1. The name of the internal winning combination shown in FIG. 42 corresponds to the name of the sub-flag described above.

The CZ1 medium mode-up lottery table has a correspondence relationship between each combination of the current mode and the internal winning combination, the mode-up lottery result (winning / non-winning), and the lottery value information associated with each lottery result. To specify. As shown in FIG. 44A described later, in CZ1, the higher the mode (the higher the value of the mode), the higher the probability of winning the ART lottery, and when the mode goes up to the mode 6, the ART lottery is always won.

The lottery result "mode 1 UP" in FIG. 42 means that the mode of CZ1 is raised by one step, and the lottery result "mode 2 UP" means that the mode of CZ1 is raised by two steps. Therefore, for example, in a situation where the current mode is mode 2, if the lottery result "mode 2 UP" is won, the mode of CZ1 goes up from mode 2 to mode 4. Further, for example, when the lottery result "mode 6UP_freeze occurrence" is won, the freeze occurs, and the winning of the ART lottery and the granting of CT are determined.

[CZ2 middle point lottery table]
Next, the CZ2 middle point lottery table used in the CZ2 point-up lottery performed in the first half of the CZ2 will be described with reference to FIG. 43. FIG. 43 is a configuration diagram of a CZ2 middle point lottery table. The name of the internal winning combination shown in FIG. 43 corresponds to the name of the sub-flag described above.

The CZ2 middle point lottery table shows the correspondence between each combination of the current points and the internal winning combination, the result of the point-up lottery (winning / non-winning), and the lottery value information associated with each lottery result. Prescribe. As shown in FIG. 44B, which will be described later, in CZ2, the higher the points, the higher the probability of winning the ART lottery, and when the points rise to "point 10", the ART lottery is always won. The lottery result "point 2 UP" in FIG. 43 means that "2" is added to the points of the current CZ2. For example, in a situation where the current point is "2", the lottery result "point 2 UP" If you win "Point 2 UP", the points of CZ2 will increase from "2" to "4". Further, for example, when the lottery result "point 10UP_freeze occurrence" is won, the freeze occurs, and the winning of the ART lottery and the granting of CT are determined.

[ART lottery table in CZ]
Next, the ART lottery table in CZ used in the ART lottery performed during CZ will be described with reference to FIGS. 44A-44C and 45. Note that FIG. 44A is a block diagram of the CZ medium ART lottery table (for CZ1) used in the first game of the latter half of CZ1, and FIG. 44B is a configuration diagram of the CZ medium ART used in the first game of the latter half of CZ2. It is a block diagram of the lottery table (for CZ2), and FIG. 44C is the block diagram of the ART lottery table in CZ (common to CZ1, CZ2 for the latter half of the battle) used in the latter half of CZ1 and CZ2. Further, FIG. 45 is a block diagram of an ART lottery table (for CZ3) in CZ used in an ART lottery executed in CZ3. The names of the internal winning combinations shown in FIGS. 44C and 45 correspond to the names of the sub-flags described above.

The ART lottery table in CZ (for CZ1) shown in FIG. 44A defines the correspondence between the current mode, the result of the ART lottery (presence or absence of winning), and the lottery value information associated with each lottery result. .. Further, the ART lottery table (for CZ2) in CZ shown in FIG. 44B shows the correspondence between the current points, the result of the ART lottery (presence or absence of winning), and the lottery value information associated with each lottery result. Prescribe.

As is clear from the ART lottery table in CZ (for CZ1) and the ART lottery table in CZ (for CZ2), in CZ1 and CZ2, the higher the rank (mode or point) of the first half, the easier it is to win the ART lottery.

The ART lottery table in CZ (common to CZ1 and CZ2 for the latter half of the battle) shown in FIG. 44C includes the internal winning combination, the result of the ART lottery (presence or absence of winning), and the lottery value information associated with each lottery result. Prescribe the correspondence of. As is clear from the ART lottery table in CZ (common to CZ1 and CZ2 for the latter half of the battle), in the latter half of CZ1 and CZ2, the role corresponding to the rare role (sub-flags "weak cherry", "cactus" or "strong cherry". ) Is determined as the internal winning combination, and the ART lottery is won with a predetermined probability.

The ART lottery table in CZ (for CZ3) shown in FIG. 45 shows each combination of the number of digestion games of CZ3 and the internal winning combination, the result of ART lottery (presence or absence of winning), and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the ART lottery table in CZ (for CZ3), in the present embodiment, when the ART lottery is won in CZ3, the CT is always won.

<Playability during normal ART>
Next, the flow of the game during the game ART will be described with reference to FIGS. 46A and 46B. In the pachi-slot machine 1 of the present embodiment, as described above, normally ART and CT are provided as ART gaming states (see FIGS. 14A and 14B), and the inside of CT is used as an additional chance zone. Therefore, in the present embodiment, the player usually plays a game during ART with the aim of shifting to CT.

[Mode of transition from normal ART to CT]
FIG. 46A is a diagram showing a mode of transition of the gaming state from normal ART to CT. In the pachislot machine 1 of the present embodiment, as shown in FIG. 46A, when the CT lottery performed during the normal ART is won, the gaming state shifts from the normal ART to the CT. As shown in FIG. 46A, the pachislot machine 1 of the present embodiment is provided with an ART level and a CT lottery state as parameters that affect various lottery normally performed during ART.

As the ART level, four levels of levels 1 to 4 are provided, and this ART level is controlled (determined) mainly based on the number of continuous (digestion) games during normal ART. Then, the ART level affects the determination of the CT lottery state, the flag conversion lottery during the normal ART, which will be described later, and the like.

The CT lottery state is provided with four stages of low probability, normal, high probability, and ultra-high probability, and the CT lottery state is controlled mainly based on the ART level and the internal winning combination during normal ART ( It is determined. Then, the CT lottery state affects the CT lottery performed during the normal ART, the flag conversion lottery during the normal ART, which will be described later, and the like.

[Flag conversion during normal ART]
As described above, in the pachislot machine 1 of the present embodiment, during the RT4 state, that is, during the ART game state, the internal winning combinations "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_" When any one of "Reach Eye Lip D" is independently determined as an internal winning combination, a flag conversion lottery is performed, and a special privilege (for example, an addition of the number of ART games or a CT winning) is given according to the lottery result. .. FIG. 46B is a diagram showing an outline of a flag conversion lottery method that is usually performed during ART.

In the present embodiment, as shown in FIG. 46B, the flag conversion lottery is performed in the normal ART with reference to the ART level and the CT lottery state. As a result, when the flag conversion lottery is won, a special privilege is given, and the symbol combination related to the abbreviation "triple chili lip" and the symbol combination related to the abbreviation "reach eye lip" are stopped and displayed on the effective line. Navigation (for example, notification of information to aim at a predetermined symbol by pushing forward) is performed. On the other hand, if the flag conversion lottery is not won, navigation (for example, notification of the push order other than forward push) is performed to stop and display the symbol combination related to the abbreviation "replay" on the effective line.

Then, when the player performs a stop operation according to this notification (navigation), the symbol combination according to the notification content is stopped and displayed on the effective line. Specifically, when the flag conversion lottery is won, the symbol combination related to the abbreviation "triple chili lip" and the symbol combination related to the abbreviation "reach eye lip" are stopped and displayed on the effective line and are not displayed in the flag conversion lottery. In the case of winning, the symbol combination related to the abbreviation "replay" is stopped and displayed on the effective line.

<Various data tables normally used during ART>
Next, with reference to FIGS. 47 to 51, various data tables usually used in the lottery process during ART will be described. The various data tables described below are stored in the main ROM 102.

[Flag conversion lottery table during ART]
FIGS. 47A and 47B are block diagrams of a flag conversion lottery table during ART, which is usually used in a flag conversion lottery performed during ART.

In the pachislot machine 1 according to the present embodiment, the flag conversion lottery during normal ART is performed in two stages. Specifically, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, the first stage flag conversion lottery is first performed, and if the first stage flag conversion lottery is won, then The second stage flag conversion lottery is performed. Then, when the second-stage flag conversion lottery is won, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted into the sub-flag EX "triple chili lip". On the other hand, if the first-stage flag conversion lottery or the second-stage flag conversion lottery is non-winning, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted to the sub-flag EX "replay". (Treat as a normal replay role). If any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, only the second stage flag conversion lottery is performed.

FIG. 47A is a configuration diagram of an ART flag conversion lottery table used in the first stage flag conversion lottery, and FIG. 47B is a configuration diagram of an ART flag conversion lottery table used in the second stage flag conversion lottery. be.

The ART flag conversion lottery table shown in FIG. 47A has an internal winning combination (“F_certain chili lip” or “F_1 certain chili lip”) and a lottery result of the first stage flag conversion lottery (no conversion / with conversion (provisional)). And the correspondence relationship with the lottery value information associated with each lottery result is defined.

The ART flag conversion lottery table shown in FIG. 47B shows each combination of the internal winning combination, the ART level, and the CT lottery state, the lottery result of the second stage flag conversion lottery (without conversion / with conversion), and each lottery result. The correspondence with the lottery value information associated with is specified. In the game until the CT is won once in the normal ART, the table in the "First time (until the CT is won once)" column of the item "ART level" in FIG. 47B is referred to.

In the present embodiment, as shown in FIGS. 47A and 47B, in the first and second stage flag conversion lottery using each of the flag conversion lottery tables during ART, a random number value (0 to 0) having a probability denominator of "256". A lottery is carried out using 255). Therefore, in the present embodiment, the above-mentioned two-step flag conversion lottery can be regarded as substantially the same lottery as the case where one lottery is performed using a random number value having a probability denominator of "65536".

In recent pachislot machines, lottery (ART lottery, etc.) related to ball ejection, which was conventionally performed on the sub control board 72 side (hereinafter referred to as "sub side"), is performed on the main control board 71 side (hereinafter referred to as "main side"). It is required to do. However, since the capacity of the storage means (main ROM 102) on the main side is limited to a small capacity, there is a demand for a mechanism that enables lottery without impairing game playability while suppressing an increase in processing capacity.

Regarding this point, in the pachislot machine 1 of the present embodiment, the lottery having the probability denominator of "256" can be performed in two stages, so that the lottery having the probability denominator of "65536" can be performed. The increase in capacity on the side can be suppressed. Further, in the second stage lottery, since the ART level, the CT lottery state, etc. are referred to, not only the internal winning combination but also the flag conversion lottery according to the current state can be performed, and as a result, various playability can be achieved. You can perform the flag conversion lottery you have.

[ART level determination table]
FIGS. 48A and 48B are block diagrams of an ART level determination table used when determining an ART level. The ART level determination process is performed at the time of winning the ART when the transition to the ART gaming state is decided, and during the normal ART. FIG. 48A is a configuration diagram of an ART level determination table used at the time of winning ART, and FIG. 48B is a configuration diagram of an ART level determination table normally used during ART.

The ART level determination table shown in FIG. 48A defines the correspondence between the ART levels 1 to 4 (lottery results) and the lottery value information associated with each ART level. In the present embodiment, if a freeze occurs at the time of winning the ART, the ART level 2 is determined as the ART level.

The ART level determination table shown in FIG. 48B is a lottery associated with each combination of the current ART level and the number of elapsed (digested) games of the normal ART, various ART levels of the migration destination, and each ART level of the migration destination. Define the correspondence with the value information. Further, the ART level determination table shown in FIG. 48B corresponds to each combination of the current ART level and the number of elapsed games of the normal ART at the time of CT entry, various ART levels of the migration destination, and each ART level of the migration destination. The correspondence with the information of the lottery value obtained is specified. That is, during normal ART, not only the ART level can be shifted when the number of elapsed (digested) games of normal ART reaches a predetermined number of games, but also the ART level can be changed at the timing of entering CT during normal ART. It can be migrated.

[Normal ART medium and high probability lottery table]
FIG. 49 is a block diagram of a normal ART medium-high probability lottery table used when determining a CT lottery state during normal ART.

The normal ART medium-high probability lottery table has a correspondence relationship between each combination of the current CT lottery state and the internal winning combination, various CT lottery states of the migration destination, and lottery value information associated with each CT lottery state. Prescribe. The name of the internal winning combination shown in FIG. 49 corresponds to the name of the sub-flag described above.

As is clear from the normal ART medium and high probability lottery table, the internal winning combination corresponding to the sub-flag "triple chili lip (triple chili lip A and triple chili lip B)" and the sub-flag "reach eye lip (reach eye lip 1-4)". If is a win, the CT lottery state is likely to shift (fall) to a "low probability". However, as shown in FIG. 50 described later, when the internal winning combination corresponding to the sub-flags "triple chili lip" and "reach eye lip" is won, even if the CT lottery state falls, CT The structure is such that the lottery is always won.

[CT lottery table during ART]
FIG. 50 is a block diagram of a CT lottery table during ART used in a CT lottery normally performed during ART.

The CT lottery table during ART shows each combination of the current CT lottery state and the internal winning combination, various lottery results (non-winning / normal CT / high probability CT) of the CT lottery, and a lottery associated with each lottery result. Define the correspondence with the value information. The name of the internal winning combination shown in FIG. 50 corresponds to the name of the sub-flag described above.

In the present embodiment, the sub-flags "cactus", "weak cherry", "strong cherry", "triple chili lip (triple chili lip A and triple chili lip B)", and "reach eye lip (reach eye lip)" are used as internal winning roles. When the combination corresponding to "1 to 4)" or "BB" is determined, in the CT lottery process using the CT lottery table during ART, the CT lottery using the random value in the range where the probability denominator is "256" Is done. In addition, if an internal winning combination other than these roles (for example, a combination corresponding to the sub-flags "replay", "common bell", "pushing order bell", etc.) is determined as the internal winning combination, CT during ART In the CT lottery process using the lottery table, CT lottery using random values in the range where the probability denominator is "65536" is performed.

In the pachislot machine 1 of the present embodiment, two types of CTs called "normal CT" and "high probability CT" are provided as CTs. Normal CT and high-probability CT have different expectations for the number of ART games added during CT (additional chance zone), and high-probability CT is a CT in which a large number of ART games are likely to be added compared to normal CT. (See FIG. 55 below).

[Normal ART extra lottery table]
FIG. 51 is a configuration diagram of an additional lottery table during normal ART, which is used in an additional lottery for the number of ART games performed during normal ART. The name of the internal winning combination shown in FIG. 51 corresponds to the name of the sub-flag described above.

Normally, the additional lottery table during ART defines the correspondence between the internal winning combination, various lottery results of the additional lottery (non-winning / additional 10G to 300G), and the lottery value information associated with each lottery result.

<Playability during CT>
Next, the flow of the game during CT will be described with reference to FIGS. 52A to 52C. It should be noted that FIGS. 52A and 52B are mainly diagrams showing an outline of the game flow during CT at the time of winning the sub-flag EX "triple chili lip", and FIG. 52C shows an outline of the flag conversion process performed during CT. It is a figure.

[Game content during CT]
In the pachislot machine 1 of the present embodiment, in CT, one set of eight games (8 games) is played. During the CT period, an additional lottery for the number of ART games is performed for each game based on the internal winning combination. Then, when the additional lottery is won, the unit game number (game number) of the CT game is not subtracted, while when the additional lottery is non-winning, the unit game number (game number) of the CT game is not subtracted. Number) is subtracted. Therefore, during the CT period, the CT does not end in the game in which the number of ART games is added, and the CT ends when the game in which the number of ART games is not added is performed eight times in the same set. ..

Further, in the present embodiment, as shown in FIGS. 52A and 52B, when the sub-flag EX "triple chili lip" is won, that is, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won. However, if the flag conversion lottery is won, the CT games 8 times per set are reset (stocked). Then, the set of the reset (stocked) CT game is started after the set of the CT game is completed.

For example, in the same set, after the unit game that is not a winning lottery is played 7 times in the lottery for adding the number of ART games, the CT ends when the CT game in which the number of ART games is not added is played once. If the sub-flag EX "Triple Chili Lip" is won, the CT game will be reset. As a result, after the CT game is reset, the CT will not end until the unit game, which is a non-winning lottery, is performed eight times in the additional lottery for the number of ART games. Therefore, the game period of CT becomes long enough to win the sub-flag EX "triple chili lip".

[Flag conversion during CT]
Next, with reference to FIG. 52C, a method of flag conversion lottery performed during CT will be described. As described above, in the present embodiment, when the sub-flag EX "triple chili lip" is won during the CT period (internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, and the flag conversion lottery is won. Then), the CT is reset (stocked). Further, as shown in the CT flag conversion lottery table of FIG. 54, which will be described later, if the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is won during CT, the flag conversion lottery is always won (sub-flag EX “sub-flag EX”. It will always be converted to "triple chili lip"). That is, in the present embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won during CT, the CT is always reset.

Further, in the flag conversion lottery when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, the flags are based on three types of flag conversion tables (tables 0 to 2). The winning probability of the conversion lottery is controlled. Specifically, as shown in FIG. 52C, table 0 is a flag conversion table having the lowest probability of being converted to the sub-flag EX "reach eye lip", and table 1 is converted to the sub-flag EX "reach eye lip". It is a flag conversion table having the next lowest probability, and table 2 is a flag conversion table having the highest probability of being converted to the sub-flag EX “reach eye lip”. If the sub-flag EX "reach eye lip" is won during CT, CT is newly added as shown in the lottery table for adding the number of sets in CT described later in FIG. 56.

Further, in the present embodiment, in normal CT, as shown in FIG. 52C, the flag conversion table is determined based on the ART level. On the other hand, in high-probability CT, table 0 is always determined as the flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, various data tables used in the lottery process performed during CT will be described with reference to FIGS. 53 to 56. The various data tables described below are stored in the main ROM 102.

[Table during CT lottery table]
FIG. 53 is a configuration diagram of a CT table lottery table used when determining a table to be used for the flag conversion lottery from the three-stage flag conversion tables (tables 0 to 2).

The lottery table during CT shows the correspondence between each state such as the ART level and the type of CT to be executed, the type of the flag conversion table (tables 0 to 2), and the lottery value information associated with each type. Prescribe. The table lottery table during CT is referred to when it is decided to win the CT lottery and shift to CT, or at the start of CT.

[Cut flag conversion lottery table]
FIG. 54 is a configuration diagram of a flag conversion lottery table during CT used in a flag conversion lottery performed during CT.

The flag conversion lottery table during CT includes an internal winning combination (one of "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D") and each flag conversion table ( The correspondence between the lottery result (without conversion / with conversion) of the flag conversion lottery in Tables 0 to 2) and the lottery value information associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, if the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won during CT, the flag conversion lottery is always won (sub-flag EX "triple chili lip" is always won). Will be converted).

[Additional lottery table during CT]
FIG. 55 is a configuration diagram of an additional lottery table during CT used in an additional lottery for the number of ART games performed during CT.

The extra lottery table during CT is associated with each combination of the current CT state and the internal winning combination, various lottery results of the additional lottery (non-winning / additional 10 games / ... / additional 300 games), and each lottery result. The correspondence with the lottery value information is specified. The name of the internal winning combination shown in FIG. 55 corresponds to the name of the sub-flag described above, and when a combination other than the internal winning combination (sub-flag) shown in FIG. 55 is internally won, the additional lottery during CT is won. There is nothing to do.

Further, in the additional lottery during the normal CT of the present embodiment, the form of granting the number of additional games changes according to the number of winnings of the sub-flag "triple chili lip" (internal winning combination "F_certain chili lip" or "F_1 certain chili lip"). do.

Specifically, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 1 to 8, it is given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. The number of additional games will be 10 games and 20 games, respectively. Therefore, in this case, 10 games can be easily determined as the number of additional games of ART. Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 9 to 16 times, the additional game given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Both numbers will be 20 games. That is, the number of additional games (lottery result) corresponding to the lottery value "extremely high" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 20 games. Therefore, in this case, 20 games can be easily determined as the number of additional games for ART.

Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 17 to 24 times, the additional game given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Both numbers will be 30 games. That is, the number of additional games (lottery result) corresponding to the lottery values "extremely high" and "extremely low" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 30 games. Therefore, in this case, "30 games" can be easily determined as the number of additional games for ART. Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 25 times or more, the number of additional games given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Will both be 50 games. That is, the number of additional games (lottery result) corresponding to the lottery values "extremely high" and "extremely low" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 50 games. Therefore, in this case, "50 games" can be easily determined as the number of additional games for ART.

As described above, in the pachislot machine 1 of the present embodiment, it is possible to increase the number of ART games that can be added by one additional lottery according to the number of times the sub-flag "triple chili lip" is won during CT. Further, as described above, in the present embodiment, as long as the number of ART games is added, the CT does not end, and when the sub-flag EX "triple chili lip" is applied, the CT is reset (stock). Is done. Therefore, in the present embodiment, the player can be expected to increase the additional amount per game as the CT continues, and the interest during the CT can be improved. In addition, the number of winnings of the sub-flag "Triple Chili Lip", which is an opportunity to increase the amount of addition per game, is more than the basic number of games (8 times) for one set of CT (9 times or more). It is possible to prevent an excessive profit from being given to the game, and it is possible to balance the profit between the player and the game store.

In the present embodiment, the number of winnings of the above-mentioned sub-flag "triple chili lip" (internal winning combination "F_certain chili lip" or "F_1 certain chili lip") is the number of times counted in the same CT set. The present invention is not limited to this. For example, a new CT given when a lottery for adding the number of sets performed during CT is won may be included in "in the same CT set".

[Lottery table with additional sets during CT]
FIG. 56 is a configuration diagram of a lottery table for adding the number of sets in CT used in the lottery for adding CT sets performed during CT.

The lottery table for adding the number of sets during CT is a combination of the current CT state and the internal winning combination (sub-flag "reach-eye rip (reach-eye rips 1 to 4)"), and various lottery results of the additional lottery (non-winning / normal). The correspondence between the CT winning / high-probability CT winning) and the lottery value information associated with each lottery result is defined.

As is clear from the additional lottery table for the number of sets during CT, if you win any of the internal winning roles "F_reach eye lip A" to "F_reach eye lip D" during CT, you will definitely win the additional lottery for the CT set. (CT sets are always stocked). The stocked CT set is started after the currently operating CT set is completed.

<Playability in bonus state>
Next, the flow of the game in the bonus state will be described with reference to FIGS. 57A to 57C. FIG. 57A is a diagram showing the flow of the game when the gaming state shifts to the bonus state during the general gaming state (ART non-winning), and FIG. 57B shows the case where the gaming state shifts to the bonus state during normal ART. It is a figure which shows the flow of the game in FIG. 57C, and FIG. 57C is a figure which shows the flow of the game when the game state shifts to the bonus state during CT.

In the pachislot machine 1 of the present embodiment, as shown in FIGS. 57A to 57C, a normal BB and a special BB are provided as bonus types in terms of playability, and the type of this bonus is determined at the time of transition to the bonus state. Will be done. At this time, if the special BB is determined, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the normal BB is determined, the game state of the transition destination differs depending on the state before the transition to the bonus state.

When the gaming state shifts from the general gaming state to the normal BB, as shown in FIG. 57A, in the game during the normal BB, the ART lottery is performed based on the internal winning combination. Then, when the ART lottery is won, the game state shifts to the normal ART via the ART preparation state after the end of the bonus state. In this case, in the game in the bonus state after winning the ART lottery, the number of ART games is added to the lottery.

When the gaming state shifts from the normal ART to the normal BB, as shown in FIG. 57B, a CT lottery is performed at the end of the normal BB. The winning probability of this CT lottery is 50%, and when the winning is done, the game state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the CT lottery is not won, the game state shifts to the normal ART via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state that has been transferred from the normal ART, an additional lottery for the number of ART games is also performed.

When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 57C, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state transferred from CT, an additional lottery for the number of ART games is also performed.

<Various data tables used in games in the bonus state>
Subsequently, with reference to FIGS. 58 to 60, various data tables used in the lottery process performed in the game in the bonus state will be described. The various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 58 is a configuration diagram of a bonus type lottery table used when determining a bonus type (normal BB, special BB).

The bonus type lottery table shows each game state (CT and others) before shifting to the bonus state, various lottery results (bonus type: normal BB / special BB), and a lottery value associated with each lottery result. Define the correspondence with information. The bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[Bonus lottery table with the number of ART games added]
FIG. 59 is a configuration diagram of a lottery table for adding the number of ART games in the bonus used in the ART lottery and the lottery for adding the number of ART games performed in the game in the bonus state.

The lottery table for adding the number of ART games in the bonus is associated with each combination of the current bonus type and the internal winning combination, various lottery results of the additional lottery (non-winning / 5 games / ... / 300 games), and each lottery result. The correspondence with the information of the lottery value obtained is specified.

In the present embodiment, in the ART non-winning state (the state until the ART lottery is won in the normal BB shifted from the general game state), the lottery table for adding the number of ART games during the bonus is used for the ART lottery. Specifically, in the ART non-winning state, when the number of additional games of 1 game or more (50 games or more in the example shown in FIG. 59) is determined by the lottery using the lottery table for adding the number of ART games during the bonus, ART Along with winning the lottery, the corresponding number of games is given as the number of ART games. On the other hand, in the state after winning the ART, the lottery table for adding the number of ART games during the bonus is used only for the lottery for adding the number of ART games.

[CT lottery table at the end of bonus]
FIG. 60 is a configuration diagram of a CT lottery table at the end of the bonus used in the CT lottery performed at the end of the bonus state.

The CT lottery table at the end of the bonus shows each combination of the bonus type (normal BB, special BB) and the game state (during normal CT, high probability CT) before shifting to the bonus state, and various lottery results of the CT lottery (during normal CT, high probability CT). The correspondence between the non-winning / normal CT winning / high-probability CT winning) and the lottery value information associated with each lottery result is defined. As is clear from the CT lottery table at the end of the bonus, for example, if a normal BB is performed during a normal ART, there is a 50% chance of winning the CT at the end of the bonus state.

<Exceptional playability during general game state>
Next, with reference to FIG. 61, an exceptional game flow during the general game state will be described.

In the basic flow of the gaming state in the pachislot machine 1 of the present embodiment, the gaming state shifts from the normal gaming state to the CZ during the general gaming state, and the gaming state shifts to the ART gaming state by winning the ART lottery in the CZ. do. Then, in the present embodiment, the ART gaming state is realized by notifying in the RT4 state. Further, in the present embodiment, as shown in FIG. 61, the transition control of the RT state is performed according to the symbol combination displayed as stopped.

It should be noted that the symbol combination for shifting the RT state is a stop display according to the player's stop operation order (push order) (see FIG. 24), so that the notification may not be performed. By chance, the RT state may shift to the RT4 state. Further, in the RT4 state, one of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" may be determined, so that even during the general gaming state (non-ART), It is possible to display a reach eye (a symbol combination related to the abbreviation "reach eye lip") to which a special privilege is given.

Therefore, in the pachislot machine 1 of the present embodiment, as shown in FIG. 61, the RT state accidentally shifts to the RT4 state during the general gaming state (non-ART), and the symbol combination related to the abbreviation "reach eye lip" can be displayed. In such a state, the gaming state can be shifted to the ART gaming state (normal ART) without going through the CZ.

More specifically, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined in the general game state and in the RT4 state, a flag conversion lottery is performed. When this flag conversion lottery is won, notification (navigation) for displaying the symbol combination related to the abbreviation "reach eye lip" is performed, and the right of ART is granted. On the other hand, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined in the general game state and in the RT4 state, the flag conversion lottery is not won. Notification is performed to display the symbol combination related to the abbreviation "replay", and control is performed so that the symbol combination related to the abbreviation "reach eye lip" is not displayed.

<Various data tables used for exceptional game control during the general game state>
Next, with reference to FIG. 62, a data table used in the lottery process performed in the exceptional game control in the general game state described above will be described. The data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 62 is a configuration diagram of a non-ART flag conversion lottery table used in a flag conversion lottery performed in a game in the general game state and in the RT4 state.

The non-ART flag conversion lottery table has an internal winning combination ("F_reach eye lip A" to "F_reach eye lip D"), a lottery result of the flag conversion lottery (without conversion / with conversion), and each lottery result. Define the correspondence with the associated lottery value information.

<Notification function controlled by the main side>
In the conventional pachislot machine, information (navigation) of reel stop operation information (pushing order, etc.) is performed by controlling the sub (sub-control board 72) side during ART. However, since the presence or absence of this notification affects the profit of the player (so-called ball ejection), in recent years, it has been required to perform the notification on the main (main control board 71) side that manages the profit of the player. There is. Therefore, in the pachi-slot machine 1 of the present embodiment, as described above, the information display 6 controlled on the main side is provided with an instruction monitor (not shown) for notifying the information of the stop operation, and is controlled by the main side. A function for notifying information on the reel stop operation is provided.

Here, FIGS. 63A to 63D show the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the pachislot machine 1 of the present embodiment. Note that FIG. 63A is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the ART preparation state, and FIG. 63B is a diagram during ART (normal ART or CT). It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side, and the notification (navigation) performed on the sub side. Further, FIG. 63C is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flags), and FIG. 63D is a diagram showing the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side. It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in (between BB2 flags).

In the present embodiment, as shown in FIGS. 63A to 63D, on the main (main control board 71) side, the information of the reel stop operation is notified by displaying the numerical values of "1" to "11" on the instruction monitor. do. The numerical values of "1" to "11" displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

Specifically, the numerical values "1" to "3" indicate the types of reels that perform the first stop operation, and the numerical values "1" mean that the first stop operation is performed on the left reel 3L. Then, the numerical value "2" means that the first stop operation is performed on the middle reel 3C, and the numerical value "3" means that the first stop operation is performed on the right reel 3R.

Further, the numerical values "4" to "9" indicate the push order to be notified, and the numerical value "4" means that the push order is "left, middle, right", and the numerical value "5". Means that the push order is "left, right, middle", the numerical value "6" means that the push order is "middle, left, right", and the numerical value "7" is the push order. The order is "middle, right, left", the numerical value "8" means that the pushing order is "right, left, middle", and the numerical value "9" is the pushing order. It means that the order is "right, middle, left".

In addition, the numerical values "10" and "11" respectively notify the bonus combination, and the numerical value "10" is a symbol combination related to the combination name "C_BB1" (design "white 7" -design "white 7"-. The symbol "white 7") is meant, and the numerical value "11" means a symbol combination (symbol "blue 7" -symbol "blue 7" -symbol "blue 7") related to the combination name "C_BB2".

Although the numerical values "1" to "11" notified on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be notified, all players are clear based on the numerical values. It is not always possible to grasp the content of the notification. For example, it may not be possible for some players to grasp the content of the notification simply by displaying the numerical value "6" on the instruction monitor on the main side.

Therefore, in the pachi-slot machine 1 of the present embodiment, the information related to the stop operation of the stop button is notified on the sub side as well as the notification on the main side. Specifically, the display measure 11 (projector mechanism 211 and display unit 212) controlled on the sub side is used to notify the information related to the stop operation under the control of the sub side.

For example, when notifying the push order in which the first stop operation is performed on the left reel 3L, the numerical value "1" is displayed on the instruction monitor on the main side, and the left reel in the display screen of the display device 11 is displayed on the sub side. A numerical value "1" is displayed above the 3L to notify that the left reel 3L is the target of the first stop operation. Further, when notifying the push order "middle, left, right", the numerical value "6" is displayed on the instruction monitor on the main side, and the numerical value is displayed above the middle reel 3C in the display screen of the display device 11 on the sub side. "1" is displayed, the numerical value "2" is displayed above the left reel 3L, and the numerical value "3" is displayed above the right reel 3R. Notify that Further, when the internal winning combination "F_BB1" is determined, the numerical value "10" is displayed on the instruction monitor on the main side, and "white 7"-"white 7" is displayed on the display screen of the display device 11 on the sub side. -Displays information about the symbol combination of "White 7" and informs the player of the symbol to be aimed at.

The timing of notification on the main side can be set to any timing as long as it is at least the period of one game in which notification is performed. For example, the main side may be notified at the timing when the player's start operation is detected (accepted), the main side may be notified at the start of reel rotation, and the first stop operation to the third stop operation may be performed. The main side may be notified at the timing when any of the stop operations is detected. On the other hand, the timing of performing the notification on the sub side is preferably at least a timing before the first stop operation. Therefore, in the pachi-slot machine 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or the timing when the rotation of the reel starts. As a result, before the player performs the stop operation, the stop operation information is notified on both the instruction monitor on the main side and the display device 11 on the sub side.

In the ART preparation state, as shown in FIG. 63A, notifications (navigation) called "bell navigation", "maintenance lip navigation", "RT3 transition lip navigation" and "RT4 transition lip navigation" are performed by the control of the main side. In "Bell Navi", when the internal winning combination "F_3 choice bell_1st" to "F_3 choice bell_3rd" is decided, the symbol combination (see FIG. 29) related to the abbreviation "bell" is stopped and displayed on the effective line. The push order of is notified. In "Maintenance Lip Navi", when the internal winning combination "F_Maintenance Lip_1st" to "F_Maintenance Lip_3rd" is determined, the symbol combination (see FIG. 28) related to the abbreviation "Replay" is stopped and displayed on the effective line. The push order for is notified. In the "RT3 transition lip navigation", when the internal winning combinations "F_RT3 lip_1st" to "F_RT3 lip_3rd" are determined, the symbol combination (see FIG. 28) related to the abbreviation "RT3 transition lip" is stopped and displayed on the effective line. The push order for making the user is notified. Further, in the "RT4 transition lip navigation", when the internal winning combinations "F_RT4 lip_123" to "F_RT4 lip_3rd" are determined, the symbol combination (see FIG. 28) related to the abbreviation "RT4 transition lip" is placed on the effective line. The push order for displaying the stop is notified.

Further, in the ART gaming state (normal ART or CT), as shown in FIG. 63B, the notifications referred to as "Bell Navi", "Maintenance Lip Navi", "RT3 Transition Lip Navi" and "RT4 Transition Lip Navi" are controlled by the main side. (Navigation) is performed. In the game in the ART game state (RT4 state), a flag conversion lottery is performed, and based on the lottery result, a symbol combination related to the abbreviations "triple chili lip", "reach eye lip" or "replay" is displayed. The push order is notified, but this notification is performed only on the sub side, not on the main side.

As mentioned above, since the symbol combination related to the abbreviation "triple chili lip" or "reach eye lip" is related to the granting of special benefits, the presence or absence of notification affects the player's profit (ball output). Although it seems to be given, in reality, in the pachislot machine 1 of the present embodiment, the special privilege is given based on the lottery result of the flag conversion lottery, so that the displayed symbol combination is the privilege to be given. It does not affect it. Therefore, for example, in the state of winning the flag conversion lottery, even if the symbol combination related to the abbreviation "replay" is stopped and displayed, a special privilege is given. On the other hand, even if the symbol combination related to the abbreviation "triple chili lip" or "reach eye lip" can be stopped and displayed in the state where the flag conversion lottery is not won, no special privilege is given. In the pachislot machine 1 of the present embodiment, when the symbol combination displayed in this way does not affect the profit (ball output) of the player, it is controlled on the sub side without notifying the instruction monitor on the main side. The notification is performed only on the display device 11.

Further, in the RT5 state (inter-flag state), as shown in FIGS. 63C and 63D, information is notified to the player to aim at the symbol combination related to the bonus combination carried over as the internal winning combination. For example, when the internal winning combination "F_BB1" is carried over, as shown in FIG. 63C, a notification (navigation) called "white 7 navigation" is performed by the control of the main side, and the internal winning combination "F_BB2" is performed. "Is carried over, as shown in FIG. 63D, a notification (navigation) called" blue 7 navigation "is performed by the control of the main side.

In "White 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB1", that is, the symbol combination related to the combination name "C_BB1" ("White 7"-"White 7"-"White 7": see FIG. 28). Information on the stop operation for displaying the stop on the valid line is notified. Further, in "Blue 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB2", that is, the symbol combination related to the combination name "C_BB2" ("Blue 7"-"Blue 7"-"Blue 7": FIG. 28 Information on the stop operation for displaying the stop display on the valid line (see) is notified.

In the inter-flag state, when the bonus combination and any of the internal winning combinations "off", "F_special 1", "F_special 2" and "F_special 3" are determined, as described in FIG. 24. , The symbol combination related to the bonus combination (BB combination) can be stopped and displayed on the effective line. However, if the internal winning combination other than the internal winning combination "missing", "F_special 1", "F_special 2" and "F_special 3" and the bonus combination are winning, the symbol combination related to the bonus combination Cannot be stopped and displayed on the valid line. Therefore, in the present embodiment, as shown in FIGS. 63C and 63D, the carried-over bonus combination and the internal winning combination “missing”, “F_special role 1”, “F_special role 2” and “F_special role” Only when any of "3" is a winning bonus, a notification called "white 7 navigation" or "blue 7 navigation" is performed under the control of the main side. Therefore, in the present embodiment, the notification (navigation) called "white 7 navigation" or "blue 7 navigation" controlled by the main side can be performed at an appropriate timing in which the bonus combination can be won.

The pachi-slot machine 1 of the present embodiment is also provided with a function of notifying a bonus by displaying a bonus confirmation screen or turning on a bonus confirmation lamp, for example. Therefore, on the main side, the navigation called "white 7 navigation" or "blue 7 navigation" may be performed only after announcing (bonus notification) that the bonus combination has been determined as the internal winning combination.

As a bonus notification, for example, an effect that is performed over a plurality of game periods (so-called continuous effect) is generally performed, and a bonus confirmation screen is displayed according to the result of this continuous effect. There is. If "White 7 Navi" or the like is performed on the main side during such a continuous production, the result of the continuous production will be known in the middle, which may spoil the interest. Therefore, in the present embodiment, after the bonus notification is made, the main control board 71 is notified (navigation) called "white 7 navigation" or "blue 7 navigation" by the control of the main side.

The method of making it possible for the main side to grasp the timing of the bonus announcement is arbitrary. As one of the methods, when the bonus combination is determined as the internal winning combination, the main control board 71 determines the number of games required until the end of the bonus notification, and after digesting the games of this number of games, "White 7 Navi" or A method of performing notification (navigation) called "blue 7 navigation" can be considered. More specifically, when the main control board 71 determines the number of games required until the end of the bonus notification, the main control board 71 notifies the sub control board 72 of the number of games. The sub-control board 72 controls the production according to the number of games, and displays the bonus confirmation screen at the timing when the games of the number of games are exhausted, so that the timing when the bonus notification is made on the main side can be grasped. Can be done. That is, the main control board 71 counts the number of unit games since the bonus combination is determined as the internal winning combination in a state where the bonus combination has not been carried over, and after the counting result reaches a predetermined number of times, the bonus combination And, when any of the internal winning bonuses "missing", "F_special role 1", "F_special role 2" and "F_special role 3" is determined as the internal winning combination, "white 7 navigation" or "white 7 navigation" or " Perform "Blue 7 Navi".

Further, as another method, a method of controlling the bonus notification on the main side instead of the sub side can be considered. More specifically, when the main control board 71 determines the bonus combination as the internal winning combination in the state where the bonus combination is not carried over, the main control board 71 determines the effect (at least the number of games required for the effect) to be executed by the display device 11. Notify the sub-control board 72. By executing the effect notified by the sub-control board 72 and displaying the bonus confirmation screen, it is possible to grasp the timing at which the bonus notification is made on the main side.

It should be noted that the main side may be configured to be able to grasp the timing at which the bonus notification is made by a method other than the above two methods. In this case, since the main control board 71 cannot receive the signal from the sub control board 72 or the like, it is necessary to grasp the timing at which the bonus notification is made based on the signal that the main control board 71 can accept. For example, since the main control board 71 can accept the signal associated with the stop operation, when a predetermined stop operation (for example, other than forward pressing) is performed while the bonus combination is determined as the internal winning combination. In addition, a method of notifying a bonus is also conceivable. Specifically, the sub-control board 72 acquires information on the internal winning combination and information on the stop operation from the main control board 71, and gives a bonus notification when the combination of these information is a predetermined combination. By adopting such a bonus notification method, the trigger of the bonus notification can also be grasped by the main control board 71, so that the timing at which the bonus notification is made can be grasped on the main side.

<Explanation of operation of main control circuit>
Next, with reference to FIGS. 64 to 119, the contents of various processes executed by the main CPU 101 of the main control circuit 90 by using the program will be described.

[Processing when power is turned on (reset interrupt)]
First, the power-on (reset interrupt) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIG. FIG. 64 is a flowchart showing a procedure for processing when the power is turned on (reset interrupt). In the power-on (reset interrupt) processing shown in FIG. 64, when the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 has started, the reset signal is sent to the microprocessor 91. It is output to the "XSRST" terminal, and after undergoing a delay operation by the security mode, it is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 performs an initialization process of the timer circuit 113 (PTC) (S1). In this process, the main CPU 101 initially sets the timer circuit 113. Specifically, the main CPU 101 sets the frequency division ratio in the timer prescaler register (not shown), sets the timer control register (not shown) to interrupt enable, etc., and sets the timer counter (not shown). Set the initial count value.

Next, the main CPU 101 performs initialization processing of the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub-control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. Initialization processing is performed (S2). Next, the main CPU 101 performs an initialization process of the random number circuit 110 (RDG) (S3). Next, the main CPU 101 performs a write test of the main RAM 103 (S4).

Next, the main CPU 101 determines whether or not the writing to the main RAM 103 has been normally performed as a result of the writing test (S5).

In S5, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when the determination in S5 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S5, when the main CPU 101 determines that the writing to the main RAM 103 has been normally performed (when the determination in S5 is YES), the main CPU 101 is in the state of the timer control register (not shown) of the timer circuit 113. (S6).

Next, the main CPU 101 determines whether or not the current state is the occurrence timing of the interrupt process based on the acquired state of the timer control register (S7). Specifically, the main CPU 101 determines whether or not 1.1172 ms has elapsed from the start of the timer count based on the acquired state of the timer control register.

In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. After that, the status of the timer circuit 113 can be acquired by reading the information of the timer control register (not shown). Then, in the present embodiment, a bit (discrimination bit) capable of discriminating (seeing) whether or not the current state is the occurrence timing of the interrupt process (whether or not it is the timer interrupt state) in the timer control register. ) Is provided.

Therefore, in the process of S6, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S7, the main CPU 101 is in the ON / OFF state of the discrimination bit in the timer control register (not shown). By referring to "1" / "0"), it is determined whether or not the current state is the occurrence timing of the interrupt process. When 1.1172 ms has elapsed from the start of counting by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the discrimination bit is turned on.

In S7, when the main CPU 101 determines that the current state is not the timing at which the interrupt process occurs (when the determination in S7 is NO), the main CPU 101 returns the process to the process of S6 and repeats the processes after S6.

On the other hand, in S7, when the main CPU 101 determines that the current state is the occurrence timing of the interrupt process (when the determination in S7 is YES), the main CPU 101 sets the command transmission start timer (S8). The command transmission start timer is a timer for managing the activation delay period (see FIG. 120 described later), which will be described later, and the period from when the command transmission start timer is set until it becomes 0 is the main control circuit 90 (see FIG. 120 described later). Command data is not transmitted from the main control board 71) to the sub control circuit 200 (sub control board 72) (see FIG. 115 described later). As a result, when the power of the pachi-slot machine 1 is turned on, the time required for the startup control of the sub CPU 201 (the time until the command can be received) is secured. That is, by setting the command transmission start timer, the transmission of communication data (command data) by the communication data transmission process is delayed for a period corresponding to the timer. In the present embodiment, in S8, "21801" (21801 x 1.1172 ms = about 24.3561 seconds) is set as the value of the command transmission start timer. However, the value of the command transmission start timer can be appropriately changed according to the specifications of the sub-control circuit 200 mounted at the same time.

The command transmission start timer is a software timer allocated in the game RAM area of the main RAM 103 in 2 bytes, and is arranged at an address that is not erased by the setting change confirmation process (see FIG. 66) described later.

Next, the main CPU 101 performs a thumb check process (non-standard) (S9). In this process, the main CPU 101 performs a thumb check process of the main RAM 103, and this process is performed in an unspecified work area (see FIG. 11C) in the main RAM 103. Further, the program used in this thumb check process is stored in the non-standard area in the main ROM 102 (see FIG. 11B). The details of the thumb check process will be described later with reference to FIGS. 72 and 73 described later.

After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S10).

In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, in S10, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S10 is NO), the main CPU 101 determines the thumb check based on the result of the thumb check process in S9. It is determined whether or not the result is normal (S11).

In S11, when the main CPU 101 determines that the thumb check determination result is not normal (when the determination in S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S11, when the main CPU 101 determines that the thumb check determination result is normal (when the determination in S11 is YES), the main CPU 101 performs the game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power failure detection. The details of the game return process will be described later with reference to FIG. 65, which will be described later.

When the determination in S5 or S11 is NO, the main CPU 101 displays the character string "88" indicating the occurrence of an error on the information display 6 (7-segment LED display) (S13). After that, the main CPU 101 repeats the WDT clearing process (S14).

Here, returning to the process of S10 again, if S10 is a YES determination, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation / storage process at the start of the setting change. The details of the setting change confirmation process will be described later with reference to FIG. 66 described later.

Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area for use. Then, after the processing of S16, the main CPU 101 starts the main processing described later (see FIG. 74 described later).

[Game return processing]
Next, with reference to FIG. 65, the game return processing performed in S12 during the power-on (reset interrupt) processing (see FIG. 64) will be described. Note that FIG. 65 is a flowchart showing the procedure of the game return process.

First, the main CPU 101 sets the stack pointer (SP) at the time of power failure (S21). Next, the main CPU 101 determines whether or not the command transmission start timer has counted up (S22). In S22, when the main CPU 101 determines that the command transmission start timer has not counted up (when the determination in S22 is NO), the main CPU 101 repeats the process of S22.

On the other hand, in S22, when the main CPU 101 determines that the command transmission start timer has counted up (when the determination in S22 is YES), the main CPU 101 has the on-edge data before the input port interrupt processing and the current Clear (off) the set on-edge data (S23). Next, the main CPU 101 reads the backup data of the output port from the output port backup storage area (not shown) of the main RAM 103, and sets the backup data in the output port (S24). Next, the main CPU 101 reads the data of the input port and stores the data in the data storage area (input port storage area 1 and input port storage area 2) of the input port at present and before the interrupt processing (S25). ..

Next, the main CPU 101 sets the address of the rotating cylinder control data storage area (S26). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S27).

Next, the main CPU 101 acquires reel control management information (data related to fluctuation control of the display column when a power failure occurs) of a predetermined reel based on the address of the set rotation cylinder control data storage area (S28). The reel control management information (variation control management information in the display column) is information related to the control state (rotation status) of each reel, and is backed up and saved in the event of a power failure.

Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation status during reel acceleration, constant speed waiting, or constant speed (S29).

In S29, when the main CPU 101 determines that the condition of S29 is not satisfied (when the determination in S29 is NO), the main CPU 101 performs the process of S32 described later. On the other hand, in S29, when the main CPU 101 determines that the condition of S29 is satisfied (YES in S29), the main CPU 101 clears the spinning control data (reel control management information) (S30). By this process, after returning to the game, the rotation control of the reel is started from the acceleration process. Next, the main CPU 101 sets the reel operation timing value (execution start timing “1” of the rotation cylinder control data) (S31). When "1" is set for the reel operation timing, the excitation change timing is set in the reel control process (see S903 in FIG. 114 described later), so that the main CPU 101 accelerates the reel rotation control. Start from.

After the processing of S31 or when the determination in S29 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S32). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S33).

In S33, when the main CPU 101 determines that the value of the number of reels after subtraction is not "0" (when the determination in S33 is NO), the main CPU 101 changes the reel to be checked and shifts the processing to the processing of S28. Return and repeat the processing after S28.

On the other hand, in S33, when the main CPU 101 determines that the value of the number of reels after subtraction is "0" (when the determination in S33 is YES), the main CPU 101 performs the RAM initialization process (S34). In this process, the main CPU 101 sets the address “at the time of power recovery” in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the final address of the game RAM area is set from the start address. Delete (clear) the information up to the address.

Next, the main CPU 101 restores the data of all the registers saved at the time of power failure detection to all the registers (S35). Then, after the process of S35, the main CPU 101 ends the game return process and returns the process to the process at the time of power failure detection.

In the present embodiment, the game return process is performed as described above. In the game return processing of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management is performed at the time of power recovery. The information is acquired and the processing necessary for starting the re-rotation of the reel is also performed (see the processing of S26 to S33). Therefore, in the present embodiment, the reel re-rotation control can be stably performed even when the reel is recovered from the electric power failure during the rotation of the cylinder, and the player is not discomforted.

[Setting change confirmation process]
Next, with reference to FIG. 66, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 64) will be described. FIG. 66 is a flowchart showing the procedure of the setting change confirmation process. If the setting key type switch 54 is turned on (that is, in the case of "setting confirmation" to confirm the current setting value) after the power of the gaming machine is turned on, this setting change confirmation is performed from S44 described later. The process may be started.

First, the main CPU 101 performs an initialization process of an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt wait process (S42). In this process, when the command transmission start timer is counting up, a non-operation command is transmitted to the sub-control circuit 200 by the communication data transmission process (see FIG. 115) described later. If the command transmission start timer does not count up, no command is transmitted to the sub-control circuit 200. Therefore, if the command transmission start timer does not count up, this process is omitted. You may.

Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area for use.

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for setting the setting value (settings 1 to 6) of the pachislot machine 1, and is set when the setting key is turned on. The key type switch 54 is turned on.

In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S44 is NO), the main CPU 101 ends the setting change confirmation process and turns on the power (reset interrupt). ) Move to the processing of S16 of the time processing (see FIG. 64). On the other hand, in S44, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 5) is not driven, and the inserted medals are ejected from the medal payout outlet 24 (see FIG. 2).

Next, the main CPU 101 sets the setting change start or setting confirmation start information (005H: first value) in the L register, and performs the generation and storage process of the setting change command (setting change / setting confirmation start) (S46). .. In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 67 described later. Further, the setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115.

Next, the main CPU 101 sets the error count relay to the ON state (S47). Next, the main CPU 101 performs a 7-segment display setting process of the set value (S48). By this process, the current set value can be displayed by the 7-segment LED in the information display 6.

Next, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S49). In S49, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S49 is NO), the main CPU 101 performs the process of S54 described later.

On the other hand, in S49, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S49 is YES), does the main CPU 101 have the reset switch 76 turned on? Whether or not it is determined (S50).

In S50, when the main CPU 101 determines that the reset switch 76 is in the ON state (when the determination in S50 is YES), the main CPU 101 updates the set value (S51). That is, each time the reset switch 76 is operated, the main CPU 101 sequentially updates the set value within the range of "1" to "6". After the processing of S51, the main CPU 101 returns the processing to the processing of S48, and repeats the processing after S48. On the other hand, in S50, when the main CPU 101 determines that the reset switch 76 is not in the ON state (when the determination in S50 is NO), the main CPU 101 determines whether or not the start switch 79 is in the ON state (S52). ..

When the main CPU 101 determines in S52 that the start switch 79 is not in the ON state (when the determination in S52 is NO), the main CPU 101 returns the process to the process in S48 and repeats the processes after S48. On the other hand, in S52, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S52 is YES), the main CPU 101 is set in the set value storage area (not shown) provided in the main RAM 103. Store the value (S53).

When the determination in S49 is NO or after the processing in S53, the main CPU 101 determines whether or not the setting key type switch 54 is in the off state (S54).

In S54, when the main CPU 101 determines that the setting key type switch 54 is not in the off state (when the determination in S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, in S54, when the main CPU 101 determines that the setting key type switch 54 is in the off state (when the determination in S54 is YES), the main CPU 101 determines whether the setting is changed or the setting is confirmed. (S55).

In S55, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, in S55, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S55 is YES), the main CPU 101 performs the RAM initialization process (S56). .. In this process, the main CPU 101 uses the address (the address next to the setting value storage area) of the main RAM 103 shown in FIG. 11C at the end of the setting change, which is not shown, as the start address of the initialization start. It is set and the information from the start address to the final address of the game RAM area is erased (cleared).

After processing S56 or when S55 determines NO, the main CPU 101 sets the setting change end or setting confirmation end information (004H: second value) in the L register, and sets the setting change command (setting change / setting confirmation end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 67 described later. Further, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 of the power-on (reset interrupt) processing (see FIG. 64).

[Setting change command generation and storage processing]
Next, with reference to FIG. 67, the setting change command generation / storage process performed in S46 and S58 during the setting change confirmation process (see FIG. 66) will be described. Note that FIG. 67 is a flowchart showing the procedure for generating and storing the setting change command.

First, the main CPU 101 sets the information of the set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets the RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

Next, the main CPU 101 performs a communication data storage process (S64). In this process, the main CPU 101 has the information set in each register in S61 to S63 and the information set in the L register in S46 or S58 (see FIG. 66) (setting change start / setting change end / setting status). Setting change command data is generated by using (setting confirmation start / setting confirmation end), and the generated command data is saved in the communication data storage area. The details of the communication data storage process will be described later with reference to FIG. 68 described later.

After the process of S64, the main CPU 101 ends the setting change command generation and storage process. When the setting change command generation and storage process performed in S46 during the setting change confirmation process (see FIG. 66) is terminated, the main CPU 101 performs the process after the process of S64 in the setting change confirmation process (see FIG. 68). Move to the process of S47. Further, when ending the setting change command generation and storage process performed in S58 during the setting change confirmation process (see FIG. 66), the main CPU 101 ends the setting change command generation and storage process after the process of S64, and also sets the settings. The change confirmation process (see FIG. 66) is also completed.

[Communication data storage process]
Next, with reference to FIG. 68, for example, the communication data storage process performed in S64 during the setting change command generation / storage process (see FIG. 67) will be described. The communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 68 is a flowchart showing the procedure of the communication data storage process.

First, the main CPU 101 stores the data set in the A register as communication command type data in the communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area in the main RAM 103 as parameters 1 and 2 of the communication command, respectively (S72).

Next, the main CPU 101 stores the data set in the D register and the E register as the parameters 3 and 4 of the communication command in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register as the data of the parameter 5 of the communication command and the RT state, respectively, in the communication data temporary storage area in the main RAM 103 (S74).

Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

After the processing of S76, the main CPU 101 determines whether or not there is a vacancy in the communication data storage area in the main RAM 103 (S77). In this embodiment, a maximum of nine command data can be stored in the communication data storage area.

In S77, when the main CPU 101 determines that there is no free space in the communication data storage area (when the determination in S77 is NO), the main CPU 101 ends the communication data storage process and, for example, sets change command generation and storage process (when the communication data storage area is determined to be NO). (See FIG. 68) also ends.

On the other hand, in S77, when the main CPU 101 determines that there is a vacancy in the communication data storage area (when the determination in S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the above-mentioned processes S71 to S76. Each of the data is stored (registered) in the communication data storage area as communication data (command data) (S78).

Next, the main CPU 101 performs the communication data pointer update process (S79). In this process, the main CPU 101 mainly updates the communication data pointer indicating the storage address of the communication data in the communication data storage area. The details of the communication data pointer update process will be described later with reference to FIG. 69 described later.

Then, after the process of S79, the main CPU 101 ends the communication data storage process and, for example, the setting change command generation and storage process (see FIG. 67).

As described above, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a command data creation method, the data stored in each register at the time of command generation is stored as it is in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including unused parameters is created, the value of the unused parameters becomes an indefinite value each time it is created. This makes it difficult to analyze communication data and suppresses fraudulent acts such as goto, and since it is not necessary to add unnecessary goto countermeasure processing, the program of the main control circuit 90 by adding the goto countermeasure processing. The pressure on the capacity can be suppressed.

[Communication data pointer update process]
Next, with reference to FIG. 69, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 68) will be described. Note that FIG. 69 is a flowchart showing the procedure of the communication data pointer update process.

First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

Next, the main CPU 101 adds and updates the value of the communication data pointer by one packet (8 bytes) (S82). In this process, when the value of the updated communication data pointer is equal to or greater than the upper limit size of the communication data storage area, the main CPU 101 sets the updated communication data pointer value to "0". This invalidates all the command data stored in the communication data storage area (makes it the same state as the discarded state).

In the present embodiment, the amount of data (1 packet) transmitted in one transmission operation is 8 bytes. That is, in the present embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of nine command data can be stored in the communication data storage area, the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). Therefore, in the present embodiment, the range of the communication data pointer is set to "0" to "71", and in the process of S82, the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is "71 (when the communication data pointer is updated by +8). If the value exceeds "upper limit value)", set the updated communication data pointer value to "0" (return the communication data storage destination address to the start address) and store the communication data. Disable all command data stored in the area (make it the same as the discarded state). If the value of the communication data pointer is set to "0", the next time the command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area, so it is stored before that. The command data will be overwritten with new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds "71 (upper limit value)".

Then, after the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 68).

[Processing at the time of power failure (external)]
Next, the power failure (external) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIG. 70. FIG. 70 is a flowchart showing a procedure of (external) processing at the time of power failure. In the power interruption (external) process shown in FIG. 70, when the power supply management circuit 93 detects a decrease in the power supply voltage (power interruption) supplied to the microprocessor 91, the power interruption detection signal is transmitted to the microprocessor 91. Is output to the "XINT" terminal of the above, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads the data set in the power failure detection port (S92).

Next, the main CPU 101 determines whether or not the power failure detection port is in the ON state (S93).

In S93, when the main CPU 101 determines that the power interruption detection port is not in the ON state (when the determination in S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 ends the (external) processing at the time of power failure. It should be noted that these processes performed when S93 is a NO determination correspond to the process of countermeasures against momentary power failure that occurs when the power supply management circuit 93 momentarily detects a power failure or the like.

On the other hand, in S93, when the main CPU 101 determines that the power failure detection port is in the ON state (when the determination in S93 is YES), the main CPU 101 sets that the medal cannot be inserted and sets the stop of the hopper device 51. (S95).

Next, the main CPU 101 saves the currently set value of the stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

Next, the main CPU 101 performs a checksum generation process of the main RAM 103 (S97). This process is performed in the non-standard work area (see FIG. 11C) in the main RAM 103. Further, the program used in this checksum generation process is stored in the non-standard area in the main ROM 102 (see FIG. 11B). The details of the checksum generation process will be described later with reference to FIG. 71, which will be described later.

Next, the main CPU 101 sets access prohibition to the main RAM 103 (S98). Then, after the processing of S98, the infinite loop processing is performed until the power supply is stopped (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation process (non-standard)]
Next, with reference to FIG. 71, the checksum generation process performed in S97 during the power failure (external) process (see FIG. 70) will be described. Note that FIG. 71 is a flowchart showing the procedure of the checksum generation process.

First, the main CPU 101 saves the current stack pointer (SP) value (the address in use of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets the address value (F0H) on the upper side of the RAM address (address of the non-standard stack area) in the Q register (S103). Next, the main CPU 101 sets the power failure occurrence flag (S104).

Next, the main CPU 101 sets the stack pointer with the calculation start address of the sum value in the game RAM area, and sets the sum calculation counter with the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2". Set (S105). The sum calculation counter is a counter for determining the end trigger of the sum value calculation, and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation process of the game RAM area of the main RAM 103 is terminated.

Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value "0" of the sum value is set.

Next, the main CPU 101 executes an instruction code called a "POP instruction" and stores data (stored value) in an area of 2 bytes from the address of the storage area of the main RAM 103 set in the stack pointer (SP) in the DE register. Read (S107).

When the "POP" instruction is executed, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address where the updated address is updated by 1 is loaded into the register on the upper side of the pair register. When the "POP" instruction is executed, an address update process for 2 bytes (a process of adding "2" to the address) is performed on the address set in the stack pointer (SP).

Therefore, in the processing of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and saved at the address specified by the stack pointer plus "1". The data (memory contents) is loaded into the D register.

After the process of S107, the main CPU 101 performs a process of calculating the sum value (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S110).

In S110, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

On the other hand, in S110, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S110 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standard sum count value is the number of bytes in the non-standard storage area. Therefore, when the sum calculation counter set in S111 becomes "0", the sum value calculation process of the non-standard RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 is completed.

Next, the main CPU 101 reads the data (stored value) of one byte from the address of the non-standard RAM area set in the DE register into the A register (S112).

Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S115).

In S115, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S115 is NO), the main CPU 101 returns the processing to the processing in S112 and repeats the processing after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the non-standard RAM area of the main RAM 103 to the sum value of the gaming RAM area is completed.

On the other hand, in S115, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S115 is YES), the main CPU 101 sets the value stored in the HL register when a power failure occurs. As the sum value of, it is stored in the sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S101 in the stack pointer (S117). Then, after the processing of S117, the main CPU 101 ends the checksum generation processing, and shifts the processing to the processing of S98 at the time of power failure (external) processing (see FIG. 70).

[Sum check processing (non-standard)]
Next, the thumb check process performed in S9 during the power-on processing (see FIG. 64) will be described with reference to FIGS. 72 and 73. 72 and 73 are flowcharts showing the procedure of the thumb check process.

First, the main CPU 101 saves the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2" in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end trigger of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power failure occurs is stored in the HL register.

Next, the main CPU 101 executes the "POP" instruction and reads the data (stored value) of the area of 2 bytes from the address of the storage area of the main RAM 103 set in the stack pointer (SP) into the DE register (S124). .. At this time, by executing the "POP" instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is used. 1 The data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register. Further, when the "POP" instruction is executed, an address update process for 2 bytes (a process of adding 2 addresses) is performed on the address set in the stack pointer (SP).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (initial value of the sum value or the sum value after the previous subtraction process), and the subtraction is performed. The value is stored in the HL register as a sum value.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S127).

In S127, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S127 is NO), the main CPU 101 returns the process to the process of S124, and repeats the processes after S124. That is, the processes of S124 to S127 are repeated until the subtraction process of the sum value is completed over the entire area of the game RAM area of the main RAM 103.

On the other hand, in S127, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S127 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard sum count value is the number of bytes in the non-standard RAM area.

Next, the main CPU 101 reads the data (stored value) of one byte of the area from the address of the non-standard RAM area set in the DE register into the A register (S129).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S132).

In S132, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S132 is NO), the main CPU 101 returns the processing to the processing of S129, and repeats the processing after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire area of the non-standard RAM area of the main RAM 103.

On the other hand, in S132, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S132 is YES), the main CPU 101 sets "sum error" in the determination result of the thumb check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value becomes "0" when the value of the sum calculation counter set in S128 becomes "0", that is, when the subtraction process of the sum value is completed over the entire area of the main RAM 103. If, the zero flag in the flag register F is set to "1", and if the sum value is not "0", the zero flag in the flag register F is set to "0". Therefore, if "1 (on state)" is set in the zero flag of the flag register F at the time of processing S134, the main CPU 101 determines that the sum value is "0".

In S134, when the main CPU 101 determines that the calculated sum value is not "0" (when the determination in S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, in S134, when the main CPU 101 determines that the calculated sum value is "0" (when the determination in S134 is YES), the main CPU 101 sets "power failure" in the determination result (S135). ).

Next, the main CPU 101 acquires the power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power failure generation flag is in the state without power failure (off state) (S137).

In S137, when the main CPU 101 determines that the power interruption occurrence flag is in the state of no power interruption (when the determination in S137 is YES), the main CPU 101 performs the process of S139 described later. On the other hand, in S137, when the main CPU 101 determines that the power interruption occurrence flag is not in the state without power interruption (when the determination in S137 is NO), the main CPU 101 sets "normal" in the determination result (S138).

After the processing of S138, if S134 is a NO determination or S137 is a YES determination, the main CPU 101 saves the determination result in the thumb check determination result and clears (offs) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S121 to the stack pointer (S140). Then, after the processing of S140, the main CPU 101 ends the thumb check processing, and shifts the processing to the processing of S10 of the power-on processing (see FIG. 64).

[Main processing of pachislot under the control of the main CPU]
Next, with reference to FIG. 74, the main processing (main operation processing) of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described. Note that FIG. 74 is a flowchart (hereinafter referred to as a main flow) showing the procedure of the main process.

First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address of "at the end of one game" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and from the start address to the game RAM area. Delete (clear) the information up to the final address. The storage area in this range is, for example, a storage area in which data needs to be erased for each unit game (game) such as an internal winning combination storage area and a display combination storage area.

Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this process, the main CPU 101 performs an input check process for each medal sensor (see FIG. 5), a start switch 79, and the like. The details of the medal reception / start check process will be described later with reference to FIGS. 75 and 76 described later.

Next, the main CPU 101 performs a random number acquisition process (S203). In this process, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: a value of the random number register 0 of the random number circuit 110 that becomes a hard latch random number) and a random number value for production used in various ART-related lottery (0 to 65535). 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 to be a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 to be a soft latch random number), etc. The extracted various random number values are stored in a random number value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 81 described later.

Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs a process of determining the internal winning combination by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 82 described later.

Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. And so on. The details of the symbol setting process will be described later with reference to FIG. 83, which will be described later.

Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates start command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. The start command is configured to include parameters (sub-flags, etc.) that specify the internal winning combination and the like.

Next, the main CPU 101 performs the second interface board control process (S207). The second interface board control process is executed in the non-standard work area of the main RAM 103. In this process, the main CPU 101 performs a process for outputting, for example, a test signal related to the push order navigation determined by the main control board 71 via the second interface board 302 for the testing machine.

Next, the main CPU 101 performs a state-specific control process (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-specific control processing will be described later with reference to FIG. 85 described later.

Next, the main CPU 101 performs a reel stop initial setting process (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (see FIG. 26), and sets the pull-in priority table selection table number, the pull-in priority table number, and the stop table number based on the internal winning combination and the game state. The process of acquiring, the process of storing "3" in the stop button non-operation counter, and the like are performed.

Next, the main CPU 101 performs a reel rotation start process (S210). In this process, the main CPU 101 requests the start of rotation of all reels. Then, when the start of rotation of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 158 described later) executed at a constant cycle (1.1172 msec). Controlled, the rotation of the left reel 3L, the middle reel 3C and the right reel 3R is started. Each reel is then accelerated and controlled until its rotational speed reaches a constant speed, after which it is controlled to maintain that constant speed.

Next, the main CPU 101 performs a reel rotation start command generation / storage process (S211). In this process, the main CPU 101 generates data for a reel rotation start command to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. The reel rotation start command is configured to include a parameter indicating that the reel rotation start operation has been started.

Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the attraction priority data and stores it in the attraction priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 100 described later.

Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 controls the rotation stop of the corresponding reel based on the timing at which the left stop button 17L, the middle stop button 17C, and the right stop button 17R are pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 105 described later.

Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 35) in the winning operation flag storage area (see FIGS. 28 to 30). Further, in this process, the main CPU 101 determines whether or not the display combination is displayed on the effective line, and sets the number of medals to be paid out based on the determination result. The details of the winning search process will be described later with reference to FIG. 106 described later.

Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 synthesizes a hit request flag (internal winning combination) and a winning operation flag (display combination), and determines whether or not there is an illegal hit error based on the combination result. The details of the illegal hit check process will be described later with reference to FIG. 107 described later.

Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a process of generating a winning operation command. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of payouts of the display combination determined in S214, and performs the medal payout process. The details of the winning check / medal payout process will be described later with reference to FIG. 108 described later.

Next, the main CPU 101 performs a BB check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. The details of the BB check process will be described later with reference to FIG. 110 described later.

Next, the main CPU 101 performs an RT check process (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination stopped and displayed on the effective line. The details of the RT check process will be described later with reference to FIGS. 111 and 112 described later.

Next, the main CPU 101 performs CZ / ART end processing (S219). In this process, the main CPU 101 mainly performs a CZ pullback lottery process. The details of the processing at the end of CZ / ART will be described later with reference to FIG. 113 described later. Then, after the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal reception / start check processing]
Next, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 74) will be described with reference to FIGS. 75 and 76. 75 and 76 are flowcharts showing the procedure of medal reception / start check processing.

First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is "0" (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is "1" or more, the main CPU 101 determines that there is an automatic insertion request. Further, the automatic insertion medal counter is data for identifying whether or not the display combination related to the replay is established in the previous unit game. When the display combination related to the re-game is established, the number of medals inserted in the previous unit game is automatically inserted into the automatic insertion medal counter.

In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when the determination in S221 is YES), the main CPU 101 performs the process of S225 described later.

On the other hand, in S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S221 is NO), the main CPU 101 performs the medal insertion process (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, an LED lighting control process for the number of medals inserted, and the like. The details of the medal insertion process will be described later with reference to FIG. 77 described later.

Next, the main CPU 101 subtracts the value of the automatic insertion medal counter (S223). In this process, the main CPU 101 may subtract the value of the automatic insertion medal counter at a time (for example, "3") or may subtract "1" at a time. Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is "0" (S224).

In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S224 is NO), the main CPU 101 returns the process to the process of S222 and repeats the processes after S222.

On the other hand, in S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when S224 is a YES determination), or when S221 is a YES determination, the main CPU 101 is used for medal auxiliary storage. The storage switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not the medal can be inserted based on the result of the medal insertion state check process (S227).

When the main CPU 101 determines in S227 that the medal cannot be inserted (when the determination in S227 is NO), the main CPU 101 performs the process of S231 described later.

On the other hand, in S227, when the main CPU 101 determines that the medal insertion is possible (when the determination in S227 is YES), the main CPU 101 performs the medal insertion check process (S228). In this process, the main CPU 101 credits the medal, for example, based on the medal sensor input state, a process of determining whether or not the medal has passed normally, and when the number of medals inserted exceeds a specified number. Perform processing and so on. The details of the medal insertion check process will be described later with reference to FIGS. 78 and 79 described later.

Next, the main CPU 101 determines whether or not the medal insertion or credit is possible based on the result of the medal insertion check process (S229).

When the main CPU 101 determines in S229 that the medal can be inserted or credited (when the determination in S229 is YES), the main CPU 101 performs the process of S231 described later. On the other hand, in S229, when the main CPU 101 determines that the medal cannot be inserted or credited (when the determination in S229 is NO), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 5) is not driven (the solenoid that has been excited is demagnetized), and the select plate 804 shifts from the guide position to the discharge position, so that the inserted medal is released. It will be discharged from the medal payout outlet 24.

After the processing of S230, if S227 is a NO determination or S229 is a YES determination, the main CPU 101 determines whether or not the current number of inserted medals is the playable start number (S231). In this embodiment, the number of games that can be started is three (see FIGS. 28 to 30).

In S231, when the main CPU 101 determines that the current number of inserted medals is the number of playable start numbers (when the determination in S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, in S231, when the main CPU 101 determines that the current number of inserted medals is not the playable start number (when the determination in S231 is NO), the main CPU 101 determines whether or not there is a medal inserted (S232). ).

In S232, when the main CPU 101 determines that a medal has been inserted (when the determination in S232 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226. On the other hand, in S232, when the main CPU 101 determines that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described with reference to FIG. 66 (S233). In this process, the main CPU 101 performs a setting change command generation / storage process at the start of setting confirmation. This makes it possible to check the set values and hall menus (various history data (errors, power failure history, etc.)) regardless of whether the game state is a bonus state (special prize operating state). Cheating can be suppressed. In the setting change confirmation process performed in S233, even if the setting key type switch 54 is in the off state, a setting change command (setting confirmation start) including at least information on the current setting value is generated and stored. Therefore, the command data may be stored in the communication data storage area provided in the main RAM 103. Thereby, it may be possible to check whether or not the set value is appropriate (whether or not it is within the range of settings 1 to 6) for each game.

After the processing of S233 or when the determination in S231 is YES, the main CPU 101 determines whether or not the start switch 79 is in the ON state (S234).

When the main CPU 101 determines in S234 that the start switch 79 is not in the ON state (when the determination in S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

On the other hand, in S234, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 5) is not driven (the solenoid that has been excited is demagnetized), and the select plate 804 shifts from the guide position to the discharge position, so that the inserted medal is released. It will be discharged from the medal payout outlet 24.

Next, the main CPU 101 sets a timer value (“72” in this embodiment) in the medal monitoring timer (S236). The medal monitoring timer is a timer for monitoring the period until the excited solenoid is degaussed (that is, the period until the select plate 804 moves from the guide position to the ejection position) in the selector 66. (See FIG. 121 described later), for example, when the period until the excited solenoid completes degaussing is 80 ms, a timer value for measuring at least a longer period (“about 80.44 ms”). Is set. That is, the medal monitoring timer actually operates after the start lever 16 is operated (the start switch 79 is turned on) and the control for prohibiting medal acceptance is started when the number of medals that can be played is inserted. Monitor a specific period of time before the acceptance of medals is (physically) banned. As a result, when a medal is inserted in the specific period in combination with the start lever ON flag described later, the medal insertion check 2 process described later, etc., the medal is accidentally swallowed (that is, the medal is inserted). However, it is prevented from being housed in the hopper device 51 without being counted). The value of the medal monitoring timer can be appropriately changed according to the specifications of the selector 66 (mainly the solenoid). Further, as long as it is guaranteed to prevent the medal from being swallowed, the period until the excited solenoid is completely degaussed can be set to a period shorter than the period until the demagnetization is completed.

Next, the main CPU 101 sets the start lever ON flag to the ON state (S237). The start lever ON flag is information for identifying whether or not the start lever 16 has been operated (the start switch 79 has been turned on) when the number of medals that can be played has been inserted. ..

Next, the main CPU 101 performs the medal insertion check 2 process (S238). In this process, the main CPU 101 basically performs the same process as the medal insertion check process. The details of the medal insertion check process and the medal insertion check 2 process will be described later with reference to FIGS. 78 and 79 described later.

Next, the main CPU 101 determines whether or not the start lever ON flag is in the OFF state (S239). In S239, when the main CPU 101 determines that the start lever ON flag is in the OFF state (when the determination in S239 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226.

On the other hand, in S239, when the main CPU 101 determines that the start lever ON flag is not in the off state (that is, is in the ON state) (when the determination in S239 is NO), the main CPU 101 sets the medal monitoring timer to "0". It is determined whether or not there is (S240). In S239, when the main CPU 101 determines that the medal monitoring timer is not "0" (that is, "1" or more) (when the determination in S240 is NO), the main CPU 101 returns the process to S238, and after S238. Repeat the process of.

On the other hand, in S240, when the main CPU 101 determines that the medal monitoring timer is "0" (when the determination in S240 is YES), the main CPU 101 ends the medal acceptance / start check process and performs the process in the main flow (when the medal monitoring timer is determined to be YES). (See FIG. 74).

[Medal insertion process]
Next, referring to FIG. 77, the medal insertion performed in S222 during the medal acceptance / start check process (see FIGS. 75 and 76) and S265 during the medal insertion check process (see FIGS. 78 and 79) described later. The processing will be described. Note that FIG. 77 is a flowchart showing the procedure of the medal insertion process.

First, the main CPU 101 adds "1" to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

Next, the main CPU 101 performs a medal insertion command generation / storage process (S242). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command is configured to include parameters for specifying the number of inserted medals and the like.

Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 6) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the number of inserted medals based on the number of inserted medals (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, the LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and for example, when the number of inserted medals is three. LED lighting data for lighting all of the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

Next, the main CPU 101 uses the calculated LED lighting data to light the corresponding LED for displaying the number of inserted medals (S245). Then, after the process of S245, the main CPU 101 ends the medal insertion process, and performs the process in S223 of the medal acceptance / start check process (see FIGS. 75 and 76) or the medal insertion check process (FIGS. 78 and 79) described later. (See) to S253.

[Medal insertion check process]
Next, with reference to FIGS. 78 and 79, the medal insertion check process and the medal acceptance / start check process (FIGS. 75 and 76) performed in S228 during the medal acceptance / start check process (see FIGS. 75 and 76). The medal insertion check 2 process performed in S238 in (see) will be described. 78 and 79 are flowcharts showing the procedure of the medal insertion check process. The medal insertion check 2 process starts from S253 of the medal insertion check process, and the processes of S253 to S268 are the same as those in the medal insertion check process. The procedure of the input check process will be described.

First, the main CPU 101 determines whether or not the game is being replayed (S251).

When the main CPU 101 determines in S251 that the replay is in progress (when the determination in S251 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (FIGS. 75 and FIG. Move to S229 of (see 76).

On the other hand, in S251, when the main CPU 101 determines that the replay is not in progress (when the determination in S251 is NO), the main CPU 101 permits medal acceptance (S252). In this process, the solenoid of the selector 66 (see FIG. 5) is driven (the solenoid that has been degaussed is excited), and the select plate 804 shifts from the ejection position to the guide position, so that the medal is inserted from the medal insertion slot 14. The medals that have been won are counted and accommodated in the hopper device 51.

Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1-bet button 15b) has been operated based on the ON / OFF state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the betting button check processing in S253 (S254).

In S254, when the main CPU 101 determines that the betting operation is completed (when the determination in S254 is YES), the main CPU 101 ends the medal insertion check process (or the medal insertion check 2 process), and accepts the medal. The process proceeds to S229 of the start check process (see FIGS. 75 and 76) (or S239 of the medal reception / start check process (see FIGS. 75 and 76)).

On the other hand, in S254, when the main CPU 101 determines that the betting operation has not been completed (when the determination in S254 is NO), the main CPU 101 determines that the medal sensor input state (game medium reception state) at the time of the current processing. Acquires the medal sensor input state at the time of the previous processing (S255). The medal sensor input state is information indicating the passing status of the medal received in the medal insertion slot 14 in the selector 66, and is generated based on the detection result of each medal sensor (see FIG. 5) of the selector 66.

In the present embodiment, the medal sensor input state is represented by 1-byte (8-bit) data, and the detection result of the first medal sensor 806 on the upstream side provided at the exit of the selector 66 in the direction of passing the medal is obtained. It corresponds to the information of bit 0 (“0” or “1”), and the detection result of the second medal sensor 807 on the downstream side corresponds to the information of bit 1 (“0” or “1”). When the passage of the medal is detected by the first medal sensor, "1" is set in bit 0, and when the passage of the medal is detected by the second medal sensor, "1" is set in bit 1. Will be done. Therefore, the medal sensor input state "0000000000B" indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state "00000001B" indicates the state at the start of passing the medal, and the medal sensor input state "0000000000B". "00000011B" indicates a state in which the medal is passing, and "00000010B" in the medal sensor input state indicates a state immediately before the completion of passing the medal.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (S256).

In S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has not changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is NO), the main CPU 101 is described in S262, which will be described later. Perform processing.

On the other hand, in S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is YES), the main CPU 101 sets the start lever ON flag. If is on, the start lever ON flag is set to the off state (S257). That is, in this process, the main CPU 101 inserts medals in a specific period from when the start operation is performed and the control for prohibiting medal acceptance is started until the medal acceptance is actually (physically) prohibited. When it is detected, a process of invalidating the start operation is performed.

Next, the main CPU 101 generates a normal value (normal change value) of the medal sensor input state obtained at the time of the current processing by arithmetic processing based on the medal sensor input state at the time of the previous processing (S258).

In this process, when the medal sensor input state at the time of the previous process is "00000000000B" (when both the first and second medal sensors have not detected medals), it is regarded as a normal change value of the medal sensor input state. When "00000001B" (when the first medal sensor detects medals and the second medal sensor does not detect medals) is generated and the medal sensor input state at the time of the previous processing is "00000001B", the medal sensor "00000011B" (when both the first and second medal sensors are medal detection) is generated as a normal change value of the input state. Further, in this process, when the medal sensor input state at the time of the previous process is "00000011B", the normal change value of the medal sensor input state is "00000010B" (the first medal sensor has not detected a medal, and the second (When the medal sensor is medal detection) is generated, and when the medal sensor input state at the time of the previous processing is "00000010B", the normal change value of the medal sensor input state is "0000000000B" (first and second medals). If both sensors do not detect medals) is generated.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing is the same as the normal change value generated in S258 (S259). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition of S259 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S258 (when the determination in S259 is NO), the main CPU 101 performs the processing of S263 described later. conduct.

On the other hand, in S259, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is the same as the normal change value generated in S258 (when the determination in S259 is YES), the main CPU 101 is at the time of the current processing. It is determined whether or not the medal sensor input state of the above is the state at the time of passing the medal (“00000000B”) (S260). In S260, when the main CPU 101 determines that the medal sensor input state at the time of the current process is the state at the time of passing the medal (when the determination in S260 is YES), the main CPU 101 performs the process of S264 described later.

In S260, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the state at the time of passing the medal (when the determination in S260 is NO), the main CPU 101 sets the medal passing check timer (S261). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to, for example, the medal sensor input state at the time of the current process.

After the processing of S261 or when the determination of S256 is NO, the main CPU 101 indicates whether the medal sensor input state at the time of the current processing is the medal passing state (“000000111B”) and the medal passing check timer is stopped. (S262). In this determination process, it is determined whether or not a medal passing error (inserted medal passing time error) has occurred, and if the determination condition of S262 is satisfied, the main CPU 101 determines that a medal passing error has occurred.

In S262, when the main CPU 101 determines that the determination condition of S262 is not satisfied (when the determination in S262 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

On the other hand, in S262, when the main CPU 101 determines that the determination condition of S262 is satisfied (when S262 is a YES determination), or when S259 is a NO determination, that is, a medal passing error or a medal retrograde error has occurred. If it is determined, the main CPU 101 performs error processing (S263). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process. The details of error handling will be described later with reference to FIG. 80 described later. Then, after the processing of S263, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

Here, returning to the process of S260 again, if S260 is determined to be YES, the main CPU 101 determines whether or not a specified number of medals (three medals in this embodiment) have already been inserted (S264). ..

In S264, when the main CPU 101 determines that the specified number of medals have not been inserted (NO in S264), the main CPU 101 performs the medal insertion process described with reference to FIG. 77 (S265). Then, after the processing of S265, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

On the other hand, in S264, when the main CPU 101 determines that a specified number of medals have already been inserted (when the determination in S264 is YES), the main CPU 101 adds "1" to the value of the credit counter (S266). ). Next, the main CPU 101 performs a medal insertion command generation and storage process (S267). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115.

Next, the main CPU 101 determines whether or not the number of credits of the medal is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S268).

In S268, when the main CPU 101 determines that the number of credits for medals is not the upper limit value (when the determination in S268 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, in S268, when the main CPU 101 determines that the number of credits for medals is the upper limit value (when the determination in S268 is YES), the main CPU 101 ends the medal insertion check process (or medal insertion check 2 process). , The process is transferred to S229 of the medal reception / start check process (see FIGS. 75 and 76) (or S239 of the medal reception / start check process (see FIGS. 75 and 76)).

[Error handling]
Next, with reference to FIG. 80, for example, the error processing performed in S263 during the medal insertion check processing (see FIG. 78) will be described. FIG. 80 is a flowchart showing a procedure for error handling.

First, the main CPU 101 turns off the medal solenoid (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 5). Next, the main CPU 101 saves the medal payout number display data (S272). Next, the main CPU 101 performs an error table setting process (S273).

Next, the main CPU 101 acquires an error factor (S274). The error factor acquired in this process changes according to the process in which the error process currently being processed is read. The error factors targeted in this embodiment include "hopper empty error", "hopper jam error", "inserted medal passing count error", "inserted medal passing check error", and "inserted medal passing check error". "Insert medal passing time error", "Insert medal retrograde error", "Insert medal auxiliary storage full error", "Illegal hit error" are specified. For example, when the error process is read after the process of S259 during the medal insertion check process, the "inserted medal retrograde error (Cr)" is acquired as an error factor in this process. Further, for example, when the error process is read after the process of S262 during the medal insertion check process, the "inserted medal passing time error (CE)" is acquired as an error factor in this process.

Next, the main CPU 101 acquires error display data from the error table and the error cause (S275). For example, when the error factor is "insertion medal retrograde error (Cr)", the 1-byte data "001001110B" is used as the error display data to be output to the upper digit 7-segment LED among the 2-digit 7-segment LEDs in this process. Is acquired, and 1-byte data “000001001B” is acquired as error display data to be output to the lower digit 7-segment LED. In this case, the two characters "Cr" are displayed as error information on the two-digit 7-segment LED.

Next, the main CPU 101 performs an error command (generation) generation and storage process (S276). In this process, the main CPU 101 generates data of an error command when an error occurs, which is transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The error command when an error occurs stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. The error command when an error occurs includes a parameter indicating the occurrence of an error.

Next, the main CPU 101 performs a standby process for an interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been cleared (S278).

When the main CPU 101 determines in S278 that the error has not been cleared (when the determination in S278 is NO), the main CPU 101 returns the process to the process in S277 and repeats the processes after S277.

On the other hand, in S278, when the main CPU 101 determines that the error has been cleared (when the determination in S278 is YES), the main CPU 101 performs the error factor clearing process (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a restoration process of the payout number display data of the medals saved in S272 (S280).

Next, the main CPU 101 performs an error command (release) generation and storage process (S281). In this process, the main CPU 101 generates data of an error command at the time of error cancellation to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. The error command at the time of error cancellation includes a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and shifts the processing to, for example, S253 during the medal insertion check processing (see FIG. 78). In the error release, the cause of the error is released, and the error state is released by pressing the reset switch 76.

[Random number acquisition process]
Next, with reference to FIG. 81, the random number acquisition process performed in S203 in the main flow (see FIG. 74) will be described. Note that FIG. 81 is a flowchart showing the procedure of the random number acquisition process.

First, the main CPU 101 acquires a hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for internal winning combination lottery, and uses a random number value storage area (non-standard) in the main RAM 103. It is stored in (shown) (S291).

Next, the main CPU 101 generates soft latch random numbers (0 to 65535: random numbers for production used in ART-related lottery processing, random numbers in 0 to 255: 1-byte lottery processing) of random number registers 1 to 7 of the random number circuit. The soft latch random number acquisition register is set for this purpose (S292). Next, the main CPU 101 sets the acquisition number (for example, 7) of the soft latch random numbers (S293).

Next, the main CPU 101 collectively acquires the number of acquired soft latch random numbers, and stores the acquired number of soft latch random numbers in the random number value storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random number value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random number value storage area. It is stored in an area different from the area in which the latch random number (random number value for the internal winning combination lottery) is stored. Then, after the processing of S294, the main CPU 101 ends the random number acquisition processing, and shifts the processing to S204 of the main flow (see FIG. 74). In the present embodiment, in order to store four 2-byte random numbers and four 1-byte random numbers, a 12-byte storage area is allocated to the main RAM 103 as a random number storage area.

[Internal lottery processing]
Next, with reference to FIG. 82, the internal lottery process performed in S204 in the main flow (see FIG. 74) will be described. Note that FIG. 82 is a flowchart showing the procedure of the internal lottery process.

First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 checks the set value (any of 1 to 6) of the current game and the number of inserted medals (3 in the present embodiment).

Next, the main CPU 101 sets the internal lottery table for general games (see the internal lottery table in the “RT0” state shown in FIG. 16) and the number of lottery (53 times in the present embodiment) (S302).

Next, the main CPU 101 determines whether or not the RB is in operation (S303). When the main CPU 101 determines in S303 that the RB is not in operation (when the determination in S303 is NO), the main CPU 101 performs the process of S305 described later.

On the other hand, when the main CPU 101 determines in S303 that the RB is in operation (when the determination in S303 is YES), the main CPU 101 has an internal lottery table for RB (see the internal lottery table shown in FIG. 17B) and The number of lottery (5 times in this embodiment) is set (S304). In this process, the internal lottery table and the number of lottery for general games set in S302 are overwritten by the internal lottery table and the number of lottery for RB.

After the processing of S304 or when the determination in S303 is NO, the main CPU 101 acquires the determination data (data related to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

Next, the main CPU 101 determines whether or not the determination data is RT state-specific data (S306). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the RT state. Specifically, the main CPU 101 determines whether or not the address defined in the currently acquired lottery target combination determination data is an address in the lottery value selection table (not shown) for each RT state. ..

In S306, when the main CPU 101 determines that the determination data is not the RT state-specific data (when the determination in S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, in S306, when the main CPU 101 determines that the determination data is the data for each RT state (when the determination in S306 is YES), the main CPU 101 selects data from the RT state lottery value selection table based on the determination data. Is acquired, and the acquired selection data is set in the determination data (S307).

After the processing of S307 or when the determination in S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is the data for each setting (S308). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the set value. Specifically, the main CPU 101 determines whether or not the address defined in the currently acquired lottery target combination determination data is an address in the internal lottery value table (not shown) for each setting.

In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when the determination in S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, in S308, when the main CPU 101 determines that the determination data is the data for each setting (when the determination in S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is the data associated with the set value, but the set value data "0" to "5" are not the values of the set value itself, but are "0" to "5", respectively. It is the data corresponding to "setting 1" to "setting 6".

After the processing of S309 or when the determination in S308 is NO, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target combination is stored based on the set determination data (address data), and sets the address to the address. The stored lottery value is acquired (S310).

For example, in the case of an internal winning combination whose lottery value changes according to both the RT state and the set value, the lottery value is referred to both the RT state lottery value selection table and the internal lottery value table for each setting. Is obtained.

Next, the main CPU 101 acquires a random number value (any of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

Next, the main CPU 101 performs a lottery execution process (S312). In this process, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as the lottery result (winning / non-winning of the lottery target combination). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (overflow), it is determined that the lottery target combination has been won (the lottery target combination has been determined as the internal winning combination). NS.

Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after the lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not the lottery execution process has won (whether or not an overflow has occurred) (S314).

In S314, when the main CPU 101 determines that the winning is won in the lottery execution process (when the determination in S314 is YES), the main CPU 101 refers to the internal lottery table and refers to the winning request flag status corresponding to the winning internal winning combination (the winning request flag status (when the determination is YES in S314). For example, the special prize winning number (that is, information that can identify the type of the winning bonus combination) and the small winning combination winning number (that is, the winning small winning combination or replay combination) corresponding to "No." in FIGS. 16 and 17. The value of (information that can identify the type)) is acquired (S315). Then, after the processing of S315, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 74).

On the other hand, in S314, when the main CPU 101 determines that the lottery has not been won in the lottery execution process (when the determination in S314 is NO), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table, and draws the lottery. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lottery after subtraction is "0" (S317).

In S317, when the main CPU 101 determines that the number of lottery after subtraction is not "0" (when the determination in S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

On the other hand, in S317, when the main CPU 101 determines that the number of lottery after subtraction is "0" (when the determination in S317 is YES), that is, when the internal winning combination is "missing", the main CPU 101 determines. Set the loss status (S318). The "missing status" corresponds to the winning request flag status in which both the special prize winning number and the small winning combination winning number are "0". Then, after the processing of S318, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 74).

[Design setting process]
Next, with reference to FIG. 83, the symbol setting process performed in S205 in the main flow (see FIG. 74) will be described. Note that FIG. 83 is a flowchart showing the procedure of the symbol setting process.

First, the main CPU 101 extracts the special prize winning number and the small winning combination winning number based on the winning request flag status acquired in the internal lottery process, and extracts the extracted special winning winning number and the small winning combination winning number in the main RAM 103. It is stored in the winning number storage area (not shown) (S321).

In the present embodiment, the special prize winning numbers "1" and "2" are associated with the internal winning combinations "F_BB1" and "F_BB2", respectively. Further, the small winning combination "1" to "36" are associated with the internal winning combination "F_chili lip" to "F_RB combination 4", respectively. The value of the winning request flag status is composed of a value obtained by multiplying the special prize winning number by the special prize number (“37 (25H in hexadecimal number)” in the present embodiment) and adding the small winning combination winning number. Therefore, in the process of S321, since the special prize winning number and the small winning combination winning number are extracted from the value of the winning request flag status, in the present embodiment, the main CPU 101 sets the value of the winning request flag status to the special prize number (“37””. ) To divide. As a result, the value of the quotient generated by the division process becomes the special prize winning number (one of 0 to 2 in decimal), and the remaining value becomes the small winning winning number (one of 0 to 36 in decimal). Become.

Next, the main CPU 101 determines whether or not the small winning combination (or replay winning combination) has won based on the extracted small winning combination winning number (S322). In this process, if the small winning combination winning number is any of 1 to 36, the main CPU 101 determines that the small winning combination (or replay winning combination) has won, and if the small winning combination winning number is 0, , The main CPU 101 determines that the small winning combination (or replay winning combination) has not been won.

In S322, when the main CPU 101 determines that the small winning combination (or replay winning combination) has not been won (when the determination in S322 is NO), the main CPU 101 performs the process of S331 described later. On the other hand, in S322, when the main CPU 101 determines that the small winning combination (or replay winning combination) has won (when the determination in S322 is YES), the main CPU 101 sets the small winning combination winning number as the initial value of the subtraction result (when it is determined that S322 is YES). S323).

Next, the main CPU 101 sets a hit request flag table (not shown) (S324). Next, the main CPU 101 subtracts 1 from the subtraction result and updates the subtraction result (S325). Next, the main CPU 101 determines whether or not the subtraction result is less than "0" (S326).

In S326, when the main CPU 101 determines that the subtraction result is not less than "0" (when the determination in S326 is NO), the main CPU 101 performs the bit number calculation process (S327). In the bit number calculation process of S327, the number of blocks in the storage area of the hit request flag data corresponding to the small winning combination winning number specified in the hit request flag table is acquired.

In the present embodiment, the hit request flag storage area (internal winning combination storage area) is provided with blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11. Therefore, the maximum value of the number of blocks in the storage area of the hit request flag data acquired by the bit number calculation process of S327 is “2”. For example, when the internal winning combination is "F_certain chili lip", the storage area 7 included in the blocks of the hit request storage areas 0 to 7 and the storage area 9 included in the blocks of the hit request storage areas 8 to 11 Since the hit request flag data is defined for each, the number of blocks in the storage area of the hit request flag data acquired in the bit number calculation process of S327 is “2”.

Next, the main CPU 101 performs a bit number calculation process (S328). In the bit number calculation process of S328, the number of bytes of the hit request flag data in the block unit specified in the hit request flag table is calculated. For example, when the internal winning combination is "F_certain chili lip", the hit request flag data of 1 byte is stored in both the storage area 7 and the storage area 9, so that the block acquired by the bit number calculation process of S328 is performed. The number of bytes of the request flag data per unit is 1 byte.

The above-mentioned processing of S325 to S328 is repeated as many times as the number of small winning combination winning numbers. For example, when the internal winning combination is "F_certain winning combination" (small winning combination number is "2"), the above-mentioned processing of S325 to S328 is repeated twice. When the processing of S325 to S328 is repeated a plurality of times, the number of blocks acquired in the bit number calculation processing of S327 and S328 and the number of bytes of the hit request flag data for each block are stored in another storage area. Will be done. Further, the number of blocks obtained by the above-mentioned processing of S325 to S328 and the number of bytes of the hit request flag data in the block unit are information (on-bit information) for designating the storage destination of the hit request flag data.

Here, returning to the processing of S326 again, when the main CPU 101 determines in S326 that the subtraction result is less than "0" (when the determination in S326 is YES), the main CPU 101 is in the hit request flag storage area ( The internal winning combination storage area) is set (S329). At this time, the main CPU 101 checks (updates) the hit request flag based on the number of blocks obtained by the above-mentioned processes of S325 to S328 and the number of bytes (on-bit information) of the hit request flag data for each block. Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register.

Next, the main CPU 101 performs a compressed data storage process (S330). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). The details of the compressed data storage process will be described later with reference to FIG. 84 described later.

After the processing of S330 or when the determination in S322 is NO, the main CPU 101 refers to the carry-over combination storage area (see FIG. 31) to determine whether or not there is a carry-over combination (S331). In S331, when the main CPU 101 determines that there is a carry-over combination (when the determination in S331 is YES), the main CPU 101 performs the process of S334 described later.

On the other hand, in S331, when the main CPU 101 determines that there is no carry-over combination (when the determination in S331 is NO), the main CPU 101 determines the bonus combination (BB1 or BB2) based on the special prize winning number extracted in the process of S321. ) Wins or not (S332).

In S332, when the main CPU 101 determines that the bonus combination has not been won (when the determination in S332 is NO), the main CPU 101 ends the symbol setting process and shifts the process to S206 in the main flow (see FIG. 74). Transfer.

On the other hand, in S332, when the main CPU 101 determines that the bonus combination has been won (when the determination in S332 is YES), the main CPU 101 stores the winning special prize winning number in the carry-over combination storage area (S333).

After the processing of S333 or when the determination in S331 is NO, the main CPU 101 sets the special prize winning number in the winning number storage area (not shown), sets the hit request flag data in the hit request flag storage area, and sets the RT state to RT5. Set to the state and clear (“0”) the number of RT games (the number of digestion games in the RT1 state) (S334). Then, after the processing of S334, the main CPU 101 ends the symbol setting processing and shifts the processing to S206 of the main flow (see FIG. 74).

[Compressed data storage process]
Next, with reference to FIG. 84, for example, the compressed data processing performed in S330 during the symbol setting process (see FIG. 83) will be described. FIG. 84 is a flowchart showing the procedure of the compressed data storage process.

The compressed data storage process shown in FIG. 84 is executed not only in S330 during the symbol setting process (see FIG. 83) but also in S649 during the symbol code acquisition process (see FIG. 101 described later) described later. In the compressed data storage process executed in S330 during the symbol setting process (see FIG. 83), the flag data to be processed is the hit request flag data (flag data related to the winning combination), but the symbol code acquisition process described later In the compressed data storage process executed in S649 (see FIG. 101 described later), the flag data to be processed is the winning operation flag data (flag data related to the winning combination). Then, both processes are the same except that the types of flag data to be processed are different.

Therefore, in the flowchart of FIG. 84, the flag data to be processed is referred to as “process target flag data”, and the flag table to be processed is referred to as “process target flag table”. In addition, in accordance with this description, in the following description of the compressed data storage process, the winning request flag data or the winning operation flag data is referred to as "processing target flag data", and the winning request flag table or the symbol-corresponding winning operation table described later is used. (Not shown) is referred to as a "process target flag table".

First, the main CPU 101 sets the storage destination check bit (S341). In this process, the storage destination check bit is stored in a register other than the A register.

The storage destination check bit is 1-byte data for designating a block that is a storage destination (transfer destination) of the processing target flag data. In the present embodiment, the hit request flag storage area and the winning operation flag storage area are both composed of two blocks (blocks of storage areas 0 to 7 and blocks of storage areas 8 to 11). Then, for example, when the internal winning combination "F_certain chili lip" is determined, the hit request flag data is stored in each of the storage area 7 and the storage area 9 (the number of blocks in the storage destination is set to "2"). Therefore, in the process of S341, "00000011B" is set as the storage destination check bit. The bit 0 value (1/0) of this 1-byte data corresponds to the presence or absence of a storage destination in the block of the storage areas 0 to 7, and the bit 1 value (1/0) corresponds to the storage areas 8 to 11. Corresponds to the presence or absence of the storage destination in the block of.

Next, the main CPU 101 sets the value of the transfer counter in byte units to "8" (S342). In the present embodiment, since the number of bytes of each block is "8", "8" is set as the initial value of the transfer counter.

Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the processing of S343, the storage destination check bit stored in the 1-byte register is shifted to the right once (for 1 bit). As a result, the transfer instruction bit is extracted. Specifically, when the 1-byte register (register other than the A register) in which the storage destination check bit is stored is shifted to the right once, the data stored in bits 7 to 1 are changed to bits 6 to 0, respectively. As it moves, the data of bit 0 before the shift is output. Then, the data output by this shift process becomes the value of the transfer instruction bit.

Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000011B" is set as the storage destination check bit, transfer is performed in the first (corresponding to the first block of the storage area) and second (corresponding to the second block of the storage area) determination process of S344. Although it is determined that there is an instruction, in the determination process of S344 after the third time, it is determined that there is no transfer instruction.

In S344, when the main CPU 101 determines that there is no transfer instruction (when the determination in S344 is NO), the main CPU 101 performs the process of S354 described later.

On the other hand, in S344, when the main CPU 101 determines that there is a transfer instruction (when the determination in S344 is YES), the main CPU 101 acquires byte unit storage destination designation information from the processing target flag table (S345). In this process, the transfer destination is stored at the start address of the area in which the flag data of the process target combination (winning combination or winning combination) in the processing target flag table is stored as the byte unit storage destination specification information. Byte data is retrieved. For example, when the internal winning combination is "F_certain chili lip", the storage area 7 stored in the start address of the area in which the flag data of "F_certain chili lip" is stored in the hit request flag table is transferred. The 1-byte data "10000000B" specified as the destination is acquired as the byte unit storage destination designation information.

Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address to be referred to in the process target flag table (S346). Further, in this process, the main CPU 101 sets as an initial address an address that specifies the head storage area of the block that is the storage (transfer) destination of the processing target flag data. For example, in the processing of the first block, the address of the storage area 0 is set as the initial address in the processing of S346, and in the processing of the second block, the address of the storage area 8 is set as the initial address in the processing of S346. ..

Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage destination designation information (S347). The transfer instruction bit referred to here corresponds to bit 0 of the byte unit storage destination specification information, and in the processing of S347, the byte unit storage destination specification information stored in the 1-byte register is shifted to the right once. Extracts the value of the transfer instruction bit (outputs bit 0 data).

Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000010B" is set as the byte unit storage destination designation information, the bit 1 data "1" is processed in S347 of the second time (the storage area 1 of the first block or the storage area 9 of the second block). Is output as the value of the transfer instruction bit, and it is determined that there is a transfer instruction. However, in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

In S348, when the main CPU 101 determines that there is no transfer instruction (when the determination in S348 is NO), the main CPU 101 performs the process of S351 described later.

On the other hand, in S348, when the main CPU 101 determines that there is a transfer instruction (when the determination in S348 is YES), the main CPU 101 is the processing target flag stored in the address in the currently set processing target flag table. The data (winning request flag data or winning operation flag data) is transferred (copied) to the designated storage area (S349).

For example, when the internal winning combination is "F_certain chili lip" and the current processing is performed for the storage area (storage area 0 to 7) of the first block, the byte unit storage destination specification information is ". Since it becomes "10000000B" (data that specifies the storage area 7 as the storage destination), it is determined that there is a transfer instruction in the eighth processing of S347, and in the subsequent processing of S349, the hit request flag data "10000000B" and "01000000B" are obtained. , "00100000B" and "00010000B" are transferred (copied) to the storage area 7 of the hit request flag storage area.

Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address to be referred to in the process target flag table (S350).

After the processing of S350 or when the determination in S348 is NO, the main CPU 101 performs an address update processing (a processing of adding 1 to the address) for designating a storage area to be a storage destination of the processing target flag data (S351). Next, the main CPU 101 subtracts 1 from the value of the transfer counter (S352).

Next, the main CPU 101 determines whether or not the value of the transfer counter is "0" (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not "0" (when the determination in S353 is NO), the main CPU 101 returns the processing to the processing of S347 and repeats the processing after S347.

On the other hand, in S353, when the main CPU 101 determines that the value of the transfer counter is "0" (when the determination in S353 is YES), does the main CPU 101 have a transfer instruction target remaining in the current storage destination check bit? Whether or not it is determined (S354). In this process, the main CPU 101 determines whether or not a bit in which "1" is stored remains in the storage destination check bit at the time of the current process. Then, when the bit in which "1" is stored remains in the storage destination check bit, that is, when the block to be processed exists, the main CPU 101 gives a transfer instruction to the current storage destination check bit. Determine that the target remains.

In S354, when the main CPU 101 determines that the transfer instruction target remains in the current storage destination check bit (when the determination in S354 is YES), the main CPU 101 returns the process to the process of S342, and the process after S342. repeat. On the other hand, in S354, when the main CPU 101 determines that the transfer instruction target does not remain in the current storage destination check bit (when the determination in S354 is NO), the main CPU 101 ends the compressed data storage process and performs the process. For example, it is moved to S331 in the symbol setting process (see FIG. 83).

[Control processing by state]
Next, with reference to FIG. 85, the state-specific control processing performed in S208 in the main flow (see FIG. 74) will be described. FIG. 85 is a flowchart showing the procedure of the state-specific control process.

First, the main CPU 101 performs a sub-flag conversion process (S401). In this process, the main CPU 101 performs a process of converting the internal winning combination into sub-flags (see FIGS. 36 and 37). The details of the sub-flag conversion process will be described later with reference to FIG. 86 described later.

Next, the main CPU 101 performs a navigation set process (S402). In this process, the main CPU 101 acquires navigation data based on the RT state, the game state, and the small winning combination winning number. The details of the navigation set processing will be described later with reference to FIG. 87 described later.

Next, the main CPU 101 determines whether or not the current RT state is the RT4 state (S403). In S403, when the main CPU 101 determines that the current RT state is not the RT4 state (when the determination in S403 is NO), the main CPU 101 performs the process of S406 described later.

On the other hand, in S403, when the main CPU 101 determines that the current RT state is the RT4 state (when the determination in S403 is YES), the main CPU 101 performs a flag conversion process (S404). In this process, the main CPU 101 performs a flag conversion lottery process (compression process of sub-flag data) for converting the sub-flag into the sub-flag EX (see FIG. 36). By this flag conversion process, 19 types (including loss) of sub-flags are converted (compressed) into 9 types (including loss) of sub-flag EX. The details of the flag conversion process will be described later with reference to FIG. 88 described later.

Next, the main CPU 101 performs a sub-flag compression process (S405). In this process, the main CPU 101 converts the sub-flag EX into the sub-flag D (see FIG. 36), and further compresses the sub-flag data. By this sub-flag compression process, 9 types (including loss) of sub-flag EX are converted (compressed) into 7 types (including loss) of sub-flag D.

After the processing of S405 or when the determination in S403 is NO, the main CPU 101 determines whether or not the current gaming state is the normal gaming state (S406).

In S406, when the main CPU 101 determines that the current gaming state is the normal gaming state (when the determination in S406 is YES), the main CPU 101 performs the normal middle start process (S407). The details of the normal start processing will be described later with reference to FIG. 89 described later. Then, after the processing of S407, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

On the other hand, in S406, when the main CPU 101 determines that the current gaming state is not the normal gaming state (when the determination in S406 is NO), the main CPU 101 determines whether or not the current gaming state is CZ (when the current gaming state is determined to be NO). S408).

In S408, when the main CPU 101 determines that the current gaming state is CZ (when the determination in S408 is YES), the main CPU 101 performs the CZ middle start process (S409). The details of the CZ middle start processing will be described later with reference to FIG. 90 described later. Then, after the processing of S409, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

On the other hand, in S408, when the main CPU 101 determines that the current gaming state is not CZ (when the determination in S408 is NO), the main CPU 101 determines whether or not the current gaming state is normal ART (S410). ).

In S410, when the main CPU 101 determines that the current gaming state is the normal ART (when the determination in S410 is YES), the main CPU 101 performs the normal start processing during the ART (S411). The details of the normal start processing during ART will be described later with reference to FIG. 94 described later. Then, after the processing of S411, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

On the other hand, in S410, when the main CPU 101 determines that the current gaming state is not normal ART (when the determination in S410 is NO), the main CPU 101 determines whether or not the current gaming state is CT (S412). ).

In S412, when the main CPU 101 determines that the current gaming state is CT (when the determination in S412 is YES), the main CPU 101 performs a process at the start during CT (S413). The details of the processing at the start during CT will be described later with reference to FIG. 95 described later. Then, after the processing of S413, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

On the other hand, in S412, when the main CPU 101 determines that the current gaming state is not CT (when the determination in S412 is NO), the main CPU 101 determines whether or not the current gaming state is a bonus state (S414). ).

In S414, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S414 is YES), the main CPU 101 performs the process at the start during BB (S415). The details of the BB start processing will be described later with reference to FIG. 99 described later. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

On the other hand, in S414, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S414 is NO), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a game state other than the game state targeted by the various determination processes. For example, when the current game state is the ART preparation state, processing corresponding to the ART preparation state is performed. Then, after the processing of S416, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

[Sub-flag conversion process]
Next, with reference to FIG. 86, the sub-flag conversion process performed in S401 during the state-based control process (see FIG. 85) will be described. FIG. 86 is a flowchart showing the procedure of the sub-flag change processing.

First, the main CPU 101 acquires the small winning combination winning numbers (0 to 36) (S421). Next, the main CPU 101 determines whether or not the bonus operation is currently in progress (S422).

In S422, when the main CPU 101 determines that the bonus is currently in operation (when the determination in S422 is YES), the main CPU 101 converts the small winning combination winning number into a sub flag in which the bonus is operating and saves it (S423). .. Then, after the processing of S423, the main CPU 101 ends the sub-flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 85).

On the other hand, in S422, when it is determined that the main CPU 101 is not currently operating the bonus (when the determination in S422 is NO), the main CPU 101 sets a sub-flag conversion table (not shown) (S424). In this process, the initial value of the sub-flag to be determined is set to "loss (00)", and the sub-flag "loss (00)" is stored as the initial address of the block in the sub-flag conversion table to be referenced. Set the existing address ("dSBCVTB + 1").

Next, in the main CPU 101, whether the data of the small winning combination winning number defined in the block in the sub-flag conversion table currently being referenced is the data corresponding to the small winning combination winning number acquired in the current game. Whether or not it is determined (S425).

In S425, the main CPU 101 determines that the data of the small winning combination winning number defined in the block in the sub-flag conversion table to be referred to is not the data corresponding to the small winning combination winning number acquired in the current game. At this time (when the determination in S425 is NO), the main CPU 101 updates the block in the sub-flag conversion table to be referred to to the block at the next address (S426). Next, the main CPU 101 adds "1" to the value of the sub flag (S427). Then, after the processing of S427, the main CPU 101 returns the processing to the processing of S425, and repeats the processing after S425.

On the other hand, in S425, the data of the small winning combination winning number defined in the block in the sub-flag conversion table to be referenced by the main CPU 101 is the data corresponding to the small winning combination winning number acquired in the current game. When it is determined (when the determination in S425 is YES), the main CPU 101 refers to the sub-flag conversion table and sets the sub-flag conversion control data (to the address next to the address of the small winning combination number) associated with the small winning combination winning number. The stored 1-byte data) is acquired, and the sub-flag conversion control data is stored in the sub-flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). In this process, for example, when the small winning combination winning number acquired in the current game is "03" (internal winning combination "F_3 consecutive chili lip"), the sub-flag conversion control data "00000011B" is referred to with reference to the sub-flag conversion table. Is acquired. Then, after the processing of S428, the main CPU 101 ends the sub-flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 85).

[Naviset processing]
Next, with reference to FIG. 87, the navigation set process performed in S402 during the state-based control process (see FIG. 85) will be described. FIG. 87 is a flowchart showing the procedure of the navigation set process.

First, the main CPU 101 determines whether or not the navigation set flag is set in the sub-flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub-flag conversion control data storage area, and the set sub-flag conversion control data is data corresponding to the small winning combination winning numbers (10 to 23) that generate push order navigation. Determine if it is. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub-flag conversion control data storage area (when the determination in S431 is NO), the main CPU 101 ends the navigation set processing and performs the processing according to the state. The control process (see FIG. 85) is transferred to S403.

On the other hand, in S431, when the main CPU 101 determines that the navigation set flag is set in the sub-flag conversion control data storage area (when the determination in S431 is YES), the RT state of the main CPU 101 is RT0 or RT1. Whether or not it is determined (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (when the determination in S432 is NO), the main CPU 101 ends the navigation set process and controls the process according to the state (see FIG. 85). Move to S403.

On the other hand, in S432, when the main CPU 101 determines that the RT state is the RT0 or RT1 state (when the determination in S432 is YES), the main CPU 101 determines whether or not the gaming state is the general gaming state (when the RT state is determined to be YES). S433). In S433, when the main CPU 101 determines that the gaming state is the general gaming state (when the determination in S433 is YES), the main CPU 101 ends the navigation set process and controls the process according to the state (see FIG. 85). Move to S403.

On the other hand, in S433, when the main CPU 101 determines that the gaming state is not the general gaming state (when the determination in S433 is NO), the main CPU 101 acquires the small winning combination winning number (S434). Next, the main CPU 101 refers to the navigation data table (not shown) and acquires navigation data (any of 1 to 9) based on the small winning combination winning number (S435).

Next, the main CPU 101 stores the acquired navigation data (information regarding the stop operation of the variable display of the plurality of display columns) in the navigation data storage area (stop operation instruction information storage area) (S436) in the main RAM 103. Then, after the processing of S436, the main CPU 101 ends the navigation set processing, and shifts the processing to S403 of the state-based control processing (see FIG. 85).

[Flag conversion process]
Next, with reference to FIG. 88, the flag conversion process performed in S404 during the state-based control process (see FIG. 85) will be described. Note that FIG. 88 is a flowchart showing the procedure of the flag conversion process.

First, the main CPU 101 determines whether or not it is the start of CT (S441).

When the main CPU 101 determines in S441 that it is not the start of CT (when the determination in S441 is NO), the main CPU 101 performs the process of S443 described later. On the other hand, in S441, when the main CPU 101 determines that it is the start of CT (when the determination in S441 is YES), the main CPU 101 determines the table number of the flag conversion lottery table used for the flag conversion lottery during CT by lottery. And set (S442).

After the processing of S442 or when the determination in S441 is NO, the main CPU 101 sets the flag conversion lottery table according to the current state (S443). For example, if the current state is the RT4 state during non-ART, the non-ART flag conversion lottery table (see FIG. 62) is set, and if the current state is the RT4 state during normal ART, The flag conversion lottery table during ART (see FIGS. 47A and 47B) is set, and when the current state is the RT4 state during CT, the flag conversion lottery table during CT (see FIG. 54) is set.

Next, the main CPU 101 refers to the set flag conversion lottery table, and performs the flag conversion lottery process based on the internal winning combination (S444). In fact, in this process, the main CPU 101 performs a flag conversion lottery process using the sub-flag conversion control data acquired from the sub-flag conversion table based on the sub-flag corresponding to the internal winning combination.

Next, the main CPU 101 determines whether or not the flag conversion lottery of S444 has been won (S445).

In S445, when the main CPU 101 determines that the flag conversion lottery has been won (when the determination in S445 is YES), the main CPU 101 performs the sub-flag conversion process (S446). In this process, for example, when the internal winning combination is "F_1 certainty lip", that is, when the sub flag is "triple chili lip B (03)", when the flag conversion lottery process is won, the sub flag conversion process of S446 is performed. , The sub-flag "triple chili lip B (03)" is converted to the sub-flag EX "fixed combination (06)" or the sub-flag EX "triple chili lip (07)" (see FIG. 36).

After the process of S446, the main CPU 101 determines whether or not the current gaming state is the non-ART state (S447). In S447, when the main CPU 101 determines that the current gaming state is not the non-ART state (when the determination in S447 is NO), the main CPU 101 ends the flag conversion process and controls the process according to the state (see FIG. 85). ) S405.

On the other hand, in S447, when the main CPU 101 determines that the current gaming state is the non-ART state (when the determination in S447 is YES), the main CPU 101 adds "1" to the number of ART sets (S448). Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S449). Then, after the processing of S449, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-based control processing (see FIG. 85).

Here, returning to the process of S445 again, when the main CPU 101 determines in S445 that the flag conversion lottery has not been won (when the determination in S445 is NO), the main CPU 101 performs the sub-flag maintenance process (S450). .. In this process, for example, when the internal winning combination is "F_1 certainty lip", that is, when the sub flag is "triple chili lip B (03)", and the flag conversion lottery is not winning, the sub flag of S450 is maintained. By the processing, the sub-flag "triple chili lip B (03)" is converted (maintained) into the sub-flag EX "replay (01)". Then, after the processing of S450, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-based control processing (see FIG. 85).

[Normal start processing]
Next, with reference to FIG. 89, the normal middle start process performed in S407 during the state-based control process (see FIG. 85) will be described. Note that FIG. 89 is a flowchart showing the procedure of the normal start processing.

First, the main CPU 101 refers to the CZ lottery table (see FIG. 41A), and performs the CZ lottery process based on the current CZ lottery state and the internal winning combination (sub-flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery of S461 has been won (S462).

In S462, when the main CPU 101 determines that the CZ lottery has not been won (when the determination in S462 is NO), the main CPU 101 performs the process of S465 described later.

On the other hand, in S462, when the main CPU 101 determines that the CZ lottery has been won (when the determination in S462 is YES), the main CPU 101 sets the winning type CZ in the game state of the next game (S463). Next, the main CPU 101 sets the number of winning CZ games in the CZ game number counter (S464). The CZ game number counter is a counter that counts the duration of CZ, and is provided in the main RAM 103. In the process of S464, for example, when CZ1 wins, the first predetermined number of games (for example, "12") is set in the CZ game number counter (first half), and CZ2 wins. Is set to a second predetermined number of games (for example, "15") in the CZ game number counter (first half), and when CZ3 wins, a fourth predetermined number of games is set in the CZ game number counter. (For example, "17") is set.

After the processing of S464 or when the determination in S462 is NO, the main CPU 101 usually refers to the medium-high probability lottery table (see FIG. 40A), and performs a lottery to shift the lottery state of CZ based on the internal winning combination (sub-flag) (S465). ). Next, the main CPU 101 updates the lottery state of CZ based on the result of the transition lottery (S466). Then, after the processing of S466, the main CPU 101 ends the normal middle start processing and also ends the state-specific control processing (see FIG. 85).

[Processing at start during CZ]
Next, with reference to FIG. 90, the CZ middle start process performed in S409 during the state-specific control process (see FIG. 85) will be described. Note that FIG. 90 is a flowchart showing the procedure of the CZ middle start processing.

First, the main CPU 101 determines whether or not the current gaming state is CZ1 (S471).

In S471, when the main CPU 101 determines that the current gaming state is CZ1 (when the determination in S471 is YES), the main CPU 101 performs CZ1 (CZ2) intermediate processing (S472). The details of the processing during CZ1 (CZ2) will be described later with reference to FIGS. 91 and 92 described later. Then, after the processing of S472, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 85).

On the other hand, in S471, when the main CPU 101 determines that the current gaming state is not CZ1 (when the determination in S471 is NO), the main CPU 101 determines whether or not the current gaming state is CZ2 (S473). ..

In S473, when the main CPU 101 determines that the current gaming state is CZ2 (when the determination in S473 is YES), the main CPU 101 performs CZ1 (CZ2) intermediate processing (S474). Details of the processing during CZ1 (CZ2) will be described later with reference to FIGS. 91 and 92 described later. Then, after the processing of S474, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 85). In the present embodiment, the CZ1 intermediate processing and the CZ2 intermediate processing differ only in the rank (mode or point) indicating the degree of expectation of winning the ART lottery, and the basic processing contents are the same. Therefore, in the present embodiment, the CZ1 intermediate process and the CZ2 intermediate process will be described as one process as the CZ1 (CZ2) intermediate process.

On the other hand, in S473, when the main CPU 101 determines that the current gaming state is not CZ2 (when the determination in S473 is NO), the main CPU 101 performs CZ3 intermediate processing (S475). The details of the processing during CZ3 will be described later with reference to FIG. 93 described later. Then, after the processing of S475, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 85).

[Processing during CZ1 (CZ2)]
Next, with reference to FIGS. 91 and 92, the CZ1 (CZ2) intermediate processing performed in S472 or S474 during the CZ intermediate start processing (see FIG. 90) will be described. In addition, FIG. 91 and FIG. 92 are flowcharts showing the procedure of processing in CZ1 (CZ2).

First, the main CPU 101 determines whether or not the current game is a game in the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not the game of the first half of CZ1 (or CZ2) (when the determination in S481 is NO), the main CPU 101 performs the process of S490 described later.

On the other hand, in S481, when the main CPU 101 determines that the current game is a game in the first half of CZ1 (when the determination in S481 is YES), the main CPU 101 refers to the CZ1 middle mode-up lottery table (see FIG. 42). Then, the mode-up lottery process is performed based on the internal winning combination (sub flag) (S482). Further, in S481, when the main CPU 101 determines that the current game is a game in the first half of CZ2 (when the determination in S481 is YES), the main CPU 101 refers to the CZ2 middle point lottery table (see FIG. 43). , A point-up lottery is performed based on the internal winning combination (sub flag) (S482).

Next, the main CPU 101 updates the rank (mode or point) based on the lottery result of S482 (S483). Next, the main CPU 101 determines whether or not the freeze has been won in the lottery of S482 (S484).

In S484, when the main CPU 101 determines that the freeze has been won (when the determination in S484 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game, and the number of ART sets and the number of CT sets. Add "1" to (S485). Further, in this process, the main CPU 101 determines and sets the ART level with reference to the ART level determination table (see FIG. 48A). When a freeze occurs, "ART level 2" is determined as the ART level.

Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S486). Then, after the processing of S486, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing at the start during CZ (see FIG. 90).

Here, returning to the processing of S484 again, when it is determined in S484 that the main CPU 101 has not won the freeze (when the determination in S484 is NO), the main CPU 101 is the value of the CZ game number counter (first half). Is subtracted by 1 (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half) is "0" (S488).

In S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is not "0" (when the determination in S488 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and at the same time, The processing at the start during CZ (see FIG. 90) is also completed.

On the other hand, in S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is "0" (when the determination in S488 is YES), the main CPU 101 sets the CZ1 or the game state of the next game. The latter half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing at the start during CZ (see FIG. 90).

Here, returning to the process of S481 again, when the determination in S481 is NO, the main CPU 101 determines whether or not the current game is the first game in the latter half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game in the latter half of CZ1 or CZ2 (when the determination in S490 is NO), the main CPU 101 performs the process of S495 described later.

On the other hand, in S490, when the main CPU 101 determines that the current game is the first game in the latter half of CZ1 or CZ2 (when the determination in S490 is YES), the main CPU 101 uses the ART lottery table in CZ (FIGS. 44A and 44A and). (Refer to 44B), the ART lottery process is performed based on the rank (mode or point) of the first half (S491).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S492). In S492, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S492 is NO), the main CPU 101 performs the process of S494 described later.

On the other hand, in S492, when the main CPU 101 determines that the ART lottery has been won (when the determination in S492 is YES), the main CPU 101 adds "1" to the number of ART sets and sets the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S493).

After the processing of S493 or when the determination in S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half) (S494). In the processing of S494, for example, when the ART lottery is won, "4" is set in the CZ game number counter (second half), and when the ART lottery is not won, the number of CZ games is set. "3" is set in the counter (second half).

After the processing of S494 or when the determination in S490 is NO, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 44C) and performs the ART lottery processing based on the internal winning combination (sub flag) (S495).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S496). In S496, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S496 is NO), the main CPU 101 performs the process of S498 described later.

On the other hand, in S496, when the main CPU 101 determines that the ART lottery has been won (when the determination in S496 is YES), the main CPU 101 adds "1" to the number of ART sets and sets the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S497).

After the processing of S497 or when the determination in S496 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (second half) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is "0" (S499).

In S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is not "0" (when the determination in S499 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and at the same time, The processing at the start during CZ (see FIG. 90) is also completed.

On the other hand, in S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is "0" (when the determination in S499 is YES), the main CPU 101 has an ART set number of "1" or more. It is determined whether or not it is (S500).

In S500, when the main CPU 101 determines that the number of ART sets is "1" or more (when the determination in S500 is YES), the main CPU 101 sets the ART preparation state in the game state of the next game (S501). Then, after the processing of S501, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing at the start during CZ (see FIG. 90).

On the other hand, in S500, when the main CPU 101 determines that the number of ART sets is not "1" or more (when the determination in S500 is NO), the main CPU 101 sets the game state of the next game to the state at the time of CZ failure (when the CZ failure state is set). S502). Then, after the processing of S502, the main CPU 101 ends the processing during CZ1 (CZ2) and also ends the processing at the start during CZ (see FIG. 90).

[Processing during CZ3]
Next, with reference to FIG. 93, the CZ3 intermediate processing performed in S475 during the CZ intermediate start processing (see FIG. 90) will be described. Note that FIG. 93 is a flowchart showing the procedure of processing during CZ3.

First, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 45), and performs the ART lottery process based on the internal winning combination (sub flag) (S511).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S512). In S512, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S512 is NO), the main CPU 101 performs the process of S518 described later.

On the other hand, in S512, when the main CPU 101 determines that the ART lottery has been won (when the determination in S512 is YES), the main CPU 101 adds "1" to the number of ART sets and adds "1" to the number of CT sets. Add (S513). Next, the main CPU 101 determines whether or not the freeze has been won in the ART lottery of S512 (S514).

In S514, when the main CPU 101 determines that the freeze has not been won (when the determination in S514 is NO), the main CPU 101 performs the process of S516 described later. On the other hand, in S514, when the main CPU 101 determines that the freeze has been won (when the determination in S514 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game (S515).

After the processing of S515 or when the determination in S514 is NO, the main CPU 101 performs an ART level lottery process with reference to the ART level determination table (see FIG. 48A), and sets the lottery result (ART level) (S516). .. Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S517). Then, after the processing of S517, the main CPU 101 ends the processing during CZ3 and also ends the processing at the start during CZ (see FIG. 90).

Here, returning to the process of S512 again, when the determination in S512 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether or not the value of the CZ game number counter is "0" (S519).

In S519, when the main CPU 101 determines that the value of the CZ game number counter is not "0" (when the determination in S519 is NO), the main CPU 101 ends the CZ3 middle processing and the CZ middle start processing (FIG. 90) also ends.

On the other hand, in S519, when the main CPU 101 determines that the value of the CZ game number counter is "0" (when the determination in S519 is YES), the main CPU 101 adds "1" to the number of ART sets and ARTs. An ART level lottery is performed with reference to the level determination table (see FIG. 48A), and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S521). Then, after the processing of S521, the main CPU 101 ends the processing during CZ3 and also ends the processing at the start during CZ (see FIG. 90).

[Processing at start during normal ART]
Next, with reference to FIG. 94, the process at the start of normal ART performed in S411 during the state-specific control process (see FIG. 85) will be described. Note that FIG. 94 is a flowchart showing the procedure of the normal start processing during ART.

First, the main CPU 101 adds "1" to the value of the ART continuous game number counter (S531). The ART continuation game number counter is a counter that normally counts the number of games (digestion games) that ART has continued. Further, in the present embodiment, in addition to the ART continuous game number counter, an ART end game number counter that counts the number of games that can be normally continued by ART is also provided. Then, in the pachislot 1 of the present embodiment, the value of the ART continuous game number counter is compared with the value of the ART end game number counter, and when the value of the ART continuous game number counter reaches the value of the ART end game number counter, ART The game state ends.

Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 50), and performs the CT lottery process based on the current CT lottery state and the internal winning combination (sub flag) (S532). Next, the main CPU 101 determines whether or not the CT lottery has been won (S533). In S533, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S533 is NO), the main CPU 101 performs the process of S536 described later.

On the other hand, in S533, when the main CPU 101 determines that the CT lottery has been won (when the determination in S533 is YES), the main CPU 101 adds "1" to the number of CT sets and adds "1" to the value of the CT game number counter. 8 ”is set (S534). Next, the main CPU 101 sets the winning type of CT in the game state of the next game (S535).

After the processing of S535 or when the determination in S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48B), draws the ART level based on the value of the ART continuous game number counter, and sets the lottery result. (S536). Next, the main CPU 101 refers to the normal ART medium-high probability lottery table (see FIG. 49), draws the CT lottery state of the migration destination based on the current CT lottery state and the internal winning combination (sub flag), and the lottery result. Is set (S537).

Next, the main CPU 101 refers to the additional lottery table during normal ART (see FIG. 51), and performs an additional lottery process for the number of ART games based on the internal winning combination (sub-flag) (S538). Next, the main CPU 101 determines whether or not the additional lottery has been won (S539).

In S539, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S539 is NO), the main CPU 101 performs the process of S541 described later. On the other hand, in S539, when the main CPU 101 determines that the additional lottery has been won (when the determination in S539 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S540).

After the processing of S540 or when the determination in S539 is NO, the main CPU 101 determines whether or not the value of the ART continuous game number counter has reached the value of the ART end game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continuation game number counter has not reached the value of the ART end game number counter (when the determination in S541 is NO), the main CPU 101 normally processes at the start during ART. Is terminated, and the state-specific control process (see FIG. 85) is also terminated.

On the other hand, in S541, when the main CPU 101 determines that the value of the ART continuous game number counter has reached the value of the ART end game number counter (when the determination in S541 is YES), the main CPU 101 sets the number of ART sets to 1. Subtract (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 ends the normal start processing during ART, and also ends the state-specific control processing (see FIG. 85).

[Processing at start during CT]
Next, with reference to FIG. 95, the process at the start of CT performed in S413 during the state-specific control process (see FIG. 85) will be described. Note that FIG. 95 is a flowchart showing the procedure of the start processing during CT.

First, the main CPU 101 refers to the additional lottery table during CT (see FIG. 55), and performs an additional lottery for the number of ART games based on the internal winning combination (sub-flag) (S551). Next, the main CPU 101 determines whether or not the additional lottery has been won (S552).

In S552, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S552 is NO), the main CPU 101 performs the process of S556 described later. On the other hand, in S552, when the main CPU 101 determines that the additional lottery has been won (when the determination in S552 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S553). As described above, in the pachislot machine 1 of the present embodiment, the more times the sub-flag "triple chili lip (triple chili lip A or triple chili lip B)" is won during the same CT, the more per lottery. The amount of extra is increased.

After the processing of S553, the main CPU 101 determines whether or not the internal winning combination corresponds to the sub-flag EX "triple chili lip" (or "fixed combination"), that is, the internal winning combination "F_certain chili lip" or "F_1". It is determined whether or not the flag conversion lottery process of S444 in FIG. 88 has been won (S554).

In S554, when the main CPU 101 determines that the internal winning combination does not correspond to the sub-flag EX "triple chili lip" (when the determination in S554 is NO), the main CPU 101 ends the processing at the start during CT, and at the same time, The state-specific control process (see FIG. 85) also ends.

On the other hand, in S554, when the main CPU 101 determines that the internal winning combination corresponds to the sub-flag EX "triple chili lip" (when the determination in S554 is YES), the main CPU 101 sets the value of the CT game number counter. "1" is added (S555). Then, after the processing of S555, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 85).

Here, returning to the process of S552 again, when the determination in S552 is NO, the main CPU 101 performs the CT lottery process during CT (S556). In this process, the main CPU 101 mainly performs an additional lottery for the number of CT sets. The details of the CT lottery process during CT will be described later with reference to FIG. 96 described later.

Next, the main CPU 101 subtracts 1 from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether or not the value of the CT game number counter is "0" (S558).

In S558, when the main CPU 101 determines that the value of the CT game number counter is not "0" (when the determination in S558 is NO), the main CPU 101 ends the CT start processing and state-specific control processing (when the CT game number counter value is not "0"). (See FIG. 85) also ends. On the other hand, in S558, when the main CPU 101 determines that the value of the CT game number counter is "0" (when the determination in S558 is YES), the main CPU 101 determines whether the number of CT sets is "1" or more. (S559).

In S559, when the main CPU 101 determines that the number of CT sets is "1" or more (when the determination in S559 is YES), the main CPU 101 subtracts 1 from the number of CT sets (S560). Next, the main CPU 101 sets the value of the CT game number counter to "8" (S561). Then, after the processing of S561, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 85).

On the other hand, in S559, when the main CPU 101 determines that the number of CT sets is not "1" or more (when the determination in S559 is NO), the main CPU 101 sets the normal ART in the gaming state of the next game (S562). Then, after the processing of S562, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 85).

[CT lottery processing during CT]
Next, with reference to FIG. 96, the CT lottery process during CT performed in S556 during the start process during CT (see FIG. 95) will be described. Note that FIG. 96 is a flowchart showing the procedure of CT lottery processing during CT.

First, the main CPU 101 sets the CT lottery table during CT (S571). The CT lottery table set here is a lottery table for adding the number of sets in CT, which is outlined in FIG. 56.

Next, the main CPU 101 performs a table data acquisition process (S572). In this process, the main CPU 101 acquires the address of the lottery table referred to in the CT lottery process during CT. The details of the table data acquisition process will be described later with reference to FIG. 97, which will be described later.

Next, the main CPU 101 performs a 1-byte lottery process (S573). In this process, the main CPU 101 performs an additional lottery of the CT set. The details of the 1-byte lottery process will be described later with reference to FIG. 98 described later.

Next, the main CPU 101 determines whether or not the 1-byte lottery process has been won (S574). In S574, when the main CPU 101 determines that the 1-byte lottery process has not been won (when the determination in S574 is NO), the main CPU 101 ends the CT lottery process during CT and performs the process at the start of CT (FIG. (Refer to 95), move to S557.

On the other hand, in S574, when the main CPU 101 determines that the 1-byte lottery process has been won (when the determination in S574 is YES), the main CPU 101 adds "1" to the number of CT sets (S575). Then, after the processing of S575, the main CPU 101 ends the CT lottery processing during CT, and shifts the processing to S557 of the processing at the start during CT (see FIG. 95).

[Table data acquisition process]
Next, with reference to FIG. 97, the table data acquisition process performed in S572 during the CT lottery process during CT (see FIG. 96) will be described. FIG. 97 is a flowchart showing the procedure of the table data acquisition process.

In the present embodiment, when the lottery value referred to in the CT lottery process during CT is acquired, the lottery value is stored through the two-step address calculation process (first-step and second-step table data acquisition process). Calculate the address. First, in the first-stage table data acquisition process (processes S582 and S583 described later), a "selection value (1 byte)" associated with the internal winning combination (actually, the sub flag D) is acquired. The selected value is provided for each type of internal winning combination, it is possible to determine whether or not the internal winning combination is a lottery target, and it is possible to specify the placement destination of the lottery table associated with the internal winning combination. Value (relative value) is specified. Further, in the present embodiment, the selection value "0" is defined in advance for the internal winning combination (actually, the sub-flag D) in which the lottery result of the CT lottery processing during CT is non-winning, and the internal winning combination is set to 1. It is treated as "miss" at the time of the table data acquisition process of the stage. Then, in the second stage table data acquisition processing (processing of S585 to S587 described later), an address in which the lottery value of the internal winning combination in which the selection value other than "0" is defined is stored is calculated (lottery table). The address is calculated by adding the relative value (selected value) from the reference address (2 bytes) of.

First, the main CPU 101 refers to the CT lottery selection table during CT (not shown), and addresses the first and second stages of additional selection data for calculating the address of the CT lottery table during CT, and the CT. The number of lottery lottery (twice in this embodiment) is acquired (S581). Next, the main CPU 101 adds the address of the first-stage addition selection data to the address of the CT lottery table during CT to calculate the first-stage selection address (S582).

Next, the main CPU 101 acquires the selection value stored in the calculated first-stage selection address (S583). Next, the main CPU 101 determines whether or not the selected value is "0" (S584).

In S584, when the main CPU 101 determines that the selected value is "0" (when the determination in S584 is YES), the main CPU 101 ends the table data acquisition process and performs the CT lottery process during CT (FIG. 96). (See) to S573.

On the other hand, in S584, when the main CPU 101 determines that the selection value is not "0" (when the determination in S584 is NO), the main CPU 101 adds the selection value to the selection address to obtain the selection address of the second stage. Calculate (S585). Next, the main CPU 101 adds the address of the second-stage addition selection data to the second-stage selection address to calculate the selection address (S586).

Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates the address to be referred to in the CT lottery table during CT (S587). .. Then, after the processing of S587, the main CPU 101 ends the table data acquisition processing, and shifts the processing to S573 of the CT lottery processing during CT (see FIG. 96).

[1 byte lottery process]
Next, with reference to FIG. 98, the 1-byte lottery process performed in S573 during the CT lottery process during CT (see FIG. 96) will be described. FIG. 98 is a flowchart showing the procedure of the 1-byte lottery process.

First, the main CPU 101 sets a 1-byte random number value (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110) stored in the random number storage area (not shown) in the main RAM 103 for CT lottery during CT. Set (S591). Next, the main CPU 101 acquires lottery determination data from the CT lottery table during CT based on the address calculated in S587 during the table data acquisition process (S592). Further, in this process, the main CPU 101 sets the number of determination bits "8" as the initial value of the number of lottery.

Next, the main CPU 101 determines whether or not the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to the bit data in the determination bit associated with the current number of lottery, and if the bit data is "1", it determines that the lottery target is selected. In the present embodiment, the bits 0 to 7 in the determination bit are associated with the number of lottery "8" to "1", respectively.

In S593, when the main CPU 101 determines that the lottery determination data is not the lottery target (when the determination in S593 is NO), the main CPU 101 performs the process of S599 described later. On the other hand, in S593, when the main CPU 101 determines that the lottery determination data is the lottery target (when the determination in S593 is YES), the main CPU 101 acquires the lottery value from the CT lottery table during CT (S594).

Next, the main CPU 101 determines whether or not the lottery value is "0" (winning confirmation data) (S595).

In S595, when the main CPU 101 determines that the lottery value is "0" (when the determination in S595 is YES), the main CPU 101 ends the 1-byte lottery process, and performs the CT lottery process during CT (FIG. 96). (See) to S574. On the other hand, in S595, when the main CPU 101 determines that the lottery value is not "0" (when the determination in S595 is NO), the main CPU 101 performs a CT lottery (additional lottery of the number of CT sets) process (S596). Specifically, the main CPU 101 subtracts a lottery value from a random number value (1 byte random value), and uses the subtraction result as a random number value.

Next, the main CPU 101 determines whether or not the CT lottery of S596 has been won (S597). In the CT lottery of S596, the main CPU 101 determines that the winning result is obtained when the subtraction result of S596 is "0" or less (when a so-called "digit shift" occurs).

In S597, when the main CPU 101 determines that the CT lottery has been won (when the determination in S597 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is the CT lottery process during CT (see FIG. 96). Move to S574. On the other hand, in S597, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S597 is NO), the main CPU 101 refers to the lottery value storage address (lottery address) in the CT lottery table during CT. Is updated to the next lottery address (S598).

After the processing of S598 or when the determination in S593 is NO, the main CPU 101 subtracts 1 from the number of lottery (S599). Next, the main CPU 101 determines whether or not the number of lottery is "0" (S600).

In S600, when the main CPU 101 determines that the number of lottery is not "0" (when the determination in S600 is NO), the main CPU 101 returns the process to S593 and repeats the processes after S593. On the other hand, in S600, when the main CPU 101 determines that the number of lottery is "0" (when the determination in S600 is YES), the main CPU 101 ends the 1-byte lottery process, and performs the CT lottery process during CT (CT lottery process). (See FIG. 96).

[Processing at start during BB]
Next, with reference to FIG. 99, the BB start-time processing performed in S415 during the state-specific control processing (see FIG. 85) will be described. Note that FIG. 99 is a flowchart showing the procedure of the start processing during BB.

First, the main CPU 101 refers to the bonus lottery table for adding the number of ART games (see FIG. 59), and performs the lottery process for adding the number of ART games based on the internal winning combination (S611). Next, the main CPU 101 determines whether or not the additional lottery has been won (S612).

In S612, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S612 is NO), the main CPU 101 ends the BB start process and also performs the state-specific control process (see FIG. 85). finish. On the other hand, in S612, when the main CPU 101 determines that the additional lottery has been won (when the determination in S612 is YES), the main CPU 101 adds the winning result (the number of additional games) to the ART end game number counter (S613). ..

Next, the main CPU 101 determines whether or not the number of ART sets is "0" (S614). In S614, when the main CPU 101 determines that the number of ART sets is not "0" (when the determination in S614 is NO), the main CPU 101 ends the BB start processing and the state-specific control processing (see FIG. 85). ) Also ends.

On the other hand, in S614, when the main CPU 101 determines that the number of ART sets is "0" (when the determination in S614 is YES), the main CPU 101 adds "1" to the number of ART sets (S615). Then, after the processing of S615, the main CPU 101 ends the processing at the start during BB, and also ends the state-specific control processing (see FIG. 85).

[Pull-in priority storage process]
Next, with reference to FIG. 100, the pull-in priority storage process performed in S212 in the main flow (see FIG. 74) will be described. FIG. 100 is a flowchart showing the procedure of the attraction priority storage process.

First, the main CPU 101 sets "3" to the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, the pull-in priority table (see FIG. 27) is selected based on the internal winning combination and the operation stop button.

Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the reel to be searched is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

Next, the main CPU 101 performs a symbol code acquisition process (S625). In this process, the symbol code is acquired by referring to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 101 described later.

Next, the main CPU 101 performs a logical product calculation process (S626). In this process, the main CPU 101 performs a winning operation flag data generation process. The details of the logical product calculation process will be described later with reference to FIG. 102 described later.

Next, the main CPU 101 performs a pull-in priority acquisition process (S627). In this process, in the main CPU 101, the bit is set to "1" in the winning operation flag (winning combination) storage area (see FIGS. 28 to 30), and the bit is set to "1" in the hit request flag storage area. With reference to the attraction priority table (see FIG. 27), the attraction priority data is acquired for the winning combination. The details of the pull-in priority acquisition process will be described later with reference to FIGS. 103 and 104 described later.

Next, the main CPU 101 stores the acquired attraction priority data in the attraction priority data storage area (not shown) in the main RAM 103 (S628). At this time, the attraction priority data is stored in the attraction priority data storage area so that the value of each priority and the bit of the storage area correspond to each other.

The pull-in priority data storage area is provided with a priority data storage area for each type of main reel. In each attraction priority data storage area, the attraction priority data determined according to each symbol position "0" to "19" of the corresponding main reel is stored. In the present embodiment, by referring to this attraction priority data storage area, it is searched whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces determined based on the stop table.

The content of the priority pull-in data stored in the pull-in priority data storage area differs depending on the type of the pull-in priority table number in the pull-in priority table referred to when determining the pull-in priority data. Further, the pull-in priority data indicates that the larger the value, the higher the priority. By referring to the pull-in priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol whose highest value is determined as the attraction priority data is the symbol having the highest priority. Therefore, it can be said that the pull-in priority data indicates the order between the symbols arranged on the peripheral surface of the main reel. If there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

Next, the main CPU 101 updates the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is "0" (S631).

In S631, when the main CPU 101 determines that the number of symbol checks is not "0" (when the determination in S631 is NO), the main CPU 101 returns the process to the process of S625 and repeats the processes after S625. On the other hand, in S631, when the main CPU 101 determines that the number of symbol checks is "0" (when the determination in S631 is YES), the main CPU 101 performs a search target reel change process (S632).

Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is "0", that is, whether or not the above-mentioned series of processes has been performed on all the main reels (S634).

In S634, when the main CPU 101 determines that the number of search reels is not "0" (when the determination in S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, in S634, when the main CPU 101 determines that the number of search reels is "0" (when the determination in S634 is YES), the main CPU 101 ends the attraction priority storage process and performs the process in the main flow (FIG. FIG. (Refer to 74), move to S213.

[Design code acquisition process]
Next, with reference to FIG. 101, the symbol code acquisition process performed in S625 during the attraction priority storage process (see FIG. 100) will be described. FIG. 101 is a flowchart showing the procedure of the symbol code acquisition process.

First, the main CPU 101 clears the winning operation flag storage area (S641). In this process, the main CPU 101 sets "0" in all the storage areas in the winning operation flag storage area (see FIGS. 28 to 30). Next, the main CPU 101 sets the first reel symbol arrangement table (not shown) (S642).

Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when the determination in S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S643, when the main CPU 101 determines that the first reel (left reel 3L) is not stopped (when the determination in S643 is NO), the main CPU 101 sets the second reel symbol arrangement table (not shown). (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten by the second reel symbol arrangement table.

Next, the main CPU 101 determines whether or not the second reel (middle reel 3C) is stopped (S645).

In S645, when the main CPU 101 determines that the second reel (middle reel 3C) is stopped (when the determination in S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S645, when the main CPU 101 determines that the second reel (middle reel 3C) is not stopped (when the determination in S645 is NO), the main CPU 101 sets the third reel symbol arrangement table (not shown). (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten by the third reel symbol arrangement table.

After the processing of S646, or when S643 or S645 is a YES determination, the main CPU 101 performs a symbol check process at the time of executing the stop operation on the reel to be stopped controlled, and corresponds to the symbol corresponding to the symbol acquired by the symbol check process. Acquire a winning operation table (not shown) (S647). The symbol-corresponding winning operation table is a table for identifying the type of winning combination (symbol combination) that can be won if the corresponding symbol stops on the effective line in the reel to be stopped and controlled.

Next, the main CPU 101 sets the winning operation flag storage area (S648). Next, the main CPU 101 performs the compressed data storage process described with reference to FIG. 84 (S649). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the winning operation flag data that can be won in the symbol-corresponding winning operation table to the corresponding storage area in the winning operation flag storage area.

For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the symbol combinations (combinations) that can be won are shown in FIGS. 28 to 28 to FIG. As shown in 30, the combination names "C_2nd_A_01", "C_2nd_A_01" and "C_SP1_01" defined in the second storage area, and the combination names "C_9 sheets C_01" to "C_9 sheets C_03" defined in the third storage area, "C_9 sheets C_07" to "C_9 sheets C_09" and "C_9 sheets E_01", combination names defined in the fourth storage area "C_RB role A_01", "C_RB role A_02", "C_RB role B_01" to "C_RB role B_04" , "C_RB role C_01" and "C_RB role C_02", combination names defined in the sixth storage area "C_reach eye lip C_01" to "C_reach eye lip C_03", "C_reach eye lip D_01", "C_ Reach eye lip D_02 "and" C_reach eye lip E_01 ", and the combination name" C_BB1 "defined in the tenth storage area.

After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and the data length of the winning operation flag storage area (12 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and shifts the processing to S626 of the pull-in priority storage processing (see FIG. 100).

[Logical product operation processing]
Next, with reference to FIG. 102, for example, the logical product calculation process performed in S626 during the attraction priority storage process (see FIG. 100) will be described. FIG. 102 is a flowchart showing the procedure of the logical product calculation process. The logical product calculation process shown in FIG. 102 is not only in S626 in the attraction priority storage process (see FIG. 100), but also in S687 in the attraction priority acquisition process (see FIGS. 103 and 104 described later). Is also executed.

In the logical product calculation process executed in S626 during the attraction priority storage process (see FIG. 100), the two data to be ANDed are stored in the winning operation flag set in S650 during the symbol code acquisition process described above. It is the data of the area and the data of the symbol code storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "12" of the data length (12 bytes) set in S650 during the above-mentioned symbol code acquisition process corresponds to the "number of logical products" described later.

On the other hand, in the logical product operation process executed in S687 in the attraction priority acquisition process (see FIGS. 103 and 104 described later), the two data to be ANDed are the hit (retract) request flag storage area. Data and data of the winning operation flag storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag described later corresponds to the "logical product number" described later.

First, the main CPU 101 acquires the logical product source data (for example, the data of the symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and saves the calculation result as the logical product destination data (S662).

Next, the main CPU 101 adds 1 to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is "0" (S666).

In S666, when the main CPU 101 determines that the number of logical products is not "0" (when the determination in S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is "0" (when the determination in S666 is YES), the main CPU 101 ends the logical product calculation process and stores the process, for example, in the pull-in priority order. The process moves to S627 of the process (see FIG. 100).

[Pull-in priority acquisition process]
Next, the attraction priority acquisition process performed in S627 during the attraction priority storage process (see FIG. 100) will be described with reference to FIGS. 103 and 104. It should be noted that FIGS. 103 and 104 are flowcharts showing the procedure of the attraction priority acquisition process.

First, the main CPU 101 determines whether or not it is time to check the right reel 3R (specific display column) (S671).

When the main CPU 101 determines in S671 that it is not the time to check the right reel 3R (when the determination in S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S671, when the main CPU 101 determines that it is the time to check the right reel 3R (when the determination in S671 is YES), the main CPU 101 "ANY combination" in the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (a combination of predetermined symbols) is included (S672). The "ANY combination" here means a combination in which the winning is confirmed regardless of at least the stop symbol of the right reel 3R (at least the winning combination in which the stop symbol of the right reel 3R is an arbitrary symbol).

In S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination does not include the "ANY combination" (when the determination in S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes the "ANY combination" (when the determination in S672 is YES), the main CPU 101 determines that the "ANY combination" in the winning operation flag storage area. The storage area corresponding to the "combination" is masked (S673). Specifically, the main CPU 101 sets "1" in the bit corresponding to the "ANY combination" in the winning operation flag storage area. If the "ANY combination" is not specified for the symbol combination (winning combination) related to the internal winning combination, the processes of S671 to S673 may not be required. Further, when the "ANY combination" defines the stop symbol of the left reel 3L or the middle reel 3C as an arbitrary symbol, the processing of S672 and S673 is performed even when the left reel 3L or the middle reel 3C is checked. It may be performed (the same applies to the processes of S681 to S683 described later).

After the processing of S673, or when S671 or S672 is determined to be NO, the main CPU 101 sets "1" to the address of the last storage area as the address of the winning operation flag storage area (see FIGS. 28 to 30). The added address is set, the stop prohibition data is set, and the winning operation flag data length (data length of the winning operation flag storage area: 12 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation is detected. Further, the operation stop button operation state is acquired by referring to the operation stop button storage area (see FIG. 33).

Next, the main CPU 101 subtracts (updates -1) the address of the set winning operation flag storage area by 1 (S676). Next, the main CPU 101 generates hit request flag data from the set winning operation flag storage area and the corresponding hit request flag storage area (see FIGS. 28 to 30), and the generated hit request flag data. The prohibited winning operation position is generated based on (S677).

Next, the main CPU 101 determines whether or not the stop operation position is the prohibited winning operation position (S678).

In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning operation position (when the determination in S678 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S678, when the main CPU 101 determines that the stop operation position is the prohibited winning operation position (when the determination in S678 is YES), the value of the stop button operation counter of the main CPU 101 is the value of the third stop. Whether or not it is determined (S679).

In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when the determination in S679 is YES), the main CPU 101 performs the process of S705 described later. On the other hand, in S679, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the third stop (when the determination in S679 is NO), the value of the stop button operation counter of the main CPU 101 is the second stop. It is determined whether or not it is a value (S680).

In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the second stop (when the determination in S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S680, when the main CPU 101 determines that the value of the stop button operation counter is the value of the second stop (when the determination in S680 is YES), whether or not the main CPU 101 is after the right reel 3R is stopped. (S681).

In S681, when the main CPU 101 determines that the right reel 3R has been stopped (when the determination in S681 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S681, when the main CPU 101 determines that the right reel 3R has not been stopped (when the determination in S681 is NO), the main CPU 101 has a flag that the hit request flag may be interfered with by the "ANY combination". It is determined whether or not (whether or not "ANY combination" is not included in the symbol combination (winning combination) related to the internal winning combination) (S682).

In S682, when the main CPU 101 determines that the hit request flag is not a flag that may be interfered with by the "ANY combination" (when the determination in S682 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be interfered with by the "ANY combination" (when the determination in S682 is NO), the main CPU 101 currently checks "ANY". It is determined whether or not it is time to check the hit request flag including the "combination" (S683).

In S683, when the main CPU 101 determines that the current check is at the time of checking the hit request flag including the "ANY combination" (when the determination in S683 is YES), the main CPU 101 performs the process of S705 described later.

On the other hand, in S683, when the main CPU 101 determines that the current check is not at the time of checking the hit request flag including "ANY combination" (when S683 is NO determination), when S678 or S680 is NO determination, or S681. Alternatively, when the determination in S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning operation flag data length is “0” (S685).

In S685, when the main CPU 101 determines that the winning operation flag data length is not "0" (when the determination in S685 is NO), the main CPU 101 returns the processing to the processing of S676 and repeats the processing after S676.

On the other hand, in S685, when the main CPU 101 determines that the winning operation flag data length is "0" (when the determination in S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). .. In this process, for example, the main CPU 101 performs the logical product operation process described with reference to FIG. 102. In the logical product operation process executed in the process of S686, as described above, the data of the hit (pull-in) request flag storage area is set in the "logical product destination data", and the data of the winning operation flag storage area is set. It is set in the "logical product source data", and the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag is set in the "logical product count". The RT operation combination display flag is a storage area in which the symbol combination related to the RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 11 is defined as shown in FIGS. 28 to 30. Become.

Next, the main CPU 101 refers to the pull-in priority table address storage area and acquires the pull-in priority table (S687). In this process, the initial value "1 (001H)" of the attraction priority data is set to the currently set address, and any of the attraction priority table numbers "00" to "05" shown in FIG. 27. The pull-in priority table is acquired.

Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is the end code (000H) (S688).

In S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is the end code (when the determination in S688 is YES), the main CPU 101 uses S705, which will be described later. Is processed. On the other hand, in S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is not the end code (when the determination in S688 is NO), the main CPU 101 operates the winning operation. The flag storage area is set (S689).

Next, the main CPU 101 acquires the attraction priority data based on the attraction priority table stored in the currently set address (S690). Next, the main CPU 101 sets the block counter of the pull-in priority table (S691). In the present embodiment, in this process, the main CPU 101 sets "2" to the value of the block counter in the pull-in priority table.

Next, the main CPU 101 sets the number of checks of the attraction priority table, and adds 1 (+1 update) to the address of the attraction priority table to be referred to (S692). In the present embodiment, in this process, the main CPU 101 sets "8" to the number of checks in the pull-in priority table.

Next, the main CPU 101 acquires check data based on the updated address of the pull-in priority table, and extracts check bits from the check data (S693). In the present embodiment, the check bit extracted here corresponds to bit 0 of the check data. For example, in the process of S690, when the attraction priority data "03EH" is acquired from the attraction priority table of the attraction priority table number "00" shown in FIG. 27, in the process of S693, "10001000B" is used as the check data. Is acquired, and "0" is extracted as the value of the check bit.

Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

In S694, when the main CPU 101 determines that the value of the extracted check bit is not "1" (when the determination in S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S694, when the main CPU 101 determines that the value of the extracted check bit is "1" (when the determination in S694 is YES), the main CPU 101 adds 1 to the address of the reference pull-in priority table. (+1 update), and based on the updated address, the determination data is acquired from the pull-in priority table (S695).

Next, the main CPU 101 determines whether or not the currently acquired winning operation flag data is the determination target based on the determination data acquired in S695 (S696). In this process, the main CPU 101 compares the currently acquired winning operation flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In that case, it is determined that the currently acquired winning operation flag data is the determination target.

In S696, when the main CPU 101 determines that the winning operation flag data is not the determination target (when the determination in S696 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S696, when the main CPU 101 determines that the winning operation flag data is the determination target (when the determination in S696 is YES), the main CPU 101 updates the attraction priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set attraction priority data with the attraction priority data associated with the determination data acquired in S697.

Next, the main CPU 101 updates the check data (S698). In this process, the main CPU 101 shifts the check data by one bit to the right (direction from bit 7 to bit 0). In this process, "0" is set in the bit 7 of the check data after the shift.

After the processing of S698, or when S694 or S696 is determined to be NO, the main CPU 101 determines whether or not there is a bit to be checked (a bit in which "1" is set) in the check data (S699).

In S699, when the main CPU 101 determines that there is no bit to be checked in the check data (when the determination in S699 is NO), the main CPU 101 performs the process of S702 described later. On the other hand, in S699, when the main CPU 101 determines that the check data has a bit to be checked (when the determination in S699 is YES), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update). ), And the number of checks is subtracted by 1 (S700).

Next, the main CPU 101 determines whether or not the number of checks is "0" (S701). In S701, when the main CPU 101 determines that the number of checks is not "0" (when the determination in S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

On the other hand, in S701, when the main CPU 101 determines that the number of checks is "0" (when the determination in S701 is YES), the main CPU 101 sets the number of checks to the address of the winning operation flag storage area currently referred to. The initial value "8" is added to update the address of the winning operation flag storage area, and the value of the block counter is subtracted by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is "0" (S703).

In S703, when the main CPU 101 determines that the value of the block counter is not "0" (when the determination in S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is "0" (when the determination in S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to (+1 update). ) (S704). For example, when the attraction priority table currently referred to is the attraction priority table of the attraction priority table number “00” shown in FIG. 27, the attraction priority table to be referred to is changed to FIG. 27 by this process. It is changed to the pull-in priority table of the above-mentioned pull-in priority table number "01". Then, after the processing of S704, the main CPU 101 returns the processing to the processing of S688, and repeats the processing after S688.

Here, returning to the processing of S679, S683 or S688 again, if S679, S683 or S688 is a YES determination, the main CPU 101 uses the attraction order data set at this time as the final attraction priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets "0 (00H)" as the final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data "0 (00H)", no pull-in data (stop prohibition) is set. Then, after the processing of S705, the main CPU 101 ends the attraction priority acquisition process, and shifts the process to S628 of the attraction priority storage process (see FIG. 100).

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 74) will be described with reference to FIG. 105. Note that FIG. 105 is a flowchart showing the procedure of the reel stop control process.

First, the main CPU 101 performs a reel stop enable signal OFF process (S711). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal OFF data. Further, this process is performed using the non-standard work area of the main RAM 103.

Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not the speed has reached a "constant speed") (S712). In S712, when the main CPU 101 determines that the rotation speeds of all reels are not "constant speed" (when the determination in S712 is NO), the main CPU 101 repeats the process of S712.

On the other hand, in S712, when the main CPU 101 determines that the rotation speeds of all the reels have reached "constant speed" (when the determination in S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal ON data. Further, this process is performed using the non-standard work area of the main RAM 103.

Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

In S714, when the main CPU 101 determines that the valid stop button has not been pressed (when the determination in S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, in S714, when the main CPU 101 determines that a valid stop button has been pressed (when the determination in S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 33), and the stop button is not yet pressed. The value of the operation counter is subtracted by 1 (S715).

Next, the main CPU 101 determines the search target reel from the operation stop button (S716). Further, in this process, the address (start address) set process of the rotation cylinder control data storage area in which the reel control management information of the search target reel is stored is also performed.

Next, the main CPU 101 performs a reel stop enable signal OFF process (S717). Similar to S711, this process is performed using the non-standard work area of the main RAM 103. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

Next, the main CPU 101 performs a reel stop selection process (S719). Although detailed description is omitted, in this process, the main CPU 101 performs a process of selecting the number of sliding pieces.

Next, the main CPU 101 determines a scheduled stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined stop scheduled position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding pieces to the stop start position, and sets the addition result as the stop scheduled position.

Next, the main CPU 101 executes the symbol code storage process (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) based on the value of the stop button non-operation counter, and the value of the stop button non-operation counter is set. When it is "0", it is determined that the reel to be controlled is the reel of the final stop.

In S722, when the main CPU 101 determines that the reel to be controlled is not the reel of the final stop (when the determination in S722 is NO), the main CPU 101 performs the control change process (S723). In this process, the stop information group used for stopping the reel is updated when the reel is at a specific stop position. Next, the main CPU 101 performs the attraction priority storage process described with reference to FIG. 100 (S724).

Next, the main CPU 101 performs a stop interval remaining time standby process (S725). In this process, the main CPU 101 performs a standby process until a preset predetermined reel stop interval time elapses. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing after S711.

Here, returning to the process of S722 again, when the main CPU 101 determines in S722 that the reel to be controlled is the reel of the final stop (when the determination in S722 is YES), the main CPU 101 excites all the reels. Determines whether or not is in the stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all reels is not in the stopped state (when the determination in S726 is NO), the main CPU 101 repeats the process of S726.

On the other hand, in S726, when the main CPU 101 determines that the excitation of all reels is in the stopped state (when the determination in S726 is YES), the main CPU 101 keeps the stop button operated for the third stop in the ON state. It is determined whether or not (the stop button is not released) (S727). In S727, when the main CPU 101 determines that the stop button operated by the third stop operation remains in the ON state (when the determination in S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, in S727, when the main CPU 101 determines that the stop button operated by the third stop operation is not in the ON state (when the determination in S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. Move to S214 of the main flow (see FIG. 74).

[Prize search process]
Next, with reference to FIG. 106, the winning search process performed in S214 in the main flow (see FIG. 74) will be described. Note that FIG. 106 is a flowchart showing the procedure of the winning search process.

First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 35) to the corresponding storage area of the winning operation flag storage area (see FIGS. 28 to 30). (S761). Then, at the end of this processing, the address at the end of the winning operation flag storage area is set in the DE register.

Next, the main CPU 101 sets the address of the payout number data table (not shown) that defines the payout number (see FIGS. 28 to 30) of the winning combination (symbol combination) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables (for example, "5" in this embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

Next, the main CPU 101 sets the data of the number of medals to be paid out (in this embodiment, any one of 1, 2, 3, and 9) in the C register based on the address set in the HL register. , The determination target data is set in the A register, and "2" is added (+2 update) to the address set in the HL register (S764). In the payout number data table, the data of the payout number of medals is defined as, for example, "payout number (1, 2, 3 or 9) * 2 + 0". Further, in the following, the data "0" in the data "number of medals to be paid out (1, 2, 3 or 9) * 2 + 0" set in the C register will be referred to as a "judgment bit". This determination bit is information indicating whether or not the block is the determination target block of the winning search.

Next, the main CPU 101 extracts the value of the determination bit from the data of the number of medals to be paid out set in the C register (S765). Next, the main CPU 101 determines whether or not the block is a determination target block based on the value of the extracted determination bit (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is "1". In the present embodiment, regardless of the number of medals to be paid out, the value of the determination bit is always defined as "0", so that the processing of S766 is always a NO determination.

In S766, when the main CPU 101 determines that the block is not the determination target block (when the determination in S766 is NO), the main CPU 101 performs the process of S768 described later. On the other hand, in S766, when the main CPU 101 determines that the block is the determination target block (when the determination in S766 is YES), the main CPU 101 subtracts 1 from the address of the winning operation flag storage area set in the DE register (-). 1 update) (S767).

After the processing of S767 or when the determination in S766 is NO, the main CPU 101 extracts the data of the storage area specified by the address of the winning operation flag storage area set in the DE register as the determination data (S768).

Next, the main CPU 101 determines whether or not the determination result is a prize based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a prize.

In S769, when the main CPU 101 determines that the result of the determination is not a prize (when the determination in S769 is NO), the main CPU 101 performs the process of S776 described later. On the other hand, in S769, when the main CPU 101 determines that the result of the determination is a prize (when the determination in S769 is YES), the main CPU 101 has three current games (a game in which the number of medals bet is three). ) (S770).

In S770, when the main CPU 101 determines that the current game is a three-card game (when the determination in S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, in S770, when the main CPU 101 determines that the current game is not a three-card game (when the determination in S770 is NO), the main CPU 101 pays out a two-card game (a game in which the number of medals bet is two). The number of sheets (2 sheets) is set in the C register (S771).

After the processing of S771 or when the determination in S770 is YES, the main CPU 101 updates the number of payouts (S772). Specifically, the main CPU 101 adds the number of medals to be paid out set in the C register to the current value of the winning number counter, and sets the added value to the number of payouts.

Next, the main CPU 101 determines whether or not the value of the number of payouts is less than the maximum number of payouts "10" (S773).

In S773, when the main CPU 101 determines that the value of the number of payouts is less than the maximum number of payouts "10" (when the determination in S773 is YES), the main CPU 101 performs the process of S775 described later. On the other hand, in S773, when the main CPU 101 determines that the value of the number of payouts is not less than the maximum number of payouts "10" (when the determination in S773 is NO), the main CPU 101 sets the maximum number of payouts "10" to the number of payouts. (S774).

After the processing of S774 or when the determination in S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

After the processing of S775 or when the determination in S769 is NO, the main CPU 101 determines whether or not there is another prize (S776). In S776, when the main CPU 101 determines that there is another prize (when the determination in S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

On the other hand, in S7776, when the main CPU 101 determines that there is no other prize (when the determination in S776 is NO), the main CPU 101 subtracts 1 (updates -1) the value of the prize search counter (S777). In addition, as in the present embodiment, when there is only one effective line, since a plurality of small winning combinations are not duplicated and won a prize, the determination process of S776 is always a NO determination.

Next, the main CPU 101 determines whether or not the value of the winning search counter is "0" (S778).

In S778, when the main CPU 101 determines that the value of the winning search counter is not "0" (when the determination in S778 is NO), the main CPU 101 returns the processing to the processing of S764 and repeats the processing after S764. On the other hand, in S778, when the main CPU 101 determines that the value of the winning search counter is "0" (when the determination in S778 is YES), the main CPU 101 ends the winning search process and performs the process in the main flow (FIG. FIG. (Refer to 74), the process proceeds to S215.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 74) will be described with reference to FIG. 107. Note that FIG. 107 is a flowchart showing the procedure of the illegal hit check process. An illegal hit is a special prize winning number and a small winning combination winning number (internal winning combination) that are drawn by the internal lottery process (see FIG. 82) and stored in the winning number storage area by the symbol setting process (see FIG. 83). Based on this, it is a term indicating that the left reel 3L, the middle reel 3C, and the right reel 3R are stopped on the effective line with a combination of symbols that cannot be established (symbol combination is not established).

First, the main CPU 101 sets the address of the winning operation flag storage area (see FIGS. 28 to 30) (S781). Next, the main CPU 101 sets the size of the winning operation flag storage area (the number of bytes, “12” in the present embodiment) to the value of the check counter (S782).

Next, the main CPU 101 is based on the address of the winning operation flag storage area currently set, and the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storage area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored in the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

In this synthesis process, the main CPU 101 first obtains the exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data). Next, the main CPU 101 obtains the logical product of the calculated exclusive OR calculation result and the winning combination data (winning operation flag data), and uses the calculated logical product as the synthesis result. If no illegal hit error has occurred, the value of this synthesis result is "0".

Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the synthesis process of S784 (S785).

In S785, when the main CPU 101 determines that an illegal hit error has not occurred (NO in S785), the main CPU 101 updates the address of the winning operation flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is "0" (S788).

In S788, when the main CPU 101 determines that the value of the check counter is not "0" (when the determination in S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is "0" (when the determination in S788 is YES), the main CPU 101 ends the illegal hit check process and performs the process in the main flow (FIG. FIG. (Refer to 74), the process proceeds to S216.

Here, returning to the processing of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (when the determination in S785 is YES), the main CPU 101 performs the error processing described with reference to FIG. 80. (S789). By this process, the two-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6 is used to display the two characters "EE" indicating the occurrence of an illegal hit error as error information. Error display data is output. The state in which the illegal hit error occurs (error state) is released by pressing the reset switch 76 (see FIG. 6).

Next, the main CPU 101 clears the value of the winning number counter and the data of the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 74).

In this embodiment, as shown in FIGS. 28 to 30, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning operation flag storage area arranged in the main RAM 103 at the time of combining the winning combination of the winning operation flag storage area and the internal winning combination can have the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of synthesizing the data of the winning combination and the data of the internal winning combination) is simply a logical product of the data of the winning combination and the data of the internal winning combination. It is obtained by executing (for example, executing with the "AND" instruction). As a result, in the present embodiment, the illegal hit check process can be made more efficient and simplified, the free space of the main control program can be secured (increased), and the increased free space can be used for playability. It becomes possible to increase.

[Prize check / medal payout process]
Next, with reference to FIG. 108, the winning check / medal payout process performed in S216 in the main flow (see FIG. 74) will be described. Note that FIG. 108 is a flowchart showing the procedure of winning check / medal payout processing.

First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub-control circuit 200. The winning operation command is configured to include a parameter for specifying a winning operation flag (display combination) and the like.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 68 (S802). By this process, the winning operation command data is stored in the communication data storage area provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115.

Next, the main CPU 101 determines whether or not the value of the winning number counter is "0" (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is "0" (when the determination in S803 is YES), the main CPU 101 ends the winning check / medal payout process, and performs the process in the main flow (when the winning check / medal payout process is completed). (Refer to FIG. 74), the process proceeds to S217.

On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not "0" (when the determination in S803 is NO), the main CPU 101 has the maximum number of medals credited (stored). In the embodiment, it is determined whether or not the number is 50 or more (S804).

In S804, when the main CPU 101 determines that the number of credits for medals is not equal to or greater than the upper limit (when the determination in S804 is NO), the main CPU 101 adds "1" to the value of the credit counter (updates +1). S805). The added value of the credit counter is displayed by a 2-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). The details of the medal payout number check process will be described later with reference to FIG. 109 described later.

Next, the main CPU 101 determines whether or not the payout of medals has been completed (S807). In S807, when the main CPU 101 determines that the medal payout has been completed (when the determination in S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 74). Move to the processing of S217.

On the other hand, in S807, when the main CPU 101 determines that the payout of medals has not been completed (when the determination in S807 is NO), the main CPU 101 performs a payout interval standby process (S808). In this process, the main CPU 101 waits until the preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt process (1.1172 msec cycle) described later in FIG. 114) elapses. Wait. Then, after the processing of S808, the main CPU 101 returns the processing to the processing of S803, and repeats the processing after S803.

Here, returning to the process of S804 again, when the main CPU 101 determines in S804 that the number of credits for medals is equal to or greater than the upper limit (50) (when the determination in S804 is YES), the main CPU 101 determines. The medal payout process is performed (S809). By this process, the medals that are not stored as the number of credits are paid out. In the process of S809, the processes of S806 to 806 may be repeated every time one medal is paid out until the payout of medals is completed. Then, after the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 74).

[Check process for paying out medals]
Next, with reference to FIG. 109, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 108) will be described. Note that FIG. 109 is a flowchart showing the procedure of the medal payout number check process.

First, the main CPU 101 adds (+1 update) to the value of the medal OUT counter (S811). The medal OUT counter is a counter for counting the number of times the medal is paid out. Next, the main CPU 101 adds (+1 update) to the value of the payout number counter (S812). The payout number counter is a counter for counting the payout number of medals.

Next, the main CPU 101 performs a payout number 7SEG display process (S813). In this process, the main CPU 101 performs a control process of displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

Next, the main CPU 101 performs an update process of the winning combination end number counter (S814). In addition, in the counter for the number of end-of-roles, the number of payouts that can be paid out in the bonus game when the bonus game starts is the number of coins that can be paid out in the bonus game when the bonus combination wins (the combination of symbols "C_BB1" or "C_BB2" is available). It is a counter that is set (see FIG. 110 described later), counts the remaining number of medals to be paid out during the bonus game, and determines the end of the bonus game (see S822 of FIG. 110 described later). In this process, the main CPU 101 compares the value of the combination end number counter with the lower limit value “0”, and if the value of the combination end number counter is larger than the lower limit value “0”, the combination end number counter. The value of the counter is subtracted by 1 (updated by -1), and when the value of the winning combination end number counter is equal to or less than the lower limit value "0", the value of the winning combination ending number counter is held at "0". The number of payouts set in the combination end number counter does not mean the number actually paid out to the player. For example, 216 is set in the combination end number counter and the combination end number counter is 215. If 9 cards are won in this state, the actual number of cards to be paid out will be 225. The number-of-commitment counter becomes "0" after 216 sheets are paid out, and thereafter, the lower limit "0" of the value of the number-of-commitment counter is maintained.

Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub-control circuit 200. The credit information command is configured to include a parameter for specifying the number of credits for medals.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 68 (S817). By this process, the credit information command data is stored in the communication data storage area provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process described later with reference to FIG. 115. Then, after the process of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 during the winning check / medal payout process (see FIG. 108).

[BB check process]
Next, the BB check process performed in S217 in the main flow (see FIG. 74) will be described with reference to FIG. 110. Note that FIG. 110 is a flowchart showing the procedure of the BB check process.

First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). In S821, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S821 is NO), the main CPU 101 performs the process of S831 described later.

On the other hand, in S821, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S821 is YES), is the main CPU 101 having a value of "0" or less for the number of consecutive ends? Whether or not it is determined (S822). In S822, when the main CPU 101 determines that the value of the winning combination end number counter is not "0" or less (when the determination in S822 is NO), the main CPU 101 ends the BB check process and performs the process in the main flow (FIG. (Refer to 74), the process proceeds to S218.

On the other hand, in S822, when the main CPU 101 determines that the value of the winning combination end number counter is "0" or less (when the determination in S822 is YES), the main CPU 101 performs the bonus end processing (S823). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the on state.

Next, the main CPU 101 refers to the CT lottery table at the end of the bonus (see FIG. 60) and performs the CT lottery at the end of the bonus (S824). Next, the main CPU 101 determines whether or not the CT lottery at the end of the bonus has been won (S825).

In S825, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S825 is NO), the main CPU 101 performs the process of S827 described later. On the other hand, in S825, when the main CPU 101 determines that the CT lottery has been won (when the determination in S825 is YES), the main CPU 101 adds "1" to the number of CT sets (S826). If the CT lottery is won when the number of ART sets is "0", "1" is added to the number of CT sets and "1" is also added to the number of ART sets in the processing of S826. ..

After the processing of S826 or when the determination in S825 is NO, the main CPU 101 determines whether or not the number of ART sets or the number of CT sets is "1" or more (S827).

In S827, when the main CPU 101 determines that the number of ART sets or the number of CT sets is "1" or more (when the determination in S827 is YES), the main CPU 101 sets the ART preparation state in the game state of the next game. (S828). Then, after the processing of S828, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S218 in the main flow (see FIG. 74).

On the other hand, in S827, when the main CPU 101 determines that the number of ART sets or the number of CT sets is not "1" or more (when the determination in S827 is NO), the main CPU 101 sets the normal game state to the game state of the next game. (S829). Next, the main CPU 101 draws the lottery state of CZ with reference to the normal medium-high probability lottery table (see FIG. 40B), and sets the lottery result (S830). Then, after the processing of S830, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S218 in the main flow (see FIG. 74).

Here, returning to the process of S821 again, when the determination in S821 is NO, the main CPU 101 determines whether or not the symbol combination related to the BB combination (the symbol combination of the combination "C_BB1" or "C_BB2") is displayed. (S831). In S831, when the main CPU 101 determines that the symbol combination related to the BB combination is not displayed (when the determination in S831 is NO), the main CPU 101 ends the BB check process and performs the process in the main flow (see FIG. 74). Move on to the processing of S218 inside.

On the other hand, in S831, when the main CPU 101 determines that the symbol combination related to the BB combination is displayed (when the determination in S831 is YES), the main CPU 101 refers to the bonus type lottery table (see FIG. 58) and gives a bonus. The type is drawn and the lottery result is set (S832). Next, the main CPU 101 sets a predetermined value (the number of payouts that triggers the end of the bonus: “216” in the present embodiment) to the value of the counter for the number of ends of the winning combination (S833).

Next, the main CPU 101 performs a bonus start processing (S834). In this process, the main CPU 101 performs various processes necessary for starting the operation of the bonus, such as setting a bonus state in the game state of the next game. Then, after the processing of S834, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S218 in the main flow (see FIG. 74).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 74) will be described with reference to FIGS. 111 and 112. 11 and 112 are flowcharts showing the procedure of RT check processing.

First, the main CPU 101 determines whether or not the RT state is the RT5 state (S841). In S841, when the main CPU 101 determines that the RT state is the RT5 state (when the determination in S841 is YES), the main CPU 101 ends the RT check process and performs the process in S219 in the main flow (see FIG. 74). Move to the processing of.

On the other hand, in S841, when the main CPU 101 determines that the RT state is not the RT5 state (when the determination in S841 is NO), the main CPU 101 determines whether or not the RT state is the RT0 state (S842). In S842, when the main CPU 101 determines that the RT state is not the RT0 state (when the determination in S842 is NO), the main CPU 101 performs the process of S845 described later.

On the other hand, in S842, when the main CPU 101 determines that the RT state is the RT0 state (when the determination in S842 is YES), the main CPU 101 displays the symbol combination of the abbreviation "bell spilled eyes" (see FIG. 28). It is determined whether or not it is (S843). In S843, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is not displayed (when the determination in S843 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. (Refer to 74), the process proceeds to S219.

On the other hand, in S843, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is displayed (when the determination in S843 is YES), the main CPU 101 sets the RT2 state flag to the ON state (S844). .. By this process, the RT state shifts from the RT0 state to the RT2 state. Then, after the processing of S844, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

Here, returning to the process of S842 again, when the determination in S842 is NO, the main CPU 101 determines whether or not the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (when the determination in S845 is NO), the main CPU 101 performs the process of S850 described later.

On the other hand, in S845, when the main CPU 101 determines that the RT state is the RT1 state (when the determination in S845 is YES), the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eye" is displayed. (S846).

In S846, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eye" is displayed (when the determination in S846 is YES), the main CPU 101 sets the RT1 state flag to the off state and sets the RT2 state flag. Is set to the on state (S847). By this process, the RT state shifts from the RT1 state to the RT2 state. Then, after the processing of S847, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

On the other hand, in S846, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is not displayed (when the determination in S846 is NO), the main CPU 101 determines whether or not 20 games have passed in the RT1 state. (S848).

In S848, when the main CPU 101 determines that 20 games in the RT1 state have not elapsed (NO in S848), the main CPU 101 ends the RT check process and performs the process in the main flow (see FIG. 74). ) Moves to the processing of S219. On the other hand, in S848, when the main CPU 101 determines that 20 games have passed in the RT1 state (when the determination in S848 is YES), the main CPU 101 sets the RT1 state flag to the off state (S849). By this process, the RT state shifts from the RT1 state to the RT0 state. Then, after the processing of S849, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

Here, returning to the process of S845 again, when S845 is a NO determination, the main CPU 101 determines whether or not the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (when the determination in S850 is NO), the main CPU 101 performs the process of S853 described later.

On the other hand, in S850, when the main CPU 101 determines that the RT state is the RT2 state (when the determination in S850 is YES), the main CPU 101 displays the symbol combination (see FIG. 28) of the abbreviation "RT3 transition lip". It is determined whether or not it is (S851). In S851, when the main CPU 101 determines that the symbol combination of the abbreviation "RT3 transition lip" is not displayed (when the determination in S851 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. (Refer to 74), the process proceeds to S219.

On the other hand, in S851, when the main CPU 101 determines that the symbol combination of the abbreviation "RT3 transition lip" is displayed (when the determination in S851 is YES), the main CPU 101 sets the RT2 state flag to the off state and RT3. The state flag is set to the on state (S852). By this process, the RT state shifts from the RT2 state to the RT3 state. Then, after the processing of S852, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

Here, returning to the process of S850 again, when the determination in S850 is NO, the main CPU 101 determines whether or not the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (when the determination in S853 is NO), the main CPU 101 performs the process of S862 described later.

On the other hand, in S853, when the main CPU 101 determines that the RT state is the RT3 state (when the determination in S853 is YES), the main CPU 101 displays the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip". It is determined whether or not it has been done (S854).

In S854, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (when the determination in S854 is YES), the main CPU 101 sets the RT3 state flag to the off state. At the same time, the RT2 state flag is set to the on state (S855). By this process, the RT state shifts from the RT3 state to the RT2 state. Then, after the processing of S855, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

On the other hand, in S854, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is not displayed (when the determination in S854 is NO), the main CPU 101 has the abbreviation "RT4 transition". It is determined whether or not the symbol combination (see FIG. 28) of "Rip" is displayed (S856).

In S856, when the main CPU 101 determines that the symbol combination of the abbreviation "RT4 transition lip" is not displayed (when the determination in S856 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (when it is determined as NO). (Refer to FIG. 74), the process proceeds to S219. On the other hand, in S856, when the main CPU 101 determines that the symbol combination of the abbreviation "RT4 transition lip" is displayed (when the determination in S856 is YES), the main CPU 101 sets the RT3 state flag to the off state and RT4. The state flag is set to the on state (S857). By this process, the RT state shifts from the RT3 state to the RT4 state.

After the process of S857, the main CPU 101 determines whether or not the game state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the gaming state is not the ART ready state (when the determination in S858 is NO), the main CPU 101 ends the RT check process and performs the process in S219 in the main flow (see FIG. 74). Move to the processing of.

On the other hand, in S858, when the main CPU 101 determines that the gaming state is the ART preparation state (when the determination in S858 is YES), the main CPU 101 determines whether or not the number of CT sets is "1" or more. (S859).

In S859, when the main CPU 101 determines that the number of CT sets is "1" or more (when the determination in S859 is YES), the main CPU 101 sets CT in the game state of the next game and sets the CT game number counter. Set "8" (S860). Then, after the processing of S860, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

On the other hand, in S859, when the main CPU 101 determines that the number of CT sets is not "1" or more (when the determination in S859 is NO), the main CPU 101 sets the normal ART in the game state of the next game, and the ART end game. A predetermined value is set in the number counter (S861). Then, after the processing of S861, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

Here, returning to the process of S853 again, when the determination in S853 is NO, the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (S862). In S862, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eye" or "RT2 transition lip" is not displayed (when the determination in S862 is NO), the main CPU 101 ends the RT check process. , The process is transferred to the process of S219 in the main flow (see FIG. 74).

On the other hand, in S862, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (when the determination in S862 is YES), the main CPU 101 turns off the RT4 state flag. At the same time, the RT2 state flag is set to the on state (S863). By this process, the RT state shifts from the RT4 state to the RT2 state. Then, after the processing of S863, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

[Processing at the end of CZ / ART]
Next, with reference to FIG. 113, the CZ / ART end-time processing performed in S219 in the main flow (see FIG. 74) will be described. Note that FIG. 113 is a flowchart showing a procedure for processing at the end of CZ / ART.

First, the main CPU 101 determines whether or not the current gaming state is at the time of CZ failure or at the end of ART (S871). In S871, when the main CPU 101 determines that the current gaming state is neither at the time of CZ failure nor at the end of ART (when the determination of S871 is NO), the main CPU 101 ends the processing at the end of CZ / ART. The process is transferred to the process of S201 in the main flow (see FIG. 74).

On the other hand, in S871, when the main CPU 101 determines that the current gaming state is either when the CZ fails or when the ART ends (when the determination in S871 is YES), the main CPU 101 uses the CZ lottery table (see FIG. 41B). ), The CZ pullback lottery is performed (S872). Next, the main CPU 101 determines whether or not the CZ pull-back lottery has been won (S873).

In S873, when the main CPU 101 determines that the CZ pull-back lottery has been won (when the determination in S873 is YES), the main CPU 101 sets the winning type CZ in the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type of CZ in the CZ game number counter (S875). Then, after the processing of S875, the main CPU 101 ends the processing at the end of CZ / ART, and shifts the processing to the processing of S201 in the main flow (see FIG. 74).

On the other hand, in S873, when the main CPU 101 determines that the CZ pull-back lottery has not been won (when the determination in S873 is NO), the main CPU 101 sets the normal game state to the game state of the next game (S876). Next, the main CPU 101 draws the lottery state of CZ with reference to the normal medium-high probability lottery table (see FIG. 40B), and sets the lottery result (S877). Then, after the processing of S877, the main CPU 101 ends the processing at the end of CZ / ART, and shifts the processing to the processing of S201 in the main flow (see FIG. 74).

[Interrupt processing controlled by the main CPU (1.1172 msec)]
Next, with reference to FIG. 114, the interrupt process performed by the main CPU 101 at a cycle of 1.1172 msec will be described. Note that FIG. 114 is a flowchart showing the procedure of the interrupt process. The interrupt process repeatedly executed in a cycle of 1.1172 msec is generated based on the output timing of the timeout signal of the timer circuit 113 set in the initialization process of the timer circuit 113 (PTC) (see S2 in FIG. 64). This is a process executed when the interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

First, the main CPU 101 performs a register save process (S901). Next, the main CPU 101 performs an input port check process (S902). In this process, various switches such as a start switch 79 and a stop switch connected via an external bus interface 104, index sensors (not shown) provided on each of the left reel 3L, the middle reel 3C, and the right reel 3R, etc. The signals input from various sensors are checked. In the present embodiment, these various switches and various sensors pass through the cabinet side relay board 44, the door relay terminal board 68, the reel relay terminal board 74, etc., and the input port IC (not) via the external bus interface 104. It is connected to the input terminal of the input IC connected to the output terminal (shown in the figure). Further, in the main RAM 103, an input port storage area (not shown) for the main CPU 101 to store the state of the input port IC (simply referred to as "input port" in this embodiment) connected to the external bus interface 104. ) Is assigned. Here, the input port storage area includes, for example, an input port storage area 1 for storing the current state of the input port and an input port storage area 2 for storing the state of the input port before the interrupt processing. Consists of. Then, in this process, the main CPU 101 first stores various information stored in the input port storage area 1 in the input port storage area 2, and then stores various information read from the input port in the input port storage area 1. do. The connection configuration of various switches and various sensors and the configuration of the input port storage area are not limited to those described above. That is, the configuration may be such that the main CPU 101 can recognize the on / off states of various switches and various sensors.

Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotating the left reel 3L, the middle reel 3C, and the right reel 3R when all the reels are requested to start rotating, and then each reel rotates at a constant speed. Drive and control three stepping motors. When the number of sliding pieces is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding pieces. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the scheduled stop position (the symbol at the scheduled stop position reaches the area on the effective line of the display window) of the corresponding reel. The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

Next, the main CPU 101 performs a communication data transmission process (S904). In this process, various commands stored in the communication data storage area are mainly transmitted to the sub-control circuit 200 via the first serial communication circuit 114 (see FIG. 8) of the main control circuit 90. The details of the communication data transmission process will be described later with reference to FIG. 115 described later.

Next, the main CPU 101 performs a insertion medal passage check process (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed the selector 66 based on the detection result (medal sensor input state) of each medal sensor (see FIG. 5).

Next, the main CPU 101 performs a 7-segment LED drive process (S906). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6, and displays, for example, the number of medals paid out, the number of credits, the stop button pressing order data, and the like. The details of the 7-segment LED drive process will be described later with reference to FIG. 117 described later.

Next, the main CPU 101 performs a timer update process (S907). In this process, the main CPU 101 performs a count (subtraction) process of various set timers. The details of the timer update process will be described later with reference to FIG. 119 described later.

Next, the main CPU 101 performs an error detection process (S908). Next, the main CPU 101 performs a door open / close check process (S909). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on (door closed) / off (door open) state of the door open / close monitoring switch 67.

Next, the main CPU 101 performs a test firing test signal control process (S910). In this process, control process is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed using the non-standard work area (see FIG. 11C) of the main RAM 103. In the present embodiment, this process is also performed at a time other than the test firing test (after the pachislot machine 1 is installed in the game store), but at this time, the main control board 71 passes through the second interface boat or the like. Since it is not connected to the testing machine, various test signals are generated but not output.

Next, the main CPU 101 performs a register reset process (S911). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[Communication data transmission processing]
Next, with reference to FIG. 115, the communication data transmission process performed in S904 during the interrupt process (see FIG. 114) will be described. Note that FIG. 115 is a flowchart showing the procedure of the communication data transmission process.

First, the main CPU 101 performs the WDT setting process (S961). In this process, the main CPU 101 performs a process of restarting the WDT in the reset controller 106 and the like. The details of the WDT setting process will be described later with reference to FIG. 116 described later.

Next, the main CPU 101 determines whether or not the command transmission start timer has counted up (S962). That is, the main CPU 101 determines whether or not the transmission of communication data is being delayed. In S962, when the main CPU 101 determines that the command transmission start timer has not counted up (when the determination in S962 is NO), the main CPU 101 ends the communication data transmission process and interrupts the process (FIG. 114). (See) Move to the process of S905 in.

On the other hand, in S962, when the main CPU 101 determines that the command transmission start timer has counted up (when the determination in S962 is YES), the main CPU 101 determines whether or not the communication data has been transmitted (S963). .. Specifically, the main CPU 101 refers to the data stored in the command status register (not shown) of the first serial communication circuit 114 (SCU1), and if the data indicating the completion of transmission is stored, the communication data. Determines that the transmission is completed, and if the data indicating the transmission completion is not stored, it is determined that the communication data has not been transmitted.

In S963, when the main CPU 101 determines that the communication data has not been transmitted (NO in S963), the main CPU 101 ends the communication data transmission process and interrupts the process (see FIG. 114). Move to the processing of S905 inside. On the other hand, in S963, when the main CPU 101 determines that the communication data has been transmitted (YES in S963), the main CPU 101 performs the communication data acquisition process (S964). In this process, the main CPU 101 performs a process of acquiring communication data (command data) from the communication data storage area of the main RAM 103.

Next, the main CPU 101 determines whether or not there is untransmitted data in the acquired communication data (S965). In S965, when the main CPU 101 determines that there is untransmitted data in the acquired communication data (when the determination in S965 is YES), the main CPU 101 performs the process of S969 described later.

On the other hand, in S965, when the main CPU 101 determines that there is no untransmitted data in the acquired communication data (when the determination in S965 is NO), the main CPU 101 sets the non-operation command data in each register (S966). ). The non-operation command data is information related to the player's game operation (for example, input operation, start operation, stop operation, etc. as an operation for advancing the game) (for example, these operations have been performed). Each parameter is set so as not to include the information indicating the above, or, for example, the information indicating the internal winning combination determined based on the start operation). Note that each parameter of the non-operation command data includes, for example, a parameter indicating the on / off state of each switch in the pachislot 1 and a parameter indicating the on / off state of each sensor (for example, the input port storage area 1). And the information stored in the input port storage area 2) may be set. As a result, the possibility of malfunction or failure of these switches and sensors may be determined on the sub-control circuit 200 side.

Next, the main CPU 101 performs a communication data storage process (see FIG. 68) (S967). That is, the main CPU 101 performs a process of storing the non-operation command data generated in S966 in the communication data storage area of the main RAM 103. Next, the main CPU 101 performs a communication data acquisition process (S968). That is, the main CPU 101 performs a process of acquiring non-operation command data stored in the communication data storage area in S967.

As described above, in the present embodiment, at least no operation command is transmitted for each interrupt process (see FIG. 114) even when there is no communication data to be transmitted from the main control circuit 90 to the sub control circuit 200. It has become like. Therefore, it is possible to prevent unauthorized communication data from being transmitted from the outside due to the absence of communication data to be transmitted from the main control circuit 90 to the sub control circuit 200. From this point of view, the non-operation command data does not include information related to the player's game operation, but the content of each parameter to be set is not limited to this and can be changed as appropriate. Is.

After the processing of S968 or when the determination in S965 is YES, the main CPU 101 sets the buffer size for one packet in the transmission counter (S969). In the present embodiment, since the transmission data for one packet is 8 bytes, the buffer size for one packet is also composed of 8 bytes. Further, in the present embodiment, when a plurality of communication data (command data) are stored in the communication data storage area, they are transmitted in the order in which they are stored (first in the oldest storage) (FIFO format). ..

Next, the main CPU 101 acquires transmission data from the communication buffer and sets it in the transmission data register (S970). Specifically, the main CPU 101 sets the transmission data in the transmission data register (not shown) of the first serial communication circuit 114 (SCU1) in 1-byte units. As a result, the set transmission data is transferred to the transmission shift register (not shown) of the first serial communication circuit 114 (SCU1), and is transmitted one packet at a time.

Next, the main CPU 101 updates (+1) the address of the communication buffer (S971). Next, the main CPU 101 subtracts "1" from the transmission counter (S972). Next, the main CPU 101 determines whether or not the transmission counter is "0" (S973). That is, the main CPU 101 determines whether or not the transmission of the transmission data for one packet is completed. In S973, when the main CPU 101 determines that the transmission counter is not "0" (when the determination in S973 is NO), the main CPU 101 returns the processing to the processing of S970 and repeats the processing after S970.

On the other hand, in S973, when the main CPU 101 determines that the transmission counter is "0" (when the determination in S973 is YES), the main CPU 101 performs a communication data pointer update process (see, for example, FIG. 69) (S974). ). Then, after the processing of S974, the main CPU 101 ends the communication data transmission processing, and shifts the processing to the processing of S905 in the interrupt processing (see FIG. 114).

[WDT setting process]
Next, with reference to FIG. 116, the WDT setting process performed in S961 during the communication data transmission process (see FIG. 115) will be described. Note that FIG. 116 is a flowchart showing the procedure of the WDT setting process.

First, the main CPU 101 sets the address of the WDT clear register (not shown) in the WDT in the reset controller 106 (S981). Next, the main CPU 101 sets clear data (for example, "55H") at the set address (S982). Next, the main CPU 101 sets the restart data (for example, "AAH") at the set address (S983).

Next, the main CPU 101 compares the command transmission start timer with its lower limit value "0", and if the command transmission start timer is larger than the lower limit value "0", the command transmission start timer is subtracted by 1 (-1 update). If the command transmission start timer is equal to or less than the lower limit value "0", the command transmission start timer is held at "0" (S984). Then, after the processing of S984, the main CPU 101 ends the WDT setting processing, and shifts the processing to the processing of S962 of the communication data transmission processing (see FIG. 115).

As described above, in the present embodiment, the WDT reset setting and management information (WDT permission / prohibition, reference clock, timeout time (for example, 419.4 ms), etc.) are stored in the program management area, and S982 and By performing the process of S983, the set timeout time is remeasured. When a reset signal is output due to a timeout and the main CPU 101 is restarted, the checksum generation process (FIG. 70) is restarted without executing the power failure (external) process (see FIG. 70). The sum value calculated by (see 71) is not stored in the main RAM 103 (sum value storage area). Therefore, in this case, the thumb check determination result in the power-on processing (see S11 in FIG. 64) is not normal (that is, as "RAM error"), and an error occurs in the information display 6 (7-segment LED display). The character string "88" indicating the occurrence is displayed.

[7-segment LED drive processing]
Next, with reference to FIG. 117, the 7-segment LED drive process performed in S906 during the interrupt process (see FIG. 114) will be described. Note that FIG. 117 is a flowchart showing the procedure of the 7-segment LED drive process.

First, the main CPU 101 adds (+1 update) to the value of the interrupt counter (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when the determination in S922 is NO), the main CPU 101 ends the 7-segment LED drive process and interrupts the process (see FIG. 114). ) Moves to the processing of S907. That is, in the present embodiment, the 7-segment LED drive process is performed every two interruption cycles. In the present embodiment, an example of executing the 7-segment LED drive process when the value of the interrupt counter is even has been described, but the present invention is not limited to this, and the 7-segment LED drive process is not limited to this when the value of the interrupt counter is odd. The LED drive process may be executed, or the execution timing of the 7-segment LED drive process may be determined by using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

On the other hand, in S922, when the main CPU 101 determines that the value of the interrupt counter is an odd number (when the determination in S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

Next, the main CPU 101 performs a 7-segment display data generation process (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 118 described later.

Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets the address of the credit display data storage area for storing the credit display data output to each cathode of the 7-segment LED (S927).

Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 118 described later.

Next, the main CPU 101 sets the address of the 7-segment common counter storage area for storing the value of the 7-segment common counter described later (S929). Next, the main CPU 101 adds (+1 update) to the value of the 7-segment common counter (S930). In this process, when the updated 7-segment common counter value becomes "8", the main CPU 101 sets the 7-segment common counter value to "0". In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 times.

Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and addresses the target cathode data storage area (push order display data storage area or target storage area in the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed in order to temporarily turn off the 7-segment LED to eliminate the influence of the afterimage.

Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED drive processing, and shifts the processing to the processing of S907 in the interrupt processing (see FIG. 114).

[7-segment display data generation process]
Next, with reference to FIG. 118, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 117) will be described. Note that FIG. 118 is a flowchart showing the procedure of the 7-segment display data generation process.

The "display data" described later generated in the 7-segment display data generation process performed in S925 during the 7-segment LED drive process (see FIG. 117) corresponds to the push-order display data, and the 7-segment LED drive process (FIG. 117). The "display data" described later, which is generated in the 7-segment display data generation process performed in S928 in (see 117), corresponds to the credit display data.

First, the main CPU 101 divides the display data set in the cathode data storage area by "10", acquires the quotient value of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and divides the data. The remaining value of the result is acquired as the display data of the lower digit (S941). Next, the main CPU 101 determines whether or not to display the upper digit based on the acquired display data of the upper digit (S942).

In S942, when the main CPU 101 determines that the upper digit display is to be performed (when the determination in S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, in S942, when the main CPU 101 determines that the upper digit is not displayed (when the determination in S942 is NO), the main CPU 101 sets no display of the upper digit (S943).

After the processing of S943 or when the determination in S942 is YES, the main CPU 101 refers to the 7-segment cathode table (not shown) and acquires the display data of the upper digit (S944). Next, the main CPU 101 saves the acquired high-order digit display data in the high-order digit display data storage area (not shown) (S945).

Next, the main CPU 101 refers to the 7-segment cathode table (not shown) and acquires the display data of the lower digits (S946). Next, the main CPU 101 saves the acquired low-order digit display data in the low-order digit display data storage area (not shown) (S947).

Then, after the processing of S947, the main CPU 101 ends the 7-segment display data generation processing. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 117), the main CPU 101 changes the process to the process of S926 during the 7-segment LED drive process. Transfer. On the other hand, when the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 117), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. ..

[Timer update process]
Next, the timer update process performed in S907 during the interrupt process (see FIG. 114) will be described with reference to FIG. 119. Note that FIG. 119 is a flowchart showing the procedure of the timer update process.

First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the number of 2-byte timers in the B register (S951). The 2-byte timer storage area is used to manage a time of 286 ms (256 × 1.1172 ms) or more (that is, a timer value exceeding 1 byte).

Next, the main CPU 101 compares the number of 2-byte timers with the lower limit value "0", and if the number of 2-byte timers is larger than the lower limit value "0", subtracts 1 from the number of 2-byte timers (updates -1). When the number of 2-byte timers is equal to or less than the lower limit value "0", the number of 2-byte timers is held at "0" (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 updates) the update start address of the 2-byte timer storage area set in the HL register. Note that, for example, since the command transmission start timer also has a 2-byte timer, the update may be performed in this process (see FIG. 116).

Next, the main CPU 101 subtracts (updates -1) the number of 2-byte timers set in the B register by 1 (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is "0" (S954).

In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not "0" (when the determination in S954 is NO), the main CPU 101 returns the processing to the processing of S952, and after S952. Repeat the process.

On the other hand, in S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is "0" (when the determination in S954 is YES), the main CPU 101 stores the 1-byte timer in the HL register. The update start address of is set, and the number of 1-byte timers is set in the B register (S955). The 1-byte timer storage area is used to manage the time less than 286 ms (256 × 1.1172 ms) (that is, the timer value not exceeding 1 byte). For example, the medal monitoring timer is updated as a 1-byte timer.

Next, the main CPU 101 compares the number of 1-byte timers with the lower limit value "0", and if the number of 1-byte timers is larger than the lower limit value "0", subtracts 1 from the number of 1-byte timers (-1 update). However, when the number of 1-byte timers is equal to or less than the lower limit value "0", the number of 1-byte timers is held at "0" (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 1-byte timers set in the B register by 1 (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is "0" (S958).

In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not "0" (when the determination in S958 is NO), the main CPU 101 returns the processing to the processing of S956, and after S956. Repeat the process.

On the other hand, in S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is "0" (when the determination in S958 is YES), the main CPU 101 performs an electromagnetic counter control process (S959). ). In this process, an output control process is performed when a signal indicating IN / OUT of the medal is output to the external centralized terminal plate 47. Then, after the processing of S959, the main CPU 101 ends the timer update processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 114).

<Explanation of operation when the power is turned on>
Next, with reference to FIG. 120, the operation of the pachi-slot machine according to the embodiment of the present invention when the power is turned on will be described. FIG. 120 is a timing chart showing an example of the operation of the pachi-slot machine 1 when the power is turned on.

In FIG. 120, "Main CPU" indicates the main CPU 101 (main control circuit 90), and "SubCPU" indicates the sub CPU 201 (sub control circuit 200).

Further, in FIG. 120, the operating state "security mode" of the "Main CPU" indicates the state of being in the above-mentioned security mode, and the operating state "startup delay period" of the "Main CPU" is described above after the end of the security mode. Indicates the period until the command transmission start timer is set and the set command transmission start timer becomes "0" (that is, the period during which the setting can be changed but the transmission of communication data is delayed). The operation state "normal operation period" of the "Main CPU" indicates a state in which the delay in the transmission of the communication data has ended and the communication data can be transmitted to the sub CPU 201 (sub control circuit 200).

Further, in FIG. 120, the operating state "initialization" of the "SubCPU" is the initialization (startup) process (hard boot time, bios (driver) initialization, kernel) when the power of the sub CPU 201 (sub control circuit 200) is turned on. (OS) booting, etc.) indicates a state (that is, a state in which communication data transmitted from the main CPU 101 (main control circuit 90) cannot be received), and the operating state "normal operating period" of the "SubCPU" is It shows a state in which the initialization (startup) process at the time of turning on the power is completed and the communication data transmitted from the main CPU 101 (main control circuit 90) can be received.

Further, in FIG. 120, in the "setting operation A", the setting change is started in the "startup delay period" (for example, the power of the pachislot 1 is turned on while the setting key type switch 54 is on), and then "normally". The operation when the setting change is completed in the "operation period" is shown, and the "transmission mode A" is the setting change command (setting change / setting confirmation start) (COM1) and the setting change in the case of the "setting operation A". Indicates the transmission timing of the command (setting change / setting confirmation end) (COM2). Further, in the "Main CPU setting change process" under the "transmission mode A", the setting change command is the communication of the main RAM 103 in the setting change confirmation process (see FIG. 66) by the main CPU 101 in the case of the "transmission mode A". The timing of storage (registration) in the data storage area (see also the setting change command generation storage process in FIG. 67 and the communication data storage process in FIG. 68) is shown.

Further, in FIG. 120, in the "setting operation B", the setting change is started in the "startup delay period" (for example, the power of the pachislot 1 is turned on while the setting key type switch 54 is on), and then the "setting operation B" is described. The operation when the setting change is completed in the "startup delay period" is shown, and the "transmission mode B" is the setting change command (setting change / setting confirmation start) (COM1) and the setting in the case of the "setting operation B". Indicates the transmission timing of the change command (setting change / setting confirmation end) (COM2). Further, in the "Main CPU setting change process" under the "transmission mode B", the setting change command is the communication of the main RAM 103 in the setting change confirmation process (see FIG. 66) by the main CPU 101 in the case of the "transmission mode B". The timing of storage (registration) in the data storage area (see also the setting change command generation storage process in FIG. 67 and the communication data storage process in FIG. 68) is shown.

When the power of the pachi-slot machine 1 is turned on and a reset signal is input, the operating state of the security mode is controlled by the security unit (not shown) of the microprocessor 91. In the security mode, the main CPU 101 is delayed in starting for a period corresponding to the setting stored in the security setting area. When the security mode ends, the main CPU 101 delays the transmission of communication data for a predetermined period. The main CPU 101 can change the setting even when the transmission of communication data is delayed.

Here, as shown in "setting operation A", when the setting change is started during the delay in the transmission of the communication data and the setting change is completed after the delay in the transmission of the communication data is completed, the main CPU 101 communicates. When the delay in data transmission ends, the setting change command (setting change / setting confirmation start) (COM1) is transmitted to the sub-control circuit 200, and when the setting change is completed, the setting change command (setting) (Change / setting confirmation end) (COM2) is transmitted to the sub-control circuit 200.

On the other hand, as shown in "setting operation B", when the setting change is started during the delay in the transmission of the communication data and the setting change is completed during the delay in the transmission of the communication data, the main CPU 101 uses the communication data. When the transmission delay ends, the setting change command (setting change / setting confirmation start) (COM1) and the setting change command (setting change / setting confirmation end) (COM2) are sequentially transmitted to the sub-control circuit 200. .. That is, when the delay in transmitting the communication data ends, the setting change command (setting change / setting confirmation start) (COM1) and the setting change command (setting change / setting confirmation end) (COM2) are sent to the communication data storage area. If registered, these communication data are transmitted in the registered order.

As described above, according to the pachi-slot machine 1 of the present embodiment, by delaying the start-up of the main CPU 101 when the power of the pachi-slot machine 1 is turned on, the main control circuit 90 can be started stably and the main CPU 101 is started. By delaying the transmission of the communication data after the delay is completed, the time required for starting the sub-control circuit 200 can be secured and the sub-control circuit 200 can be started stably.

Then, after the delay in starting the main CPU 101 is completed, the setting can be changed even before the delay in transmitting the communication data is completed. Therefore, for example, when opening a store in a game store, a pachislot machine is used. When the power of 1 is turned on (that is, when a reset signal is input accordingly), the setting can be changed in advance without waiting for the completion of starting the sub-control circuit 200, so that the setting can be changed at the time of turning on the power. It is possible to improve the work efficiency in.

Further, if the setting change is made before the delay of the transmission of the communication data ends, the communication data indicating these is registered at the start of the setting change or the end of the setting change, and the delay of the transmission of the communication data is delayed. Since these communication data are transmitted in the order in which they are registered when the operation is completed, even if the setting is changed in advance without waiting for the completion of the activation of the sub-control circuit 200. As a result, it is possible to prevent a discrepancy in the information held between the main control circuit 90 and the sub control circuit 200. Further, for example, even when the sub control circuit 200 is configured to determine fraudulent activity, error, or the like according to the order of communication data transmitted from the main control circuit 90, the result of such determination is obtained. It is possible to make an accurate judgment without affecting the above.

Further, according to the pachi-slot machine 1 of the present embodiment, when the communication data transmission process is performed, at least no operation command data is transmitted even if the communication data is not registered. For example, it is possible to prevent communication data from being transmitted from the outside by an unauthorized means such as illegally accessing the connection line between the main control circuit 90 and the sub control circuit 200. Further, since the registration / transmission of the non-operation command data is not performed before the delay in the transmission of the communication data is completed, it is possible to reduce the control load when the power of the pachislot 1 is turned on. From the viewpoint of preventing fraudulent activity, the non-operation command data may not include information related to the player's game operation.

Further, according to the pachi-slot machine 1 of the present embodiment, the delay period for starting the main CPU 101 is composed of a fixed period and a variable period, and these periods (or a range thereof) can be appropriately selected and set. Therefore, it is possible to set an appropriate delay time according to the specifications of the main control circuit 90 and the sub control circuit 200. From the viewpoint of shortening the period until the setting can be changed, it is possible to set a predetermined period range (for example, "no setting" in the random extension period) in which 0 is always determined as the variable period. In that case, the range of the predetermined period may be set.

In this embodiment, an example will be described in which a setting value setting operation (setting change operation) is possible during a period in which the transmission of communication data is delayed (“startup delay period”) after the end of the security mode. However, the operations that can be executed during the period in which the transmission of communication data is delayed (“startup delay period”) are not limited to this. For example, the setting key type switch 54 is turned on during the period in which the power of the pachislot machine 1 is turned on while the setting key type switch 54 is off and the transmission of communication data is delayed (“startup delay period”). In this case, the setting value confirmation operation (setting confirmation operation) may be enabled during the period. As a result, for example, when opening a game store, even if the setting is not changed but the current setting value is to be confirmed, the setting confirmation is performed in advance without waiting for the start completion of the sub-control circuit 200. Since this can be done, it is possible to improve the work efficiency when the power is turned on.

<Explanation of operation when inserting medals>
Next, with reference to FIG. 121, the operation of the pachislot machine according to the embodiment of the present invention at the time of inserting medals will be described. FIG. 121 is a timing chart showing an example of the operation of the pachi-slot machine 1 when inserting medals.

In FIG. 121, the “start switch” indicates the start switch 79, and the “medal sensor” is the detection state of the upstream medal sensor (first medal sensor) 806 and the downstream medal sensor (second medal sensor) 807. (Medal sensor input state), the "medal acceptance signal" indicates that the on state ("ON") indicates that the medal acceptance is permitted (medal acceptance permission), and the off state ("OFF") indicates the medal. Indicates a state in which the reception of medals is prohibited (see FIGS. 75 and 76).

Further, in FIG. 121, the “solenoid” indicates the solenoid of the selector 66 (the drive source that shifts the select plate 804 to the guide position or the discharge position), and the “monitoring timer” indicates the medal monitoring timer (FIGS. 75 and FIG. (Refer to 76), the "operating state" is a state in the pachislot machine 1 that enables the progress of the game after the start operation ("during the game") and a state that does not allow the progress of the game after the start operation ("game wait"). "), And.

When the number of medals that can start the game (three in this embodiment) is inserted, the main CPU 101 can accept the start operation for the start lever 16. As shown in FIG. 121, in this state, if medals can be stored as the number of credits (if the number of credits is less than 50), until the start operation for the start lever 16 is performed (started by the start switch 79). Until the operation is detected), the state in which the medal acceptance is permitted (the state in which the medal acceptance signal is "ON") continues. Although not shown, in this state, if medals cannot be stored as the number of credits (if the number of credits is 50), the acceptance of medals is prohibited (the medal acceptance signal is "OFF". It has changed to the state).

In the main CPU 101, a start operation (first start on the left side in FIG. 121) is performed by the start switch 79 in a state where the number of medals that can start the game (three in this embodiment) is inserted and the medals can be stored as the number of credits. When an operation (transition of the start switch 79 from "OFF" to "ON") is detected as "start operation A"), the medal acceptance is permitted (the medal acceptance signal is "ON"). It shifts from a certain state) to a state where medal acceptance is prohibited (a state where the medal acceptance signal is "OFF"), starts shifting the solenoid of the selector 66 to a demagnetized state, and monitors with a medal monitoring timer (a state). Measurement) is started. At this time, the above-mentioned start lever ON flag is turned on.

When a medal is inserted during monitoring (measurement) by the medal monitoring timer (that is, before the solenoid of the selector 66 completes the transition from the excited state to the degaussed state), the main CPU 101 inputs the medal sensor of each medal sensor. When it is determined that medals have been inserted based on the state), the inserted medals are counted by changing the solenoid of the selector 66, which was in the process of changing from the excited state to the degaussed state, to the excited state again. It is guided into the hopper device 51. Further, in this case, the "start operation A" is detected by the start switch 79, but based on the detection, the operation state is changed to the state in which the game can proceed after the start operation ("during the game"). Do not change. At this time, the above-mentioned start lever ON flag is turned off. That is, in this case, "start operation A" is invalidated.

In the main CPU 101, when a medal is inserted during monitoring (measurement) by the medal monitoring timer (that is, before the transition from the excited state to the demagnetized state of the solenoid of the selector 66 is completed), the medal of each medal sensor is inserted. When it is determined that a medal has been inserted based on the sensor input status), the acceptance of medals is further permitted from the state in which the acceptance of medals is prohibited (the state in which the medal acceptance signal is "OFF"). It may be changed to a state (a state in which the medal reception signal is "ON").

After that, the main CPU 101 again presses the start operation 79 (in FIG. 121, the second start operation on the right side (transition of the start switch 79 from "OFF" to "ON") is referred to as "start operation B"). When is detected, the solenoid of the selector 66 is changed from the excited state to the degaussed state again, and monitoring (measurement) by the medal monitoring timer is started again. At this time, the start lever ON flag described above is turned on again.

Then, when the main CPU 101 does not insert medals during monitoring (measurement) by the medal monitoring timer (that is, before the solenoid of the selector 66 completes the transition from the excited state to the degaussed state), the main CPU 101 does not insert medals (of each medal sensor). When it is not determined that a medal has been inserted based on the medal sensor input state), the operating state is completed after the monitoring (measurement) by the medal monitoring timer is completed (that is, after the solenoid of the selector 66 has been transferred from the excited state to the degaussed state). Is changed to a state that enables the progress of the game after the start operation (“during the game”), and the game can be progressed (that is, after the medal reception / start check process (see FIGS. 75 and 76)). Executes the processing of).

Although not shown, the main CPU 101 detects the "start operation A" by the start switch 79 and is permitted to accept medals (the medal acceptance signal is "ON"). The reception of medals is prohibited (the medal reception signal is "OFF"), the solenoid of the selector 66 is changed to the demagnetized state, and monitoring (measurement) by the medal monitoring timer is started. Later, during monitoring (measurement) by the medal monitoring timer (that is, before the transition from the excited state to the demagnetized state of the solenoid of the selector 66 is completed), if no medal is inserted (medal sensor input state of each medal sensor). Even when it is not determined that a medal has been inserted based on the above), as in the case where "start operation B" is detected by the start switch 79, after monitoring (measurement) by the medal monitoring timer is completed (that is, the solenoid of the selector 66 is excited) After the transition from the state to the demagnetized state is completed, the operating state is changed to a state that enables the progress of the game after the start operation (“during the game”), and the game can be progressed (that is, the medal reception). -The processing after the start check processing (see FIGS. 75 and 76) can be executed).

As described above, according to the pachi-slot machine 1 of the present embodiment, when the game is started with the start operation of the player, for example, a medal monitoring timer for preventing the occurrence of "swallowing" of medals is provided. It is set. By this medal monitoring timer, in the selector 66, the inserted medals are discharged to the outside of the game machine from the state where the inserted medals are stored inside the game machine (the state where the select plate 804 is in the guide position due to the solenoid being excited). The time until the select plate 804 is physically transferred to the state (the state in which the select plate 804 is in the discharge position due to the solenoid being in the degaussed state) is secured.

If a medal is inserted during monitoring (measurement) by the medal monitoring timer, the start operation that is the basis of the medal is invalidated, and in the selector 66, the inserted medal is placed inside the gaming machine. Return to the stored state. Therefore, it is possible to prevent the occurrence of "swallowing" of medals and appropriately process the inserted medals.

Further, according to the pachi-slot machine 1 of the present embodiment, even if a medal is inserted during monitoring (measurement) by the medal monitoring timer, the medal is counted, so that the inserted medal can be counted. It is possible to prevent omission of counting and to process the inserted medals more appropriately.

Further, according to the pachi-slot machine 1 of the present embodiment, the timer value of the medal monitoring timer (for example, “72”) is changed from the state in which the inserted medals are stored inside the game machine to the state in which the inserted medals are discharged to the outside of the game machine. Since the period until the physical transition (for example, 80 ms) or more (for example, "72" x 1.1172 ms) is set, the occurrence of "swallowing" of medals is surely prevented. Therefore, it becomes possible to process the inserted medals more appropriately. When the drive unit is a solenoid as in the present embodiment, such an effect becomes more remarkable.

<Various deformation examples>
The configuration and operation of the gaming machine of the present invention according to the present embodiment have been described above, including their effects. However, the invention according to the present embodiment is not limited to the above-described embodiment, and includes various other embodiments and modifications as long as the gist of the invention according to the present embodiment is not deviated.

[Another example of granting benefits]
In the pachi-slot machine 1 of the above embodiment, since the notification content is controlled based on the result of the flag conversion lottery performed on the main side, the symbol combination displayed is different when the stop operation is performed according to the notification. That is, in the above embodiment, an example in which whether or not to grant the privilege is determined based on the result of the flag conversion lottery performed on the main side has been described, but the present invention is not limited to this. For example, on the main side (main control board 71), the privilege may be given based on the actually displayed symbol combination.

In this case, the main control board 71 (main CPU 101) gives a privilege when a predetermined symbol combination is displayed according to the notification performed according to the result of the flag conversion lottery, and when the notification is not followed, the main control board 71 (main CPU 101) gives a privilege. , Even if a predetermined symbol combination is displayed, the privilege may not be given. In the pachislot machine 1 of the above embodiment, the symbol combinations displayed according to the pressing order are different, but even when the player ignores the notification and performs the stop operation, the symbol combinations related to the abbreviation "triple chili lip" are used. There is a possibility that a special symbol combination such as, etc. will be displayed. Therefore, in this example, even if the notification is ignored and a special symbol combination is displayed, the privilege is given only when the special symbol combination is displayed according to the notification without giving the privilege. You may.

[Another example of normal ART and CT termination conditions]
Normally, the termination conditions for ART and CT are not limited to the examples described in the above embodiments, and any termination conditions can be adopted. For example, the number of medals awarded during normal ART or CT, the number of times a unit game is digested during normal ART or CT, the number of times information is notified that is advantageous to the player during normal ART or CT, When the predetermined number of games (for example, 50 games) is set as one set, the end condition such as the number of sets and the continuation rate at the end of one set can be adopted.

Further, as a method for counting the number of medals given during normal ART or CT, for example, a method for counting the number of medals paid out in a unit game may be adopted, or a method of counting the number of medals paid out in a unit game may be adopted. A method of counting the difference number (net increase number) obtained by subtracting the number of bets (multiplications) of the medals used in the unit game from the number of medals played may be adopted. Further, as a method for counting the number of medals given during normal ART or CT, a method of calculating based on the actually increased medals (calculation based on the actual value) may be adopted, or has the number actually increased? Regardless of whether or not, a method of calculating based on the number of medals scheduled to increase when following the notification (calculation based on an ideal value) may be adopted.

Further, depending on the type of internal winning combination, a configuration in which the number of medals granted is not increased, that is, a configuration in which the number of medals that is the end condition of the number of medals granted or the difference is not counted may be adopted. .. For example, even if a part of the winning combination (rare role) with a low probability of being determined as the internal winning combination or a combination in which the display / non-display of the symbol combination is switched according to the timing of the stop operation is determined as the internal winning combination. , The number of medals granted may not be increased or decreased (counted).

[others]
The content of the notification normally performed during ART or CT is not limited to the above-mentioned example, and is arbitrary. For example, the order of stop operations (pushing order) in which a special symbol combination that is advantageous to the player is displayed may be notified, or the timing of the stop operation required for displaying the symbol combination ( The symbol to be aimed at) may be notified.

As an advantageous state for the player, the winning probability of the internal winning combination related to the re-game does not change (or changes within a range that does not affect the game playability), but the mode of the stop operation that is advantageous for the player. It may be in a gaming state in which the notification function, that is, the AT function is activated. Further, as an advantageous state for the player, a re-game high probability state (replay time) in which the winning probability of the internal winning combination related to the re-game is high is activated, and a mode of the stop operation advantageous for the player is notified. It may be in a gaming state in which the function is activated, that is, the ART function is activated.

Further, in the above-described embodiment and various modifications, the pachi-slot machine has been described as an example of the gaming machine, but the gaming machine to which the invention according to the present embodiment can be applied is not limited to this. For example, features other than the features peculiar to pachislot, such as features related to reel stop control based on a stop operation, can be applied to a gaming machine called "pachinko", and the same effect can be obtained.

[Other expandability of gaming machines according to the present embodiment]
In the pachislot 1 of the present embodiment, the player's medal insertion operation (that is, the operation of inserting the hand-held medal into the medal insertion slot 14 or the credited medal is inserted into the MAX bet button 15a or the 1-bet button 15b. If the game is started by (operation of inserting) and the medal is paid out when the game is finished, the hopper device 51 is driven to pay out the medal from the medal payout outlet 24, or credit. The form to be used has been described, but the present invention is not limited to this.

For example, the present invention is applied to all forms in which a player inputs a game medium necessary for a game, a game is performed based on the game medium, and a privilege is given (for example, a medal is paid out) based on the result of the game. be able to. That is, not only the game medium is input (hanged) and the game medium is paid out by the physical movement of the player, but also the main control circuit 90 (main control board 71) itself is the game medium owned by the player. It may be possible to play a game without a medal by electromagnetically managing the above. Further, it may be a game medium management device that is mounted (connected) to the main control circuit 90 (main control board 71) and manages the game medium to electromagnetically manage the game medium owned by the player. ..

In this case, the game medium management device is a device having a ROM and an RWM (or RAM) and provided in the game machine, and bidirectionally communicates with an external game medium handling device (not shown) via a predetermined interface. It is connected so that it can be connected, and a prize is awarded for the operation of lending the game medium (that is, the operation of providing the game medium necessary for the player to perform the operation of inserting the game medium) or the role of paying out the game medium (that is, the operation of providing the game medium). When the combination is established), the game medium payout operation (that is, the action of making the player acquire the game medium necessary for paying out the game medium), or the game medium to be used for the game. It suffices that the operation of recording electromagnetically can be performed. Further, the game medium management device not only manages the actual number of game media, but also displays the number of game media held on the front surface of the pachislot machine 1, for example, based on the management result of the number of game media. A number display device (not shown) may be provided to manage the number of game media displayed on the possessed game medium number display device. That is, the game medium management device may be capable of recording and displaying the total number of game media that the player can use for the game by an electromagnetic method.

Further, in this case, the game medium management device has a performance that allows the player to freely transmit a signal indicating the number of recorded game media to an external game medium handling device, and the player. In addition to the case of direct operation, when the number of recorded game media cannot be reduced, and when an external connection terminal plate (not shown) is provided between the device and an external game medium handling device. It is desirable that the player has the ability to transmit a signal indicating the number of recorded game media only through the external connection terminal plate.

In addition to the above, the gaming machine is provided with a lending operating means, a return (settlement) operating means, and an external connection terminal plate that can be operated by the player, and the gaming medium handling device is provided with a slot for valuable value such as banknotes and a recording medium. (For example, IC card) insertion slot, non-contact communication antenna for depositing electronic money from mobile terminals, other operating means such as lending operation means, return operation means, external connection terminal board on the game medium handling device side It may be provided (neither is shown).

As a flow of the game at that time, for example, the player deposits valuable value to the game medium handling device by any method, and subtracts a predetermined number of valuable values based on the operation of any of the above lending operation means. Then, the game medium corresponding to the valuable value subtracted from the game medium handling device to the game medium management device is increased. Then, the player plays a game, and if a game medium is required, the above operation is repeated. After that, a predetermined number of game media are acquired as a result of the game, and when the game is finished, the number of game media is transmitted from the game medium management device to the game medium handling device by operating one of the return operation means, and the game is played. The medium handling device discharges a recording medium on which the number of game media is recorded. The game medium management device clears the number of game media stored by itself when the number of game media is transmitted. The player takes the discharged recording medium to a prize counter or the like for exchanging prizes, or moves the game table to play a game based on the game medium recorded on another table.

In the above example, all the gaming media are transmitted to the gaming media handling device, but only the number of gaming media desired by the player is transmitted on the gaming machine or the gaming media handling device side, and the gaming medium possessed by the player is transmitted. It may be divided and processed. Further, not only the recording medium is discharged, but cash or a cash equivalent may be discharged, or the recording medium may be stored in a mobile terminal or the like. In addition, the game medium handling device may be capable of inserting a member recording medium of the game hall and storing the member recording medium in the member recording medium so that the game can be replayed at a later date.

Further, in the game machine or the game medium handling device, a lock operation for locking the game medium or valuable value data communication can be executed on the game medium handling device or the game medium management device by operating a predetermined operating means (not shown). May be good. In that case, the player may be stored by setting information such as a one-time password that only the player can know, or by an imaging means provided in the game machine or the game medium handling device.

As described above, the game medium management device may be capable of playing games only without a medal, or the game medium is inserted (hanged) by the physical movement of the player, and the game medium is played. It may be a form in which the game is paid out, a form in which the game is possible without a medal, or a form in which the game is possible in both forms. In this case, the game medium management device may adopt a method of directly controlling the selector 66 and the hopper device 51 described above, or these are controlled by the main control circuit 90 (main control board 71). Based on the transmission of the control result, a method is adopted that enables control in which the total number of game media that the player can use for the game is recorded by an electromagnetic method and displayed. You can also.

Further, in the above, the case where the game medium management device is applied to the pachi-slot machine 1 has been described. However, in the slot machine and the enclosed game machine using the above-mentioned game ball, the game medium management device is similarly provided and the player It is also possible to manage the game medium of.

As described above, by providing the above-mentioned game medium management device, it is possible to reduce the number of selectors 66, hopper devices 51, etc. inside the game machine as compared with the case where the game medium is physically used for the game. Not only can the cost and manufacturing cost be reduced, but also the player can be prevented from coming into direct contact with the gaming medium, the gaming environment can be improved, noise can be reduced, and the number of devices can be reduced. It also reduces the power consumption of. In addition, it is possible to prevent fraudulent acts through the game medium and the slot and payout port of the game medium. That is, it is possible to provide a gaming machine that can improve various environments surrounding the gaming machine.

<Supplementary note (summary of the present invention)>
[Game machines with the first to third configurations]
It is known that conventional gaming machines can change the degree of advantage (set value) of a player regarding a game by turning on the power with the setting key switch provided in the game control device turned on. (For example, see JP-A-2006-055444).

Further, in the conventional gaming machine, by delaying the activation of the game control device from the activation of the effect control device (dependent control device), the effect control device reliably receives the command transmitted from the game control device. It is known that this can be done (see, for example, Japanese Patent Application Laid-Open No. 2012-205773).

By the way, in recent years, high-definition such as the image quality of the displayed production image and the sound quality of the output BGM has been advanced for the purpose of further improving the interest in the production. For this reason, the processing at the time of starting the effect control device is complicated, and the amount of data developed at the time of activation is also increased, so that the start-up time of the effect control device is longer than before.

Under such circumstances, it is possible to change the set value (change the setting) by waiting for the start of the effect control device and then trying to start the game control device, as in the game machine of JP2012-205773. For example, when opening a pachinko / pachislot machine, it may be difficult to change the settings even if the power of the pachinko / pachislot machine is turned on. Will occur.

The present invention has been made in view of these points, and an object of the present invention is to provide a gaming machine capable of improving work efficiency when the power is turned on.

In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following first configuration.

A gaming machine (for example, pachislot machine 1) having a game control unit (for example, a main control circuit 90) for controlling a game operation and an effect control unit (for example, a sub control circuit 200) for controlling an effect operation.
The game control unit
An arithmetic processing unit (for example, main CPU 101) that executes various processes for controlling game operations, and
A first storage unit (for example, main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit (for example, main RAM 103) in which information is stored based on the execution of various processes by the arithmetic processing unit, and
A security unit having a security function (for example, a microprocessor 91) and
It is configured to include a serial communication unit (for example, a first serial communication circuit 114) that performs serial communication.
The first storage unit is
A program area (for example, a program area) in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and a management area (for example, a program management area and a security setting area) in which settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means (for example, the communication data storage process shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means (for example, a communication data transmission process shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit.
A transmission delay means (for example, a command transmission start timer) that delays the transmission of communication data by the communication data transmission means for a predetermined period, and
A setting value setting means (for example, a setting key type switch 54) capable of setting a setting value (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game is provided.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means sets the communication data storage area in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 (for example, a setting change command (setting change / setting confirmation start)) can be registered, and when the setting of the setting value by the setting value setting means is completed, the second communication data storage area is set. Communication data (for example, setting change command (setting change / setting confirmation end)) can be registered.
When the delay in transmission of communication data by the transmission delay means is completed, the communication data transmission means registers the first communication data and the second communication data in the communication data storage area. Is a gaming machine characterized by transmitting these communication data in a registered order.

Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following second configuration.

A gaming machine (for example, pachislot machine 1) having a game control unit (for example, a main control circuit 90) for controlling a game operation and an effect control unit (for example, a sub control circuit 200) for controlling an effect operation.
The game control unit
An arithmetic processing unit (for example, main CPU 101) that executes various processes for controlling game operations, and
A first storage unit (for example, main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit (for example, main RAM 103) in which information is stored based on the execution of various processes by the arithmetic processing unit, and
A security unit having a security function (for example, a microprocessor 91) and
It is configured to include a serial communication unit (for example, a first serial communication circuit 114) that performs serial communication.
The first storage unit is
A program area (for example, a program area) in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and a management area (for example, a program management area and a security setting area) in which settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means (for example, the communication data storage process shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means (for example, a communication data transmission process shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit.
A transmission delay means (for example, a command transmission start timer) that delays the transmission of communication data by the communication data transmission means for a predetermined period, and
A setting value setting means (for example, a setting key type switch 54) capable of setting a setting value (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game is provided.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means sets the communication data storage area in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 (for example, a setting change command (setting change / setting confirmation start)) can be registered, and when the setting of the setting value by the setting value setting means is completed, the second communication data storage area is set. Communication data (for example, setting change command (setting change / setting confirmation end)) can be registered.
The communication data transmission means transmits communication data registered in the communication data storage area at regular intervals.
When the delay in transmitting the communication data by the transmission delay means is completed and the first communication data and the second communication data are registered in the communication data storage area, these communication data are stored. Send in the registered order,
When the transmission of communication data is not delayed by the transmission delay means and the communication data is not registered in the communication data storage area, the communication data registration means provides a third communication data storage area. A gaming machine characterized in that the communication data (for example, no operation command) of the above is registered and the registered third communication data is transmitted.

Further, in the gaming machine having the second configuration, the third communication data does not include information related to the gaming operation of the player by the effect control unit.

Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following third configuration.

A gaming machine (for example, pachislot machine 1) having a game control unit (for example, a main control circuit 90) for controlling a game operation and an effect control unit (for example, a sub control circuit 200) for controlling an effect operation.
The game control unit
An arithmetic processing unit (for example, main CPU 101) that executes various processes for controlling game operations, and
A first storage unit (for example, main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit (for example, main RAM 103) in which information is stored based on the execution of various processes by the arithmetic processing unit, and
A security unit having a security function (for example, a microprocessor 91) and
It is configured to include a serial communication unit (for example, a first serial communication circuit 114) that performs serial communication.
The first storage unit is
A program area (for example, a program area) in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and a management area (for example, a program management area and a security setting area) in which settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means (for example, the communication data storage process shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means (for example, a communication data transmission process shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit.
A transmission delay means (for example, a command transmission start timer) that delays the transmission of communication data by the communication data transmission means for a predetermined period, and
A setting value setting means (for example, a setting key type switch 54) capable of setting a setting value (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game is provided.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means sets the communication data storage area in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 (for example, a setting change command (setting change / setting confirmation start)) can be registered, and when the setting of the setting value by the setting value setting means is completed, the second communication data storage area is set. Communication data (for example, setting change command (setting change / setting confirmation end)) can be registered.
When the delay in transmission of communication data by the transmission delay means is completed, the communication data transmission means registers the first communication data and the second communication data in the communication data storage area. Sends these communication data in the registered order,
A fixed period and a variable period can be set as the delay period for starting the arithmetic processing unit by the start delay means.
The game is characterized in that the fixed period can be set to one period from a plurality of periods, and the variable period can be set to a range of one period from a range of a plurality of periods. Machine.

Further, in the gaming machine having the third configuration, the variable period is at least a range of a first period in which 0 is always determined as the variable period and a range in which the variable period is 0 to a predetermined period at random. The range of the second period to be determined and can be set,
A gaming machine characterized in that a range of the first period is set as the variable period.

According to the gaming machines having the first to third configurations, the security unit delays the activation of the arithmetic processing unit, so that the game control unit can be stably activated and the activation of the arithmetic processing unit is delayed. By delaying the transmission of the communication data after the completion of the above, the time required for starting the effect control unit can be secured and the effect control unit can be started stably.

Then, after the delay in starting the arithmetic processing unit is completed, the setting can be changed even before the delay in transmitting the communication data is completed. Therefore, for example, when opening a game in a game store, the setting can be changed. When the power of the gaming machine is turned on (that is, when a reset signal is input along with it), the setting can be changed in advance without waiting for the activation of the effect control unit to be completed. It is possible to improve the work efficiency in.

Further, if the setting change is made before the delay of the transmission of the communication data ends, the communication data indicating these is registered at the start of the setting change or the end of the setting change, and the delay of the transmission of the communication data is delayed. Since these communication data are transmitted in the order in which they are registered when the operation is completed, even if the setting is changed in advance without waiting for the activation of the effect control unit to be completed, it can be changed. It is possible to prevent a discrepancy in the information held between the game control unit and the effect control unit. Further, for example, even if the effect control unit is configured to determine fraudulent acts, errors, etc. according to the order of communication data transmitted from the game control unit, the result of such determination is affected. It is possible to make an accurate judgment without reaching the above.

Further, according to the gaming machine having the second configuration, at least predetermined communication data (third communication data) is used even when the communication data is not registered when the communication data transmission process is performed. Is transmitted, for example, it is possible to prevent communication data from being transmitted from the outside by an unauthorized means such as illegally accessing the connection line between the game control device and the effect control device. It becomes possible. Further, since the registration / transmission of the predetermined communication data is not performed before the delay in the transmission of the communication data is completed, it is possible to reduce the control load when the power of the gaming machine is turned on. From the viewpoint of preventing fraudulent activity, the predetermined communication data may not include information related to the player's game operation.

Further, according to the gaming machine having the third configuration, the delay period for starting the arithmetic processing unit is composed of a fixed period and a variable period, and these periods (or a range thereof) can be appropriately selected and set. Therefore, it is possible to set an appropriate delay time according to the specifications of the game control device and the effect control device. From the viewpoint of shortening the period until the setting can be changed, if it is possible to set a predetermined period range (the range of the first period) in which 0 is always determined as the variable period, it is possible to set. The range of the predetermined period may be set.

[Game machines with 4th to 6th configurations]
In a conventional game machine, when medals can be accepted and the inserted medals are appropriate medals, the inserted medals are counted by the medal sensor and stored inside the game machine. If the inserted medals are not proper medals even if the medals cannot be accepted, or even if the medals can be accepted, the inserted medals will not be counted by the medal sensor and will be sent to the outside of the game machine. A medal sorting device (selector) for discharging is known (see, for example, Japanese Patent Application Laid-Open No. 2006-130213).

In the medal sorting device (selector) shown in JP-A-2006-130213, if the medal can be accepted by the member (regulation guide plate) whose position is changed by the drive of the solenoid, the inserted medal is used. Is guided in the first direction that passes through the medal sensor and is stored inside the game machine, and if the medal cannot be accepted, the inserted medal is not guided in the first direction and the game machine. It is designed to be guided in the second direction of being discharged to the outside.

By the way, since the solenoid uses magnetic force, it takes a certain amount of time to excite and demagnetize. Therefore, depending on the timing of inserting medals, for example, the inserted medals are counted by the medal sensor because the switching of the guiding direction of the medals is not completed even though the medal cannot be accepted. It may be stored inside the gaming machine (that is, "swallowing" of medals may occur).

If such a situation occurs, not only will the player suffer a loss, but the reliability of the game will also be reduced. Therefore, it is desired to provide a gaming machine capable of appropriately processing the inserted medals by preventing the occurrence of "swallowing" of medals.

The present invention has been made in view of such a point, and an object of the present invention is to provide a gaming machine capable of appropriately processing the introduced gaming medium.

In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following fourth configuration.

A game control unit (for example, a main control circuit 90) that controls a game operation, a game medium detection unit (for example, a selector 66) that detects the input of a game medium, and a game start detection unit (for example, a game start detection unit) that detects a game start operation. , Start switch 79), and a gaming machine (for example, pachislot machine 1).
The game medium detection unit
With a distribution unit (for example, select plate 804) that can distribute and guide the introduced gaming medium in the first direction for storing inside the gaming machine or in the second direction for discharging the introduced gaming medium to the outside of the gaming machine. ,
A drive unit (for example, a solenoid) that electromagnetically drives the distribution unit,
A detection unit (for example, a medal sensor) is provided to detect the inserted game medium.
The game control unit
It is possible to switch the control state between the acceptable state (for example, medal acceptance permission) that allows the reception of game media and the unacceptable state (for example, medal acceptance prohibition) that does not allow the reception of game media. When the game start detection unit detects a start operation, the control state is switched from the acceptable state to the unacceptable state (for example, the medal acceptance / start check process shown in FIGS. 75 and 76). ,
When the state switching means switches the control state from the acceptable state to the unacceptable state, the first drive state (for example, the first drive state (for example,) in which the distribution unit guides the game medium in the first direction). , Excitation state) to the second drive state (for example, degaussing state) in which the distribution unit guides the game medium in the second direction, and a drive unit control means (for example, main CPU 101).
A standby processing means (for example, a medal monitoring timer) that performs a standby process for a predetermined period when the state switching means switches the control state from the acceptable state to the unacceptable state.
When the detection unit detects the game medium during the standby process, the start operation invalidation processing means (for example, the medal insertion shown in FIGS. 78 and 79) that invalidates the start operation detected by the game start detection unit is inserted. Check 2 processing)
When the detection unit detects a gaming medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following fifth configuration.

A game control unit (for example, a main control circuit 90) that controls a game operation, a game medium detection unit (for example, a selector 66) that detects the input of a game medium, and a game start detection unit (for example, a game start detection unit) that detects a game start operation. , Start switch 79), and a gaming machine (for example, pachislot machine 1).
The game medium detection unit
With a distribution unit (for example, select plate 804) that can distribute and guide the introduced gaming medium in the first direction for storing inside the gaming machine or in the second direction for discharging the introduced gaming medium to the outside of the gaming machine. ,
A drive unit (for example, a solenoid) that electromagnetically drives the distribution unit,
A detection unit (for example, a medal sensor) is provided to detect the inserted game medium.
The game control unit
When the detection unit detects a game medium, a game medium counting means (for example, a credit counter) that counts the game medium, and
It is possible to switch the control state between the acceptable state (for example, medal acceptance permission) that allows the reception of game media and the unacceptable state (for example, medal acceptance prohibition) that does not allow the reception of game media. , A state switching means for switching the control state from the acceptable state to the unacceptable state when a predetermined number (for example, three) of game media are inserted and the game start detection unit detects a start operation. For example, the medal reception / start check process shown in FIGS. 75 and 76) and
When the state switching means switches the control state from the acceptable state to the unacceptable state, the first drive state (for example, the first drive state (for example,) in which the distribution unit guides the game medium in the first direction). , Excitation state) to the second drive state (for example, degaussing state) in which the distribution unit guides the game medium in the second direction, and a drive unit control means (for example, main CPU 101).
A standby processing means (for example, a medal monitoring timer) that performs a standby process for a predetermined period when the state switching means switches the control state from the acceptable state to the unacceptable state.
When the detection unit detects the game medium during the standby process, the start operation invalidation processing means (for example, the medal insertion shown in FIGS. 78 and 79) that invalidates the start operation detected by the game start detection unit is inserted. Check 2 processing)
The game medium counting means enables counting of game media even when the detection unit detects the game medium during the standby process.
When the detection unit detects a gaming medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following sixth configuration.

A game control unit (for example, a main control circuit 90) that controls a game operation, a game medium detection unit (for example, a selector 66) that detects the input of a game medium, and a game start detection unit (for example, a game start detection unit) that detects a game start operation. , Start switch 79), and a gaming machine (for example, pachislot machine 1).
The game medium detection unit
With a distribution unit (for example, select plate 804) that can distribute and guide the introduced gaming medium in the first direction for storing inside the gaming machine or in the second direction for discharging the introduced gaming medium to the outside of the gaming machine. ,
A drive unit (for example, a solenoid) that electromagnetically drives the distribution unit,
A detection unit (for example, a medal sensor) is provided to detect the inserted game medium.
The game control unit
It is possible to switch the control state between the acceptable state (for example, medal acceptance permission) that allows the reception of game media and the unacceptable state (for example, medal acceptance prohibition) that does not allow the reception of game media. When the game start detection unit detects a start operation, the control state is switched from the acceptable state to the unacceptable state (for example, the medal acceptance / start check process shown in FIGS. 75 and 76). ,
When the state switching means switches the control state from the acceptable state to the unacceptable state, the first drive state (for example, the first drive state (for example,) in which the distribution unit guides the game medium in the first direction). , Excitation state) to the second drive state (for example, degaussing state) in which the distribution unit guides the game medium in the second direction, and a drive unit control means (for example, main CPU 101).
A standby processing means (for example, a medal monitoring timer) that performs a standby process for a predetermined period when the state switching means switches the control state from the acceptable state to the unacceptable state.
When the detection unit detects the game medium during the standby process, the start operation invalidation processing means (for example, the medal insertion shown in FIGS. 78 and 79) that invalidates the start operation detected by the game start detection unit is inserted. Check 2 processing)
When the detection unit detects the game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state.
During the predetermined period, the distribution unit guides the gaming medium in the first direction in response to the shift of the drive unit from the first drive state to the second drive state by the drive unit control means. A gaming machine characterized in that it is set for a period equal to or longer than a period from a position until the distribution unit moves to a position for guiding the gaming medium in the second direction.

Further, in the gaming machine having the sixth configuration, the driving unit is a solenoid, the first driving state is a state in which the solenoid is excited, and the second driving state is degaussing the solenoid. A gaming machine characterized by being in a state.

According to the gaming machines having the fourth to sixth configurations, when the game is started with the start operation of the player, for example, there is a waiting period for preventing the occurrence of "swallowing" of medals. Set. During this waiting period, the game medium detection unit secures a time from the state in which the inserted medals are stored inside the game machine to the state in which the inserted medals are physically discharged to the outside of the game machine.

If a medal is inserted during the waiting period, the starting operation that is the basis of the medal is invalidated, and the inserted medal is stored inside the gaming machine in the game medium detection unit. Return to. Therefore, it is possible to prevent the occurrence of "swallowing" of medals and appropriately process the inserted medals.

Further, according to the gaming machine having the fifth configuration, even if medals are inserted during the waiting period, the medals are counted, so that the counting omission of the inserted medals is prevented. It is possible to process the inserted medals more appropriately.

Further, according to the gaming machine having the sixth configuration, the waiting period is equal to or longer than the period from the state in which the inserted medals are stored inside the gaming machine to the state in which the inserted medals are physically discharged to the outside of the gaming machine. Since the period is set to, it is possible to reliably prevent the occurrence of "swallowing" of medals and to process the inserted medals more appropriately. When the drive unit is a solenoid, such an effect becomes more remarkable.

1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information display, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit, 200 ... Sub control circuit, 201 ... Sub CPU 201, 301 ... First interface board, 302 ... Second interface board

Claims (2)

A gaming machine having a game control unit that controls a game operation and an effect control unit that controls an effect operation.
The game control unit
An arithmetic processing unit that executes various processes to control game operations,
A first storage unit in which information necessary for the arithmetic processing unit to execute various processes is stored, and
A second storage unit that stores information based on the execution of various processes by the arithmetic processing unit, and
Security department with security function and
It is configured to include a serial communication unit that performs serial communication.
The first storage unit is
A program area in which a program for executing various processes by the arithmetic processing unit is stored, and
A data area in which data for the arithmetic processing unit to execute various processes is stored, and
It is configured to include the arithmetic processing unit and the management area in which the settings and management information of the security unit are stored.
The security unit includes a start-up delay means for delaying the start-up of the arithmetic processing unit based on the input of a reset signal.
The game control unit
A communication data registration means for registering communication data in the communication data storage area of the second storage unit, and
A communication data transmission means capable of transmitting communication data registered in the communication data storage area to the effect control unit via the serial communication unit, and a communication data transmission means.
A transmission delay means for delaying the transmission of communication data by the communication data transmission means for a predetermined period, and a transmission delay means.
It is provided with a setting value setting means capable of setting a setting value indicating the degree of advantage of the player regarding the game.
The activation delay means delays the activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays the transmission of communication data by the communication data transmission means after the delay in starting the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of a set value even when the transmission of communication data is delayed by the transmission delay means.
Even when the transmission of communication data is delayed by the transmission delay means, the communication data registration means is set in the communication data storage area when the setting of the set value by the set value setting means is started. The communication data of 1 can be registered, and the second communication data can be registered in the communication data storage area when the setting of the set value by the set value setting means is completed.
The communication data transmission means transmits communication data registered in the communication data storage area at regular intervals.
When the delay in transmitting the communication data by the transmission delay means is completed and the first communication data and the second communication data are registered in the communication data storage area, these communication data are stored. Send in the registered order,
When the delay in transmitting the communication data by the transmission delay means is completed, the first communication data is registered in the communication data storage area, and if the second communication data is not registered, it is registered. The first communication data is transmitted, and then the registered second communication data is transmitted when the second communication data is registered in the communication data storage area.
When the transmission of communication data is not delayed by the transmission delay means and the communication data is not registered in the communication data storage area, the communication data registration means provides a third communication data storage area. A gaming machine characterized in that the communication data of the above is registered and the registered third communication data is transmitted. The gaming machine according to claim 1, wherein the third communication data does not include information related to the gaming operation of the player.

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