JP2019097045A5 - Address bit string storage method - Google Patents

Description

According to the present invention, the bit string of the source address of the packet or the fixed phone number is converted into a binary number or the mobile phone number is converted into the respective upper digits 090 , 080 , and 070 of the respective digits except the numeral 0. each of the bit string of the conversion of low-order 8-digit number into a binary number each decimal binding, either, for bit stream storage how the address for storing the partial or hash.

The present invention has been made in view of the above-mentioned problems of the prior art, and a means for solving the problem is to convert a bit string of a source address of a packet or a fixed telephone number into a binary number or a higher digit 090 of a mobile telephone number. , 080, 070 each of the remaining numbers except the number 0 , the lower 8 digits are combined with each of the decimal numbers converted into binary numbers, each bit string, any, part or hash ( hereinafter, divided) that bit string of address upper bit string and a lower bit string, the specified by upper bit string, each bit of the parallel data read from the designated address position in the memory cell array in the memory to 1 temporary the parallel data comprising the low-order bit string from OR of the outputs of the respective bits of the parallel bit decoded by the decoder, latch, the The pitch output data, designated by said upper bit string, the return to the designated address position in the memory cell array by storing the bit string storage side of the address that allows storage of long bit string of stored bit length Is the law .

The present invention, in each of the remaining digits excluding the digit 0 in each digit of the upper digit 090,080,070 bit string or mobile phone number converted bit string or a fixed telephone number of the source address of the packet to binary each of the bit string of the conversion of low-order 8-digit number into a binary number each decimal binding, either the address specified by the upper bit string when the bit string part or hash of the address is divided into upper bit string and a lower bit string In the parallel storage data area at the specified address position of the memory cell array in the memory, the parallel storage data is stored in the memory at a position where the lower bit string matches the position of bit 1 in the parallel bits decoded by the decoder. The data is read out of the cell array and the original address is being returned to the specified address position. It is characterized in that bit 1 having a bit string storage of an address is stored by inserting bit 1 in a position corresponding to the position of bit 1 in the parallel bit of decoding by the decoder of the lower bit string of the column storage data. This is a method of storing a bit string of addresses to be used.

According to the present invention, a bit string of an address to be stored is divided into a high-order bit string and a low -order bit string, and an address is specified by the high-order bit string. Each bit of parallel data temporarily read from the specified address in a memory cell array. When the lower bit string latched and each bit of the parallel bits of the decoding by the decoder, the parallel bit consisting of OR output of the specification of said address by upper bit string of the latched output the memory cell array is designated by returning to the data storage area of the address position, a function of storing bit first memory chromatic bit string of the address to be stored,
The bit string of the address to check whether the stored divided into upper bit string and a lower bit string, the address by the upper bit string is specified, and each bit of the parallel data read from the specified address location within the memory cell array, the lower and each bit of the parallel bit decoded by the bit string to the decoder, which is the oR circuit outputs of all bits of each bit of the parallel bits of the output of the aND, signals of the storage / absence of a bit string of the address to check whether the stored A memory having a function of outputting .

The present invention, when the signal input to store the bit 0, divided bit string of addresses to be erased to the upper bit string and a lower bit string, the address by the upper bit string is specified, 1:00 from the designated address location within the memory cell array and each bit of the parallel data to read, and each bit of the logical inversion of each bit of the parallel bit decoded by the low-order bit string to the decoder, the parallel data consisting of the output of the aND of the address is specified by the upper bit string that, by returning to the data storage area of the designated address position in the memory cell array, a further Ru comprising memory a function of writing the bit 0 of the bit string storage free address erase.

As described above, according to the present invention, the bit string of the source address of a packet or the fixed phone number of a packet having a long storage bit length and a large number can be converted into a binary number by a simple method or a mobile phone. Each of the upper digits of the numbers 090 , 080 , 070 is combined with the remaining 8 digits except the numeral 0, and the lower 8 digits are combined . Each bit string of each decimal number converted to binary number, either There is an advantage that it is possible to provide a memory that can store a part or a hash in one memory.

Diagram for explaining a first storing a bit string of address examples, the memory in which the internal memory cell array and a decoder and an input register and a peripheral circuit configuration of the present invention Diagram for explaining a second bit string storage and erasure of address examples, the memory in which the internal memory cell array and a decoder and an input register and a peripheral circuit configuration of the present invention

A first embodiment of the present invention will be described with reference to FIG. In this embodiment, the bit string of the source address of the packet or the bit string obtained by converting the fixed telephone number into a binary number or the upper digits of the mobile telephone number 090 , 080 and 070 , respectively, the remaining digits except the numeral 0 each bit column of the lower 8 digits in binary number each decimal binding, either partial or memory cell array and a decoder as the input register and the peripheral circuit for storing a bit string of the address corresponding to the hash It is the configuration of the memory that has built-in .

In Figure 1, memory 1 for storing a bit string of the address, the memory cell array 2, 3 decoder, 4 denotes an input register, a write enable signal 5, the addressing signal of the upper bit row 6, the address lower bit string 7 specifying signal 9 input data, OR circuits 10,17,18, the aND circuits 11 and 12, the output data of the memory cell array 2 13, 15 the output signal of the entire input bit 0 of the decoder 3, 16 Is an output signal of all bits 1 input to the decoder 3, and 19 is an output signal of the memory 1.

The operation of FIG. 1 will be described below. First, the operation of storing the bit string of the address in the memory 1 will be described. An address designation signal of an upper bit string (for example, 19 bits) when a bit string of an address corresponding to a lower address when a packet source address of a packet transfer system is divided into an upper address and a lower address is divided into an upper bit string and a lower bit string 6 address is specified by, from the specified address position of the memory cell array 2, and each bit of the parallel data from Q0 to be read Q31, the lower bit string (e.g., 5 bits) addressing signal 7 the decoding circuit 3 Each bit of the parallel bits of decoding by the AND circuit is operated by an AND circuit and an OR circuit, and the result is latched by a latch circuit in the input register 4 which is not shown in the figure, and the latch output is supplied with the write enable signal 5. enable and is stored in the designated address position of the memory cell array 2.

Specifically, when the output 3 when the signal of all bits 0 of the lower bit sequence is input to the decoder 3 and the output Q15 (13) is 0, the output of the OR circuit 17 is 1, so that Q0 is 0 even in the address position specified by the upper bit string of the memory cell array 2, as input data, 1 is stored. On the other hand, when the output 16 when the signal of all bits of the lower bit string is 0 is input to the decoder 3 , the output of the OR circuit 18 becomes 1, so the data of Q31 (14) is used as it is as the input data. It is stored in the address location specified by said upper bit string of the memory cell array 2. Thus, parallel data signal of the position output of the first decoder 3 to output parallel data from the address position specified by the upper bit string of the memory array 2 has been inserted, designated by the upper bit string of the memory cell array 2 It is possible to store the bit string of the target address by returning to the address position to be written and writing.

Next, the operation for confirming whether the bit string of the target address is stored in the memory 1 will be described. An address designation signal of an upper bit string (for example, 19 bits) when a bit string of an address corresponding to a lower address when a packet source address of a packet transfer system is divided into an upper address and a lower address is divided into an upper bit string and a lower bit string 6 address is specified by, depending from the specified address position of the memory cell array 2, the Q0 from the respective bits of parallel data Q31, decode circuit 3 addressing signal 7 of the lower bit string (e.g., 5 bits) to be read and each bit of the parallel bits of the decoding, calculated by an aND circuit and OR circuit, and it and the output signal of the memory 1.

Specifically, in the case where a signal of which the lower bit string is all bit 0 is input to the decoder 3 , the output 15 is 1 , the output 16 is bit 0 , Q0 (13) is 1 and Q31 (14) is 1 Moreover, the output of the AND circuit 11 becomes 1, while the output of the AND circuit 12 becomes bit 0, so that the number of inputs to the OR circuit 10 becomes one and the output 19 of the memory 1 becomes bit 1. In this case, it is determined that the bit string of the target address is stored. Under the above conditions, if Q0 (13) is bit 0, the output 19 of the memory 1 is bit 0. In this case, it is determined that the bit string of the target address is not stored. Thus, the output of the decoder 3 from the output parallel data from the address position specified by the upper bit string of the memory cell array 2 selects a signal of a position of the bit 1, a bit string storage / absence signals of the address memory Since 1 is output, it can be confirmed whether the bit string of the target address is stored.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the bit string of the source address of the packet or the bit string obtained by converting the fixed telephone number into a binary number or the upper digits of the mobile telephone number 090 , 080 and 070 , respectively, the remaining digits except the numeral 0 A memory array, a decoder, an input register, and a peripheral circuit for storing each bit string of combining each of the lower eight digits into each of the decimal numbers into a binary number, and storing a bit string of an address corresponding to any of a part or a hash It is the configuration of the memory that has built-in .

In FIG. 2, 20 is an input register, 8 is a write signal of bit 0 , 21 and 22 are AND circuits, and 23 is a NOT circuit. Others are the same as in FIG.

The operation of FIG. 2 will be described below. First, the operation of storing the bit string of the address in the memory 1 will be described. An address designation signal of an upper bit string (for example, 19 bits) when a bit string of an address corresponding to a lower address when a packet source address of a packet transfer system is divided into an upper address and a lower address is divided into an upper bit string and a lower bit string According from the specified address position of the memory cell array 2 which address is specified by 6, and each bit of the parallel data from Q0 to be read Q31, the decoding circuit 3 addressing signal 7 of the lower bit string (e.g., 5 bits) When the write signal 8 of bit 0 is bit 0, each bit of the parallel bits of decoding is operated by the OR circuit and the AND circuit, and the result is latched by the latch circuit (not shown) in the input register 20. the latch output data enable write enable signal 5, before the memory cell array 2 The data is stored in the address position designated by the high-order bit string .

Specifically, when the write signal of bit 0 is bit 0 , the input signals from the AND circuits 21 and 22 are cut off in the input register 20, and the input signals from the OR circuits 17 and 18 are latched, so that the memory since the input to the address position specified by the upper bit string of the cell array 2, the output 15 is bit 1 at the lower bit string signals of all bit 0 input to the decoder 3, when Q0 (13) is 0 , the output 1 next to the OR circuit 17, the output of the aND circuit 21 becomes 0, Q0 in the address location specified by said upper bit string of the memory cell array 2 be 0, as input data, bit 1 is stored To be done. On the other hand, when the output 16 when the signal of all bits 0 in the lower bit string is input to the decode 3 , the signal of Q31 appears as it is at the output of the AND circuit 22, so the data of Q31 remains as it is. It is stored in the address location specified by said upper bit string of the memory cell array 2 as. Thus, parallel data signal of position output of the decoder 3 to output parallel data from the address position specified by the upper bit string of the memory cell array 2 is bit 1 is inserted, the upper memory cell array 2 By returning to the address position designated by the bit string and writing it, the bit string of the target address can be stored.

Next, the operation of confirming whether the bit string of the target address is stored in the memory 1 will be described. An address designation signal of an upper bit string (for example, 19 bits) when a bit string of an address corresponding to a lower address when a packet source address of a packet transfer system is divided into an upper address and a lower address is divided into an upper bit string and a lower bit string 6 address is specified by decoding from the specified address position of the memory cell array 2 in the memory, and each bit of the parallel data Q0 from Q31 to be read, the address signal 7 of the lower bit string (e.g., 5 bits) and each bit of the parallel bit decoded by the circuit 3 calculates the aND circuit and OR circuit, it is the output 19 of the memory 1.

Specifically, when the output 15 is a bit 1 and a signal of Q0 (13) is a bit 1 when a signal of all bits 0 of the lower bit string is input to the decoder 3 , the output of the AND circuit 11 becomes a bit 1 and the decoding is performed. Since the other output (eg, 16) of 3 becomes bit 0 and the output of the AND circuit 12 becomes bit 0, the number of inputs to the OR circuit 10 becomes one and the output 19 of the memory 1 becomes bit 1. In this case, it is determined that the bit string of the target address is stored. Under the above conditions, if Q0 (13) is bit 0, the output 19 of the memory 1 is bit 0. In this case, it is determined that the bit string of the target address is not stored. Thus, the output of the decoder 3 from the output parallel data from the address position specified by the upper bit string of the memory cell array 2 selects the data by a signal position of the bit 1, bit string address the selected data Since there is a signal with / without memory and the output is the output 19 of the memory 1, it is possible to confirm whether the bit string of the target address is stored.

Next, the operation of erasing the memory of the bit string of the target address from the memory 1 will be described. An address designation signal of an upper bit string (for example, 19 bits) when a bit string of an address corresponding to a lower address when a packet source address of a packet transfer system is divided into an upper address and a lower address is divided into an upper bit string and a lower bit string address by 6 is designated, from the specified address position of the memory cell array 2 in the memory, and each bit of the parallel data from Q0 to be read Q31, the addressing signal 7 of the lower bit string (e.g., 5 bits) When the write signal 9 of bit 0 is bit 1, the AND circuit and the OR circuit operate on each bit of each bit of the parallel bits decoded by the decode circuit 3 and the result is stored in the input register 20. Latch with a latch circuit (not shown), and output the latch output data with the write enable signal 5. Enable and is stored in the address location specified by said upper bit string of the memory cell array 2.

Specifically, when the write signal of bit 0 is bit 1 , the input signals from the OR circuits 17 and 18 are cut off in the input register 20, and the input signals from the AND circuits 21 and 22 are latched. since the input to the address position specified by the upper bit string of the memory cell array 2, the lower bit string output 15 when the signal of all bits 0 input to the decoder 3 by bit 1, Q0 (13) is bit 1 If, the output of the aND circuit 21 becomes bit 0, Q0 is the address position specified by the upper bit string of the memory cell array 2 even bit 1, as D0 of the input data, bit 0 is stored. On the other hand, if the lower bit string output 16 when the signal of all bits 0 input to the decode 3 becomes bit 0, as data of Q31 is designated by the upper bit string of the memory cell array 2 as input data Stored at address location . Thus, parallel data output of the decoder 3 to output parallel data from the address position specified by the upper bit string of the memory cell array 2 is erased out by the inverted signal of the bit 1 position of the bit 1, the memory cell array By returning to the address position designated by the upper bit string of 2 and writing, the memory of the bit string of the target address can be erased.

Memory 2 memory cell array 3 decoder 4 input registers 5 write enable signal 6 upper bit string of the addressing signal 7 write signal 9 of lower bit string of the address specifying signal 8 bit 0 input data 10 OR circuits 11 and 12 for storing a bit string of one address AND circuits 13 and 14 the memory cell array 2 of the output data 15 the decoder 3 inputs the output signal 20 input register 21 of the output signal 17, 18 OR circuit 19 memory 1 input all bit 1 of the output signal 16 the decoder 3 of all bits 0, 22 AND circuit 23 NOT circuit

Claims (3)

Of converting a bit string or a fixed telephone number of the source address of the packet in binary respective upper digits 090,080,070 bit string or mobile phone number without the digit 0 digit of the remaining respective numbers in the lower 8 digits Each bit string for converting each decimal number of a combination of numbers into a binary number, any part or hash ( hereinafter, referred to as an address bit string ) is divided into an upper bit string and a lower bit string , and the address is determined by the upper bit string. In the designated parallel memory data area of the specified address position of the memory cell array in the memory, the parallel storage data is located at a position where the lower bit string matches the position of bit 1 in the parallel bits decoded by the decoder. Is read out of the memory cell array and returned to the position where the original address is specified A bit 1 having a bit string storage of an address is stored by inserting the bit 1 at a position of the parallel storage data in which the lower bit string corresponds to the position of the bit 1 in the parallel bit decoded by the decoder. Method of storing bit string of address. A memory for storing a bit string of an address to which the method of storing a bit string of an address according to claim 1 is applied,
The bit string of the storage address is divided into an upper bit string and a lower bit string , each bit of the parallel data temporarily read from the specified address in the memory cell array whose address is designated by the upper bit string, and the lower bit. latching each bit parallel bit decoded by the bit string to the decoder, the parallel bits of the OR of the outputs of the latch output data of the designated address position where the address by upper bit string is designated in the memory cell array back to the data storage area by storing a function that stores bit 1 of the memory chromatic bit string of addresses of the memory,
The bit string of confirmation of address or stored separately in the high-order bit string and a lower bit string, the address by the upper bit string is specified, and each bit of the parallel data read from the specified address location within the memory cell array, the lower and each bit of the parallel bit decoded by the bit string to the decoder, which is the output of all bits of each bit oR of the parallel bits of the output of the aND, signals of the storage / absence of a bit string of checked addresses stored A memory having a function of outputting. When the signal input to store a bit 0, divided bit string of addresses of erased upper bit string and a lower bit string, the address by the upper bit string is specified, it is read from the designated address position in the memory cell array 1 temporary and each bit of the parallel data, and each bit of the bit inversion of each bit of the parallel bit decoded by the low-order bit string to the decoder, the parallel bits of the output of the aND of the latches, the latch output data, by the upper bit string address is specified, the return to the data storage area of the designated address position in the memory cell array by storing, claim Ru further comprising a function of writing the bit 0 of the bit string storage free address of the erase 2 Memory described in.