JP2019096970A - Operational amplifier, semiconductor device - Google Patents

Abstract

To provide an operational amplifier capable of fast turn-around.SOLUTION: An input differential pair 10 is connected with a noninverting input terminal (INP), and an inverting input terminal (INN). A tail current source 12 is connected with the input differential pair 10. A cascode type current mirror circuit 14 is connected with the input differential pair 10 as an active load, and is constituted by stacking up transistors of isomorphism in two steps vertically. The current mirror circuit 14 adjusts the working point of cascode type current mirror circuit, so that the voltages at the input node B and the output node A of the current mirror circuit 14 are equalized. The differential pair of a buffer amplifier 16 is constituted of depletion type MOS transistors.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an operational amplifier.

  An operational amplifier (differential amplifier) is used to amplify the difference between the two input voltages. FIG. 1 is a circuit diagram showing a configuration example of a general operational amplifier. The operational amplifier 100R includes an input differential pair 10, a tail current source 12, a current mirror circuit 14, a bias circuit 20, and an output stage 30.

The input differential pair 10 includes a first transistor M1 and a second transistor M2. The tail current source 12 supplies a tail current _ITAIL to the input differential pair 10. The current mirror circuit 14 is an active load of the input differential pair 10, and is configured in a cascode type capable of low voltage operation.

  The current mirror circuit 14 includes third to sixth transistors M3 to M6. The gates of the transistors M5 and M6 are appropriately biased, and the gate of the transistor M3 (M4) is connected to the drain of the transistor M5. As a result, the transistors M3 and M5 can be surely saturated and copied to saturate the transistors M4 and M6, thereby achieving low voltage operation.

  In order to operate the circuit at high speed, a large current needs to be supplied to the current mirror circuit 14. The element size of the transistor is large, and the gate capacitance of the node C is large. In the operational amplifier 100R of FIG. 1, the node C is directly connected to the node B, and the gate capacitance can be seen from the signal line including the node B, resulting in a decrease in circuit operation.

  The present invention has been made in view of such problems, and one of the exemplary objects of one aspect thereof is to provide an operational amplifier capable of high-speed operation.

  One aspect of the present invention relates to an operational amplifier. The operational amplifier is connected to the non-inverted input terminal, the input differential pair connected to the inverted input terminal, the tail current source connected to the input differential pair and supplying tail current to the input differential pair, and active to the input differential pair And a cascode current mirror circuit connected as a load and configured by vertically stacking two stages of identical transistors. The cascode current mirror circuit includes a buffer amplifier that adjusts the operating point of the cascode current mirror circuit so that the voltages at the input node and the output node of the cascode current mirror circuit become equal. The buffer amplifier includes a differential pair composed of depletion type MOS transistors.

  According to this aspect, by providing the buffer amplifier, the capacitance coupled to the signal line can be reduced, and the speed of the operational amplifier can be increased. Further, by forming the differential pair of the buffer amplifier with a depression type MOS transistor, the operational amplifier can be reliably activated when the power is turned on.

  The differential pair of buffer amplifiers may be configured by N channel MOS transistors.

  Another aspect of the present invention relates to a semiconductor device. The semiconductor device may include the above-described operational amplifier.

  It is to be noted that any combination of the above-described constituent elements, or one in which the constituent elements and expressions of the present invention are mutually replaced among methods, apparatuses, systems, etc. is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the speed of the operational amplifier can be increased.

It is a circuit diagram showing an example of composition of a common operational amplifier. It is a circuit diagram of the operational amplifier concerning an embodiment. It is a circuit diagram of the buffer amplifier of FIG. It is a circuit diagram of a differential amplifier concerning a comparison technique. It is a figure which shows the input-output characteristic when a voltage follower is comprised by the differential amplifier of FIG. It is a figure which shows the input-output characteristic when a voltage follower is comprised with the buffer amplifier of FIG. FIG. 7A is a diagram showing the power supply voltage dependencies of a plurality of nodes of the operational amplifier according to the embodiment, and FIG. 7B is a view showing the power supply voltage dependencies of a plurality of nodes of the operational amplifier according to the comparison technology. FIG.

  Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and duplicating descriptions will be omitted as appropriate. In addition, the embodiments do not limit the invention and are merely examples, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In the present specification, "a state in which the member A is connected to the member B" means that the members A and B are physically directly connected, or the members A and B are electrically connected. It also includes the case of being indirectly connected through other members that do not substantially affect the state or inhibit the function.
Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, or the electric member It also includes the case of being indirectly connected through other members that do not substantially affect the connection state or inhibit the function.

  FIG. 2 is a circuit diagram of the operational amplifier 100 according to the embodiment. The basic configuration of the operational amplifier 100 is the same as that of the operational amplifier 100R of FIG. 1 and includes an input differential pair 10, a tail current source 12, a current mirror circuit 14, a bias circuit 20, and an output stage 30. The operational amplifier 100 is integrated on one semiconductor chip. The semiconductor chip is incorporated in a semiconductor device such as an operational amplifier IC or another functional IC.

  The input differential pair 10 includes a first transistor M1 and a second transistor M2 which are PMOS transistors. The tail current source 12 is composed of a PMOS transistor whose gate is biased.

  The current mirror circuit 14 is provided as an active load of the input differential pair 10. The current mirror circuit 14 is a cascode current mirror circuit capable of low voltage operation, and includes third to sixth transistors M3 to M6, which are NMOS transistors, and a buffer amplifier 16. The gates of the third transistor M3 and the fourth transistor M4 are connected in common. The gates of the fifth transistor M5 and the sixth transistor M6 are connected in common and appropriately biased by a bias circuit (not shown).

The buffer amplifier 16 adjusts the operating point of the current mirror circuit 14, that is, the voltage of the gate C of the transistors M3 and M4, so that the voltages V _B and V _{A at} the input node B and the output node B of the current mirror circuit 14 become equal. Do.

Output stage 30 generates an output voltage V _OUT according to the voltage of output node A of current mirror circuit 14. The configuration of the output stage 30 is not particularly limited, and a known technique may be used.

  FIG. 3 is a circuit diagram of the buffer amplifier 16 of FIG. The buffer amplifier 16 is a differential amplifier including a differential pair 40, a tail current source 42, an active load 44 and a current mirror circuit 46. Active load 44 includes transistors M9-M12. The current mirror circuit 46 also includes transistors M13 to M16. The differential pair 40 of the buffer amplifier 16 is formed of a depletion type NMOS transistor. The configurations of the active load 44 and the current mirror circuit 46 are not limited to those shown in FIG.

  The above is the configuration of the operational amplifier 100. Next, the advantages will be described.

  In the operational amplifier 100 of FIG. 3, nodes A and B, which are signal propagation paths, are separated by the buffer amplifier 16 from the node C having a large capacitance. By designing the input capacitance of the buffer amplifier 16 sufficiently smaller than the gate capacitance of the node C, a decrease in operating speed is suppressed, and high speed operation of the operational amplifier 100 becomes possible.

  In addition, as described with reference to FIG. 3, the differential pair of the buffer amplifier 16 is configured of a depression type MOS transistor. This advantage is made clear by comparison with the comparison techniques described below.

  FIG. 4 is a circuit diagram of a buffer amplifier 16R according to a comparison technique. Since it is required to reduce the input capacitance as much as possible, the buffer amplifier 16R is composed of the simplest differential amplifier, and the differential pair is composed of a general enhancement type PMOS transistor.

  FIG. 5 is a diagram showing input / output characteristics when a voltage follower is configured by the differential amplifier of FIG. As can be seen from FIG. 5, the buffer amplifier 16R of FIG. 4 has a dead zone on both the VDD side and the VSS side.

  When the buffer amplifier 16R having such characteristics is incorporated into the current mirror circuit 14 of FIG. 3, there arises a problem that the operational amplifier can not be started. Hereinafter, an operational amplifier in which the buffer amplifier 16R is incorporated in the current mirror circuit 14 will be denoted by reference numeral 100R. This problem is uniquely recognized by the present inventors, and should not be recognized as a common recognition of those skilled in the art.

  More specifically, when the voltage of nodes A and B is included in the dead band on the VDD side at the time of power activation of operational amplifier 100R, the input differential pair of buffer amplifier 16R is turned off, and the output of buffer amplifier 16R, ie, node C The potential goes low, causing the current mirror circuit 14 to be in the off state, disabling activation.

  Return to FIG. There are also cases where this problem of unstartable can be solved by providing the current limit circuit 32 in the output stage 30. That is, the current limiting circuit 32 limits the current that the operational amplifier 100 sinks from the output terminal OUT in the operating state of the operational amplifier 100 (100R). More specifically, when the voltage at node A (ie, the gate voltage of output transistor M23) rises, transistor M21 turns on and transistor M22 turns on, current is drawn from node A, and the voltage at node A decreases, and the output transistor Feedback is applied to reduce the sink current flowing to M23.

The current limiting circuit 32 also acts as a start circuit at the time of power supply start. Immediately after startup, a voltage near the power supply voltage V _DD appears at the node A. Then, the transistors M21 and M22 are turned on to lower the potential of the node A. As a result, the voltage of the node A becomes lower than the voltage of the node B, the voltage of the node C rises by the comparator operation of the buffer amplifier 16R, a current flows in the current mirror circuit 14, and the operational amplifier 100R starts.

  However, there are cases where the current limiting function, which is the original function of the current limiting circuit 32, can not be compatible with the start assist. Specifically, depending on the setting of the amount of current to be limited, the voltage of the node A may not fall within the input voltage range of the buffer amplifier 16, and in that case, start-up assistance by the current limiting circuit 32 can not be expected.

  If only the improvement of the start-up characteristic is considered, the approach of configuring the differential input stage of the buffer amplifier 16R with a full swing type including PMOS differential pair and NMOS differential pair used in the Rail-To-Rail amplifier However, since such a differential input stage has a large number of elements, the input capacity becomes large and can not be adopted for the operational amplifier 100 that requires high speed.

  The above is the comparative technique and the problems associated with it. The description returns to the description of the operational amplifier 100 according to the embodiment.

  FIG. 6 is a diagram showing input / output characteristics when a voltage follower is configured by the differential amplifier of FIG. By forming the differential pair in a depletion type, the input voltage range is greatly expanded compared to FIG.

  FIG. 7A shows the power supply voltage dependency of a plurality of nodes of the operational amplifier 100 according to the embodiment. FIG. 7 (b) also shows the power supply voltage dependencies of a plurality of nodes of the operational amplifier 100R according to the comparison technique.

  The operation of the comparison technique will be described with reference to FIG. 7 (b) earlier. In the region where the power supply voltage is lower than 2.45 V, the voltages at nodes A and B stick close to the power supply voltage, and the voltage at node C is lower than the gate threshold of the MOSFET. It is.

  Subsequently, the operation of the operational amplifier 100 according to the embodiment will be described with reference to FIG. 7 (a). When the power supply voltage rises, the voltage at node C increases without sticking to 0V. When the voltage at the node C exceeds the gate threshold of the MOSFET, a current flows in the current mirror circuit 14 and the operational amplifier 100 is activated.

  As described above, according to the operational amplifier 100 according to the embodiment, the capacitance coupled to the signal line (nodes A and B) can be reduced by providing the buffer amplifier 16, and the operational amplifier 100 can be speeded up. In addition, by forming the differential pair 40 of the buffer amplifier 16 with a depression type MOS transistor, the operational amplifier 100 can be reliably activated when the power is turned on.

  Further, the current limiting circuit 32 of FIG. 3 can be designed in consideration of only the function of the original current limiting. The current limiting circuit 32 is not essential and may be omitted, or a current limiting circuit with another circuit configuration may be added.

  The configuration of the operational amplifier 100 described in the embodiment is an example, and it is understood by those skilled in the art that various modifications exist. Although the embodiment describes the PMOS input operational amplifier, the present invention is also applicable to an NMOS input operational amplifier. For example, the circuit may be reversed, and the P channel and the N channel may be switched. The configuration of the bias circuit 20 is also not limited to that of FIG.

  While the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement can be made without departing from the concept of the present invention.

DESCRIPTION OF SYMBOLS 100 operational amplifier 102 power supply line 104 earthing ground INP noninverting input terminal INN inverting input terminal 10 differential pair 12 tail current source 14 current mirror circuit 16 buffer amplifier 20 bias circuit 30 output stage 32 current limiting circuit 40 differential pair 42 tail current source 44 Active load 46 Current mirror circuit

Claims (3)

An input differential pair connected to the non-inverting input terminal and the inverting input terminal,
A tail current source connected to the input differential pair and supplying tail current to the input differential pair;
A cascode current mirror circuit connected as an active load to the input differential pair and configured by vertically stacking two stages of transistors of the same type;
Equipped with
The cascode current mirror circuit includes a buffer amplifier that adjusts an operating point of the cascode current mirror circuit so that voltages of an input node and an output node of the cascode current mirror circuit become equal,
The operational amplifier is characterized in that the buffer amplifier includes a differential pair composed of depletion type MOS transistors.   The operational amplifier according to claim 1, wherein the differential pair of the buffer amplifier is formed of an N-channel MOS transistor.   A semiconductor device comprising the operational amplifier according to claim 1.

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