JP2019092305A - Current sense amplifier circuit and switching power supply device - Google Patents

Abstract

To provide a current sense amplifier circuit capable of evenly performing trimming for avoiding an influence to be given to a current sense signal by offset on an input side for N gain setting circuits by adjustment of a current source of a trimming circuit.SOLUTION: A current sense amplifier circuit 4A is provided with: an operational amplifier 41 which amplifies voltage to be generated in a resistor R1; three gain setting circuits which are controlled by the operational amplifier 41 to take out three current sense signals Vo1 to Vo3 with different gains based on the voltage to be generated in the resistor R1; and a trimming circuit which performs trimming of the three gain setting circuits. Circuit constants of the three gain setting circuits are set to hold predetermined relations. The trimming circuit adjusts trimming current to be applied to resistors R41 to R43 of the three gain setting circuits by current Ib0 of a current source 43.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a current sense amplifier circuit that detects a current flowing in a current detection transistor and a switching power supply device of a current mode control type using the current sense amplifier circuit.

  A current mode control type switching power supply that steps down an input voltage and outputs a constant voltage is configured, for example, as shown in FIG. 5 (patent documents 1, 2, 3 as similar techniques). This switching power supply device is a PMOS first switching transistor MP1 connected between the first node LX and the first power supply terminal 1 and whose ON / OFF is controlled by the drive signal φ1, the first node LX and the second power supply terminal A second switching transistor MN1 for synchronous rectification of NMOS connected between (ground terminal) 2 and whose ON / OFF is controlled by a drive signal φ2 in phase with the drive signal φ1 is provided. L1 is an inductor connected between the first node LX and the output terminal 3, and C1 is an output capacitor connected between the output terminal 3 and the second power supply terminal 2.

  MP2 is a PMOS current detection transistor whose drain is connected to the first node LX and whose ON / OFF is controlled in synchronization with the first switching transistor MP1 by the drive signal φ1; R1 is the source of the transistor MP2 and the first power supply terminal 1; A current detection resistor 4C connected between them is a current sense amplifier circuit that amplifies the voltage Vd generated in the resistor R1 by dividing the current Isw flowing in the inductor L1 and outputs it as a current sense signal Vo.

  A control circuit 5 controls ON / OFF of the transistors MP1, MP2, and MN1, and includes a drive circuit 51. The drive circuit 51 sets the drive signals φ1 and φ2 to the “L” level by inputting the rising edge of the fixed period signal oscillated by the oscillator 52 to the SET terminal, and the rising edge of the signal input to the RESET terminal. Drive signals .phi.1 and .phi.2 are set to the "H" level. An operational amplifier 53 works as an error amplifier, and compares the feedback voltage Vfb obtained by dividing the voltage Vout output to the output terminal 3 with the resistors Ra and Rb with the reference voltage Vref that sets the target voltage of the output voltage Vout. An error voltage Verr is generated. A comparator 54 compares the current sense signal Vo output from the current sense amplifier circuit 4C with the error voltage Verr, and outputs the comparison result to the RESET terminal of the drive circuit 51 as a reset signal.

  The current sense amplifier circuit 4C has an inverting input terminal connected to the first power supply terminal 1 via the resistor R2, and a non-inverting input terminal connected to the source of the transistor MP2 and a gate connected to the output terminal of the operational amplifier 41. A PMOS control transistor MP3 is connected, the source is connected to the inverting input terminal of the operational amplifier 41, and the drain is connected to the second power supply terminal 2 via the resistor R3. The gain of the current sense amplifier circuit 4C is G = Vo / Vd = R3 / R2.

  FIG. 6 shows operation waveforms of the switching power supply device of FIG. When the pulse output from the oscillator 52 rises to "H", the drive signal .phi.1 falls from "H" to "L" by the drive circuit 51, and the transistors MP1 and MP2 are turned ON. The drive signal φ2 falls from “H” to “L” early by the dead time, and at this time, the transistor MN1 is turned off. Then, when the transistor MP1 is turned on, the current Isw flows from the first power supply terminal 1 through the first node LX to the inductor L1, energy is stored therein, the capacitor C1 is charged, and the output terminal 3 Power is supplied to the load not shown. Since the current Isw gradually increases in accordance with the inductance of the inductor L1, the current sense voltage Vo output from the current sense amplifier circuit 4C gradually increases in accordance with the current Isw.

  On the other hand, the feedback voltage Vfb corresponding to the output voltage Vout is compared with the reference voltage Vref in the operational amplifier 53, and the error voltage Verr (= Vref-Vfb) which is the comparison result is input to the comparator 54. The comparator 54 compares the current sense voltage Vo output from the current sense amplifier circuit 4C with the error voltage Verr. When Vo> Verr, the voltage of the RESET terminal of the drive circuit 51 changes from "L" to "H". Launch.

  As a result, the drive signal φ1 output from the drive circuit 51 rises to “H”, and the transistors MP1 and MP2 are switched from ON to OFF. Further, the drive signal φ2 rises from “L” to “H” with a delay by the dead time, and the transistor MN1 switches from OFF to ON. As a result, the current Isw flows in the direction of the output terminal 3 by the energy stored in the inductor L1, and returns to the first node LX via the load and the transistor MN1. Thereafter, the same operation is repeated, and the output voltage Vout converges to a voltage corresponding to the reference voltage Vref.

  By the way, since the gain G of the current sense voltage Vo obtained by the current sense amplifier circuit 4C is set by R3 / R2 as described above, the gain G can be determined by appropriately setting the value of the resistor R2 or R3. Although this can be done, there are cases where multiple types of this gain G are required.

  For example, when the switching power supply device is operated in the normal current mode, the gain G can be suppressed to be small because it is necessary to widen the control range, but when operating in the light load mode, the control range can be narrowed. can do. Here, in order to be able to switch between the normal current mode and the light load current mode, two sets of current sense amplifier circuits 4C may be prepared, but there is a problem of increasing the chip area.

  Therefore, if the current sense amplifier circuit is configured to be able to take out a plurality of current sense signals having different gains and one current sense signal can be selected from the plurality of current sense signals and input to the comparator 54, The above problem can be solved to realize switching between the normal current mode and the light load mode.

  FIG. 7 is a circuit showing a current mode control type switching power supply in consideration of this point. Here, as the current sense amplifier circuit 4D, three gain setting circuits are configured to take out three current sense signals Vo1, Vo2, Vo3 having different gains. That is, the control transistors MP31, MP32 and MP33 are connected to be controlled by the output signal of the operational amplifier 41, and the resistors R21, R22 and R23 are connected between the sources of the control transistors MP31, MP32 and MP33 and the first power supply terminal 1. Are connected, the drains are connected to the resistors R31, R32, R33, and the resistors R41, R42, R43 are connected between the resistors R31, R32, R33 and the second power supply terminal 2.

  The gain of the current sense signal Vo1 obtained at the drain of the transistor MP31 is "(R31 + R41) / R21", and the gain of the current sense signal Vo2 obtained at the drain of the transistor MP32 is "(R32 + R42) / R22". The gain of the current sense signal Vo3 to be output is "(R33 + R43) / R23".

  However, when there is the offset voltage Vos1 of the operational amplifier 41 or the intentionally added offset voltage Vos2 (generated by the resistor Ros and the current Ios of the current source 42), these offset voltages Vos1 or Vos (= Vos1 + Vos2) Since the gain is amplified by the gain of the sense signals Vo1 to Vo3, the influence of the offset is different for each of the current sense signals Vo1 to Vo3. In order to avoid this, the offset voltage Vos2 can be adjusted by the offset addition circuit, but this is performed on the input side of the operational amplifier 41, which affects the current sense signals Vo1 to Vo3.

  Therefore, trimming is performed by outputting trimming currents Ib4 to Ib6 to resistors R41 to R43 using current sources 43A, 43B and 43C, but the trimming is performed for each gain setting circuit for extracting current sense signals Vo1 to Vo3. The process is complicated.

Unexamined-Japanese-Patent No. 2006-109689 Unexamined-Japanese-Patent No. 2010-220355 Unexamined-Japanese-Patent No. 2016-067113

  It is an object of the present invention to adjust a current source of a trimming circuit so as to prevent the influence of an offset on the input side on the current sense signal even when current sense signals of different gains are taken out from N gain setting circuits. It is an object of the present invention to provide a current sense amplifier circuit and a switching power supply device using the same, which can be uniformly performed on N gain setting circuits.

となるように、Ｎ個のゲイン設定回路のα_Ｎとβ_Ｎを設定したことを特徴とする
請求項３にかかる発明は、請求項１又は２に記載の電流センスアンプ回路において、前記第２抵抗は前記Ｎ個のゲイン設定回路で同一値に設定され、前記制御トランジスタは前記Ｎ個のゲイン設定回路で同一導電型で同一サイズに設定されていることを特徴とする。
請求項４にかかる発明は、請求項１、２又は３に記載の電流センスアンプ回路において、前記Ｎ個のゲイン設定回路の内の少なくとも１個のゲイン設定回路の前記第２抵抗と前記制御トランジスタの直列回路が２以上に分割され並列接続されていることを特徴とする。
請求項５にかかる発明は、請求項１、２、３又は４に記載の電流センスアンプ回路において、オフセットを付加するオフセット付加回路が、前記オペアンプの非反転入力端子に接続されていることを特徴とする。
請求項６にかかる発明のスイッチング電源装置は、ドレインが第１ノードに接続されソースが第１電源端子に接続された第１スイッチングトランジスタと、ドレインが前記第１ノードに接続されソースが第１抵抗の他端に接続され前記第１スイッチングトランジスタと同期してＯＮ/ＯＦＦが制御される電流流検出トランジスタと、ドレインが前記第１ノードに接続されソースが第２電源端子に接続され、前記第１スイッチングトランジスタと相補的にＯＮ／ＯＦＦが制御される第２スイッチングトランジスタと、前記第１ノードと出力端子の間に接続されたインダクタと、前記出力端子と前記第２電源端子の間に接続された出力キャパシタと、請求項１乃至５のいずれか１つに記載の電流センスアンプ回路と、該電流センスアンプ回路のＮ個のゲイン設定回路で得られるＮ個の電流センス信号の内の１つと前記出力端子の出力電圧に応じて、前記電流検出トランジスタ、前記第１スイッチングトランジスタ、及び前記第２スイッチングトランジスタのＯＮ/ＯＦＦを制御する制御回路と、を備えることを特徴とする。 In order to achieve the above object, the current sense amplifier circuit of the invention according to claim 1 detects a current flowing through a first resistor whose one end is connected to a first power supply terminal based on a voltage generated in the first resistor. In the current sense amplifier circuit, an operational amplifier for amplifying a voltage generated in the first resistor, and N pieces controlled by the operational amplifier to take out current sense signals having different gains based on the voltage generated in the first resistor. A gain setting circuit (N = 1, 2,..., N) and a trimming circuit for trimming an influence of an offset on the input side of the operational amplifier, each of the N gain setting circuits 1) a second resistor whose one end is connected to the power supply terminal; a control transistor whose gate is connected to the output terminal of the operational amplifier and whose source is connected to the other end of the second resistor; A third resistor has one end connected to the drain of the transistor, and a fourth resistor connected between the other end of the third resistor and the second power supply terminal, and the operational amplifier has the N inverting input terminals. The non-inverting input terminal of one of the gain setting circuits is connected to the source of the control transistor, the non-inverting input terminal is connected to the other end of the first resistor, and the trimming circuit controls the current of the adjustable current source. A current mirror circuit configured to mirror and output the fourth resistor of the N gain setting circuits as a trimming current, the second resistor, the third resistor, the fourth resistor, and the current source of the trimming circuit The mirror ratio of the current mirror circuit with respect to the current of (4) is set so as to maintain a predetermined identical relationship among the N gain setting circuits.
The invention according to claim 2 is the current sense amplifier circuit according to claim 1, wherein the second resistor is R2N, the third resistor is R3N, the fourth resistor is R4N, and the trimming current of the trimming current is Assuming that the mirror ratio of the current mirror circuit to the current is MN, k is an arbitrary number,

According to a third aspect of the present invention, in the current sense amplifier circuit according to the first or second aspect of the present invention, α _N and β _N of _N gain setting circuits are set so that The resistors are set to the same value by the N gain setting circuits, and the control transistors are set to the same conductivity type and the same size by the N gain setting circuits.
The invention according to claim 4 is the current sense amplifier circuit according to claim 1, 2 or 3, wherein the second resistor and the control transistor of at least one gain setting circuit among the N gain setting circuits. The series circuit is divided into two or more and connected in parallel.
The invention according to claim 5 is characterized in that, in the current sense amplifier circuit according to claim 1, 2, 3 or 4, an offset adding circuit for adding an offset is connected to the non-inverting input terminal of the operational amplifier. I assume.
In the switching power supply device according to the invention, the drain is connected to the first node and the source is connected to the first power supply terminal, the drain is connected to the first node, and the source is the first resistor A current flow detection transistor connected to the other end of the switch to control ON / OFF in synchronization with the first switching transistor; a drain connected to the first node; a source connected to the second power supply terminal; A second switching transistor controlled to be turned on / off complementarily to the switching transistor, an inductor connected between the first node and the output terminal, and connected between the output terminal and the second power supply terminal An output capacitor, the current sense amplifier circuit according to any one of claims 1 to 5, and N current sense amplifier circuits. The current detection transistor, the first switching transistor, and the second switching transistor are turned ON / OFF according to one of the N current sense signals obtained by the gain setting circuit and the output voltage of the output terminal. And a control circuit for controlling.

  According to the present invention, the mirror ratio of the current mirror circuit with respect to the current of the second resistor, the third resistor, the fourth resistor, and the trimming current of the gain setting circuit is predetermined among N gain setting circuits. Since the same relationship is set to be maintained, trimming for avoiding the influence of the offset on the input side on the current sense signal is made uniform for the N gain setting circuits by adjusting the current source of the trimming circuit. Can be done.

FIG. 1 is a circuit diagram of a switching power supply device according to a first embodiment of the present invention. It is a characteristic view of the output voltage of current sense amplifier circuit 4A of FIG. It is trimming explanatory drawing of the output voltage of the current sense amplifier circuit 4A of FIG. It is a circuit diagram of the current sense amplifier circuit 4B of the switching power supply device of the second embodiment of the present invention and the vicinity thereof. It is a circuit diagram of the conventional switching power supply device. FIG. 6 is an operation waveform diagram of the switching power supply device of FIG. 5; FIG. 6 is a circuit diagram of another conventional switching power supply device.

First Embodiment
FIG. 1 shows an embodiment of a switching power supply according to the present invention. In this embodiment, as the current sense amplifier circuit 4A, an operational amplifier 41 for amplifying the voltage Vd generated in the resistor R1 and three current sense signals Vo1, Vo2 and Vo3 having different gains based on the voltage Vd generated in the resistor R1. , And three trimming circuits for trimming the offsets of the three gain setting circuits.

  In the first gain setting circuit, a PMOS control transistor MP31 whose gate is connected to the output terminal of the operational amplifier 41, its source is connected to the first power supply terminal 1 via the resistor R21, and its drain is connected to one end of the resistor R31 It comprises a resistor R41 connected between the other end of R31 and the second power supply terminal 2. The source of the transistor MP31 is connected to the inverting input terminal of the operational amplifier 41, and the transistor MP31 acts as a negative feedback control transistor.

  In the second gain setting circuit, a PMOS control transistor MP32 whose gate is connected to the output terminal of the operational amplifier 41, its source is connected to the first power supply terminal 1 via the resistor R22, and its drain is connected to one end of the resistor R32 It comprises a resistor R 42 connected between the other end of R 32 and the second power supply terminal 2.

  The third gain setting circuit is a PMOS control transistor MP33 whose gate is connected to the output terminal of the operational amplifier 41, its source is connected to the first power supply terminal 1 via the resistor R23, and its drain is connected to one end of the resistor R33 It comprises a resistor R 43 connected between the other end of R 33 and the second power supply terminal 2.

  43 is a current source having a variable current Ib0, MP40 is a PMOS transistor whose current source 43 is connected to the drain, MP41 to MP43 are PMOS transistors current-mirror connected to the transistor MP40, and these current sources 43 and The trimming current generating circuit is configured by the transistors MP40 to MP43. The trimming current Ib1 is M1 times the current Ib0 to the resistor R41 from the transistor MP41, M2 times the trimming current Ib2 to the resistor I42 from the transistor R42, and the resistor R43 from the transistor MP43 Thus, the trimming current Ib3 which is M3 times the current Ib0 can be applied.

  The resistors R21 to R23 are set to the same resistance value, and the transistors MP31 to MP33 are set to the same size. Therefore, the drain current IS1 of the transistor MP31, the drain current IS2 of the transistor MP32, and the drain current IS3 of the transistor MP33 are the same. Current (IS1 = IS2 = IS3).

  Therefore, if the resistance value is set as (R31 + R41) <(R32 + R42) <(R33 + R43), the current sense signal Vo1 obtained at the drain of the transistor MP31, the current sense signal Vo2 obtained at the drain of the transistor MP32, the transistor The current sense signal Vo3 obtained at the drain of the MP33 has gain characteristics shown in FIG. FIG. 2A shows gain characteristics when there is no offset voltage in the operational amplifier 41, and the current Isw that can be detected is limited to the current in the positive direction (direction from the input terminal 1 to the first node LX) of 0 or more. When the negative offset voltage Vos1 is present in the operational amplifier 41, the gain characteristic shown in FIG. 2B is obtained. The current Isw that can be detected in FIG. 2 (b) is limited to the forward current equal to or greater than Isw1.

  By the way, the direction of the first power supply terminal 1 from the first node LX is such that the current Isw flowing to the first node LX flows not only in the positive direction described above, but also the charge is not excessively accumulated in the capacitor C1 when the load is light. It may flow in the reverse direction. Since this backflow current is a current regenerated to the first power supply terminal 1, it is also called a regenerative current. In order to detect such a backflow current, it is necessary to give a large positive offset voltage to the operational amplifier 41 so as to obtain gain characteristics as shown in FIG. 2 (c). In FIG. 2C, it is possible to detect the reverse current indicated by Isw2.

  In order to detect even such reverse current, an offset voltage Vos (= Vos1 + Vos2) obtained by adding an offset voltage Vos2 by the resistor Ros and the current Ios of the current source 42 to the original offset voltage Vos1 of the operational amplifier 41 It is necessary to The added offset voltage Vos2 can be realized by trimming the current Ios, but is not preferable because it causes temperature drift. In addition, the current Isw2 may deviate from the target value due to the variation of the current sense amplifier circuit 4A.

  Therefore, in the present embodiment, while the offset voltage Vos (= Vos1 + Vos2) is set by the current Ios, when the current Isw2 is out of the target value, the trimming currents Ib1 to Ib3 are used at the output side of the current sense amplifier circuit 4A. Trimming is performed to adjust the offset voltage Vos to a target value.

  FIG. 3 is an explanatory view of the trimming process. When the reverse current to be detected is up to Isw 2, if the variation is generated so that the reverse current Isw 3 can be detected by the offset Vos, the trimming currents Ib 1, Ib 2, Ib 3 supplied from the transistors MP41, MP42, MP43 Can be adjusted to match the gain characteristics of the current sense signals Vo1, Vo2 and Vo3 shown by the dotted lines with the target gain characteristics shown by the solid lines. The trimming currents Ib1, Ib2 and Ib3 can be uniformly set by adjusting the current Ib0 of the current source 43. As described above, in order to uniformly adjust the gain characteristics of the gain setting circuits only by adjusting the trimming current, the resistors R21 to R23, R31 to R33, R41 to R43 of the current sense amplifier circuit 4A, the current mirror ratio M1, M2, M3 may be selected to satisfy the following equation.

となる。この電圧Ｖ１は、

で表すことができる。ａ傾き、ｂは切片であり、

である。 The input voltage V1 input to the operational amplifier 41 is such that the voltage of the power supply terminal 1 is Vin, the source voltage of the current detection transistor MP2 is Vd, the ON resistance of the first switching transistor MP1 is Ron, and the ON resistance of the current detection transistor MP2 is Rons. Then Ron <<<< Rons, so

It becomes. This voltage V1 is

Can be represented by a slope, b is an intercept,

It is.

で求められる。α_ＮはＮ番目の電流センス信号ＶｏＮを出力するゲイン設定回路のゲイン、β_Ｎは同ゲイン設定回路の切片であり、次の式で求まる。ＭＮはトランジスタＭＰ４１〜ＭＰ４４のカレントミラーの倍率（ＭＮ＝Ｍ１，Ｍ２，Ｍ３）である。

On the other hand, the current sense signal VoN (N is 1, 2, 3) on the output side of the current sense amplifier circuit 4A is

It is determined by α _N is the gain of the gain setting circuit that outputs the N-th current sense signal Vo _N , and β _N is the intercept of the gain setting circuit, which is obtained by the following equation. MN is the magnification (MN = M1, M2, M3) of the current mirror of the transistors MP41 to MP44.

の関係が保持できるように設定することで、電流源４３の電流Ｉ０ｂの調整のみで各ゲイン設定回路についてのトリミングを一律に行う。ｋは任意数である。以下、詳しく説明する。 In this embodiment, for each gain setting circuit, the resistances R2N, R3N, R4N, the magnification MN of the current mirror,

By setting so as to be able to hold the relationship of (1), trimming for each gain setting circuit is uniformly performed only by adjusting the current I0b of the current source 43. k is an arbitrary number. Details will be described below.

となり、Ｉｓｗ＝０のときは、

となる。 Equation (5) is derived from equation (2)

And if Isw = 0, then

It becomes.

となる。 When the offset of the circuit varies and the intercept b due to the offset Vos (= Vos1 + Ros × Ios) varies by db, the variation dVoN of the current sense signal when trimming the bias current Ib0 by dIb0 accordingly is

It becomes.

となる。

である。 Therefore, in order to offset the circuit variation, it is sufficient to set the above equation (11) to 0. In this case,

It becomes.

It is.

Although α _N and β _{N in} equation (13) are determined by the _Nth gain setting circuit, each gain setting circuit is preset so that the relationship between α _N and β _N becomes k shown in equation (13). In this case, when the intercept b of the equation (2) fluctuates by db, the fluctuation can be eliminated uniformly for each gain setting circuit only by trimming the bias current Ib0 of the current source 43 by dIb0. Therefore, if the current sense signal VoN at Isw = 0 of the Nth gain setting circuit is measured, and the variation dIb0 due to trimming is determined from the difference between the current value of VoN and the target value, the remaining gain setting circuit The trimming can be realized uniformly.

  Here, referring back to FIG. 3, in order to detect up to the target current Isw2 when the detection currents of the current sense signals Vo1, Vo2 and Vo3 are up to Isw3 due to the offset of the circuit, the current Ib0 You can adjust the Ib1 = Ib0 × M1, Ib2 = Ib0 × M2, Ib3 = Ib0 × M3; trimming amounts are Ib1 × R41 for Vo1, Ib2 × R42 for Vo2, and Ib3 × R43 for Vo3.

Second Embodiment
In the current sense amplifier circuit 4A of FIG. 1, three gain setting circuits are configured to obtain the current sense signals Vo1, Vo2 and Vo3, but in the example shown in FIG. It is further divided into three lines. The transistor MP31 of the gain setting circuit which has obtained the current sense signal Vo1 in FIG. 1 is divided into transistors MP311, MP312 and MP313, and the resistor R21 is divided into resistors R211, R212 and R213. Further, the transistor MP32 of the gain setting circuit which has obtained the current sense signal Vo2 in FIG. 1 is divided into the transistors MP321, MP322 and MP323, and the resistor R22 is divided into the resistors R221, R222 and R223.

  By dividing the transistor MP31 and the resistor R21 into three lines as described above, the current IS1 can be increased, and the gain of the gain setting circuit can be increased. This can avoid the need for a large resistance value for the resistors R31 and R41. Similarly, by dividing the transistor MP32 and the resistor R22 into three systems, the current IS2 can be increased, and the gain of the gain setting circuit can be increased. This can avoid the need for a large resistance value for the resistors R32 and R42. Furthermore, by setting all the resistors R211 to R213 and R221 to R223 to the same resistance value, the impedance at the source end of the control transistors MP312, MP313, MP321, MP322, MP323 is the same as the impedance at the source end of the control transistor MP311. The gain setting circuits can be easily matched.

<Other Embodiments>
Although the current sense amplifier circuits 4A and 4B described above detect the current flowing through the switching transistor MP1, the current sense amplifier circuit 4B detects the current flowing through the switching transistor MN1 for synchronous rectification. The same applies, for example, by using transistors of the opposite conductivity type. Also, these current sense amplifier circuits 4A and 4B can be applied to current detection other than the switching power supply device.

  1: power supply terminal 2: 2: ground terminal 3: output terminal 4A to 4D: current sense amplifier circuit 41: operational amplifier 42, 43 current source 5: control circuit 51: drive circuit 52: oscillator 53: Operational amplifier, 54: comparator

Claims (6)

In a current sense amplifier circuit that detects a current flowing through a first resistor whose one end is connected to a first power supply terminal based on a voltage generated in the first resistor,
N operational amplifiers controlled by the operational amplifier so as to take out current sense signals having different gains based on the voltages generated in the first resistor and the operational amplifiers that amplify the voltage generated in the first resistor (N = 1, 2, , N), and a trimming circuit for trimming the influence of the offset on the input side of the operational amplifier,
Each of the N gain setting circuits has a second resistor whose one end is connected to the first power supply terminal, a gate connected to the output terminal of the operational amplifier, and a source connected to the other end of the second resistor. A control transistor, a third resistor having one end connected to the drain of the control transistor, and a fourth resistor connected between the other end of the third resistor and the second power supply terminal,
The operational amplifier has an inverting input terminal connected to the source of the control transistor of one of the N gain setting circuits and a non-inverting input terminal connected to the other end of the first resistor.
The trimming circuit comprises a current mirror circuit that mirrors the current of the current adjustable current source and outputs the mirrored current to the fourth resistor of the N gain setting circuits.
The mirror ratio of the current mirror circuit to the current of the current source of the second resistor, the third resistor, the fourth resistor, and the trimming circuit has a predetermined same relationship among the N gain setting circuits. A current sense amplifier circuit which is set to be held. In the current sense amplifier circuit according to claim 1,
Assuming that the second resistor is R2N, the third resistor is R3N, the fourth resistor is R4N, and the mirror ratio of the trimming current to the current of the current source is MN, k is an arbitrary number.

A current sense amplifier circuit characterized by setting α _N and β _N of _N gain setting circuits so that In the current sense amplifier circuit according to claim 1 or 2,
The current sense amplifier is characterized in that the second resistor is set to the same value by the N gain setting circuits, and the control transistor is set to the same conductivity type and the same size by the N gain setting circuits. circuit. In the current sense amplifier circuit according to claim 1, 2 or 3
A series circuit of the second resistor of at least one of the N gain setting circuits and the control transistor is divided into two or more and connected in parallel. In the current sense amplifier circuit according to claim 1, 2, 3 or 4
A current sense amplifier circuit characterized in that an offset addition circuit for adding an offset is connected to the non-inversion input terminal of the operational amplifier. A first switching transistor having a drain connected to the first node and a source connected to the first power supply terminal;
A current flow detection transistor whose drain is connected to the first node, whose source is connected to the other end of the first resistor, and whose ON / OFF is controlled in synchronization with the first switching transistor;
A second switching transistor having a drain connected to the first node, a source connected to the second power supply terminal, and ON / OFF controlled complementarily to the first switching transistor;
An inductor connected between the first node and the output terminal;
An output capacitor connected between the output terminal and the second power supply terminal;
A current sense amplifier circuit according to any one of claims 1 to 5;
The current detection transistor, the first switching transistor, and the first switching transistor according to one of N current sense signals obtained by the N gain setting circuits of the current sense amplifier circuit and the output voltage of the output terminal. 2) A control circuit which controls ON / OFF of the switching transistor,
The switching power supply device characterized by having.

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