JP2019092020A5 - - Google Patents

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JP2019092020A5
JP2019092020A5 JP2017218953A JP2017218953A JP2019092020A5 JP 2019092020 A5 JP2019092020 A5 JP 2019092020A5 JP 2017218953 A JP2017218953 A JP 2017218953A JP 2017218953 A JP2017218953 A JP 2017218953A JP 2019092020 A5 JP2019092020 A5 JP 2019092020A5
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Japan
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tsv
routers
clusters
fault
virtual
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JP2017218953A
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JP2019092020A (ja
JP7239099B2 (ja
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JP2017218953A 2017-11-14 2017-11-14 ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置 Active JP7239099B2 (ja)

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JP2017218953A JP7239099B2 (ja) 2017-11-14 2017-11-14 ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置

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Application Number Priority Date Filing Date Title
JP2017218953A JP7239099B2 (ja) 2017-11-14 2017-11-14 ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置

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JP2019092020A JP2019092020A (ja) 2019-06-13
JP2019092020A5 true JP2019092020A5 (enExample) 2022-12-01
JP7239099B2 JP7239099B2 (ja) 2023-03-14

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JP2017218953A Active JP7239099B2 (ja) 2017-11-14 2017-11-14 ３ｄネットワークオンチップのためのｔｓｖ誤り耐容ルータ装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7277682B2 (ja) * 2019-07-03 2023-05-19 公立大学法人会津大学 ３次元ネットワークオンチップによるスパイキングニューラルネットワーク

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* Cited by examiner, † Cited by third party
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KR101737264B1 (ko) * 2016-02-05 2017-05-17 연세대학교 산학협력단 3차원 집적회로

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