JP2019088036A - Current detector and controller of rotary electric machine - Google Patents

Abstract

To provide a downsized current detector and a controller of a rotary electric machine comprising the downsized current detector.SOLUTION: A current detector 40 for detecting phase current flowing in a motor 10 comprises: TADs 43u, 43v and 43w; a TAD 43b; an arm current detection section 44; a bus current detection section 44; and an amplitude correction section 45. The TADs 43u, 43v and 43w are connected to first terminals of a lower arm switch Sn, and an analog signal indicative of a potential at a connection point is converted into numerical value data. The TAD 43b is connected to a negative electrode side bus Ln between second terminals of three lower arm switches Sn and a shunt resistor 23, and the analog signal indicative of the potential at the connection point is converted into numerical value data. The arm current detection section 44 calculates a difference between respective outputs of the TADs 43u, 43v and 43w and output of the TAD 43b, and detects phase current Irm flowing in the motor 10 on the basis of each of the calculated differences.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a technology for detecting a phase current flowing in a rotating electrical machine.

  A rotating electric machine controlled based on a phase current flowing in the rotating electric machine is known. In order to control such a rotating electrical machine, a current detection device that detects a phase current is required. Patent Document 1 describes a current detection device applied to a rotating electrical machine.

  The current detection device described in Patent Document 1 detects a bus current from an output of an A / D conversion circuit by connecting signal lines connected to both terminals of a shunt resistor connected to the bus to an A / D conversion circuit. doing. Further, in the current detection device described in Patent Document 1, A / D conversion is performed by connecting signal lines connected to input / output terminals of three lower arm switches included in a three-phase inverter to an A / D conversion circuit. The phase current of at least two phases is detected from the output of the circuit. The current detection device described in Patent Document 1 corrects the amplitude of the phase current based on the bus current and uses it.

JP, 2017-123736, A

The current detection device described in Patent Document 1 has a problem that it becomes large because it connects a total of six signal lines to three lower arm switches in order to detect phase currents of at least two phases.
This indication is made in view of the said situation, and aims at providing a control device of rotation electrical machinery provided with a miniaturized current detection device and a miniaturized current detection device.

  The present disclosure includes three DC power supplies (21), and a series connection of first arm switches (Sp, Sn) and second arm switches (Sn, Sp), and DC power supplies via bus lines (Lp, Ln). A rotary electric machine system comprising: an inverter (20) connected to the motor; a shunt resistor (23) provided on a bus connecting the DC power supply and the second arm switch; and a rotary electric machine (10) connected to the inverter Current detecting device for detecting a phase current flowing in a rotating electrical machine, comprising three first A / D conversion circuits (43u, 43v, 43w) and one second A / D conversion circuit (43b) And an arm current detection unit (44), a bus current detection unit (44), and an amplitude correction unit (45).

  The three first A / D conversion circuits are connected to each of the first terminals with the terminals of the second arm switch connected to the first arm switch as the first terminal, and the analog signals representing the potential at the connection point are numerical values Convert to data. The second A / D conversion circuit is an analog that represents a potential at a connection point, which is connected to a bus between the two second terminals and the shunt resistor, with the terminal of the second arm switch connected to the bus as the second terminal. Convert the signal into numerical data. The arm current detection unit outputs each of the outputs of the first A / D conversion circuit connected to the first terminal of the second arm switch in the on state during a period in which the second arm switch for at least two phases is in the on state. The difference with the output of the second A / D conversion circuit is calculated, and based on the calculated difference, phase currents for at least two phases flowing through the rotating electrical machine are detected. The bus current detection unit detects a bus current flowing through the shunt resistor as a phase current flowing through the rotating electrical machine. The amplitude correction unit is configured to generate respective amplitudes of second phase currents that are phase currents for at least two phases detected by the arm current detection unit based on the first phase current that is the phase current detected by the bus current detection unit. To correct the second phase current.

  According to the present disclosure, the potential at the first terminal of the lower arm switch in the on state is output as numerical data by the three first A / D conversion circuits, and the second terminal is output by the one second A / D conversion circuit. The potential of V is output as numerical data. Then, the difference between each of the outputs of the at least two first A / D conversion circuits and the output of the second A / D conversion circuit is calculated, and based on the calculated difference, the phase currents for at least two phases are A second phase current is detected. That is, the respective potentials of the second terminals of the lower arm switches are acquired by the common second A / D conversion circuit, and the respective potentials of the first terminals of the lower arm switches are acquired by the individual first A / D conversion circuits . Therefore, compared to the conventional case, the number of signal lines connecting the inverter and each A / D conversion circuit can be reduced from six to four, so that a miniaturized current detection device can be realized. In addition, since the potential difference between the first terminal and the second terminal is calculated by sharing the potential at the second terminal of each lower arm switch, the potential difference for each lower arm can be compared accurately.

  In addition, the reference numerals in parentheses described in this column and the claims indicate the correspondence with the specific means described in the embodiment described later as one aspect, and the technical scope of the present disclosure It is not limited.

It is a figure showing the whole motor control system composition of a 1st embodiment. FIG. 2 is a block diagram showing a configuration of an A / D conversion circuit. It is a figure which shows an example of the noise shape at the time of using the oversampling of an A / D conversion circuit. It is a figure which shows the relationship between a voltage vector and the phase current which can be acquired by bus current and arm current. It is a time chart which shows an example of detection timing of arm current and bus current. FIG. 7 is a circuit diagram showing how current flows when voltage vector V0 is applied. FIG. 7 is a circuit diagram showing how current flows at a voltage vector V1. It is a circuit diagram which shows the distribution | circulation aspect of the electric current at the time of voltage vector V2. It is a figure which shows the relationship between a modulation rate and the appearance time of an effective voltage vector and a zero voltage vector. It is a time chart which shows another example of the detection timing of an electric current. It is a time chart which shows another example of detection timing of current. It is a figure which shows the dispersion | variation in the voltage drop amount resulting from the individual difference and temperature of MOSEFT. It is a time chart which shows transition of each phase current which can be acquired from arm current. It is a time chart which shows transition of each phase current which can be acquired from bus current. It is a block diagram which shows the detail of an amplitude correction | amendment part. It is a figure which shows the whole structure of the motor control system of 2nd Embodiment.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
First Embodiment
<1. Overall configuration>
First, a configuration of a motor control system to which a current detection device of the first embodiment and a control device of a rotating electrical machine including the current detection device are applied will be described with reference to FIG. The motor control system of the first embodiment includes a motor 10, an inverter 20, and a control device 30.

  The motor 10 is a three-phase synchronous machine used to drive an on-vehicle accessory. As a synchronous machine, a permanent magnet synchronous machine is mentioned, for example. Examples of the on-vehicle accessory include a radiator fan, an air conditioner blower, and a water pump.

  The inverter 20 is a drive circuit that drives the motor 10. The inverter 20 includes three series connected bodies in which the upper arm switches Sup, Svp, Swp and the lower arm switches Sun, Svn, Swn are connected in series. Hereinafter, the upper arm switches Sup, Svp, Swp will be collectively referred to as an upper arm switch Sp, and the lower arm switches Sun, Svn, Swn will be collectively referred to as a lower arm switch Sn. Further, the upper arm switch Sp and the lower arm switch Sn are collectively referred to as an arm switch Spn.

  In the present embodiment, a voltage control type semiconductor switching element is used as the arm switch Spn. Specifically, an N-channel MOSFET is used as the arm switch Spn, and a parasitic diode is connected in antiparallel to each arm switch Spn. Each arm switch Spn is turned on or off in response to a control signal output from control device 30.

  The first end (not shown) of the winding of the corresponding phase of the motor 10 is connected to the connection point of the U-phase, V-phase and W-phase upper arm switches Sp and lower arm switches Sn. Further, the second ends of the U phase, V phase and W phase are connected to each other at a neutral point.

  The drain terminal of the upper arm switch Sp is connected to the positive side bus Lp connected to the positive terminal of the battery 21 which is a DC power supply. The source terminal of the lower arm switch Sn is connected to the negative electrode side bus Ln connected to the negative electrode terminal of the battery 21. The negative terminal of the battery 21 is grounded. The positive side bus Lp and the negative side bus Ln are connected by the smoothing capacitor 22 which smoothes the input voltage of the inverter 20. Further, a shunt resistor 23 is provided on the negative electrode side bus Ln. Specifically, the shunt resistor 23 is connected between the connection point of the source terminals of the three lower arm switches Sn and the negative electrode side bus Ln and the negative terminal of the battery 21. In the present embodiment, the upper arm switch Sp corresponds to the first arm switch, the lower arm switch Sn corresponds to the second arm switch, the drain terminal of the lower arm switch Sn corresponds to the first terminal, and the source terminal of the lower arm switch Sn It corresponds to the second terminal.

<2. Control device>
Next, the control device 30 will be described with reference to FIG. Control device 30 is mainly configured of a microcomputer, and turns on each arm switch Spn of inverter 20 based on the phase current flowing through motor 10 so as to control the rotational speed of motor 10 to command rotational speed Ntgt. And control off. In the present embodiment, control device 30 uses rotation angle information of motor 10 detected by a rotation angular velocity detection unit such as a Hall element or resolver according to the method described in FIG. 1 of JP-A-2004-64860. Control the rotational speed of the motor 10.

  Specifically, control device 30 includes current detection device 40, gain calculation unit 51, memory 52, current selection unit 53, amplitude setting unit 31, voltage phase setting unit 32, and basic function generation unit 33. , A basic function integrator 34, a target integral value setting unit 35, a first deviation calculating unit 36, a gain multiplying unit 37, and a second deviation calculating unit 38.

  The amplitude setting unit 31 sets a voltage amplitude that is the amplitude of the voltage vector of the inverter 20 based on the command rotational speed Ntgt of the motor 10. Specifically, the amplitude setting unit 31 sets the voltage amplitude based on, for example, a map in which the command rotational speed Ntgt and the voltage amplitude are associated. In the present embodiment, the voltage amplitude is defined as the square root of the sum of the square of the d-axis voltage Vd and the square of the q-axis voltage Vq. The d-axis and q-axis voltages Vd and Vq are the d-axis and q-axis components of the voltage vector. The commanded rotational speed Ntgt is input from, for example, a control device higher than the control device 30 to the control device 30.

  The voltage phase setting unit 32 sets a voltage phase basic value which is a basic value of the phase of the voltage vector. The phase of the voltage vector is defined, for example, as an angle between the d axis and the voltage vector. The voltage phase setting unit 32 sets the voltage phase basic value based on, for example, a map in which the command rotational speed Ntgt and the voltage phase basic value are associated with each other.

  The basic function generation unit 33 performs three operations of the motor 10 based on the electric angular velocity of the motor 10 determined based on the command rotational speed Ntgt and the voltage phase basic value corrected by the second deviation calculation unit 38 described later. Generate a sinusoidal basis function of the applied voltage for each phase. The sine wave basic functions of each of the three phases are sine wave signals whose phases are mutually shifted by 120 ° in electrical angle.

  The basic function integrator 34 calculates a basic function integral value by integrating the sine wave basic function generated by the basic function generation unit 33 in the integration period. The basic function integrator 34 determines an integration period based on the phase current output from the current selection unit 53 described later. The fundamental function integral value is a correlation value of the phase difference between the phase current flowing through the motor 10 and the sinusoidal fundamental function.

  The target integral value setting unit 35 sets a target integral value based on the command rotational speed Ntgt. The target integral value is an integral value of the sine wave fundamental function corresponding to the target phase difference between the phase current flowing through the motor 10 and the sine wave fundamental value. The target integral value setting unit 35 sets a target integral value based on, for example, a map in which the command rotational speed Ntgt and the target integral value are associated with each other.

  The first deviation calculation unit 36 calculates the deviation of the integral value by subtracting the basic function integral value calculated by the basic function integrator 34 from the target integral value set by the target integral value setting unit 35.

The gain multiplication unit 37 multiplies the deviation of the integrated value calculated by the first deviation calculation unit 36 by the gain A.
The second deviation calculation unit 38 corrects the voltage phase basic value by subtracting the product of the deviation of the integral value and the gain A from the voltage phase basic value set by the voltage phase setting unit 32. The second deviation calculating unit 38 inputs the corrected voltage phase basic value to the basic function generating unit 33.

  The signal generation unit 39 performs control signals gup, gun, gvp, and three-phase modulation based on the voltage amplitude set by the amplitude setting unit 31 and the sine wave fundamental function generated by the fundamental function generation unit 33. Generate gvn, gwp, gwn. Control signals gup, gun, gvp, gvn, gwp, gwn are PWM signals for turning on or off the upper or lower arm switches Sup, Sun, Svp, Svn, Swp, Swn, respectively.

  Specifically, the signal generation unit 39 calculates command duty ratios Dutyu, Dutyv, and Dutyw of U-phase, V-phase, and W-phase whose phases are mutually shifted by 120 ° in electrical angle based on the voltage amplitude and the sine wave basic function. Do. In the present embodiment, the command duty ratios Dutyu, Dutyv, and Dutyw are sine wave signals, and are standardized by the inter-terminal voltage Vdd of the battery 21. The signal generation unit 39 generates a control signal by pulse width modulation based on magnitude comparison between the command duty ratio and the carrier signal SigC in each of the three phases. In the present embodiment, the carrier signal SigC is a triangular wave signal in which the gradual increase rate and the gradual deceleration rate are equal. In each phase, control signals gup, gvp, gwp for the upper arm switch Sp and control signals gun, gvn, gwn for the lower arm switch Sn are signals complementary to each other. That is, in each phase, the upper arm switch Sp and the lower arm switch Sn are alternately turned on.

  Further, the signal generation unit 39 generates a pulse signal PA and a sampling clock PB which are input to a TAD 43 described later. In addition, the signal generation unit 39 generates a shunt timing and an arm timing to be input to a current detection unit 44 described later.

Note that the temperature sensor 24, the gain calculation unit 51, the memory 52, the current selection unit 53, and the current detection device 40 will be described later.
<3. Current detection device>
Next, the current detection device 40 will be described. The current detection device 40 includes five level shift circuits 41a, 41b, 41u, 41v, 41w, three protection circuits 42u, 42v, 42w, five TADs 43a, 43b, 43u, 43v, 43w, and currents. A detection unit 44 and an amplitude correction unit 45 are provided. Hereinafter, the five level shift circuits 41a, 41b, 41u, 41v, and 41w are collectively referred to as a level shift circuit 41, and the three protection circuits 42u, 42v, and 42w are collectively referred to as a protection circuit 42. The five TADs 43a, 43b, 43u, 43v, 43w are collectively referred to as TAD 43.

  The level shift circuit 41 a is connected between the shunt resistor 23 and the negative terminal of the battery 21. The level shift circuit 41 b is connected between the source terminals of the three lower arm switches Sn and the shunt resistor 23. The TADs 43a and 43b are connected to the level shift circuits 41a and 41b, respectively. The level shift circuits 41u, 41v, 41w are connected to the drain terminals of the lower arm switches Sun, Svn, Swn, respectively. Then, protection circuits 42u, 42v, 42w are connected to the level shift circuits 41u, 41v, 41w, respectively, and TADs 43u, 43v, 43w are connected to the protection circuits 42u, 42v, 42w, respectively. .

  That is, the TAD 43a is connected between the shunt resistor 23 and the negative terminal of the battery 21 via the level shift circuit 41a, and the TAD 43b is connected to the three lower arm switches Sn via the level shift circuit 41b. It is connected between the source terminal and the shunt resistor 23. The TADs 43u, 43v, 43w are connected to the drain terminals of the lower arm switches Sun, Svn, Swn via level shift circuits 41u, 41v, 43w and protection circuits 42u, 42v, 42w, respectively.

  The level shift circuit 41 is a circuit that sets an operating voltage of the TAD 43. The protection circuit 42 is a circuit that protects the TADs 43u, 43v, 43w by suppressing the voltages input to the TADs 43u, 43v, 43w within a predetermined range. When the upper arm switch Sp is on, a relatively large voltage is applied to the drain terminal of the lower arm switch Sn. Therefore, when the voltage applied to the drain terminal is directly input to the TAD 43 u, 43 v, 43 w, There is a risk of damaging the TAD 43 u, 43 v, 43 w. Therefore, a protection circuit 42 is provided. Since only a relatively small voltage is applied to both terminals of the shunt resistor 23, no protection circuit is required between the level shift circuits 41a and 41b and the TADs 43a and 43b, but a protection circuit may be provided. In the present embodiment, the TADs 43u, 43v, 43w correspond to a first A / D conversion circuit, the TAD 43b corresponds to a second A / D conversion circuit, and the TAD 43a corresponds to a third A / D conversion circuit.

  The TAD 43 is a time A / D conversion circuit that converts an analog input signal Vin into numerical data and outputs the numerical data. The TAD 43 a uses the potential of the terminal on the battery 21 side of the shunt resistor 23 as an analog input signal Vin, and outputs the potential of the terminal on the battery 21 side as numerical data. The TAD 43 b uses the potential of the terminal on the lower arm switch Sn side of the shunt resistor 23, that is, the potential of the source terminal of the lower arm switch Sn as an analog input signal Vin, and outputs the potential of the source terminal of the lower arm switch Sn as numerical data. The TADs 43u, 43v, 43w respectively use the potential of the drain terminal of the lower arm switch Sn as an analog input signal Vin, and output the potential of the drain terminal of the lower arm switch Sn as numerical data. The configuration of the TAD 43 will be described in detail below.

As shown in FIG. 2, the TAD 43 includes a delay line 431, a counter circuit 432, a latch & encoder 434, latch circuits 433 and 435, and an adder 436.
The delay line 431 is configured by connecting a plurality of delay units in a ring shape. The plurality of delay units include one NAND circuit and 31 inverter circuits. In the present embodiment, the delay line 431 includes 31 inverter circuits, but the number of inverter circuits may be any number. For example, a CMOS gate circuit having a PMOS transistor and an NMOS transistor can be employed as the NAND circuit and the inverter circuit.

  The delay line 431 is supplied with an analog input signal Vin as a driving power supply. A pulse signal PA for transmission is input to the input terminal of the NAND circuit. When the pulse signal PA input to the NAND circuit changes from low level to high level, the delay line 431 starts operating, and the pulse signal PA circulates around the delay line 431. The delay line 431 is configured to continue circulation without stopping the pulse signal PA.

  Then, each delay unit propagates the pulse signal PA while delaying the time corresponding to the analog input signal Vin. That is, the delay lines 431 are configured such that the number of delay units through which the pulse signal PA passes in a predetermined period is the number according to the magnitude of the potential as the analog input signal Vin. Therefore, the analog input signal Vin can be converted into numerical data by digitizing the number of passes of the delay unit in a predetermined period.

  The counter circuit 432 counts the number of times the pulse signal PA circulates the delay line 431. The latch circuit 433 receives the input of the sampling clock PB, and latches the output of the counter circuit 432 every sampling period. In the present embodiment, the number of rounds is represented by 17-bit numerical data. The latch & encoder 434 receives the input of the sampling clock PB and repetitively digitizes the position of the pulse signal PA in the delay line 431 every sampling period. In the present embodiment, the position of the pulse signal PA is represented by 5-bit numerical data.

  Then, 22-bit position data DTp is generated, in which the number of circulations of the pulse signal PA is the upper bit data and the position of the pulse signal PA in the delay line 431 is the lower bit data. The generated 22-bit position data DTp is input to the latch circuit 435 and the adder 436. The latch circuit 435 holds the latest position data DTp inputted, and outputs the position data DTp held immediately before the latest position data DTp as a comparison value to the adder 436. The adder 436 subtracts the comparison value from the latest position data DTp to generate 22-bit numerical data DT. This numerical data DT is a digitized potential corresponding to the analog input signal Vin.

  Here, the TAD 43 is used after oversampling. For example, the signal generation unit 39 generates a sampling clock PB with an oversampling ratio of 25, and the TAD 43 performs 25 times oversampling. As a result, as shown in FIG. 3, the output of the TAD 43 obtains the effect of noise shaping, and the resolution of the output is improved. Furthermore, the TAD 43 may apply a second-order low-pass filter to the output of the TAD 43 to reduce noise and improve the resolution of the output. By combining and applying the 25 × oversampling and the second-order low-pass filter, the resolution of the output of the TAD 43 can be increased by five times as compared with the case where the over-sampling and the second-order low-pass filter are not applied.

  The current detection unit 44 detects the bus current IDC flowing through the shunt resistor 23 as a phase current. Specifically, the current detection unit 44 calculates the difference between the outputs of the TAD 43 b and the TAD 43 a, and detects the bus current IDC as a phase current based on the calculated difference between the outputs. The difference between the calculated outputs of TAD 43 b and TAD 43 a corresponds to the voltage drop of shunt resistor 23.

  As shown in FIG. 4, in a period in which the voltage vector of the inverter 20 becomes the effective vectors V1 to V6, a phase current of one phase corresponding to the voltage vector flows in the shunt resistor 23. Therefore, the current detection unit 44 can detect the phase current of one phase according to the voltage vector based on the difference between the outputs of the TAD 43 b and the TAD 43 a. As shown in FIG. 5, since two types of effective voltage vectors appear twice in one cycle of the carrier signal SigC, the current detection unit 44 respectively generates phase currents for two phases in one cycle of the carrier signal SigC. It can be detected twice. In FIG. 5, the bus current IDC is detected as the phase current Iw of the W phase in a period in which the voltage vector is an even voltage vector V2 in one cycle of the carrier signal SigC, and the bus current is in a period in which the voltage vector is an odd voltage vector V1. The example which detects IDC as U phase current Iu is shown. In the present embodiment, the bus current IDC corresponds to the first phase current.

  Further, FIG. 7 shows that the U-phase current Iu can be detected based on the difference between the outputs of the TAD 43 b and the TAD 43 a in a period in which the voltage vector becomes the odd voltage vector V 1. FIG. 8 shows that the W-phase current Iw can be detected based on the difference between the outputs of the TAD 43 b and the TAD 43 a in a period in which the voltage vector is an even voltage vector V 2.

  The current detection unit 44 detects the bus current IDC at the shunt timing output from the signal generation unit 39. The signal generation unit 39 calculates a voltage vector based on each of the generated control signals, and outputs a shunt timing to the current detection unit 44 when it determines that the calculated voltage vector is the effective voltage vector V1 to V6. Specifically, the signal generation unit 39 outputs, as a shunt timing, a timing at which the base time Tsta has elapsed from the timing at which it is determined that the voltage vector is any of the effective voltage vectors V1 to V6. The specified time Tsta is the time from when the voltage vector is switched to when the ringing of the phase current converges.

  In the present embodiment, with regard to the current flowing through the shunt resistor 23, the direction of the current flowing from the inverter 20 side to the negative terminal side of the battery 21 among both terminals of the shunt resistor 23 is defined as positive. Further, with regard to the actual phase current, the direction of the current flowing from the inverter 20 side to the motor 10 side is defined as positive. For this reason, in the column of the bus current IDC shown in FIG. 4, a negative sign is attached when the sign of the phase current detected by the shunt resistor 23 is different from the sign of the actual phase current.

  Further, the current detection unit 44 detects phase currents for at least two phases based on the inter-terminal voltage Vds between the source terminal and the drain terminal of the lower arm switch Sn in the on state. Specifically, the current detection unit 44 calculates the difference between the output of each of the TAD 43 u, 43 v, 43 w and the TAD 43 b, and detects the U, V, W phase current Irmu, Irmv, Irmw based on the difference between the outputs. . The difference between the calculated TAD 43u, 43v, 43w and the output of the AD 43b corresponds to the inter-terminal voltage Vds of the lower arm switches Sun, Svn, Swn. Hereinafter, the U, V, W phase currents Irmu, Irmv, Irmv detected by the current detection unit 44 will be collectively referred to as a phase current Irm.

  As shown in FIG. 4, phase currents of 1 to 3 phases flow through the lower arm switch Sn during the on period according to the voltage vectors V0 to V6. The rotational speed control of the motor 10 requires at least two phases of phase currents. Therefore, in the present embodiment, the current detection unit 44 detects phase currents of three phases based on the inter-terminal voltage Vds of the lower arm switches Sun, Svn, and Swn in a period in which the voltage vector becomes the zero voltage vector V0. Do. FIG. 5 shows an example in which the U, V, W phase currents Irmu, Irmv, Irmw are detected at the timing when the carrier signal SigC becomes an extreme value in a period when the voltage vector becomes the zero voltage vector V0.

  Further, FIG. 6 shows that U, V, W phase currents Irmu, Irmv, Irmw are detected based on the difference between the outputs of TAD 43 u, 43 v, 43 w and TAD 43 b in a period when the voltage vector becomes zero voltage vector V0. Show what you can do. In the present embodiment, the phase current Irm corresponds to the second phase current.

  The current detection unit 44 detects the phase current Irm at the arm timing output from the signal generation unit 39. The signal generation unit 39 outputs an arm timing to the current detection unit 44 when it determines that the calculated voltage vector is the zero voltage vector V0. Specifically, for example, when the signal generation unit 39 determines that the period in which the voltage vector is the zero voltage vector V0 has become equal to or more than the period obtained by doubling the defined time Tsta, the period in which the period is the zero voltage vector V0 Among them, the timing at which the carrier signal SigC becomes the maximum value and / or the timing at which the value becomes the minimum value is output as the arm timing. The condition that the period in which the voltage vector is the zero voltage vector V0 is equal to or more than the period obtained by doubling the defined time Tsta is a condition for avoiding the arm timing being included in the period in which ringing occurs.

  In the present embodiment, the sign of the inter-terminal voltage Vds when the drain potential of the lower arm switch Sn is higher than the source potential is defined as positive. Further, regarding the actual phase current, as described above, the current direction flowing from the inverter 20 side to the motor 10 side is defined as positive. For this reason, in the column of arm current shown in FIG. 4, a negative sign is attached when the sign of the voltage Vds between terminals is different from the sign of the actual phase current.

  The amplitude correction unit 45 adjusts the U, V, and W phase currents Irmu so that the amplitudes of the U, V, and W phase currents Irmu, Irmv, and Irmw are equalized based on the bus current IDC detected by the current detection unit 44. , Irmv, Irmw are corrected.

  As shown in FIG. 12, when a predetermined drain current Id flows in each lower arm switch Sn, the inter-terminal voltage Vds of each lower arm switch Sn varies depending on the individual difference and temperature of each lower arm switch Sn. . FIG. 12 shows the variation due to the individual difference in the case where the lower arm switch Sn has a relatively high temperature. When the terminal voltage Vds of each phase varies, the amplitudes of the phase currents Irmu, Irmv, and Irmw of the detected three phases will vary.

  FIG. 13 illustrates an example in which the amplitude of the U-phase current Irmu detected by the current detection unit 44 and the amplitudes of the V and W-phase currents Irmv and Irmw deviate. When the phase current Irm whose amplitude is dispersed is used to control the rotational speed of the motor 10, the controllability of the rotational speed may be degraded, for example, the rotational speed may fluctuate.

  Here, since the bus current IDC detected by the current detection unit 44 is detected from the voltage drop amount of a single element, as shown in FIG. 9, there is no variation due to individual differences among the elements. Therefore, the bus current IDC detected by the current detection unit 44 can be used to reduce variations in amplitude of the phase current Irm detected by the current detection unit 44.

Specifically, the amplitude correction unit 45 corrects the amplitudes of the phase currents Irmu, Irmv, and Irmw using the correction gains Gu, Gv, and Gw of each phase calculated by the gain calculation unit 51.
As shown in FIG. 15, the gain calculation unit 51 includes a correction gain calculation unit 51a and a temperature correction unit 51b. As shown in FIG. 14, the correction gain calculation unit 51a detects U, V, W phase currents Isu, Isv, Isw which are bus current IDC sequentially detected by the current detection unit 44 in the electrical angle range over 180 °. Get the peak value. Hereinafter, the U, V, W phase currents Isu, Isv, Isw are collectively referred to as a phase current Is. In the present embodiment, the signs of the peak values of the three-phase phase current Is are made positive or negative. The peak value may be detected by, for example, a peak hold circuit.

  The correction gain calculation unit 51a acquires peak values of the U, V, and W phase currents Irmu, Irmv, and Irmw detected by the current detection unit 44. In the present embodiment, the sign of the peak value of the three-phase phase current Irm is matched with the sign of the three-phase phase current Is. The correction gain calculation unit 51a divides each peak value of the phase currents Isu, Isv, Isw by each peak value of the phase currents Irmu, Irmv, Irmw, and the absolute value of each division value is corrected gain Gu, Gv, Gw Calculated as Hereinafter, the correction gains Gu, Gv, and Gw will be collectively referred to as a correction gain G.

  The temperature correction unit 51b corrects the correction gain G to be lower as the temperature of the shunt resistor 23 detected by the temperature sensor 24 (hereinafter, detected temperature Ts) is higher. The temperature sensor 24 is a temperature detection unit that detects the temperature of the shunt resistor 23.

  As the temperature of the shunt resistor 23 increases, the resistance value of the shunt resistor 23 increases. Therefore, when the predetermined phase current Is flows through the shunt resistor 23, as the temperature of the shunt resistor 23 increases, the voltage drop amount of the shunt resistor 23 increases, and the phase current Is detected by the current detection unit 44 increases. Become. Therefore, in the present embodiment, in order to increase the detection accuracy of the phase current Is, the correction gain G is corrected to be smaller so that the phase current Is becomes smaller as the detection temperature Ts becomes higher. As a specific correction method, for example, the method described below can be adopted.

  The temperature correction unit 51b sets the temperature correction coefficient Kt (> 0) to 1 when the detected temperature Ts is the same as the reference temperature Tref. Further, the temperature correction unit 51b sets the temperature correction coefficient Kt smaller as the detected temperature Ts becomes larger than the reference temperature Tref, and sets the temperature correction coefficient Kt larger as the detected temperature Ts becomes smaller than the reference temperature Tref. Then, the temperature correction unit 51 b corrects each of the correction gains G by multiplying each of the correction gains G by the temperature correction coefficient Kt, and inputs the correction gain G to the amplitude correction unit 45 and the memory 52.

  The amplitude correction unit 45 corrects each of the phase currents Irm by multiplying each of the phase currents Irm detected by the current detection unit 44 by each of the correction gains G. Thereby, the variation in amplitude of each phase current Irm is reduced.

  In the memory 52, the correction gain G output from the temperature correction unit 51b is stored in order to increase the correction opportunity of the phase current Irm detected by the current detection unit 44. Here, since calculation of the correction gain G requires both the phase current Irm and the phase current Is detected by the current detection unit 44, the modulation area in which the correction gain G can be calculated is only the middle modulation area. That is, the correction gain G can not be calculated in the low modulation region and the high modulation region. Since the modulation factor Mr at the time of startup of the motor 10 is in the low modulation region, the correction gain G can not be calculated at the time of startup of the motor 10.

  Therefore, when the modulation factor Mr is in the middle modulation area, the calculated correction gain G is stored in the memory 52. As a result, when the motor 10 is started next time, the phase current Irm detected by the current detection unit 44 can be corrected using the correction gain G stored in the memory 52.

<5. Current selection>
The current selection unit 53 is for control using at least one of the phase current Is and the phase current Irm detected by the current detection unit 44 based on the modulation factor Mr of the output voltage of the inverter 20 to control the control amount of the motor 10. Select as current. In the present embodiment, the modulation factor Mr corresponds to the amplitude of the duty ratio. The current selection unit 53 is provided to prevent the detection accuracy of the phase current from being reduced immediately after the voltage vector is switched, due to the occurrence of ringing in the phase current.

  Specifically, when it is determined that the modulation factor Mr is in the low modulation region, the current selection unit 53 selects and selects the phase current Irm for three phases output from the amplitude correction unit 45 as a control current. The phase current Irm of the three-phase part is output to the basic function integrator 34. As shown in FIG. 9, the low modulation area is an area where the modulation factor Mr is 0 or more and less than the first predetermined value M1. The first prescribed value M1 is set to a modulation factor Mr equal to the prescribed time Tsta from when the voltage vector is switched to when the ringing converges after the voltage vector is changed to the effective voltage vector. The time taken to be an effective voltage vector becomes longer as the modulation factor Mr becomes larger. In FIG. 10, when the modulation ratio Mr is in the low modulation region, the timing when the carrier signal SigC becomes the maximum value in the period when the zero voltage vector V0 is the detection timing TD of the phase current Imr, that is, the arm timing. Indicates

  In addition, when the current selection unit 53 determines that the modulation factor Mr is in the middle modulation region, the phase current Imr detected by the current detection unit 44 for each of the three phases detected by the current detection unit 44 An average value with the current Is is selected as the control amount current. Then, the current selection unit 53 outputs the selected average value to the basic function integrator 34. As shown in FIG. 9, the middle modulation area is an area where the modulation factor Mr is equal to or more than the first predetermined value M1 and less than the second predetermined value M2. Here, the reason for calculating the average value is to mitigate the influence even if noise is mixed in any of the phase current Imr and the phase current Is detected by the current detection unit 44. The second prescribed value M2 is set to the modulation factor Mr in which the time during which the voltage vector is the zero voltage vector V0 is equal to the prescribed time Tsta. The time taken to be the zero voltage vector V0 becomes shorter as the modulation factor Mr becomes larger.

  Furthermore, when it is determined that the modulation factor Mr is in the high modulation region, the current selection unit 53 sequentially selects the phase current Is corresponding to the phase current of one phase detected by the current detection unit 44 as a control current. And sequentially output the selected phase current Is to the basic function integrator 34. FIG. 11 shows that, of the periods in which the effective voltage vectors V1 and V2 are established, the timing at which the specified time Tsta has elapsed since the switching of the voltage vector is the detection timing TD of the phase current Is, that is, the shunt timing.

<6. Effect>
According to the first embodiment described above, the following effects can be obtained.
(1) The potential of the drain terminal of the lower arm switch Sn in the on state is output as numerical data by the TADs 43 u, 43 v, 43 w, and the potential of the source terminal of the lower arm switch Sn in the on state is output as numerical data by the TAD 43 b. Ru. And the difference of each of the output of TAD43u, 43v, 43w, and the output of TAD43b is calculated, and the phase current Imru, Imrv, Imrw is detected based on the calculated difference. That is, the potential of the source terminal of each lower arm switch Sn is acquired by the common TAD 43 b, and the potential of the drain terminal of each lower arm switch Sn is acquired by the individual TAD 43 u, 43 v, 43 w. Therefore, compared with the conventional case, the signal line connecting the inverter 20 and the TAD 43 for detecting the phase current Imr can be reduced from 6 lines to 4 lines. It can be realized. In addition, since the potential difference between the drain terminal and the source terminal of each lower arm switch Sn is calculated by sharing the potential of the source terminal of each lower arm switch Sn, the potential difference for each lower arm switch Sn should be compared accurately. Can.

  (2) By further providing the TAD 43a, it is possible to calculate the difference between the outputs of the TAD 43a and the TAD 43b, that is, the amount of voltage drop of the shunt resistor. Therefore, the bus current IDC can be detected based on the difference between the outputs of the TAD 43a and the TAD 43b.

(3) The TAD 43 is used after oversampling. Therefore, noise shaping can be realized to improve the resolution of the output value of the TAD 43.
(4) By selecting at least one of the phase current Imr and the phase current Is as the control current based on the modulation factor Mr, ringing occurs in the phase current immediately after the voltage vector is switched. It is possible to prevent the detection accuracy of the control current from being lowered.

  (5) When the modulation factor Mr is in the middle modulation area, both the phase current Imr and the phase current Is can be detected. Therefore, by setting the average of the phase current Imr and the phase current Is as a control current, even if noise is mixed in any of the phase current Imr and the phase current Is, the influence of the noise can be alleviated.

Second Embodiment
<1. Differences from the First Embodiment>
The basic configuration of the second embodiment is the same as that of the first embodiment, and thus the description of the common configuration will be omitted, and differences will be mainly described. The same reference numerals as those in the first embodiment denote the same components, and reference is made to the preceding description.

  The configuration of the motor control system of the second embodiment is shown in FIG. The motor control system of the second embodiment differs from the motor control system of the first embodiment in that a controller 30A is provided instead of the controller 30. Control device 30A differs from control device 30 in that a current detection device 40A is provided instead of current detection device 40.

  The current detection device 40A differs from the current detection device 40 in the detection unit of the bus current IDC. Specifically, the current detection device 40A differs from the current detection device 40 in that the level shift circuit 41a and the TAD 43a are not provided. That is, the current detection device 40A does not detect the potential on the side of the terminal of the shunt resistor 23 which is grounded.

  The current detection unit 44 detects the bus current IDC based on the output of the TAD 43 b connected between the shunt resistor 23 and the source terminal of the lower arm switch Sn. Among both terminals of the shunt resistor 23, the terminal to which the level shift circuit 41b and the TAD 43b are not connected is grounded. Therefore, the current detection unit 44 can detect the voltage drop amount of the shunt resistor 23 only from the potential detected by the TAD 43 b among the potentials of both terminals of the shunt resistor 23. However, the output of the TAD 43b includes an offset amount. Therefore, the current detection unit 44 subtracts the offset amount from the potential detected by the TAD 43 b to correct the potential, and detects the bus current IDC from the corrected potential.

<2. Effect>
According to the second embodiment described above, in addition to the effects (1) to (5) of the first embodiment described above, the following effects can be obtained.

  (6) One of both terminals of the shunt resistor 23 is grounded. Therefore, the output of the TAD 43 b has a value corresponding to the voltage drop amount of the shunt resistor 23. Therefore, the phase current Is can be detected based on the output of the TAD 43 b.

(Other embodiments)
As mentioned above, although the form for implementing this indication was described, this indication can be variously deformed and implemented, without being limited to an above-mentioned embodiment.

(A) In the above embodiments, although the correction gain G is corrected by the temperature correction unit 51b, the correction of the correction gain by the temperature correction unit 51b may not be performed.
(B) In each of the above embodiments, the correction gain calculation unit 51a calculates the correction gain G using the phase current Imr and the peak value of the phase current Is, but using other than the peak value to calculate the correction gain G It is also good. For example, for each of the phase current Imr and the phase current Is, it is possible to use the value of the timing advanced by a predetermined electrical angle from the timing of the peak value.

  (C) The current detection unit 44 generates the phase current Imr of two phases based on the voltage Vds between the terminals of the lower arm switch Sn of two phases in a period when the voltage vector becomes the odd voltage vector V1, V3, V5. It may be detected. Then, the current detection unit 44 may calculate the phase current for the remaining one phase using the fact that the sum of the phase currents for the three phases is zero.

  (D) The switching element constituting the inverter 20 is not limited to the MOSFET, and may be, for example, an IGBT. In this case, a free wheeling diode may be connected in reverse parallel to the IGBT. The switching element constituting the inverter 20 is not limited to the voltage control type element, and may be a current control type element such as a bipolar transistor.

  (E) The shunt resistor 23 may be provided on the positive electrode bus Lp instead of the negative electrode bus Ln. Specifically, the positive side bus Lp may be provided between the positive electrode terminal of the battery 21 and the upper arm switch Sp. In this case, the TAD 43a may be connected between the battery 21 and the shunt resistor 23, and the TAD 43b may be connected between the shunt resistor 23 and the drain terminal of the upper arm switch Sp. Then, the current detection unit 44 may detect the phase current Irm based on the inter-terminal voltage Vds of the upper arm switch Sp. Further, in this case, the upper arm switch Sp corresponds to a second arm switch, and the lower arm switch Sn corresponds to a first arm switch.

(F) The control amount of the motor 10 is not limited to the rotational speed, and may be, for example, a torque.
(G) The plurality of functions of one component in the above embodiment may be realized by a plurality of components, or one function of one component may be realized by a plurality of components . Also, a plurality of functions possessed by a plurality of components may be realized by one component, or one function realized by a plurality of components may be realized by one component. In addition, part of the configuration of the above embodiment may be omitted. In addition, at least a part of the configuration of the above-described embodiment may be added to or replaced with the configuration of the other above-described embodiment. In addition, all the aspects contained in the technical thought specified only by the words described in the claim are an embodiment of this indication.

  DESCRIPTION OF SYMBOLS 10 ... Motor, 20 ... Inverter, 21 ... Battery, 40, 40A ... Current detection apparatus, 43a, 43b, 43u, 43v, 43w ... TAD, 44 ... Current detection part, 45 ... Amplitude correction part, Sun, Swn ... Lower arm Switch, Snp, Svp, Swp ... Upper arm switch.

Claims (7)

Three series connected bodies of a DC power supply (21), a first arm switch (Sp, Sn) and a second arm switch (Sn, Sp), and connected to the DC power supply via a bus (Lp, Ln) Rotating electric machine system comprising: an inverter (20); a shunt resistor (23) provided on a bus connecting the DC power supply and the second arm switch; and a rotating electric machine (10) connected to the inverter Current detecting device (40, 40A) for detecting a phase current flowing to the rotating electric machine,
A / D conversion is performed on the terminals of the second arm switch connected to the first arm switch as first terminals and connected to each of the first terminals to convert an analog signal representing the potential at the connection point into numerical data Three first A / D conversion circuits (43u, 43v, 43w) which are circuits;
A terminal of the second arm switch connected to the bus is used as a second terminal, and a bus connected between the three second terminals and the shunt resistor is connected to an analog signal representing a potential at a connection point as numerical data A second A / D conversion circuit (43b), which is an A / D conversion circuit that converts
The respective outputs of the first A / D conversion circuit connected to the first terminal of the second arm switch in the on state and the second arm switch in a state in which the second arm switch of the at least two phases is in the on state An arm current detection unit (44) that calculates a difference with the output of the 2A / D conversion circuit and detects phase current for at least two phases flowing in the rotating electric machine based on the calculated difference;
A bus current detection unit (44) that detects a bus current flowing through the shunt resistor as a phase current flowing through the rotating electrical machine;
Based on the first phase current that is the phase current detected by the bus current detection unit, the amplitudes of the second phase currents that are the phase currents of at least two phases detected by the arm current detection unit are made uniform. An amplitude correction unit (45) for correcting the second phase current;
Current detection device. The third A / D conversion circuit (43a), which is connected between the shunt resistor and the DC power supply, is an A / D conversion circuit that converts an analog signal representing the potential at the connection point into numerical data. Equipped
The bus current detection unit calculates a difference between outputs of the second A / D conversion circuit and the third A / D conversion circuit, and detects the first phase current based on the calculated difference.
The current detection device according to claim 1. The first arm switch is an upper arm switch connected to a positive electrode terminal of the DC power supply via the bus bar,
The second arm switch is a lower arm switch connected to the negative terminal of the DC power supply via the bus bar,
Of the two terminals of the shunt resistor, the terminal on the side of the DC power supply is grounded.
The bus current detection unit detects the first phase current based on the output of the second A / D conversion circuit.
The current detection device according to claim 1. The A / D conversion circuit is used by oversampling.
The current detection device according to any one of claims 1 to 3. A control device for a rotating electrical machine, comprising the current detection device according to any one of claims 1 to 4 and controlling a control amount of the rotating electrical machine based on a phase current detected by the current detection device, ,
A current selection unit (53) for selecting at least one of the first phase current and the second phase current as a control current used to control the control amount based on a modulation factor of an output voltage of the inverter;
The amplitude correction unit corrects the second phase current when the current selection unit selects the second phase current as the control current.
Control device of rotating electric machine. When it is determined that the modulation factor is in the low modulation area, the current selection unit selects the second phase current as the control current, and the modulation factor is higher in the high modulation area than the low modulation area. When it is determined that there is, the first phase current is selected as the control current,
The control apparatus of the rotary electric machine of Claim 5. The current selection unit determines an average of the first phase current and the second phase current when it is determined that the modulation rate is in a middle modulation area sandwiched between the low modulation area and the high modulation area. Select as the control current,
The control apparatus of the rotary electric machine of Claim 6.