JP2019077601A - Group iii nitride semiconductor substrate and production method of group iii nitride semiconductor substrate - Google Patents

Abstract

To enhance internal quantum efficiency of a device formed on a group III nitride semiconductor substrate.SOLUTION: A group III nitride semiconductor substrate 20 includes a sapphire substrate 21 and a group III nitride semiconductor layer 23 which is positioned on the sapphire substrate 21 and of which the principal plane (growth plane 24) is a semipolar plane and is represented by a Miller index (hkml), where l is less than 0. A half value width of XRC (X-ray Rocking Curve) of {11-22} plane is 500 arcsec or less, as measured by making X-rays incident on the growth plane 24 of the group III nitride semiconductor layer 23 parallel to m-axis of the group III nitride semiconductor crystal and scanning an angle between the incident direction of the X-rays and the growth plane 24.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a group III nitride semiconductor substrate and a method of manufacturing a group III nitride semiconductor substrate.

  Related techniques are disclosed in Patent Document 1 and Patent Document 2. As disclosed in Patent Document 1 and Patent Document 2, when a device (e.g., an optical device, an electronic device, etc.) is formed on the c-plane of a Group III nitride semiconductor crystal, the internal quantum is caused by the piezoelectric field. Efficiency is reduced. Therefore, attempts have been made to form devices on so-called semipolar surfaces (surfaces different from polar surfaces and nonpolar surfaces).

  Further, related techniques are disclosed in Patent Document 3 and Patent Document 4. As disclosed in Patent Document 3 and Patent Document 4, a semipolar film prepared by cutting out a crystal piece having a semipolar surface as a main surface from bulk III-nitride semiconductor crystal and bonding the crystal pieces An attempt has been made to manufacture a group III nitride semiconductor crystal having a plane as the main surface.

  Further, a related technology is disclosed in Patent Document 5. As disclosed in Patent Document 5, a GaN-based semiconductor optical device having a (20-21) plane and a (20-2-1) plane which are semipolar planes inclined in the m-axis direction from the c-plane. Attempts have been made to manufacture.

JP, 2012-160755, A JP, 2016-12717, A JP, 2010-13298, A JP, 2013-82628, A JP 2012-15555 A

  An object of the present invention is to provide a technique for improving the internal quantum efficiency of a device formed on a group III nitride semiconductor substrate.

According to the invention
With sapphire substrate,
A Group III nitride semiconductor layer located on the sapphire substrate and whose main surface is a semipolar surface;
Have
X-rays were incident parallel to the m-axis of the group III nitride semiconductor crystal to the main surface of the group III nitride semiconductor layer, and the angle between the incident direction of the X-rays and the main surface was scanned and measured {11 There is provided a group III nitride semiconductor substrate in which the half-width of XRC (X-ray Rocking Curve) with respect to the (22) plane is 500 arcsec or less.

  According to the present invention, the internal quantum efficiency of a device formed on a group III nitride semiconductor substrate can be improved.

It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is an Example which shows the difference with the group III nitride semiconductor substrate of this embodiment. It is a flowchart which shows an example of the flow of a process of the manufacturing method of the group III nitride semiconductor substrate of this embodiment. It is a side surface schematic diagram which shows an example of the group III nitride semiconductor substrate of this embodiment. It is a side surface schematic diagram which shows an example of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the difference with the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the characteristic of the group III nitride semiconductor substrate of this embodiment. It is a figure which shows the measurement result of a comparative example. It is a figure which shows the measurement result of an Example. It is a figure for demonstrating the measurement point of XRC.

  Hereinafter, embodiments of a group III nitride semiconductor substrate and a method of manufacturing a group III nitride semiconductor substrate of the present invention will be described with reference to the drawings. The drawings are merely schematics for explaining the configuration of the invention, and the sizes, shapes, numbers, and ratios of sizes of different members are not limited to those illustrated.

  First, an outline of the present embodiment will be described. According to the method of manufacturing a group III nitride semiconductor substrate of the present embodiment including a plurality of characteristic steps, a group III nitride semiconductor is grown on a sapphire substrate using a semipolar plane on the N polarity side as a growth plane Can. As a result, a group III nitride semiconductor substrate (template substrate) can be obtained in which the group III nitride semiconductor layer whose exposed surface is a semipolar surface on the N polarity side is located on a sapphire substrate. In addition, by peeling the sapphire substrate from the template substrate or from the laminate in which the group III nitride semiconductor is thick-film grown on the template substrate, group III nitriding is performed with the semipolar plane on the N polarity side as the growth plane. A group III nitride semiconductor substrate (a freestanding substrate) comprising a group III nitride semiconductor layer obtained by growing an oxide semiconductor is obtained.

  In the present embodiment, “a semipolar surface which is expressed by Miller index (hk ml) and l is more than 0” may be referred to as “a semipolar surface on the Ga polarity side”. In addition, "a semipolar surface, which is expressed by Miller index (hk ml) and l is less than 0" may be referred to as "a semipolar surface on the N polarity side".

  Further, by adjusting a part of the manufacturing method of the group III nitride semiconductor substrate of the characteristic embodiment, X-rays are made of the group III nitride semiconductor crystal with respect to the main surface of the group III nitride semiconductor layer. Group III nitride semiconductor substrate (template substrate) that is incident parallel to the m-axis and the XRC half width at 500 arcsec or less with respect to the {11-22} plane measured by scanning the angle between the X-ray incident direction and the main surface Is obtained.

  Furthermore, by adjusting a part of the manufacturing method of the group III nitride semiconductor substrate of the characteristic embodiment of the present invention, X-rays are made of the group III nitride semiconductor crystal with respect to the main surface of the group III nitride semiconductor layer. Group III in which the half width of XRC with respect to the {11-22} plane is 500 arcsec or less, incident parallel to the projection axis obtained by projecting the c axis onto the main surface and scanning the angle formed by the incident direction of the X-ray and the main surface A nitride semiconductor substrate (template substrate) is obtained.

  By forming devices on such a group III nitride semiconductor substrate (template substrate, freestanding substrate), improvement in internal quantum efficiency is realized. The details will be described below.

  First, a method of manufacturing a group III nitride semiconductor substrate (template substrate) will be described. FIG. 3 is a flowchart showing an example of a process flow of a method of manufacturing a group III nitride semiconductor substrate (template substrate). As illustrated, the method of manufacturing a group III nitride semiconductor substrate (template substrate) includes a substrate preparation step S10, a heat treatment step S20, a preflow step S30, a buffer layer formation step S40, and a growth step S50. .

  In the substrate preparation step S10, a sapphire substrate is prepared. The diameter of the sapphire substrate is, for example, 1 inch or more. The thickness of the sapphire substrate is, for example, 250 μm or more.

  The plane orientation of the main surface of the sapphire substrate is one of a plurality of elements controlling the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown thereon. The relationship between the element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following example. In the substrate preparation step S10, a sapphire substrate whose main surface is a desired surface orientation is prepared.

  The main surface of the sapphire substrate is, for example, a {10-10} plane or a plane in which the {10-10} plane is inclined at a predetermined angle in a predetermined direction.

  The {10-10} plane is inclined at a predetermined angle in a predetermined direction, for example, the {10-10} plane is inclined at any angle within 0 ° and 0.5 ° or less in any direction. It may be a plane.

  In addition, a surface in which the {10-10} plane is inclined at a predetermined angle in a predetermined direction is any one of 0 ° to less than 10.5 ° in a direction in which the {10-10} plane is parallel to the a plane. It may be a surface inclined at an angle. Alternatively, a surface in which the {10-10} plane is inclined at a predetermined angle in a predetermined direction is any one of 0 ° to 10.5 ° in a direction in which the {10-10} plane is parallel to the a plane. It may be a surface inclined at an angle. For example, a plane in which the {10-10} plane is inclined at a predetermined angle in a predetermined direction is 0.5 ° or more and 1.5 ° or less in a direction in which the {10-10} plane is parallel to the a plane. A surface inclined at an angle of more than 2.5 ° or less, 4.5 ° or more and 5.5 ° or less, 6.5 ° or more and 7.5 ° or less, and 9.5 ° or more and 10.5 ° or less It may be

  The heat treatment step S20 is performed after the substrate preparation step S10. In the heat treatment step S20, heat treatment is performed on the sapphire substrate under the following conditions.

Temperature: 800 ° C. to 1200 ° C., preferably 800 ° C. to 930 ° C. Pressure: 30 torr to 760 torr Heat treatment time: 5 to 20 minutes Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio 0 ~ 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (However, since the supply amount varies depending on the size of the growth apparatus, it is not limited to this.)

Note that the heat treatment on the sapphire substrate may be performed while performing the nitriding treatment, or may be performed without performing the nitriding treatment. When the heat treatment is performed while performing the nitriding treatment, NH _{3 of} 0.5 slm or more and 20 slm or less is supplied onto the sapphire substrate during the heat treatment (however, since the supply amount varies depending on the size of the growth apparatus, it is not limited thereto). In addition, when heat treatment is performed without performing nitriding treatment, NH ₃ is not supplied at the time of heat treatment.

  The presence or absence of the nitriding treatment at the time of heat treatment may be one of a plurality of elements controlling the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between the element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following example.

  The temperature for heat treatment at a temperature of 800 ° C. or more and 1200 ° C. or less is a temperature for manufacturing the template substrate or the self-supporting substrate of the present embodiment having a group III nitride semiconductor layer in which the main surface is a semipolar surface on the N polarity side. It is a condition. The temperature 800 ° C. to 930 ° C. at the time of heat treatment is a temperature condition for manufacturing the template substrate of the present embodiment in which the half width of XRC with respect to the {11-22} plane is 500 arcsec or less.

  The pre-flow step S30 is performed after the heat treatment step S20. In the pre-flow step S30, the metal-containing gas is supplied on the main surface of the sapphire substrate under the following conditions. The pre-flow step S30 may be performed, for example, in an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.

Temperature: 500 ° C. or more and 1000 ° C. or less Pressure: 30 torr or more to 200 torr or less Trimethylaluminum supply amount, supply time: 20 ccm or more to 500 ccm or less, 1 second to 60 seconds or less Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio 0 to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (however, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth apparatus)

  The above conditions are for supplying trimethylaluminum and triethylaluminum which are organic metal raw materials as metal-containing gas. In this process, a metal-containing gas containing another metal is supplied instead of trimethylaluminum triethylaluminum, and another metal film such as a titanium film, a vanadium film or a copper film is used as the main surface of the sapphire substrate instead of the aluminum film. It may be formed on top. In addition, other metal carbide films such as aluminum carbide, titanium carbide, vanadium carbide and copper carbide, which are reaction films with hydrocarbon compounds such as methane, ethylene and ethane generated from organic metal raw materials, on the main surface of the sapphire substrate You may form.

  In the pre-flowing step S30, a metal film and a metal carbide film are formed on the main surface of the sapphire substrate. The presence of the metal film is a condition for reversing the polarity of the crystal grown thereon. That is, in the implementation of the pre-flowing step S30, the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate is a plurality of elements for making the semipolar plane on the N polarity side. It is one of the

  The buffer layer formation step S40 is performed after the pre-flow step S30. In the buffer layer forming step S40, a buffer layer is formed on the main surface of the sapphire substrate. The thickness of the buffer layer is, for example, 20 nm or more and 300 nm or less.

  The buffer layer is, for example, an AlN layer. For example, an AlN crystal may be epitaxially grown under the following conditions to form a buffer layer.

Growth method: MOCVD Growth temperature: 800 ° C. to 950 ° C. Pressure: 30 torr to 200 torr Trimethylaluminum supply amount: 20 ccm to 500 ccm NH ₃ supply amount: 0.5 slm to 10 slm Carrier gas: H ₂ or H ₂ And N ₂ (H ₂ ratio 0 to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (however, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth apparatus)

  The growth conditions for the buffer layer formation step S40 may be one of a plurality of elements controlling the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate. The relationship between the element and the plane orientation of the growth surface of the group III nitride semiconductor layer is shown in the following example.

  Also, the growth conditions (relatively lower predetermined growth temperature, specifically 800 to 950 ° C., and relatively lower pressure) in the buffer layer formation step S40 are for growing AlN while maintaining the N polarity side. It becomes a condition. That is, the growth conditions in the buffer layer formation step S40 are a plurality of elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate to the semipolar plane on the N polarity side. It is one of the

  The growth step S50 is performed after the buffer layer formation step S40. In the growth step S50, a group III nitride semiconductor crystal (for example: GaN crystal) is epitaxially grown on the buffer layer under the following growth conditions, and the growth surface becomes a predetermined surface orientation (semipolar surface on the N polarity side) Forming a group III nitride semiconductor layer. The thickness of the group III nitride semiconductor layer 30 is, for example, not less than 1 μm and not more than 20 μm.

Growth method: MOCVD Growth temperature: 800 ° C. or more and 1025 ° C. or less
Pressure: 30 torr to 200 torr TMGa supply amount: 25 sccm to 1000 sccm NH3 supply amount: 1 slm to 20 slm Carrier gas: H ₂ or H ₂ and N ₂ (H ₂ ratio 0 to 100%)
Carrier gas supply amount: 3 slm or more and 50 slm or less (however, the gas supply amount is not limited to this because it varies depending on the size and configuration of the growth apparatus)
Growth rate: 10 μm / h or more

  The growth conditions (relatively low growth temperature, relatively low pressure, relatively fast growth rate) in the growth step S50 are conditions for growing GaN while maintaining the N polarity side. That is, the growth conditions in the growth step S50 are a plurality of elements for making the plane orientation of the growth surface of the group III nitride semiconductor layer epitaxially grown on the main surface of the sapphire substrate the semipolar plane on the N polarity side. It is one of the

  By manufacturing under the above conditions, as shown in FIG. 4, the sapphire substrate 21, the buffer layer 22 and the group III nitride semiconductor layer 23 are stacked in this order, and the growth surface of the group III nitride semiconductor layer 23 is obtained. A group III nitride semiconductor substrate 20 in which the plane orientation of 24 is a semipolar plane on the N polarity side can be manufactured. Further, by adjusting the manufacturing conditions within the range of the above conditions, the plane orientation of the growth surface 24 can be made a desired semipolar plane.

  Next, a method of manufacturing a group III nitride semiconductor substrate (a freestanding substrate) will be described.

  For example, after the laminate (template substrate) as shown in FIG. 4 is manufactured according to the flow shown in FIG. 3, the sapphire substrate 21 and the buffer layer 22 are removed from the laminate (peeling step), as shown in FIG. The group III nitride semiconductor substrate 10 (self-supporting substrate) which consists of such a group III nitride semiconductor layer 23 can be manufactured. The means for removing the sapphire substrate 21 and the buffer layer 22 is not particularly limited. For example, stress caused by the difference in linear expansion coefficient between the sapphire substrate 21 and the group III nitride semiconductor layer 23 may be used to separate them. Then, the buffer layer 22 may be removed by polishing, etching or the like.

  As another removal example, a peeling layer may be formed between the sapphire substrate 21 and the buffer layer 22. For example, a carbon layer in which carbide (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide) is dispersed, and carbide (aluminum carbide, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide) After forming a laminated body of the above layers on the sapphire substrate 21, the layer subjected to the nitriding treatment may be formed as a peeling layer.

  When the buffer layer 22 and the group III nitride semiconductor layer 23 are formed on such a peeling layer, the stack is heated at a temperature higher than the heating temperature at the time of forming the group III nitride semiconductor layer 23 The separation layer can be separated into a part on the sapphire substrate 21 side and a part on the group III nitride semiconductor layer 23 side with the part of the peeling layer as a boundary. By removing the buffer layer 22 and the like from the portion on the side of the group III nitride semiconductor layer 23 by polishing, etching or the like, a group III nitride semiconductor substrate 10 (group III nitride semiconductor layer 23 shown in FIG. It is possible to obtain a free standing substrate).

  As an example of another manufacturing method of a self-supporting substrate, a laminate (template substrate) as shown in FIG. 4 is produced according to the flow shown in FIG. 3, and then on the template substrate (on the III-nitride semiconductor layer 23). ), For example, a Group III nitride semiconductor may be thick-film grown by HVPE (Hydride Vapor Phase Epitaxy) to form an HVPE layer. As a result, on the template substrate (on the group III nitride semiconductor layer 23), an HVPE layer of a group III nitride semiconductor in which the exposed surface is a semipolar surface on the N polarity side is obtained. The growth conditions for epitaxially growing a group III nitride semiconductor by the HVPE method are not particularly limited, and if a semipolar plane on the N polarity side is used as a growth plane, thick film growth of the group III nitride semiconductor is possible if adopting the one according to the prior art. It can be done. Then, the group III nitride semiconductor substrate 10 (self-supporting substrate) may be obtained by slicing or the like from the HVPE layer.

  Next, configurations and features of the group III nitride semiconductor substrate 20 (template substrate) and the group III nitride semiconductor substrate 10 (free-standing substrate) obtained by the above manufacturing method will be described.

  As shown in FIG. 4, the group III nitride semiconductor substrate 20 (template substrate) includes a sapphire substrate 21, a buffer layer 22 formed on the sapphire substrate 21, and a group III formed on the buffer layer 22. And the nitride semiconductor layer 23. The main surface (growth surface 24) of the group III nitride semiconductor layer 23 is a semipolar surface, is expressed by a Miller index (hk ml), and is a surface where l is less than zero.

  The film thickness of the group III nitride semiconductor layer 23 is 1 μm or more and 20 μm or less. Then, an X-ray is incident parallel to the m-axis of the group III nitride semiconductor crystal with respect to the main surface of the group III nitride semiconductor layer 23, and the angle between the incident direction of the X-ray and the main surface is scanned and measured { The half width of XRC with respect to the (11-22) plane is 500 arcsec or less.

  Further, X-rays are incident on the main surface of the group III nitride semiconductor layer 23 parallel to the projection axis of the c-axis of the group III nitride semiconductor crystal projected onto the main surface, and the incident direction of the X-rays and the main surface The half-width of XRC with respect to the {11-22} plane measured by scanning the formed angle is 500 arcsec or less.

As shown in the following examples, the thickness of the group III nitride semiconductor layer is a semipolar plane, represented by the Miller index (hk ml), and when the group III nitride semiconductor is epitaxially grown on a growth plane where l exceeds 0, The greater the thickness, the worse the crystallinity. As a result, as the thickness of the group III nitride semiconductor layer increases, the half-width of XRC with respect to the {11-22} plane increases. Therefore, when the growth surface is a semipolar surface, is represented by Miller index (hk ml), and l is a surface exceeding 0, the crystallinity is good and a thick film III nitride semiconductor layer is manufactured. It is difficult.

  On the other hand, as shown in the following examples, when a group III nitride semiconductor is epitaxially grown on a growth surface which is a semipolar surface, is represented by a Miller index (hk ml), and l is less than 0, the group III nitride semiconductor layer The crystallinity hardly changes even when the thickness of In the case of the present embodiment in which a group III nitride semiconductor is epitaxially grown on a growth surface which is a semipolar surface, is represented by a Miller index (hk ml), and l is less than 0, the crystallinity is good as described above and As described above, a thick (for example, 100 μm or more) group III nitride semiconductor layer can be manufactured.

  As shown in FIG. 5, the group III nitride semiconductor substrate 10 (the free-standing substrate) is composed of a group III nitride semiconductor layer 23 composed of a group III nitride semiconductor crystal. The film thickness of the group III nitride semiconductor substrate 10 (self-supporting substrate) is 100 μm or more.

  The self-supporting substrate is made of a group III nitride semiconductor crystal, and the exposed first and second main surfaces 11 and 12 in a front-back relationship are both semipolar surfaces. X-rays are incident in parallel to the m axis of the group III nitride semiconductor crystal on each of the first main surface 11 and the second main surface 12, and the angle between the X-ray incident direction and the main surface is scanned for measurement The half width of XRC for the {11-22} plane is 500 arcsec or less. In addition, X-rays are incident on the first major surface 11 and the second major surface 12 in parallel to the projection axis of the c-axis of the group III nitride semiconductor crystal projected onto the major surface, respectively. The half-width of XRC with respect to the {11-22} plane measured by scanning the angle formed by the main surface is 500 arcsec or less.

  Note that after a group III nitride semiconductor is epitaxially grown on a sapphire substrate, the growth surface is a semipolar surface, is represented by a Miller index (hk ml), and l exceeds 0, the sapphire substrate is taken from the group III nitride semiconductor layer. When removed, the appearance becomes the same as the group III nitride semiconductor substrate 10 (the free standing substrate) of the present embodiment shown in FIG. However, such a substrate and the group III nitride semiconductor substrate 10 (the free-standing substrate) of the present embodiment have a growth surface when epitaxially growing a group III nitride semiconductor is “semipolar and the Miller index (hkml Or l) is greater than 0 or "a semipolar surface, is represented by the Miller index (hk ml), and it differs in whether l is less than 0".

  The difference can be confirmed by looking at the relationship between the film thickness and the difference in the half-width of XRC of the main surface which is in the relation between the front and back.

  As described above, when a group III nitride semiconductor is epitaxially grown on a growth surface which is a semipolar surface, is represented by a Miller index (hk ml), and l is greater than 0, the thickness of the group III nitride semiconductor layer becomes thicker. The crystallinity deteriorates and the half width of XRC increases. That is, the larger the film thickness, the larger the difference in XRC half value widths of the main surfaces in the relation between the front and back.

  On the other hand, when a group III nitride semiconductor is epitaxially grown on a growth surface which is a semipolar surface, is represented by a Miller index (hk ml), and l is less than 0, the thickness of the group III nitride semiconductor layer becomes large. The crystallinity hardly changes. That is, even if the film thickness is increased, the difference in half-width of XRC of the main surfaces in the relation between the front and back becomes equal to or less than a predetermined level.

  From the above, the group III nitride semiconductor substrate is a “semipolar surface, and the Miller index ( hkml), "1 is greater than 0" epitaxially grown on a growth surface, or "a semipolar surface, represented by Miller index (hkml), l less than 0" growth surface It can be confirmed whether it has been formed by epitaxial growth.

  Specifically, when the film thickness is 300 μm or more, when the difference in the half width of XRC of the main surfaces in the relationship between the front and back is 100 arcsec or less, the surface is a semipolar surface and Miller index (hkml) It can be said that it is a group III nitride semiconductor substrate formed by epitaxial growth on a growth surface of “l less than 0”. When the film thickness is 300 μm or more and the difference in the half width of XRC of the main surfaces in the front and back relationship is larger than 100 arcsec, it is a semipolar surface and is represented by Miller index (hkml) It can be said that the group III nitride semiconductor substrate is formed by epitaxial growth on a growth surface where l is greater than zero.

  Next, the operation and effect of the present embodiment will be described.

  According to the method of manufacturing a group III nitride semiconductor substrate of the present embodiment, a group III nitride semiconductor can be grown on a sapphire substrate using a semipolar plane on the N polarity side as a growth plane. As a result, as shown in FIG. 4, the group III nitride semiconductor substrate 20 in which the group III nitride semiconductor layer 23 whose exposed surface (growth surface 24) is a semipolar surface on the N polarity side is located on the sapphire substrate 21 ( Template substrate is obtained. In addition, as shown in FIG. 5, a group III nitride semiconductor substrate 10 (group III nitride semiconductor layer 23 obtained by growing a group III nitride semiconductor with the semipolar plane on the N A self-supporting substrate is obtained.

  By forming devices on such a group III nitride semiconductor substrate (template substrate, freestanding substrate), improvement in internal quantum efficiency is realized.

  Moreover, if the group III nitride semiconductor substrate (template substrate, self-supporting substrate) of this embodiment is used, a device can be formed on the main surface which is a semipolar surface by the side of N polarity. In such a case, not only the reduction of the piezoelectric polarization due to the effect of the semipolar surface but also the reduction of the spontaneous polarization is realized. Therefore, the Stark effect caused by the internal electric field can be suppressed.

  Furthermore, when the group III nitride semiconductor is grown with the semipolar plane on the N polarity side as the growth plane, the present inventors grew the group III nitride semiconductor using the semipolar plane on the Ga polarity side as the growth plane. It has been confirmed that the surface condition tends to be flat compared to the case. When a group III nitride semiconductor is grown with the semipolar plane on the Ga polarity side as the growth plane, pits and facets derived from the m-plane component tend to occur. Also in such a point, the group III nitride semiconductor substrate (template substrate, self-supporting substrate) of the present embodiment is excellent.

  Furthermore, when the group III nitride semiconductor is grown with the semipolar plane on the N polarity side as the growth plane, the present inventors grew the group III nitride semiconductor using the semipolar plane on the Ga polarity side as the growth plane. It has been confirmed that the incorporation of impurities is smaller than in the case. Specifically, HaLL measurements of two polar planes (a semipolar plane on the N polar side and a semipolar plane on the Ga polar side) grown in the same device and under the same growth conditions were carried out. When the group III nitride semiconductor is grown with the polar plane as the growth plane, the carrier concentration is one digit smaller than when the group III nitride semiconductor is grown with the semipolar plane on the Ga polarity side as the growth plane. confirmed. It is presumed that this is because the uptake of O was reduced. Also in such a point, the group III nitride semiconductor substrate (template substrate, self-supporting substrate) of the present embodiment is excellent.

  Further, according to the present embodiment, a Group III nitride semiconductor layer formed on a sapphire substrate, which is a semipolar surface, is represented by a Miller index (hk ml), and has an exposed main surface where l is less than 0, A group III nitride semiconductor substrate having a sapphire substrate as a base substrate is provided. Further, by performing crystal growth on the group III nitride semiconductor substrate, the group III nitride semiconductor free-standing substrate in which the exposed first and second main surfaces in the relationship between the front and back are both semipolar surfaces is provided. Be done.

  The exposed first and second main surfaces of the group III nitride semiconductor freestanding substrate provided by the present embodiment are, for example, 38.0 ° or more in the a-plane direction from the c-plane, for example. .0 and not more than 16.0 degrees and not more than 16.0 degrees in the m plane direction, and the other is 38.0 degrees to 53.0 degrees in the -a plane direction from the -c plane. It is a semipolar surface inclined by -16.0 ° or more and 16.0 ° or less in the m-plane direction. In addition, the main surface of the group III nitride semiconductor substrate having a sapphire substrate as a base substrate is, for example, 38.0 ° to 53.0 ° in the a-plane direction from the -c plane and -16.0 ° in the m-plane direction. It is a semipolar surface inclined by 16.0 ° or less.

  In particular, when a light emitting device (LED, LD) is formed on the main surface, the plane ((11-24) plane) inclined 39.1 ° from the c-plane to the a-plane is Jpn. J. Appl. Phys. Vol. As shown in Fig. 1 reported in Fig. 1 reported in 39 (2000) pp. 413-416, the internal quantum efficiency due to the Stark effect equivalent to the m-plane and a-plane of the nonpolar plane is zero because the piezoelectric field is zero. The reduction effect of the decrease in the power consumption can reduce the power consumption and improve the light emission efficiency. In addition, the principal plane ((-1-12-4) plane) inclined 39.1 ° from the -c plane to the -a plane direction is not only the reduction of the piezoelectric polarization due to the effect of the semipolar plane but Reduction of spontaneous polarization occurring in the direction of atoms is also realized. Therefore, the Stark effect caused by the internal electric field generated in the active layer of the light emitting device (LED, LD) can be further suppressed, so that the performance of the light emitting device (LED, LD) can be further improved.

  The group III nitride semiconductor layers provided in Patent Document 1 and Patent Document 2 are both semipolar planes, represented by Miller index (hk ml), and have a main surface in which l exceeds 0, this embodiment In comparison with a III-nitride semiconductor substrate having a III-nitride semiconductor layer having a main surface with a major surface less than 0 and a sapphire substrate, the semipolar surface being provided by The device's internal quantum efficiency is low.

  If the group III nitride semiconductor substrate having a sapphire substrate as an underlying substrate provided by the present embodiment is used, the sapphire substrate is equivalent to the size of the sapphire substrate used if it is removed by any method including known techniques and conventional techniques. Thus, it is possible to manufacture a group III nitride semiconductor free-standing substrate which has a large diameter, uniform in-plane crystallinity of the substrate, surface flatness, impurity concentration, and axial deviation of plane orientation and does not require a precise manufacturing technique. The well-known technique and the conventional technique referred to here are, for example, chemical etching, mechanical polishing, crystal peeling using thermal stress, and the like.

  The group III nitride semiconductor free-standing substrate provided by the methods of Patent Document 3 and Patent Document 4 joins crystal pieces cut out in any plane orientation from the group III nitride semiconductor free-standing substrate whose main surface is c-plane It is a manufactured group III nitride semiconductor free-standing substrate having a semipolar surface as a main surface. In order to realize this, a high yield can be realized because a process of cutting out a large amount of crystal pieces from the bulk crystal and a process of aligning the crystal pieces in the same high crystal axis direction with high accuracy are necessary. Need precise technology to do this. In addition, since the crystal pieces are joined to increase the diameter of the substrate, displacement of atomic positions occurs at the junctions, and high-density dislocations occur in the junctions. As a result, the decrease in the crystallinity of the substrate and the in-plane distribution unevenness of the dislocation density occur. Also, if the bonding surface is a c-face, m-face, or a face inclined from the m-face toward the c-face, facets such as {11-22} or {10-11} appear. As shown in (2), large depressions and crystal growth abnormalities occur, so that the surface flatness is significantly deteriorated and the bonding strength is insufficient, which makes it difficult to handle the substrate.

  In addition, in order to solve the difficulty in handling of the substrate due to the remarkable deterioration of the surface flatness due to the large depression and the crystal growth abnormality as shown in FIG. 2 and the insufficient bonding strength, the methods of Patent Document 3 and Patent Document 4 are used. It is easy to consider that the bonding surface is only the a-plane and the inclined surface from the a-plane, but also in this case, dislocation generation due to the displacement of the atomic position at the bonding surface and the in-plane of the dislocation density accompanying this Uneven distribution can not be resolved. In addition, since crystal bonding is performed with the a-plane or the a-plane inclined, it is not possible to manufacture the group III nitride semiconductor free-standing substrate with the main plane of the a-plane inclined provided in the present embodiment. .

  The first and second main surfaces of the group III nitride semiconductor free-standing substrate provided by the present embodiment are both inclined surfaces of, for example, the a-plane, and thus have cleavage planes (m-planes) on the side surfaces. By providing a substrate having a cleavage plane, it is possible to easily obtain a reflective mirror surface excellent in flatness, in which atoms are regularly and finely arranged, which are essential for optical resonance in a semiconductor laser (LD).

  The GaN-based semiconductor laser device having the (20-21) plane and the (20-2-1) plane as the principal planes provided in Patent Document 5 is cleaved at the side surfaces because the principal plane is the m-plane inclined plane. It does not have a face. Therefore, it is not possible to obtain a highly flat reflective mirror that can obtain optical resonance. Therefore, in the manufacture of a product, a high-level and precise technique for flattening the side surface is required, and the manufacturing process is complicated. In addition, since a reflective mirror having inferior flatness is used, the performance is improved as compared to a GaN-based semiconductor optical laser device in which a mirror structure is manufactured using a cleavage plane.

<First evaluation>
In the first evaluation, the group III nitride semiconductor is satisfied by satisfying all of the “plural elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semipolar plane on the N polarity side” described above. It was confirmed that the plane orientation of the growth surface of the layer can be made a semipolar plane on the N polarity side. In addition, when at least one of the “plural elements for making the growth surface of the group III nitride semiconductor layer a semipolar surface on the N polarity side” is not satisfied, the group III nitride is used. It was confirmed that the plane orientation of the growth surface of the semiconductor layer was a semipolar plane on the Ga polarity side.

  First, a sapphire substrate was prepared, which is a plane inclined at 2 ° in the direction parallel to the a-plane from the m-plane ((10-10) plane) from the m-plane ((10-10) plane). The sapphire substrate had a thickness of 430 μm and a diameter of 2 inches.

  And with respect to the prepared sapphire substrate, heat processing process S20 was implemented on condition of the following.

Temperature: 1000 to 1050 ° C.
Pressure: 100 torr
Carrier gas: H ₂ , N ₂
Heat treatment time: 10 minutes or 15 minutes Carrier gas supply: 15 slm

In the heat treatment step S20, 20 slm of NH ₃ was supplied to perform nitriding treatment.

Thereafter, the pre-flow step S30 was performed under the following conditions.
Temperature: 800 to 930 ° C
Pressure: 100 torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

  Then, buffer layer formation process S40 was performed on condition of the following, and the AlN layer was formed.

Growth method: MOCVD growth temperature: 800 to 930 ° C.
Pressure: 100 torr
Trimethylaluminum supply amount: 90 sccm
NH ₃ supply amount: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

  Thereafter, the growth step S50 is performed under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD pressure: 100 torr
TMGa supply: 50 to 500 sccm (continuous change)
NH ₃ supply amount: 5 to 10 slm (continuous change)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm
Growth rate: 10 μm / h or more

  The growth temperature of the first sample was controlled to 900 ° C. ± 25 ° C., and the growth temperature of the second sample was controlled to 1050 ° C. ± 25 ° C. That is, the first sample is a sample that satisfies all the “plural elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semipolar plane on the N polarity side” described above. The second sample is a part of the “plural elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semipolar plane on the N polarity side” described above (the growth temperature in the growth step S50 It is a sample that does not satisfy).

  The plane orientation of the growth surface of the group III nitride semiconductor layer of the first sample is a direction inclined 5.0 degrees in the -a plane direction from the (-1-12-4) plane and parallel to the m plane. It was a surface inclined below 5 °. On the other hand, the plane orientation of the growth surface of the group III nitride semiconductor layer of the second sample is inclined by 5.0 ° in the a-plane direction from the (11-24) plane and 8.5 ° in the direction parallel to the m-plane The following was an inclined surface. That is, the plane orientation of the growth plane is Ga polarity depending on whether the above-mentioned “plural elements for setting the plane orientation of the growth plane of the group III nitride semiconductor layer to the semipolar plane on the N polarity side” are satisfied or not. It can be seen that it can be adjusted whether it becomes or N polarity.

  FIG. 6 shows the results of measuring the XRD pole points of the (-1-12-4) plane or the (11-24) plane in the first sample. It can be confirmed that the diffraction peak is a position several degrees away from the center point of the pole. Detailed measurement of angular deviation: -a plane direction 5.0 ° and 8.5 ° in the direction parallel to the m plane, or a plane direction 5.0 ° and parallel to the m plane 8 It can be confirmed that the position is .5 °.

  FIG. 7 shows the results of confirming that the exposed surface (growth surface 24) shown in FIG. 4 in the first sample is N-polar. Also, as a comparison, FIG. 8 shows the result of a group III nitride semiconductor free-standing substrate fabricated by slicing from a thick film-grown GaN free-standing substrate of + c plane to have the same plane orientation as the first sample. The first sample and the semipolar freestanding substrate prepared by slicing from the + c-plane GaN freestanding substrate were both polished on both sides (front and back of the substrate) by 1.5 μm, and the mixed solution of phosphoric acid and sulfuric acid was maintained at 150 ° C. Etching was performed for 30 minutes.

  From FIGS. 7 and 8, the etched surface condition of the back surface (N-polar surface) of the semipolar free-standing substrate fabricated by slicing from the exposed surface (growth surface 24) of the first sample and the + c-plane GaN free-standing substrate is equal. You can confirm that. In addition, since it can be confirmed that the etched surface state of the surface (Ga polar surface) of the semipolar free-standing substrate fabricated by slicing from the peeling surface of the first sample and the + c-plane GaN free-standing substrate is identical, as shown in FIG. It can be confirmed that the exposed surface (growth surface 24) is N-polar.

  The present inventors do not satisfy the other part of the “plural elements for setting the plane orientation of the growth surface of the group III nitride semiconductor layer to the semipolar plane on the N polarity side” described above. In addition, it has been confirmed that the plane orientation of the growth surface is Ga polarity even in the case where the whole is not satisfied.

<Second evaluation>
In the second evaluation, the plane orientation of the growth plane of the group III nitride semiconductor layer is adjusted by adjusting the “plural elements for adjusting the plane orientation of the growth plane of the group III nitride semiconductor layer” described above. I confirmed that I could do it.

  First, a plurality of sapphire substrates having various principal plane orientations were prepared. The sapphire substrate had a thickness of 430 μm and a diameter of 2 inches.

  And with respect to each prepared sapphire substrate, heat processing process S20 was performed on condition of the following.

Temperature: 1000 to 1050 ° C.
Pressure: 200 torr
Heat treatment time: 10 minutes Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

In addition, the sample which varied the presence or absence of the nitriding treatment at the time of heat processing was created. Specifically, 20 slm of NH ₃ was supplied at the time of heat treatment, and a sample to be nitrided was prepared, and a sample not to be supplied with NH ₃ at the heat treatment and not to be nitrided was prepared.

Thereafter, the pre-flow step S30 was performed under the following conditions.
Temperature: 880-930 ° C
Pressure: 100 torr
Trimethylaluminum supply amount, supply time: 90 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

  In addition, both the sample which performs pre-flow process S30, and the sample which is not performed were created.

  Thereafter, a buffer layer (AlN buffer layer) having a thickness of about 150 nm was formed on the main surface (exposed surface) of the sapphire substrate under the following conditions.

Growth method: MOCVD pressure: 100 torr
V / III ratio: 5184
TMAl supply amount: 90 ccm
NH ₃ supply amount: 5 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

  The growth temperature was varied in the range of 700 ° C. or more and 1110 ° C. or less for each sample.

  Thereafter, a group III nitride semiconductor layer (GaN layer) having a thickness of about 15 μm was formed on the buffer layer under the following conditions.

Growth method: MOCVD growth temperature: 900-1100 ° C.
Pressure: 100 torr
V / III ratio: 321
TMGa supply amount: 50 to 500 ccm (ramp up)
NH ₃ supply amount: 5 to 10 slm (ramp up)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

  As described above, the group III nitride semiconductor substrate 1 in which the sapphire substrate, the buffer layer, and the group III nitride semiconductor layer were stacked in this order was manufactured.

  Tables 1 to 7 show the relationship between “plural elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer” and the plane orientation of the growth surface of the group III nitride semiconductor layer.

  In the column of “sapphire main surface” in the table, the plane orientation of the main surface of the sapphire substrate is shown. In the column of "Nitriding treatment at elevated temperature", the presence or absence ("Yes" or "None") of nitriding treatment at elevated temperature in the heat treatment step S20 is shown. The column "presence or absence of the trimethyl aluminum pre-flow process" indicates the presence or absence ("presence" or "none") of the trimethyl aluminum pre-flow process. The column of "AlN buffer growth temperature" indicates the growth temperature in the buffer layer formation step. The growth temperature in the GaN layer formation step is indicated in the column "GaN growth temperature". In the column “Growth of III-nitride semiconductor layer”, the plane orientation of the growth surface of the III-nitride semiconductor layer is shown.

  According to the result, the growth surface of the group III nitride semiconductor layer can be made semipolar by adjusting the “plural elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer” described above. Yes, expressed in Miller index (hk ml), it can be seen that l can be adjusted in the plane beyond 0. Then, based on the results of the first evaluation and the results of the second evaluation, “a plurality of elements for making the plane orientation of the growth surface of the group III nitride semiconductor layer a semipolar surface on the N polarity side” Of the growth surface of the group III nitride semiconductor layer by adjusting “plural elements for adjusting the plane orientation of the growth surface of the group III nitride semiconductor layer”, It can be seen that the Miller index (hkml) can be adjusted and l can be adjusted within 0.

<Third evaluation>
The crystallinity of the sample produced by this method was evaluated. Three kinds of samples were prepared. Sample A was produced by the method described in the present specification, and has a {11-23} plane as a growth plane. Samples B and C are comparative samples, and sample B has a {10-10} plane as a growth surface. Moreover, the sample C made the {11-22} plane the growth surface. The {11-23} plane corresponds to a plane having an off angle of 10 ° or less from the {-1-12-4} plane.

  FIG. 9 shows the XRC half value width with respect to the {11-22} plane when X-rays are incident in parallel to the c-axis projection axis of the group III nitride semiconductor crystal at a plurality of GaN film thicknesses for each sample. . However, in Sample C whose main surface is a {11-23} plane, the XRC half width of the {11-22} plane was measured because X-ray diffraction of the {11-23} plane can not be obtained due to the extinction rule.

  From FIG. 9, it can be seen that the XRC half width with respect to the {11-22} plane hardly changes even if the film thickness of the GaN layer in the sample A is increased. On the other hand, in the samples B and C, it can be read that the XRC half width with respect to the {11-22} plane tends to increase as the film thickness of the GaN layer increases.

<Fourth evaluation>
The crystallinity of the sample produced by this method was evaluated. Sample D (Example) was produced by the method described in the present specification, the details of which are as follows.

  First, a sapphire substrate was prepared, which is a plane inclined at 2 ° in the direction parallel to the a-plane from the m-plane ((10-10) plane) from the m-plane ((10-10) plane). The sapphire substrate had a thickness of 430 μm and a diameter of 2 inches.

  And with respect to the prepared sapphire substrate, heat processing process S20 was implemented on condition of the following.

Temperature: 800 to 930 ° C
Pressure: 100 torr
Carrier gas: H ₂ , N ₂
Heat treatment time: 10 minutes Carrier gas supply amount: 4 slm

In the heat treatment step S20, 2 slm of NH ₃ was supplied to perform nitriding treatment.

Thereafter, the pre-flow step S30 was performed under the following conditions.
Temperature: 800 to 930 ° C
Pressure: 100 torr
Trimethylaluminum supply amount, supply time: 50 sccm, 10 seconds Carrier gas: H ₂ , N ₂
Carrier gas supply: 4 slm

  Then, buffer layer formation process S40 was performed on condition of the following, and the AlN layer was formed.

Growth method: MOCVD growth temperature: 800 to 930 ° C.
Pressure: 100 torr
Trimethylaluminum supply amount: 50 sccm
NH ₃ supply amount: 2 slm
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm

  Thereafter, the growth step S50 is performed under the following conditions to form a group III nitride semiconductor layer.

Growth method: MOCVD Growth temperature: 900 ° C ± 25 ° C
Pressure: 100 torr
TMGa supply: 50 to 500 sccm (continuous change)
NH ₃ supply amount: 5 to 10 slm (continuous change)
Carrier gas: H ₂ , N ₂
Carrier gas supply: 15 slm
Growth rate: 10 μm / h or more

  Sample E (comparative example) is produced by the same method as sample D, but differs in the following points.

In the heat treatment step S20, the heat treatment temperature is set to 1000 ° C. to 1050 ° C., and the carrier gas flow rate is set to 15 slm. In addition, the amount of NH ₃ supplied was set to 20 slm.

  In the pre-flow step S30, the trimethyl aluminum supply amount is 90 sccm, and the carrier gas flow rate is 15 slm.

In the buffer layer forming step S40, the supply amount of trimethylaluminum is 90 sccm, and the supply amount of NH ₃ is 5 slm.

  After trial manufacture of the template substrate, X-ray pole figures were measured for sample D and sample E respectively. As a result of the measurement, it was confirmed that both the main surface of Sample D and the main surface of Sample E were surfaces having an off angle within 10 ° from the {-1-12-4} surface.

  And about each of the sample D and the sample E, the half value width of XRC with respect to a {11-22} plane was measured. Specifically, it was measured by the following procedure (see FIG. 12).

(1) X-rays are irradiated to the central part of the template substrate (sample D and sample E respectively) produced as a prototype, and (000-2) plane diffraction XRC is measured. Specifically, the template substrate is set in an X-ray diffractometer, and the detector and the template substrate are set at theoretical angles at which diffraction of the (000-2) plane can be obtained with respect to incident X-rays. Then, the template substrate is vertically inclined at an angle of 40 ° to 50 °. Furthermore, the template substrate is rotated in the in-plane direction to search for a rotation angle at which a (000-2) plane diffraction peak can be obtained. Finally, measurement is performed by adjusting various angles other than the in-plane rotational direction of the substrate so that the (000-2) plane diffraction peak can be obtained best. When the template substrate produced by the method described in this specification is measured according to the above procedure, a (000-2) plane diffraction peak can be obtained only when X-rays are incident parallel to the m-axis. That is, this measurement also serves as axis alignment in the m-axis direction.
(2) Measure the m-axis incidence XRC. Specifically, in the portion (center portion of the template substrate) where the (000-2) plane XRC is measured (center portion of the template substrate), the rotation in the plane other than the in-plane direction of the substrate is performed so as to obtain the best diffraction. Adjust various angles). Thereafter, the measurement of the {11-22} plane XRC is performed at a total of three points of the central portion and two points separated by 20 mm in the m-axis direction from the central portion.
(3) c Measure the projection axis incidence XRC. Specifically, after the measurement described in (2), the template substrate is rotated by 90 ° in the in-plane direction. As a result, the X-ray enters the c projection axis (the projection axis obtained by projecting the c axis onto the main surface). Then, the {11-22} plane is centered at the center, and the {11-22} plane XRC is measured at a total of three points at the center and two points 20 mm away from the center in the c projection axis direction. I do.

  The measurement result of sample D is shown in FIG. 11, and the measurement result of sample E is shown in FIG. The value corresponding to (m) is the half-width of XRC with respect to the {11-22} plane measured with X rays incident parallel to the m axis of the group III nitride semiconductor crystal, corresponding to “m axis incidence” The value to be taken is the average value of 3 measurement points. The value corresponding to (c) is the half-width of XRC with respect to the {11-22} plane measured parallel to the projection axis obtained by projecting the X axis of the c-axis of the group III nitride semiconductor crystal onto the main surface The value corresponding to “c-axis projection axis incidence” is an average value of three measurement points. The outline of the measurement point is as illustrated.

  From FIG. 11, in the group III nitride semiconductor substrate manufactured by the manufacturing method of this embodiment, X-rays are incident on the main surface of the group III nitride semiconductor layer in parallel to the m axis of the group III nitride semiconductor crystal. It can be seen that the half-width of XRC with respect to the {11-22} plane measured by scanning the angle between the incident direction of the X-ray and the main surface is 500 arcsec or less. Further, X ray is incident parallel to the projection axis of the c-axis of the group III nitride semiconductor crystal projected onto the above main surface with respect to the main surface of the group III nitride semiconductor layer, and the incident direction of the x ray and the above main surface It can be seen that the half-width of XRC with respect to the {11-22} plane measured by scanning the angle is also 500 arcsec or less.

  Furthermore, “X-rays were incident parallel to the m-axis of the group III nitride semiconductor crystal to the main surface of the group III nitride semiconductor layer, and the angle between the X-ray incident direction and the main surface was scanned and measured {11 The measured value at three points separated by 20 mm in the m-axis direction, and “X-ray with respect to the main surface of the group III nitride semiconductor layer”; The half width of XRC with respect to the {11-22} plane, which is measured parallel to the projection axis obtained by projecting the c axis of the semiconductor crystal on the main plane, and the angle between the X ray incident direction and the main plane is scanned, The difference between the maximum value and the minimum value in “measurement values at three points separated by 20 mm in the projection axis direction with the c axis projected onto the main surface” is 50 arcsec. It turns out that it is within. That is, it can be seen that the anisotropy between the two is small.

  On the other hand, according to FIG. 10, the group III nitride semiconductor substrate not manufactured by the manufacturing method of the present embodiment is parallel to the m-axis of the group III nitride semiconductor crystal with respect to the main surface of the group III nitride semiconductor layer. It can be seen that the half-width of XRC with respect to the {11-22} plane measured by scanning the angle between the incident direction of the X-ray and the above-mentioned main surface exceeds 500 arcsec. Further, X ray is incident parallel to the projection axis of the c-axis of the group III nitride semiconductor crystal projected onto the above main surface with respect to the main surface of the group III nitride semiconductor layer, and the incident direction of the x ray and the above main surface It can be seen that the half-width of XRC relative to the {11-22} plane measured by scanning the angle also exceeds 500 arcsec.

  When a nitride semiconductor is crystal-grown on an m-plane sapphire substrate, it is known that the growth surface, the crystallinity, and the orientation of the crystal axis of the nitride semiconductor differ depending on the presence or absence of the nitriding, the nitriding temperature, and the film forming temperature. ing. Since the film formation temperature of the buffer layer is the same as in the embodiment and the comparative example, it is considered that the temperature of the heat treatment step S20 has the largest influence among the manufacturing conditions.

  From the results of the example, it can be understood that adjusting the temperature of the heat treatment step S20 to 800 ° C. or more and 930 ° C. or less makes the half width of XRC with respect to the {11-22} plane to be good. It can be seen that the temperature of the heat treatment step has a great influence on the crystallinity of the buffer layer and the Group III nitride semiconductor crystal and the orientation of crystal axes.

Hereinafter, an example of a reference form is added.
1. With sapphire substrate,
A group III nitride semiconductor layer located on the sapphire substrate, the main surface being a semipolar surface, represented by a Miller index (hk ml), and a surface where l is less than 0;
Have
X-rays were incident parallel to the m-axis of the group III nitride semiconductor crystal to the main surface of the group III nitride semiconductor layer, and the angle between the incident direction of the X-rays and the main surface was scanned and measured {11 III-nitride semiconductor substrate wherein the half-width of XRC (X-ray Rocking Curve) with respect to the (22) plane is 500 arcsec or less.
2. In the group III nitride semiconductor substrate described in 1,
An X-ray is incident parallel to a projection axis obtained by projecting the c-axis of the group III nitride semiconductor crystal onto the main surface with respect to the main surface of the group III nitride semiconductor layer, and the incident direction of the X-ray and the main surface The group III nitride semiconductor substrate whose half-width of XRC with respect to the {11-22} plane measured by scanning the angle is 500 arcsec or less.
3. In the group III nitride semiconductor substrate described in 1 or 2,
X-rays were incident parallel to the m-axis of the group III nitride semiconductor crystal to the main surface of the group III nitride semiconductor layer, and the angle between the incident direction of the X-rays and the main surface was scanned and measured {11 The half value width of XRC with respect to the (22) plane, and measurement values at three points separated by 20 mm in the m-axis direction, and
An x-ray is incident parallel to a projection axis of the c-axis of the group III nitride semiconductor crystal projected onto the main surface with respect to the main surface of the group III nitride semiconductor layer, and an angle formed by the incident direction of the x-ray and the main surface The half width of the XRC with respect to the {11-22} plane measured by scanning the measured values at three points separated by 20 mm in the projection axis direction in which the c axis is projected onto the main surface,
The difference between the maximum value and the minimum value at 50 arcsec. III-nitride semiconductor substrate which is within
4. In the group-III nitride semiconductor substrate according to any one of 1 to 3,
The group III nitride semiconductor substrate, wherein the thickness of the group III nitride semiconductor layer is 1 μm or more and 20 μm or less.
5. Production of a group III nitride semiconductor substrate in which a group III nitride semiconductor is grown on the group III nitride semiconductor substrate according to any one of 1 to 4 by HVPE (Hydride Vapor Phase Epitaxy) to form an HVPE layer Method.
6. In the method of manufacturing a group III nitride semiconductor substrate according to 5,
The manufacturing method of the group III nitride semiconductor substrate which cuts out the group III nitride semiconductor substrate from the said HVPE layer.

10 group III nitride semiconductor substrate 11 first main surface 12 second main surface 20 group III nitride semiconductor substrate 21 sapphire substrate 22 buffer layer 23 group III nitride semiconductor layer 24 growth surface

Claims (6)

With sapphire substrate,
A group III nitride semiconductor layer located on the sapphire substrate, the main surface being a semipolar surface, represented by a Miller index (hk ml), and a surface where l is less than 0;
Have
X-rays were incident parallel to the m-axis of the group III nitride semiconductor crystal to the main surface of the group III nitride semiconductor layer, and the angle between the incident direction of the X-rays and the main surface was scanned and measured {11 III-nitride semiconductor substrate wherein the half-width of XRC (X-ray Rocking Curve) with respect to the (22) plane is 500 arcsec or less. In the group III nitride semiconductor substrate according to claim 1,
An X-ray is incident parallel to a projection axis obtained by projecting the c-axis of the group III nitride semiconductor crystal onto the main surface with respect to the main surface of the group III nitride semiconductor layer, and the incident direction of the X-ray and the main surface The group III nitride semiconductor substrate whose half-width of XRC with respect to the {11-22} plane measured by scanning the angle is 500 arcsec or less. The group III nitride semiconductor substrate according to claim 1 or 2
X-rays were incident parallel to the m-axis of the group III nitride semiconductor crystal to the main surface of the group III nitride semiconductor layer, and the angle between the incident direction of the X-rays and the main surface was scanned and measured {11 The half value width of XRC with respect to the (22) plane, and measurement values at three points separated by 20 mm in the m-axis direction, and
An x-ray is incident parallel to a projection axis of the c-axis of the group III nitride semiconductor crystal projected onto the main surface with respect to the main surface of the group III nitride semiconductor layer, and an angle formed by the incident direction of the x-ray and the main surface The half width of the XRC with respect to the {11-22} plane measured by scanning the measured values at three points separated by 20 mm in the projection axis direction in which the c axis is projected onto the main surface,
The difference between the maximum value and the minimum value at 50 arcsec. III-nitride semiconductor substrate which is within The group III nitride semiconductor substrate according to any one of claims 1 to 3,
The group III nitride semiconductor substrate, wherein the thickness of the group III nitride semiconductor layer is 1 μm or more and 20 μm or less.   A group III nitride, wherein a group III nitride semiconductor is grown on the group III nitride semiconductor substrate according to any one of claims 1 to 4 by HVPE (Hydride Vapor Phase Epitaxy) to form an HVPE layer. Method of manufacturing a semiconductor substrate In the method of manufacturing a group III nitride semiconductor substrate according to claim 5,
The manufacturing method of the group III nitride semiconductor substrate which cuts out the group III nitride semiconductor substrate from the said HVPE layer.