JP2019075474A - Semiconductor device manufacturing method - Google Patents

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises a step of mounting on a die pad DP of a common lead frame, a semiconductor chip CP or a second semiconductor chip different from the semiconductor chip CP. To each of a plurality of leads LD, a tape TP1 and a tape TP2 are fixed. Each of the plurality of leads LD has a tip part where a metal film BM is formed. The tip part includes a first portion LDP1 located closer to the die pad DP than the tape TP1, a portion LDP2 which is located further from the die pad DP than the portion LDP1 and overlaps the tape TP1 and a portion LDP3 which is located farther from the die pad DP than the portion LDP2 and located between the tap TP1 and the tape TP2. When the semiconductor chip CP is mounted, a wire BW is connected to the metal film BM on the portion LDP1. When the second semiconductor chip is mounted, the wire BW is connected to the metal film BM2 on the portion LDP3.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a manufacturing technology of a semiconductor device, for example, to a technology effectively applied to a semiconductor device in which a semiconductor chip and a plurality of leads are connected via a plurality of wires.

  In JP-A-8-204111 (Patent Document 1) and JP-A-2006-13391 (Patent Document 2), a tape material is attached around the tip of a plurality of leads connected to a semiconductor chip. Structure is described.

JP-A-8-204111 Unexamined-Japanese-Patent No. 2006-13391

  There is a semiconductor device in which a semiconductor chip mounted on a die pad of a lead frame and a plurality of leads are electrically connected via bonding wires. If a common lead frame can be used for a plurality of types of semiconductor devices, the versatility of the lead frame is increased, and the manufacturing efficiency of the semiconductor device is improved.

  However, when using a common lead frame for multiple types of semiconductor chips with different external appearances, such as the external size of the semiconductor chip and the arrangement of the electrode pads, the positional relationship between the electrode pads and the leads is different Problems, which may arise in terms of the reliability of the semiconductor device. For example, when a large number of leads are arranged at a narrow pitch, a bonding wire connected to one lead may contact another lead and cause a short circuit depending on the positional relationship between the pad and the leads. .

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  A method of manufacturing a semiconductor device according to an embodiment includes the step of mounting a first semiconductor chip or a second semiconductor chip different in appearance from each other on a die pad of a common lead frame. A first lead fixing tape and a second lead fixing tape are fixed to each of the plurality of leads provided in the lead frame. Also, the plurality of leads are provided with a tip on which a plating film is formed. The tip portion is, in a plan view, a first portion located closer to the die pad than the first lead fixing tape, and a tip portion located farther from the die pad than the first portion, and the first lead fixed A second portion overlapping the tape, and a third portion located farther from the die pad than the second portion, and located between the first lead fixing tape and the second lead fixing tape . When the semiconductor chip mounted on the die pad is a first semiconductor chip, a wire is connected to the plating film on the first portion. When the semiconductor chip mounted on the die pad is a second semiconductor chip, a wire is connected to the plating film on the third portion.

  According to the above embodiment, the reliability of the semiconductor device can be improved.

FIG. 1 is a top view of a semiconductor device according to an embodiment; It is sectional drawing along the AA of FIG. It is a see-through | perspective top view which shows the internal structure of a semiconductor device in the state which saw through the sealing body shown in FIG. FIG. 4 is a perspective plan view showing a plurality of wires shown in FIG. 3 removed. It is an enlarged plan view which expands and shows the periphery of the wire shown in FIG. It is the enlarged plan view which further expanded the periphery of the lead shown in FIG. It is an enlarged plan view which shows the study example with respect to FIG. It is an enlarged plan view which shows the modification with respect to FIG. It is explanatory drawing which shows the flow of the assembly process of the semiconductor device demonstrated using FIGS. 1-8. It is an enlarged plan view which shows the lead frame prepared at the base-material preparatory process shown in FIG. It is an enlarged plan view which expands and shows the front-end | tip part periphery of the lead shown in FIG. FIG. 6 is an enlarged plan view showing a state in which a part of a lead is removed in a lead tip cutting step included in the manufacturing process of the semiconductor device shown in FIG. 5; FIG. 9 is an enlarged plan view showing a state in which a portion of a lead is removed in a lead tip cutting step included in the manufacturing process of the semiconductor device shown in FIG. 8; It is an enlarged plan view which shows the state which mounted the semiconductor chip on the die pad of the lead frame shown in FIG. FIG. 14 is an enlarged plan view showing a state in which the semiconductor chip is mounted on the die pad of the lead frame shown in FIG. 13; FIG. 15 is an enlarged plan view showing a state in which the semiconductor chip shown in FIG. 14 and a plurality of leads are electrically connected via a wire; FIG. 16 is an enlarged plan view showing a state in which the semiconductor chip shown in FIG. 15 and a plurality of leads are electrically connected via a wire; FIG. 17 is an enlarged cross-sectional view showing a state in which the pad and the lead of the semiconductor chip shown in FIG. 16 are electrically connected via a wire; FIG. 18 is an enlarged cross-sectional view showing a state in which the pad and the lead of the semiconductor chip shown in FIG. 17 are electrically connected via a wire; It is an enlarged plan view which shows the state in which the sealing body which seals a semiconductor chip in the sealing process shown in FIG. 9 was formed. FIG. 21 is an enlarged plan view showing a state in which a metal film is formed on exposed surfaces of the plurality of leads shown in FIG. FIG. 22 is an enlarged plan view showing a state in which the semiconductor package is obtained by cutting the suspension lead shown in FIG. 21. It is a top view which shows the modification of the semiconductor chip shown in FIG. FIG. 6 is an enlarged plan view showing a positional relationship between die pads of a semiconductor device which is a modification example of FIG. 3 and a semiconductor chip; FIG. 12 is an enlarged cross-sectional view of the tip of a lead according to a modification of FIG. FIG. 12 is an enlarged cross-sectional view of a tip portion of a lead which is another modification example of FIG. 11;

(Description of description form, basic terms and usage in this application)
In the present application, the description of the embodiment will be described by dividing it into a plurality of sections etc. as needed for convenience, but unless explicitly stated otherwise, these are not mutually independent and different from each other, and described Before and after, each part of a single example, one being a partial detail or part or all of a modification of the other. Also, in principle, similar parts will not be described repeatedly. In addition, each component in the embodiment is not essential unless clearly indicated otherwise, unless it is theoretically limited to the number and clearly from the context.

  Similarly, in the description of the embodiment and the like, regarding the material, the composition, etc., even if "X consisting of A" etc. is mentioned, elements other than A unless clearly stated otherwise and clearly from the context, elements other than A It does not exclude things including. For example, the component means "X containing A as a major component". For example, the term "silicon member" is not limited to pure silicon, but is a member containing SiGe (silicon-germanium) alloy, multi-element alloy containing other silicon as a main component, other additives, etc. Needless to say, it also includes In addition, even if gold plating, Cu layer, nickel plating, etc. are not specifically stated otherwise, not only pure ones but also members containing gold, Cu, nickel etc. as main components are included. It shall be

  Furthermore, even when a specific numerical value or quantity is referred to, in the case where it is clearly stated that it is not specifically stated, a numerical value exceeding that specific numerical value is excluded unless it is theoretically limited to that number and clearly not from the context. It may be present or may be less than the specific value.

  Further, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and the description will not be repeated in principle.

  Further, in the attached drawings, hatching may be omitted even in the case of a cross section in the case where it becomes rather complicated or when the distinction from the void is clear. In relation to this, when it is clear from the description etc., the outline of the background may be omitted even if it is a hole closed in a plane. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added to clearly show that it is not a void or to clearly show the boundary of the area.

<Overview of Semiconductor Device>
First, the outline of the configuration of the semiconductor device PKG1 according to the present embodiment will be described with reference to FIGS. FIG. 1 is a top view of the semiconductor device of the present embodiment. 2 is a cross-sectional view taken along the line AA of FIG. FIG. 3 is a transparent plan view showing the internal structure of the semiconductor device in a state where the sealing body shown in FIG. 1 is seen through. FIG. 4 is a perspective plan view showing a plurality of wires shown in FIG. 3 removed.

  As shown in FIGS. 1 to 4, the semiconductor device PKG1 includes a semiconductor chip CP (see FIGS. 2 and 3), a plurality of leads LD electrically connected to the semiconductor chip CP, and a plurality of semiconductor chips CP. And a plurality of wires BW (see FIG. 2) which are conductive members for electrically connecting the leads LD. The semiconductor chip CP and the plurality of wires BW are sealed in a sealing body (resin body) MR. The inner lead portion ILD (see FIG. 2) of each of the plurality of leads LD is sealed in the sealing body MR, and the outer lead portion OLD of each of the plurality of leads LD is exposed from the sealing body MR .

  As shown in FIG. 1, the planar shape of the sealing body MR provided in the semiconductor device PKG1 is a square. The sealing body MR has an upper surface MRt, a lower surface (back surface, mounting surface) MRb located on the opposite side of the upper surface MRt (see FIG. 2), and a side surface MRs located between the upper surface MRt and the lower surface MRb (FIG. 1, FIG. 2) See).

  Further, as shown in FIG. 1 and FIG. 3, the sealing body MR intersects the side (main side) S1 extending (extends) along the X direction and the X direction in plan view (in FIG. 1) It has a side (principal side) S2 extending along the orthogonal Y direction. In addition, the sealing body MR is located on the opposite side of the side S1, has a side S3 extending along the X direction, and is located on the opposite side of the side S2, and has a side S4 extending along the Y direction. doing. As shown in FIG. 1, four side surfaces MRs of the sealing body MR are disposed along each side of the sealing body MR. Further, in the example shown in FIG. 1, the corner portion MRc where the sides of the sealing body MR intersect has a chamfered shape.

  Here, the corner portion MRc of the sealing body MR means a peripheral region of an angle which is an intersection point of any two intersecting sides (two main sides) of the four sides (four main sides) of the sealing body MR. It contains. Strictly speaking, as shown in FIG. 1 and FIG. 3, the corner portion MRc of the sealing body MR is in a chamfered shape (in the example shown in FIG. Since the intersection of the main sides is disposed outside the corner MRc of the sealing body MR. However, since the chamfered portion is sufficiently smaller than the length of the main side, in the present application, the center of the chamfered portion will be described as the corner of the sealing body MR. That is, in the present application, when the arbitrary two sides (two main sides) of the four sides (four main sides) of the sealing body MR intersect with each other and the area is chamfered, When the chamfered portion corresponds to the corner portion MRc and the area is not chamfered, the intersection of any two sides (two main sides) corresponds to the corner portion MRc. Hereinafter, in the present application, when describing as the corner portion MRc of the sealing body MR, it is used as the same meaning and content as above, except in the case where it is specified that the meaning is different.

  Further, in the semiconductor device PKG1, a plurality of leads LD are disposed along each side (each main side) of the sealing body MR whose planar shape is a quadrangle. Each of the plurality of leads LD is made of a metal material, and in the present embodiment, it is a metal member whose main component is copper (Cu), for example.

  As shown in FIG. 2, the outer lead portions OLD of the plurality of leads LD protrude toward the outside of the sealing body MR on the side surface MRs of the sealing body MR. Further, on the exposed surface of the outer lead portion OLD of the plurality of leads LD, for example, a metal film (exterior plating film) MC is formed on the surface of a base material containing copper as a main component. The metal film MC is, for example, a metal film made of a metal material such as solder having better wettability to solder than copper as a base material, and covering the surface of the copper member as a base material. When the semiconductor device PKG1 is mounted on a mounting substrate by forming the metal film MC made of solder or the like on each of the outer lead portions OLD of the plurality of leads LD which are external terminals of the semiconductor device PKG1, conductive connection is made. The wettability of the solder material which is the material can be improved. As a result, the bonding area between the plurality of leads LD and the solder material is increased, so that the bonding strength between the plurality of leads LD and the terminal on the mounting substrate can be improved.

  The metal film MC is, for example, an Sn—Pb solder material containing lead (Pb), or a solder material made of so-called lead-free solder which does not substantially contain Pb. Examples of lead-free solder include, for example, only tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. . Here, lead-free solder means that the content of lead (Pb) is 0.1 wt% or less, and this content is defined as the standard of the Restriction of Hazardous Substances (RoHS) directive.

  Although the example shown in FIG. 2 shows an example in which the metal film MC which is a solder film is formed on the exposed surface of the outer lead portion OLD of the lead LD by a plating method, the metal film MC has various modifications. . For example, the metal film MC may be a laminated film of a metal film containing nickel (Ni) as a main component and a metal film containing palladium (Pd) as a main component. Alternatively, for example, a metal film containing gold (Au) as the main component may be further stacked on the surface of a metal film containing palladium as the main component. When the metal film MC is formed of a material other than solder, the metal film MC may be formed to cover the surfaces of the inner lead portions ILD of the plurality of leads LD and the outer lead portion OLD.

  Further, as shown in FIG. 2 and FIG. 3, the semiconductor chip CP is sealed inside the sealing body MR. As shown in FIG. 3, the semiconductor chip CP forms a quadrangle in plan view, and the surface CPt has a plurality of pads (bonding pads) PD along the four sides constituting the outer edge of the surface CPt (figure) 2) is provided. The semiconductor chip CP (specifically, the semiconductor substrate) is made of, for example, silicon (Si). Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (specifically, the semiconductor element formation region provided on the upper surface of the semiconductor substrate of the semiconductor chip CP). Then, the plurality of pads PD are provided via interconnections (not shown) formed in the interconnection layer disposed inside the semiconductor chip CP (specifically, between the surface CPt and the semiconductor element formation region not shown). It is electrically connected to the semiconductor element. That is, the plurality of pads PD are electrically connected to the circuit formed in the semiconductor chip CP.

  In addition, an insulating film is formed on the surface CPt of the semiconductor chip CP to cover the substrate and the wiring of the semiconductor chip CP, and the surfaces of the plurality of pads PD are insulated in the openings formed in the insulating film. Exposed from the membrane. Further, the pad PD is made of metal, and in the present embodiment, it is made of, for example, aluminum (Al).

  Further, a plurality of leads LD are disposed around the semiconductor chip CP (in other words, around the die pad DP (see FIG. 2)). Then, each of the plurality of pads (bonding pads) PD exposed on the surface CPt of the semiconductor chip CP is via the inner lead portion ILD of the lead LD located inside the sealing body MR and the wire (conductive member) BW. Are connected electrically. The wire BW is made of, for example, gold (Au) or copper (Cu), and a part (for example, one end) of the wire BW is bonded to the pad PD, and the other part (for example, the other end) is an inner lead part It is joined to the wire bonding area (area to which a part of the wire BW is connected) at the tip of the ILD.

  In the present embodiment, a metal film (plated film, plated metal film) BM (see FIG. 2) is formed in the wire bonding region at the tip of the inner lead portion ILD. As shown in FIG. 2, the metal film BM is partially formed on a portion of the inner lead portion ILD (the upper surface (surface) LDt of the tip closest to the die pad DP). The metal film BM is made of, for example, a material containing silver (Ag), gold, or palladium as a main component (for example, a laminated structure in which a thin gold film is formed on a palladium film). In the inner lead portion ILD, the metal film BM made of a material mainly composed of silver, gold or palladium is formed in the portion to which the wire BW is connected, so that the bonding strength with the wire BW made of gold is achieved. Can be improved. Details of the region in which the metal film BM is formed will be described later.

  Further, as shown in FIG. 2, the semiconductor chip CP is mounted on a die pad DP which is a chip mounting portion. In the example shown in FIG. 4, the upper surface (chip mounting surface) DPt of the die pad DP forms a hexagon having an area larger than the area of the surface CPt of the semiconductor chip CP. The die pad DP is a support member for supporting the semiconductor chip CP, and the shape and size thereof are variously modified in addition to the example shown in FIG. For example, the planar shape of the die pad DP may be square or circular.

  Further, as shown in FIG. 4, a plurality of suspension leads HL are disposed around the die pad DP. The suspension lead HL is a member for supporting the die pad DP on the support portion (frame portion) of the lead frame in the manufacturing process of the semiconductor device PKG1, and one end of the suspension lead HL is connected to the die pad DP . In the example shown in FIG. 4, four suspension leads HL1, HL2, HL3, and HL4 extending from a part of the die pad DP toward each of the four corner portions MRc of the sealing body MR are connected to the die pad DP. There is. A plurality of leads LD1 are provided between the suspension lead HL1 and the suspension lead HL2, a plurality of LD2 are provided between the suspension lead HL2 and the suspension lead HL4, and a plurality of leads are provided between the suspension lead HL4 and the suspension lead HL3. A plurality of leads LD4 are respectively disposed between the suspension lead HL3 and the suspension lead HL1.

  In detail, one end of the plurality of suspension leads HL is connected to a corner (corner) of the die pad DP. Further, the other ends of the plurality of suspension leads HL extend toward the corner MRc of the sealing body MR, and bifurcate in the vicinity of the corner MRc, and the sealing body at the side surface MRs of the sealing body MR Exposed from MR. By extending the hanging leads HL toward the corner portion MRc of the sealing body MR, the arrangement of the plurality of leads LD arranged along each side (each main side) of the sealing body MR is inhibited by the hanging leads HL It becomes difficult to do.

  Further, in the present embodiment, as shown in FIG. 2, the upper surface DPt of the die pad DP and the upper surface of the inner lead portion ILD of the lead LD are disposed at different heights. In the example shown in FIG. 2, the upper surface DPt of the die pad DP is disposed at a lower position than the position of the upper surface LDt of the inner lead portion ILD. Therefore, the plurality of suspension leads HL shown in FIG. 4 are bent such that the height of the upper surface DPt of the die pad DP is located at a height different from the height LDt of the inner lead portion ILD of the lead LD (see FIG. 2). The offset portion (bent portion, in the example of the present embodiment, the downset portion) HLB is provided.

  The semiconductor chip CP is mounted at the center of the die pad DP. As shown in FIG. 2, the semiconductor chip CP is mounted on the die pad DP via the die bonding material (adhesive material) DB in a state where the back surface CPb faces the upper surface DPt of the die pad DP. That is, it is mounted by a so-called face-up mounting method in which the opposite surface (back surface CPb) of the surface (main surface) CPt on which the plurality of pads PD are formed is opposed to the chip mounting surface (upper surface DPt). The die bonding material DB is an adhesive material for die bonding of the semiconductor chip CP, and for example, a resin adhesive in which metal particles of silver or the like are contained in an epoxy-based thermosetting resin, a solder material, or the like. Metal bonding material is used.

<Lead structure>
Next, the layout of a plurality of leads of this embodiment will be described in detail. FIG. 5 is an enlarged plan view showing the periphery of the wire shown in FIG. 3 in an enlarged manner. 6 is an enlarged plan view further enlarging the periphery of the lead shown in FIG. FIG. 7 is an enlarged plan view showing a study example with respect to FIG. FIG. 8 is an enlarged plan view showing a modification of FIG.

  As shown in FIG. 4, the semiconductor device PKG1 has a lead group LDg1 composed of a plurality of leads LD1 arranged along the side S1 of the sealing body MR. The semiconductor device PKG1 also has a lead group LDg2 composed of a plurality of leads LD2 arranged along the side S2 of the sealing body MR. The semiconductor device PKG1 further includes a lead group LDg3 including a plurality of leads LD3 disposed along the side S3 of the sealing body MR. The semiconductor device PKG1 further includes a lead group LDg4 including a plurality of leads LD4 disposed along the side S4 of the sealing body MR.

  Also, it is connected to the die pad DP between the lead group LDg1 and the lead group LDg2, between the lead group LDg1 and the lead group LDg4, between the lead group LDg2 and the lead group LDg3, and between the lead group LDg3 and the lead group LDg4. Hanging leads HL (which support the die pad DP) are respectively arranged.

  The plurality of leads LD and the plurality of pads PD (see FIG. 2) of the semiconductor chip CP are electrically connected via the wire BW as shown in FIG. By shortening the length of the plurality of wires BW, the electrical characteristics of the transmission path including the wires BW can be improved. Alternatively, by shortening the length of the wire BW, deformation of the wire BW can be suppressed in the step of forming the sealing body MR.

  In order to shorten the length of each of the plurality of wires BW, the tip of the lead LD is disposed in the vicinity of the pad PD of the semiconductor chip CP, and the distance between the tip of the lead LD and the pad PD of the semiconductor chip CP. It is preferable to reduce Further, as in the present embodiment, in the case of the semiconductor device having a large number of terminals, the tips of the plurality of leads LD (tips of the inner lead portion ILD) are arranged in a narrow region at a narrow pitch. On the other hand, since the arrangement pitch of the outer lead portion OLD shown in FIG. 3 is subject to the restriction of the terminal on the side of the mounting substrate (not shown) on which the semiconductor device PKG1 is mounted, it is difficult to extremely narrow the pitch. The extension distance of the inner lead portion ILD that each of the plurality of leads LD has is long.

  Further, as shown in FIG. 3, when the extension distance of the inner lead portion ILD of the lead LD is long, a part of the lead LD is easily deformed in the manufacturing process of the semiconductor device. The deformation of the lead LD described above includes, in addition to irreversible plastic deformation, for example, reversible (elastic deformation) due to the weight of the lead itself. In particular, the tip of the lead LD provided with the wire bonding area is more easily deformed (mainly elastically deformed) as the distance of the inner lead portion ILD becomes longer. Then, in the wire bonding process, when the tip of the lead LD is elastically deformed, it becomes difficult to bond the wire BW.

  For this reason, in the present embodiment, as shown in FIG. 3, a plurality of tape materials (tapes TP1 and TP2 shown in FIG. 3) are attached (fixed) so as to straddle each of the plurality of leads LD. The deformation of the lead LD is suppressed.

  The tape (lead fixing tape) TP1 and the tape (lead fixing tape) TP2 are fixing members that connect and fix a plurality of leads LD, and for example, one surface (adhesive surface) of a base material such as a resin film An adhesive layer (adhesive layer) is formed on the When the adhesive layers of the tapes TP1 and TP2 are brought into contact with one surface of the leads LD (for example, the upper surface LDt in the example shown in FIG. 2), the tapes TP1 and TP2 are attached to the leads LD.

  Further, only by mutually connecting each of the plurality of leads LD, there is a possibility that the whole of the plurality of connected leads LD may be deformed by its own weight. Therefore, as shown in FIG. 4, it is preferable that a part of each of the tapes TP1 and TP2 is attached to the suspension lead HL. In the wire bonding step in the manufacturing process of the semiconductor device PKG1 described later, one end of the suspension lead HL is connected to the die pad DP, and the other end is connected to the frame of the lead frame. Therefore, if a part of each of tape TP1 and tape TP2 is stuck on suspension lead HL, a plurality of leads LD will be supported by suspension lead HL. As a result, deformation of the plurality of leads LD can be suppressed.

  However, in order to suppress the deformation of the lead LD in the bonding area shown in FIG. 2, it is sufficient if there is at least the tape TP1. In other words, even when the tape TP2 is not present, the deformation of the lead LD in the bonding area shown in FIG. 2 can be suppressed. However, in the semiconductor device PKG1 of the present embodiment, the tape TP1 and the tape TP2 are attached to each of the plurality of leads LD. As a result, even when a semiconductor chip having an outer size, a pad arrangement, or the like that differs in appearance in plan view from the semiconductor chip CP is mounted on the die pad DP, it is possible to use a lead frame common to the semiconductor device PKG1.

  “Semiconductor chips having different appearances in plan view” refer to semiconductor chips having structural differences visible in plan view, such as outer size and arrangement of pads, due to differences in product types of semiconductor chips. Means Therefore, for example, semiconductor chips having different circuits but having the same external size and arrangement of pads are not included in the “semiconductor chips having different appearances in plan view”. In addition, semiconductor chips having different thicknesses but having the same external size in plan view are not included in “semiconductor chips having different appearances in plan view”.

  As shown in FIG. 5, the tip of each of the leads LD has a partial LDP1 located closer to the die pad DP than the tape TP1 in plan view. In addition, the tip has a portion LDP2 located farther from the die pad DP than the portion LDP1 and overlapping the tape TP1. In addition, the tip has a partial LDP3 located farther from the die pad DP than the partial LDP2 and located between the tape TP1 and the tape TP2. Plating films are formed on the portions LDP1 and LDP3 of the leads LD.

  In the case of the semiconductor device PKG1, the metal film BM is formed on the partial LDP1 of the lead LD, and the metal film (plating film, plated metal film) BM2 is formed on the partial LDP3. The metal film BM2 is made of the same material as the metal film BM. The metal film BM2 is formed on the upper surface (surface) LDt of the partial LDP 3. The wire BW is connected to the metal film BM on the partial LDP1, and is not connected to the metal film BM2 on the partial LDP3. Further, the metal film BM and the metal film BM2 are separated from each other, and the metal films BM and BM2 are not formed on the portion LDP2 of the lead LD.

  As shown in FIG. 6, the portion LDP1 of the lead LD has a tip side LDts facing the die pad DP. The front end side LDts is a side which intersects the extending direction of the front end portion of the lead LD, and is a side of the outer edge of the lead LD which is disposed closest to the die pad DP. From the viewpoint of suppressing contact between the wire BW connected to a certain lead LD and the lead LD positioned next to the lead LD, the wire BW intersects with the tip side LDts in plan view Is preferred. In other words, in plan view, the wire BW connected to a certain lead LD preferably overlaps the tip side LDts of the lead LD.

  Hereinafter, a state in which the wire BW connected to a certain lead LD does not overlap with the tip side LDts of the lead LD is referred to as a “tip end state”. When the wire BW is connected to the lead LD in a state where it is out of the tip, the possibility that the wire BW contacts the adjacent lead LD is increased. For example, in the sealing step described later, when the wire BW is sealed, if the wire BW is deformed by the supply pressure of the sealing resin, the possibility that a part of the wire BW is deformed to the adjacent lead LD is increased. . On the other hand, as shown in FIG. 6, in the case where the wire BW is not in the tip-off state, even if the wire BW is deformed in the sealing step, the possibility of the wire BW contacting the adjacent lead LD is small. That is, as shown in FIG. 5, when each of the plurality of wires BW intersects the tip side LDts (see FIG. 6) of the lead LD to be connected, the electrical reliability of the semiconductor device PKG1 is improved. It can be done. Ideally, it is preferable that all the wires BW of the semiconductor device PKG1 intersect the tip side LDts (see FIG. 6) of the lead LD to be connected. However, it does not exclude that a part of many wires BW are in the tip-off state.

  As in the semiconductor device PKG1 shown in FIG. 5, to arrange each of the plurality of wires BW so as to intersect the tip side LDts (see FIG. 6) of the lead LD to be connected, it is connected to the wires BW The positional relationship between the portion LDP1 of the lead LD and the pad PD is important. In plan view, the wire BW linearly extends so as to connect the pad PD and the wire bonding region of the lead LD. Therefore, the planar positional relationship between the wire bonding area of the lead LD and the pad PD determines whether or not the tip end is out. For example, as in a semiconductor device PKG2 shown in FIG. 7, when a semiconductor chip CP2 having a different layout of the pad PD from the semiconductor chip CP shown in FIG. 1 is mounted on the die pad DP, a part of the plurality of wires BW The wire BW may be in the state of being detached from the wire BW.

  If the layout of the leads LD is determined according to the layout of the pads PD of the semiconductor chip CP, the positional relationship between the plurality of pads PD of the semiconductor chip CP and the wire bonding area of the leads LD can be optimized. However, in this case, it is necessary to prepare different types of lead frames for each type of semiconductor chip CP. That is, the versatility of the lead frame is reduced.

  Therefore, the inventor of the present application examined a technique for improving the versatility of the lead frame and improving the reliability of the semiconductor device. In the present embodiment, each of the plurality of leads LD has the partial LDP1 and the partial LDP3, and the metal film BM or BM2 is formed on the partial LDP1 and the partial LDP3, respectively. Therefore, as in the semiconductor device PKG3 shown in FIG. 8, when the partial LDP1 and the partial LDP2 shown in FIG. 5 are removed, the metal film BM2 on the partial LDP3 can be used as a wire bonding region. In the case of the semiconductor device PKG3, the extension distance of the wire BW (in other words, the distance from the pad PD of the semiconductor chip CP2 to the wire bonding region of the lead LD) is longer than that of the semiconductor device PKG2 shown in FIG. In this case, it is difficult for each of the plurality of wires BW to be in the tip-off state. In the example shown in FIG. 8, each of the plurality of wires BW is not in the tip-off state.

Further, as shown in FIG. 8, in the case of the semiconductor device PKG3, the portion LDP3 of the lead LD to which the wire BW is connected is between the tape TP2 and the die pad DP. The tape TP2 is disposed in the vicinity of the partial LDP3. Therefore, in the wire bonding step, deformation of the partial LDP 3 can be suppressed when the wire BW is connected to the partial LDP 3, so that the wire bonding can be stably performed. Specifically, if the wire bonding portion to which the wire BW is bonded is held so as not to be deformed, the wire BW and the metal film BM2 on the partial LDP 3 can be stably bonded in the wire bonding step. As a result, the bonding strength between the wire BW and the metal film BM2 can be improved.

  Further, in the case of the semiconductor chip CP having a small planar size as in the semiconductor device PKG1 shown in FIG. 5, even when the wire BW is connected onto the partial LDP1 of the lead LD, the wire BW is less likely to be dislocated from the tip. . For this reason, in the case of the semiconductor device PKG1, even if the wire BW is connected onto the partial LDP1 of the lead LD, the tip end is unlikely to come off and the length of the wire BW can be shortened, thereby improving the electrical characteristics. be able to.

  As described above, as in the semiconductor device PKG1 of the present embodiment, each of the plurality of leads LD has a plurality of wire connectable portions. For this reason, even when a common lead frame is used for a plurality of types of semiconductor chips having different outer sizes and pad PD layouts, it is possible to make it difficult for the tip end off state to occur. In other words, according to the present embodiment, the versatility of the lead frame can be improved, and the reliability of the semiconductor device can be improved.

  In the present embodiment, as an example in the case where the tip off state of the wire BW is likely to occur, semiconductor chips having different outer sizes such as the semiconductor chip CP shown in FIG. 5 and the semiconductor chip CP2 shown in FIG. The example mounted on the same kind of lead frame was taken up and explained. However, the tip-off state occurs according to the planar positional relationship between the pad PD and the wire bonding area of the lead LD. Therefore, even if the outer size of the semiconductor chip is the same, if the arrangement of the plurality of pads PD is different, the tip off state of the wire BW may easily occur.

  Further, the tip-off state of the wire BW is more likely to occur as the angle between the extending direction of the wire BW and the extending direction of the lead LD in the wire bonding region becomes larger. For example, as shown in FIG. 7, among the plurality of leads LD, the lead LDE disposed next to the suspension lead HL1 is more likely to cause the tip end of the wire BW to be out compared with the other leads LD. In particular, in the case of a semiconductor device in which the number of external terminals exceeds 100 as in the present embodiment, the lead LDE is disposed in the vicinity of the suspension lead HL, so the wire BW connected to the lead LDE in plan view And the extending direction of the lead LDE (see the angle θ1 shown in FIG. 7 and the angle θ2 shown in FIG. 8) tend to be large. In FIG. 5, since the angle formed by the wire BW connected to the lead LDE and the extending direction of the lead LDE is close to 0 degree, the illustration of the auxiliary line indicating the angle is omitted.

  As shown in FIG. 7, in the case of the semiconductor device PKG2, an angle θ1 between the wire BW connected to the lead LDE and the extending direction of the tip of the lead LDE is the lead LDE in the semiconductor device PKG1 shown in FIG. The angle between the wire BW to be connected and the extending direction of the tip of the lead LDE is larger. Therefore, when the wire BW is bonded to the metal film BM on the partial LDP 1 of the lead LDE, the tip end of the wire BW is likely to be dislocated. On the other hand, when the wire BW is connected to the metal film BM2 on the portion LDP3 of the lead LDE as in the semiconductor device PKG3 shown in FIG. 8, the angle θ2 shown in FIG. 8 is smaller than the angle θ1 shown in FIG. Therefore, in the case of the semiconductor device PKG3, in the lead LDE in which the tip off state particularly easily occurs, the tip off state of the wire BW does not occur. In other words, in plan view, the wire BW connected to the lead LDE intersects the tip side LDts of the lead LDE.

<Method of Manufacturing Semiconductor Device>
Next, a method of manufacturing the semiconductor device PKG1 and the semiconductor device PKG3 described with reference to FIGS. 1 to 8 will be described with reference to a flowchart shown in FIG. FIG. 9 is an explanatory view showing a flow of an assembly process of the semiconductor device described with reference to FIGS.

  Although FIG. 9 shows the main steps of the manufacturing process of the semiconductor device PKG1, various modified examples other than the assembly flow shown in FIG. 9 can be applied. For example, in FIG. 9, although the marking process which forms a product identification mark in sealing body MR is not shown in figure, this can also be added between a sealing process and a plating process. Further, for example, although the inspection process is not illustrated in FIG. 9, for example, an inspection process may be added after the singulation process.

<Base material preparation process>
In the base material preparation step shown in FIG. 9, a lead frame LF shown in FIG. 10 is prepared. FIG. 10 is an enlarged plan view showing a lead frame prepared in the base material preparation step shown in FIG. FIG. 11 is an enlarged plan view showing the vicinity of the tip end portion of the lead shown in FIG.

  Although the lead frame LF is a base material provided with a plurality of device formation portions LFd, in FIG. 10, one of the plurality of device formation portions LFd is shown enlarged for easy viewing. Further, in FIG. 10, some of the leads LD shown in FIG. 3 are not shown for easy viewing. Similarly, in FIGS. 20 to 22 described later, some of the leads LD illustrated in FIG. 3 are not shown.

  The lead frame LF prepared in this process includes a plurality of device formation portions LFd inside the frame portion LFf. The lead frame LF is made of metal, and in the present embodiment, it is made of metal whose main component is, for example, copper (Cu).

  In the present embodiment, as shown in FIG. 9, a plating process is performed after the sealing process, and an example in which the metal film MC shown in FIG. 2 is formed on the outer lead portion OLD will be described. However, as a modification, at the stage of the base material preparation step, the surface of the base material containing copper as a main component may be previously covered with the metal film MC. In this case, the entire exposed surface of the lead frame LF is covered with the metal film MC.

  Further, as shown in FIG. 10, a die pad DP which is a chip mounting portion is formed at the central portion of the device formation portion LFd. A plurality of suspension leads HL are respectively connected to the die pad DP and arranged to extend toward the corner of the device formation portion LFd. That is, the die pad DP is supported by the suspension lead HL, and is supported by the frame portion LFf of the lead frame LF via the suspension lead HL.

  Further, around the die pad DP, a plurality of leads LD are respectively formed between the plurality of suspension leads HL. The plurality of leads LD are respectively connected to the frame portion LFf. In the example shown in FIG. 10, the plurality of leads LD include a plurality of leads LD1 arranged along the X direction, and a plurality of LD2 arranged along the Y direction intersecting (orthogonal) with the X direction. . In addition, the plurality of leads LD are arranged along the X direction and along the Y direction, and along the X direction, and along the Y direction, and along the opposite side of the multiple leads LD2. Includes a plurality of leads LD4.

  Further, each of the plurality of leads LD is connected to each other via a tie bar TB. The tie bar TB has a function as a dam member for suppressing the leakage of the resin in the sealing step shown in FIG. 9 in addition to the function as a connecting member for connecting the plurality of leads LD. The tie bar TB is connected to the leads LD and the frame portion LFf of the lead frame LF. In addition, one end of each of the leads LD is connected to the frame portion LFf of the lead frame LF. For this reason, each of the leads LD is supported by the frame portion LFf of the lead frame LF until the lead cutting process shown in FIG.

  Further, as shown in FIG. 11, the lead frame LF has a connecting portion LDcp which connects the tip end portions of the plurality of leads LD. At the stage of this process, each of the plurality of leads LD is connected to each other via a connecting portion LDcp connecting the tip end portions, a tie bar TB shown in FIG. 10, and a frame portion LFf.

  Further, the lead frame LF is a tape TP1 fixed to each of the plurality of leads LD so as to straddle each of the plurality of leads LD in plan view, and a plurality of leads so as to straddle each of the plurality of leads LD in plan view And a tape TP2 fixed to each of the LDs. In the example of the present embodiment, the tapes TP1 and TP2 do not overlap with the metal films BM and BM2 (see FIG. 11) which are plating films, and are stuck on the portions LDP2 of the leads LD. The metal film BM is also formed on the partial LDP1A (see FIG. 11) of the lead LD and on the coupling portion LDcp (see FIG. 11).

  The partial LDP 1A shown in FIG. 11 is a portion removed together with the connection portion LDcp in the lead end cutting step described later, and the remaining portion (part corresponding to the partial LDP 1 shown in FIG. 5) remaining after the lead end cutting step. And.

<Lead tip cutting process>
Next, in the lead tip cutting step shown in FIG. 9, a portion including the connecting portion LDcp shown in FIG. 11 is removed from the tip portion of the lead LD. FIG. 12 is an enlarged plan view showing a state in which a part of the lead is removed in the lead tip cutting step included in the manufacturing process of the semiconductor device shown in FIG. FIG. 13 is an enlarged plan view showing a state in which a part of the lead is removed in the lead tip cutting step included in the manufacturing process of the semiconductor device shown in FIG.

  In the case of the present embodiment, as described above, a common lead frame is used for a plurality of types of semiconductor chips. Therefore, a portion of the lead LD is removed in the lead tip cutting step, but the range in which the portion of the lead LD is removed is selected according to the type of semiconductor chip mounted in the die bonding step shown in FIG. .

  First, when the semiconductor chip mounted in the die bonding step is the semiconductor chip CP shown in FIG. 5, the connecting portion LDcp (see FIG. 11) so that the tape TP1 remains as shown in FIG. 12 before the die bonding step. And a portion of the LDP 1A (see FIG. 11) at the tip of each of the leads LD. By this process, tip side LDts is formed in partial LDP1 which is the remaining part of partial LDP1A of each lead LD. The wire BW (see FIG. 5) is connected to the metal film BM on the partial LDP 1 including the tip side LDts in the wire bonding step shown in FIG. In other words, in the wire bonding step, the wire BW is connected to the remaining part of the metal film BM formed on the remaining part of the LDP 1 in the tip part.

  On the other hand, when the semiconductor chip mounted in the die bonding step is the semiconductor chip CP2 (see FIG. 8) whose appearance in plan view differs from the semiconductor chip CP shown in FIG. 5, the lead tip cutting step is performed as follows. Be done. That is, for example, when the outer size of the semiconductor chip CP2 is larger than the outer size of the semiconductor chip CP, the connecting portion LDcp (see FIG. 11) such that the tape TP2 is left as shown in FIG. Then, all of the partial LDP1A (see FIG. 11) of each of the tips of the plurality of leads LD and all of the partial LDP2 (see FIG. 11) of each of the tips of the plurality of leads LD are removed. By this process, tip side LDts is formed in each partial LDP3 of a plurality of leads LD. The wire BW (see FIG. 8) is connected to the metal film BM2 on the partial LDP 3 having the tip side LDts in the wire bonding step shown in FIG. In other words, in the wire bonding step, the wire BW is connected to the metal film BM2 formed in the partial LDP 3 of the tip. Note that in this process, a part of the portion LDP3 of the tip of each of the plurality of leads LD may be removed. In this case, in the wire bonding step, the wire BW is connected to the remaining part of the metal film BM2 formed on the remaining part of the LDP 3 in the tip part.

  As described above, in the present embodiment, after preparing a lead frame having a plurality of wire bondable regions at each of a plurality of leads LD, the semiconductor chip is mounted on the die pad DP before the die bonding step. Select the part to be used as the wire bonding area according to the type of. Then, when the partial LDP3 is used as a wire bonding area, the tape TP1 shown in FIG. 11 is removed before the die bonding step. For this reason, when connecting the wire BW to the metal film BM2 in the wire bonding step, the tape TP1 does not get in the way. Also, after the present process, each of the plurality of leads LD is fixed by the tape TP2 attached in the vicinity of the partial LDP3. Therefore, deformation of the periphery of the partial LDP 3 can be suppressed.

  In the present process, the method for removing a part of the tip of the lead LD is not particularly limited. For example, the leading end of the lead LD may be cut using a cutting die including a die and a punch (not shown), and the removal portion may be removed. Alternatively, there is a method of removing the tip of the lead LD by etching.

  Further, in the present embodiment, although the base material preparation step and the lead end step have been described separately, the steps up to the office for implementing the steps after the die bonding step shown in FIG. 9 and the lead end cut step are performed. The place of business may be different. In this case, at a business office implementing the steps after the die bonding step, the lead frame in a state in which the lead tip cutting step is completed may be prepared as the base material preparation step before the die bonding step.

<Die bonding process>
Next, in the die bonding step (semiconductor chip mounting step) shown in FIG. 9, as shown in FIG. 14, the semiconductor chip CP is mounted on the die pad DP. Alternatively, as shown in FIG. 15, the semiconductor chip CP2 is mounted on the die pad DP. FIG. 14 is an enlarged plan view showing the semiconductor chip mounted on the die pad of the lead frame shown in FIG. FIG. 15 is an enlarged plan view showing a state in which the semiconductor chip is mounted on the die pad of the lead frame shown in FIG.

  Each of the semiconductor chip CP (see FIG. 14) and the semiconductor chip CP2 (see FIG. 15) has a surface CPt on which a plurality of pads PD are formed and a back surface CPb opposite to the surface CPt. In this step, for example, the semiconductor chip CP and the die pad DP are bonded and fixed via a die bonding material DB (see FIG. 2) which is an adhesive made of a thermosetting resin such as an epoxy resin. In the example shown in FIG. 14, the semiconductor chip CP is mounted so that a part of the upper surface DPt of the die pad DP is covered by the semiconductor chip CP in plan view. In the example shown in FIG. 15, the semiconductor chip CP2 is mounted so that a part of the upper surface DPt of the die pad DP is covered by the semiconductor chip CP2 in plan view. The semiconductor chip CP is smaller in planar size than the semiconductor chip CP2. For this reason, after the process, the area of the die pad DP exposed from the semiconductor chip CP or CP2 is smaller in the example shown in FIG.

  Further, as described with reference to FIG. 2, in the example of the present embodiment, the semiconductor chip CP (or the semiconductor chip CP2 shown in FIG. 15) is opposed to the upper surface DPt where the back surface CPb is the chip mounting surface of the die pad DP. As a result, it is mounted on the die pad DP by a so-called face-up mounting method.

  When the lead end cutting process shown in FIG. 9 is performed in the same office as the die bonding process, the lead end cutting process can be performed after the die bonding process. However, in this case, when removing the tip of the lead LD, it is necessary to work in a state in which the already mounted semiconductor chip CP (or CP2) is protected. Therefore, from the viewpoint of suppressing damage to the semiconductor chip CP (or CP2), the lead tip cutting step is preferably performed before the die bonding step.

<Wire bond process>
Next, in the wire bonding step shown in FIG. 9, as shown in FIG. 16, a plurality of pads PD formed on the surface CPt of the semiconductor chip CP and a plurality of leads LD arranged around the semiconductor chip CP. And the plurality of wires (conductive members) BW are electrically connected to one another. Alternatively, in the wire bonding step shown in FIG. 9, as shown in FIG. 17, a plurality of pads PD formed on the surface CPt of the semiconductor chip CP2 and a plurality of leads LD arranged around the semiconductor chip CP2. They are electrically connected to one another via a plurality of wires (conductive members) BW.

  FIG. 16 is an enlarged plan view showing a state in which the semiconductor chip shown in FIG. 14 and a plurality of leads are electrically connected via wires. FIG. 17 is an enlarged plan view showing a state in which the semiconductor chip shown in FIG. 15 and a plurality of leads are electrically connected via wires. FIG. 18 is an enlarged cross-sectional view showing a state in which the pad and the lead of the semiconductor chip shown in FIG. 16 are electrically connected via a wire. FIG. 19 is an enlarged cross-sectional view showing a state in which the pad and the lead of the semiconductor chip shown in FIG. 17 are electrically connected via a wire.

  In this process, for example, as shown in FIGS. 18 and 19, the heat stage 10 having the recess 10c is prepared, and the semiconductor chip CP (or CP2) is mounted such that the die pad DP is positioned in the recess 10c. The lead frame LF is placed on the heat stage 10. Then, the pad PD and the lead LD of the semiconductor chip CP (or CP2) are electrically connected via the wire BW. Here, in the present embodiment, the wire BW is supplied through the capillary 11, and the wire BW is bonded by a bonding method in which ultrasonic and thermocompression bonding are used in combination. Also, in the present embodiment, after connecting one end of the wire BW to the pad PD of the semiconductor chip CP, the other end of the wire BW is connected to the wire bonding region of the lead LD, a so-called positive bonding method The wire BW is joined by In the example shown in FIG. 18, the other end of the wire BW is bonded to the metal film BM formed on the upper surface LDt of the lead LD. On the other hand, in the example shown in FIG. 19, the other end of the wire BW is bonded to the metal film BM2 formed on the upper surface LDt of the lead LD.

  Prior to this process, the tips of the plurality of leads LD are cut in accordance with the type of semiconductor chip mounted on the die pad DP. For this reason, as shown in FIG. 16 and FIG. 17, the plurality of wires BW are not in the state of tip-off with respect to the lead LD to which the wires BW are connected.

  For example, in the example illustrated in FIG. 16, the wire BW connected to the metal film BM on the portion LDP1 of the lead LDE located next to the suspension lead HL1 intersects the tip side LDts of the lead LDE in plan view. Further, in plan view, the wires BW connected to each of the plurality of leads LD intersect the tip side LDts of each of the plurality of leads LD.

  For example, in the example illustrated in FIG. 17, the wire BW connected to the metal film BM2 on the portion LDP3 of the lead LDE located next to the suspension lead HL1 intersects the tip side LDts of the lead LDE in plan view. Further, in plan view, the wires BW connected to each of the plurality of leads LD intersect the tip side LDts of each of the plurality of leads LD.

  Further, in this process, the leads LD are heated via the heat stage 10. Therefore, it is preferable that the tapes TP1 and TP2 (see FIG. 18) attached to the leads LD be disposed so as not to inhibit the adhesion between the heat stage 10 and the leads LD. Therefore, it is preferable that the tape TP1 and the tape TP2 be attached to the same surface as the surface to which the wire BW is joined among the upper surface LDt and the lower surface LDb of the lead LD. In the case of the present embodiment, the wire BW is bonded to the upper surface LDt side of the lead LD. Therefore, each of the tape TP1 and the tape TP2 is attached to the upper surface LDt of the lead LD. Thereby, the heat stage 10 and the leads LD can be brought into close contact with each other.

  Further, according to the present embodiment, the vicinity of each wire bonding area of the plurality of leads LD is held by the tape TP1 or the tape TP2. For this reason, it is possible to suppress deformation of a part of the lead LD in the wire bonding process. As a result, the wire BW can be reliably bonded to the wire bonding region of each of the plurality of leads LD.

<Sealing process>
Next, in the sealing step shown in FIG. 9, the inner lead portion ILD of the semiconductor chip CP (or CP2), the plurality of wires BW and the plurality of leads LD shown in FIG. 16 or 17 is sealed with resin. , Form a sealing body MR shown in FIG. FIG. 20 is an enlarged plan view showing a state in which a sealing body for sealing a semiconductor chip is formed in the sealing step shown in FIG. The semiconductor chip CP shown in FIG. 16 and the semiconductor chip CP2 shown in FIG. 17 have the same appearance of the device formation portion LFd after the sealing step, and therefore FIG. 20 is shown as a diagram common to both cases. ing.

  In this step, for example, in a state in which the lead frame LF is disposed in a molding die having a plurality of cavities (not shown), the resin is supplied into the space formed by the cavities and then the resin is cured to seal Form a body (sealing portion) MR. Such a method of forming the sealing body MR is called a transfer molding method.

  In the example shown in FIG. 20, the sealing body MR is formed in a region surrounded by the tie bars TB of the device formation portion LFd in a plan view. Further, a part of the resin leaking from the cavity is blocked by the tie bar TB. For this reason, the outer lead portion OLD provided for each of the plurality of leads LD is exposed from the sealing body MR.

  As in the present embodiment, when the sealing body MR is formed by the transfer mold method, the plurality of wires BW (FIG. 1) are generated due to the pressure at the time of filling the raw material resin of the sealing body into the cavity. May be deformed. As described above, according to the present embodiment, since each of the plurality of wires BW can be prevented from coming into the tip end state, even if the wires BW are deformed, the wire BW connected to a certain lead LD is Contact with the lead LD positioned next to the lead LD can be suppressed.

<Plating process>
Next, in the plating step shown in FIG. 9, a metal film MC (see FIG. 2) is formed by plating on the exposed surfaces of the plurality of leads LD shown in FIG. The metal film MC formed in this step is formed to improve the wettability of a solder material used as a bonding material when the semiconductor device PKG1 is mounted on a mounting substrate (not shown).

  In this process, it is preferable to form a metal film MC made of solder on the exposed surface of the lead LD. Further, as a method of forming the metal film MC, an electroplating method can be applied in which ionized metal ions are deposited on the exposed surface of the lead LD. The electroplating method is preferable in that the film quality of the metal film MC can be easily controlled by controlling the current at the time of forming the metal film MC. Further, the electrolytic plating method is preferable in that the formation time of the metal film MC can be shortened.

<Lead cutting process>
Next, in the lead cutting process shown in FIG. 9, as shown in FIG. 21, the outer lead portions OLD of the plurality of leads LD are cut, and each of the plurality of leads LD is separated from the lead frame LF. Further, in the present embodiment, after cutting the leads LD, bending as shown in FIG. 2 is performed to form a plurality of leads LD. FIG. 21 is an enlarged plan view showing a state in which a metal film is formed on the exposed surfaces of the plurality of leads shown in FIG.

  In this process, the tie bar TB (see FIG. 20) connecting the leads LD is cut. Further, each of the plurality of leads LD is separated from the frame portion LFf. As a result, the plurality of leads LD become independent members separated from one another. In addition, after the plurality of leads LD are separated, the sealing body MR and the plurality of leads LD are supported by the frame portion LFf via the suspension leads HL (see FIG. 10).

  The plurality of leads LD and tie bars TB are cut by pressing using a cutting die. Further, as shown in FIG. 2, for example, the outer leads OLD of the plurality of leads LD are subjected to bending processing using, for example, press processing using a molding die (not shown). Can be molded into

<Dividing process>
Next, in the singulation step shown in FIG. 9, as shown in FIG. 22, the plurality of suspension leads HL are respectively cut to separate the semiconductor package in each of the device formation portions LFd. FIG. 22 is an enlarged plan view showing a state in which the semiconductor package is obtained by cutting the suspension lead shown in FIG.

  In this step, the plurality of suspension leads HL shown in FIG. 10 and the resin remaining at the corner of the sealing body MR are cut to obtain a semiconductor package (specifically, an inspection body before the inspection step). The cutting method can be performed by, for example, press working using a cutting die (not shown) as in the above-described lead forming process.

  After this process, necessary inspections and tests such as appearance inspections and electrical tests are performed, and those which pass the test become semiconductor devices PKG1 of the finished product shown in FIG. 1 or semiconductor devices PKG3 shown in FIG.

  Next, representative modifications to the embodiment described with reference to FIGS. 1 to 22 will be described.

<Modification 1>
For example, in FIGS. 1 to 22, an embodiment in which the semiconductor chip CP (see FIG. 5) and the semiconductor chip CP2 (see FIG. 8) having different outer sizes are mounted on the die pad DP of the common lead frame has been described. However, as described above, whether or not the tip of the wire BW is deviated depends on the positional relationship between the pad of the semiconductor chip and the wire bonding area of the lead.

  Therefore, for example, even if it is a semiconductor chip having the same external size as the semiconductor chip CP as in the semiconductor chip CP3 shown in FIG. 23, the wire BW can be formed on the metal film BM2 over the partial LDP 3 similarly to the semiconductor device PKG3 shown in It may be easier to prevent the tip from coming off if it is connected. FIG. 23 is a plan view showing a modification of the semiconductor chip shown in FIG. The semiconductor chip CP3 shown in FIG. 23 differs from the semiconductor chip CP shown in FIG. 3 in the arrangement of the pads PD. Specifically, the semiconductor chip CP3 is similar to the semiconductor chip CP shown in FIG. 3 in that the plurality of pads PD are arranged along the four sides of the surface CPt, the number of pads PD, and the external size. However, the plurality of pads PD included in the semiconductor chip CP3 are arranged in a plurality of rows (two rows in FIG. 23) along each side of the surface CPt. In addition, each of the pad groups arranged along each side of the surface CPt of the semiconductor chip CP3 is arranged to be concentrated near the center of each side of the surface CPt.

  When this semiconductor chip CP3 is mounted on the die pad DP as in the case of the semiconductor chip CP shown in FIG. 5, for example, the distance between the lead LDE next to the suspension lead HL1 and the pad PD becomes long. When the wire BW is connected to the lead LDE, an angle (an angle corresponding to the angle θ1 shown in FIG. 7) between the extending direction of the wire BW and the extending direction of the tip of the lead LDE becomes large. Therefore, when the semiconductor chip CP3 is mounted on the die pad DP, the connection portion LDcp, the partial LDP1A, and the portion illustrated in FIG. 11 are performed prior to the die bonding step as in the method of manufacturing the semiconductor device PKG3 illustrated in FIG. It is preferable to remove all of LDP2 (and part of the LDP2 side of partial LDP3). In this case, the wire BW connected to the pad PD of the semiconductor chip CP3 is connected to the portion LDP3 of the lead LD. As a result, it can be suppressed that the wire BW connected to the semiconductor chip CP3 is in the tip-off state.

  For example, as shown in FIG. 24, even when the semiconductor chip CP is mounted on the die pad DP, the wire BW is connected to the metal film BM2 on the partial LDP 3 as in the semiconductor device PKG3 shown in FIG. In some cases, it may be easier to suppress the tip-off state. FIG. 24 is an enlarged plan view showing the positional relationship between the die pad and the semiconductor chip of the semiconductor device which is a modification example to FIG. In FIG. 24, the center CPc of the surface CPt of the semiconductor chip CP is schematically shown by a black circle, and the center DPc of the upper surface DPt of the die pad DP is schematically shown by a cross. In the case of the modification shown in FIG. 24, the center CPc of the surface CPt of the semiconductor chip CP does not overlap with the center DPc of the upper surface DPt of the die pad DP. The positional relationship between the center CPc and the center DPc can be expressed as follows with reference to the lead LDE located next to the suspension lead HL1. In the Y direction, the center CPc is located closer to the lead LDE than the center DPc. In the X direction, the center CPc is disposed at a position farther from the lead LDE than the center DPc.

  In the case of the layout shown in FIG. 24, the angle between the extending direction of the wire BWE connecting the lead LDE and the pad PDE and the extending direction of the tip of the lead LDE is large. Therefore, in order to prevent the wire BWE from being in the tip-off state, it is preferable that the wire BWE is connected to the metal film BM2 on the portion LDP3 of the lead LDE as shown in FIG.

<Modification 2>
In FIGS. 1 to 22, as shown in FIG. 5, the metal film BM is formed on the portion LDP1 at the tip of the lead LD, and the metal film BM2 separated from the metal film BM is formed on the portion LDP3. The embodiment in which the metal film (plating film) is not formed on the partial LDP 2 has been described. In this case, since the tape TP1 is directly stuck on the partial LDP2 of the lead LD, the height of the tape TP1 can be reduced by the height of the metal film BM.

  However, as shown in FIG. 25 as a modification, the metal film BM may be formed across the partial LDP1A, the partial LDP2 and the partial LDP3 (and the connecting portion LDcp) at the tip of the lead LD. In this case, the tape TP1 is fixed to the partial LDP 2 via the metal film BM. FIG. 25 is an enlarged cross-sectional view of a tip portion of a lead which is a modification example of FIG.

  In the case of the modification shown in FIG. 25, the boundary between the partial LDP2 and the partial LDP3 is covered with the metal film BM. For this reason, when utilizing the area | region on partial LDP3 as a wire bonding area | region, a wire can be connected in the state by which the front-end | tip of lead | read | reed LD was covered by metal film BM reliably.

<Modification 3>
Furthermore, as a further modification of the above-mentioned modification 2, as shown in FIG. 26, the metal film BM is not only a part LDP1A, a part LDP2 and a part LDP3 (and a connecting part LDcp) of the tip of the lead LD. , And may be formed across the portion where the tape TP2 is to be attached. In this case, not only the tape TP1 but also the tape TP2 is fixed to the lead LD via the metal film BM.

<Modification 4>
Further, for example, although various modifications have been described as described above, the respective modifications described above can be combined and applied.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

  In addition, part of the contents described in the above embodiment will be described below.

[Supplementary Note 1]
With die pad,
A semiconductor chip mounted on the die pad;
With multiple leads,
A plurality of bonding wires electrically connecting the plurality of leads and the semiconductor chip;
A plated film formed on the tip of each of the plurality of leads;
A first lead fixing tape fixed to each of the plurality of leads so as to straddle each of the plurality of leads in plan view;
And a second lead fixing tape fixed to each of the plurality of leads so as to straddle each of the plurality of leads in plan view,
The second lead fixing tape is fixed at a position farther from the die pad than the first lead fixing tape among the plurality of leads.
The tip portion is, in a plan view, a first portion positioned closer to the die pad than the first lead fixing tape, and a tip portion positioned farther from the die pad than the first portion and fixed to the first lead A second portion where the tape overlaps and a third portion located farther from the die pad than the second portion and located between the first lead fixing tape and the second lead fixing tape And
The semiconductor device, wherein the plurality of bonding wires are connected to the first portion of each of the plurality of leads.

[Supplementary Note 2]
A method of manufacturing a semiconductor device, comprising the following steps:
(A) a die pad, a first suspension lead and a second suspension lead connected to the die pad and supporting the die pad, and a plurality of leads disposed between the first suspension lead and the second suspension lead; The plurality of connecting portions for connecting the respective tip portions of the plurality of leads, the plating film formed on each of the tip portion and the connecting portion, and the plurality of the plurality of leads in plan view A lead frame having a first lead fixing tape fixed to each of the leads and a second lead fixing tape fixed to each of the plurality of leads so as to straddle each of the plurality of leads in plan view Preparing step;
here,
The second lead fixing tape is fixed at a position farther from the die pad than the first lead fixing tape among the plurality of leads.
The tip portion is, in a plan view, a first portion positioned closer to the die pad than the first lead fixing tape, and a tip portion positioned farther from the die pad than the first portion and fixed to the first lead A second portion overlapping the tape, and a third portion located farther from the die pad than the second portion and located between the first lead fixing tape and the second lead fixing tape And
(B) mounting a semiconductor chip on the die pad after the step (a);
(C) after the step (b), electrically connecting the plurality of electrode pads of the semiconductor chip and the plurality of leads via a plurality of bonding wires;
(D) sealing the semiconductor chip and the plurality of bonding wires with resin after the step (c);
here,
When the semiconductor chip mounted in the step (b) is a first semiconductor chip, each of the connecting portion and the plurality of leads is arranged so that the first lead fixing tape remains before the step (b). Removing a portion of the first portion of the tip portion, and in the step (c), bonding the plurality of bonding wires to the remaining portion of the plating film formed on the remaining portion of the first portion of the tip portion Connect each
In the case where the semiconductor chip mounted in the step (b) is a second semiconductor chip, the connecting portion and the first portion of the tip portion are set so that the second lead fixing tape remains before the step (b). Removing the portion and the second portion of the tip, and in the step (c), connecting the plurality of bonding wires to the plating film formed on the third portion of the tip,
The plurality of leads have a first lead located next to the first suspension lead,
When the semiconductor chip mounted in the step (b) is the second semiconductor chip, the semiconductor chip is connected to the extending direction of the tip of the first lead and on the third portion of the first lead When the semiconductor chip mounted in the step (b) is the first semiconductor chip, an angle formed by the extending direction of the wire is the extending direction of the tip portion of the first lead and the first direction. A method of manufacturing a semiconductor device, wherein the angle is larger than the angle formed by the extending direction of a wire connected on the first portion of a lead.

10 heat stage 10 c recessed portion 11 capillary BM, BM 2 metal film (plated film, plated metal film)
BW, BWE Wire (Conductive member)
CP, CP2, CP3 Semiconductor chip CPb Back surface CPc Center CPt Surface (main surface)
DB die bonding material (adhesive material)
DP die pad (chip mounting part)
DPc center DPt upper surface (chip mounting surface, surface)
HL, HL1, HL2, HL3, HL4 Hanging lead HLB offset part (folded part)
ILD Inner lead part LD, LD1, LD2, LD3, LD4, LDE Lead LDb Lower side LDcp Coupling part LDg1, LDg2, LDg3, LDg4 Lead group LDP1, LDP1A, LDP2, LDP3 Partial LDt Upper surface (surface)
LDts Tip side LF Lead frame LFd Device formation part LFf Frame part MC Metal film (exterior plating film)
MR sealing body (sealing part, resin body)
MRb lower surface (rear surface, mounting surface)
MRc Corner MRs Side MRt Top OLD Outer lead PD, PDE Pad (bonding pad, electrode pad)
PKG1, PKG2, PKG3 Semiconductor devices S1, S2, S3, S4 Side (main side)
TB tie bar TP1, TP2 tape (lead fixing tape)
θ1, θ2 angle

Claims (10)

A method of manufacturing a semiconductor device, comprising the following steps:
(A) A die pad, a plurality of leads, a connecting portion for connecting the respective tips of the plurality of leads to each other, a plated film formed on each of the tip and the connecting portion, and the above in a plan view A first lead fixing tape fixed to each of the plurality of leads so as to straddle each of the plurality of leads, and a first tape fixed to each of the plurality of leads so as to straddle each of the plurality of leads in plan view Preparing a lead frame having a two lead fixing tape;
here,
The second lead fixing tape is fixed at a position farther from the die pad than the first lead fixing tape among the plurality of leads.
The tip portion is, in a plan view, a first portion positioned closer to the die pad than the first lead fixing tape, and a tip portion positioned farther from the die pad than the first portion and fixed to the first lead A second portion overlapping the tape, and a third portion located farther from the die pad than the second portion and located between the first lead fixing tape and the second lead fixing tape And
(B) mounting a semiconductor chip on the die pad after the step (a);
(C) after the step (b), electrically connecting the plurality of electrode pads of the semiconductor chip and the plurality of leads via a plurality of bonding wires;
(D) sealing the semiconductor chip and the plurality of bonding wires with resin after the step (c);
here,
When the semiconductor chip mounted in the step (b) is a first semiconductor chip, each of the connecting portion and the plurality of leads is arranged so that the first lead fixing tape remains before the step (b). Removing a portion of the first portion of the tip portion, and, in the step (c), forming the plurality of bonding wires on the remaining portion of the plating film formed on the remaining portion of the first portion of the tip portion. Connect each
In the case where the semiconductor chip mounted in the step (b) is a second semiconductor chip different in appearance in plan view from the first semiconductor chip, the second lead fixing tape remains before the step (b). And the first portion of the tip portion and the second portion of the tip portion are removed, and in the step (c), the plating formed on the third portion of the tip portion is further performed. The plurality of bonding wires are respectively connected to the film. In claim 1,
A method of manufacturing a semiconductor device, wherein an outer size of the first semiconductor chip and an outer size of the second semiconductor chip are different from each other. In claim 2,
A method of manufacturing a semiconductor device, wherein an outer size of the first semiconductor chip is smaller than an outer size of the second semiconductor chip. In claim 1,
A method of manufacturing a semiconductor device, wherein an array of a plurality of electrode pads included in the first semiconductor chip and an array of a plurality of electrode pads included in the second semiconductor chip are different from each other. In claim 1,
The lead frame has a first suspension lead and a second suspension lead connected to the die pad and supporting the die pad,
The plurality of leads are disposed between the first suspension lead and the second suspension lead,
The plurality of leads have a first lead located next to the first suspension lead,
When the semiconductor chip mounted in the step (b) is the second semiconductor chip, the semiconductor chip is connected to the extending direction of the tip of the first lead and on the third portion of the first lead When the semiconductor chip mounted in the step (b) is the first semiconductor chip, an angle formed by the extending direction of the wire is the extending direction of the tip portion of the first lead and the first direction. A method of manufacturing a semiconductor device, wherein the angle is larger than the angle formed by the extending direction of a wire connected on the first portion of a lead. In claim 1,
The lead frame has a first suspension lead and a second suspension lead connected to the die pad and supporting the die pad,
The plurality of leads are disposed between the first suspension lead and the second suspension lead,
The plurality of leads have a first lead located next to the first suspension lead,
Before the step (b), the tip end of the first lead is formed with a tip side which intersects the extending direction of the tip and faces the die pad in plan view,
In the step (c), there is provided a method of manufacturing a semiconductor device in which a wire connected to the first lead intersects the tip side of the first lead in plan view. In claim 1,
Before the step (b), a tip side which intersects the extending direction of the tip and faces the die pad in plan view is formed at the tip of each of the plurality of leads.
In the step (c), there is provided a method of manufacturing a semiconductor device in which a wire connected to each of the plurality of leads intersects the tip side of each of the plurality of leads in plan view. In claim 1,
The method for manufacturing a semiconductor device, wherein the plating film is formed on each of the first portion and the third portion, and not formed on the second portion. In claim 1,
The plating film is formed across the first portion, the second portion, and the third portion of the tip portion,
The method of manufacturing a semiconductor device, wherein the first lead fixing tape is fixed on the second portion via the plating film. In claim 1,
A method of manufacturing a semiconductor device, wherein each of the first lead fixing tape and the second lead fixing tape is fixed to each of the plurality of leads via the plating film.

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