JP2019068067A - Semiconductor memory element - Google Patents

Abstract

To provide a three-dimensional semiconductor memory element in which an integration degree is improved.SOLUTION: A semiconductor memory element includes multiple memory cell transistors laminated on a substrate in a vertical direction, a first conductive line to be connected with a source of at least one memory cell transistor, a second conductive line to be connected with a gate of the memory cell transistor, and a capacitor connected with a drain of at least one memory cell transistor. The capacitor includes a first electrode extending from the drain horizontally in a first direction parallel with a top face of the substrate. One of the first and second conductive lines is extended horizontally in a second direction intersecting with the first direction, and the other of the first and second conductive lines is extended vertically in a third direction perpendicular to the top face of the substrate.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor memory device with improved integration.

  There is a need to increase the degree of integration of semiconductor devices in order to satisfy the superior performance and inexpensive price demanded by consumers. In the case of semiconductor devices, the degree of integration is an important factor in determining the value of a product, so an increased degree of integration is particularly required. In the case of a conventional two-dimensional or planar semiconductor device, the degree of integration thereof is mainly determined by the area occupied by unit memory cells, and thus is greatly influenced by the level of fine patterning technology. However, since an extremely expensive equipment is required to miniaturize the pattern, the degree of integration of the two-dimensional semiconductor device is increasing, but it is still restrictive. Therefore, a three-dimensional semiconductor memory device having memory cells arranged three-dimensionally has been proposed.

U.S. Patent No. 7,781,773 U.S. Pat. No. 8,207,032 U.S. Patent No. 8,441,053 U.S. Patent No. 8,780,602 U.S. Patent No. 9,514,792 U.S. Patent No. 9,887,199 U.S. Patent Application Publication No. 2010/0308390 U.S. Patent Application Publication No. 2014/0008711 U.S. Patent Application Publication No. 2016/0064079 US Patent Application Publication No. 2017/0053906

  The problem to be solved by the present invention is to provide a three-dimensional semiconductor memory device with an increased degree of integration.

  A semiconductor memory device according to the concept of the present invention comprises a plurality of memory cell transistors vertically stacked on a substrate, a first conductive line connected to a source of at least one of the memory cell transistors, and the memory cell transistor And a capacitor connected to the drain of the at least one memory cell transistor. The capacitor may include a first electrode extending horizontally from the drain in a first direction parallel to the top surface of the substrate, and one of the first and second conductive lines may be formed in the first direction and the first direction. The first electrode may extend horizontally in a second intersecting direction, and the other one of the first and second conductive lines may extend vertically in a third direction perpendicular to the top surface of the substrate.

  A semiconductor memory device according to another aspect of the present invention may include a plurality of structures vertically spaced from one another and vertically stacked on a substrate. Each of the structures includes a semiconductor pattern having a first impurity region, a channel region, and a second impurity region, and a first electrode of a capacitor connected to the second impurity region, each of the structures May be horizontally extended in a first direction parallel to the top surface of the substrate.

  According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a stacked structure having a plurality of layers stacked vertically on a substrate; and extending vertically through the stacked structure through the stacked structure. And a first conductive line. Each of the layers of the stacked structure has a first extension extending horizontally in a first direction parallel to the upper surface of the substrate, and a second direction intersecting the first direction from the first extension. And a second extension extending horizontally, wherein the first extension includes a second conductive line, and the second extension includes a semiconductor pattern and a first electrode connected to the semiconductor pattern. The semiconductor pattern may be interposed between the second conductive line and the first electrode, and the first conductive line may surround the semiconductor pattern.

  A memory cell transistor and a capacitor may be three-dimensionally stacked on a substrate in a three-dimensional semiconductor memory device according to an embodiment of the present invention. Therefore, the integration degree of the memory device can be improved.

1 is a simplified circuit diagram of a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention. 1 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. It is sectional drawing which shows M area | region of FIG. It is sectional drawing which shows N area | region of FIG. FIG. 3 is a cross-sectional view illustrating an M region of FIG. 2, for explaining a three-dimensional semiconductor memory device according to an embodiment of the present invention. 1 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. It is sectional drawing which shows M area | region of FIG. It is sectional drawing which shows N area | region of FIG. 1 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. It is sectional drawing which shows M area | region of FIG. 1 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. 1 is a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention. It is sectional drawing in alignment with the A-A 'line | wire of FIG. It is sectional drawing in alignment with the B-B 'line | wire of FIG. It is sectional drawing in alignment with the C-C 'line | wire of FIG. 1 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. It is sectional drawing in alignment with the A-A 'line | wire of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. It is sectional drawing in alignment with the A-A 'line | wire of FIG. It is sectional drawing which follows the B-B 'line | wire of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 18 is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 18 is a cross-sectional view taken along the line B-B ′ of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 20 is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 20 is a cross-sectional view taken along the line B-B ′ of FIG. FIG. 20 is a cross-sectional view taken along the line C-C ′ of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. It is sectional drawing in alignment with the A-A 'line | wire of FIG. It is sectional drawing in alignment with the B-B 'line | wire of FIG. It is sectional drawing which follows the C-C 'line | wire of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 24 is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 24 is a cross-sectional view taken along the line B-B ′ of FIG. FIG. 24 is a cross-sectional view taken along the line C-C ′ of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 26 is a cross-sectional view of FIG. 25 taken along the line A-A ′. FIG. 26 is a cross-sectional view taken along the line B-B ′ of FIG. 25. FIG. 26 is a cross-sectional view taken along the line C-C ′ of FIG. 25. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 28 is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 28 is a cross-sectional view taken along the line B-B ′ of FIG. FIG. 28 is a cross-sectional view taken along the line C-C ′ of FIG. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 30 is a cross-sectional view taken along the line A-A ′ of FIG. 29. FIG. 30 is a cross-sectional view taken along the line B-B ′ of FIG. 29. FIG. 30 is a cross-sectional view taken along the line C-C ′ of FIG. 29. FIG. 6 is a plan view illustrating a method of manufacturing a three-dimensional semiconductor memory device in accordance with an embodiment of the present invention. FIG. 32 is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 32 is a cross-sectional view taken along the line B-B ′ of FIG. 31. FIG. 32 is a cross-sectional view taken along the line C-C ′ of FIG.

  FIG. 1 is a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a plurality of sub cell arrays SCA. The sub cell array SCA is arranged along the second direction D2.

  Each sub cell array SCA includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT is disposed between one word line WL and one bit line BL.

  The bit line BL is a conductive pattern (e.g., metal line) spaced apart from the substrate and disposed on the substrate. The bit line BL is extended in the first direction D1. The bit lines BL in one sub cell array SCA are spaced apart from each other in the vertical direction (ie, the third direction D3).

  The word lines WL are conductive patterns (e.g., metal lines) extending in a direction perpendicular to the substrate (i.e., the third direction D3). Word lines WL in one sub cell array SCA are spaced apart from each other in the first direction D1.

  A gate of the memory cell transistor MCT is connected to a word line WL, and a source of the memory cell transistor MCT is connected to a bit line BL. Each memory cell transistor MCT includes a capacitor DS. For example, the drain of the memory cell transistor MCT is coupled to the capacitor DS.

  FIG. 2 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 3A is a cross-sectional view showing a region M of FIG. FIG. 3B is a cross-sectional view showing the N region of FIG.

  Referring to FIGS. 1, 2, 3 A, and 3 B, one of the plurality of sub cell arrays SCA described with reference to FIG. 1 is provided on the substrate 100. The substrate 100 is a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

  Specifically, a stacked structure SS including the first to third layers L1, L2 and L3 is provided on the substrate 100. The first to third layers L1, L2 and L3 of the stacked structure SS are separated from each other in the vertical direction (ie, the third direction D3) and stacked. Each of the first to third layers L1, L2 and L3 includes a plurality of semiconductor patterns SP, a plurality of first electrodes EL1, and a first conductive line CL1.

  The semiconductor pattern SP may have a line shape, a bar shape, or a pillar shape extending in the second direction D2 from the first conductive line CL1. As one example, the semiconductor pattern SP includes silicon, germanium or silicon-germanium. Each semiconductor pattern SP includes a channel region CH, a first impurity region SD1, and a second impurity region SD2.

  The channel region CH is interposed between the first and second impurity regions SD1 and SD2. The channel region CH corresponds to the channel of the memory cell transistor MCT described with reference to FIG. The first and second impurity regions SD1 and SD2 correspond to the source and drain of the memory cell transistor MCT described with reference to FIG. The first and second impurity regions SD1 and SD2 are regions where the semiconductor pattern SP is doped with an impurity. Therefore, the first and second impurity regions SD1 and SD2 have n-type or p-type conductivity.

  The first electrode EL1 is connected to one end of the semiconductor pattern SP. Again, the first electrode EL1 is connected to the second impurity region SD2 of the semiconductor pattern SP. The first electrode EL1 extends horizontally in the second direction D2 from the semiconductor pattern SP. The first electrode EL1 has a line shape, a bar shape, or a pillar shape.

  One end of each of the first electrodes EL1 is connected to the second impurity region SD2 of the semiconductor pattern SP, and the other end of each of the first electrodes EL1 is connected to the support film SUP. An imaginary line connecting the one end and the other end of each of the first electrodes EL1 is defined. The imaginary lines extend parallel to the top surface of the substrate 100. The imaginary line is parallel to the second direction D2.

  The support film SUP physically supports the first electrode EL1 to prevent the first electrode EL1 from bending. The support film SUP is commonly connected to the plurality of first electrodes EL1. The support film SUP includes an insulating material, and the insulating material is any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  The first conductive line CL1 has a line shape or a bar shape extended in the first direction D1. The first conductive lines CL1 are stacked apart from each other along the third direction D3. The first conductive line CL1 includes a conductive material. For example, the conductive material may be a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride film (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium or tantalum), Any one of metal-semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). The first conductive line CL1 is the bit line BL described with reference to FIG.

  Of the first to third layers L1, L2 and L3, the first layer L1 will be representatively described in detail. The semiconductor patterns SP of the first layer L1 may be spaced apart from each other in the first direction D1. The semiconductor patterns SP of the first layer L1 are located at the same first level. The first conductive line CL1 of the first layer L1 is connected to the first impurity region SD1 of the semiconductor pattern SP of the first layer L1. Again, the first conductive line CL1 of the first layer L1 is connected to the first impurity region SD1 and extended in the first direction D1. As an example, the first conductive line CL1 is located at the first level where the semiconductor pattern SP is located.

  The first electrode EL1 of the first layer L1 extends horizontally in the second direction D2 from the semiconductor pattern SP of the first layer L1. The first electrodes EL1 of the first layer L1 may be spaced apart from each other in the first direction D1. The first electrodes EL1 of the first layer L1 are located at the same first level. The first electrode EL1 includes a conductive material, and the conductive material is any one of a doped semiconductor material, a conductive metal nitride film, a metal, and a metal-semiconductor compound. The first electrode EL1 may include substantially the same material as the first conductive line CL1.

  The specific description of the second layer L2 and the third layer L3 is substantially the same as the first layer L1 described above. The first conductive line CL1, the semiconductor pattern SP, and the first electrode EL1 of the second layer L2 may be located at a second level higher than the first level. The first conductive line CL1, the semiconductor pattern SP, and the first electrode EL1 of the third layer L3 are positioned at a third level higher than the second level.

Referring again to FIG. 3A, a dielectric film DL covering the surface of the first electrode EL1 of the stacked structure SS is provided. The dielectric film DL has a uniform thickness on the surface of the first electrode EL1. For example, the dielectric film DL may be a metal oxide such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide, and SrTiO ₃ (STO), (Ba, Sr) TiO ₃ (BST), BaTiO ₃ , PZT, at least one of dielectric materials having a perovskite structure such as PLZT.

  A second electrode EL2 is provided on the dielectric film DL. The second electrode EL2 surrounds the first electrode EL1. The second electrode EL2 includes a conductive material, and the conductive material is any one of a doped semiconductor material, a conductive metal nitride film, a metal, and a metal-semiconductor compound. Each of the first electrode EL1, the dielectric film DL, and the second electrode EL2 constitutes a capacitor DS. The capacitor DS is a memory element for storing data.

  Referring again to FIGS. 1, 2, 3 A, and 3 B, a second conductive line CL 2 penetrating the stacked structure SS is provided on the substrate 100. The second conductive line CL2 has a line shape, a bar shape, or a column shape extended in the third direction D3. The second conductive lines CL2 may be spaced apart from each other in the first direction D1.

  Each second conductive line CL2 surrounds and vertically extends the vertically stacked semiconductor patterns SP. The second conductive line CL2 covers the top, bottom, and both sidewalls of the semiconductor pattern SP (see FIG. 3B). The gate insulating film GI is interposed between the second conductive line CL2 and the semiconductor pattern SP. Again, the memory cell transistor MCT according to the embodiment of the present invention is a gate all around transistor.

  The gate insulating film GI includes a single selected film of a high-k dielectric film, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a combination thereof. For example, the high-k dielectric film may be hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide And at least one of strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

  As one example, one of the second conductive lines CL2 may be a first semiconductor pattern SP of the semiconductor patterns SP of the first layer L1 and a first semiconductor pattern of the semiconductor patterns SP of the second layer L2. It surrounds the first semiconductor pattern SP among the semiconductor patterns SP of the SP and the third layer L3. Another second conductive line CL2 is a second semiconductor pattern SP of the semiconductor patterns SP of the first layer L1, a second semiconductor pattern SP of the semiconductor patterns SP of the second layer L2, and The second semiconductor pattern SP of the semiconductor patterns SP in the third layer L3 is surrounded.

  The second conductive line CL2 includes a conductive material, and the conductive material is any one of a doped semiconductor material, a conductive metal nitride film, a metal and a metal-semiconductor compound. The second conductive line CL2 is the word line WL described with reference to FIG.

  The first semiconductor pattern SP and the first first electrode EL1 of the first layer L1 constitute a first structure. The first semiconductor pattern SP and the first first electrode EL1 of the second layer L2 constitute a second structure. The first semiconductor pattern SP and the first first electrode EL1 of the third layer L3 constitute a third structure. The first to third structures are vertically spaced apart from each other. The first to third structures overlap in the vertical direction. Each of the first to third structures has a line shape, a bar shape, or a column shape extending in the second direction D2. One second conductive line CL2 surrounds the semiconductor pattern SP of the first to third structures.

  Although not shown, the open space in the stacked structure SS is filled with an insulating material. For example, the insulating material includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  A three-dimensional semiconductor memory device according to an embodiment of the present invention includes a memory cell transistor MCT three-dimensionally stacked on a substrate 100 and a first electrode EL1 (i.e., a capacitor) connected to them and horizontally extended. Including DS). Therefore, the degree of integration of elements as compared with a memory element including memory cell transistors arranged in a two-dimensional manner on a conventional substrate and a first electrode (i.e., a capacitor) connected to them and extending in the vertical direction. Can be improved.

  FIG. 4 is a cross-sectional view illustrating an M region of FIG. 2 for explaining a three-dimensional semiconductor memory device according to an embodiment of the present invention. In the present embodiment, detailed description of technical features overlapping with those described above with reference to FIGS. 1, 2, 3A, and 3B will be omitted, and differences will be described in detail. .

  Referring to FIGS. 1, 2, 3 </ b> B and 4, each first electrode EL <b> 1 includes a semiconductor pillar SPI and a conductive film TML surrounding the surface of the semiconductor pillar SPI. The conductive film TML conformally covers the surface of the semiconductor pillar SPI. A dielectric film DL is provided on the conductive film TML.

  The semiconductor pillar SPI has a pillar shape horizontally extended from the semiconductor pattern SP in the second direction D2. The semiconductor pillar SPI is integrally connected to the semiconductor pattern SP. The semiconductor pillar SPI includes the same semiconductor material as the semiconductor pattern SP. As one example, the semiconductor pillar SPI includes a doped semiconductor. The conductive film TML contains any one of a conductive metal nitride film, a metal, and a metal-semiconductor compound.

  FIG. 5 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 6A is a cross-sectional view showing a region M of FIG. FIG. 6B is a cross-sectional view showing the N region of FIG. In the present embodiment, detailed description of technical features overlapping with those described above with reference to FIGS. 1, 2, 3A, and 3B will be omitted, and differences will be described in detail. .

  Referring to FIGS. 1, 5, 6 </ b> A, and 6 </ b> B, back gate lines BG may be provided on the substrate 100 through the stacked structure SS. The back gate line BG has a line shape, a bar shape, or a pillar shape extended in the third direction D3. The back gate lines BG are spaced apart from each other in the first direction D1.

  Each back gate line BG and the second conductive line CL2 adjacent thereto are spaced apart from each other in the second direction D2. The back gate line BG and the second conductive line CL2 adjacent thereto surround the semiconductor pattern SP. The back gate line BG covers the top, bottom, and both sidewalls of the semiconductor pattern SP (see FIG. 6B).

  A first gate insulating film GI1 is interposed between the second conductive line CL2 and the semiconductor pattern SP, and a second gate insulating film GI2 is interposed between the back gate line BG and the semiconductor pattern SP. The second gate insulating film GI2 includes one selected single film of the high-k dielectric film, the silicon oxide film, the silicon nitride film, and the silicon oxynitride film, or a combination thereof.

  For example, when the memory cell transistor MCT is an NMOS, holes are accumulated in the semiconductor pattern SP which is a channel. The back gate line BG may induce holes stored in the semiconductor pattern SP to be discharged through the first conductive line CL1. Therefore, the electrical characteristics of memory cell transistor MCT can be stabilized.

  FIG. 7 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 8 is a cross-sectional view showing a region M of FIG. In the present embodiment, detailed description of technical features overlapping with those described above with reference to FIGS. 1, 2, 3A, and 3B will be omitted, and differences will be described in detail. .

  Referring to FIGS. 1, 7 and 8, a first support film SUP <b> 1 and a second support film SUP <b> 2 are provided on the substrate 100. The first and second support films SUP1 and SUP2 are connected to the first electrode EL1 of the multilayer structure SS to physically support them. The first support film SUP1 is connected to the other end of the first electrode EL1, and the second support film SUP2 is connected to a part between one end of the first electrode EL1 and the other end. The first and second support films SUP1 and SUP2 each independently include any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  FIG. 9 is a perspective view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. In the present embodiment, detailed description of technical features overlapping with those described above with reference to FIGS. 1, 2, 3A, and 3B will be omitted, and differences will be described in detail. .

  Referring to FIG. 9, the first conductive line CL1 has a line shape, a bar shape, or a column shape extended in the third direction D3. The first conductive lines CL1 connect the semiconductor patterns SP stacked in the vertical direction and extend in the vertical direction. The second conductive line CL2 has a line shape, a bar shape, or a column shape extended in the first direction D1. The one second conductive line CL2 extends in the horizontal direction so as to surround the semiconductor pattern SP arranged in the horizontal direction in any one of the layers L1, L2, and L3.

  The semiconductor memory device according to the present embodiment differs from the semiconductor memory device described above with reference to FIGS. 1, 2, 3A, and 3B in that the bit line BL (ie, the first conductive line CL1) is vertical. The word lines WL (i.e., the second conductive lines CL2) are horizontally extended. On the other hand, the semiconductor pattern SP and the first electrode EL1 of the semiconductor memory device according to the present embodiment are horizontally extended from the first conductive line CL1 in the second direction D2.

  FIG. 10 is a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention. 11A to 11C are cross-sectional views taken along the lines A-A ', B-B' and C-C 'of FIG. 10, respectively. FIG. 12 is a perspective view showing a three-dimensional semiconductor memory device according to an embodiment of the present invention. In the present embodiment, detailed description of technical features overlapping with those described above with reference to FIGS. 1, 2, 3A, and 3B will be omitted, and differences will be described in detail. .

  Referring to FIGS. 10, 11A to 11C, and 12, a stacked structure SS is provided on a substrate 100. The stacked structure body SS includes first to fourth layers L1, L2, L3, and L4 sequentially stacked on the substrate 100. Each of the first to fourth layers L1, L2, L3 and L4 includes a first conductive line CL1, a semiconductor pattern SP, and a first electrode EL1. Insulating films IL4 and IL5 are interposed between the first to fourth layers L1, L2, L3 and L4. As an example, the insulating films IL4 and IL5 include any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

  Each of the first to fourth layers L1, L2, L3 and L4 of the stacked structure SS is extended in the second direction D2 from the first extension EP1 and the first extension EP1 extended in the first direction D1. A second extension EP2 is included. The first extension EP1 includes a first conductive line CL1. The second extension part EP2 includes the semiconductor pattern SP and the first electrode EL1.

  The first conductive line CL1 in each of the first to fourth layers L1, L2, L3 and L4 is extended in the first direction D1. The first conductive line CL1 is the bit line BL described with reference to FIG. The semiconductor pattern SP in each of the first to fourth layers L1, L2, L3, L4 comprises a semiconductor material, for example comprising silicon, germanium or silicon-germanium.

  A first trench TR1 penetrating the stacked structure SS is formed. A second extension EP2 of the stacked structure SS is defined by the first trench TR1. A first trench TR1 is defined between a pair of adjacent second extensions EP2 of the stacked structure SS.

  The semiconductor patterns SP adjacent in the horizontal direction are separated from each other by the first trenches TR1. The first electrodes EL1 horizontally adjacent to each other are separated from each other by the first trenches TR1.

  Each semiconductor pattern SP includes a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH is interposed between the first and second impurity regions SD1 and SD2. The first conductive line CL1 is connected to the first impurity region SD1 of the semiconductor pattern SP. The first electrode EL1 is connected to the second impurity region SD2 of the semiconductor pattern SP. The first electrode EL1 is extended in the second direction D2 from the second impurity region SD2 of the semiconductor pattern SP.

  A second conductive line CL2 is provided through the stacked structure SS and extending in the vertical direction (ie, the third direction D3). The second conductive lines CL2 surround the semiconductor patterns SP stacked in the vertical direction, and extend in the third direction D3. The second conductive lines CL2 may be spaced apart from each other along the first direction D1. A gate insulating film GI is provided between the second conductive line CL2 and the semiconductor pattern SP.

  A second electrode EL2 is provided on the first electrode EL1. The second electrode EL2 surrounds the first electrode EL1. A dielectric film DL is interposed between the first electrode EL1 and the second electrode EL2. Each of the first electrode EL1, the dielectric film DL, and the second electrode EL2 constitutes a capacitor DS.

  Support films SUP are provided on both sides of the stacked structure SS. The support film SUP is connected to one end of the second extension EP2 of the stacked structure SS. The support film SUP physically supports the first electrode EL1 of the stacked structure SS.

  FIGS. 13, 15, 17, 19, 21, 23, 25, 27, 29, and 31 illustrate a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. FIGS. 14, 16A, 18A, 20A, 22A, 24A, 26A, 28A, 30A, and 32A are shown in FIGS. 13, 15, 17, 19, 21, 21, 23, respectively. FIG. 28 is a cross-sectional view taken along the line AA 'of FIGS. 25, 27, 29, and 31; FIGS. 16B, 18B, 20B, 22B, 24B, 26B, 28B, 30B, and 32B are shown in FIGS. 15, 17, 19, 21, 23, 23, 25 and 27, respectively. FIG. 30 is a cross-sectional view taken along the line BB ′ in FIGS. FIGS. 20C, 22C, 24C, 26C, 28C, 30C, and 32C are taken along lines CC 'in FIGS. 19, 21, 23, 25, 27, 29, and 31 respectively. It is sectional drawing which follows.

  Referring to FIGS. 13 and 14, the stacked structure SS is formed on the substrate 100. Forming the stacked structure SS includes forming the first to fourth layers L1, L2, L3, and L4 stacked sequentially. Each of the first to fourth layers L1, L2, L3, and L4 includes a first insulating film IL1 and a semiconductor film SL. The semiconductor film SL contains a semiconductor material, for example, silicon, germanium or silicon-germanium. The first insulating film IL1 includes any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the first insulating film IL1 includes a silicon oxide film.

  An additional first insulating film IL1 is formed on the stacked structure body SS. Again, the first insulating film IL1 is formed to cover the uppermost semiconductor film SL of the stacked structure SS.

  Referring to FIGS. 15, 16A and 16B, a first patterning process is performed on the substrate 100 to form a first trench TR1. The stacked structure SS is patterned to have a first extension EP1 and a second extension EP2. Specifically, performing the first patterning process may include forming a first mask pattern having a first opening, and etching the stacked structure SS using the first mask pattern as an etching mask. And removing the first mask pattern. A portion of the top surface of the substrate 100 is exposed by the first trench TR1.

  The first extension EP1 of the stacked structure SS may extend in the first direction D1. The second extension EP2 of the stacked structure SS extends from the first extension EP1 in the second direction D2. The second extensions EP2 are spaced apart from each other along the first direction D1.

  Referring to FIGS. 17, 18A and 18B, a second insulating film IL2 is formed to fill the first trench TR1. The second insulating film IL2 may include an insulating material that is the same as or different from the first insulating film IL1. The second insulating film IL2 includes any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the second insulating film IL2 includes a silicon oxide film.

  Referring to FIGS. 19 and 20A to 20C, a second patterning process is performed on the substrate 100 to form a second trench TR2. The second trench TR2 is extended in the first direction D1. Specifically, performing the second patterning process may include forming a second mask pattern having a second opening, and selectively etching the first insulating film IL1 using the second mask pattern as an etching mask. And removing the second mask pattern.

  During the second patterning process, the first insulating film IL1 exposed by the second opening is selectively removed. The second trench TR <b> 2 formed by removing the first insulating film IL <b> 1 exposes a part of the semiconductor pattern SP of the stacked structure SS.

  Referring to FIGS. 21 and 22A to 22C, a third insulating film IL3 may be formed to fill the second trench TR2. The third insulating film IL3 includes an insulating material having etch selectivity with the first and second insulating films IL1 and IL2. The third insulating film IL3 includes any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the third insulating film IL3 includes a silicon nitride film. The third insulating film IL3 filled in the second trench TR2 exposing one end of the second extension EP2 of the stacked structure SS constitutes a support film SUP.

  Referring to FIGS. 23 and 24A to 24C, the first and second insulating films IL1 and IL2 may be selectively removed. Over the substrate 100, the stacked structure SS including the semiconductor film SL and the third insulating film IL3 remain.

  The semiconductor film SL is exposed by removing the first and second insulating films IL1 and IL2. An impurity doping process is performed on the exposed semiconductor film SL to form a doping region DR in the semiconductor film SL. The doped impurities are diffused by the heat treatment process, and a part of the doping region DR overlaps the third insulating film IL3 in the vertical direction.

  Referring to FIGS. 25 and 26A to 26C, the exposed semiconductor film SL is replaced with a conductive material to form the first conductive line CL1 and the first electrode EL1. Specifically, replacing the semiconductor film SL with a conductive material includes a silicide process. The exposed semiconductor film SL reacts with the metal to form a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide or the like). As another example, replacing the semiconductor film SL with a conductive material includes forming a metal nitride film or a metal film conformally on the semiconductor film SL.

  While the exposed semiconductor film SL is replaced with the conductive material, the semiconductor film SL covered by the third insulating film IL3 is protected. Therefore, the semiconductor film SL covered by the third insulating film IL3 constitutes the semiconductor pattern SP. A channel region CH, a first impurity region SD1, and a second impurity region SD2 are defined in each semiconductor pattern SP. The first and second impurity regions SD1 and SD2 are formed from the remaining doping region DR. The channel region CH is a region interposed between the first and second impurity regions SD1 and SD2.

  Referring to FIGS. 27 and 28A to 28C, the fourth insulating film IL4 is formed on the substrate 100 so as to fill the space in the stacked structure SS. The fourth insulating film IL4 may include an insulating material having etch selectivity with the third insulating film IL3. The fourth insulating film IL4 includes any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the fourth insulating film IL4 includes a silicon oxide film.

  The third insulating film IL3 is selectively removed to form a third trench TR3. However, the support film SUP may not be removed. Specifically, removing the third insulating film IL3 may be performed by forming a third mask pattern having a third opening that exposes the third insulating film IL3, and using the third mask pattern as an etching mask. Selectively etching the insulating film IL3; and removing the third mask pattern. The third mask pattern is formed to cover the support film SUP. On the substrate 100, the stacked structure body SS including the first conductive line CL1, the semiconductor pattern SP, and the first electrode EL1 and the fourth insulating film IL4 remain.

  Referring to FIGS. 29 and 30A to 30C, the gate insulating film GI and the second conductive line CL2 are formed in the third trench TR3. Specifically, the gate insulating film GI is formed to conformally cover the semiconductor pattern SP exposed through the third trench TR3. A conductive film surrounding the semiconductor pattern SP is formed on the gate insulating film GI. The conductive layer is patterned to form second conductive lines CL2 spaced apart from each other in the first direction D1. The conductive film is formed of any one of a doped semiconductor material, a conductive metal nitride film, a metal, and a metal-semiconductor compound. Each of the second conductive lines CL2 is formed to surround the vertically stacked semiconductor patterns SP and extend in the third direction D3.

  Referring to FIGS. 31 and 32A to 32C, the fifth insulating film IL5 is formed to fill the space in the third trench TR3. The fifth insulating film IL5 is formed to cover the upper surface of the fourth insulating film IL4. The fifth insulating film IL5 includes any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the fifth insulating film IL5 includes a silicon oxide film.

  A third patterning process is performed on the substrate 100 to selectively expose the first electrode EL1. Specifically, performing the third patterning process may include forming a fourth mask pattern having a fourth opening, and using the fourth mask pattern as an etching mask to form fourth and fifth insulating films IL4 and IL5. Selectively etching, and removing the fourth mask pattern.

  Referring again to FIGS. 10 and 11A to 11C, a dielectric film DL is formed to conformally cover the exposed first electrode EL1. A second electrode EL2 surrounding the first electrode EL1 is formed on the dielectric film DL. Each of the first electrode EL1, the dielectric film DL, and the second electrode EL2 constitutes a capacitor DS.

  Although the embodiments of the present invention have been described above with reference to the attached drawings, the present invention may be embodied in other specific forms without changing its technical idea and essential features. possible. Thus, the embodiments described above are illustrative in all aspects and not limiting.

100 substrate CL1 first conductive line CL2 second conductive line DL dielectric film DS capacitor EL1 first electrode EL2 second electrode GI gate insulating film MCT memory cell transistor SCA sub cell array SP semiconductor pattern SS laminated structure SUP support film

Claims (24)

A plurality of memory cell transistors vertically stacked on a substrate;
A first conductive line coupled to a source of at least one of the memory cell transistors;
A second conductive line connected to the gate of the memory cell transistor;
A capacitor coupled to the drain of the at least one memory cell transistor,
The capacitor includes a first electrode extending horizontally from the drain in a first direction parallel to the top surface of the substrate,
One of the first and second conductive lines is horizontally extended in a second direction intersecting the first direction,
The semiconductor memory device, wherein the other one of the first and second conductive lines is vertically extended in a third direction perpendicular to the top surface of the substrate. The at least one memory cell transistor includes a semiconductor pattern having the source, the drain, and a channel interposed therebetween.
The semiconductor memory device of claim 1, wherein the semiconductor pattern is extended in the first direction from the first conductive line. The semiconductor pattern and the first electrode are located at the same level as each other,
The semiconductor memory device of claim 2, wherein the semiconductor pattern and the first electrode are aligned in the first direction.   The semiconductor memory device of claim 1, wherein the second conductive line surrounds a channel of each of the memory cell transistors. The capacitor is
A dielectric film covering the first electrode;
The semiconductor memory device of claim 1, further comprising: a second electrode on the dielectric film. The first electrode includes one end connected to the drain and the other end opposite to the one end,
The semiconductor memory device according to claim 1, wherein a virtual line connecting the one end and the other end is parallel to the first direction.   7. The semiconductor memory device of claim 6, further comprising: a first support layer connected to the other end of the first electrode to support the first electrode.   8. The semiconductor memory device of claim 7, further comprising: a second support film disposed between the one end and the other end of the first electrode to support the first electrode.   The semiconductor memory device of claim 1, further comprising a back gate line adjacent to a channel of the memory cell transistor and extending in parallel with the second conductive line. Comprising a plurality of structures vertically spaced apart from one another on a substrate,
Each said structure is
A semiconductor pattern having a first impurity region, a channel region, and a second impurity region;
A first electrode of a capacitor connected to the second impurity region,
A semiconductor memory device, wherein each of the structures extends horizontally in a first direction parallel to the top surface of the substrate. The semiconductor pattern and the first electrode of each of the structures are located at the same level as one another;
The semiconductor memory device of claim 10, wherein the semiconductor pattern and the first electrode of each of the structures are aligned in the first direction.   The semiconductor memory device of claim 10, wherein the structures overlap in a vertical direction. A first conductive line connected to the first impurity region of the semiconductor pattern of at least one of the structures;
And a second conductive line surrounding the channel region of the semiconductor pattern of the structure.
The first conductive line is horizontally extended in a second direction intersecting the first direction,
The semiconductor memory device of claim 10, wherein the second conductive line is vertically extended in a third direction perpendicular to the top surface of the substrate. Further comprising a back gate line surrounding the channel region of the semiconductor pattern of the structure;
The semiconductor memory device of claim 13, wherein the back gate line is extended in the third direction in parallel with the second conductive line. The capacitor is
A dielectric film covering the first electrode of the structure;
The semiconductor memory device of claim 10, further comprising: a second electrode provided on the dielectric layer and commonly covering the first electrode.   The semiconductor memory device of claim 10, further comprising: a support layer connected in common to one end of the first electrode of the structure to support the first electrode. A stacked structure having a plurality of layers vertically stacked on a substrate;
A first conductive line extending through the stacked structure and extending perpendicularly to the top surface of the substrate;
Each of the layers of the laminated structure is
A first extension extending horizontally in a first direction parallel to the top surface of the substrate;
And a second extension extending horizontally from the first extension in a second direction intersecting the first direction,
The first extension includes a second conductive line,
The second extension may include a semiconductor pattern and a first electrode connected to the semiconductor pattern.
The semiconductor pattern is interposed between the second conductive line and the first electrode.
The semiconductor memory device, wherein the first conductive line surrounds the semiconductor pattern. The semiconductor pattern includes a first impurity region, a second impurity region, and a channel region between the first and second impurity regions,
The second conductive line is connected to the first impurity region,
The semiconductor memory device of claim 17, wherein the first electrode is connected to the second impurity region. The plurality of second extensions may be provided in the plurality of layers of each of the stacked structures,
The plurality of second extensions are commonly connected to the first extension,
The semiconductor memory device of claim 17, wherein the second extensions are spaced apart from each other in the first direction.   The semiconductor memory device of claim 17, further comprising: a support film disposed on one side of the stacked structure to commonly connect the first electrodes of the layers. A dielectric film covering the first electrode of the layer;
A second electrode provided on the dielectric layer and commonly covering the first electrode;
The semiconductor memory device of claim 17, wherein the first electrode, the dielectric layer, and the second electrode constitute a capacitor.   The semiconductor memory device of claim 17, wherein the first conductive line surrounds the top surface, the bottom surface, and both sidewalls of the semiconductor pattern.   The semiconductor memory device of claim 17, wherein the second conductive line and the first electrode comprise the same conductive material.   18. The semiconductor memory device of claim 17, further comprising a gate insulating layer interposed between the first conductive line and the semiconductor pattern.

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