JP2019064708A - Tray for semiconductor integrated circuit with notch for binding band - Google Patents

Tray for semiconductor integrated circuit with notch for binding band Download PDF

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JP2019064708A
JP2019064708A JP2017193156A JP2017193156A JP2019064708A JP 2019064708 A JP2019064708 A JP 2019064708A JP 2017193156 A JP2017193156 A JP 2017193156A JP 2017193156 A JP2017193156 A JP 2017193156A JP 2019064708 A JP2019064708 A JP 2019064708A
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semiconductor integrated
tray
integrated circuit
trays
notch
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JP2017193156A
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JP6500068B1 (en
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成彬 朴
Sung-Bin Park
成彬 朴
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SHINON CORP
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SHINON CORP
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Priority to JP2017193156A priority Critical patent/JP6500068B1/en
Priority to TW106135138A priority patent/TWI663110B/en
Priority to CN201711423616.XA priority patent/CN109592177B/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D19/00—Pallets or like platforms, with or without side walls, for supporting loads to be lifted or lowered
    • B65D19/38—Details or accessories
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D21/00—Nestable, stackable or joinable containers; Containers of variable capacity
    • B65D21/02—Containers specially shaped, or provided with fittings or attachments, to facilitate nesting, stacking, or joining together
    • B65D21/0209—Containers specially shaped, or provided with fittings or attachments, to facilitate nesting, stacking, or joining together stackable or joined together one-upon-the-other in the upright or upside-down position
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D2519/00—Pallets or like platforms, with or without side walls, for supporting loads to be lifted or lowered
    • B65D2519/00004—Details relating to pallets
    • B65D2519/00736—Details
    • B65D2519/00935—Details with special means for nesting or stacking
    • B65D2519/00955—Details with special means for nesting or stacking stackable
    • B65D2519/00965—Details with special means for nesting or stacking stackable when loaded
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D2585/00—Containers, packaging elements or packages specially adapted for particular articles or materials
    • B65D2585/68—Containers, packaging elements or packages specially adapted for particular articles or materials for machines, engines, or vehicles in assembled or dismantled form
    • B65D2585/86—Containers, packaging elements or packages specially adapted for particular articles or materials for machines, engines, or vehicles in assembled or dismantled form for electrical components

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Stackable Containers (AREA)
  • Package Frames And Binding Bands (AREA)
  • Packages (AREA)

Abstract

PURPOSE: To form no gap between trays in binding a tray for a semiconductor integrated circuit.SOLUTION: There is presented a tray for a semiconductor integrated circuit characterized in that: an outer peripheral wall 12 which has a predetermined height is formed slightly inside a peripheral edge part of a front side face of a tray 1 for a semiconductor integrated circuit formed into a substantially rectangular shape in plan view along the peripheral edge part; when a plurality of trays for a semiconductor integrated circuit are supposed to be stacked, the peripheral edge part of a front side face 4 is configured to abut on a peripheral edge part of a back side face 5 of another tray for a semiconductor integrated circuit located in the upper stage; and a notch where a binding band for binding the plurality of trays for a semiconductor integrated circuit is hooked is formed along a lower side at least at one place among four places within 3.4 cm or less from respective end edges of two side faces extending in a longer direction or shorter direction of the trays for a semiconductor integrated circuit, a dimension of a depth of the notch being shorter than a dimension of the predetermined height of the outer peripheral wall.SELECTED DRAWING: Figure 2

Description

本発明は、ＩＣパッケージ（ＰＫＧ）等の半導体集積回路部品を収容するためのトレーに関し、詳しくは、複数のトレーの梱包作業において、複数のトレーに結束バンドを掛ける際に生じ得るトレーの撓み（変形）を最小限に抑え、ひいては、これらのトレー間に隙間が生じたり水平方向のズレが生じたりすることを防ぐことに関する。   The present invention relates to a tray for accommodating a semiconductor integrated circuit component such as an IC package (PKG), and more particularly, deflection of a tray which may occur when binding a plurality of trays to a bundling band in packing operations of the plurality of trays. Deformation) to the minimum, thus preventing the formation of gaps or horizontal displacement between the trays.

ＩＣ等の電子部品の製造、測定、出荷の各工程において使用される半導体集積回路用トレーは、納品先で実施される落下試験を含む種々の品質試験に合格しなければならない。落下試験の一例としては、複数の半導体集積回路部品（ＩＣパッケージ等）を載せた複数の半導体集積回路用トレーが結束バンドを使って束ねられ、吸湿剤と一緒にアルミニウムの袋に入れられて真空パッキングされた後、段ボールに入れられて梱包され、約１ｍの高さからコンクリートの地面へ向けて２０回落下させて衝撃を与える試験（トレーの６つの面すべて、３つの辺、四隅の１つを下向きにして１０回落下させることを１セットの落下試験として、２セットの落下試験）が行われる。この落下試験の終了後にトレー上のＩＣ部品が破損していなければ、正規の半導体集積回路用トレーとして出荷先へ納品することができる。   Trays for semiconductor integrated circuits used in manufacturing, measuring, and shipping steps of electronic parts such as ICs must pass various quality tests including drop tests performed at the delivery destination. As an example of the drop test, a plurality of semiconductor integrated circuit trays on which a plurality of semiconductor integrated circuit parts (IC package etc.) are mounted are bundled using a binding band, put in an aluminum bag together with a hygroscopic agent, and vacuumed. After being packed, put into a cardboard box and packed, it will be dropped 20 times from the height of about 1 m to the concrete ground to give an impact test (all 6 sides of the tray, 3 sides, one of the four corners) Two sets of drop tests are performed, with one set being a drop test, in which 10 drops are made downward. If the IC parts on the trays are not damaged after the drop test, they can be delivered to the shipping destination as regular trays for semiconductor integrated circuits.

特許文献３に記載の半導体集積回路装置格納用トレイ（１）においては、結束バンドを掛けるための切り欠き（３）が形成されている。しかし、特許文献１の明細書の段落０００８の後段における「切り欠き（３）とその裏側にあるリブ（６）には段差が無いことが好ましい。それにより剛性を更に増すことができる（明細書の段落０００８）」との記載に基づいて切り欠き（３）の裏側に段差なくリブ（６）が形成されている場合、複数のトレイ（１）が積み重ねられるときに、トレイの表側面の周端部と、１つ上段に位置する別個のトレイの裏側面の外周部とが当接することなく、トレイ間の周縁部に隙間が生じてしまうことがある（特許文献１の図６等を参照）。この点に関し、引用文献３は、切欠きの深さの寸法を外周壁の高さの寸法よりも短くすることを教示していない。   In the semiconductor integrated circuit device storage tray (1) described in Patent Document 3, a notch (3) for attaching a binding band is formed. However, it is preferable that the notch (3) and the rib (6) on the back side of the notch (3) have no step in the latter part of the paragraph 0008 of the specification of Patent Document 1. Thereby, the rigidity can be further increased (Specification When the rib (6) is formed without steps on the back side of the notch (3) based on the description of paragraph 0008), the perimeter of the front side of the tray when the plurality of trays (1) are stacked. A gap may be generated at the peripheral edge between the trays without the end and the outer peripheral portion of the back side of the separate tray located in the upper row being in contact (see FIG. 6, etc. of Patent Document 1) ). In this respect, the cited reference 3 does not teach to make the dimension of the depth of the notch shorter than the dimension of the height of the outer peripheral wall.

特開２００４−１７９８６号公報JP, 2004-17986, A 特開２０１０−１８９０４８号公報JP, 2010-189048, A 特開２０１１−２３８６６０号公報JP 2011-238660 A

従来の半導体集積回路用トレーが結束バンド３を使って束ねられる際には、該半導体集積回路トレーの中央部付近に力が加わり過ぎてトレーが撓むことにより、積み重ねられた半導体集積回路用トレー間に隙間１０が生じてしまう問題があった（図６（ｂ）を参照）。特許文献２に開示されるようなインターロック機能部１１（スタックがたを抑える凸体と凹体とからなるもの）が各トレーに形成されている場合にも、落下試験で大きな衝撃を受けたときに、半導体集積回路用トレー間の隙間が広くなり、該トレー同士の水平方向のズレが大きくなってしまう。すると、下段のトレーに載っている半導体集積回路が、上段の別個のトレーの表ガイド６ａの方へ押され、表ガイド６ａと裏ガイド６ａに挟まれて破損してしまうことがあった（図７（ａ）を参照）。   When the conventional semiconductor integrated circuit trays are bundled using the binding band 3, a force is applied to the vicinity of the central portion of the semiconductor integrated circuit trays so that the trays are bent, thereby stacking the stacked semiconductor integrated circuit trays. There is a problem that a gap 10 is generated between the two (see FIG. 6 (b)). Even in the case where the interlock function portion 11 (having a convex body and a concave body for suppressing stacks) as disclosed in Patent Document 2 is formed in each tray, a large impact is received in the drop test. Occasionally, the gaps between the semiconductor integrated circuit trays become wide, and the horizontal displacement between the trays becomes large. As a result, the semiconductor integrated circuit placed on the lower tray is pushed toward the front guide 6a of the separate tray on the upper stage, and may be damaged by being caught between the front guide 6a and the back guide 6a (see FIG. 7 (a)).

本発明の一実施例においては、平面視で概ね四角形の形状に形成された半導体集積回路用トレーであって、該半導体集積回路用トレーの表側面の周縁部に沿って該周縁部よりも僅かに内側に、所定の高さを有する外周壁が形成されており、複数の該半導体集積回路用トレーが積み重ねられるとした場合に上記表側面の周縁部が、上段に位置する別個の該半導体集積回路用トレーの裏側面の周縁部（アーム掛け部等を除く）に当接するように構成されている、半導体集積回路用トレーにおいて、該半導体集積回路用トレーの長手方向に延びている２つの側面又は短手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所のうちの少なくとも１箇所における下辺に沿って、複数の該半導体集積回路用トレーを束ねる結束バンドを掛けるための切欠きが形成されており、上記外周壁の所定の高さの寸法よりも上記切欠きの深さの寸法の方が短いことを特徴とする、結束バンド用切欠きを有する半導体集積回路用トレーを提示する。   In one embodiment of the present invention, a tray for a semiconductor integrated circuit formed in a substantially rectangular shape in plan view, which is slightly smaller than the periphery along the periphery of the front side surface of the tray for a semiconductor integrated circuit. On the inner side, an outer peripheral wall having a predetermined height is formed, and when the plurality of trays for semiconductor integrated circuits are stacked, the peripheral portion of the front side surface is a separate semiconductor integrated device located in the upper stage In a semiconductor integrated circuit tray configured to abut the peripheral edge portion (except for the arm hook portion etc.) of the back surface of the circuit tray, two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray Alternatively, a banding band for bundling a plurality of the above-mentioned trays for semiconductor integrated circuits is hung along the lower side at at least one of four places within 3.4 cm from each edge of the two side surfaces extending in the lateral direction. Semiconductor integrated circuit having a notch for a bundling band, characterized in that a notch for forming the notch is formed, and the dimension of the depth of the notch is shorter than the dimension of the predetermined height of the outer peripheral wall Present trays.

他の実施例においては、平面視で概ね四角形の形状に形成された半導体集積回路用トレーであって、該半導体集積回路用トレーの表側面の周縁部に沿って該周縁部よりも僅かに内側に、所定の高さを有する外周壁が形成されており、複数の該半導体集積回路用トレーが積み重ねられるとした場合に上記表側面の周縁部が、上段に位置する別個の該半導体集積回路用トレーの裏側面の周縁部（アーム掛け部等を除く）に当接するように構成されている、半導体集積回路用トレーにおいて、該半導体集積回路用トレーの長手方向に延びている２つの側面又は短手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所のうちの少なくとも１箇所の上方に位置する部分の上記外周壁に沿って、複数の該半導体集積回路用トレーを束ねる結束バンドを掛けるための切欠きが形成されており、上記外周壁の所定の高さの寸法よりも上記切欠きの深さの寸法の方が短いことを特徴とする、結束バンド用切欠きを有する半導体集積回路用トレーを提示する。   In another embodiment, there is provided a tray for a semiconductor integrated circuit formed in a generally rectangular shape in a plan view, and slightly inside the periphery along the periphery of the front side surface of the tray for a semiconductor integrated circuit. The outer peripheral wall having a predetermined height is formed, and when the plurality of trays for semiconductor integrated circuits are stacked, the peripheral portion of the front side surface is a separate upper portion for the semiconductor integrated circuit located in the upper stage In a semiconductor integrated circuit tray configured to abut on a peripheral edge portion (except for an arm hook portion etc.) of a back side surface of the tray, two side surfaces or a short side extending in the longitudinal direction of the semiconductor integrated circuit tray A plurality of the semiconductor integrated circuit trays are formed along the outer peripheral wall of the upper portion of at least one of four places within 3.4 cm from each edge of the two side surfaces extending in the hand direction. Bundling It has a notch for forming a band, and has a notch for a tie band characterized in that the dimension of the depth of the notch is shorter than the dimension of the predetermined height of the outer peripheral wall. A tray for a semiconductor integrated circuit is presented.

本発明の結束バンド用切欠きを有する半導体集積回路用トレーによれば複数の該半導体集積回路用トレーを束ねる結束バンドを掛けるための切欠きが形成されているので、結束バンドが掛けられたときに、半導体集積回路用トレーが撓んでしまうことがない。従って、落下試験において大きな衝撃を受けたときに、半導体集積回路用トレー間に隙間が生じることがなく、該半導体集積回路用トレー間にズレが生じることもない。   According to the semiconductor integrated circuit tray having the notch for the binding band of the present invention, the notch for hanging the binding band for binding the plurality of trays for the semiconductor integrated circuit is formed, so when the binding band is hung In addition, the tray for semiconductor integrated circuits does not bend. Therefore, when a large impact is received in the drop test, no gap is generated between the semiconductor integrated circuit trays, and no misalignment occurs between the semiconductor integrated circuit trays.

付随的な効果として、本発明の結束バンド用切欠きを有する半導体集積回路用トレーにおいては、各々の半導体集積回路用トレーのポケットに収納されたＩＣ等の半導体集積回路を盗難の被害から防ぐことができる。その理由は、本発明の半導体集積回路用トレーに形成されている切欠きに結束バンドを掛ければ、半導体集積回路用トレー間に隙間が生じないので、非常に薄くて小さい現在のＩＣパッケージ（ＰＫＧ）であっても、半導体集積回路用トレー間の隙間から滑り落ちてしまうことがないからである。   As an additional effect, in the semiconductor integrated circuit tray having the binding band notch of the present invention, the semiconductor integrated circuit such as an IC or the like stored in the pocket of each semiconductor integrated circuit tray is protected from theft damage. Can. The reason is that if a binding band is placed on the notch formed in the tray for semiconductor integrated circuits of the present invention, a gap is not generated between the trays for semiconductor integrated circuits, so a very thin and small current IC package (PKG Even in the above case, it does not slide off from the gap between the trays for semiconductor integrated circuits.

本発明の結束バンド用切欠きを有する半導体集積回路用トレーを示す図。The figure which shows the tray for semiconductor integrated circuits which has the notch for binding bands of this invention. 結束バンドが掛けられている複数の半導体集積回路用トレーを示す側面図。FIG. 2 is a side view showing a plurality of semiconductor integrated circuit trays on which a binding band is hung. 半導体集積回路用トレーに形成された４つの型式の切欠きを示す側面図。FIG. 6 is a side view showing four types of notches formed in a tray for semiconductor integrated circuits. ４つの型式の切欠きを拡大して示す図。The figure which expands and shows four types of notch. 本発明の半導体集積回路用トレーの一実施例を示す斜視図。FIG. 1 is a perspective view showing an embodiment of a tray for semiconductor integrated circuits of the present invention. 半導体集積回路用トレーの梱包過程を概略的に示す図。FIG. 8 schematically shows a packing process of the tray for semiconductor integrated circuits. （ａ）スタックのズレの大きい従来品のトレーを示す図、（ｂ）スタックのズレのない本発明の半導体集積回路用トレーを示す図。(A) A diagram showing a conventional tray with large misalignment of the stack, (b) A diagram showing a tray for semiconductor integrated circuits of the present invention without misalignment of the stack.

本発明の結束バンド用切欠きを有する半導体集積回路用トレー１（以下、単に「トレー１」ともいう）について、添付の図を参照しつつ具体例に基づいて以下に説明する。   A semiconductor integrated circuit tray 1 (hereinafter, also simply referred to as a "tray 1") having a binding band notch according to the present invention will be described below based on a specific example with reference to the attached drawings.

図１は、本発明の結束バンド用切欠きを有するトレー１を示す六面図である。図１に示される実施例においては、トレー１の長手方向に延びている２つの側面において、各端縁（つまり、コーナー部）から３．４ｃｍ以内の４箇所における下辺のみに沿って切欠き２が形成されている。   FIG. 1 is a six-sided view showing a tray 1 having a binding band notch according to the present invention. In the embodiment shown in FIG. 1, the two side surfaces extending in the longitudinal direction of the tray 1 are notched along only the lower sides at four places within 3.4 cm from each edge (that is, the corner portion). Is formed.

図２に示されるように、積み重ねられた複数のトレー１に結束バンド３を巻き付ける際に、梱包作業員がこれらのトレー１の切欠き２に結束バンド３を掛けながら巻き付けることにより、結束された複数のトレー１間に隙間１０が生じてしまうことがない。   As shown in FIG. 2, when winding the binding band 3 around the plurality of stacked trays 1, the packing worker carries out the binding by winding the binding band 3 around the notches 2 of the tray 1. There are no gaps 10 between the plurality of trays 1.

図３は、種々の切欠き２を有するトレー１の実施例を示す。図３（ａ）〜図３（ｃ）に示される実施例において、平面視で概ね四角形の形状の半導体集積回路用トレー１の長手方向に延びている２つの側面の端縁（コーナー部）付近における上辺及び下辺の少なくとも一方に沿って、結束バンド３を掛けるための切欠き２が形成されている。   FIG. 3 shows an embodiment of a tray 1 with various notches 2. In the embodiment shown in FIGS. 3 (a) to 3 (c), near the edges (corners) of two side surfaces extending in the longitudinal direction of the semiconductor integrated circuit tray 1 having a substantially rectangular shape in plan view. A notch 2 for hanging the binding band 3 is formed along at least one of the upper side and the lower side of.

また、図３（ｄ）に示される実施例においては、平面視で概ね四角形の形状のトレー１の長手方向に延びている２つの側面の端縁付近における上辺及び下辺の少なくとも一方に沿って、結束バンド３を掛けるための切欠き２が形成されており、さらに該切欠き２の位置において、該トレー１の側面が上辺から下辺まで窪んでおり、かつ、切欠き２の幅とほぼ同じ幅を有する溝２ａが形成されている。   Further, in the embodiment shown in FIG. 3D, along at least one of the upper side and the lower side near the edges of the two side surfaces extending in the longitudinal direction of the tray 1 having a substantially rectangular shape in plan view, A notch 2 for hanging the binding band 3 is formed, and the side surface of the tray 1 is recessed from the upper side to the lower side at the position of the notch 2 and has a width substantially the same as the width of the notch 2 A groove 2a is formed.

図４（ａ）〜（ｄ）は、図３（ａ）〜（ｄ）に示した４つの型式の切欠きをそれぞれ拡大して示す図である。図４（ａ）に示される実施例においては、トレー１の長手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所における下辺に沿って、結束バンドを掛けるための切欠き２が形成されている。図４（ｂ）に示される実施例においては、トレー１の長手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所の上方の表側面４に位置する外周壁１２に沿って、結束バンドを掛けるための切欠き２が形成されている。また、図４（ｃ）に示される実施例においては、トレー１の長手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所における上辺及び下辺に沿って、結束バンド３を掛けるための切欠き２が形成されている。   FIGS. 4 (a) to 4 (d) are enlarged views of the four types of notches shown in FIGS. 3 (a) to 3 (d), respectively. In the embodiment shown in FIG. 4 (a), a cut for hanging a tying band along the lower side at four places within 3.4 cm from each edge of the two side surfaces extending in the longitudinal direction of the tray 1 The notch 2 is formed. In the embodiment shown in FIG. 4 (b), the outer peripheral wall 12 located on the four upper front side surfaces 4 within 3.4 cm from each edge of the two side surfaces extending in the longitudinal direction of the tray 1 Along the length, a notch 2 for hooking a tying band is formed. Further, in the embodiment shown in FIG. 4C, the binding band 3 is formed along the upper side and the lower side at four places within 3.4 cm from each edge of the two side surfaces extending in the longitudinal direction of the tray 1. The notch 2 for hooking is formed.

また、図４（ｄ）に示される実施例においては、トレー１の長手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所における上辺及び下辺の両方に沿って、結束バンドを掛けるための切欠き２が形成されており、更には、トレー１の側面が切欠き２の位置において上辺から下辺まで窪んでいて、切欠き２の幅とほぼ同じ幅の溝２ａが形成されている。このようにトレー１の側面の溝２ａが、上述した種々の切欠き２の位置に形成されている場合には、これらの溝２ａに結束バンドを収容させるように掛けることができるので、複数のトレー１を強固に束ねることが可能となる。   Further, in the embodiment shown in FIG. 4 (d), binding is performed along both the upper side and the lower side at four places within 3.4 cm from each edge of the two side surfaces extending in the longitudinal direction of the tray 1. A notch 2 for hanging a band is formed, and furthermore, the side surface of the tray 1 is recessed from the upper side to the lower side at the position of the notch 2 to form a groove 2a having substantially the same width as the width of the notch 2 It is done. Thus, when the grooves 2a on the side surface of the tray 1 are formed at the positions of the various notches 2 described above, it can be hung so as to accommodate the binding band in these grooves 2a. It becomes possible to bundle the tray 1 firmly.

一実施例においては、トレー１の表側面４の外周に沿って、所定の高さを有する外周壁１２が延在している。そして、複数のトレー１を積み重ねる際に、重なり合う下段のトレー１の表側面４に形成されている外周壁１２と、１つ上段に位置するトレー１の裏側面に形成されている凹所とが嵌合することにより、これら２枚のトレー１の位置合わせがなされる。   In one embodiment, an outer peripheral wall 12 having a predetermined height extends along the outer periphery of the front side 4 of the tray 1. Then, when stacking the plurality of trays 1, the outer peripheral wall 12 formed on the front side surface 4 of the overlapping lower stage tray 1 and the recess formed on the back side surface of the tray 1 located one upper stage By fitting, the two trays 1 are aligned.

図５に示される本発明の他の実施例においては、トレー１の長手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所における上辺及び下辺に沿って切欠きが形成されていることに加えて、或いは代わりに、トレー１の短手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の２箇所における上辺及び下辺に沿って切欠きが形成されている。さらなる実施例においては、トレー１の側面の中央部付近にも上辺及び下辺に沿って切欠きが形成されている場合もある。トレー１の側面の中央部付近にも切欠きが形成されている場合には、これらの切欠きの箇所に４つの結束バンドを掛けることにより、複数のトレー１を隙間なく密接させることが可能となる。   In another embodiment of the present invention shown in FIG. 5, notches are formed along the upper and lower sides at four places within 3.4 cm from each edge of the two longitudinally extending sides of the tray 1 In addition to or instead of being cut, notches are formed along the upper side and the lower side at two places within 3.4 cm from each edge of the two side surfaces extending in the short direction of the tray 1 There is. In a further embodiment, a notch may be formed along the upper side and the lower side also near the central portion of the side surface of the tray 1. If a notch is also formed near the central part of the side surface of the tray 1, it is possible to closely attach the plurality of trays 1 without gaps by hanging four binding bands at the location of the notch. Become.

一実施例においては、トレー１の表側面４に形成されている外周壁１２の所定の高さの寸法は約１．５ｍｍであり、トレー１の切欠き２の深さの寸法は約１．０ｍｍである。他の実施例においては、他の寸法を有するように形成されている場合もある。   In one embodiment, the predetermined height dimension of the outer peripheral wall 12 formed on the front side surface 4 of the tray 1 is about 1.5 mm, and the depth dimension of the notches 2 of the tray 1 is about one. It is 0 mm. Other embodiments may be formed to have other dimensions.

複数のトレー１の梱包過程について、図６を参照しつつ説明する。なお、図６は説明することを重視しており、実際の寸法とは異なり得る。図６（ａ）は、ＩＣ等の半導体集積回路部品７を収容するための複数のポケット５が形成された従来の半導体集積回路用トレーを示す平面図である。図６（ｂ）は、従来の梱包過程を概略的に示す図である。   The packing process of the plurality of trays 1 will be described with reference to FIG. Note that FIG. 6 emphasizes the description, and may differ from the actual dimensions. FIG. 6A is a plan view showing a conventional semiconductor integrated circuit tray in which a plurality of pockets 5 for housing semiconductor integrated circuit components 7 such as ICs are formed. FIG. 6 (b) is a view schematically showing a conventional packing process.

梱包作業員は最初に、図６（ａ）に示されるように、半導体集積回路用トレーに形成されているポケット５内に半導体集積回路部品７を納め、続いて、図６（ｂ）に示されるように、半導体集積回路部品７を載せた所定の枚数（５枚又は１０枚であることが多い）のトレーを積み重ねてから、結束バンド３を機械で掛ける。梱包作業員は続いて、図６（ｃ）に示されるように、結束された複数のトレーの周囲に、エアパッキン等からなる緩衝用シート８を一周巻いた後に、段ボール箱９に入れることにより梱包作業を完了させる。   The packing worker first places the semiconductor integrated circuit component 7 in the pocket 5 formed in the tray for semiconductor integrated circuits, as shown in FIG. 6 (a), and subsequently, as shown in FIG. 6 (b). As described above, after stacking a predetermined number (often five or ten) of trays on which the semiconductor integrated circuit components 7 are placed, the binding band 3 is machined. Subsequently, as shown in FIG. 6C, the packing worker winds around the buffer sheets 8 made of air packing or the like around a plurality of bundled trays, and then puts them in the cardboard box 9. Complete the packing process.

図６（ｂ）に示されるように、従来品のトレーにも形成されているアーム掛け部１ａ（図１に示されているＪＥＤＥＣ規格の半導体集積回路用トレーにおいて、幅が１インチ（約２．５４ｃｍ）であり、深さが０．１インチ（約０．２５４ｃｍ）の凹部）は、半導体集積回路の製造、検品の工程においてロボットアーム等がトレーを掴むときの把持部である。このアーム掛け部１ａとしての凹部は、結束バンド３を掛けたくなる凹状の形状をしているが、昨今の薄型の半導体集積回路用トレーにおいては、アーム掛け部１ａの部分におけるトレー１の厚さが特に薄くて弱いので、このアーム掛け部１ａに結束バンド３を掛けてはいけない。なぜなら、ポリフェニレンエーテル（ＰＰＥ）製のトレーに結束バンドを巻き付ける工程においては、機械を使って約２３ｋｇ重の力を加えながら結束バンドを巻き付けることがあるので、積み重ねられたトレーの中央部付近に力が加わり過ぎてトレー１が撓んでしまい、積み重ねられたトレー間の隙間１０が拡大してしまうからである（図６（ｂ），（ｃ）を参照）。   As shown in FIG. 6 (b), the arm hooking portion 1a formed on the conventional tray (the tray for the semiconductor integrated circuit of JEDEC standard shown in FIG. 1 has a width of 1 inch (about And a recess of 0.1 inch (about 0.254 cm) in depth is a gripping portion when the robot arm or the like grips the tray in the process of manufacturing and inspection of the semiconductor integrated circuit. The recess as the arm hooking portion 1a has a concave shape in which the binding band 3 tends to be hooked, but the thickness of the tray 1 in the portion of the arm hooking portion 1a in the recent thin tray for semiconductor integrated circuits However, the strapping band 3 should not be hooked on the arm hooking portion 1a, since it is particularly thin and weak. Because, in the process of winding the binding band around the tray made of polyphenylene ether (PPE), since the binding band may be wound while applying about 23 kg of force using a machine, the force near the center of the stacked trays Is added to cause the tray 1 to bend, and the gap 10 between the stacked trays is enlarged (see FIGS. 6B and 6C).

これに対して、本発明のトレー１においては、該トレー１の長手方向又は短手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所における上辺及び下辺のうちの少なくとも一辺に沿って、複数の該トレー１を束ねる結束バンドを掛けるための切欠きが形成されていることにより、結束バンドで束ねられたトレー１の撓み（変形）が最小限に抑えられる。従って、落下試験において大きな衝撃を受けたとしても、複数のトレー１間に生じる隙間を最小限に抑えることができるので、トレー１上のＩＣ等が破損しにくい（図７（ｂ）を参照）。   On the other hand, in the tray 1 of the present invention, at least one of the upper side and the lower side at four positions within 3.4 cm from each edge of the two side surfaces extending in the longitudinal direction or the lateral direction of the tray 1 By forming notches along which the binding band for binding the plurality of trays 1 is formed along one side, the deflection (deformation) of the tray 1 bundled with the binding band is minimized. Therefore, even if a large impact is received in the drop test, the gaps formed between the plurality of trays 1 can be minimized, so that the IC and the like on the tray 1 is not easily damaged (see FIG. 7B). .

一実施例においては、外周壁１２の所定の高さの寸法よりも切欠き２の深さの寸法の方が短く形成されていることにより、複数のトレー１が積み重ねられるときに、下段のトレー１の表側面４の外周壁１２の外側に位置する周縁部１３と、上段のトレー１の裏側面５の周縁部とが当接し、上段のトレー１が下段のトレー１の外周壁１２を入れ子状に収容するようにトレー１同士が係合する。加えて、切欠き２の深さが浅く形成されていることにより、切欠き２の位置においてもトレー１の厚さが充分にあるため、結束バンド３を掛けてもトレー１が破損しにくいという利点がある。   In one embodiment, when the plurality of trays 1 are stacked, the depth dimension of the notches 2 is shorter than the predetermined height dimension of the outer peripheral wall 12 so that the lower trays are stacked. The peripheral edge portion 13 located outside the outer peripheral wall 12 of the front side surface 4 of 1 and the peripheral edge portion of the back side surface 5 of the upper tray 1 abut each other, and the upper tray 1 nests the outer peripheral wall 12 of the lower tray 1 The trays 1 engage with each other so as to be accommodated in the shape of a circle. In addition, since the thickness of the tray 1 is sufficient even at the position of the notch 2 because the depth of the notch 2 is formed to be shallow, the tray 1 is difficult to be damaged even when the binding band 3 is hung. There is an advantage.

１…（本発明の）半導体集積回路用トレー
１ａ…アーム掛け部
２…切欠き
２ａ…溝
３…結束バンド
４…表側面
５…裏側面
６…ポケット
６ａ…表ガイド
６ｂ…裏ガイド
７…半導体集積回路部品（ＩＣパッケージ等）
８…緩衝用シート
９…段ボール箱
１０…隙間
１１…インターロック機能部
１２…外周壁
１３…（表側面の）周縁部
DESCRIPTION OF SYMBOLS 1... (Invention) tray for semiconductor integrated circuit 1 a .. arm hanging portion 2 .. notch 2 a .. groove 3 .. binding band 4 .. front side 5 .. back side 6. Integrated circuit parts (IC package etc.)
8: Buffer sheet 9: Corrugated box 10: Gap 11: Interlock function portion 12: Outer peripheral wall 13: (peripheral portion of front surface)

特許文献１に記載の半導体集積回路装置格納用トレイ（１）においては、結束バンドを掛けるための切り欠き（３）が形成されている。しかし、特許文献１の明細書の段落０００８の後段における「切り欠き（３）とその裏側にあるリブ（６）には段差が無いことが好ましい。それにより剛性を更に増すことができる」との記載に基づいて切り欠き（３）の裏側に段差なくリブ（６）が形成されている場合、複数のトレイ（１）が積み重ねられるときに、トレイ（１）の表側面の周縁部と、１つ上段に位置する別個のトレイ（１）の裏側面の周縁部とが当接することなく、トレイ（１）間の周縁部に隙間が生じてしまうことがある（特許文献１の図６等を参照）。この点に関し、特許文献１は、積み重ねられた場合に周縁部どうしが当接するようなトレイにおいて、切り欠きの深さの寸法を表側面の外周壁の高さの寸法よりも短くすることを教示していない。
In the semiconductor integrated circuit device storage tray (1) described in Patent Document 1 , a notch (3) for attaching a binding band is formed. However, as "it is preferable step is not in the ribs (6) with notches and (3) to the back side thereof. Ru can thereby further increase the rigidity" in the subsequent paragraph 0008 of the specification of Patent Document 1 If back in steps without ribs notches based on the described (3) (6) is formed, when a plurality of trays (1) are stacked, a peripheral edge portion of the front surface of the tray (1) A gap may be generated at the peripheral edge between the trays (1) without contact with the peripheral edge of the back side of the separate tray (1) located at the upper row of one (FIG. 6 of Patent Document 1) See etc.). In this regard, Patent Document 1, the tray as each other periphery when stacked abuts, to the dimension of depth away Ri switching shorter than the dimension of the height of the outer peripheral wall of the front face I do not teach.

Claims (2)

平面視で概ね四角形の形状に形成された半導体集積回路用トレーであって、
該半導体集積回路用トレーの表側面の周縁部に沿って該周縁部よりも僅かに内側に、所定の高さを有する外周壁が形成されており、
複数の該半導体集積回路用トレーが積み重ねられるとした場合に上記表側面の周縁部が、上段に位置する別個の該半導体集積回路用トレーの裏側面の周縁部に当接するように構成されている、半導体集積回路用トレーにおいて、
該半導体集積回路用トレーの長手方向に延びている２つの側面又は短手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所のうちの少なくとも１箇所における下辺に沿って、複数の該半導体集積回路用トレーを束ねる結束バンドを掛けるための切欠きが形成されており、
上記外周壁の所定の高さの寸法よりも上記切欠きの深さの寸法の方が短いことを特徴とする、結束バンド用切欠きを有する半導体集積回路用トレー。 It is a tray for semiconductor integrated circuits formed in a substantially square shape in plan view,
An outer peripheral wall having a predetermined height is formed along the periphery of the front side surface of the semiconductor integrated circuit tray and slightly inward of the periphery.
When a plurality of the semiconductor integrated circuit trays are stacked, the peripheral portion of the front side surface is configured to abut the peripheral portion of the back side surface of the separate semiconductor integrated circuit tray located in the upper stage. , In trays for semiconductor integrated circuits,
Along the lower side at at least one of four places within 3.4 cm from the edges of the two longitudinally extending side surfaces or the two laterally extending two side surfaces of the tray for semiconductor integrated circuits And a notch for attaching a binding band for bundling a plurality of the semiconductor integrated circuit trays,
What is claimed is: 1. A tray for a semiconductor integrated circuit, having a tie-band notch, wherein the dimension of the depth of the notch is shorter than the dimension of the predetermined height of the outer peripheral wall. 平面視で概ね四角形の形状に形成された半導体集積回路用トレーであって、
該半導体集積回路用トレーの表側面の周縁部に沿って該周縁部よりも僅かに内側に、所定の高さを有する外周壁が形成されており、
複数の該半導体集積回路用トレーが積み重ねられるとした場合に上記表側面の周縁部が、上段に位置する別個の該半導体集積回路用トレーの裏側面の周縁部に当接するように構成されている、半導体集積回路用トレーにおいて、
該半導体集積回路用トレーの長手方向に延びている２つの側面又は短手方向に延びている２つの側面の各端縁から３．４ｃｍ以内の４箇所のうちの少なくとも１箇所の上方に位置する部分の上記外周壁に沿って、複数の該半導体集積回路用トレーを束ねる結束バンドを掛けるための切欠きが形成されており、
上記外周壁の所定の高さの寸法よりも上記切欠きの深さの寸法の方が短いことを特徴とする、結束バンド用切欠きを有する半導体集積回路用トレー。 It is a tray for semiconductor integrated circuits formed in a substantially square shape in plan view,
An outer peripheral wall having a predetermined height is formed along the periphery of the front side surface of the semiconductor integrated circuit tray and slightly inward of the periphery.
When a plurality of the semiconductor integrated circuit trays are stacked, the peripheral portion of the front side surface is configured to abut the peripheral portion of the back side surface of the separate semiconductor integrated circuit tray located in the upper stage. , In trays for semiconductor integrated circuits,
Located above at least one of four locations within 3.4 cm from the edges of the two longitudinally extending sides or the two laterally extending sides of the tray for semiconductor integrated circuits A notch is formed along a portion of the outer peripheral wall for attaching a binding band for bundling a plurality of the semiconductor integrated circuit trays,
What is claimed is: 1. A tray for a semiconductor integrated circuit, having a tie-band notch, wherein the dimension of the depth of the notch is shorter than the dimension of the predetermined height of the outer peripheral wall.
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CN109592177B (en) 2020-12-25

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