JP2019063185A - Game machine - Google Patents

Abstract

To provide a game machine capable of properly processing inserted game media.SOLUTION: A game machine of the present invention is provided with a standby period for preventing an occurrence of, for example, a "swallow" of medal(s) (tokens) or the like, when a game is started following a start operation of a player. When medals are inserted during the standby period, a start operation that is a reason for the insertion is made invalid. Further, in a game medium detection unit, the inserted medals are returned from a state to be discharged outside the game machine to a state to be stored inside the game machine.SELECTED DRAWING: Figure 121

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachislot having a plurality of reels provided with a plurality of symbols on each surface, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit The machine is known. The start switch detects that the start lever has been operated by the player after game media such as medals and coins have been inserted into the gaming machine (hereinafter also referred to as "start operation"), and all reels are rotated. Output a signal requesting start. The stop switch detects that the player has pressed a stop button provided corresponding to each reel (hereinafter also referred to as “stop operation”), and outputs a signal requesting stop of rotation of the corresponding reel. Do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

  In such a gaming machine, when the start operation is detected, lottery processing using random numbers (hereinafter referred to as "internal lottery processing") is performed on the program, and the result of the lottery (hereinafter referred to as "internal winning combination") Stop the rotation of the reel based on the timing of the stop operation). Then, when the rotation of all the reels is stopped and the combination (display combination) of the symbols related to the establishment of the winning is displayed, a bonus corresponding to the combination of the symbols is given to the player. In addition, as an example of the privilege given to the player, the operation of the re-game (hereinafter, also referred to as "replay") in which the internal lottery process is performed again without paying out the game medium (medal and the like) and consuming the game medium. , Activation of a bonus game, etc., where the payout opportunities for gaming media are increased.

  In addition, in such a gaming machine, a function to notify the procedure of the stop operation which is advantageous for the player so that the probability of establishment of a specific combination (for example, the combination related to the payout of gaming media) is increased, , "AT") has a function. In addition, when a specific condition such as a specific symbol combination is displayed, the game state where the winning probability of replay is higher than normal is activated, that is, the replay time (hereinafter referred to as "RT") Some have functions. In addition, there are some which have a function of assist replay time (hereinafter referred to as "ART") in which AT and RT operate simultaneously.

  Such a game machine usually controls the main game operation of the game machine such as the determination of the internal winning combination, the rotation and stop of each reel, and the start and end of the above AT, RT, or ART ( A production control device (main control circuit) in which the main control circuit is mounted, and an effect control device (sub control circuit) in which the effect control circuit (sub control circuit) for controlling the rendering operation of the gaming machine such as displaying a video is mounted And the control circuit performs control of each of them to control the entire gaming machine.

  Conventionally, in such a gaming machine, when the medals can be accepted and the inserted medal is a proper medal, the inserted medal is counted by the medal sensor and stored inside the gaming machine. Also, if the medals inserted are not appropriate medals even if medals can not be accepted or medals can be accepted, the inserted medals are not counted by the medal sensor, and the game is not played. There is known one provided with a medal sorting device (selector) for being ejected outside the machine (see, for example, Patent Document 1).

  In the medal sorting apparatus (selector) shown in Patent Document 1, when the medals can be received by a member (regulatory guide plate) whose position is shifted by the drive of the solenoid, the inserted medals are used as medal sensors. The player is guided in the first direction to pass through and stored inside the gaming machine, and when the medals can not be received, the inserted medal is not guided in the first direction and is discharged outside the gaming machine. To be guided in a second direction.

JP, 2006-130213, A

  By the way, since the solenoid utilizes magnetic force, it takes some time for excitation and demagnetization. Therefore, depending on the insertion timing of the medal, for example, the inserted medal is counted by the medal sensor because the switching of the guiding direction of the medal is not completed although the medal acceptance is not possible. There is a case where the game is stored inside the gaming machine (that is, the medal "spit-in" occurs).

  If such a situation occurs, not only will the player be given a loss, but also the reliability of the game will be reduced. Therefore, it is desirable to provide a gaming machine capable of properly processing the inserted medals by preventing the generation of the medals such as "spit-in".

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of properly processing inserted gaming media.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following first configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, And state switching means (for example, medal acceptance / start check processing shown in FIGS. 75 and 76) for switching the control state from the receivable state to the unacceptable state when the game start detection unit detects the start operation. ,
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide the following gaming machine of the second configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
Gaming medium counting means (for example, a credit counter) for counting gaming media when the detection unit detects gaming media;
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, A state switching means for switching the control state from the acceptable state to the unacceptable state when the predetermined number (for example, three) of gaming media is inserted and the gaming start detection unit detects the start operation For example, medal reception / start check processing shown in FIGS. 75 and 76),
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
The gaming medium counting means enables counting of gaming media even when the detection unit detects gaming media during the standby process.
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following third configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, And state switching means (for example, medal acceptance / start check processing shown in FIGS. 75 and 76) for switching the control state from the receivable state to the unacceptable state when the game start detection unit detects the start operation. ,
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
The drive unit control means shifts the drive unit from the second drive state to the first drive state when the detection unit detects a game medium during the standby process.
In the predetermined period, the distributing unit guides the game medium in the first direction in response to the drive unit controlling means shifting from the first drive state to the second drive state by the drive unit control means. A game machine characterized by being set to a period equal to or longer than a period from the position until the distribution unit moves to the position for guiding the game medium in the second direction.

  In the gaming machine of the third configuration, the drive unit is a solenoid, the first drive state is a state in which the solenoid is excited, and the second drive state is a demagnetization of the solenoid. A gaming machine characterized by being in a state.

  According to the gaming machine of the first to third configurations, when the game is started along with the player's start operation, for example, the waiting period for preventing the occurrence of the medal "snipping" etc. It is set. By this waiting period, the game medium detection unit secures a time until the inserted medal is physically stored in the gaming machine from being physically discharged to the outside of the gaming machine.

  When the medal is inserted during the standby period, the original start operation is invalidated, and in the gaming medium detection unit, the inserted medal is stored inside the gaming machine. Return to Therefore, it is possible to appropriately process the inserted medals by preventing the occurrence of the "snipping" of the medals and the like.

  Further, according to the gaming machine of the second configuration, even when the medals are inserted during the standby period, the medals are counted, so that the counting omission of the inserted medals is prevented. It is possible to process the inserted medals more appropriately.

  Further, according to the gaming machine of the third configuration, the standby period is longer than a period until the inserted medal is physically stored in the gaming machine and physically discharged from the gaming machine. Since it is set to the period of (1), it becomes possible to prevent the occurrence of "spit-in" etc. of the medals reliably and to process the inserted medals more appropriately. In addition, when a drive part is a solenoid, such an effect becomes more remarkable.

  According to the gaming machine configured as described above, it is possible to provide a gaming machine capable of properly processing the inserted gaming media.

It is a figure for demonstrating the functional flow of the game machine in one Embodiment of this invention. It is a perspective view showing the appearance structure of the game machine in one embodiment of the present invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the structure of the selector with which the game machine of one Embodiment of this invention is equipped. FIG. 1 is a block diagram showing an entire configuration of a circuit included in a game machine according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram showing an internal configuration of a microprocessor in one embodiment of the present invention. It is a block diagram showing an internal configuration of a sub control circuit in an embodiment of the present invention. It is a block diagram of the various registers which the main CPU in one Embodiment of this invention has. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure explaining the security mode of the main control circuit in one embodiment of the present invention. FIG. 7 is a diagram showing a transition flow of the gaming state between the bonus state and the non-bonus state of the pachislot according to the embodiment of the present invention. FIG. 16 is a diagram showing a transition flow of the gaming state between the ART gaming state, the non-ART gaming state, and the bonus state of the gaming machine according to the embodiment of the present invention. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows an example of the reel stop initialization setting table in one Embodiment of this invention. It is a figure which shows an example of the drawing-in priority table in one Embodiment of this invention. It is a figure which shows the structure (the 1) of the hit request flag storage area in one Embodiment of this invention, a prize operation flag storage area. It is a figure which shows the structure (the 2) of the hit request | requirement flag storage area in one Embodiment of this invention, a prize operation flag storage area. It is a figure which shows (the 3) of the hit request | requirement flag storage area in one Embodiment of this invention, and a prize operation flag storage area. It is a figure which shows the structure of the carry-over combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the action | operation stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the correspondence table (the 1) of the internal winning combination and a subflag in one Embodiment of this invention. It is a figure which shows the correspondence table (the 2) of the internal winning combination and a subflag in one Embodiment of this invention. FIG. 17 is a diagram for describing a notification operation when a sub-flag EX “three-in-one chilli lip” or “reach eye lip” is won in the gaming machine of one embodiment of the present invention. It is a figure for demonstrating the flow of the game in the general game state in one Embodiment of this invention. It is a figure which shows an example of the normal middle high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ1 inside mode up lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ2 middle point lottery table in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ1, CZ2) in CZ in one Embodiment of this invention. It is a figure which shows an example of the ART lottery table (for CZ3) in CZ in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in normal ART in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART inside high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table during ART in one Embodiment of this invention. It is a figure which shows an example of a normal ART middle additional lottery table in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in CT state in one Embodiment of this invention. It is a figure which shows an example of the table lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the CT middle addition lottery table in one Embodiment of this invention. It is a figure which shows an example of the number-of-sets during CT top addition lottery table in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the bonus state in one Embodiment of this invention. It is a figure which shows an example of the bonus classification lottery table in one Embodiment of this invention. It is a figure which shows an example of the number ART game number addition bonus lottery table in one Embodiment of this invention. It is a figure which shows an example of CT bonus lottery table at the time of the bonus end in one embodiment of the present invention. It is a figure for demonstrating the flow of a game (others) in the general game state in one Embodiment of this invention. It is a figure which shows an example of the non-ART flag conversion lottery table in one Embodiment of this invention. It is a figure which shows the correspondence of the main side navigation data and sub side navigation data in one Embodiment of this invention. It is a flowchart which shows the example of a process at the time of the power activation (reset interruption) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flow chart which shows an example of game return processing in one embodiment of the present invention. It is a flowchart which shows the example of the setting change confirmation process in one Embodiment of this invention. It is a flow chart which shows an example of setting change command generation storage processing in one embodiment of the present invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of a power-off (external) process in one Embodiment of this invention. It is a flowchart which shows the example of the checksum generation process (outside of prescription | regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the thumb check process (outside of prescription | regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the thumb check process (outside of prescription | regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the main processing (main operation processing) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flow chart which shows an example of medal acceptance / start check processing in one embodiment of the present invention. It is a flow chart which shows an example of medal acceptance / start check processing in one embodiment of the present invention. It is a flow chart which shows an example of medal insertion processing in one embodiment of the present invention. It is a flowchart which shows the example of the medal input check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal input check process in one Embodiment of this invention. It is a flowchart which shows the example of the error processing in one Embodiment of this invention. It is a flow chart which shows an example of random number acquisition processing in one embodiment of the present invention. It is a flowchart which shows the example of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compression data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the control processing according to the state in one Embodiment of this invention. It is a flowchart which shows the example of the subflag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the navi set process in one Embodiment of this invention. It is a flowchart which shows the example of the flag conversion process in one Embodiment of this invention. It is a flow chart which shows an example of processing at the time of the usual middle start in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of CZ start in one embodiment of the present invention. It is a flowchart which shows the example of a process in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of a process in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of a process in CZ3 in one Embodiment of this invention. It is a flow chart which shows an example of processing at the time of start during normal ART in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of start in CT in one embodiment of the present invention. It is a flow chart which shows an example of CT lottery processing during CT in one embodiment of the present invention. It is a flowchart which shows the example of the table data acquisition process in one Embodiment of this invention. It is a flow chart which shows an example of 1 byte lottery processing in one embodiment of the present invention. It is a flow chart which shows an example of processing at the time of BB start in one embodiment of the present invention. It is a flowchart which shows the example of the drawing-in priority storing process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the logical product operation process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing-in priority acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing-in priority acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control processing in one Embodiment of this invention. It is a flow chart which shows an example of winning a prize search processing in one embodiment of the present invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of the prize-winning check / medal payout process in one Embodiment of this invention. It is a flow chart which shows an example of medal number-of-payouts check processing in one embodiment of the present invention. It is a flow chart which shows an example of BB check processing in one embodiment of the present invention. It is a flow chart which shows an example of RT check processing in one embodiment of the present invention. It is a flow chart which shows an example of RT check processing in one embodiment of the present invention. It is a flowchart which shows the example of a CZ * ART end process in one Embodiment of this invention. It is a flowchart which shows the example of the interruption process performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the communication data transmission process in one Embodiment of this invention. It is a flowchart which shows the example of the WDT setting process in one Embodiment of this invention. It is a flow chart which shows an example of 7 segments LED drive processing in one embodiment of the present invention. It is a flow chart which shows an example of 7 segment display data generation processing in one embodiment of the present invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a timing chart which shows an example of operation at the time of power activation of a game machine in one embodiment of the present invention. It is a timing chart which shows an example of operation at the time of medal insertion of a game machine in one embodiment of the present invention.

  Hereinafter, as a gaming machine according to an embodiment of the present invention, a pachislot machine is taken as an example, and the configuration and operation thereof will be described with reference to the drawings. In the present embodiment, a pachislot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, referring to FIG. 1, the functional flow of the pachislot machine will be described. In the pachislot machine of the present embodiment, a medal is used as a game medium for playing a game. In addition to the medals, for example, coins, gaming balls, point data or tokens for gaming may be applied as gaming media.

  When a player inserts a medal into a pachislot and the start lever is operated, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value to determine an internal winning combination. The internal lottery means is one of various processing means (processing functions) provided in a main control circuit described later. By the determination of the internal winning combination, a combination of symbols permitting display along an effective line (winning determination line) described later is determined in advance. The types of combinations of symbols include those related to "winning" in which a player is given a benefit such as payout of medals, activation of replay (replay), activation of bonus, etc. Those concerned are provided. In the following, the role associated with the payout of medals is referred to as a “small role”, and the role associated with the operation of replay (replay) is referred to as a “replay role”. Further, the role associated with the activation of the bonus (bonus game) is also referred to as a "bonus role".

  In addition, when the start lever is operated, rotation of the plurality of reels is performed. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is one of various processing means (processing functions) provided in a main control circuit described later.

  In the pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec) after the stop button is pressed. In the present embodiment, the number of symbols moving with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. Then, in the present embodiment, when the prescribed period is 190 msec, the maximum number of sliding symbols (maximum sliding symbol number) is determined to be four symbols.

  When an internal winning combination that permits combination display of symbols relating to winning is determined, the reel stop control means normally sets the combination of symbols to the effective line within a prescribed time of 190 msec (for four symbols of symbols). Stop rotation of the reel so that it is displayed as much as possible. Also, the reel stop control means uses the specified time to stop the rotation of the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the effective line.

  In this manner, when the rotations of the plurality of reels are all stopped, the prize determination means determines whether or not the combination of the symbols displayed along the activated line relates to a prize. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. Then, if it is determined that the combination of the displayed symbols is related to winning by the prize determining means, a bonus such as payout of medals is given to the player. In the pachislot, a series of such flows as described above are performed as one game (unit game).

  Moreover, in the pachislot, various effects are displayed using the display of an image by a display device, the output of light by various lamps, the output of sound by a speaker, or a combination of these in the flow of the series of game operations described above. Is done.

  Specifically, when the start lever is operated, random numbers for presentation are extracted separately from the random numbers used to determine the internal winning combination described above. When the random number value for effect is extracted, the effect content determination means randomly determines the effect to be executed this time out of a plurality of types of effect content associated with the internal winning combination. The effect content determination means is one of various processing means (processing functions) included in the sub control circuit described later.

  Next, when the effect content is determined by the effect content determining means, the effect executing means responds to each trigger at the start of rotation of the reel, at the time of rotation stop of each reel, at the time of determination of presence or absence of winning, etc. Run. Thus, in pachislot, for example, the opportunity to know or predict the determined internal winning combination (in other words, the combination of the symbols to be aimed at) is played by executing the presentation content corresponding to the internal winning combination. Provided to the player, and the player's interest can be improved.

<Structure of Pachislot>
Next, with reference to FIGS. 2 to 5, the structure of a pachi slot according to an embodiment of the present invention will be described.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi slot 1.

  The pachi slot 1 includes an exterior body (game machine main body) 2 as shown in FIG. The exterior body 2 has a cabinet (chassis) 2a for housing a reel, a circuit board and the like, and a front door (front door) 2b attached so as to be able to open and close the opening of the cabinet 2a.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variation display means, display rows) are arranged in a row. Hereinafter, the respective reels 3L, 3C, 3R (main reels) are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each of the reels 3L, 3C, 3R has a cylindrical reel body and a translucent sheet material mounted on the peripheral surface of the reel body. Then, on the surface of the sheet material, a plurality of (for example, twenty) symbols are drawn at predetermined intervals along the circumferential direction (rotational direction of the reel).

  The front door 2 b includes a door body 9, a front panel 10, a lumbar panel 12, and a pedestal 13. The door body 9 is attached to the cabinet 2a so as to be able to open and close using a hinge (not shown). The hinge is provided at the left side end of the door body 9 as viewed from the front side (player side) of the pachi slot 1.

  The front panel 10 is provided on the top of the door body 9. The front panel 10 is formed of a frame-like member having an opening 10a. The opening 10a of the front panel 10 is closed by a display cover 30, and the display cover 30 is disposed to face a display 11 described later disposed inside the cabinet 2a.

  The display cover 30 is formed of a black translucent synthetic resin. Therefore, the player can visually recognize an image (image) displayed by the display device 11 described later via the display device cover 30. Further, in the present embodiment, by forming the display device cover 30 with a black semitransparent synthetic resin, the entry of external light into the cabinet 2a is suppressed, and an image (image) displayed by the display device 11 is obtained. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21 a and 21 b provided on the top of the front panel 10 as viewed from the player side. Each of the lamps constituting the lamp group 21 is constituted by an LED (Light Emitting Diode) or the like (see the LED group 85 in FIG. 6 described later), and turns on and off the light in a pattern corresponding to the contents of the effect.

  The waist panel 12 is provided substantially at the center of the door body 9. The waist panel 12 has a decorative panel on which an arbitrary image is drawn, and a light source (an LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal 13 is provided between the front panel 10 and the waist panel 12. The pedestal portion 13 includes a symbol display area 4 and various devices to be operated by the player (the medal insertion slot 14, the MAX bet button 15a, the 1 bet button 15b, the start lever 16, three stop buttons 17L, 17C, 17R, a settlement button (not shown), etc. are provided.

  The symbol display area 4 is an area overlapping the three reels 3L, 3C, 3R when viewed from the front, and is disposed at a position closer to the player than the three reels 3L, 3C, 3R. It has a size that makes 3L, 3C, 3R visible. The symbol display area 4 functions as a display window, and is configured to be able to visually recognize the respective reels 3L, 3C, 3R provided behind it. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  The reel display window 4 is, when the rotation of the three reels 3L, 3C, 3R provided behind it is stopped, 3 of the plurality of symbols provided on the circumferential surface of each reel, continuously arranged 3 One symbol is configured to be displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, in the frame of the reel display window 4, one symbol (three in total) in each of the upper, middle and lower areas for each reel Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). In the present embodiment, in the frame of the reel display window 4, a middle line area of the left reel 3L, a middle area of the middle reel 3C, and a pseudo line (center line) connecting the middle area of the right reel 3R It defines as an effective line which determines whether it is a winning or not.

  The reel display window 4 is formed by the opening of the frame member 31 provided on the pedestal portion 13. Further, under the frame member 31 defining the reel display window 4, a pedestal region of a substantially horizontal surface is provided. When viewed from the player side, the medal insertion slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1 bet button 15b are provided on the left side.

  The medal insertion slot 14 is provided to receive a medal dropped from the outside into the pachislot 1 by the player. The medals received from the medal insertion slot 14 are used for one game with a predetermined number (for example, 3) set in advance as the upper limit, and the number of medals exceeding the predetermined number is deposited inside the pachislot 1 (So-called credit function (game media storage means)).

  The MAX bet button 15a and the 1 bet button 15b are provided to determine the number of medals to be used for one game from the medals deposited inside the cabinet 2a. In addition, inside the MAX bet button 15a, a bet button LED (not shown) is provided which lights up when medals can be inserted. Further, the settlement button is provided to pull out (discharge) the medal deposited inside the pachislot 1.

  When the player presses the MAX bet button 15a, medals of the bet number (3 pieces) of the unit game are inserted, and the activated line is activated. On the other hand, one medal is inserted each time the 1-bet button 15 b is pressed once. When the 1-bet button 15b is operated three times, medals of the bet number (3 pieces) of the unit game are inserted, and the activated line is activated.

  Hereinafter, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting medals into the medal insertion slot 14 (operation of inserting medals to play a game) are all referred to as "insertion operations".

  The start lever 16 is provided to start the rotation of all the reels (3L, 3C, 3R). The stop buttons 17L, 17C, 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as the left stop button 17L, the middle stop button 17C, and the right stop button 17R, respectively.

  Further, an information display 6 is provided substantially at the center of the pedestal area of the substantially horizontal surface below the reel display window 4. The information display 6 is covered by a transparent window cover (not shown).

  A two-digit seven-segment LED for digitally displaying (notifying) the player with information on the number of medals (hereinafter referred to as “the number of payouts”) to be paid out to the player as a benefit on the information display 6 Information for the player (hereinafter referred to as “7-segment LED”) and the number of medals deposited inside the pachislot 1 (hereinafter referred to as “number of credits”) is digitally displayed (notified) to the player A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) information on occurrence of errors and error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the payout number of medals switches from the display mode of the payout number to the display mode of the information of the error type.

  Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on stop operation necessary to display the symbol combination according to the combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction indicator) is configured of, for example, a 2-digit 7-segment LED. Then, in the instruction monitor, the two-digit 7-segment LED is turned on, blinks, or is extinguished in a mode uniquely corresponding to the information on the stop operation to notify, thereby notifying the player of the information on the necessary stop operation. Do. That is, for example, in the later-described ART gaming state advantageous for the player, information on stop operation advantageous for the player (see FIG. 24 described later) is notified.

  In this case, the information corresponding to the information on the stop operation to be notified uniquely corresponds to, for example, the case where the push order “1st (performing the first stop operation to the left reel 3L)” is notified. When displaying the numerical value “1” on the instruction monitor and notifying the pushing order “2nd (performing the first stop operation to the middle reel 3C)”, the numerical value “2” is displayed on the instruction monitor, and the pushing order In the case of informing "3rd (performing the first stop operation to the right reel 3R)", it is an aspect such as displaying the numerical value "3" on the instruction monitor.

  The information display 6 is electrically connected to the main control board 71 via the door relay terminal board 68 and the game operation display board 81 as shown in FIG. 6 described later, and the display operation of the information display 6 is mainly It is controlled by the below-mentioned main control circuit 90 in the control board 71. Moreover, the control system of various 7 segment LED mentioned above is dynamic lighting control.

  In addition to the instruction monitor controlled by the main control board 71, the pachi slot 1 of the present embodiment is provided with a configuration for notifying information on the stop operation using other means controlled by the sub control board 72. Specifically, information on the stop operation is notified by a display device 11 described later that is configured by a projector mechanism 211 described later and a display unit 212 (see FIG. 3 and FIG. 6 described later).

  When such a configuration is applied, the mode of notification in the instruction monitor and the mode of notification in the other means controlled by the sub control board 72 may be different from each other. That is, in the instruction monitor, notification may be made in a mode uniquely corresponding to the information of the stop operation to be notified, and it is not necessary to directly notify the information of the stop operation (for example, the numerical value "1" in the instruction monitor Even if is displayed, some players may not be able to specify the notification content, which is not a direct notification). On the other hand, in the notification on the sub side (sub control substrate side) by other means such as the display device 11 described later, the information on the stop operation may be notified directly. For example, when notifying the pushing order "1st", the instruction monitor displays the numerical value "1" that uniquely corresponds to the pushing order notified, but the other means (for example, the display device 11 etc.), the left reel 3L Alternatively, instruction information for causing the first stop operation to be issued may be notified directly.

  In the pachi slot 1 having such a configuration, not only the control of the sub control board 72 but also the control of the main control board 71 can notify the information of the necessary stop operation according to the internal winning combination. Further, the presence or absence of notification of such stop operation information may be controlled in accordance with the gaming state. For example, in the general gaming state (non-ART gaming state) described later, the information on the stopping operation may be notified in the ART gaming state (see FIG. 14 described later) without notifying the information on the stopping operation.

  Also, a sub display 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand vertically from the pedestal region of the substantially horizontal surface of the pedestal portion 13 in the front surface portion of the door main body 9. The sub display device 18 is configured by a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various information.

  Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 6 described later). The touch sensor 19 operates according to a predetermined operation principle such as a capacitance method, and outputs a signal corresponding to the operation as touch input information when the operation of the player is received. And, the pachislot 1 of the present embodiment has a function of making it possible to switch the display of the sub display device 18 according to the operation of the player received via the touch sensor 19 (touch input information output from the touch sensor 19). Have. The sub display device 18 is controlled by a sub control board 72 (see FIG. 6 described later) based on touch input information output from the touch sensor 19.

  In the lower part of the door main body 9, a medal payout port 24, a medal receiving tray 25, two speaker holes 20L, 20R and the like are provided. The medal payout port 24 guides the medals discharged by the driving of a medal payout device 51 described later to the outside. The medal receiver 25 stores the medals discharged from the medal payout opening 24. Further, from the two speaker holes 20L and 20R, sounds such as sound effects and music corresponding to the contents of the effect are output.

[Internal structure]
Next, the internal structure of the pachi slot 1 will be described with reference to FIGS. 3 is a view showing the internal structure of the cabinet 2a, FIG. 4 is a view showing the internal structure of the back side of the front door 2b, and FIG. 5 is a view described later provided on the back side of the front door 2b. It is a figure which shows the structure of the selector 66. FIG.

  As shown in FIG. 3, the cabinet 2a has a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. And the display apparatus 11 is arrange | positioned by the upper part in the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection target member 212 a onto which the image light projected from the projector mechanism 211 is projected, and performs image display by projection mapping. Specifically, in the display device 11, video light is generated based on the position (projection distance, angle, etc.) and shape of the projection target member 212a to be a three-dimensional object, and the video light is projected by the projector mechanism 211. It is projected on the surface of 212a. By providing such a rendering function, sophisticated and powerful rendering can be performed. Further, although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and either projected member is provided depending on the gaming state. , It is used as a screen on which image light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the projection target members in accordance with the game state.

  A medal payout device (hereinafter, referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply 53 are disposed at a lower portion in the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large amount of medals and discharging them one by one. The hopper device 51 pays out the medals, for example, when the stored medals exceed 50, or when the settlement button is pressed and the settlement of the medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout opening 24 (see FIG. 2).

  The medal auxiliary storage 52 stores the medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. Moreover, the medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 has a power switch 53a and a power supply substrate 53b (power supply means) (see FIG. 6 described later). The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the power of the AC voltage 100 V supplied from the sub power supply device (not shown) into the power of the DC voltage required by each part, and supplies the converted power to each part.

  Further, above the power supply device 53 in the cabinet 2a, a sub control board case 57 for accommodating a sub control board 72 (see FIG. 6 described later) is disposed. A sub control circuit 200 described later (see FIG. 9 described later) is mounted on the sub control substrate 72 housed in the sub control substrate case 57. The sub control circuit 200 is a circuit that controls execution of effects by displaying a video or the like. The specific configuration of the sub control circuit 200 will be described later.

  The sub relay board 61 is disposed above the sub control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which a wire connecting the sub control board 72 and a main control board 71 described later is mounted. Further, the sub relay board 61 is a relay board on which a wire for connecting the sub control board 72 and a board provided around the sub control board 72, various device units (units), and the like is mounted.

  Although not shown in FIG. 3, a cabinet side relay board 44 (see FIG. 6 described later) is disposed in the cabinet 2a. The cabinet side relay board 44 includes a main control board 71 (see FIG. 6 described later), a hopper device 51, a medal auxiliary storage switch 75 (see FIG. 6 described later), and a medal payout count switch (not shown). Is a relay board on which a wire for connecting is mounted.

  As shown in FIG. 4, a middle door 41 is disposed at the center on the back side of the front door 2b, and the reel display window 4 (see FIG. 2) is attached so as to be able to be opened and closed from the back. Although not shown in FIG. 4, three reels 3L, 3C, 3R are attached to the reel display window 4 side of the middle door 41, and the main control is performed on the side opposite to the reel display window 4 side of the middle door 41. A main control board case 55 in which a board 71 (see FIG. 6 described later) is accommodated is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, 3R via a gear having a predetermined speed reduction ratio.

  The main control board 71 housed in the main control board case 55 has a main control circuit 90 (see FIGS. 7 and 8 described later) described later. The main control circuit 90 (main control means) is a circuit for controlling the main flow of the game in the pachislot 1 such as determination of the internal winning combination, rotation and stop of each reel 3L, 3C, 3R, and determination of presence or absence of winning. . Further, in the present embodiment, the main control circuit 90 also performs control of, for example, lottery processing of determination of ART, display processing of navigation information to an instruction monitor, transmission processing of various test signals, and the like. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back side of the front door 2b. The speakers 65L and 65R are disposed at positions facing the speaker holes 20L and 20R (see FIG. 2).

  Further, a selector 66 and a door open / close monitoring switch 67 are disposed above the speaker 65L. The selector 66 is a device for detecting medals inserted into the medal insertion slot 14 and is a device for selecting whether or not the inserted medals are appropriate medals, and is classified as appropriate medals In this case, the medal is guided to the hopper device 51 side and driven so as to be accommodated in the hopper device 51, and when it is determined that the medal is not a proper medal, the medal is moved to the medal payout port 24 side. And driven so as to be discharged from the medal payout opening 24. That is, the selector 66 is also a device for distributing the medals inserted into the medal insertion slot 14 to the hopper device 51 side or the medal payout port 24 side.

  As shown in FIG. 5, the selector 66 has a base 803 provided with a medal rail (medal passage) 802 through which the medal passes, and a select plate for guiding the inserted medal to the hopper device 51 side or the medal payout port 24 side. 804, a medal pusher 805 for pushing the medal to the medal payout opening 24 side when the inserted medal is not a proper medal, an upstream medal sensor for detecting the inserted medal on the upstream side of the medal rail 802 (first A medal sensor) 806 and a downstream medal sensor (second medal sensor) 807 for detecting the inserted medal on the downstream side of the medal rail 802.

  Further, although not shown in FIG. 5, the selector 66 has a medal guide (that forms a flow path of medals from the selector 66 to the hopper device 51 when the medals are guided to the hopper device 51 by the select plate 804) (Not shown) and a cancel chute (not shown) for forming a flow path of the medal from the selector 66 to the medal payout opening 24 when the medal is placed on the medal payout opening 24 side by the select plate 804 is detachable It is attached.

  The select plate 804 is driven by a solenoid (not shown) included in the selector 66. The select plate 804 moves the guiding medal to a guiding position for guiding the passing medal to the hopper device 51 side when the solenoid is driving, but does not guide the passing medal to the hopper device 51 side when the solenoid is not driving. It moves to the discharge position (that is, it guides to the medal payout opening 24 side). Specifically, when the solenoid is driven, the select plate 804 moves toward the rear side of the pachi slot 1 to guide the upper side of the medal, while when the solenoid is not driven, the select plate 804 is pochi slot 1 It moves in the forward direction so as not to guide the upper side of the medal. In addition, the guide method of the medal | token by the select plate 804 is not restricted to this, For example, the movement of a guide position and a discharge position is enabled by setting it as the mechanism which can move to the up-down direction of pachislot 1 May be That is, the select plate 804 is moved by the solenoid or other drive source to a guide position on the medal rail 802 that does not prevent the passing medal from moving to the hopper device 51 side, and the passing medal to the hopper device 51 side Any mechanism can be adopted as long as it is a mechanism that is capable of shifting between the discharge position where it is guided to the medal payout opening 24 side and the movement thereof is prevented.

  For example, when the select plate 804 is moved to the guide position, the medal pusher 805 operates so as not to protrude in the rear direction of the pachi slot 1 and the select plate 804 is not moved to the guide position In the case of moving to the rear side of the pachi slot 1). That is, when the medal pusher 805 is at a position where it does not protrude in the rear side direction of the pachi slot 1, it becomes a guide position for guiding the passing medal to the hopper device 51 side, and when in a position where it protrudes in the rear side direction of the pachi slot 1. The passing medal is not guided to the side of the hopper device 51 (i.e., guided to the side of the medal payout opening 24), which is a discharge position.

  The upstream medal sensor 806 and the downstream medal sensor 807 constitute gaming medium detection means for detecting that the medal has passed. Each medal sensor is, for example, a reflection type sensor including a pair or a plurality of pairs of light emitting elements and light receiving elements, and the light emitting elements emit light to the medals and reflected light reflected from the medals When the light receiving element receives light, passage of the medal is detected. The configuration of the sensor can be changed as appropriate, and, for example, a transmission sensor or the like can be employed. Further, the passage of the medal may be detected only by the downstream side medal sensor 807 without providing the upstream side medal sensor 806. Moreover, the specific control based on the detection result (the medal sensor input state) of each medal sensor will be described later.

  The door open / close monitoring switch 67 is disposed obliquely downward to the left of the selector 66 when the front door 2 b is viewed from the back side. The door opening and closing monitoring switch 67 outputs a security signal for notifying the opening and closing of the front door 2 b to the outside of the pachi slot 1.

  Further, although not shown in FIG. 4, a door relay terminal plate 68 is disposed on the back of the front door 2b at the back side and in the area opened and closed by the middle door 41 and below the reel display window 4 (see FIG. 6). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a test machine, and the like. It is a relay board on which the wiring which connects with each of the second interface board 302 for a tester is mounted. Examples of the various buttons and switches include a MAX bet button 15a, a 1 bet button 15b, a door open / close monitoring switch 67, a bet switch 77 described later, and a start switch 79.

<Control system equipped with Pachislot>
Next, a control system included in the pachi slot 1 will be described with reference to FIG. FIG. 6 is a circuit block diagram showing a configuration of a control system of pachi-slot 1.

  The pachi slot 1 has a main control board 71 provided on the middle door 41 and a sub control board 72 provided on the front door 2b. The pachi slot 1 also has a reel relay terminal board 74, a setting key type switch 54 (setting switch) and a cabinet side relay board 44 connected to the main control board 71. Furthermore, the pachi slot 1 has an external concentrated terminal board 47 connected to the main control board 71 via the cabinet side relay board 44, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76 and a power supply device 53. In addition, since it mentioned above about the structure of the hopper apparatus 51, the description is abbreviate | omitted here.

  The reel relay terminal board 74 is disposed inside the reel body of each of the reels 3L, 3C, 3R. The reel relay terminal board 74 is electrically connected to stepping motors (not shown) of the respective reels 3L, 3C, 3R, and relays signals outputted from the main control board 71 to the stepping motors.

  The setting key type switch 54 is provided on the main control board case 55. The setting key type switch 54 is used when changing the setting value (setting 1 to setting 6) of the pachislot 1 or confirming the setting of the pachislot 1. The setting value indicates the degree of advantage of the player regarding the game, and generally, the lower the setting value (for example, the closer to setting 1), the relatively lower the degree of advantage of the player. The higher the setting value (eg, the closer to setting 6), the higher the degree of advantage of the player. In the present embodiment, the higher the set value, the higher the winning probability of the bonus combination described later can be made to change the degree of advantage of the player, and the higher the set value, the more ART or CT described later. It is also possible to change the degree of advantage of the player by increasing the probability of winning such a lottery.

  The cabinet side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external concentrated terminal plate 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. It is. The external concentrated terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachi-slot 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52, and detects whether the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachi slot 1.

  The power supply device 53 includes a power supply substrate 53 b and a power switch 53 a connected to the power supply substrate 53 b. The power switch 53 a is pressed to supply the necessary power to the pachi slot 1. The power supply substrate 53 b is connected to the main control substrate 71 via the cabinet side relay substrate 44, and is also connected to the sub control substrate 72 via the sub relay substrate 61.

  The pachi slot 1 is connected to the main control board 71 via the door relay terminal board 68 and the door relay terminal board 68, the selector 66, the door open / close monitoring switch 67, the BET switch 77, the settlement switch 78, It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub relay board 61, a first interface board for testing machine 301, and a second interface board for testing machine 302. Since the selector 66, the door open / close monitoring switch 67, and the sub relay board 61 have been described above, the description thereof is omitted here.

  The BET switch 77 (input operation detection means) detects that the MAX bet button 15a or the 1 bet button 15b has been pressed by the player. The settlement switch 78 detects that the settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detection means) detects that the player has operated the start lever 16 (start operation).

  The stop switch substrate 80 (stop operation detection means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stopable main reel by an LED or the like. In addition, the stop switch substrate 80 is provided with a stop switch (not shown). The stop switch detects that each stop button 17L, 17C, 17R has been pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. For example, three LEDs for displaying the number of inserted medals (hereinafter referred to as “first LED” to “the first LED”) are lighted corresponding to the number of medals inserted in the current game (hereinafter referred to as “inserted number”). Based on the signal input from the game operation display board 81), a mark indicating that the medal can be inserted, a mark indicating the start of the game, an LED to light the mark for performing the replay, etc. And so on. In the first to third LEDs (display means), when one medal is inserted, the first LED is turned on, and when two medals are inserted, the first and second LEDs are turned on, and three medals (game When the startable number of cards is inserted, the first to third LEDs light up. In addition, about the information display 6, since it mentioned above, those description is abbreviate | omitted.

  Both the first interface board for testing machine 301 and the second interface board for testing machine 302 are relay boards used when outputting various signals relating to the game to the testing machine in the verification test (test shooting test) of the pachislot 1 ( Since these relay boards are not mounted on the pachislot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for testing machine and the testing machine. The various electronic components required to connect to the second interface board 302 are also not mounted). For example, a test signal for controlling a main operation related to a game (for example, internal lottery, reel stop control, etc.) is output through the first interface board 301 for a test machine, and is determined by the main control board 71, for example. A test signal or the like relating to the push order navigation performed is output via the second interface board 302 for a tester.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. The pachi slot 1 also has a speaker group 84, an LED group 85, a 24 h door open / close monitoring unit 63, a touch sensor 19, and a display unit 212 connected to the sub control board 72 via the sub relay board 61. In addition, since the touch sensor 19 has been described above, the description thereof is omitted here.

  The speaker group 84 is configured to include the speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source for emitting light for illuminating the decorative panel of the waist panel 12 from the back side, and the like. The 24 h door opening and closing monitoring unit 63 stores history information of the opening and closing of the middle door 41. Further, when the middle door 41 is opened, the 24 h door opening / closing monitoring unit 63 outputs a signal for performing an error display by the display device 11 to the sub control board 72 (sub control circuit 200). The display unit 212 includes, for example, a projection target member 212a constituting the display device 11, and another projection target member having a curved display surface provided on the back side of the projection target member 212a.

  The pachi slot 1 also includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub control substrate 72. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are accommodated in the sub control substrate case 57 together with the sub control substrate 72.

  The ROM cartridge substrate 86 is a substrate for managing various control programs to be executed by the sub CPU 201, and images (videos) for presentation, audio (speaker group 84), light (LED group 85), and communication data. . The liquid crystal relay substrate 87 is a substrate that relays connection wiring between the sub control substrate 72, the projector mechanism 211 that constitutes the display device 11, and the sub display device 18. The projector mechanism 211 and the sub display device 18 have been described above, and thus the description thereof is omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 7 is a block diagram showing a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 functions as a game control unit for controlling a game operation, and includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

  The microprocessor 91 is a microprocessor with a security function for a gaming machine. In the microprocessor 91 of the present embodiment, various instruction codes (hereinafter referred to as "main CPU 101 dedicated instruction code") specific to the microprocessor 91 that can be defined on a program are provided. In the present embodiment, by using the main CPU 101 dedicated instruction code, processing efficiency, program capacity reduction, and the like are realized. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 8 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by the main control circuit described later. Do.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

  The power supply management circuit 93 manages fluctuations in the power supply voltage of DC 12 V supplied from the power supply substrate 53b (see FIG. 6). Then, the power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the start voltage value (10 V) from 0 V). When a power failure occurs (when the power supply voltage falls from 12 V to a power failure voltage value (10.5 V)), a power failure detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (start signal) to the microprocessor 91 when the power is turned on (starting means), and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as means for outputting (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of 5 V DC) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, an internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 8 is a block diagram showing an internal configuration of the microprocessor 91. As shown in FIG.

  The microprocessor 91 includes a main CPU 101 (arithmetic processing unit), a main ROM 102 (first storage unit), a main RAM 103 (second storage unit), an external bus interface 104, a clock circuit 105, and a reset controller 106. The arithmetic circuit 107, the random number circuit 110, the parallel port 111, the interrupt controller 112, the timer circuit 113, the first serial communication circuit 114, and the second serial communication circuit 115 are included. The components constituting the microprocessor 91 are connected to one another via a signal bus 116.

  The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 to perform control related to the entire game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  The main CPU 101 counts the number of times the pulse is output to the stepping motor of each reel 3L, 3C, 3L (main reel) after detecting the reel index. Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many reels the symbol has rotated). The reel index is information indicating that the reel has made one rotation. The reel index includes, for example, an optical sensor having a light emitting portion and a light receiving portion, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting portion and the light receiving portion by rotation of each main reel. It is detected by the provided reel position detection unit (not shown).

  Here, management of the rotation angles of the respective reels 3L, 3C, 3L (main reels) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the pulse counter counts the output of a predetermined number of pulses necessary for the rotation of one symbol, the symbol counter provided in the main RAM 103 is incremented by one. A symbol counter is provided for each reel. The value of the symbol counter is cleared when a reel index is detected by a reel position detection unit (not shown).

  That is, in this embodiment, by managing the symbol counter, it is managed how many symbol rotations have been performed since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control instructions (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by the execution of the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG. 11 described later.

  The external bus interface 104 electrically connects the microprocessor 91 to an external signal bus (not shown) to which various components (for example, respective reels and the like) provided outside the microprocessor 91 are connected. It is an interface circuit. The clock circuit 105 includes, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is divided into other components (for example, timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or a WDT (watchdog timer) based on a reset signal input from the power management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when executing a "MUL (multiplication)" instruction on a program, the arithmetic circuit 107 executes multiplication processing based on this "MUL" instruction.

  The random number circuit 110 generates a random number (for example, 0 to 65535 or 0 to 255) within a predetermined range. Although not shown, the random number circuit 110 includes a random number register 0 for obtaining a 2-byte hard latch random number, a random number register 1 to 3 for obtaining a 2-byte soft latch random number, and a 1 byte soft latch random number. It consists of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from the random numbers in the predetermined range generated by the random number circuit 110 as, for example, a random number value for internal lottery. The parallel port 111 is a port (memory map I / O) of a signal input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93 etc.) provided outside the microprocessor 91. . The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is also connected to any input port of PI0 to PI4 of the parallel port 111, and is latched from the parallel port 111 to the random number register 0 of the random number circuit 110 at the timing (on edge) when the start switch 79 is turned on. A signal is output. Then, in the random number circuit 110, the random number register 0 is latched by inputting the latch signal, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs interrupt processing by the main CPU 101 based on the power failure detection signal input from the power management circuit 93 via the parallel port 111 or the time-out signal input from the timer circuit 113 in a cycle of 1.172 ms. Control the execution timing of When a power failure detection signal is input from the power supply management circuit 93, or when a time-out signal is input from the timer circuit 113, the interrupt controller 112 generates an interrupt request signal indicating an interrupt processing start command as the main CPU 101. Output to The main CPU 101 performs input port check processing, reel control processing, communication data transmission processing, 7 segment LED driving processing, timer based on an interrupt request signal input from the interrupt controller 112 in response to a time out signal from the timer circuit 113. Various interrupt processing such as update processing (see FIG. 114 described later) is performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal (clock pulse signal of a frequency obtained by dividing the clock pulse signal for operating the main CPU by a divider (not shown)) generated by the clock circuit 105 (a clock pulse signal). Count elapsed time). Then, the timer circuit 113 outputs a time-out signal (trigger signal) to the interrupt controller 112 in a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when transmitting data (various control commands (commands)) from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls the serial transmission operation when transmitting data from the main control board 71 to the second interface board 302 for a tester.

<Sub control circuit>
Next, with reference to FIG. 9, the configuration of the sub control circuit 200 (sub control means) mounted on the sub control substrate 72 will be described. FIG. 9 is a block diagram showing a configuration example of the sub control circuit 200 of the pachislot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of effects based on commands transmitted from the main control circuit 90. The sub control circuit 200 functions as an effect control unit that controls an effect operation, and basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge substrate 86. The driver 205 is connected to the liquid crystal relay substrate 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  The program storage area stores a control program to be executed by the sub CPU 201. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random value for effect are extracted, and effect registration (render data) is determined and registered. It contains various programs for performing tasks. Further, the control program includes a drawing control task for controlling the display of an image by the display device 11 based on the determined effect contents, a lamp control task for controlling light output by a light source such as the LED group 85, and a sound by the speaker group 84. Also included are various programs for executing a voice control task that controls the output of

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data relating to creation of a video. The data storage area also includes a storage area for storing sound data relating to BGM and sound effects, and a storage area for storing lamp data relating to a light on / off pattern.

  The sub RAM 202 is provided with a storage area for registering the determined effect content and presentation data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create an image according to the animation data specified by the effect contents, and the created image is displayed on the display device 11 (projector mechanism 211) Alternatively, it is displayed on the sub display 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM in accordance with the sound data designated by the contents of the effect. Further, the sub CPU 201 controls lighting and extinguishing of the LED group 85 in accordance with the lamp data designated by the contents of the effect.

<Various registers of the main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. FIG. 10 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 includes, as main registers, an accumulator A (hereinafter referred to as "A register"), a flag register F (flag register), a general purpose register B (hereinafter referred to as "B register"), and a general purpose register C (hereinafter referred to C register), general purpose register D (hereinafter referred to as "D register"), general purpose register E (hereinafter referred to as "E register"), general purpose register H (hereinafter referred to as "H register") and general purpose register L (hereinafter referred to , “L register”). The main CPU 101 also includes an accumulator A ′, a flag register F ′, a general purpose register B ′, a general purpose register C ′, a general purpose register D ′, a general purpose register E ′, a general purpose register H ′ and a general purpose register L ′ as sub registers. As a general purpose register. Each register is composed of a 1-byte register.

  Further, in the present embodiment, the B register and the C register are used as a pair register (hereinafter, referred to as "BC register"), and the D register and the E register are used as a pair register (hereinafter, referred to as "DE register"). Furthermore, in the present embodiment, the H register and the L register are used as a pair register (hereinafter referred to as "HL register").

  As shown in FIG. 10, predetermined flag information indicating the result of the arithmetic processing is set in each bit of the flag register F, F '. For example, data (zero flag) indicating whether the operation result is “0” in the determination processing of the operation result is set in bit 6 (D6). Specifically, when the operation result is "0", data "1" is set to bit 6, and when the operation result is not "0", data "0" is set to bit 6. Then, in the determination processing of the calculation result, the main CPU 101 performs determination (YES / NO) with reference to data “0” / “1” of bit 6.

  Further, the main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is configured of a 1-byte register. In the present embodiment, as will be described in the various processing flows to be described later, various main CPU 101 dedicated instruction codes for specifying addresses using this Q register are provided in the program. By the use, the processing efficiency and the capacity reduction of the main ROM 102 are realized. Note that, in various main CPU 101 dedicated instruction codes that perform addressing using the Q register, the Q register stores address data (address value) on the upper side of the address. Note that “F0H” is set in the Q register as an initial value immediately after the main CPU 101 is reset. Also, in the “LDQ, n (8-bit data)” instruction using the Q register, change the value of the Q register by setting an arbitrary 1-byte data to “n” and executing the instruction. Can.

  Furthermore, the main CPU 101 includes an interrupt page address register I and a memory refresh register R, which are configured by 1-byte registers, and an index register IX, an index register IY, which is configured by 2-byte registers. , A stack pointer SP and a program counter PC as dedicated registers.

<Internal Configuration of Main ROM and Main RAM (Memory Map)>
Next, with reference to FIGS. 11A to 11C, an internal configuration (hereinafter referred to as a “memory map”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described. 11A is a view showing a memory map of the entire memory, FIG. 11B is a view showing a memory map of the main ROM 102, and FIG. 11C is a view showing a memory map of the main RAM 103.

  In the memory map of the entire memory provided in the main control circuit 90 (microprocessor 91), as shown in FIG. 11A, from the top (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, The XCS decode areas are arranged at predetermined addresses in this order with non-use areas in between.

  In the memory map of the main ROM 102, as shown in FIG. 11B, the program area, the data area, the non-regulation area, the trademark recording area, the program management area and the security setting area are from the head (0000H) side of the address of the main ROM 102. In order, each is arranged at a predetermined address.

  In the program area, control programs of various processes to be executed by the main CPU 101 are stored in various control processes related to the playability of the game performed by the player. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, various data for the sub control circuit 200, and the like) in various control processes related to game playability implemented by the player. Data etc. for transmitting a control command (command) are stored. That is, in the gaming ROM area (game storage area) consisting of the program area and the data area, it is necessary for the control processing (processing related to the game property) related to the game property of the game actually played by the player in the game shop. Various programs and various data are stored.

  In addition, control programs and data of various processes (processes that do not affect the game property) that do not directly participate in the game property of the game performed by the player are stored in the non-regulation area. For example, programs and data used in pachislot 1 verification test (test injection test), control programs and data used in checksum generation processing at power failure, sum check processing at power recovery, etc., and anti-corruption program And the data etc. required for it are stored in the non-prescribed area.

  The program management area and the security setting area store various settings and management information regarding execution of the control program or security function. For example, setting and management information of start address and end address (that is, data range) of control program stored in the program area, setting and management information of address number of readable RAM area, reset setting and management information of WDT, Interrupt setting and management information, setting of permission / non-permission setting and management information of reading of control program stored in program area, setting and management information regarding activation of random number circuit 110, update method, etc., and setting of security mode described later The management information and the like are stored in the program management area and the security setting area. In the present embodiment, other settings and management information not related to the security function are stored in the program management area, and settings and management information related to the security function are stored in the security setting area. For example, the setting and management information may be stored as a single management area.

  In the memory map of the main RAM 103, as shown in FIG. 11C, from the top (F000H) side of the address of the main RAM 103, a gaming RAM area (predetermined storage area, gaming temporary storage area) and non-prescribed RAM area (non-prescribed temporary) Storage areas are arranged in this order at predetermined addresses.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the playability of the game performed by the player. . Then, each of the various data is stored in a work area of a predetermined address in the gaming RAM area.

  In the non-regulation RAM area, a non-regulation work area, which is a working area for various processes not directly involved in the gameplay of the game played by the player, and a non-regulation stack are provided. In the present embodiment, various processes that do not directly participate in the playability of the game performed by the player, such as a thumb check process, are executed using this non-specified RAM area.

  As described above, in the Pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes not directly involved in the playability of the game performed by the player in the main ROM 102 It is stored in a non-specified ROM area (non-specified storage area) arranged at an address different from the ROM area. In addition, various processes that do not directly participate in the playability of the game performed by such a player are performed in the main RAM 103 using a non-specified RAM area arranged at an address different from the game RAM area. .

  With such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are placed in the ROM area (non-specified ROM area) where the placement of programs and the like was not possible according to the conventional rules. can do. Therefore, in the present embodiment, compression of the capacity of the gaming ROM area can be avoided.

<Security mode>
Next, referring to FIG. 12, a security mode which is a part of the security function of the main control circuit 90 (microprocessor 91) will be described. FIG. 12 is a diagram for explaining the security mode.

  In the security mode, for example, when the power of the pachi slot 1 is turned on and a reset signal is input from the power management circuit 93, the microprocessor 91 operates. During this security mode, the activation of the main CPU 101 is delayed for a period corresponding to the setting stored in the security setting area (that is, execution of power-on processing (see FIG. 64 described later) is started by the main CPU 101). Delay). When the main CPU 101 is activated through this security mode, the security of the microprocessor 91 is secured, and a time necessary for activation control at power on is secured to activate the main CPU 101 stably.

  In the present embodiment, for example, the reset controller 106 can delay the start of the main CPU 101 by delaying the reset signal input at the time of power on for a predetermined period, or the interrupt controller 112 can It is also possible to delay the activation of the main CPU 101 by delaying the interrupt permission of the reset interrupt process (see FIG. 64 described later) at the time of power-on for a predetermined period. Further, each controller may cooperate to delay the activation of the main CPU 101. Further, for example, a delay circuit can be provided in the microprocessor 91 (or in the reset controller 106 or the interrupt controller 112), and the activation of the main CPU 101 can be delayed by this delay circuit. That is, the configuration (security unit) for executing the security function in the microprocessor 91 can be appropriately modified and applied according to the specification.

  As shown in FIG. 12, as the delay period in the security mode, a fixed extension time (fixed period) and a random extension time (variable period) can be set. In the present embodiment, for example, one of the plurality of fixed extension times is fixedly extended by selecting and setting one of the modes 1 to 8 in which different fixed extension times are associated with each other. A range of a plurality of random extension times can be set by selecting and setting one of the modes 1 to 4 in which the time can be set and the range of different random extension times is associated with each other. The range of one random extension time can be set from inside.

  For example, when “mode 4” is selected as the fixed extension time and “mode 4” is selected as the random extension time, and these settings are stored in the security setting area, the microprocessor 91 turns on the pachislot 1 power supply, When the reset signal is input from the power management circuit 93, first, the start of the main CPU 101 is delayed for about 4 seconds (4000 ms) as a fixed extension time, and then out of the range of 0 to 500 ms as a random extension time One extension time is randomly selected, and the start of the main CPU 101 is delayed for the selected time.

  Although the range of the fixed extension time and the random extension time can be set appropriately, in the present embodiment, the range of the random extension time is set from the viewpoint of shortening the time until the setting change becomes possible when the pachislot 1 is powered on. It is desirable to set "mode 1" in which the random extension time is always "0".

<Transition flow of gaming state>
Next, with reference to FIG. 13 and FIG. 14, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachislot 1 of the present embodiment and the transition flow thereof will be described. FIG. 13A is a transition flow diagram of the basic gaming state of the pachislot 1 and FIG. 13B is a table summarizing transition conditions of the gaming state. Also, FIG. 14A is a transition flow diagram of the gaming state in consideration of the presence / absence of operation of the notification (ART) function, and FIG. 14B is a table summarizing transition conditions of the gaming state.

[Basic game state transition flow]
In the Pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") is provided as a type of bonus game. BB is a character continuously operating device according to a regular bonus (hereinafter referred to as "RB") called a first kind special character, and operates RB continuously.

  Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on the presence / absence (winning) of the bonus combination. Specifically, as shown in FIG. 13A, the main control circuit 90 sets “Bon” based on the presence / absence (winning) of the bonus role (internal winning combination of names “F_BB1” and “F_BB2” described later). It manages three types of gaming states called "bonus not won state", "inter-flag state" and "bonus state".

  The bonus non-winning state is a state in which the bonus is not won and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, a state occurs in which the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, a state in which the bonus combination is won and the bonus is not activated.

  It should be noted that the presence or absence of winning a bonus combination is determined by data stored in a hit request flag storage area (see FIGS. 28 to 30 described later) and a carryover combination storage area (see FIG. 31 described later) provided in the main RAM 103. Managed based on. Further, the presence or absence of a bonus operation (winning) is managed based on data stored in a later-described game state flag storage area (see FIG. 32 described later) provided in the main RAM 103.

  Further, in the present embodiment, as shown in FIG. 13A, the types of internal winning combinations related to replay and the winning probability thereof differ from each other in the gaming state in which the bonus is not activated (bonus not winning state and state between flags). Six types of states (hereinafter referred to as “RT0 state” to “RT5 state”, respectively) of RT0 gaming state to RT5 gaming state are provided. The RT0 state, the RT2 state, and the RT5 state are gaming states in which the probability that a replay combination is determined as an internal winning combination is low, and the RT1 state is a moderate probability that a replay combination is determined as an internal winning combination It is a game state that becomes a middle probability. The RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is any one of the RT0 state to the RT4 state, and the RT state in the inter-flag state is the RT5 state.

  Therefore, in the present embodiment, in the gaming state in which the bonus is not activated (bonus not won state and the state between the flags), the main control circuit 90 is further based on the type of internal winning combination related to replay and its winning probability. It also manages six types of states, RT1 state to RT5 state.

  The RT0 state to the RT5 state are managed based on data stored in a later-described game state flag storage area (see FIG. 32 described later) provided in the main RAM 103. Specifically, in the pachislot 1 of the present embodiment, the RT1 status flag to the RT5 status flag are provided with five flags indicating the RT status, and the on / off status of these flags is managed by the main RAM 103 to be an RT status. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag in the on state as the current RT state. When all RT state flags are in the off state, the main control circuit 90 specifies that the current RT state is the RT0 state.

  As shown in FIGS. 13A and 13B, when a bonus combination (internal winning combination of names “F_BB1” and “F_BB2” described later) is determined as an internal winning combination under bonus non-winning condition (transition condition (1) is satisfied) The main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. When the bonus combination is won in the inter-flag state (when the transition condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

  In the bonus state, when the medal exceeding the prescribed number (216 sheets) is paid out and the bonus state ends (when the transition condition (3) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the RT1 state ( Transition to bonus non winning condition).

  In the RT1 state, when 20 games have passed (transition condition (4) is satisfied), the main control circuit 90 shifts the gaming state from the RT1 state to the RT0 state. Also, in the RT1 state, when the symbol combination (see FIG. 28 described later) relating to the abbreviation “bell spill” is displayed on the effective line before the elapse of 20 games (when the transition condition (5) is satisfied) The main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

  In the RT0 state, when the symbol combination relating to the abbreviation “bell spilled eye” is displayed on the activated line (transition condition (5) is satisfied), the main control circuit 90 shifts the gaming state from the RT0 state to the RT2 state Let In the RT2 state, when the symbol combination (see FIG. 28 described later) relating to the abbreviation “RT3 transition lip” is displayed on the activated line (when the transition condition (6) is satisfied), the main control circuit 90 performs the gaming state Transition from RT2 state to RT3 state.

  In the RT3 state, when the symbol combination (see FIG. 28 described later) relating to the abbreviation “RT4 transition lip” is displayed on the activated line (when the transition condition (7) is satisfied), the main control circuit 90 performs the gaming state Transition from RT3 state to RT4 state. Also, in the RT3 state, when the symbol combination (see FIG. 28 described later) related to the abbreviation “bell spilled eye” or “RT2 transition lip” is displayed on the effective line (when the transition condition (8) is satisfied), the main The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Furthermore, in the RT4 state, when the symbol combination relating to the abbreviation “bell spilled eye” or “RT2 transition ripple” is displayed on the effective line (when the transition condition (8) is satisfied), the main control circuit 90 performs the gaming state The gaming state is shifted from the RT4 state to the RT2 state.

  In addition, the internal winning combination (small part) according to the name “F_3 alternative bell_1st”, “F_3 alternative bell_2nd” or “F_3 alternative bell_3rd” is determined for the symbol combination relating to the abbreviation “bell spilled eyes”, And, it is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the pushing order determined for each type of the small winning combination (see FIG. 24 described later). For the symbol combination relating to the abbreviation “RT2 transition lip”, an internal winning combination (replay role) according to the name “F_maintenance lip_1st”, “F_maintenance lip_2nd” or “F_maintenance lip_3rd” described later is determined, and It is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the pushing order determined for each type of the replay combination.

  For the symbol combination relating to the abbreviation “RT3 transition lip”, an internal winning combination (replay role) according to the name “F_RT3 lip_1st”, “F_RT3 lip_213”, “F_RT3 lip_231” or “F_RT3 lip_3rd” is determined. And, it is a combination of symbols displayed when the order of the stop operation is correct for the pushing order defined for each type of the replay combination. Also, the symbol combination relating to the abbreviation “RT4 transition ripple” is an internal winning combination (replay combination) according to the name “F_RT4 ripple _123”, “F_RT4 ripple _132”, “F_RT4 ripple _2nd” or “F_RT4 ripple _3rd” described later. It is a combination of the symbols determined and displayed when the order of the stop operation is correct for the pushing order determined for each type of the replay combination.

[Transition flow of gaming state in consideration of presence / absence of operation of notification (ART) function]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not the function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the activated / deactivated state of the ART function is also managed as the gaming state in the bonus inactivated state.

  In the pachislot 1 of the present embodiment, as shown in FIG. 14A, the main control circuit 90 separates the “general gaming state” and the “ART gaming state” based on the presence or absence of notification (ART) in the non bonus operating state. Manage as a game state of. That is, in the management of the gaming state in consideration of the presence or absence of notification (ART), as shown in FIG. 14A, the main control circuit 90 is classified into "bonus state", "general gaming state" and "ART gaming state" as large classifications. Manage 3 different game states.

  The normal gaming state is basically a gaming state (non-ART) in which information on stop operation advantageous to the player is not notified (non-ART), and is a gaming state disadvantageous to the player. In addition, the general gaming state is any state of RT0 to RT4 and is a gaming state in which ART is not won.

  On the other hand, the ART gaming state is a gaming state in which information of stop operation advantageous to the player is notified, and is a gaming state advantageous to the player. Also, the ART gaming state is basically the RT4 state, and the gaming state during winning of the ART. In the present embodiment, when the RT state shifts to the RT4 state after winning the ART, an ART game is started.

  Further, in the present embodiment, as shown in FIG. 14A, two types of states called “normal gaming state” and “CZ (chance zone)” are provided as the general gaming state.

  The normal gaming state is the most disadvantageous gaming state for the player, but in the normal gaming state, transition lottery to CZ is performed. Then, as shown in FIGS. 14A and 14B, in the game in the normal gaming state, when winning the transition lottery to CZ (when the transition condition (A) is established), the main control circuit 90 performs the gaming state as the normal gaming state Transition from to CZ.

  The CZ is a gaming state (chance zone) where the degree of expectation for the transition to the ART gaming state is high, and in the game during the CZ, the transition lottery to the ART is performed. Then, as shown in FIGS. 14A and 14B, in the game during CZ, when the transition lottery to ART is not won (when the transition condition (B) is established), the main control circuit 90 performs the gaming state , CZ to transition to the normal gaming state. On the other hand, in the game during CZ, when the transition lottery to ART is won (transition condition (C) is satisfied), the main control circuit 90 shifts the gaming state from CZ to the ART gaming state. At this time, although not shown in FIG. 14A, the main control circuit 90 shifts the gaming state from CZ to the ART gaming state (general ART or CT described later) via the ART preparation state described later.

  As described above, the ART gaming state is started when the RT state transitions to the RT4 state after winning the ART. As shown in FIG. 13A, since the RT4 state shifts from the RT0 to RT2 state via the RT3 state, the ART gaming state is not started immediately after winning the ART. Therefore, in the pachislot 1 of the present embodiment, the gaming state of the period from the winning of the ART to the transition of the RT state to the RT4 state is set to the ART preparation state. Then, in the game in the ART preparation state, information of a stop operation necessary to shift the RT state to the RT4 state is notified.

  Further, in the present embodiment, as shown in FIG. 14A, there are provided two types of states called “normal ART” and “CT (over chance)” as the ART gaming state, which have mutually different gameplay.

  The normal ART is a stop operation which is advantageous for the player during a predetermined number of games (for example, a stop operation for displaying a symbol combination having a large number of medals to be paid out, and a stop operation necessary for maintaining the RT4 state) Is the gaming state to be notified. In addition, in the game during the normal ART, a transition lottery to CT is performed.

  The CT is a gaming state in which a stop operation which is advantageous for the player is informed, and the duration of the normal ART can be usually added for a specific period (period of 1 set of 8 games), and functions as an additional chance zone Play state. In addition, during CT, games are usually played without digesting the duration of ART. Note that the gameplay during CT will be described in detail later with reference to FIGS. 52A to 52C described later.

  As shown in FIGS. 14A and 14B, in the normal ART game, when the shift lottery to CT is won (when the transition condition (D) is satisfied), the main control circuit 90 changes the gaming state from normal ART to CT. Transition the gaming state. Also, in the normal ART, when the duration of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the gaming state from the normal ART to the normal gaming state (normal gaming state or CZ). Migrate. In the present embodiment, the duration of the normal ART is managed by the number of games, but the present invention is not limited to this, and a method of managing the duration of the normal ART is optional. For example, the duration of the normal ART may be managed by the number of medals and the difference number of medals paid out during the normal ART, or by the number of times (notice of the number of navigations) the notification affecting the payout of medals during the normal ART You may manage.

  As shown in FIGS. 14A and 14B, in the CT game, when the continuation period (one set of eight games) of CT ends (when the transition condition (F) is satisfied), the main control circuit 90 performs the gaming state CT Transition to normal ART.

  Also, as shown in FIG. 14A, when the bonus combination is won in the normal gaming state (normal gaming state or CZ) or ART gaming state (normal ART or CT) (transition condition (2) described in FIGS. 13A and 13B Main control circuit 90 shifts the gaming state from the general gaming state or the ART gaming state to the bonus state.

  In the game in the bonus state, as described above, the transition lottery to the ART is performed, and in the game in the bonus state, when the transition lottery to the ART is not won (when the transition condition (G) is established) The main control circuit 90 shifts the gaming state from the bonus state to the general gaming state (normal gaming state or CZ). However, if the ART gaming state (usually ART or CT) has been shifted to the bonus state, the main control circuit 90 will play the gaming state, even if it is not winning the ART transition lottery in the bonus state game. Transition from the bonus state to the ART gaming state (usually ART or CT). On the other hand, in the bonus state game, when winning the transition lottery to ART (when the transition condition (H) is established), the main control circuit 90 changes the gaming state from the bonus state to the ART gaming state (usually ART or CT). Migrate. As described above, since the RT state shifts to the RT1 state at the end of the bonus state, when transitioning the gaming state from the bonus state to the ART gaming state, the main control circuit 90 changes the gaming state to ART. Transition to ART gaming state via preparation state.

<Structure of data table stored in main ROM>
Next, configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. In addition, various data tables used in various lottery related to the game characteristics (CZ, normal ART, CT game characteristics) in the normal gaming state and the ART gaming state will be described later separately along with the description of each game characteristic .

[Symbol arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is data for specifying the position of each symbol in the rotational direction of each of the left reel 3L, middle reel 3C and right reel 3R and the type of symbol arranged at each position (hereinafter referred to as symbol code (FIG. 15) Define the correspondence with the symbol code table of

  In the symbol arrangement table, when the reel index is detected, the position of the symbol positioned in the middle region of each reel in the frame of the reel display window 4 is defined as “0”. Then, in each reel, the order corresponding to the value of the symbol counter in the order of proceeding in the direction of rotation of the reel (direction from symbol position "19" to symbol position "0" in FIG. 15) relative to symbol position "0" 0 "to" 19 "are assigned to each symbol as a symbol position.

  That is, by referring to the symbol counter values (“0” to “19”) and the symbol arrangement table, the symbols are displayed in the upper, middle and lower regions of each reel in the frame of the reel display window 4 It is possible to identify the type of symbol. In the present embodiment, “white 7”, “blue 7”, “chili 1”, “chili 2”, “chili below”, “replay”, “hat”, “cactus 1”, “chiro 1” We use 10 different designs of "Cactus 2" and "Cactus 3".

  Also, in the present embodiment, as shown in the symbol code table, "00000001" is assigned as data to the symbol "White 7" (symbol code 1), and the symbol "blue 7" (symbol code 2) is "00000010" is assigned as data. "00000011" is assigned as data to the symbol "Citi 1" (symbol code 3), and "00000 100" is assigned as the data to the symbol "2 chii 2" (symbol code 4).

  "00000101" is assigned as data to the symbol "chili lower" (symbol code 5), and "00000110" is assigned to data as the symbol "Replay" (symbol code 6). Data "00000111" is assigned to the symbol "cap" (symbol code 7), and data "0000 1000" is assigned to the symbol "cactus 1" (symbol code 8). Further, "00001001" is assigned as data to the symbol "cactus 2" (symbol code 9), and "00001010" is assigned as data to the symbol "cactus 3" (symbol code 10).

[Internal lottery table]
Next, with reference to FIGS. 16 and 17, the internal lottery table referred to in determining the internal winning combination will be described. FIG. 16 is an internal lottery table referred to in each of the RT0 state to the RT4 state. FIG. 17A is an internal lottery table referred to in the RT5 state, and FIG. 17B is an internal lottery table referred to in the bonus state.

  The internal lottery table is provided for each gaming state, and defines the correspondence between various internal winning combinations and lottery values when each internal winning combination is determined. The lottery value is defined for each setting (settings 1 to 6) for adjusting an expected value of an internal winning combination such as a bonus combination or a small winning combination set in advance. This setting is changed, for example, using the reset switch 76 and the setting key type switch 54 (see FIG. 7).

  In the internal lottery process of the present embodiment, first, random number values extracted from a predetermined numerical value range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 correspond to each internal winning combination. Add sequentially with the specified lottery value. Then, it is determined whether the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result has overflowed). Then, when the lottery result exceeds 65535 in a predetermined internal winning combination, it is determined that the internal winning combination has been won. In the internal lottery process of the present embodiment, an example is described in which the lottery value is added to the extracted random number value to perform the lottery, but the present invention is not limited to this, and the lottery value is subtracted from the random number value It is also possible to determine whether or not the internal lottery has won or not, by determining whether the subtraction result (lottery result) falls below “0” (whether or not the lottery result underflows).

  Therefore, in the internal lottery process of the present embodiment, the larger the internal winning combination defined as the lottery value is, the higher the probability of being determined. The winning probability of each internal winning combination can be represented by “lottery value defined for each winning number / number of all random values that may be extracted (random number denominator: 65536)”.

  In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, the type and the winning probability of the replay combination determined as the internal winning combination according to the type of the RT state. Changes. For example, in the RT0 state to the RT3 state, the replay role according to the names “F_chiri lip (No. 25)” to “F_ reach eye lip D (No. 31)” is not determined as the internal winning combination in the RT0 state to the RT3 state, but in the RT4 state. Only determined as an internal winning combination. In the Pachi-Slot 1 of the present embodiment, during the RT4 state, the replay role according to the names “F_chiri lip (No. 25)” to “F_ reach eye lip D (No. 31)” is determined as the internal winning combination. In this case, specific control (flag conversion described later) is performed. This flag conversion will be described in detail later.

  Further, as shown in FIG. 16, in the state RT0 to state RT3, the internal winning combinations for the names “F_reach eye lip A” to “F_reach eye lip D” pertain to the names “F_BB1” or “F_BB2”. Although it may be determined in duplicate with the bonus role (see Nos. 3 to 6 and 15 to 18), the internal winning combinations (replays) of the names “F_reach eyes Lip A” to “F_reach eyes Lip D” Role is not determined alone as an internal winning combination. Therefore, in the present embodiment, when the replay role associated with the names "F_reach eye rep A" to "F_reach eye lip D" is determined as the internal winning combination during the RT0 state to the RT3 state (as seen by the player) When the symbol combination according to the replay role according to “F_reach eyes Lip A” to “F_reach eyes Lip D” is displayed), the bonus role (name “F_BB1” or “F_BB2”) is simultaneously determined as the internal winning combination It will be done.

  Further, the RT5 state, which is an inter-flag state, is a gaming state in which the bonus combination is carried over as an internal winning combination as described above. Therefore, as shown in FIG. 17A, in the internal lottery table referred to in the RT5 state, the bonus combination carried over is always determined as the internal winning combination. Further, as shown in FIG. 17B, in the internal lottery table referred to in the bonus state, the internal winning combination relating to any of the names “F_RB role 1” to “F_RB role 4” is always won ((1) There will never be a "breakout").

[Correspondence table between internal winning combination and symbol combination (winning combination) (symbol combination determination table)]
Next, with reference to FIGS. 18-23, the correspondence table (symbol combination determination table) of an internal winning combination and a symbol combination will be described. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line (center line) associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the activated line (the type of display combination that can be won) is uniquely determined.

  The various data described in the symbol combination column in each symbol combination determination table is for identifying symbol combinations that allow display along the effective line set across the left reel 3L, middle reel 3C and right reel 3R. It is data. The relationship between each name described in the symbol combination (display combination) column and a specific symbol combination is shown in a winning operation flag storage area in FIG. 28 to FIG. 30 described later.

  In the symbol combination determination table, "o" marks indicate symbol combinations (combinations) that can be displayed on the activated line, that is, display combinations that can be won in the determined internal winning combination. For example, when the internal winning combination "F_Cilirip" is determined, as shown in FIGS. 18 and 19, combination names "C_Maintenance Lip A_01" to "C_Maintenance Lip G_01", "C_Chillip Lip A_01" to "C_Chillip" The symbol combination relating to “D_01” can be stopped and displayed. In addition, although the case where "internal winning combination" becomes "off" is not specified in the symbol combination determination table, this is all the symbols defined by the symbol combination table shown in FIGS. 18-23. Indicates that the display of the combination is not permitted.

  In the pachislot 1 of the present embodiment, when the main control circuit 90 (main CPU 101) changes the stop control according to the internal winning combination and the gaming state, and a predetermined combination is determined as the internal winning combination, FIG. The rotation stop control of the left reel 3L, the middle reel 3C and the right reel 3R is performed so that the symbol combinations (combinations) of the correspondence shown in FIG. 23 can be displayed. In the correspondence tables shown in FIG. 18 to FIG. 23, all symbol combinations that can be displayed for the determined internal winning combination are listed by "o" marks, but symbols with "o" marks are attached. Even if it is a combination, it may not be displayed.

  In the present embodiment, it has a function to make stop control (for example, symbols to be drawn in preferentially) different according to symbol combinations that can be stopped and displayed and the current gaming state, and in terms of drawn in on priority, "○" Even if it is a symbol combination with a mark, it may not be displayed. The correspondence between the type of internal winning combination and the symbol combination actually displayed will be described with reference to FIGS. 24 and 25 described later.

[Correspondence between winning combination in non-flag state and symbol combination to be displayed stopped]
Here, with reference to FIG. 24, the correspondence between the internal winning combination in the gaming state (non-flag state) excluding the inter-flag state and the symbol combination displayed in the stop state will be described. In addition, FIG. 24 shows the correspondence (abbreviated about some roles) between various internal winning combinations that can be determined in the non-flag state and symbol combinations (abbreviation) displayed stopped at each internal winning combination determination. FIG. In addition, the name of the symbol combination described in FIG. 24 is "abbreviation" described in the content column shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

  In the pachi slot 1 of the present embodiment, a combination of symbol combinations displayed in accordance with the order (pushing order) of the player's stop operation is provided, that is, a so-called "pushing order". The symbol combination associated with the “push order correct answer” described in FIG. 24 is a symbol combination advantageous to the player among the symbol combinations displayed according to the push order, and the “push order incorrect answer” Among the symbol combinations displayed according to the pressing order, the associated symbol combination is a symbol combination that is disadvantageous to the player. When notifying a stop operation advantageous for the player, the pressing order that is the correct answer is notified, and if the stopping operation is performed according to the notification, the symbol combination associated with the “pushing order correct” is displayed. In addition, even in the ART gaming state, there may be a notification that the pushing order is incorrect, but the contents will be described in detail later.

  In the present embodiment, for a part of the pushing order, the pushing order that is the correct answer is indicated at the end of the name. Specifically, the end "1st" of the name of the internal winning combination means that the pressing order for the correct answer is that the first stop operation (the first stop operation) is for the left reel 3L, The end "2nd" of the name of the internal winning combination means that the pressing order for the correct answer is that the first stop operation is for the middle reel 3C, and the end "3rd" of the name of the internal winning combination is the correct answer. The pushing order is that the first stop operation is for the right reel 3R. In addition, the end "123" of the name of the internal winning combination means that the pressing order to be the correct answer is the order of "left, middle, right", and the end "132" of the name of the internal winning combination is the correct Means that the order of push is "left, right, middle", and the end "213" of the internal winning combination name is the order of correct push that is "medium, left, right" The suffix “231” of the name of the internal winning combination means that the pressing order to be the correct answer is the order of “left, right, middle”.

  In the following, the stop operation order when the first stop operation is performed on the left reel 3L, specifically, the pressing order of "left, middle, right" and "left, right, middle" It is also called "order push". Furthermore, in the following, the stop operation order when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, “middle, left, right”, “middle, right, left”, The pressing order of "right, middle, left" and "right, left, middle" is also referred to as "irregular pressing".

  In the present embodiment, as shown in FIG. 24, the internal winning combination "F_chiri lip" is a pushing order in which the symbol combinations displayed in accordance with the pushing order are different, and the pushing order is correct. Among the symbol combinations (see FIG. 28 described later) related to “chill lip”, any one of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, if the pressing order is not the correct one, any one of the displayable symbol combinations shown in FIG. 18 to FIG. 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) Is displayed. When the internal winning combination "F_Cilirip" is determined, the combination name "C_Cilirip A_01", "C_Cilirip B_01" or "C_Cililip C_01" (abbreviated as "Single Cilirip") as shown in FIGS. Or "Double chili lip": A symbol combination related to the abbreviation "chiri lip (no triple)" in Fig. 28 described later can be displayed, but combination names "C_chiri lip D_01" to "C_1 positive chiri lip D_01" (abbreviated "Triple chiri lip": The symbol combination according to the abbreviation "chiri lip (triple)" in FIG. 28 described later can not be displayed. That is, the internal winning combination "F_chiri lip" is a part which can not display the symbol combination concerning the abbreviation "triple chiri lip".

  In addition, the internal winning combinations "F_ Certain Chiri Lip" and "F_1 Certain Chiri Lip" are both pressing orders with different symbol combinations displayed according to the pressing order, and in the case where the pressing order is correct, the abbreviation "chiri lip" Of the symbol combinations according to (see FIG. 28 described later), any one of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, if the pressing order is not the correct one, any one of the displayable symbol combinations shown in FIG. 18 to FIG. 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) Is displayed. In addition, when an internal winning combination "F_certain lip" or "F_1 certain lip" is determined, as shown in Figs. 18 to 23, it is possible to display a symbol combination relating to the abbreviation "triple chiri lip". That is, the internal winning combinations "F_certain lip" and "F_1 certain lip" are characters that can display the symbol combination according to the abbreviation "triple chiri lip".

  In addition, internal winning combinations "F_ reach eyes Lip A" ~ "F_ reach eyes Lip D" is a pressing order with different symbol combinations displayed according to pressing order, and if the pressing order is correct, abbreviated Of the symbol combinations (see FIGS. 28 and 29 described later) related to “reach eye lip”, any one of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, if the pressing order is not the correct one, any one of the displayable symbol combinations shown in FIG. 18 to FIG. 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) Is displayed.

  In the present embodiment, the order of pressing the correct answer at the time of winning of the internal winning combination "F_Cilirip", "F_Concile rip", "F_1 Cecile Lip" and "F_Leach Eye Lip A" to "F_Leach Eye Lip D" Is for performing the first stop operation on the left reel 3L. Therefore, for example, in the game in which the internal winning combination "F_reach eye rep A" is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation "reach eye lip" is used. The symbol combination concerned is stopped and displayed. The present invention is not limited to this, and the internal winning combinations "F_Cilirip," "F_Confirmary Lip," "F_1 Certain Chiririp" and "F_Leach Eye Lip A" to "F_Leach Eye Lip D" The pushing order of the correct answer can be set arbitrarily.

  In addition, both of the internal winning combinations "F_Maintenance Lip A" and "F_Maintenance Lip B" are not the pressing order, and regardless of the pressing order, the figure among the symbol combinations (see FIG. 28 described later) related to the abbreviation "Replay". One of the displayable symbol combinations shown in 18 to 23 is displayed along the effective line.

  In addition, the internal winning combinations "F_Maintenance Lip_1st" to "F_Maintenance Lip_3rd" are all pressing orders in which the symbol combinations displayed in accordance with the pressing order are different, and in the case where the pressing order is correct, abbreviations Of the symbol combinations (see FIG. 28 described later) related to “Replay”, any one of the displayable symbol combinations shown in FIG. 18 to FIG. 23 is displayed along the effective line. On the other hand, when the pressing order is not correct, any of the displayable symbol combinations shown in FIG. 18 to FIG. 23 among the symbol combinations (see FIG. 28 described later) related to the abbreviation “RT2 transition lip” is an effective line Displayed along the.

  In addition, the internal winning combinations “F_RT3 Lip_1st” to “F_RT3 Lip_3rd” are all pressing combinations in which the symbol combinations displayed according to the pressing order are different and the pressing sequence is correct, the abbreviation “RT3 The symbol combination (see FIG. 28 described later) related to “transition lip” is displayed along the effective line. On the other hand, if the pressing order is not the correct one, any one of the displayable symbol combinations shown in FIG. 18 to FIG. 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) Is displayed.

  Also, the internal winning combinations “F_RT4 RIP _123” to “F_RT4 rip _3rd” are all pressing combinations that the symbol combinations displayed according to the pressing order are different and the pressing sequence is correct, the abbreviation “RT4 The symbol combination (see FIG. 28 described later) related to “transition lip” is displayed along the effective line. On the other hand, if the pressing order is not the correct one, any one of the displayable symbol combinations shown in FIG. 18 to FIG. 23 among the symbol combinations relating to the abbreviation “Replay” (see FIG. 28 described later) Is displayed.

  In addition, the internal winning combinations "F_3 selection bell _ 1st" to "F 3 selection bell _3 rd" are all press combinations in which the symbol combination displayed according to the pressing order is different, and the pressing order is correct, abbreviated. The symbol combination (see FIG. 19 described later) related to "BELL" is displayed along the effective line. On the other hand, when the pressing order is not correct, the symbol combination (see FIG. 28 described later) relating to the abbreviation “bell spilled eyes” or the symbol combination relating to the abbreviation “first sheet” (see FIG. 30 described later) Is displayed.

  Also, the internal winning combination "F_common bell" is not a pressing order but can be displayed as shown in Figs. 18 to 23 among symbol combinations (see Fig. 29 described later) related to the abbreviation "bell" regardless of pressing order. Any of the graphic symbol combinations are displayed along the effective line. In addition, the internal winning combinations "F_Sabo 1" and "F_Sabo 2" are not all the pressing orders, and regardless of the pressing order, among the symbol combinations relating to the abbreviation "cactus" (see FIG. 30 described later), FIG. One of the displayable symbol combinations shown in FIG. 23 is displayed along the effective line.

  In addition, the internal winning combination "weak cherry" is not a pressing order, and regardless of the pressing order, the display possible shown in Figs. 18 to 23 among symbol combinations (see Fig. 30 described later) related to the abbreviation "weak cherry" Any of the graphic symbol combinations are displayed along the effective line. In addition, the internal winning combinations "F_strong chili 1" and "F_strong chili 2" are not both the pressing order members, and regardless of the pressing order, among symbol combinations relating to the abbreviation "strong cherry" (see FIG. 30 described later) One of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

[Correspondence between the winning combination in the inter-flag state and the symbol combination to be displayed stopped]
Next, with reference to FIG. 25, the correspondence between the internal winning combination and the symbol combination to be stopped and displayed in the inter-flag state will be described. FIG. 25 is a diagram showing the correspondence between an internal winning combination and a symbol combination to be stopped and displayed (abbreviated for a part of the combinations) in the inter-flag state, and in particular, the bonus combination (in the inter-flag state) It is a figure which shows whether the symbol combination (combination name "C_BB1" or "C_BB2") which concerns on the role of BB can be displayed.

  The "o" mark described in the "is whether or not BB is established" column in the correspondence table of FIG. 25 indicates that the symbol combination relating to the BB role can be displayed, and the "x" mark indicates the symbol combination relating to the BB role Indicates that it can not be displayed. When the symbol combination relating to the BB combination can not be displayed, the symbol combination relating to the combination determined as the internal combination winning combination with the bonus combination is displayed. For example, as shown in FIG. 25, when the internal winning combination "F_BB1 + F_Cilirip" is won (the internal winning combination "F_BB1" and the internal winning combination "F_Cilirip" are double winnings), as shown in FIG. 25, the internal winning combination "F_BB1" The symbol combination according to can be stopped and displayed, and the symbol combination according to the internal winning combination "F_chiri lip" is stopped and displayed.

  In addition, when the symbol combination relating to the BB combination can not be displayed and the symbol combination relating to the combination determined to overlap with the bonus combination is displayed in the inter-flag state, the press described in FIG. Only the symbol combination at the time of correct order may be displayed, or only the symbol combination at the wrong order of pressing may be displayed.

  For example, when the internal winning combination “F_BB1 + F_3 selection bell_1st” is won, as shown in FIG. 25, the symbol combination related to the internal winning combination “F_BB1” can not be stopped and displayed, so the internal winning combination “F_3 selection bell_1st” In this case, only symbol combinations relating to the abbreviation “BELL” displayed at the time of pressing order can be displayed, and an abbreviation “BELL Spilled eyes” displayed at the time of pressing order incorrectness. Or you may make it impossible to display the symbol combination which concerns on "one piece appearance" (refer FIG. 24). Also, for example, when the internal winning combination "F_BB1 + F_RT3 rip 1st" is won, only the symbol combination relating to the abbreviation "Replay" displayed at the time of pressing order incorrect can be displayed, and the abbreviation "RT3 displayed at the time of pressing order correct" The symbol combination relating to “transition lip” may not be displayed (see FIG. 24).

  In the inter-flag state, as shown in FIG. 25, the bonus combination (BB combination) and one of the internal winning combinations "Ball", "F_Special 1", "F_Special 2" and "F_Special 3" When it is determined in duplicate, the symbol combination relating to the BB combination can be stopped and displayed.

[Reel Stop Initial Setting Table]
Next, the reel stop initial setting table will be described with reference to FIG. The reel stop initial setting table defines the correspondence between the internal winning combination and various data used in the reel stop control process described later.

  The reel stop initialization table shown in FIG. 26 defines the correspondence between an internal winning combination (small winning combination number), a leading priority table selection table number, a leading priority table number, and a stop table number. In FIG. 26, the gaming state to be referred to and the name of the internal winning combination are also described.

  The drawing priority order table selection table number and the drawing priority order table number are data used in the selection process of the drawing priority order table. For example, in the reel stop initial setting table, if the drawing priority order table number corresponding to the stop table number is defined, the reel priority setting table number corresponding to the drawing priority order table number specified in the drawing priority order table (see FIG. 27 described later). It is possible to obtain data on the priority of the display combination. On the other hand, if the pull-in priority order table number corresponding to the stop table number is not defined in the reel stop initial setting table, the pull-up priority order table selection table number is referred to with reference to the draw priority order table selection table (not shown). A corresponding draw priority table number is determined.

  Here, stop control (determination method of stop symbol position) of the reel in the pachislot 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, stop control of the reel is performed such that the rotation of the corresponding reel is stopped within 190 msec. Specifically, it corresponds to the value obtained by adding one of the number of sliding symbols “0” to “4” to the value of the symbol counter corresponding to the relevant reel when the stop operation is detected. The symbol position is determined as a symbol position at which the rotation of the reel is stopped (hereinafter, referred to as "predetermined stop position"). The symbol position corresponding to the value of the symbol counter according to the corresponding reel when the stop operation is detected is the symbol position at which the stop of the rotation of the reel is started (hereinafter referred to as "stop start position").

  That is, the number of sliding symbols is the amount of rotation of the reel from when the stop operation is detected by the stop switch until when the rotation of the corresponding reel is stopped. In other words, it is the number of symbols passing through the middle region of the corresponding reel of the reel display window 4 in the period from when the stop operation is detected by the stop switch until when the rotation of the corresponding reel is stopped. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  Referring to the stop table (not shown), the number of sliding symbols is obtained according to the stop start position of each reel. In the present embodiment, the number of sliding symbols is acquired based on the stop table, but this is a temporary one, and the acquired number of sliding symbols does not immediately determine the planned stop position of the reel. In the present embodiment, when there is a more appropriate number of sliding symbols than the number of sliding symbols obtained based on the stop table (hereinafter referred to as “sliding number determination data”), a drawing priority order table (described later) Change the number of sliding symbols with reference to FIG. The sliding symbol number determination data is referred to determine the search order when comparing the priorities for each symbol from the stop start position to the symbol position four symbols ahead, which is the maximum sliding symbol number.

[Import priority table]
Next, the drawing priority order table will be described with reference to FIG. The draw-in priority order table includes draw-in data (winning operation flag data) for each type of winning operation flag storage area (see FIGS. 28 to 30 described later) in each of the drawing priority order table numbers “00” to “05”. ) And their predetermined priorities are defined.

  The pull-in priority order table is used to search whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols obtained based on the stop table (not shown). The priority order is data defining the order in which the stop display (retraction) is given priority among the types of symbol combinations (winning operation flag) related to winning. Further, in FIG. 27, for convenience of explanation, the combination name of the winning operation flag is described in the field of the pulling-in data (winning operation flag data), but in the actual pulling-in priority order table, each pulling-in data is a winning As shown in the operation flag storage area (refer to FIG. 28 to FIG. 30 described later), it is represented by 1 byte data, and a unique symbol combination (prize operation flag) is assigned to each bit in the 1 byte data. .

  In the reel stop control of the present embodiment, first, the number of sliding symbols is acquired based on a stop table (not shown). However, based on the priority, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces, it is changed to the appropriate number of sliding pieces. That is, in the present embodiment, the more appropriate number of sliding symbols is determined based on the priority of the symbol combination for permitting the stop display by the internal winning combination regardless of the number of sliding symbols acquired by the stop table.

  In this embodiment, the stop display (pull-in) of the symbol combination whose priority is high is performed preferentially to the stop display of the symbol combination whose priority is low.

  Further, in the present embodiment, as shown in FIG. 27, not only the priority of the symbol combination (winning operation flag) differs according to the drawing-in priority table number, but also the number of divisions of the priority differs. Specifically, if the drawing priority order table number is "00", the number of divisions of priority is set to 5, and if the drawing priority order table number is "01" or "04", the priority order The division number of is 4 Also, if the number-of-draw priority table number is “02” or “03”, the number of divisions of priority is set to 2, and if the number-of-draw priority table number is “05”, the number of divisions of priority Let be 3.

  Here, the priority in the case where the pull-in priority table number is "00" will be described, and the description of the priority in the other pull-in priority table numbers will be omitted. The combination names “C_9 sheets A_01”, “C_1 confirmation C_01”, “C_1 confirmation C_01”, and “C_1 confirmation C_01” in the priority “1” (highest priority) when the attraction priority table number is “00” The import data corresponding to “C_RT3 rep _ 01” is defined.

  The combination names “C_strong2 sheets C_01” to “C_strong2 sheets C_09”, “C_weak 2 sheets B_01” to “C_weak” are assigned to the priority order “2” when the drop-in priority order table number is “00”. Corresponding to 2 sheets B_03, “C_3 sheets E_01”, “C_3 sheets E_02”, “C_9 sheets F_01” to “C_9 sheets F_03”, “C_1 sure chill lip B_01”, “C_ chill lip D_01” and “C_ chill lip C_01” Lead-in data is defined.

  In the priority order "3" when the attraction priority table number is "00", the combination names "C_1 confirmation lip A_01", "C_tili lip A_01", "C_tili lip B_01" and "C_ maintenance lip E_01" to " The retraction data corresponding to C_Maintenance Lip E_04 "is defined.

  The combination names “C_SP1_01”, “C_SP2_01”, “C_reach eye ripple P_01”, “C_reach eye ripple P_02”, “C_reach” for priority “4” when the attraction priority table number is “00”. Eye Lip O_01, "C_ Reach Eye Lip O_02", "C_ Reach Eye Lip N_01", "C_ Reach Eye Lip N_02", "C_ Reach Eye Lip M_01", "C_ Reach Eye Lip M_02", "C_ Reach Eye Lip M_02" L_01 "to" C_ reach eyes Lip L_03 "," C_ reach eyes Lip K_01 "to" C_ reach eyes Lip K_03 "," C_ reach eyes Lip J_01 "," C_ reach eyes Lip I_01 "to" C_ reach eyes Lip I_09 " "C_ reach eyes Lip H_01" to "C_ reach eyes Lip H_03", "C_ reach eyes Lip G_01 "C_ reach eyes Lip F_01", "C_ reach eyes Lip F_02", "C_ reach eyes Lip E_01", "C_ reach eyes Lip D_01", "C_ reach eyes Lip D_02", "C_ reach eyes Lip C_01" ~ " C_reach eyes Lip C_03 "," C_reach eyes Lip B_01 "," C_reach eyes Lip B_02 "," C_reach eyes Lip A_01 "," C_ Keep Lips F_01 "," C_ Keep Lips F_02 "," C_ Keep Lips D_01 "-C_Maintenance Lip D_04", "C_Maintenance Lip C_01"-"C_Maintenance Lip C_03", "C_Maintenance Rep B_01", "C_Maintenance Rep B_02" and "C_Maintenance Rep A_01" are specified as the retraction data Be done.

  Further, in the priority order "5" (lowermost priority order) when the attraction priority table number is "00", attraction data corresponding to the combination names "C_BB1" and "C_BB2" are defined.

<Configuration of Storage Area Provided in Main RAM>
Next, with reference to FIGS. 28 to 35, configurations of various storage areas provided in the main RAM 103 will be described.

[A hit request flag storage area and a winning operation flag storage area]
First, the configurations of the hit request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described with reference to FIGS. 28 to 30. FIG. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (prize flag data storage area) have the same configuration.

  In the present embodiment, the hit request flag storage area is composed of hit request storage areas 0 to 11 each represented by 1-byte data, and the winning operation flag storage area is a winning operation represented by 1-byte data. It comprises storage areas 0-11. The data stored in each storage area of the hit request flag storage area and the winning operation flag storage area is only 1-byte data in the "data" column in FIGS. 28 to 30, but in FIGS. 28 to 30. For convenience of explanation, the symbol combinations of the respective reels (in the figure, described in the order of the symbol of the left reel 3L, the symbol of the middle reel 3C and the symbol of the right reel 3R) corresponding to the bit of each storage area The name (combination name) and abbreviation, and the number of medals paid out are also described.

  When "1" is stored in a predetermined bit in each of the hit request flag storage areas 0 to 11, it indicates that the internal winning combination corresponding to the predetermined bit is internally won. In addition, when “1” is stored in the predetermined bit in each of the winning operation storing areas 0 to 11, it indicates that the display combination (the winning operation flag) corresponding to the predetermined bit is won. That is, when "1" is stored in a predetermined bit, it indicates that various symbol combinations of the internal winning combination corresponding to the predetermined bit are displayed on the effective line.

  Also, in the hit request flag storage area and the winning operation flag storage area, as shown in FIGS. 28 to 30, a plurality of symbol combinations are assigned to one bit (flag) in each storage area. There are also That is, for such a flag, it means that there are a plurality of symbol combinations (combinations capable of winning) which can be stopped and displayed.

  For example, in the hit request storage area 5 and the bit 5 of the winning operation storage area 5, the symbol combination "cactus 2"-"white 7"-"hat" (combination name "C_ maintenance lip C_01"), the symbol combination "cactus 2 -"City 1"-"Hat" (combination name "C_ maintenance lip C_02") and symbol combination "Cactus 2"-"Cactus 2"-"Hat" (combination name "C_ maintenance lip C_03") Three symbol combinations are assigned. Therefore, when "1" is stored in bit 5 of the hit request storage area 5, it indicates that the three symbol combinations can be displayed on the active line. Also, when "1" is stored in bit 5 of the winning operation storage area 5, it indicates that any one of the three symbol combinations is displayed on the effective line.

[Hold over part storage area]
Next, the configuration of the carryover combination storage area will be described with reference to FIG. In the present embodiment, the carryover combination storage area is configured of a 1-byte data storage area.

  When the internal winning combination "F_BB1" or "F_BB2" is determined as a result of the internal lottery, the internal winning combination (BB combination) is stored as a carryover combination in the carryover combination storage area. The carryover combination stored in the carryover combination storage area is held without being cleared until the corresponding symbol combination is displayed on the effective line. While the carryover combination is stored in the carryover combination storage area, the carryover combination is stored in the hit request storage area in addition to the internal winning combination determined by the internal lottery.

[Playing state flag storage area]
Next, the configuration of the gaming state flag storage area will be described with reference to FIG. The gaming state flag storage area is configured of a 1-byte data storage area. In the present embodiment, as shown in FIG. 32, the type of bonus or the type of RT is assigned to each bit of the gaming state flag storage area.

  When “1” is stored in a predetermined bit in the gaming state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being performed. For example, when "1" is stored in bit 0 of the gaming state flag storage area, the operation of the big bonus "BB" is performed, which indicates that the gaming state is the BB gaming state. Further, for example, when “1” is stored in bit 3 of the gaming state flag storage area, it indicates that the gaming state is the RT3 state.

[Operation stop button storage area]
Next, with reference to FIG. 33, the configuration of the operation stop button storage area will be described. The operation stop button storage area is formed of a 1-byte data storage area, and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

  For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, “1” is stored in bit 0 of the operation stop button storage area. Also, for example, in the case where the left stop button 17L is not yet pressed, that is, a valid stop button, “1” is stored in the bit 4. The main CPU 101 identifies the stop button pressed this time and the stop button not yet pressed, based on the data stored in the operation stop button storage area.

[Pressing order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The pressing order storage area is formed of a 1-byte data storage area, and stores a pressing order flag consisting of 1 byte.

  In the pressing order flag, the type of pressing order of the stop button is assigned to each bit. For example, when the pressing order of the stop button is “left, middle, right”, “1” is stored in bit 0 of the pressing order storage area.

[Symbol code storage area]
Next, with reference to FIG. 35, the configuration of the symbol code storage area will be described. In the present embodiment, the symbol code storage area is configured by symbol code storage areas 0 to 11 each represented by 1-byte data. The symbol code storage area has the same configuration as the hit request flag storage area and the winning operation flag storage area (see FIGS. 28 to 30).

  In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the effective line. In addition, after all the reels stop, the symbol code corresponding to the display combination (prize operation flag) is stored in the symbol code storage areas 0-11.

[Relationship between internal winning combination and various sub-flags]
In the normal gaming state and ART gaming state, various data tables are referred to in various lottery by the main control circuit 90, but as parameters used at this time, in the present embodiment, not only internal winning combination but also internal winning combination Also used are various parameters with different names (hereinafter referred to as “sub-flag (first sub-flag)”, “sub-flag EX (second sub-flag)” and “sub-flag D”). Therefore, in the present embodiment, the main control circuit 90 performs processing for converting the internal winning combination into various sub flags (refer to sub flag conversion processing, flag conversion processing, and sub flag compression processing in FIG. 85 described later). In the present embodiment, the sub flag is set in the start command as information (communication parameter) regarding the internal winning combination, and is transmitted from the main control circuit 90 to the sub control circuit 200.

  Here, with reference to FIGS. 36 and 37, the correspondence between the internal winning combination and the various sub flags will be described. FIG. 36 is a diagram showing the correspondence between the internal winning combination (small winning combination) and the various sub-flags, and FIG. 37 is a drawing showing the correspondence between the internal winning combination (special award winning number) and the sub-flag.

  In the flag conversion process of the present embodiment, first, a plurality of internal winning combinations belonging to the same type are put together into one sub-flag. In this embodiment, as shown in FIG. 36, 32 types of internal winning combinations (small winning combination numbers) related to the small winning combination and the replay combination include 18 types of sub flags ("01" to "18") by this flag conversion processing. : Converted to flag data). For example, the internal winning combination “F_Maintenance Lip_1st (10: Small winning combination number)” to “F_Maintenance Lip_3rd (12)” is grouped into the sub-flag “Push Order Lip 1 (09: Flag Data)”. Note that the sub-flag "losing (00)" is assigned to the internal winning combination "losing".

  Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, nineteen sub-flags ("00" to "18") including the sub-flag "losing (00)" contain nine sub-flags EX ("00" To “08”: flag data). Therefore, in this conversion process, the subflag data can be further compressed. At this time, in the present embodiment, the sub-flag is converted into the sub-flag EX by lottery (flag conversion / lottery). Specifically, it is converted as follows.

  The subflag "Loss (00)" is converted to the subflag EX "Loss (00)" regardless of the result of the flag conversion lottery, and the subflag "2 consecutive chiri lip (01)" is converted regardless of the result of the flag conversion lottery The sub flag EX is converted to "replay (01)".

  When the subflag "triple chiri lip A (02)" and the sub flag "triple chiri lip B (03)" are won for the flag conversion lottery (in the case of "conversion present" described later), the sub flag EX "determinator (06)" Alternatively, it is converted into “triple chiri lip (07)”, and when it is not won in the flag conversion lottery (in the case of “conversion not performed” described later), the sub flag EX is converted into “replay (01)”.

  When the sub-flags "reach eye lip 1 (04)" to "reach eye lip 4 (07)" are won in the flag conversion lottery, they are converted to the sub flag EX "final combination (06)" or "reach eye lip (08)" If it is determined that the flag conversion lottery has not been won, it is converted into the sub flag EX “Replay (01)”.

  The sub flags “Replay (08)” and “Push Order Lip 1 (09)” to “Push Order Lip 3 (11)” are converted to the sub flag EX “Replay (01)” regardless of the result of the flag conversion lottery. The sub flags "push order bell (12)" and "common bell (13)" are converted to the sub flag EX "bell (02)" regardless of the result of the flag conversion lottery.

  The subflags "cactus (14)", "weak cherry (15)" and "strong cherry (16)" are subflag EX "cactus (03)" and "weak cherry (04), respectively, regardless of the result of the flag conversion lottery. And “strong cherry (05)”. Further, the sub flags “reach 1 (17)” and “reach 2 (18)” are converted into the sub flag EX “loss (00)” regardless of the result of the flag conversion lottery.

  As described above, in the present embodiment, the sub-flags "trile chili lip A (02)", "triple chili lip B (03)" and "reach eye lip 1 (04)" to "reach eye lip 4 (07) Only) is subject to flag conversion lottery. The lottery table used for the flag conversion lottery described above will be described in detail later.

  Furthermore, in the flag conversion process of this embodiment, as shown in FIG. 36, nine types of sub flags EX ("00" to "08") are converted into seven types of sub flags D ("00" to "06"). Ru. Therefore, the subflag data can be further compressed in this conversion process. In this conversion process, the lottery is not performed, and the conversion is performed by associating the sub flag EX with the sub flag D as follows.

  The sub-flags EX “losing (00)”, “Replay (01)” and “bell (02)” are converted into the sub-flag D “losing (00)”. Subflag EX "cactus (03)" is converted to subflag D "cactus (01)", subflag EX "weak cherry (04)" is converted to subflag D "weak cherry (02)", subflag EX "strong Cherry (05) is converted to sub-flag D "strong cherry (03)".

  In addition, the sub flag EX “fixed combination (06)” is converted to the sub flag D “fixed combination (04)”, and the sub flag EX “triple chiri lip (07)” is converted to the sub flag D “triple chiri lip (05)” And the sub flag EX “reach eye rep (08)” is converted into the sub flag D “reach eye lip (06)”.

  Further, in the flag conversion process of the present embodiment, as shown in FIG. 37, the internal winning combination "F_BB1 (01: special prize winning number)" and "F_BB2 (02)" are both converted into the sub flag "BB". .

[Game character at the time of sub flag EX conversion]
Here, the process of converting the internal winning combination into the sub-flag and the sub-flag EX and an example of the game property at the time of the sub-flag EX conversion will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing a flag conversion process when the internal winning combination "F_positive only" or "F_1 only positive" is determined, and FIG. 38B is a diagram showing the internal winning combination "F_reached eyes lip A" to "F_ It is a figure which shows the flag conversion process in case either of reach eye lip | rip D is determined.

  In Pachi-Slot 1 of the present embodiment, one of the internal winning combination "F_ Certainly Lip", "F_1 Certainly Lip" and "F_ Reached Eye Lip A" to "F_ Reached Eye Lip D" is independent during the RT4 gaming state. When it is determined that the internal winning combination is made, the flag conversion lottery is performed. Then, in the present embodiment, when winning the flag conversion lottery, a special benefit (for example, the addition of the number of ART games or the winning of a CT) is given.

  For example, when the internal winning combination "F_positive chili lip" or "F_1 positive chili lip" is determined, as shown in FIG. 38A, the internal winning combination "F_positive chili lip" and "F_1 positive chili lip" each have the sub-flag "triple". It is converted to chilli lip A (02) and "triple chilli lip B (03)".

  Next, when the sub flags "triple chiri lip A (02)" and "triple chiri lip B (03)" are hit in the flag conversion lottery, the sub-flag EX "triple chiri lip (07)" or the "determinator (06)" It is converted. On the other hand, when the flag conversion lottery has not won, the sub-flag "triple chiri lip A (02)" and "triple chiri lip B (03)" are both converted into the sub-flag EX "replay (01)" .

  As described in FIG. 24, when the internal winning combination "F_ Certain Chiri Lip" or "F_1 Certain Chiri Lip" is won, the symbol combination relating to the abbreviation "Triple Chiri Lip" is displayed when the pressing order is correct, and the pressing order is not available. At the time of correct answer, a symbol combination relating to the abbreviation "replay" is displayed. Therefore, in the present embodiment, when the internal winning combination "F_positive chirip" or "F_1 positive lip" is determined and the flag conversion lottery is won, the internal winning combination "F_positive chili lip" and "F_1 definite chiri lip" Are all treated as the role of the sub-flag EX "triple chiri lip (07)" or "decision part (06)".

  Then, when the internal winning combination "F_positive chirip" or "F_1 positive chiri lip" is converted into the sub-flag EX "triple chiri lip (07)" or "declaring part (06)" by this flag conversion process, the abbreviation "triple Information for displaying a symbol combination relating to “chiri lip” is informed (for example, information to the effect that the player is made to aim for a chili symbol by pressing in order is notified). On the other hand, in this flag conversion process, when the flag conversion lottery is not won and the internal winning combination "F_positive_lip" or "F_1_positive_lip" is converted to the sub-flag EX "Replay (01)", it is abbreviated as "Replay". Information for displaying the symbol combination is informed (for example, an order of pushing other than the order pushing (anomalous pushing) is informed).

  Also, for example, when any one of the internal winning combination "F_reach eyes Lip A" to "F_reach eyes Lip D" is determined, as shown in FIG. 38B, the internal winning combination "F_reach eyes Lip A" to " F_reach eye lip D is converted into sub-flags “reach eye lip 1 (04)” to “reach eye lip 4 (07)”, respectively.

  Next, when the sub-flags "reach eye lip 1 (04)" to "reach eye lip 4 (07)" win the flag conversion lottery, sub flag EX "reach eye lip (08)" or "decisionist (06)" It is converted. On the other hand, when the flag conversion lottery is not won, the sub-flags "reach eye lip 1 (04)" to "reach eye lip 4 (07)" are converted to the sub flag EX "replay (01)".

  In addition, as described in FIG. 24, when one of the internal winning combinations "F_reach eyes Lip A" to "F_reach eyes Lip D" is won, the symbol combination pertaining to the abbreviation "reach eyes lip" is displayed when the pressing order is correct. Is displayed, and a symbol combination relating to the abbreviation "Replay" is displayed when the pressing order is incorrect. Therefore, in the present embodiment, when one of the internal winning combination "F_reach eye lip A" to "F_reach eye lip D" is determined and the flag conversion lottery is won, the internal winning combination "F_reach eye" is determined. Each of the lip A "to" F_reach eye lip D "is treated as the role of the sub flag EX" reach eye lip (08) "or the" decision role (06) ".

  Then, when the internal winning combination "F_reach eyes Lip A" to "F_reach eyes Lip D" is converted to, for example, the sub-flag EX "reach eyes Lip (08)" or "fixed role (06)" by this flag conversion process. The information for displaying the symbol combination relating to the abbreviation "reach eye lip" is informed (for example, information to the effect of aiming the symbol "white 7" is informed to the player by forward pressing). On the other hand, in this flag conversion process, when the flag conversion lottery is not won and the internal winning combinations "F_reach eyes Lip A" to "F_reach eyes Lip D" are converted to the subflag EX "Replay (01)" Information for displaying a symbol combination relating to "Replay" is notified (for example, a push order other than the forward press (anomalous press) is notified).

  Further, in the present embodiment, when the player performs the stop operation according to the notification after winning the flag conversion lottery in the flag conversion process shown in FIG. 38A or 38B, the symbol relates to “triple chiri lip” or “reach eye lip”. The symbol combination is stopped and displayed on the activated line, and a special benefit is given. In this processing, a special benefit is awarded to the player in response to the pachislot 1 winning the flag conversion / lottery, substantially in terms of processing. The display of the symbol combination related to "Continuous Chile lip" makes it feel that special benefits have been given.

  Depending on the state, it may be preferable to change the appearance frequency of the symbol combination to which the bonus is given, rather than being constant, in order to enhance the gameplay of the pachislot machine. Since stop control (symbol combination to be displayed) differs depending on the type of internal winning combination, as a method of making the appearance frequency of symbol combination to which a privilege is given differed depending on the condition, the winning probability of the internal winning combination is made different. A method is also conceivable (in Pachislot 1, the winning probability of the internal winning combination can be made different depending on the presence or absence of the bonus operation and the RT state, for example, only the RT4 state as the RT state corresponding to the ART gaming state) Alternatively, other RT states such as RT6 state and RT7 state may be provided). However, since the opportunity (the transition opportunity of the RT state) for changing the winning probability of the internal winning combination is limited, this method lacks flexibility from the viewpoint of improving the game characteristics (interesting).

  On the other hand, in Pachi-Slot 1 of this embodiment, flag conversion lottery and notification based on the lottery result are performed in addition to internal lottery for determining the internal winning combination without changing the winning probability of the internal winning combination. The appearance frequency of the symbol combination to which the benefit is given can be flexibly changed according to the state. That is, in the state where it is easy to win the flag conversion lottery, the appearance frequency of the symbol combination to which the benefit is given can be raised, and conversely, when the condition that the flag conversion lottery is hard to win, the appearance of the symbol combination to which the bonus is given You can reduce the frequency.

<Playability in the General Game State>
Next, with reference to FIGS. 39A to 39C, the flow of gaming in the normal gaming state will be described. In the pachislot 1 of the present embodiment, the gaming state transitions from the normal gaming state to the CZ during the normal gaming state, and thereafter, the gaming state transitions from the CZ to the ART gaming state, whereby the general gaming state (non-ART gaming state ) To the ART gaming state (see FIGS. 14A and 14B).

  FIG. 39A is a diagram showing a flow of gaming when the gaming state shifts from the normal gaming state to CZ in the general gaming state. The normal gaming state has a low probability state and a high probability state as a lottery state of CZ, as shown in FIG. 39A. The low probability state and the high probability state are states in which the expectations for winning the CZ lottery which are performed during the normal gaming state are different from each other, the low probability state is the condition in which it is difficult to win the CZ lottery, and the high probability state is the CZ It is easy to win the lottery. Then, when winning the CZ lottery performed in the game in the normal gaming state, the gaming state shifts from the normal gaming state to the CZ.

  In the pachislot 1 of the present embodiment, a plurality of chance zones of “CZ1”, “CZ2” and “CZ3” are provided as the CZ (chance zone). CZ1 to CZ3 are chance zones different from each other in the expectation for winning ART lottery to be played in CZ, CZ3 is a chance zone for always winning ART lottery, and CZ1 and CZ2 have a predetermined probability. This is a chance zone for winning ART lottery. In the CZ lottery performed in the normal gaming state, not only CZ winning or not winning, but also the type of CZ (CZ1 to CZ3) to be transferred upon winning is determined (see FIG. 41 described later).

  FIG. 39B is a diagram showing a flow of gaming when transitioning from CZ1 and CZ2 in the normal gaming state to the ART gaming state. Both CZ1 and CZ2 are composed of a first half and a second half. The first half is a period to promote the rank of the degree of expectation to win the ART lottery to be played in the game during CZ, and the second half a predetermined effect of the lottery result of ART lottery based on the rank (in the present embodiment, the character Period during which it is informed by battle effect).

  In CZ1, six stages of modes (modes 1 to 6) are prepared as ranks, and the higher the mode, the higher the expectation for winning ART lottery. In the first half of CZ1, the game is continuously performed for a period of the first predetermined number of games (for example, 12 games at the maximum), and the promotion lottery of the mode is performed based on the internal winning combination. Then, in the first game of the second half of CZ1, ART lottery is performed based on the mode promoted in the first half (the mode at the end of the first half).

  Moreover, in CZ2, 10 points of points are prepared as ranks, and the higher the points, the higher the expectation for winning ART lottery. In the first half of CZ2, the game is continuously performed for a period of the second predetermined number of games (for example, 15 games at the maximum), and elevation lottery of points is performed based on the internal winning combination. Then, in the first game of the second half of CZ2, ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

  In the second half of CZ1, a battle effect in which the ally character and the enemy character A fight is performed, and in the second half of CZ2, a battle effect in which the ally character and the enemy character B battle is performed. This battle effect is performed over the game of the period of the third predetermined number of games (for example, at most four games). In addition, the outcome of the battle production is managed (decided) based on the result of ART lottery, and when winning the ART lottery, the ally character wins in the battle production and the battle is not won, The enemy character wins in the production.

  In addition, in each second half of CZ1 and CZ2 (during battle rendition), ART lottery is performed based on the internal winning combination for each game. And, winning the ART lottery, the result of the battle production is rewritten. For example, when a so-called "rare" combination is determined as an internal winning combination during battle production, ART lottery is performed, and the result of battle production is rewritten based on the result.

  In CZ1 and CZ2, in the case of not winning ART, the second half of the battle is defeated, and basically, the gaming state then shifts to the normal gaming state. On the other hand, if CZ1 and CZ2 win the ART, they win the battle effect in the second half, and then the gaming state shifts from CZ to the normal ART via the ART preparation state. In the present embodiment, freeze may occur in the first half of CZ1 and CZ2 games, in which case the gaming state is not CART but CT (over the ART preparation state from CZ). Move to Chance Zone).

  FIG. 39C is a diagram showing the flow of gaming when the gaming state transitions from CZ 3 in the general gaming state to the ART gaming state. CZ3 continues to be played for a period of the fourth predetermined number of games (for example, 17 games at the maximum). Then, in CZ3, ART lottery is performed based on the internal winning combination for each game.

  CZ3 ends when it wins ART lottery, and from the next game onward, the gaming state shifts from CZ3 to CT (superimposed chance zone) via the ART preparation state. In addition, in CZ3, a freeze may occur, and also in this case, the gaming state shifts from CZ3 to CT (superimposed chance zone) via the ART preparation state from the next game. On the other hand, in CZ3, when the game period (the fourth predetermined number of games) of CZ3 has passed without winning ART lottery, the gaming state shifts from CZ3 to the normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state is determined.

<Various data tables used during normal gaming state>
Subsequently, various data tables used in the lottery processing regarding the game property performed during the normal gaming state will be described with reference to FIGS. 40 to 45. Note that various data tables described below are stored in the main ROM 102.

  Further, various data tables shown below conceptually show information of lottery values. “0” in the data table means that a lottery value corresponding to the winning probability “0%” is defined, “very low” is a lottery corresponding to the winning probability “0% to less than 1%” A value is defined, and "very low" means that a lottery value corresponding to the winning probability "1% to less than 10%" is defined. Also, "low" in the data table means that a lottery value corresponding to the winning probability "10% to less than 30%" is defined, and "middle" indicates that the winning probability is "30% to less than 60% “High” means that a lottery value corresponding to the winning probability “60% to less than 80%” is defined. Furthermore, "very high" in the data table means that a lottery value corresponding to a winning probability "less than 80% to 99%" is defined, and "very high" means a winning probability "99% to 100". It means that the lottery value corresponding to “less than%” is defined, and “confirmed” means that the lottery value corresponding to the winning probability “100%” is defined.

  Then, in various data tables shown below, the random number value for lottery which is extracted from the range (0 to 65535) of the predetermined numerical value is sequentially subtracted by the defined lottery value by the random number register 1 of the random number circuit 110. Internal lottery is performed by determining whether or not the result of subtraction is negative (whether so-called "worried" has occurred). In the present embodiment, an example has been described in which the lottery value is subtracted from the random number value for lottery in the lottery process relating to the gaming property performed during the normal gaming state to determine the winning / not winning, but the present invention is limited thereto No, the lottery value is added to the extracted random number for lottery, and it is judged whether the addition result exceeds 65,536 (whether so-called "overflow" has occurred or not), and the winning / not winning is determined It is also good.

[Normal middle and high probability lottery table]
First, with reference to FIGS. 40A and 40B, a description will be given of a normal medium-high probability lottery table used in transition lottery of CZ lottery states (low probability and high probability). In the Pachislot 1 of the present embodiment, not only the transition of the lottery status of CZ is performed based on the internal winning combination, but also for example, at the end of the bonus or at the end of CZ, ART, etc. Transition of lottery status A lottery is performed. FIG. 40A is a block diagram of a normal middle-high probability lottery table in which each game is referred to during the normal gaming state, and FIG. 40B is, for example, normal middle-high referred when the setting is changed, the bonus ends or CZ, ART ends, It is a block diagram of a probability lottery table. The name of the internal winning combination shown in FIG. 40A corresponds to the name of the sub-flag described above.

  The normal middle high probability lottery table shown in FIG. 40A includes each combination of the current CZ lottery state and the internal winning combination, the lottery result (low probability / high probability) of the CZ lottery state after transition, and each lottery result. It defines the correspondence with the information of the extracted lottery value.

  As apparent from the normal middle-high probability lottery table shown in FIG. 40A, when the current CZ lottery status is low probability, when the internal winning combination is the role corresponding to the sub-flag "weak cherry", the CZ It becomes easy to shift the lottery status to a high probability. On the other hand, when the current CZ lottery status is high probability, when the internal winning combination is the role corresponding to any of the sub-flag "common bell", "cactus", "weak cherry" and "strong cherry" In addition, the lottery status of CZ is maintained with high probability.

  In the normal middle-high probability sorting table shown in FIG. 40B, each situation when referring to the table, the lottery result (low probability / high probability) of the lottery state of CZ after transition, and the lottery associated with each lottery result Define the correspondence with value information. As apparent from the normal middle-high probability lottery table shown in FIG. 40B, the lottery state of CZ always shifts to the high probability at the end of the bonus.

[CZ lottery table]
Next, with reference to FIGS. 41A and 41B, a CZ lottery table used in CZ lottery will be described. FIG. 41A is a configuration diagram of a CZ lottery table used when CZ lottery is performed based on an internal winning combination during the normal gaming state, and FIG. 41B is a CZ pullback, for example, at the time of CZ failure or ART termination. Is a configuration diagram of a CZ lottery table used when performing CZ lottery whether or not to perform. The name of the internal winning combination shown in FIG. 41A corresponds to the name of the sub-flag described above.

  The CZ lottery table shown in FIG. 41A is a combination of each combination of the current CZ lottery state and the internal winning combination, winning / not winning of CZ1, CZ2 and CZ3 (lottery result), and lottery results corresponding to each lottery result. Define the correspondence with value information. As apparent from the CZ lottery table shown in FIG. 41A, when the current CZ lottery state is in high probability, the CZ lottery is more successful than when the current CZ lottery state is in low probability. The probability is high.

  In the CZ lottery table shown in FIG. 41B, the correspondence between the winning / not winning (winning results) of CZ1, CZ2 and CZ3 at the time of CZ failure or at the end of ART and the information of the lottery value associated with each lottery result. To define. At the time of CZ failure (when CZ1 or CZ2 does not win the ART lottery) or at the end of the ART gaming state, the CZ pulling back lottery is performed using this CZ lottery table.

[CZ1 mode up lottery table]
Next, with reference to FIG. 42, the CZ1 medium mode up lottery table used in the CZ1 mode up lottery performed in the first half of CZ1 will be described. FIG. 42 is a block diagram of a CZ1 medium mode up lottery table. The name of the internal winning combination shown in FIG. 42 corresponds to the name of the sub-flag described above.

  The CZ1 medium mode up lottery table shows the correspondence between each combination of the current mode and the internal winning combination, the result of the mode up lottery (win / not win), and the information of the lottery value corresponding to each lottery result. To define. As shown in FIG. 44A described later, in CZ1, as the mode increases (the value of the mode increases), the probability of winning the ART lottery increases, and when the mode rises to mode 6, the ART lottery always wins.

  The lottery result “mode 1 UP” in FIG. 42 means that the mode of CZ 1 is raised by one step, and the lottery result “mode 2 UP” means that the mode of CZ 1 is increased by two steps. Therefore, for example, in a situation where the current mode is mode 2, the mode of CZ1 is raised from mode 2 to mode 4 when the lottery result "mode 2 UP" is won. Also, for example, when the lottery result “mode 6 UP_freeze occurrence” is won, a freeze occurs and the winning of ART lottery and the grant of CT are determined.

[CZ2 middle point lottery table]
Next, with reference to FIG. 43, the CZ2 middle point lottery table used in the CZ2 point-up lottery performed in the first half of CZ2 will be described. FIG. 43 is a configuration diagram of a CZ2 middle point lottery table. The name of the internal winning combination shown in FIG. 43 corresponds to the name of the sub-flag described above.

  The CZ2 medium point lottery table shows the correspondence between each combination of the current point and the internal winning combination, the result (win / not win) of the point-up lottery, and the information of the lottery value corresponding to each lottery result. Specify. As shown in FIG. 44B described later, in CZ2, as the point goes up, the probability of winning the ART lottery increases, and when the point goes up to “point 10”, the ART lottery will always win. The lottery result “point 2 UP” in FIG. 43 means that “2” is added to the current CZ 2 point, and, for example, in the situation where the current point is “2”, the lottery result “ Winning "Point 2 UP", CZ2's point goes from "2" to "4". Also, for example, when “point 10 UP_freeze occurrence” of the lottery result is won, a freeze occurs, and the winning of ART lottery and the grant of CT are determined.

[CZ ART ART lottery table]
Next, with reference to FIGS. 44A to 44C and FIG. 45, the CZ-in-CZ ART lottery table used in the ART lottery performed during CZ will be described. FIG. 44A is a block diagram of the CZ ART lottery table (for CZ1) used in the first game of the second half of CZ1, and FIG. 44B is a CZ ART used in the first game of the second half of CZ2. FIG. 44C is a configuration diagram of a lottery table (for CZ2), and FIG. 44C is a configuration diagram of an ART lottery table for CZ used in the second half of CZ1 and CZ2 (for CZ1 and CZ2 common second half battle). FIG. 45 is a block diagram of a CZ-medium ART lottery table (for CZ3) used in the ART lottery performed during CZ3. The names of the internal winning combinations shown in FIG. 44C and FIG. 45 correspond to the names of the sub-flags described above.

  The ART lottery table (for CZ1) in CZ shown in FIG. 44A defines the correspondence between the current mode, the result of ART lottery (presence or absence of winning), and the information of lottery value corresponding to each lottery result. . In addition, the ART lottery table (for CZ2) in CZ shown in FIG. 44B shows the correspondence between the current point, the result of ART lottery (presence or absence of winning), and the information of the lottery value corresponding to each lottery result. Specify.

  As apparent from the ART lottery table (for CZ1) in CZ and the ART lottery table (for CZ2) in CZ, in CZ1 and CZ2, as the rank (mode or point) of the first half increases, it becomes easier to win ART lottery.

  The ART lottery table in CZ (for CZ1 and CZ2 common and in the second half battle) shown in FIG. 44C includes an internal winning combination, results of ART lottery (presence or absence of winnings), and information of lottery values associated with each lottery result. Define the correspondence relationship between As is clear from the ART lottery table (for CZ1 and CZ2 common and for the second half battle) in CZ, in the second half of CZ1 and CZ2, the role corresponding to the sub-flag (sub-flag "weak cherry", "cactus" or "strong cherry") ) Is determined to be an internal winning combination, winning an ART lottery with a predetermined probability.

  The ART lottery table (for CZ3) in CZ shown in FIG. 45 is a combination of each combination of the number of digested games of CZ 3 and the internal winning combination, the result of ART lottery (presence or absence of winning), and the lottery result corresponding to each lottery result. Define the correspondence with value information. As apparent from the ART lottery table (for CZ3) during CZ, in the present embodiment, when ART lottery is performed during CZ3, CT is always won.

<Playability during Normal ART>
Next, the flow of the game in the game ART will be described with reference to FIGS. 46A and 46B. In the Pachi-slot 1 of this embodiment, as described above, the ART and CT are normally provided as the ART gaming state (see FIGS. 14A and 14B), and the CT is used as an additional chance zone. Therefore, in the present embodiment, in the game during the normal ART, the player plays a game aiming to shift to the CT.

[Mode of transition from normal ART to CT]
FIG. 46A is a diagram showing a transition aspect of the gaming state from the normal ART to the CT. In the pachi-slot 1 of the present embodiment, as shown in FIG. 46A, when the CT lottery performed during the normal ART is won, the gaming state shifts from the normal ART to the CT. In addition, as shown in FIG. 46A, the Pachislot 1 of the present embodiment is provided with an ART level and a CT lottery state as parameters that affect various lottery performed normally during ART.

  As the ART level, four levels of level 1 to level 4 are provided, and this ART level is controlled (determined) mainly based on the number of continued (digested) games in the normal ART. The ART level affects the determination of the CT lottery status and flag conversion lottery in the normal ART described later.

  As the CT lottery state, four stages of low probability, usually high probability and ultra high probability are provided, and the CT lottery state is mainly controlled based on ART level or internal winning combination in normal ART ( It is determined. The CT lottery status affects CT lottery performed during the normal ART, flag conversion lottery during the normal ART described later, and the like.

[Flag conversion in normal ART]
As described above, in the Pachi-Slo 1 of the present embodiment, during the RT4 state, that is, during the ART gaming state, the internal winning combinations "F_ Certainly Lip", "F_1 Certainly Lip" and "F_ Reached Eye Lip A" to "F_" If any of reach eye lip D is determined as an internal winning combination alone, flag conversion lottery is performed, and a special benefit (for example, addition of ART game number or CT win) is awarded according to the lottery result. . FIG. 46B is a diagram showing an outline of a method of flag conversion lottery that is normally performed during ART.

  In the present embodiment, as shown in FIG. 46B, flag conversion / lottery is performed with reference to the ART level and the CT lottery state during normal ART. As a result, in the case of winning the flag conversion lottery, special benefits are given, and symbol combinations related to the "triple chiri lip", symbol combinations for the "reach eye lip", etc. are stopped and displayed on the effective line. A navigation for causing the game (for example, notification of information indicating that a predetermined symbol is aimed by pressing in order) is performed. On the other hand, when the flag conversion lottery is not won, a navigation for stopping and displaying the symbol combination relating to the abbreviation “Replay” on the effective line (for example, notification of pressing order other than forward pressing) is performed.

  Then, when the player performs a stop operation in accordance with the notification (navigation), the symbol combination corresponding to the content of the notification is stopped and displayed on the effective line. Specifically, when winning the flag conversion lottery, the symbol combination related to the abbreviation "triple chiri lip" or the symbol combination related to the abbreviation "reach eye lip" is stopped and displayed on the effective line, and the flag conversion lottery is not made. In the case of winning, the symbol combination relating to the abbreviation "Replay" is stopped and displayed on the effective line.

<Various data tables used during normal ART>
Next, various data tables used in the lottery process in the normal ART will be described with reference to FIGS. Note that various data tables described below are stored in the main ROM 102.

[ART flag conversion lottery table]
FIGS. 47A and 47B are configuration diagrams of an in-ART flag conversion / lottery table used in the flag conversion / lottery performed during the normal ART.

  In the pachislot 1 according to the present embodiment, the flag conversion lottery in the normal ART is performed in two stages. Specifically, when the internal winning combination "F_ Certain Chiri Lip" or "F_1 Certain Chiri Lip" is won, first, the first stage flag conversion lottery is performed, and when this first stage flag conversion lottery is won, then , Second stage flag conversion lottery is performed. Then, when the second stage flag conversion lottery is won, the internal winning combination "F_certain lip" or "F_1 certain lip" is converted into the subflag EX "triple chiri lip". On the other hand, when the first stage of flag conversion lottery or the second stage of flag conversion lottery is not winning, the internal winning combination "F_ Certainly Lip" or "F_1 Certainly Lip" is converted into the sub flag EX "Replay" (Treated as a regular replay role). When any one of the internal winning combinations “F_reach eyes Lip A” to “F_reach eyes Lip D” is won, only the second stage flag conversion lottery is performed.

  FIG. 47A is a configuration diagram of the flag conversion lottery table in ART used in the first stage of flag conversion lottery, and FIG. 47B is a configuration diagram of the flag conversion lottery table in ART used in the second stage flag conversion lottery is there.

  In the ART flag conversion lottery table shown in FIG. 47A, the internal winning combination (“F_finality lip” or “F_1 finality lip”) and the lottery result of the first stage flag conversion lottery (no conversion / conversion (temporary)) And a correspondence between information on lottery values associated with each lottery result.

  In the ART flag conversion lottery table shown in FIG. 47B, each combination of internal winning combination, ART level and CT lottery state, lottery result of second stage flag conversion lottery (without conversion / conversion), and each lottery result Define the correspondence with the information on the lottery value associated with. In addition, in the game until the CT is won once in the normal ART, the table of the “first time (until CT wins once)” column of the item “ART level” in FIG. 47B is referred to.

  In this embodiment, as shown in FIGS. 47A and 47B, in the second and third stages of flag conversion lottery using each of the flag conversion lottery tables in ART, random number values (0 A lottery is performed using 255). Therefore, in the present embodiment, the above-described two-stage flag conversion lottery can be regarded as a lottery substantially the same as the case of performing one lottery using a random number value with a probability denominator of “65536”.

  In recent pachislots, the lottery (ART lottery etc.) for the balls taken out conventionally on the side of the sub control board 72 (hereinafter referred to as “sub side”) is referred to as the main control board 71 (hereinafter referred to as “main side”) It is required to do. However, since the capacity of the storage means (main ROM 102) on the main side is limited to a small capacity, there is a need for a mechanism that enables lottery without impairing the game performance while suppressing an increase in processing capacity.

  In this regard, in Pachi-Slot 1 of the present embodiment, by performing the lottery with the probability denominator “256” in two steps, it is possible to perform the lottery with the probability denominator “65536”, so the main processing pertaining to the lottery processing It is possible to suppress the increase of the side capacity. In addition, in the second stage of lottery, since ART level and CT lottery status etc. are referenced, flag conversion lottery can be performed according to the current status as well as the internal winning combination, as a result, various game characteristics can be obtained. It is possible to carry out a flag conversion lottery.

[ART level determination table]
FIGS. 48A and 48B are configuration diagrams of an ART level determination table used in determining an ART level. In addition, the determination process of the ART level is performed at the time of winning the ART when the transition to the ART gaming state is decided, and usually during the ART. FIG. 48A is a block diagram of an ART level determination table used at the winning of ART, and FIG. 48B is a block diagram of an ART level determination table generally used during ART.

  The ART level determination table shown in FIG. 48A defines the correspondence between ART levels 1 to 4 (lottery results) and information on lottery values associated with each ART level. In the present embodiment, when a freeze occurs at the winning of the ART, the ART level 2 is determined as the ART level.

  The ART level determination table shown in FIG. 48B is a lottery corresponding to each combination of the current ART level and the number of progress (digestion) games of normal ART, various ART levels of the transition destination, and each ART level of the transition destination. Define the correspondence with value information. Also, the ART level determination table shown in FIG. 48B is associated with each combination of the current ART level and the number of elapsed games in the normal ART at the time of CT entry, the various ART levels of the transition destination, and the respective ART levels of the transition destination. It defines the correspondence with the information of the extracted lottery value. That is, in the normal ART, not only the ART level can be shifted when the number of elapsed (digested) games in the normal ART has reached the predetermined number of games, but also the ART level can be shifted in the normal ART in the CT. It becomes possible to shift.

[Normal ART Medium-High Probability Lottery Table]
FIG. 49 is a schematic diagram of a normal ART medium high probability random determination table used when determining a CT lottery state during normal ART.

  In the normal ART medium-high probability lottery table, the correspondence between each combination of the current CT lottery state and the internal winning combination, various CT lottery states of the transition destination, and information of lottery values corresponding to each CT lottery state Specify. The name of the internal winning combination shown in FIG. 49 corresponds to the name of the sub-flag described above.

  As is apparent from the normal ART medium-high probability lottery table, the internal winning combination corresponding to the sub-flag "triple chiri lip (triple chili lip A and tri-ple chiri lip B)" and the sub-flag "reach eye lip (reach eye lip 1 to 4)" The CT lottery status is likely to shift (fall) to “low probability”. However, as shown in FIG. 50 described later, if the internal winning combination corresponding to the sub-flag “three consecutive chill lip” or “reach eye lip” is won, even if the CT lottery state falls, CT It is configured to win the lottery by all means.

[CT during lottery in ART table]
FIG. 50 is a block diagram of an during-ART CT lottery table used in CT lottery that is normally performed during ART.

  The CT lottery table during ART includes each combination of the current CT lottery status and the internal winning combination, various lottery results of CT lottery (non winning / normal CT / high probability CT), and lottery associated with each lottery result. Define the correspondence with value information. The name of the internal winning combination shown in FIG. 50 corresponds to the name of the sub-flag described above.

  In this embodiment, sub-flags "cactus", "weak cherry", "strong cherry", "triple chili lip (triple chili lip A and tril chili lip B)", "reach eye lip (reach eye lip)" as internal winning combinations. 1 to 4) "or" BB "is determined, in the CT lottery process using the CT lottery table during ART, CT lottery using random numbers in the range where the probability denominator is" 256 " Is done. In addition, if an internal winning combination other than these winning combinations (for example, a combination corresponding to the sub-flag "Replay", "common bell", "pushing order bell", etc.) is determined as an internal winning combination, CT during ART In the CT lottery process using the lottery table, CT lottery using random numbers in the range where the probability denominator is “65536” is performed.

  In the pachislot 1 of the present embodiment, two types of CT called “normal CT” and “high probability CT” are provided as CT. In normal CT and high probability CT, expectations for the number of ART games to be added in CT (superimposed chance zone) are different from each other, and high probability CT is a CT in which a large number of ART games can be easily added as compared to normal CT. (See FIG. 55 described later).

[Usually ART middle extra lottery table]
FIG. 51 is a configuration diagram of a normal ART middle-of-the-day sort lottery table used in the super sort lottery of the number of ART games normally performed during ART. The name of the internal winning combination shown in FIG. 51 corresponds to the name of the sub-flag described above.

  Normally, the ART extra-lot lottery table defines the correspondence between the internal winning combination, various lottery results of non-over-lot lottery (non winning / over 10 G to 300 G), and information of lottery value associated with each lottery result.

<Playability during CT>
Next, with reference to FIGS. 52A to 52C, the flow of a game during CT will be described. 52A and 52B are views mainly showing the outline of the game flow in CT at the time of winning the sub-flag EX "triple chiri lip", and FIG. 52C shows the outline of flag conversion processing performed during CT. FIG.

[Game content during CT]
In the pachislot machine 1 of the present embodiment, one set of eight games (eight games) is played in the CT. During the CT period, additional lottery of the number of ART games is performed based on the internal winning combination for each game. And, when winning the extra lottery, the subtraction of the unit game number (the number of games) of the CT game is not performed, while when the extra lottery is not winning, the unit game number of the CT game (game Subtraction) is performed. Therefore, during the CT period, in the game in which the number of ART games is added, the CT does not end, and in the same set, the CT is ended when eight games in which the number of ART games is not added is implemented. .

  Further, in the present embodiment, as shown in FIGS. 52A and 52B, when the sub-flag EX “triple chiri lip” is won during the CT period, that is, the internal winning combination “F_positive chili lip” or “F_1 positive chili lip” is won. And, when winning a flag conversion lottery, one set of eight CT games are reset (stocked). Then, the reset (stocked) CT game set is started after the CT game set is finished.

  For example, after a unit game which is not won for ART game number addition lottery within the same set is performed seven times, CT is ended when one CT game where the ART game number is not added is performed. If the sub-flag EX "triple chiri lip" is won, the CT game is reset. As a result, after the CT game is reset, the CT does not end until eight unit games, which are not won for the ART game number addition lottery, are performed. Therefore, the gaming period of the CT becomes so long that the sub-flag EX "triple chiri lip" is won.

[Flag conversion during CT]
Next, referring to FIG. 52C, a method of flag conversion lottery performed during CT will be described. As described above, in the present embodiment, when the sub-flag EX “triple chili lip” is won during the CT period (the internal winning combination “F_positive chili lip” or “F_1 positive chili lip” is won, and the flag conversion lottery is awarded. Then, CT is reset (stocked). Also, as shown in the flag conversion / lottery table during CT in FIG. 54 described later, when the internal winning combination "F_positive_lip" or "F_1_positive_lip" wins during CT, it always wins the flag conversion / lottery (sub-flag EX " It will always be converted to "triple chili lip". That is, in the present embodiment, CT is always reset when the internal winning combination "F_certain lip" or "F_1 certain lip" is won during CT.

  In addition, in the flag conversion lottery in the case where any of the internal winning combinations "F_reach eyes Lip A" to "F_reach eyes Lip D" is won, the flags are determined based on three types of flag conversion tables (tables 0 to 2). The winning probability of the conversion lottery is controlled. Specifically, as shown in FIG. 52C, table 0 is a flag conversion table having the lowest probability of being converted into sub-flag EX “reached-eye lip”, and table 1 is converted into sub-flag EX “reached-eye lip” It is a flag conversion table with the second lowest probability, and Table 2 is a flag conversion table with the highest probability of being converted into the sub-flag EX “reach target”. Incidentally, when the sub flag EX “reach eye lip” is won during CT, CT is newly assigned as shown in the after-set number-in-CT during FIG.

  Further, in the present embodiment, in the normal CT, as shown in FIG. 52C, the flag conversion table is determined based on the ART level. On the other hand, in high probability CT, table 0 is always determined as a flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, with reference to FIGS. 53 to 56, various data tables used in the lottery process performed during CT will be described. Note that various data tables described below are stored in the main ROM 102.

[CT during table lottery table]
FIG. 53 is a configuration diagram of a during-CT table lottery table used when determining a table to be used for flag conversion / lottery from among three-stage flag conversion tables (tables 0 to 2).

  The during-CT table lottery table shows the correspondence between each state such as the ART level and the type of CT to be executed from now, the type of the flag conversion table (tables 0 to 2), and information of the lottery value corresponding to each type. Specify. The during-CT table lottery table is referred to when it is determined that the CT lottery is to be transferred to CT or at the start of CT.

[CT flag conversion lottery table]
FIG. 54 is a configuration diagram of a during-CT flag conversion / lottery table used in the flag conversion / lottery performed during CT.

  The flag conversion lottery table during CT includes an internal winning combination (one of “F_certain lip,” “F_1 cerile lip, and“ F_reach eye lip A ”to“ F_reach eye lip D ”), and each flag conversion table ( A correspondence between a lottery result (without conversion / conversion) of flag conversion lottery in tables 0 to 2) and information of lottery value associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, the flag conversion lottery is always won if the internal winning combination "F_sure chillirip" or "F_1 sure chillirip" wins during CT (the subflag EX "triple chillirep" must be sure) Will be converted).

[CT middle addition lottery table]
FIG. 55 is a configuration diagram of a CT-in-RT addition lottery table used in the addition lottery of the number of ART games performed during CT.

  The CT top-loading lottery table is associated with each combination of the current CT status and the internal winning combination, various lottery results of top-lot lottery (non-winning / 10 games / ... / 300 games), and each lottery result It defines the correspondence with the information on the lottery value. The name of the internal winning combination shown in FIG. 55 corresponds to the name of the sub flag described above, and when a combination other than the internal winning combination (sub flag) shown in FIG. There is nothing to do.

  In addition, in the additional lottery in the normal CT of this embodiment, the form of giving the number of additional games changes in accordance with the number of winning of the sub-flag "triple chiri ripu" (internal winning combination "F_certain ririp" or "F_1 certain chiri ripu"). Do.

  Specifically, in the case where the number of winning of the sub-flag "triple chili lip" in the same CT set is 1 to 8 times, it is given by the lottery result "overlay _ 10G" and "overlay _ 20G" shown in FIG. The number of added games is 10 games and 20 games respectively. Therefore, in this case, 10 games are easily determined as the number of ART-added games. In addition, when the number of times of winning of the sub-flag "triple chiri lip" in the same CT set is 9 to 16 times, an additional game provided with lottery results "over 10 G" and "over 20 G" shown in FIG. The number is 20 games together. That is, the number of added games (lottery result) corresponding to the lottery value “extremely high” of the sub-flag “three consecutive chills” in FIG. 55 is promoted to 20 games. Therefore, in this case, 20 games are easily determined as the number of ART-added games.

  In addition, when the number of times of winning of the sub-flag "triple chiri lip" in the same CT set is 17 to 24 times, the additional game provided with the lottery results "over 10 G" and "over 20 G" shown in FIG. The number is 30 games together. That is, the number of added games (lottery result) corresponding to the lottery values “extremely high” and “extremely low” of the sub-flag “three consecutive chills” in FIG. 55 is promoted to 30 games. Therefore, in this case, "30 games" can be easily determined as the number of ART-added games. Furthermore, when the number of times of winning of the sub-flag "triple chiri lip" in the same CT set is 25 or more, the number of added games provided with the lottery results "over 10 G" and "over 20 G" shown in FIG. Both have 50 games. That is, the number of added games (lottery result) corresponding to the lottery values “extremely high” and “extremely low” of the sub-flag “three consecutive chills” in FIG. 55 is promoted to 50 games. Therefore, in this case, "50 games" can be easily determined as the number of ART-added games.

  As described above, in the pachislot machine 1 according to the present embodiment, it is possible to increase the number of ART games that can be added by one additional lottery in accordance with the number of winning of the sub-flag "triple chiri lip" in CT. In addition, as described above, in the present embodiment, as long as the addition of the number of ART games is performed, CT does not end, and when the subflag EX “triple chiri lip” is won, CT re-set (stock) Is done. Therefore, in the present embodiment, as CT continues to the player, it is possible to hold expectation for an increase in the additional amount per game, and the interest in CT can be improved. In addition, the number of wins of the sub-flag “three consecutive chillirip” that triggers an increase in the amount of additional game per game is the number of times (9 or more) greater than the number of basic games (8 times) for one set of CTs. Can be prevented from giving an excessive profit to each other, and a profit can be balanced between the player and the game arcade.

  In the present embodiment, the number of winnings of the above-mentioned sub-flag “three consecutive chillirip” (internal winning combination “F_certain ririp” or “F_1 certainty ririp”) is the number counted in the same CT set, but The present invention is not limited to this. For example, a new CT may be included in the "in the same CT set" if it is awarded the set number added lottery performed during CT.

[Set number added during CT lottery table]
FIG. 56 is a configuration diagram of a CT number-in-the-set number addition lottery table used in CT set addition lottery performed during CT.

  During CT set number addition lottery table, each combination of the current CT status and internal winning combination (sub-flag "reach eye lip (reach eye lip 1 to 4)", and various lottery results of the extra lottery (not winning / normal The correspondence between CT winning / high probability CT winning) and information on lottery values associated with each lottery result is defined.

  As evident from the set number addition lottery table during CT, if you win either internal winning combination "F_reach eyes Lip A"-"F_reach eyes Lip D" during CT, you will always win the CT set addition lottery. (The set of CTs will always be stocked). In addition, the set of stocked CTs is started after the set of currently operated CTs is finished.

<Playability during bonus state>
Next, the flow of the game in the bonus state will be described with reference to FIGS. 57A to 57C. FIG. 57A is a diagram showing the flow of gaming when the gaming state shifts to the bonus state during the normal gaming state (ART not won), and FIG. 57B is the case where the gaming state transitions to the bonus state during normal ART FIG. 57C is a diagram showing a flow of gaming when the gaming state shifts to a bonus state during CT.

  In the pachislot 1 of the present embodiment, as shown in FIGS. 57A to 57C, in terms of gaming characteristics, normal BB and special BB are provided as bonus types, and the type of this bonus is determined when shifting to the bonus state. Be done. At this time, if the special BB is determined, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the normal BB is determined, the gaming state of the transition destination differs depending on the state before the transition to the bonus state.

  When the gaming state shifts from the normal gaming state to the normal BB, as shown in FIG. 57A, in the game during the normal BB, ART lottery is performed based on the internal winning combination. Then, when winning the ART lottery, after the end of the bonus state, the gaming state shifts to the normal ART via the ART preparation state. In this case, in the game in the bonus state after winning ART lottery, additional lottery of ART game number is performed.

  When the gaming state shifts from the normal ART to the normal BB, CT lottery is performed at the end of the normal BB, as shown in FIG. 57B. The winning probability of this CT lottery is 50%, and upon winning, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, if the CT lottery is not won, the gaming state transitions to the normal ART via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state shifted from the ART, additional lottery of the number of ART games is also performed.

  When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 57C, after the bonus state ends, the gaming state shifts to CT via the ART preparation state. In addition, in the game in the bonus state shifted from CT, additional lottery of the number of ART games is also performed.

<Various data tables used in games in bonus state>
Subsequently, various data tables used in the lottery process performed in the game in the bonus state will be described with reference to FIGS. 58 to 60. Note that various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 58 is a configuration diagram of a bonus type random determination table used when determining bonus types (normal BB, special BB).

  The bonus type lottery table includes each gaming state (CT and other than that) before shifting to the bonus state, various lottery results (bonus type: normal BB / special BB), and lottery values corresponding to each lottery result. Define correspondence with information. The bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[Above number of ART games during bonus plus lottery table]
FIG. 59 is a block diagram of a lottery table for the number of ART-in-bonus bonus games used in the ART lottery and the number of ART games played in the game in the bonus state.

  The bonus ART game number addition lottery table is associated with each combination of the current bonus type and the internal winning combination and various lottery results (non winning / 5 games / ... / 300 games) of the additional lottery, and each lottery result It defines the correspondence with the information of the extracted lottery value.

  In the present embodiment, in the ART non-winning state (in the normal BB transitioning from the normal gaming state until winning the ART lottery), the bonus ART game number-added lottery table is used for ART lottery. More specifically, if the number of added games of one or more (50 games or more in the example shown in FIG. 59) is determined by lottery using a bonus ART game number addition lottery table while ART is not won, ART is selected. As well as winning a lottery, the corresponding number of games is given as the number of ART games. On the other hand, in the state after winning the ART, the number-of-bonus ART game number-added lottery table is used only for the addition of ART game number-plus lottery.

[At the end of bonus CT lottery table]
FIG. 60 is a configuration diagram of a bonus end time CT lottery table used in CT lottery performed at the end of the bonus state.

  At the end of the bonus CT lottery table, each combination of bonus type (normal BB, special BB) and gaming state (during normal CT, high probability CT during) before transition to bonus state, and various lottery results of CT lottery ( Define the correspondence between non winning / normal CT winning / high probability CT winning) and information of lottery values associated with each lottery result. As is apparent from the CT lottery table at the end of the bonus, for example, when the normal BB is performed during the normal ART, the CT is won with a 50% probability at the end of the bonus state.

<Extra playability in the general gaming state>
Next, with reference to FIG. 61, the flow of exceptional gaming in the normal gaming state will be described.

  In the flow of the basic gaming state in the pachislot 1 of the present embodiment, the gaming state shifts from the normal gaming state to CZ during the normal gaming state, and the gaming state shifts to the ART gaming state by winning ART lottery in CZ. Do. And, in the present embodiment, the ART gaming state is realized by giving a notification in the RT4 state. Further, in the present embodiment, as shown in FIG. 61, transition control of the RT state is performed according to the symbol combination to be stopped and displayed.

  The symbol combination for shifting the RT state is a case where the stop display is performed (see FIG. 24) according to the order (pushing order) of the player's stop operation, and therefore, the notification is not performed. By chance, the RT state may shift to the RT4 state. Also, in the RT4 state, any of the internal winning combination "F_reach eyes Lip A" to "F_reach eyes Lip D" may be determined, so even during the general gaming state (non-ART), It is possible to display reach eyes (symbol combinations relating to “reach eyes lip” for short) to which special benefits are given.

  Therefore, in the pachislot 1 of the present embodiment, as shown in FIG. 61, the RT state shifts to the RT4 state by chance during the normal gaming state (non-ART), and symbol combinations relating to the "reach eye lip" can be displayed. If it becomes a state, it is possible to shift the gaming state to the ART gaming state (usually ART) without passing through the CZ.

  More specifically, if one of the internal winning combination "F_reach eyes Lip A" to "F_reach eyes Lip D" is determined in the normal gaming state and the RT4 state, flag conversion lottery is performed, If this flag conversion lottery is won, a notification (navigation) for displaying a symbol combination relating to the abbreviation "reach eye lip" is performed and an ART right is granted. On the other hand, if any of the internal winning combinations "F_reach eyes Lip A" to "F_reach eyes Lip D" is determined during the normal gaming state and the RT4 state, if the flag conversion lottery is not won, The notification for displaying the symbol combination relating to the abbreviation “replay” is performed, and control is performed such that the symbol combination relating to the abbreviation “reach eye lip” is not displayed.

<Various data tables used for exceptional game control in the general game state>
Next, with reference to FIG. 62, a data table used in the lottery processing performed in the exceptional game control in the general game state described above will be described. The data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 62 is a configuration diagram of a non-ART flag conversion lottery table used in flag conversion lottery performed in a game in the normal gaming state and in the RT4 state.

  The non-ART flag conversion lottery table includes an internal winning combination (“F_reach eye lip A” to “F_reach eye lip D”), a lottery result of flag conversion lottery (without conversion / conversion), and each lottery result It defines the correspondence with the information of the extracted lottery value.

<Informing function by control on the main side>
In the conventional pachislot, notification (navigation) of information (such as pushing order) of stop operation of the reel is performed by control of the sub (sub control board 72) side during ART. However, since the presence or absence of this notification affects the player's profit (so-called, balls), in recent years, the main (main control board 71) side that manages the player's profit is required to perform the notification. There is. Therefore, in the pachislot 1 of the present embodiment, as described above, the information display 6 controlled on the main side is provided with an instruction monitor (not shown) for notifying information on the stop operation, and the control on the main side is performed. A function is provided to notify information on the reel stop operation.

  Here, FIGS. 63A to 63D show the correspondence between notification (navi) performed on the main side and notification (navi) performed on the sub side in the pachislot machine 1 according to the present embodiment. FIG. 63A is a diagram showing the correspondence between informing (navi) performed on the main side and informing (navi) performed on the sub side in the ART preparation state, and FIG. 63B is during ART (usually ART or CT). It is a figure which shows the correspondence of the alerting | reporting (navi) performed by the main side in (1), and the alerting | reporting (navi) performed by the sub side. FIG. 63C is a diagram showing the correspondence between the notification (navi) performed on the main side and the notification (navi) performed on the sub side in the RT5 state (between BB1 flags), and FIG. 63D is in the RT5 state. It is a figure in (between BB2 flag), showing the correspondence of informing (navi) performed on the main side and informing (navi) performed on the sub side.

  In the present embodiment, as shown in FIGS. 63A to 63D, on the main (main control board 71) side, information on the reel stop operation is notified by displaying numerical values of “1” to “11” on the instruction monitor. Do. The numerical values “1” to “11” displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

  Specifically, the numerical values “1” to “3” indicate the types of reels on which the first stop operation is performed, and the numerical value “1” means that the first stop operation is performed on the left reel 3L. The numerical value "2" means performing the first stop operation on the middle reel 3C, and the numerical value "3" means performing the first stop operation on the right reel 3R.

  The numerical values “4” to “9” indicate the pushing order to be notified, and the numerical value “4” means that the pushing order is in the order of “left, middle, right”, and the numerical value “5” Means that the order of pressing is "left, right, middle", the number "6" means that the order of pressing is "middle, left, right", the number "7" is The order is "middle, right, left" order, the number "8" means the push order is "right, left, middle" order, the number "9" is the push order It means that it is the order of "right, middle, left".

  In addition, the numbers "10" and "11" respectively indicate the bonus combination, and the number "10" is a symbol combination related to the combination name "C_BB1" (symbol "white 7"-symbol "white 7"- The symbol "white 7" is meant, and the numeral "11" is symbol combination (symbol "blue 7"-symbol "blue 7"-symbol "blue 7") according to the combination name "C_BB2".

  Although the numbers “1” to “11” reported on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be reported, all the players clearly based on the numbers. It is not always possible to grasp the contents of the notification. For example, the player may not be able to grasp the contents of the notification only by displaying the numerical value "6" on the instruction monitor on the main side.

  Therefore, in the pachislot machine 1 of the present embodiment, information on the stop operation of the stop button is notified on the sub side as well as the notification on the main side. Specifically, using the display device 11 (projector mechanism 211 and display unit 212) controlled on the sub side, notification of information related to the stop operation is performed by the control on the sub side.

  For example, when notifying the pressing order of performing the first stop operation on the left reel 3L, the main side displays the numerical value “1” on the instruction monitor, and the sub side displays the left reel in the display screen of the display device 11. The numerical value "1" is displayed above 3L to notify that the left reel 3L is the target of the first stop operation. In addition, when informing the pushing order “middle, left, right”, the main side displays the numerical value “6” on the instruction monitor, and the sub side displays the numerical value above the middle reel 3C in the display screen of the display device 11. “1” is displayed, the numerical value “2” is displayed above the left reel 3L, and the numerical value “3” is displayed above the right reel 3R. This display shows the order of “middle, left, right” Informing that it is. Further, when the internal winning combination "F_BB1" is determined, the main side displays the numerical value "10" on the instruction monitor, and the sub side displays "White 7"-"White 7" on the display screen of the display device 11. -Display information on the symbol combination of "White 7" and notify the player of a symbol to be aimed.

  In addition, the timing which alert | reports by the main side can be set to arbitrary timing if it is a period of one game which alert | reports at least. For example, the notification on the main side may be performed at the timing when the player's start operation is detected (received), or the notification on the main side may be performed at the start of rotation of the reel, or the first stop operation to third Notification on the main side may be performed at the timing at which one of the stop operations is detected. On the other hand, it is preferable that the timing which alert | reports by the sub side is a timing before at least 1st stop operation. Therefore, in the pachi slot 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or at the timing when the rotation of the reel starts. As a result, before the player performs the stop operation, the information on the stop operation is notified on both the instruction monitor on the main side and the display device 11 on the sub side.

  In the ART preparation state, as shown in FIG. 63A, informing (navigation) called “Bell navi”, “Maintenance rip navi”, “RT 3 transition Rip navi” and “RT 4 transition rip navi” is performed by control on the main side. In "Bell navi", when the internal winning combination "F_3 alternative bell_1st" to "F_3 alternative bell_3rd" is determined, the symbol combination (refer to FIG. 29) related to the abbreviation "bell" is stopped and displayed on the effective line. The order of pressing is notified. In "Maintenance Rip Navi", when the internal winning combination "F_Maintenance Lip_1st" to "F_Maintenance Lip_3rd" is determined, the symbol combination (see Fig. 28) relating to the abbreviation "Replay" is stopped and displayed on the effective line. The order of pushing is notified. In “RT3 transition RIPNAVI”, when the internal winning combination “F_RT3 RIP_1st” to “F_RT3 RIP_3rd” is determined, the symbol combination (see FIG. 28) relating to the abbreviation “RT3 transition RIP” is stopped and displayed on the effective line. The push order for causing the user to be notified is informed. In addition, in "RT4 transition Rip Navi", when the internal winning combination "F_RT4 Rip _123" to "F_RT4 Rip _3 rd" is determined, the symbol combination (see Fig. 28) relating to the abbreviation "RT4 transition Rip" is put on the effective line The pushing order for displaying the stop is notified.

  Also, in the ART gaming state (normally ART or CT), as shown in FIG. 63B, by the control on the main side, notification called "Bell navi", "Maintenance Rip navi", "RT 3 Transition Rip navi" and "RT 4 Transition Rip navi" (Navi) is performed. In addition, the game in the ART gaming state (RT4 state) is subjected to flag conversion lottery, and based on the lottery result, symbol combinations relating to "three consecutive chiri ripu", "reach eye lip" or "replay" are displayed. Although the order of pushing is notified, this notification is performed only on the sub side and not on the main side.

  As described above, since the symbol combination relating to the abbreviation “three consecutive chilli lip” or “reach eye lip” is related to the provision of special benefits, the presence or absence of notification affects the player's profit (earnings). Although it seems to be given, in fact in the pachislot 1 of this embodiment, since the special benefit is given based on the lottery result of the flag conversion lottery, the symbol combination displayed is for the privilege to be given It does not affect it. Therefore, for example, in the state of winning the flag conversion lottery, even if the symbol combination relating to the abbreviation "Replay" is stopped and displayed, a special benefit is provided. On the other hand, even if the symbol combination relating to the abbreviation "triple chiri lip" or "reach eye lip" can be stopped and displayed in the state where the flag conversion lottery is not won, no special benefit is given. In the pachislot 1 of the present embodiment, when the symbol combination displayed in this manner does not affect the player's profit (disbursed balls), the sub-side is controlled without notifying on the main side instruction monitor. Notification is performed only on the display device 11.

  Further, in the RT5 state (inter-flag state), as shown in FIGS. 63C and 63D, information to the effect that the player is targeted for the symbol combination relating to the bonus combination carried over as the internal winning combination is notified. For example, when the internal winning combination “F_BB1” is carried over, as shown in FIG. 63C, the control on the main side performs notification (Navi) called “White 7 Navi”, and the internal winning combination “F_BB2 When “” is carried over, as shown in FIG. 63D, a notification (navi) called “blue 7 navi” is performed by the control on the main side.

  In "White 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB1", that is, the symbol combination related to the combination name "C_BB1" ("White 7"-"White 7"-"White 7": see FIG. 28) The information of the stop operation for displaying the stop on the effective line is informed. Also, in "Blue 7 Navi", symbol combinations corresponding to the internal winning combination "F_BB2", that is, symbol combinations related to the combination name "C_BB2" ("Blue 7"-"Blue 7"-"Blue 7": FIG. 28 The information of the stop operation for displaying the stop) on the effective line is notified.

  As described in FIG. 24, when the bonus combination and one of the internal winning combination "Fail", "F_Special 1", "F_Special 2" and "F_Special 3" are determined in the inter-flag state, The symbol combination relating to the bonus combination (BB combination) can be stopped and displayed on the effective line. However, when the internal winning combination other than the internal winning combination “Failure”, “F_Special 1”, “F_Special 2” and “F_Special 3” is won, the symbol combination relating to the bonus combination is made. You can not stop displaying on the effective line. Therefore, in the present embodiment, as shown in FIGS. 63C and 63D, the bonus combination carried over and the internal winning combination "Dear", "F_special role 1", "F_special role 2" and "F_special role" Only when any one of 3) is a win, a notification called "White 7 Navi" or "Blue 7 Navi" by the control on the main side is performed. Therefore, in the present embodiment, notification (navigation) called “white 7 navigation” or “blue 7 navigation” by control on the main side can be performed at an appropriate timing at which the bonus combination can be won.

  In addition, the pachislot 1 of the present embodiment is also provided with a function of performing a bonus notification by, for example, displaying a bonus confirmation screen or turning on a bonus confirmation lamp. Therefore, on the main side, navigation may be performed "white 7 navigation" or "blue 7 navigation" only after notifying (bonus notification) that the bonus combination is determined as the internal winning combination.

  As the bonus notification, for example, effects (so-called continuous effects) performed over a plurality of game periods are performed, and effects such as displaying a bonus confirmation screen according to the result of the continuous effects are generally performed. There is. If "White 7 Navi" or the like is performed on the main side during such a continuous rendering, the result of the continuous rendering will be understood halfway, which may impair the interest. Therefore, in the present embodiment, after the bonus notification is performed, the main control board 71 performs notification (navi) called “white 7 navi” or “blue 7 navi” by the control on the main side.

  In addition, the method of enabling the main side to grasp the timing at which the bonus notification has been made is optional. As one of the methods, when the bonus combination is determined as an internal winning combination, the main control board 71 determines the number of games required until the end of the bonus notification, and after the game of this number of games is digested, "White 7 Navi" or A method of performing notification (navi) called "blue 7 navi" can be considered. More specifically, when determining the number of games required until the end of the bonus notification, the main control substrate 71 notifies the sub control substrate 72 of the number of games. The secondary control board 72 controls the effect according to the number of games, and displays the bonus confirmation screen at the timing when the game of the number of games is digested, thereby grasping the timing at which the bonus notification is performed on the main side. Can. That is, the main control board 71 counts the number of unit games since the bonus combination is determined as an internal winning combination in a state where the bonus combination is not carried over, and after the counting result reaches a predetermined number, the bonus combination is performed. And “White 7 Navi” or “White 7 Navi” when it is determined that one of the internal winning combinations “Dear”, “F_Special 1”, “F_Special 2” and “F_Special 3” is selected as the internal winning combination. Do the Blue 7 Navi.

  As another method, a method may be considered in which the bonus notification is controlled not on the sub side but on the main side. More specifically, when the bonus combination is determined as an internal winning combination in a state where the bonus combination is not carried over, the main control board 71 determines an effect (at least the number of games required for the effect) to be executed on the display device 11, The sub control board 72 is notified. By executing the effect notified by the sub control board 72 and displaying the bonus determination screen, it is possible to grasp the timing at which the bonus notification has been made on the main side.

  In addition, the main side may be configured to be able to grasp the timing at which the bonus notification is performed by another method other than the two methods described above. In this case, since the main control board 71 can not receive the signal from the sub control board 72 or the like, it is necessary to grasp the timing at which the bonus notification is performed based on the signal that can be received by the main control board 71. For example, when the main control board 71 can receive a signal accompanying the stop operation, a predetermined stop operation (for example, other than forward pressing) is performed in a state where the bonus combination is determined as the internal winning combination. In addition, a method of giving a bonus announcement can be considered. Specifically, the sub control board 72 acquires information on the internal winning combination and information on the stop operation from the main control board 71, and performs a bonus notification when the combination of these pieces of information is a predetermined combination. By adopting such a bonus notification method, it is possible to grasp the trigger of the bonus notification even on the main control board 71, so that it is possible to know the timing at which the bonus notification was made on the main side.

<Description of operation of main control circuit>
Next, contents of various processing executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS.

[Process at power on (reset interrupt)]
First, power-on (reset interrupt) processing of the pachislot 1 performed by the control of the main CPU 101 will be described with reference to FIG. FIG. 64 is a flow chart showing a procedure of power-on (reset interrupt) processing. In the power-on (reset interrupt) process shown in FIG. 64, when the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 has been started, the reset signal After being output to the “XSRST” terminal and subjected to a delay operation in the security mode, execution is performed based on an interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 performs initialization processing of the timer circuit 113 (PTC) (S1). In this process, the main CPU 101 performs initial setting of the timer circuit 113. Specifically, the main CPU 101 sets a division ratio in a timer prescaler register (not shown), performs interrupt enable setting in a timer control register (not shown), and the like. Set the initial count value.

  Next, the main CPU 101 executes initialization processing of the first serial communication circuit 114 (SCU1) for communication between the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. An initialization process is performed (S2). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S3). Next, the main CPU 101 performs a write test on the main RAM 103 (S4).

  Next, the main CPU 101 determines whether or not the writing to the main RAM 103 has been normally performed as a result of the writing test (S5).

  When the main CPU 101 determines in S5 that writing to the main RAM 103 has not been normally performed (when the determination in S5 is NO), the main CPU 101 performs the processing of S13 described later. On the other hand, when the main CPU 101 determines that the writing to the main RAM 103 has been normally performed in S5 (when the determination in S5 is YES), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. To obtain (S6).

  Next, the main CPU 101 determines, based on the acquired state of the timer control register, whether the current state is the occurrence timing of the interrupt processing (S7). Specifically, the main CPU 101 determines whether or not 1.1172 ms has elapsed since the start of the timer count, based on the acquired state of the timer control register.

  In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. Thereafter, the status of the timer circuit 113 can be acquired by reading information of the timer control register (not shown). Then, in the present embodiment, a bit (determination bit) capable of determining (referring) whether or not the current state is the occurrence timing of the interrupt processing (whether the timer is in the interrupt state) in the timer control register ) Is provided.

  Therefore, in the process of S6, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S7, the main CPU 101 turns on / off the determination bit in the timer control register. By referring to “1” / “0”), it is determined whether or not the current state is the occurrence timing of the interrupt processing. When 1.1172 ms has elapsed since the timer circuit 113 starts counting (if the count value of the timer circuit 113 is 0), the determination bit is turned on.

  When the main CPU 101 determines in S7 that the current state is not the occurrence timing of the interrupt processing (when the determination in S7 is NO), the main CPU 101 returns the processing to the processing of S6 and repeats the processing of S6 and subsequent steps.

  On the other hand, when the main CPU 101 determines in S7 that the current state is the occurrence timing of the interrupt processing (when the determination in S7 is YES), the main CPU 101 sets a command transmission start timer (S8). The command transmission start timer is a timer for managing an activation delay period described later (see FIG. 120 described later), and a period from when the command transmission start timer is set to 0 until the main control circuit 90 ( Command data is not transmitted from the main control board 71) to the sub control circuit 200 (sub control board 72) (see FIG. 115 described later). As a result, when the pachi slot 1 is powered on, the time required for the start control of the sub CPU 201 (the time until the command can be received) is secured. That is, by setting the command transmission start timer, transmission of communication data (command data) by communication data transmission processing is delayed for a period corresponding to this. In the present embodiment, “21801” (21801 × 1.1172 ms = about 24.3561 seconds) is set as the value of the command transmission start timer in S8. However, the value of the command transmission start timer can be appropriately changed according to the specifications of the sub control circuit 200 mounted at the same time.

  The command transmission start timer is a software timer allocated by 2 bytes in the gaming RAM area of the main RAM 103, and is arranged at an address which is not erased in a setting change confirmation process (see FIG. 66) described later.

  Next, the main CPU 101 performs a thumb check process (outside of specification) (S9). In this process, the main CPU 101 performs a thumb check process on the main RAM 103, but the work of this process is performed in an extra-specified work area (see FIG. 11C) in the main RAM 103. Also, the program used in the sum check process is stored in the non-prescribed area in the main ROM 102 (see FIG. 11B). The details of the thumb check process will be described later with reference to FIGS. 72 and 73 described later.

  After the process of S9, the main CPU 101 determines whether the setting key switch 54 is in the on state (S10).

  When the main CPU 101 determines in S10 that the setting key type switch 54 is in the on state (when the determination in S10 is YES), the main CPU 101 performs the processing of S15 described later. On the other hand, when the main CPU 101 determines that the setting key type switch 54 is not in the on state in S10 (when S10 is NO determination), the main CPU 101 determines a thumb check based on the result of the thumb check process of S9. It is determined whether the result is normal (S11).

  When the main CPU 101 determines in S11 that the sum check determination result is not normal (when the determination in S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S11 that the sum check determination result is normal (when the determination in S11 is YES), the main CPU 101 performs a game recovery process (S12). In this process, the main CPU 101 performs a process of returning the state of the game to the state before the detection of power interruption. The details of the game return processing will be described later with reference to FIG. 65 described later.

  If S5 or S11 is NO, the main CPU 101 displays a character string “88” indicating occurrence of an error on the information display 6 (7-segment LED display) (S13). Thereafter, the main CPU 101 repeats the WDT clear process (S14).

  Here, the process returns to step S10 again, and if the determination in step S10 is YES, the main CPU 101 performs setting change confirmation processing (S15). In this processing, the main CPU 101 mainly performs generation and storage processing of a setting change command at the start of the setting change. The details of the setting change confirmation process will be described later with reference to FIG. 66 described later.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address of "RAM abnormal or setting change start" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the game is started from the start address. Clear (clear) the information up to the final address of the RAM area. Then, after the processing of S16, the main CPU 101 starts main processing (see FIG. 74 described later) described later.

[Game return processing]
Next, with reference to FIG. 65, the game recovery processing performed in S12 in the power-on (reset interrupt) processing (see FIG. 64) will be described. FIG. 65 is a flowchart showing the procedure of the game return process.

  First, the main CPU 101 sets the stack pointer at power-off to the stack pointer (SP) (S21). Next, the main CPU 101 determines whether the command transmission start timer has counted up (S22). When the main CPU 101 determines in S22 that the command transmission start timer has not counted up (when the determination in S22 is NO), the main CPU 101 repeats the processing of S22.

  On the other hand, when the main CPU 101 determines in S22 that the command transmission start timer has counted up (when the determination in S22 is YES), the main CPU 101 determines the on-edge data before one interrupt processing of the input port and The set on-edge data is cleared (turned off) (S23). Next, the main CPU 101 reads backup data of the output port from an output port backup storage area (not shown) of the main RAM 103, and sets the backup data in the output port (S24). Next, the main CPU 101 reads the data of the input port, and stores the data in the data storage area (input port storage area 1 and input port storage area 2) before the current and one interrupt processing of the input port (S25) .

  Next, the main CPU 101 sets the address of the rotation control data storage area (S26). Next, the main CPU 101 sets the number of reels to be checked ("3" in the present embodiment) (S27).

  Next, the main CPU 101 acquires reel control management information of the predetermined reel (data related to fluctuation control of display row at the time of power failure) based on the set address of the spinning drum control data storage area (S28). The reel control management information (variation control management information of the display row) is information related to the control state (rotational state) of each reel, and is backed up and stored at power-off.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation state during constant speed waiting or constant speed while the reel is accelerating (S29).

  When the main CPU 101 determines in S29 that the condition of S29 is not satisfied (when the determination in S29 is NO), the main CPU 101 performs the processing of S32 described later. On the other hand, when the main CPU 101 determines in S29 that the condition of S29 is satisfied (when the determination in S29 is YES), the main CPU 101 clears the rotation control data (reel control management information) (S30). By this process, after the game is recovered, the rotation control of the reel is started from the acceleration process. Next, the main CPU 101 sets an operation timing value of the reel (execution start timing “1” of the drum control data) (S31). When “1” is set to the operation timing of the reel, the main CPU 101 accelerates the rotation control of the reel because the excitation change timing comes within the reel control processing (see S903 in FIG. 114 described later). Start from

  After the processing of S31 or when S29 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S32). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S33).

  When the main CPU 101 determines in S33 that the value of the number of reels after subtraction is not “0” (when the determination in S33 is NO), the main CPU 101 changes the reels to be checked, and the process proceeds to S28. Then, the processing after S28 is repeated.

  On the other hand, when the main CPU 101 determines in S33 that the value of the number of reels after subtraction is "0" (when the determination in S33 is YES), the main CPU 101 performs a RAM initialization process (S34). In this process, the main CPU 101 sets the "power return" address in the gaming RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the final address of the game RAM area is determined from the start address. Clear (clear) the information up to the address.

  Next, the main CPU 101 restores the data of all the registers saved at the time of the power failure detection to all the registers (S35). Then, after the processing of S35, the main CPU 101 ends the game recovery processing, and returns the processing to the processing at the time of the interruption detection.

  In the present embodiment, the game return processing is performed as described above. In the game recovery process of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management at power recovery. Information is acquired, and processing required to start re-rotation of the reels is also performed (see the processing in S26 to S33). Therefore, in the present embodiment, even when returning from the power interruption during the rotation of the spinning drum, the reel re-rotation control can be stably performed, and the player does not feel uncomfortable.

[Setting change confirmation process]
Next, with reference to FIG. 66, the setting change confirmation process performed in S15 in the process (see FIG. 64) at the time of power on (reset interrupt) will be described. FIG. 66 is a flowchart of the setting change confirmation process. If the setting key type switch 54 is turned on after the game machine is turned on (that is, in the case of "setting confirmation" for confirming the current setting value), the setting change confirmation is made from S44 described later. The process may be started.

  First, the main CPU 101 performs initialization processing of the non-specified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs a 1-interrupt wait process (S42). In this process, when the command transmission start timer is counting up, the no-operation command is transmitted to the sub control circuit 200 by the communication data transmission process (see FIG. 115) described later. If the command transmission start timer does not count up, no command is transmitted to the sub control circuit 200. Therefore, when the command transmission start timer does not count up, this process is omitted. May be

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address of "RAM abnormal or setting change start" in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and the game is started from the start address. Clear (clear) the information up to the final address of the RAM area.

  Next, the main CPU 101 determines whether the setting key switch 54 is in the on state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for setting the setting value (settings 1 to 6) of the pachislot 1 and is set when the setting key is turned on. The key type switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the on state (S44 is NO determination), the main CPU 101 ends the setting change confirmation processing, and powers on the processing (reset interrupt ) Processing is transferred to the processing of S16 (see FIG. 64). On the other hand, when the main CPU 101 determines in step S44 that the setting key type switch 54 is in the on state (when the determination in step S44 is YES), the main CPU 101 performs medal acceptance prohibition processing (S45). By this processing, the solenoid of the selector 66 (see FIG. 5) is not driven, and the inserted medal is discharged from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets setting change start or setting check start information (005H: first value) in the L register, and performs generation and storage processing of a setting change command (setting change / setting check start) (S46) . In this process, the main CPU 101 generates setting change command data (first command data) to be transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and the command data is generated. It is stored in a communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 67 described later. The setting change command (setting change / setting confirmation start) stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG.

  Next, the main CPU 101 sets the error count relay to the on state (S47). Next, the main CPU 101 performs 7-segment display setting processing of setting values (S48). By this processing, the current setting value can be displayed by the 7-segment LED in the information display 6.

  Next, the main CPU 101 determines which of setting change and setting confirmation has been performed (S49). When the main CPU 101 determines in S49 that the setting change has not been performed (setting confirmation has been performed) (when the determination in S49 is NO), the main CPU 101 performs the processing of S54 described later.

  On the other hand, when the main CPU 101 determines in S49 that the setting change has been performed (setting confirmation has not been performed) (if the determination in S49 is YES), the main CPU 101 determines whether the reset switch 76 is on. It is determined whether or not it is (S50).

  In S50, when the main CPU 101 determines that the reset switch 76 is in the on state (when the determination in S50 is YES), the main CPU 101 updates the setting value (S51). That is, every time the reset switch 76 is operated, the main CPU 101 sequentially updates the set value within the range of “1” to “6”. After the processing of S51, the main CPU 101 returns the processing to the processing of S48, and repeats the processing of S48 and thereafter. On the other hand, when the main CPU 101 determines that the reset switch 76 is not in the on state in S50 (when the determination in S50 is NO), the main CPU 101 determines whether the start switch 79 is in the on state (S52) .

  In S52, when the main CPU 101 determines that the start switch 79 is not in the on state (when the determination in S52 is NO), the main CPU 101 returns the process to the process of S48 and repeats the processes after S48. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is on (when the determination in S52 is YES), the main CPU 101 sets the setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  If the determination in S49 is NO or after the processing in S53, the main CPU 101 determines whether the setting key switch 54 is in the off state (S54).

  When the main CPU 101 determines in S54 that the setting key type switch 54 is not in the off state (S54 is NO), the main CPU 101 repeats the processing of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (when the determination in S54 is YES), the main CPU 101 determines which of the setting change and the setting confirmation has been performed. (S55).

  When the main CPU 101 determines in S55 that the setting change has not been performed (setting confirmation has been performed) (when the determination in S55 is NO), the main CPU 101 performs the processing of S57 described later. On the other hand, when the main CPU 101 determines in S55 that the setting change has been performed (setting confirmation has not been performed) (if S55 is YES), the main CPU 101 performs a RAM initialization process (S56). . In this process, the main CPU 101 sets an address (following the setting value storage area) (not shown) in the game RAM area of the main RAM 103 shown in FIG. 11C to the start address of the initialization start. It sets and erases (clears) the information from the top address to the final address of the gaming RAM area.

  After the processing of S56 or when S55 is NO, the main CPU 101 sets the information on the end of setting change or setting confirmation end (004H: second value) in the L register, and the setting change command (setting change / setting confirmation end) ) Is generated (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process, and the command data is generated. It is stored in a communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 67 described later. Also, the setting change command (setting change / setting confirmation end) stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 in the processing (see FIG. 64) at power-on (reset interrupt).

[Setting change command generation and storage processing]
Next, the setting change command generation and storage process performed in S46 and S58 in the setting change confirmation process (see FIG. 66) will be described with reference to FIG. FIG. 67 is a flowchart of the setting change command generation and storage process.

  First, the main CPU 101 sets information of set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets the information of the RT state in the C register (S62). Next, the main CPU 101 sets command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 performs communication data storage processing (S64). In this process, main CPU 101 performs the information set in each register in S61 to S63 and the information set in L register in S46 or S58 (see FIG. 66) (setting change start / setting change end / setting end as setting status / Setting confirmation start / setting confirmation end) is used to generate setting change command data, and the generated command data is stored in the communication data storage area. The details of the communication data storage process will be described later with reference to FIG. 68 described later.

  After the processing of S64, the main CPU 101 ends the setting change command generation and storage processing. When the setting change command generation and storage process performed in S46 in the setting change confirmation process (see FIG. 66) is ended, the main CPU 101 performs the process of the setting change confirmation process (see FIG. 68) after the process of S64. Transfer to the process of S47. In addition, when the setting change command generation and storage process performed in S58 in the setting change confirmation process (see FIG. 66) is ended, the main CPU 101 ends the setting change command generation and storage process after the process of S64. The change confirmation process (see FIG. 66) also ends.

[Communication data storage process]
Next, with reference to FIG. 68, for example, the communication data storage process performed in S64 in the setting change command generation and storage process (see FIG. 67) will be described. The communication data storage process is executed not only at the time of generation of the setting change command but also at the time of other command generation. FIG. 68 is a flowchart of the communication data storage process.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area in the main RAM 103 as parameters 1 and 2 of the communication command, respectively (S72).

  Next, the main CPU 101 stores the data set in the D register and the E register in the communication data temporary storage area in the main RAM 103 as parameters 3 and 4 of the communication command, respectively (S73). Next, the main CPU 101 stores the data set in the B register and C register in the communication data temporary storage area in the main RAM 103 as data of parameter 5 and RT state of the communication command, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

  After the process of S76, the main CPU 101 determines whether there is a space in the communication data storage area in the main RAM 103 (S77). In the present embodiment, a maximum of nine command data can be stored in the communication data storage area.

  In S77, when the main CPU 101 determines that there is no space in the communication data storage area (in the case of NO determination in S77), the main CPU 101 ends the communication data storage processing and, for example, the setting change command generation storage processing ( See also FIG. 68).

  On the other hand, when the main CPU 101 determines in S77 that there is a vacancy in the communication data storage area (when the determination in S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the processing of S71 to S76 described above. Each data is stored (registered) in the communication data storage area as communication data (command data) (S78).

  Next, the main CPU 101 performs communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating a communication data pointer indicating a storage address of communication data in the communication data storage area. The details of the communication data pointer update process will be described later with reference to FIG. 69 described later.

  Then, after the process of S79, the main CPU 101 ends the communication data storage process, and also ends, for example, the setting change command generation and storage process (see FIG. 67).

  As described above, in the present embodiment, when creating communication data (command data) of one packet (8 bytes), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a command data creation method, data stored in each register at the time of command generation is stored as it is in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including an unused parameter is created, the value of the unused parameter becomes an indeterminate value at each creation time. This makes it difficult to analyze the communication data and can prevent fraudulent acts such as goth, and there is no need to add unnecessary goto processing, so the program of the main control circuit 90 by adding goto processing is necessary. The pressure on the volume can be suppressed.

[Communication data pointer update process]
Next, with reference to FIG. 69, communication data pointer update processing performed in S79 in the communication data storage processing (see FIG. 68) will be described. FIG. 69 is a flowchart of the communication data pointer update process.

  First, the main CPU 101 acquires the value of the communication data pointer currently set (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer by one packet (8 bytes) (S82). In this process, when the value of the communication data pointer after update is equal to or more than the upper limit size of the communication data storage area, the main CPU 101 sets the value of the communication data pointer after update to “0”. As a result, all command data stored in the communication data storage area are invalidated (the same state as the discarded state).

  In the present embodiment, the amount of data (one packet) transmitted in one transmission operation is eight bytes. That is, in the present embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of nine command data can be stored in the communication data storage area, the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). Therefore, in the present embodiment, the range of the communication data pointer is "0" to "71", and the value of the communication data pointer after update (when the communication data pointer is updated +8) is "71 (in the process of S82). If the upper limit value is exceeded, set the value of the communication data pointer after updating to "0" (set the address of the communication data storage destination back to the top address), and store the communication data. Invalidate all command data stored in the area (make it the same state as the discarded state). If the value of the communication data pointer is set to “0”, the command data is stored from the start address of the communication data storage area when storing command data in the communication data storage area next time, so it is stored before that. The new command data will overwrite the new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds “71 (upper limit value)”.

  Then, after the processing of S82, the main CPU 101 ends the communication data pointer update processing and also ends the communication data storage processing (see FIG. 68).

[Power-off (external) processing]
Next, power-off (external) processing of the pachislot 1 performed by the control of the main CPU 101 will be described with reference to FIG. FIG. 70 is a flowchart of the power-off (external) process. In the power-off (external) process shown in FIG. 70, when the power management circuit 93 detects a drop (power-off) of the power supply voltage supplied to the microprocessor 91, the power-off detection signal is transmitted to the microprocessor 91. , And is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads data set in the power failure detection port (S92).

  Next, the main CPU 101 determines whether the power failure detection port is in the on state (S93).

  When the main CPU 101 determines in S93 that the power failure detection port is not in the on state (when the determination in S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 ends the power-off (external) processing. Note that these processes performed when S 93 is NO determination correspond to the process of the measure against the instantaneous blackout that occurs when the power management circuit 93 momentarily detects the power failure.

  On the other hand, when the main CPU 101 determines that the power failure detection port is in the on state in S93 (when the determination in S93 is YES), the main CPU 101 sets the medal insertion prohibition and sets the hopper device 51 to stop. (S95).

  Next, the main CPU 101 stores the value of the stack pointer (SP) currently set in the stack area of the gaming RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 executes checksum processing of the main RAM 103 (S97). Note that this process is performed in an extra-specified work area (see FIG. 11C) in the main RAM 103. Also, the program used in the checksum generation process is stored in the non-prescribed area in the main ROM 102 (see FIG. 11B). The details of the checksum generation process will be described later with reference to FIG. 71 described later.

  Next, the main CPU 101 sets the access prohibition to the main RAM 103 (S98). Then, after the process of S98, an infinite loop process is performed until the power is stopped (until the power supply voltage reaches a voltage at which the main CPU 101 can not operate).

[Checksum generation processing (out of specification)]
Next, with reference to FIG. 71, the checksum generation process performed in S97 in the power-off (external) process (see FIG. 70) will be described. FIG. 71 is a flowchart of the checksum generation process.

  First, the main CPU 101 stores the current value of the stack pointer (SP) (in-use address of the stack area of the gaming RAM area) in the non-regulation stack area of the non-regulation RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the extra stack area to the stack pointer (S102). Next, the main CPU 101 sets the upper address value (F0H) of the RAM address (the address of the non-specified stack area) in the Q register (S103). Next, the main CPU 101 sets a power failure occurrence flag (S104).

  Next, the main CPU 101 sets the calculation start address of the sum value in the gaming RAM area to the stack pointer, and the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2" in the sum calculation counter It sets (S105). The sum calculation counter is a counter for determining an end trigger of the sum value calculation and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation processing of the game RAM area of the main RAM 103 is ended.

  Next, the main CPU 101 clears the HL register to 0 (sets the value "0") (S106). By this processing, the initial value "0" of the sum value is set.

  Next, the main CPU 101 executes an instruction code called "POP instruction", and sets the data (storage value) of a 2-byte area from the address of the storage area of the main RAM 103 set in the stack pointer (SP) to the DE register. Read out (S107).

  When the "POP" instruction is executed, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded to the lower register of the pair register and specified by the stack pointer The data (memory content) stored in the 1-byte area of the address obtained by updating the address by 1 is loaded into the upper register of the pair register. Also, when the “POP” instruction is executed, address update processing (processing to add “2” of address) is performed to the address set in the stack pointer (SP) by 2 bytes.

  Therefore, in the process of S107, the data (memory content) stored at the address specified by the stack pointer is loaded into the E register, and is stored at the address obtained by adding "1" to the address specified by the stack pointer. Data (memory contents) are loaded into the D register.

  After the process of S107, the main CPU 101 performs a process of calculating a sum value (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

  Next, the main CPU 101 subtracts one from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether the value of the sum calculation counter after the update is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination in S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the process of S107 and subsequent steps. That is, the processing of S107 to S110 is repeated until the sum value calculation processing of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (when the determination in S110 is YES), the main CPU 101 determines in the DE register the non-specified RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-specified sum count value is set in the sum calculation counter (S111). The nonstandard-use sum count value is the number of bytes of the nonstandard-use storage area. Therefore, if the sum calculation counter set in S111 becomes “0”, the sum value calculation process of the non-specified RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 is completed.

  Next, the main CPU 101 reads out data (stored value) of an area of 1 byte from the address of the non-specified RAM area set in the DE register to the A register (S112).

  Next, the main CPU 101 performs a process of calculating a sum value (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

  Next, the main CPU 101 adds one to the address stored in the DE register and subtracts one from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether the value of the sum calculation counter after the update is “0” (S115).

  In S115, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination in S115 is NO), the main CPU 101 returns the process to the process of S112 and repeats the processes after S112. That is, the process of S112 to S115 is repeated until the process of adding the sum value of the non-specified RAM area of the main RAM 103 to the sum value of the gaming RAM area is completed.

  On the other hand, when the main CPU 101 determines in S115 that the value of the sum calculation counter is "0" (when the determination in S115 is YES), the main CPU 101 generates a power failure when the value stored in the HL register is interrupted. Are stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the nonstandard stack area at S101 in the stack pointer (S117). Then, after the processing of S117, the main CPU 101 ends the checksum generation processing, and shifts the processing to the processing of S98 in the power-off (external) processing (see FIG. 70).

[Sum check process (out of specification)]
Next, with reference to FIG. 72 and FIG. 73, the thumb check process performed in S9 in the power-on process (see FIG. 64) will be described. 72 and 73 are flowcharts showing the procedure of the thumb check process.

  First, the main CPU 101 stores the current value of the stack pointer (SP) in the non-specified stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets a value obtained by dividing the number of bytes of the sum value calculation target storage area by “2” in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining an end trigger of the sum value calculation (subtraction process of the sum value), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this processing, the checksum (initial value before subtraction) generated at the time of power interruption is stored in the HL register.

  Next, the main CPU 101 executes the “POP” instruction, and reads out 2-byte data (stored value) (stored value) from the address of the storage area of the main RAM 103 set in the stack pointer (SP) into the DE register (S124) . At this time, data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register by execution of the "POP" instruction, and the address specified by the stack pointer is Data (memory contents) stored in the 1-byte area of the 1-updated address is loaded into the D register. Also, when the "POP" instruction is executed, address update processing (processing to add 2 addresses) of 2 bytes is performed on the address set in the stack pointer (SP).

  Next, the main CPU 101 performs calculation (subtraction) processing of the sum value (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial value of the sum value or the sum value after the previous subtraction processing), and the subtraction is performed. Store the value as a sum value in the HL register.

  Next, the main CPU 101 subtracts one from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether the value of the sum calculation counter after the update is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination in S127 is NO), the main CPU 101 returns the process to the process of S124 and repeats the processes after S124. That is, the processing of S124 to S127 is repeated until the sum value subtraction processing is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is “0” (when the determination in S127 is YES), the main CPU 101 determines in the DE register the non-specified RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-specified sum count value is set in the sum calculation counter (S128). Note that the non-specified sum count value is the number of bytes of the non-specified RAM area.

  Next, the main CPU 101 reads out data (stored value) of an area of 1 byte from the address of the non-specified RAM area set in the DE register into the A register (S129).

  Next, the main CPU 101 performs calculation (subtraction) processing of the sum value (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value.

  Next, the main CPU 101 adds one to the address stored in the DE register and subtracts one from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the value of the sum calculation counter after the update is “0” (S132).

  In S132, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when the determination of S132 is NO), the main CPU 101 returns the process to the process of S129 and repeats the processes after S129. That is, the processing of S129 to S132 is repeated until the subtraction processing of the sum value is completed over the entire area of the non-specified RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is "0" (when the determination in S132 is YES), the main CPU 101 sets "sum error" in the determination result of the thumb check process. (S133). Next, the main CPU 101 determines whether the calculated sum value is “0” (S134).

  In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether the sum value is “0”. In the present embodiment, the sum value is “0” when the value of the sum calculation counter set in S128 becomes “0”, that is, when the subtraction process of the sum value is completed over the entire area of the main RAM 103. In this case, the zero flag of the flag register F is set to "1", and when the sum value is not "0", the zero flag of the flag register F is set to "0". Therefore, when the zero flag of the flag register F is set to “1 (on state)” at the time of the process of S134, the main CPU 101 determines that the sum value is “0”.

  When the main CPU 101 determines in S134 that the calculated sum value is not “0” (when the determination in S134 is NO), the main CPU 101 performs the processing of S139 described later. On the other hand, when the main CPU 101 determines in S134 that the calculated sum value is "0" (when the determination in S134 is YES), the main CPU 101 sets "power failure abnormality" in the determination result (S135). ).

  Next, the main CPU 101 acquires a power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power-off occurrence flag is in the non-power-off state (off state) (S137).

  In S137, when the main CPU 101 determines that the power interruption occurrence flag is in the state of no power interruption (when the determination in S137 is YES), the main CPU 101 performs the processing of S139 described later. On the other hand, when the main CPU 101 determines in S137 that the power interruption occurrence flag is not in the state of no power interruption (when the determination in S137 is NO), the main CPU 101 sets "normal" in the determination result (S138).

  After the process of S138, if S134 is NO or if S137 is YES, the main CPU 101 stores the determination result in the sum check determination result, and clears (turns off) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the nonstandard stack area at S121 in the stack pointer (S140). Then, after the process of S140, the main CPU 101 ends the sum check process, and shifts the process to the process of S10 of the power-on process (see FIG. 64).

[Pachislot main processing by control of main CPU]
Next, with reference to FIG. 74, the main processing (main operation processing) of the pachi slot 1 executed by the control of the main CPU 101 will be described. FIG. 74 is a flowchart showing the procedure of the main process (hereinafter referred to as the main flow).

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address of “at the end of one game” in the game RAM area of the main RAM 103 shown in FIG. 11C as the start address of the initialization start, and from the start address to the game RAM area. Clear (clear) the information up to the final address. Note that the storage area of this range is, for example, a storage area that requires data deletion for each unit game (game) such as an internal winning combination storing area and a display combination storing area.

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this process, the main CPU 101 performs an input check process and the like of each medal sensor (see FIG. 5), the start switch 79 and the like. The details of the medal acceptance / start check process will be described later with reference to FIGS. 75 and 76 described later.

  Next, the main CPU 101 performs random number acquisition processing (S203). In this process, the main CPU 101 selects an internal winning combination random number value (0 to 65535: a value of the random number register 0 of the random number circuit 110 which becomes a hard latch random number) or an effect random number value used in various ART-related lottery 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 to be soft latch random numbers, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 to be soft latch random numbers, etc. are extracted The extracted various random number values are stored in a random number value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 81 described later.

  Next, the main CPU 101 performs internal lottery processing (S204). In this processing, the main CPU 101 performs internal winning combination determination processing by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 82 described later.

  Next, the main CPU 101 performs symbol setting processing (S205). In this process, for example, the main CPU 101 generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag storage area. Etc. The details of the symbol setting process will be described later with reference to FIG. 83 described later.

  Next, the main CPU 101 performs start command generation and storage processing (S206). In this process, the main CPU 101 generates data of a start command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The start command is configured to include parameters (such as sub flags) for specifying the internal winning combination and the like.

  Next, the main CPU 101 performs second interface board control processing (S207). Note that the second interface board control process is executed in the non-specified work area of the main RAM 103. In this process, the main CPU 101 performs, for example, a process for outputting a test signal or the like related to the push order navigation determined by the main control board 71 via the second interface board 302 for a test machine.

  Next, the main CPU 101 performs state-based control processing (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-dependent control process will be described later with reference to FIG. 85 described later.

  Next, the main CPU 101 performs reel stop initialization processing (S209). In this process, the main CPU 101 refers to the reel stop initialization setting table (see FIG. 26), and based on the internal winning combination and the game state, the drawing priority order table selection table number, the drawing priority order table number, and the stop table number. Processing to acquire, processing to store "3" in the stop button non-operation counter, etc. are performed.

  Next, the main CPU 101 performs reel rotation start processing (S210). In this process, the main CPU 101 requests the start of rotation of all the reels. Then, when the start of rotation of all the reels is requested, the driving of three stepping motors (not shown) is performed by an interrupt process (see FIG. 158 described later) which is executed in a fixed cycle (1.1172 msec). The rotation of the left reel 3L, the middle reel 3C and the right reel 3R is started under control. Then, each reel is controlled to accelerate until its rotational speed reaches a constant speed, and thereafter, it is controlled to maintain the constant speed.

  Next, the main CPU 101 performs reel rotation start command generation and storage processing (S211). In this process, the main CPU 101 generates data of a reel rotation start command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The reel rotation start command is configured to include a parameter indicating that the reel rotation start operation has been started.

  Next, the main CPU 101 performs a drawing priority storage process (S212). In this process, the main CPU 101 acquires the pull-in priority data and stores it in the pull-in priority data storage area. The details of the leading priority storing process will be described later with reference to FIG. 100 described later.

  Next, the main CPU 101 performs reel stop control processing (S213). In this process, the main CPU 101 performs control to stop the rotation of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C and the right stop button 17R are pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 105 described later.

  Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores data of the symbol code storage area (see FIG. 35) in the winning operation flag storage area (see FIGS. 28 to 30). Further, in this processing, the main CPU 101 determines whether or not the display combination is displayed on the activated line, and sets the number of medals to be paid out based on the determination result. The details of the winning search process will be described later with reference to FIG. 106 described later.

  Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 combines the hit request flag (internal winning combination) and the winning operation flag (display combination), and determines the presence or absence of an illegal hit error based on the combination result. The details of the illegal hit check process will be described later with reference to FIG. 107 described later.

  Next, the main CPU 101 performs winning check and medal payout processing (S216). In this process, the main CPU 101 performs a process of generating a winning operation command. Further, in this processing, the main CPU 101 performs driving of the hopper device 51 and updating of the number of credits based on the number of payouts of the display combination determined in S214, and performs medal payout processing. The details of the winning check and medal payout processing will be described later with reference to FIG. 108 described later.

  Next, the main CPU 101 performs BB check processing (S217). In this process, the main CPU 101 controls the activation and termination of the bonus state. The details of the BB check process will be described later with reference to FIG. 110 described later.

  Next, the main CPU 101 performs RT check processing (S218). In this process, the main CPU 101 performs transition control of the RT state based on the symbol combination stopped and displayed on the activated line. The details of the RT check process will be described later with reference to FIGS. 111 and 112 described later.

  Next, the main CPU 101 performs CZ · ART end processing (S219). In this process, the main CPU 101 mainly performs CZ pull-back / lottery processing. The details of the CZ · ART end processing will be described later with reference to FIG. 113 described later. Then, after the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal acceptance and start check processing]
Next, with reference to FIGS. 75 and 76, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 74) will be described. 75 and 76 are flowcharts showing the procedure of the medal acceptance / start check process.

  First, the main CPU 101 determines whether the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is “1” or more, the main CPU 101 determines that there is an automatic insertion request. Further, the automatic insertion medal counter is data for identifying whether or not a display combination relating to replay (replay) is established in the previous unit game. When the display combination relating to replay is established, medals for the number inserted in the previous unit game are automatically inserted into the automatic insertion medal counter.

  In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when the determination in S221 is YES), the main CPU 101 performs the processing of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not "0" (when the determination in S221 is NO), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a process of generating and storing a medal insertion command, an LED lighting control process of the number of inserted medals, and the like. The details of the medal insertion process will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 subtracts the value of the automatic insertion medal counter (S223). In this process, the main CPU 101 may subtract the value of the automatic insertion medal counter at one time (for example, “3”) or may subtract “1” at a time. Next, it is determined whether the value of the automatically inserted medal counter after subtraction is "0" (S224).

  In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not “0” (when the determination in S224 is NO), the main CPU 101 returns the process to the process of S222 and repeats the processes after S222.

  On the other hand, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" in S224 (when S224 is a YES determination), or when S221 is a YES determination, the main CPU 101 stores the medal assistance storage. A storage switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals, based on the on / off state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 performs medal input state check processing (S226). Next, the main CPU 101 determines whether or not the medal can be inserted, based on the result of the medal input state check process (S227).

  When the main CPU 101 determines that the medal can not be inserted in S227 (when the determination in S227 is NO), the main CPU 101 performs the processing of S231 described later.

  On the other hand, when the main CPU 101 determines that the medal can be inserted in S227 (when the determination in S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, for example, the main CPU 101 determines whether the medal has passed normally based on the medal sensor input state, or credits the medal when medal insertion is performed beyond the prescribed number. Perform processing etc. The details of the medal insertion check process will be described later with reference to FIGS. 78 and 79 described later.

  Next, the main CPU 101 determines, based on the result of the medal insertion check process, whether the medal insertion or credit is possible (S229).

  In S229, when the main CPU 101 determines that medals can be inserted or credited (in the case of YES in S229), the main CPU 101 performs the processing of S231 described later. On the other hand, when the main CPU 101 determines in S229 that the medal insertion or credit is not possible (in the case of NO determination in S229), the main CPU 101 performs medal acceptance prohibition processing (S230). By this processing, the solenoid of the selector 66 (refer to FIG. 5) is not driven (the solenoid which has been excited is de-energized), and the select plate 804 is shifted from the guide position to the discharge position. It will be discharged from the medal payout opening 24.

  After the processing of S230, if S227 is NO or S229 is YES, the main CPU 101 determines whether the current medal insertion number is the game start number (S231). In the present embodiment, the number of possible games to be started is three (see FIGS. 28 to 30).

  In S231, when the main CPU 101 determines that the current medal insertion number is the game start number (when S231 is YES), the main CPU 101 performs the processing of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of medals inserted is not the game start number (when S231 is NO), the main CPU 101 determines whether or not medals are inserted (S232). ).

  In S232, when the main CPU 101 determines that medals have been inserted (when the determination of S232 is YES), the main CPU 101 returns the process to S226, and repeats the processes after S226. On the other hand, when the main CPU 101 determines that the medal has not been inserted in S232 (in the case of NO determination in S232), the main CPU 101 performs the setting change confirmation process described in FIG. 66 (S233). In this process, the main CPU 101 performs a process of generating and storing a setting change command at the start of setting confirmation. Thereby, regardless of whether or not the gaming state is the bonus state (special prize operating state), it is possible to check the setting value and the hole menu (various history data (error, power failure history, etc.)). Cheating can be suppressed. In the setting change confirmation process performed in S233, even if the setting key type switch 54 is in the OFF state, generation and storage processing of the setting change command (setting confirmation start) including at least information on the current setting value is performed. The command data may be stored in a communication data storage area provided in the main RAM 103. In this way, it may be possible to check whether the setting value is appropriate (within the range of settings 1 to 6) for each game.

  After the process of S233 or when the determination of S231 is YES, the main CPU 101 determines whether the start switch 79 is in the on state (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the on state (when S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines that the start switch 79 is in the on state in S234 (when the determination in S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this processing, the solenoid of the selector 66 (refer to FIG. 5) is not driven (the solenoid which has been excited is de-energized), and the select plate 804 is shifted from the guide position to the discharge position. It will be discharged from the medal payout opening 24.

  Next, the main CPU 101 sets a timer value ("72" in the present embodiment) in the medal monitoring timer (S236). The medal monitoring timer is a timer for monitoring the period until the energized solenoid is demagnetized in the selector 66 (that is, the period for the select plate 804 to move from the guide position to the discharge position). (Refer to FIG. 121 described later.) For example, when the period until the energized solenoid is demagnetized is 80 ms, a timer value for measuring at least a longer period (“about 80.44 ms”) Is set. That is, the medal monitoring timer is actually operated after the start lever 16 is operated (the start switch 79 is turned on) and medal acceptance prohibition control is started when medals for the game start number have been inserted. Monitor the specific period until the acceptance of medals is (physically) prohibited. As a result, together with the start lever ON flag described later, and the medal insertion check 2 process described later, when the medal is inserted during the specific period, the medal is swallowed by mistake (that is, the medal is inserted) However, they are prevented from being accommodated in the hopper device 51 without being counted. The value of the medal monitoring timer can be appropriately changed in accordance with the specification of the selector 66 (mainly solenoid). Further, as long as prevention of the medal's swallowing is secured, the period can be set to a period less than the period until the energized solenoid is completely demagnetized.

  Next, the main CPU 101 sets the start lever ON flag to ON (S237). The start lever ON flag is information for identifying whether or not the start lever 16 has been operated (the start switch 79 has been turned on) when medals for the game start number have been inserted. .

  Next, the main CPU 101 performs medal input check 2 processing (S238). In this process, the main CPU 101 basically performs the same process as the medal insertion check process. The details of the medal insertion check process and the medal insertion check 2 process will be described later with reference to FIGS. 78 and 79 described later.

  Next, the main CPU 101 determines whether the start lever ON flag is off (S239). In S239, when the main CPU 101 determines that the start lever ON flag is in the OFF state (when the determination in S239 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines that the start lever ON flag is not in the off state (that is, in the on state) in S239 (when S239 is NO), the main CPU 101 determines that the medal monitoring timer is "0". It is determined whether there is any (S240). When the main CPU 101 determines that the medal monitoring timer is not “0” (ie, is “1” or more) in S239 (when S240 is NO), the main CPU 101 returns the process to S238, and after S238. Repeat the process of

  On the other hand, when the main CPU 101 determines that the medal monitoring timer is "0" in S240 (if S240 is YES), the main CPU 101 ends the medal acceptance / start check processing, and the main flow of the process ( Move to S203 of FIG.

[Medal input processing]
Next, with reference to FIG. 77, medals are inserted in S222 in the medal reception / start check process (see FIGS. 75 and 76) and in S265 in the medal input check process described later (see FIGS. 78 and 79). The process will be described. FIG. 77 is a flowchart of the medal insertion process.

  First, the main CPU 101 adds "1" to the value of the medal counter (S241). The medal counter is a counter for counting (counting) the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 performs medal insertion command generation and storage processing (S242). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command is configured to include parameters for specifying the number of inserted cards and the like.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 6) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the medal insertion number based on the medal insertion number (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and for example, when the number of inserted medals is three In this case, LED lighting data for lighting all the first to third LEDs for displaying the number of inserted medals is calculated. The method of calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 lights up the corresponding LED for displaying the number of inserted medals, using the calculated LED lighting data (S245). Then, after the process of S245, the main CPU 101 ends the medal insertion process, and the process proceeds to S223 of the medal acceptance / start check process (see FIGS. 75 and 76) or the medal insertion check process (see FIGS. 78 and 79). Move to S253 of reference).

[Medical input check process]
Next, with reference to FIGS. 78 and 79, the medal insertion check process performed in S228 in the medal reception / start check process (see FIGS. 75 and 76) and the medal reception / start check process (FIGS. 75 and 76). A medal input check 2 process performed in S238 in (refer to) will be described. 78 and 79 are flowcharts showing the procedure of the medal insertion check process. The medal insertion check 2 process starts from S253 of the medal insertion check process, and the processes of S253 to S268 are the same as those in the medal insertion check process. The procedure will be described as the input check process.

  First, the main CPU 101 determines whether or not re-playing is in progress (S251).

  In S251, when the main CPU 101 determines that re-game is in progress (when S251 is a YES determination), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (FIG. 75 and FIG. Move to S229 of 76).

  On the other hand, when the main CPU 101 determines in S251 that the game is not being played back (when the determination in S251 is NO), the main CPU 101 performs medal acceptance permission (S252). In this process, the solenoid of the selector 66 (see FIG. 5) is driven (the de-energized solenoid is excited), and the select plate 804 is shifted from the discharge position to the guide position to insert from the medal insertion slot 14 The counted medals are counted and stored in the hopper device 51.

  Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines, based on the on / off state of the BET switch 77, whether or not the bet button (MAX bet button 15a or 1 bet button 15b) has been operated. Next, the main CPU 101 determines whether or not the bet operation has been completed based on the result of the bet button check process of S253 (S254).

  In S254, when the main CPU 101 determines that the bet operation has been completed (when S254 is a YES determination), the main CPU 101 ends the medal insertion check process (or the medal insertion check 2 process), and receives the medal reception process The process then proceeds to S229 of the start check process (see FIGS. 75 and 76) (or S239 of the medal acceptance / start check process (see FIGS. 75 and 76)).

  On the other hand, when the main CPU 101 determines that the bet operation is not completed in S254 (when S254 is NO), the main CPU 101 is in the medal sensor input state (gaming medium reception state) at the current processing time; The medal sensor input state at the time of the previous processing is acquired (S255). The medal sensor input state is information indicating the passing state of the medal received in the medal insertion slot 14 in the selector 66, and is generated by the detection result of each medal sensor (see FIG. 5) of the selector 66.

  In the present embodiment, the medal sensor input state is represented by data of 1 byte (8 bits), and the detection result of the upstream first medal sensor 806 provided at the exit of the selector 66 in the passage direction of the medal is The detection result of the second medal sensor 807 on the downstream side corresponds to the information (“0” or “1”) of the bit 1 corresponding to the information (“0” or “1”) of the bit 0. When passage of a medal is detected by the first medal sensor, "1" is set to bit 0, and when passage of a medal is detected by the second medal sensor, "1" is set to bit 1 Be done. Therefore, the medal sensor input state "00000000B" indicates the state before or after the medal passing (when passing), and the medal sensor input state "00000001B" indicates the state at the start of medal passing, and the medal sensor input state " "00000011B" indicates a state during medal passing, and a medal sensor input state "00000010B" indicates a state immediately before the medal passing completion.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the current processing time has changed from the medal sensor input state at the previous processing time (S256).

  In S256, when the main CPU 101 determines that the medal sensor input state at the current process has not changed from the medal sensor input state at the previous process (when S256 is NO), the main CPU 101 performs S262 described later. Do the processing.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state at the current process has changed from the medal sensor input state at the previous process (when S256 is YES), the main CPU 101 sets the start lever ON flag. Is ON, the start lever ON flag is set to OFF (S257). That is, in this process, main CPU 101 performs the start operation and performs medal insertion during a specific period until medal reception is actually prohibited (physically) after control of medal reception prohibition is started. If it is detected, processing for invalidating the start operation is performed.

  Next, the main CPU 101 generates a normal value (normal change value) of the medal sensor input state obtained at the current processing time by arithmetic processing based on the medal sensor input state at the previous processing time (S258).

  In this process, if the medal sensor input state at the time of the previous process is "00000000B" (when both the first and second medal sensors are not detected), the normal change value of the medal sensor input state is used. If "00000001B" (if the first medal sensor is medal detection and the second medal sensor is not detected) is generated, and the medal sensor input state at the time of the previous processing is "00000001B", then the medal sensor “00000011 B” (when both the first and second medal sensors detect medals) is generated as a normal change value of the input state. Also, in this process, when the medal sensor input state at the time of the previous process is "00000011B", "00000010B" (the first medal sensor is not detected with the medal, and the second change) as the normal change value of the medal sensor input state. When the medal sensor is medal detection) is generated, and the medal sensor input state at the time of the previous processing is “00000010 B”, “00000000 B” (first and second medals) as a normal change value of the medal sensor input state If both sensors are not detected medals are generated.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing is the same as the normal change value generated in S258 (S259). In this determination process, it is determined whether or not a medal retrogression error has occurred, and if the determination condition of S259 is not satisfied, the main CPU 101 determines that a medal retrogression error has occurred.

  When the main CPU 101 determines in S259 that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S258 (when S259 is NO), the main CPU 101 performs the processing of S263 described later. Do.

  On the other hand, when the main CPU 101 determines in S259 that the medal sensor input state in the current process is the same as the normal change value generated in S258 (when the S259 is YES), the main CPU 101 performs the current process. It is determined whether or not the medal sensor input state is a state ("00000000B") at the time of passing the medal (S260). In S260, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is the state of passing medals (when the determination of S260 is YES), the main CPU 101 performs the processing of S264 described later.

  In S260, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the state at the time of medal passing (when S260 is NO determination), the main CPU 101 sets a medal passing check timer (S261). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether the medal has passed the selector 66 or not. Also, the timer value set in this process may be changed, for example, according to the medal sensor input state at the time of the current process.

  After the process of S261 or when S256 is NO, the main CPU 101 determines whether the medal sensor input state at the current process is in the medal passing state ("00000011 B") and the medal passing check timer is stopped. It is determined (S262). In this determination process, it is determined whether a medal passage error (inserted medal passage time error) has occurred, and if the determination condition of S262 is satisfied, the main CPU 101 determines that a medal passage error has occurred.

  In S262, when the main CPU 101 determines that the determination condition of S262 is not satisfied (in the case of NO determination of S262), the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines in S262 that the determination condition of S262 is satisfied (when S262 is a YES determination), or when S259 is a NO determination, that is, a medal passage error or a medal reverse error has occurred. If it is determined that the main CPU 101 determines that the error occurs (S263). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process, for example. The details of the error processing will be described later with reference to FIG. 80 described later. Then, after the process of S263, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  Here, returning to the processing of S260, if the determination of S260 is YES, the main CPU 101 determines whether or not a prescribed number (three in the present embodiment) of medals has been inserted (S264). .

  In S264, when the main CPU 101 determines that the defined number of medals have not been inserted (in the case of NO determination in S264), the main CPU 101 performs the medal insertion processing described in FIG. 77 (S265). Then, after the process of S265, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines that the defined number of medals have been inserted in S 264 (if YES in S 264), the main CPU 101 adds “1” to the value of the credit counter (S 266). ). Next, the main CPU 101 performs medal insertion command generation and storage processing (S267). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG.

  Next, the main CPU 101 determines, based on the value of the credit counter, whether or not the number of credits of medals is the upper limit (50 in the present embodiment) (S268).

  In S268, when the main CPU 101 determines that the number of credits of medals is not the upper limit value (when the determination in S268 is NO), the main CPU 101 returns the process to the process of S253, and repeats the processes after S253. On the other hand, when the main CPU 101 determines in S268 that the number of credits of medals is the upper limit value (when the determination in S268 is YES), the main CPU 101 ends the medal insertion check process (or the medal insertion check 2 process). Then, the process proceeds to S229 of the medal acceptance / start check process (see FIGS. 75 and 76) or S239 of the medal acceptance / start check process (see FIGS. 75 and 76).

Error Handling
Next, with reference to FIG. 80, for example, an error process performed in S263 in the medal insertion check process (see FIG. 78) will be described. FIG. 80 is a flowchart showing the procedure of error processing.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops the driving of the solenoid of the selector 66 (see FIG. 5). Next, the main CPU 101 performs a save process of the medal display number display data (S272). Next, the main CPU 101 performs an error table setting process (S273).

  Next, the main CPU 101 acquires an error factor (S274). The error factor acquired in this process changes according to the process of reading out the error process currently being processed. As error factors targeted in the present embodiment, "hopper empty error", "hopper jam error", "inserted medal passage count error", "inserted medal passage check error", "inserted medal passage check error", An "inserted medal passing time error", an "inserted medal backward error", an "inserted medal auxiliary storage full error", and an "illegal hit error" are defined. For example, when the error process is read out after the process of S259 in the medal insertion check process, in this process, “inserted medal reverse error (Cr)” is acquired as an error factor. Also, for example, when the error process is read after the process of S262 in the medal insertion check process, in this process, “inserted medal passage time error (CE)” is acquired as an error factor.

  Next, the main CPU 101 acquires error display data from the error table and the error cause (S275). For example, when the error cause is "inserted medal retrogression error (Cr)", 1 byte data "01001110B" as error display data to be output to the 7-segment LED of the upper digit among the 2-digit 7-segment LED in this process. Is acquired, and 1-byte data "00001001 B" is acquired as error display data to be output to the lower digit 7-segment LED. In this case, two characters of “Cr” are displayed as error information on the 2-digit 7-segment LED.

  Next, the main CPU 101 performs an error command (occurrence) generation and storage process (S276). In this process, the main CPU 101 generates data of an error command at the time of error occurrence which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of error occurrence stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The error command upon occurrence of an error is configured to include a parameter indicating the occurrence of an error.

  Next, the main CPU 101 performs standby processing for one interruption time (1.1172 ms) (S277). Next, the main CPU 101 determines whether the error is canceled (S278).

  When the main CPU 101 determines in S278 that the error is not canceled (when the determination in S278 is NO), the main CPU 101 returns the process to the process of S277, and repeats the processes after S277.

  On the other hand, when the main CPU 101 determines that the error has been canceled in S278 (when the determination in S278 is YES), the main CPU 101 performs an error cause clear process (S279). Note that this process is performed in the extra operation area of the main RAM 103. Next, the main CPU 101 carries out return processing of the payout number display data of the medals evacuated in S272 (S280).

  Next, the main CPU 101 performs an error command (cancellation) generation and storage process (S281). In this process, the main CPU 101 generates data of an error command at the time of error cancellation, which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area provided in the main RAM 103. The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. The error command at the time of error cancellation is configured to include a parameter indicating the error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and shifts the processing to S253 in the medal insertion check processing (see FIG. 78), for example. When the error is canceled, the cause of the generated error is canceled and the reset switch 76 is pressed to cancel the error state.

[Random number acquisition process]
Next, random number acquisition processing performed in S203 in the main flow (see FIG. 74) will be described with reference to FIG. FIG. 81 is a flowchart of the random number acquisition process.

  First, the main CPU 101 acquires a hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for internal winning combination lottery. Is stored (S291).

  Next, the main CPU 101 generates soft latch random numbers (0 to 65535: random number value for effect used in lottery processing related to ART, random number value in 0 to 255: 1 byte lottery processing) of the random number registers 1 to 7 of the random number circuit. In step S292, the soft latch random number acquisition register is set. Next, the main CPU 101 sets the acquired number (for example, 7) of soft latch random numbers (S293).

  Next, the main CPU 101 acquires the number of acquired soft latch random numbers in a batch, and stores the number of acquired soft latch random numbers in the random number storage area (S294). At this time, the soft latch random number (rendering effect random number value, 2-byte random number value) acquired from the random number register 1 of the random number circuit 110 is hardware acquired from the random number register 0 of the random number circuit in the random number value storage area. The latch random number (random number value for internal winning combination lottery) is stored in an area different from the area where the random number is stored. Then, after the processing of S294, the main CPU 101 ends the random number acquisition processing, and shifts the processing to S204 of the main flow (see FIG. 74). In the present embodiment, in order to store four 2-byte random numbers and four one-byte random numbers, a 12-byte storage area is allocated to the main RAM 103 as a random number storage area.

[Internal lottery process]
Next, with reference to FIG. 82, the internal lottery process performed in S204 in the main flow (see FIG. 74) will be described. FIG. 82 is a flowchart of the internal lottery process.

  First, the main CPU 101 performs check processing of set value and medal insertion number (S301). In this processing, the main CPU 101 performs check processing of the setting value (one of 1 to 6) of the current game and the number of inserted medals (three in the present embodiment).

  Next, the main CPU 101 sets an internal lottery table for general game (see the internal lottery table in the “RT0” state shown in FIG. 16) and the number of times of lottery (53 times in this embodiment) (S302).

  Next, the main CPU 101 determines whether the RB is in operation (S303). When the main CPU 101 determines in S303 that the RB is not in operation (when the determination in S303 is NO), the main CPU 101 performs the processing of S305 described later.

  On the other hand, when the main CPU 101 determines in S303 that the RB is in operation (when the determination in S303 is YES), the main CPU 101 selects an internal lottery table for RB (refer to the internal lottery table shown in FIG. 17B) and The number of lotteries (five in the present embodiment) is set (S304). In this processing, the internal lottery table and the number of lottery times for the normal game set in S302 are overwritten with the internal lottery table and the number of lottery times for RB.

  After the process of S304 or when the determination of S303 is NO, the main CPU 101 acquires the determination data (data related to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether the determination data is data classified by RT state (S306). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination in which the lottery value changes according to the RT state. Specifically, main CPU 101 determines whether or not the address defined in the currently acquired determination data of the lottery target combination is an address in the RT condition-based lottery value selection table (not shown). .

  In S306, when the main CPU 101 determines that the determination data is not the RT state-based data (S306 is NO determination), the main CPU 101 performs the processing of S308 described later. On the other hand, when the main CPU 101 determines in step S306 that the determination data is data by RT state (when the determination in step S306 is YES), the main CPU 101 selects data from the RT state lottery value selection table based on the determination data. Is acquired, and the acquired selected data is set as determination data (S307).

  After the process of S307 or when the determination of S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is data per setting (S308). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination in which the lottery value changes in accordance with the set value. Specifically, the main CPU 101 determines whether or not the address specified in the determination data of the lottery target combination currently acquired is an address in the setting-specific internal lottery value table (not shown).

  In S308, when the main CPU 101 determines that the determination data is not the setting data (when the determination in S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, when the main CPU 101 determines in step S308 that the determination data is data by setting (when the determination in step S308 is YES), the main CPU 101 adds the set value data (0 to 5) to the determination data. Then, the added value is set as determination data (S309). The set value data added to the determination data in this process is data associated with the set value, but not the set value itself but set value data “0” to “5” It is data corresponding to setting 1 "to" setting 6 ".

  After the process of S309 or when the determination of S308 is NO, the main CPU 101 calculates the address of the area where the lottery value of the lottery subject is stored, based on the set determination data (address data), and The stored lottery value is acquired (S310).

  For example, in the case of an internal winning combination in which the lottery value changes according to both the RT state and the setting value, the lottery value is referred to with reference to both the RT state lottery value selection table and the setting-specific internal lottery value table. Is acquired.

  Next, the main CPU 101 acquires a random number value (one of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 performs lottery processing (S312). In this process, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as the lottery result (winning / not winning of the lottery object combination). In this lottery execution process, when the sum of the lottery value and the random number exceeds 65535 (when it overflows), it is determined that the lottery object combination is won (the lottery object combination is determined as the internal winning combination). Ru.

  Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after lottery execution) as a new random value in the random number storage area (S313). Next, the main CPU 101 determines whether or not winning is performed in the lottery processing (whether or not an overflow occurs) (S314).

  When the main CPU 101 determines that the lottery execution process is won in S314 (when the determination in S314 is YES), the main CPU 101 refers to the internal lottery table, and the hit request flag status (corresponding to the internal winning combination won). For example, for the prize winning number (ie, information that can identify the type of bonus role won) corresponding to “No.” in FIG. 16 and FIG. The value of the information that can identify the type) is acquired (S315). Then, after the processing of S315, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S314 that the lottery execution process has not won (S314 is NO determination), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table and performs lottery. The number is decremented by 1 (S316). Next, the main CPU 101 determines whether the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the number of lotteries after subtraction is not “0” (S317 is NO), the main CPU 101 returns the process to the process of S305, and repeats the process of S305 and subsequent steps.

  On the other hand, when the main CPU 101 determines in S317 that the number of lotteries after subtraction is “0” (when the determination in S317 is YES), that is, when the internal winning combination is “off”, the main CPU 101 The lost status is set (S318). The “lost status” corresponds to a hit request flag status in which both of the special prize winning number and the small bonus winning number become “0”. Then, after the processing of S318, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 74).

[Pattern setting process]
Next, with reference to FIG. 83, the symbol setting process performed in S205 in the main flow (see FIG. 74) will be described. FIG. 83 is a flowchart showing the procedure of symbol setting processing.

  First, based on the hit request flag status acquired in the internal lottery process, the main CPU 101 extracts the special award winning number and the small award winning number, and extracts the extracted special award winning number and the small award winning number in the main RAM 103. It stores in the winning number storage area (not shown) (S321).

  In the present embodiment, internal winning combinations “F_BB1” and “F_BB2” are associated with the special award winning numbers “1” and “2”, respectively. In addition, the internal winning combination "F_chiri lip" to "F_RB combination 4" is associated with the small winning combination numbers "1" to "36", respectively. The value of the hit request flag status is formed by adding a small winning combination number to a value obtained by multiplying the winning combination winning number with the special award number (in this embodiment, "37 (hexadecimal number 25H)"). Therefore, in the process of S321, the main CPU 101 extracts the value of the hit request flag status from the value of the hit request flag status in the present embodiment in order to extract the prize winning number and the small award winning number from the value of the hit request flag status. Divide by). As a result, the value of the quotient generated by the division process becomes the special prize winning number (0 to 2 in decimal), and the value of the remainder is the small winning combination number (0 to 36 in decimal). Become.

  Next, the main CPU 101 determines whether or not the small winning combination (or the replay combination) has been won based on the extracted small winning combination number (S322). In this process, when the small winning combination number is any one of 1 to 36, the main CPU 101 determines that the small winning combination (or the replay combination) is won and the small winning combination number is 0. The main CPU 101 determines that the small winning combination (or the replay combination) has not won.

  In S322, when the main CPU 101 determines that the small winning combination (or the replay combination) is not won (when the determination of S322 is NO), the main CPU 101 performs the processing of S331 described later. On the other hand, when the main CPU 101 determines that the small winning combination (or the replay combination) is won in S322 (when the determination in S322 is YES), the main CPU 101 sets the small winning combination number as the initial value of the subtraction result ( S323).

  Next, the main CPU 101 sets a hit request flag table (not shown) (S324). Next, the main CPU 101 subtracts one from the result of subtraction and updates the result of subtraction (S325). Next, the main CPU 101 determines whether the subtraction result is less than “0” (S326).

  In S326, when the main CPU 101 determines that the subtraction result is not less than “0” (when the determination in S326 is NO), the main CPU 101 performs bit number calculation processing (S327). In the bit number calculation process of S327, the number of blocks of the storage area of the hit request flag data corresponding to the small winning combination number defined in the hit request flag table is acquired.

  In the present embodiment, in the hit request flag storage area (internal winning combination storing area), blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11 are provided. Therefore, the maximum value of the number of blocks in the storage area of the hit request flag data acquired in the bit number calculation process of S327 is “2”. For example, in the case where the internal winning combination is "F_integrate lip", storage area 7 included in blocks of hit request storage areas 0 to 7 and storage area 9 included in blocks of hit request storage areas 8 to 11 are included. Since each hit request flag data is defined, the number of blocks in the storage region of the hit request flag data acquired in the bit number calculation process of S327 is “2”.

  Next, the main CPU 101 performs bit number calculation processing (S328). In the bit number calculation process of S328, the number of bytes of the hit request flag data in block units defined in the hit request flag table is calculated. For example, when the internal winning combination is "F_integrate lip", since 1-byte hit request flag data is stored in both storage area 7 and storage area 9, the block acquired in the bit number calculation process of S328. The number of bytes of request flag data per unit is 1 byte.

  In addition, the process of S325-S328 mentioned above is repeated only the frequency | count of a small winning combination number. For example, when the internal winning combination is "F_certain lip" (small winning combination number is "2"), the processing of S325 to S328 described above is repeated twice. In addition, when the processing of S325 to S328 is repeated multiple times, the number of blocks obtained in the bit number calculation processing of S327 and S328 and the number of bytes of the request flag data per block are stored in different storage areas. Be done. Further, the number of blocks and the number of bytes of hit request flag data in block units obtained by the above-described processing of S325 to S328 become information (on-bit information) for specifying the storage destination of the hit request flag data.

  Here, returning to the processing of S326 again, when the main CPU 101 determines that the subtraction result is less than “0” in S326 (when S326 is YES determination), the main CPU 101 stores the hit request flag storage area ( The internal winning combination storing area) is set (S329). At this time, the main CPU 101 determines a hit request flag to be checked (updated) based on the number of blocks obtained by the above-described processing of S325 to S328 and the number of bytes of the hit request flag data in block units (on bit information). Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register.

  Next, the main CPU 101 performs compressed data storage processing (S330). In this process, the main CPU 101 mainly performs a process of transferring (developing) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). The details of the compressed data storage process will be described later with reference to FIG. 84 described later.

  After the process of S330 or when the determination of S322 is NO, the main CPU 101 determines whether or not there is a carryover combination with reference to the carryover combination storage area (see FIG. 31) (S331). In S331, when the main CPU 101 determines that there is a carryover combination (when the determination in S331 is YES), the main CPU 101 performs the processing of S334 described later.

  On the other hand, when the main CPU 101 determines in S331 that there is no carryover role (if S331 is NO), the main CPU 101 selects one of the bonus roles (BB1 or BB2) based on the special prize winning number extracted in S321. ) Is determined (S332).

  In S332, when the main CPU 101 determines that the bonus combination is not won (S332 is NO determination), the main CPU 101 ends the symbol setting process, and the process proceeds to S206 of the main flow (see FIG. 74). Move.

  On the other hand, when the main CPU 101 determines that the bonus combination has been won in S332 (when the determination in S332 is YES), the main CPU 101 stores the won special prize winning number in the carryover combination storage area (S333).

  After the processing of S333 or when S331 is NO, the main CPU 101 sets the winning prize number in the winning number storage area (not shown), sets the hit request flag data in the hit request flag storage area, and RT state RT5. The state is set, and the number of RT games (the number of digested games in RT1 state) is cleared ("0") (S334). Then, after the processing of S334, the main CPU 101 ends the symbol setting processing, and shifts the processing to S206 of the main flow (see FIG. 74).

[Compressed data storage process]
Next, with reference to FIG. 84, for example, compressed data processing performed in S330 in symbol setting processing (see FIG. 83) will be described. FIG. 84 is a flowchart of a procedure of compressed data storage processing.

  The compressed data storage process shown in FIG. 84 is executed not only at S330 in the symbol setting process (see FIG. 83) but also at S649 in a symbol code acquisition process (see FIG. 101 described later). In the compressed data storage process executed in S330 in the symbol setting process (see FIG. 83), the flag data to be processed is the hit request flag data (flag data related to the winning combination), but the symbol code acquisition process described later In the compressed data storage process executed in S 649 in FIG. 101 described later, flag data to be processed is winning operation flag data (flag data relating to a winning combination). The two processes are the same except that the type of flag data to be processed is different.

  Therefore, in the flowchart of FIG. 84, flag data to be processed is referred to as "processing target flag data", and a flag table to be processed is referred to as a "processing target flag table". Also, in line with this description, in the following description of compressed data storage processing, hit request flag data or winning operation flag data will be referred to as "processing target flag data", and a hit request flag table or a symbol corresponding winning operation table described later. (Not shown) is referred to as "processing target flag table".

  First, the main CPU 101 sets a storage destination check bit (S341). In this process, the storage destination check bit is stored in a register other than the A register.

  The storage destination check bit is 1-byte data for specifying a block as a storage destination (transfer destination) of the processing target flag data. In the present embodiment, both the hit request flag storage area and the winning operation flag storage area are formed of two blocks (blocks of storage areas 0 to 7 and blocks of storage areas 8 to 11). Then, for example, in the case where the internal winning combination "F_firmity lip" is determined, the hit request flag data is stored in each of storage area 7 and storage area 9 (the number of blocks in the storage destination is "2". Therefore, in the process of S341, "00000011B" is set as the storage destination check bit. Note that the value (1/0) of bit 0 of this 1-byte data corresponds to the presence or absence of the storage destination in the blocks of storage areas 0 to 7, and the value (1/0) of bit 1 is storage areas 8 to 11 Corresponds to the presence or absence of the storage destination in the block of.

  Next, the main CPU 101 sets the value of the transfer counter in byte units to "8" (S342). In this embodiment, since the number of bytes of each block is "8", "8" is set as the initial value of the transfer counter.

  Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the processing of S343, the storage destination check bit stored in the 1-byte register is shifted right (one bit) to the right. Thus, the transfer indication bit is extracted. Specifically, when the 1-byte register (register other than A register) storing the storage destination check bit is shifted right once, the data stored in bit 7 to bit 1 is changed to bit 6 to bit 0, respectively. While moving, the data of bit 0 before shift is output. Then, the data output by this shift processing becomes the value of the transfer instruction bit.

  Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000011B" is set as the storage destination check bit, the first (corresponding to the first block of the storage area) and the second (corresponding to the second block of the storage area) determination process of S344 transfers Although it is determined that there is an instruction, in the third and subsequent determination processes of S344, it is determined that there is no transfer instruction.

  In S344, when the main CPU 101 determines that there is no transfer instruction (when S344 is NO), the main CPU 101 performs the processing of S354 described later.

  On the other hand, when the main CPU 101 determines in S344 that there is a transfer instruction (when the determination in S344 is YES), the main CPU 101 acquires byte unit storage destination designation information from the processing target flag table (S345). In this process, as the byte unit storage destination designation information, 1 is shown at the head address of the area where the flag data of the processing target combination (a winning combination or a winning combination) in the processing target flag table is stored. Byte data is acquired. For example, when the internal winning combination is "F_integrate lip", transfer storage area 7 in which the flag data of "F_integrate lip" in the hit request flag table is stored at the start address of the area in which it is stored. One-byte data "10000000B" to be designated as the destination is acquired as byte unit storage destination designation information.

  Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address referred to in the process target flag table (S346). Further, in this processing, the main CPU 101 sets an address specifying the head storage area of the block which is the storage (transfer) destination of the processing target flag data as an initial address. For example, in the processing of the first block, the address of storage area 0 is set as the initial address in the processing of S346, and in the processing of the second block, the address of storage area 8 is set as the initial address in the processing of S346. .

  Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage destination specification information (S347). Note that the transfer instruction bit here corresponds to bit 0 of the byte unit storage destination designation information, and in the process of S347, the byte unit storage destination designation information stored in the 1-byte register should be shifted right once. Thus, the value of the transfer instruction bit is extracted (data of bit 0 is output).

  Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, when the value of the extracted transfer indication bit is “1”, the main CPU 101 determines that there is a transfer indication. For example, when "00000010B" is set as byte unit storage destination designation information, data "1" of bit 1 in the process of S347 of the second time (storage area 1 of the first block or storage area 9 of the second block). Is output as the value of the transfer instruction bit and it is determined that there is a transfer instruction, but in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

  When the main CPU 101 determines in S348 that there is no transfer instruction (when the determination in S348 is NO), the main CPU 101 performs the processing of S351 described later.

  On the other hand, when the main CPU 101 determines in S348 that there is a transfer instruction (when the determination in S348 is YES), the main CPU 101 determines the processing target flag stored in the address in the processing target flag table currently set. The data (hit request flag data or winning operation flag data) is transferred (copied) to the designated storage area (S 349).

  For example, if the internal winning combination is "F_positive only" and the current process is being performed on the first block storage area (storage area 0 to 7), the byte unit storage destination specification information is " 10000000 B "(data specifying storage area 7 as the storage destination), so it is determined that there is a transfer instruction in the eighth process of S347, and in the subsequent process of S349, hit request flag data" 10000000 B "," 01000000 B " "," 00100000B "or" 00010000B "is transferred (copied) to the storage area 7 of the hit request flag storage area.

  Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address referred to in the process target flag table (S350).

  After the process of S350 or when the determination of S348 is NO, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address specifying the storage area to be the storage destination of the process target flag data (S351). Next, the main CPU 101 subtracts one from the value of the transfer counter (S352).

  Next, the main CPU 101 determines whether the value of the transfer counter is “0” (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not “0” (when the determination in S353 is NO), the main CPU 101 returns the process to the process of S347 and repeats the processes after S347.

  On the other hand, when the main CPU 101 determines in S353 that the value of the transfer counter is "0" (when the determination in S353 is YES), whether the main CPU 101 has a transfer instruction target remaining in the current storage destination check bit It is determined whether or not it is (S354). In this process, the main CPU 101 determines whether or not a bit for which “1” is stored remains in the storage destination check bit at the current process time. Then, when there is a bit for which "1" is stored in the storage destination check bit, that is, when there is a block to be processed, the main CPU 101 instructs transfer to the current storage destination check bit. It is determined that the target remains.

  In S354, when the main CPU 101 determines that the transfer instruction target remains in the current storage destination check bit (when the determination in S354 is YES), the main CPU 101 returns the process to the process of S342, and the processes after S342. repeat. On the other hand, when the main CPU 101 determines in S354 that no transfer instruction target remains in the current storage destination check bit (S354 is NO), the main CPU 101 ends the compressed data storage processing, and the processing is performed. For example, it moves to S331 in the symbol setting process (see FIG. 83).

Control processing by state
Next, referring to FIG. 85, state-based control processing performed in S208 in the main flow (see FIG. 74) will be described. FIG. 85 is a flowchart of the state-specific control process.

  First, the main CPU 101 performs sub-flag conversion processing (S401). In this process, the main CPU 101 performs a process of converting an internal winning combination into a sub flag (see FIGS. 36 and 37). The details of the sub flag conversion process will be described later with reference to FIG. 86 described later.

  Next, the main CPU 101 performs navigation set processing (S402). In this process, the main CPU 101 acquires navigation data based on the RT state, the gaming state, and the small winning combination number. The details of the navi-set process will be described later with reference to FIG. 87 described later.

  Next, the main CPU 101 determines whether the current RT state is the RT4 state (S403). When the main CPU 101 determines in S403 that the current RT state is not the RT4 state (when the determination in S403 is NO), the main CPU 101 performs the process of S406 described later.

  On the other hand, when the main CPU 101 determines in S403 that the current RT state is the RT4 state (when the determination in S403 is YES), the main CPU 101 performs flag conversion processing (S404). In this processing, the main CPU 101 performs flag conversion lottery processing (compression processing of sub flag data) for converting the sub flag into the sub flag EX (see FIG. 36). By this flag conversion process, 19 types (including lost) of sub flags are converted (compressed) into 9 types (including lost) of sub flags EX. The details of the flag conversion process will be described later with reference to FIG. 88 described later.

  Next, the main CPU 101 performs sub-flag compression processing (S405). In this process, the main CPU 101 converts the subflag EX into a subflag D (see FIG. 36), and further compresses the subflag data. By this sub flag compression process, nine types (including lost) of sub flags EX are converted (compressed) into seven types (including lost) of sub flags D.

  After the processing of S405 or when S403 is NO, the main CPU 101 determines whether the current gaming state is the normal gaming state (S406).

  In S406, when the main CPU 101 determines that the current gaming state is the normal gaming state (when the determination in S406 is YES), the main CPU 101 performs processing during normal middle start (S407). The details of the normal middle start process will be described later with reference to FIG. 89 described later. Then, after the processing of S407, the main CPU 101 ends the state-dependent control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S406 that the current gaming state is not the normal gaming state (when the determination in S406 is NO), the main CPU 101 determines whether the current gaming state is CZ ( S408).

  When the main CPU 101 determines that the current gaming state is CZ in S408 (when the determination in S408 is YES), the main CPU 101 performs CZ start processing (S409). The details of the CZ-in-start process will be described later with reference to FIG. 90 described later. Then, after the processing of S409, the main CPU 101 ends the state-dependent control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S408 that the current gaming state is not CZ (when the determination in S408 is NO), the main CPU 101 determines whether the current gaming state is the normal ART (S410) ).

  In S410, when the main CPU 101 determines that the current gaming state is normal ART (when S410 is YES), the main CPU 101 performs start processing during normal ART (S411). The details of the normal ART start process will be described later with reference to FIG. 94 described later. Then, after the processing of S411, the main CPU 101 ends the state-dependent control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S410 that the current gaming state is not the normal ART (when S410 is NO), the main CPU 101 determines whether the current gaming state is CT (S412) ).

  When the main CPU 101 determines in S412 that the current gaming state is CT (when the determination in S412 is YES), the main CPU 101 performs processing during start during CT (S413). The details of the start process during CT will be described later with reference to FIG. 95 described later. Then, after the processing of S413, the main CPU 101 ends the state-dependent control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S412 that the current gaming state is not CT (when S412 is NO), the main CPU 101 determines whether the current gaming state is the bonus state (S414) ).

  In S414, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S414 is YES), the main CPU 101 performs processing during start during BB (S415). The details of the BB start process will be described later with reference to FIG. 99 described later. Then, after the processing of S415, the main CPU 101 ends the state-dependent control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines that the current gaming state is not the bonus state in S414 (when the determination in S414 is NO), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a gaming state other than the gaming state targeted in the various determination processes. For example, when the current gaming state is ART preparation state, processing corresponding to ART preparation state is performed. Then, after the processing of S416, the main CPU 101 ends the state-dependent control processing, and shifts the processing to S209 of the main flow (see FIG. 74).

[Subflag conversion process]
Next, with reference to FIG. 86, the subflag conversion process performed in S401 in the state-based control process (see FIG. 85) will be described. FIG. 86 is a flowchart of the sub flag change process.

  First, the main CPU 101 acquires a small winning combination number (0 to 36) (S421). Next, the main CPU 101 determines whether or not the bonus is currently activated (S422).

  In S422, when the main CPU 101 determines that the bonus is currently in operation (when the determination in S422 is YES), the main CPU 101 converts the small winning combination number into a sub flag in bonus operation and saves it (S423) . Then, after the processing of S423, the main CPU 101 ends the sub flag conversion processing, and shifts the processing to S402 of the state-dependent control processing (see FIG. 85).

  On the other hand, when the main CPU 101 determines that the bonus is not in operation at S422 (when the determination at S422 is NO), the main CPU 101 sets a sub flag conversion table (not shown) (S424). In this process, when the initial value of the subflag to be determined is set to "losing (00)", the subflag "losing (00)" is stored as the initial address of the block in the subflag conversion table to be referenced. Set the address ("dSBCVTB + 1").

  Next, the main CPU 101 determines whether the data of the small winning combination number defined in the block in the subflag conversion table currently being referred to corresponds to the small winning combination number acquired in the current game. It is determined whether or not it is (S425).

  In S425, the main CPU 101 determines that the data of the small winning combination number defined in the block in the subflag conversion table to be referred to is not the data corresponding to the small winning combination number acquired in the current game. When (when S425 is NO), the main CPU 101 updates the block in the subflag conversion table to be referred to with the block of the next address (S426). Next, the main CPU 101 adds “1” to the value of the sub flag (S427). Then, after the processing of S427, the main CPU 101 returns the processing to the processing of S425, and repeats the processing of S425 and thereafter.

  On the other hand, in S425, the data of the small winning combination number defined in the block in the subflag conversion table which is the reference target by the main CPU 101 is data corresponding to the small winning combination number acquired in the current game. When it is determined that the main CPU 101 determines (YES in S425), the main CPU 101 refers to the sub flag conversion table, and the sub flag conversion control data (corresponding to the address next to the address of the small winning combination number) associated with the small winning combination number. The stored 1-byte data) is acquired, and the sub flag conversion control data is stored in a sub flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). In this process, for example, when the small winning combination number acquired in the current game is “03” (internal winning combination “F_3 continuous chiri lip”), the sub flag conversion control data “00000011 B” with reference to the sub flag conversion table. "Is obtained. Then, after the processing of S428, the main CPU 101 ends the sub flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 85).

[Navi set processing]
Next, with reference to FIG. 87, the navi-set process performed in S402 in the state-based control process (see FIG. 85) will be described. FIG. 87 is a flowchart of the navigation set process.

  First, the main CPU 101 determines whether a navigation set flag is set in the sub flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub flag conversion control data storage area, and the set sub flag conversion control data is data corresponding to the small winning combination number (10 to 23) for generating push order navigation. It is determined whether or not it is. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub flag conversion control data storage area (S431 is NO determination), the main CPU 101 ends the navigation set processing, and the processing by status It moves to S403 of control processing (refer to FIG. 85).

  On the other hand, when the main CPU 101 determines that the navigation set flag is set in the sub flag conversion control data storage area in S431 (when S431 is YES determination), the main CPU 101 is in the RT state RT0 or RT1 state. It is determined whether or not (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (in the case of NO determination in S432), the main CPU 101 ends the navigation setting process and performs the process according to the state-based control process (see FIG. 85). Move to S403 of

  On the other hand, when the main CPU 101 determines in S432 that the RT state is the RT0 or RT1 state (when the determination in S432 is YES), the main CPU 101 determines whether the gaming state is the normal gaming state ( S433). In S433, when the main CPU 101 determines that the gaming state is the normal gaming state (when S433 is determined as YES), the main CPU 101 ends the navigation setting process, and the process is controlled according to the state (see FIG. 85). Move to S403 of

  On the other hand, when the main CPU 101 determines in S433 that the gaming state is not the normal gaming state (when the determination in S433 is NO), the main CPU 101 acquires the small winning combination number (S434). Next, the main CPU 101 refers to the navigation data table (not shown), and acquires navigation data (any one of 1 to 9) based on the small winning combination number (S435).

  Next, the main CPU 101 stores the acquired navigation data (information on the stop operation of the variable display of the plurality of display lines) in the navigation data storage area (stop operation instruction information storage area) (not shown) in the main RAM 103 (S436). Then, after the processing of S436, the main CPU 101 ends the navigation setting processing, and shifts the processing to S403 of the state-dependent control processing (see FIG. 85).

[Flag conversion process]
Next, with reference to FIG. 88, the flag conversion process performed in S404 in the state-based control process (see FIG. 85) will be described. FIG. 88 is a flowchart of the flag conversion process.

  First, the main CPU 101 determines whether it is CT start time (S441).

  When the main CPU 101 determines in S441 that it is not at the start of CT (when the determination of S441 is NO), the main CPU 101 performs the processing of S443 described later. On the other hand, when the main CPU 101 determines in S441 that the CT start time (when S441 is a YES determination), the main CPU 101 randomly determines the table number of the flag conversion lottery table used for flag conversion lottery in CT. And set (S 442).

  After the processing of S442 or when the determination of S441 is NO, the main CPU 101 sets a flag conversion / lottery table according to the current state (S443). For example, if the current state is the RT4 state during non-ART, the flag conversion lottery table during non-ART (refer to FIG. 62) is set, and the current state is the RT4 state during normal ART, If the in-ART flag conversion / lottery table (see FIGS. 47A and 47B) is set and the current state is the RT4 state in CT, the in-CT flag conversion / lottery table (see FIG. 54) is set.

  Next, the main CPU 101 refers to the set flag conversion / lottery table and performs flag conversion / lottery processing based on the internal winning combination (S444). Note that, actually, in this processing, the main CPU 101 performs flag conversion lottery processing using subflag conversion control data acquired from the subflag conversion table based on the subflag corresponding to the internal winning combination.

  Next, the main CPU 101 determines whether or not the flag conversion lottery in S444 has been won (S445).

  In S445, when the main CPU 101 determines that the flag conversion lottery has been won (when the determination in S 445 is YES), the main CPU 101 performs sub flag conversion processing (S 446). In this process, for example, when the internal winning combination is "F_1 sure chill lip", that is, when the sub flag is "triple chill lip B (03)", when winning the flag conversion lottery process, the sub flag conversion process of S446 is performed. , And the sub-flag "triple chiri lip B (03)" is converted into the sub-flag EX "determine (06)" or the sub flag EX "triple chiri lip (07)" (see FIG. 36).

  After the processing of S446, the main CPU 101 determines whether the current gaming state is the non-ART state (S447). In S447, when the main CPU 101 determines that the current gaming state is not the non-ART state (in the case of NO determination in S447), the main CPU 101 ends the flag conversion process, and the process is controlled according to the state (see FIG. 85). Move to S405 of).

  On the other hand, when the main CPU 101 determines in S447 that the current gaming state is the non-ART state (when the S447 is determined as YES), the main CPU 101 adds “1” to the ART set number (S448). Next, the main CPU 101 sets the ART preparation state to the gaming state of the next game (S449). Then, after the processing of S449, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-dependent control processing (see FIG. 85).

  Here, returning to the processing of S445 again, when the main CPU 101 determines that the flag conversion lottery has not been won in S445 (when the determination in S445 is NO), the main CPU 101 performs the sub flag maintenance processing (S450) . In this process, for example, if the internal winning combination is "F_1 sure chill lip", that is, if the sub flag is "triple chill lip B (03)", it is determined that the flag conversion lottery is not successful, the sub flag maintenance of S450. As a result of the processing, the sub-flag "triple chiri lip B (03)" is converted (maintained) into the sub-flag EX "replay (01)". Then, after the processing of S450, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-dependent control processing (see FIG. 85).

[Normal middle start process]
Next, with reference to FIG. 89, the normal middle start processing performed in S407 in the state-dependent control processing (see FIG. 85) will be described. FIG. 89 is a flowchart showing the procedure of the normal middle start process.

  First, the main CPU 101 refers to the CZ lottery table (see FIG. 41A) and performs CZ lottery processing based on the current CZ lottery state and the internal winning combination (sub flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery in S461 has been won (S462).

  When the main CPU 101 determines that the CZ lottery has not been won in S 462 (when the determination in S 462 is NO), the main CPU 101 performs the processing of S 465 described later.

  On the other hand, when the main CPU 101 determines that the CZ lottery has been won in S 462 (when the determination in S 462 is YES), the main CPU 101 sets the CZ of the type winning the gaming state of the next game (S 463). Next, the main CPU 101 sets the number of winning CZ games of the winning type in the CZ game number counter (S464). The CZ game number counter is a counter that counts the continuation period of CZ, and is provided in the main RAM 103. In the process of S464, for example, when CZ1 is won, the first predetermined game number (for example, "12") is set in the CZ game number counter (first half), and CZ2 is won. The second predetermined number of games (for example, “15”) is set in the CZ game number counter (first half), and the fourth predetermined number of games is registered in the CZ game number counter when CZ3 is won. (E.g., "17") is set.

  After the processing of S464 or when S462 is NO, the main CPU 101 refers to the normal middle / high probability lottery table (see FIG. 40A) and performs transition lottery of the CZ lottery state based on the internal winning combination (subflag) (S465) ). Next, the main CPU 101 updates the lottery state of the CZ based on the result of the migration lottery (S466). Then, after the process of S466, the main CPU 101 ends the normal middle start process, and also ends the state-specific control process (see FIG. 85).

[Process at start of CZ]
Next, with reference to FIG. 90, the CZ middle start process performed in S409 in the state-dependent control process (see FIG. 85) will be described. FIG. 90 is a flowchart showing the procedure of the CZ middle start process.

  First, the main CPU 101 determines whether the current gaming state is CZ1 (S471).

  In S471, when the main CPU 101 determines that the current gaming state is CZ1 (when the determination in S471 is YES), the main CPU 101 performs processing during CZ1 (CZ2) (S472). The details of the CZ1 (CZ2) in-process will be described later with reference to FIGS. 91 and 92 described later. Then, after the processing of S472, the main CPU 101 ends the CZ start processing at the same time, and also ends the state-specific control processing (see FIG. 85).

  On the other hand, when the main CPU 101 determines in S471 that the current gaming state is not CZ1 (when the determination in S471 is NO), the main CPU 101 determines whether the current gaming state is CZ2 (S473) .

  In S473, when the main CPU 101 determines that the current gaming state is CZ2 (when the determination in S473 is YES), the main CPU 101 performs processing during CZ1 (CZ2) (S474). Details of the CZ1 (CZ2) in-process will be described later with reference to FIGS. 91 and 92 described later. Then, after the processing of S474, the main CPU 101 ends the CZ start processing at the same time, and also ends the state-specific control processing (see FIG. 85). In the present embodiment, the CZ1 in-process and the CZ2 in-process are different only in rank (mode or point) indicating the expectation for winning ART lottery, and the basic process contents are the same. Therefore, in the present embodiment, the CZ1 in-process and the CZ2 in-process will be described as one process as a CZ1 (CZ2) in-process.

  On the other hand, when the main CPU 101 determines in S473 that the current gaming state is not CZ2 (when the determination in S473 is NO), the main CPU 101 performs a CZ3 middle processing (S475). The details of the CZ3 in-process will be described later with reference to FIG. 93 described later. Then, after the processing of S475, the main CPU 101 ends the CZ start processing at the same time, and also ends the state-specific control processing (see FIG. 85).

[Processing during CZ1 (CZ2)]
Next, with reference to FIGS. 91 and 92, the CZ1 (CZ2) in-process performed in S472 or S474 in the CZ-in-start process (see FIG. 90) will be described. FIGS. 91 and 92 are flowcharts showing the procedure of the process in CZ1 (CZ2).

  First, the main CPU 101 determines whether the current game is a game in the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not a CZ1 (or CZ2) first half game (when the determination of S481 is NO), the main CPU 101 performs the process of S490 described later.

  On the other hand, when the main CPU 101 determines that the current game is a game in the first half of CZ1 in S481 (when S481 is YES determination), the main CPU 101 refers to the CZ1 medium mode lottery table (see FIG. 42). Then, the mode-up lottery process is performed based on the internal winning combination (sub-flag) (S 482). In S481, when the main CPU 101 determines that the current game is a game of the first half of CZ 2 (when S 481 is YES), the main CPU 101 refers to the CZ 2 point lottery table (see FIG. 43). , And performs point-up lottery based on the internal winning combination (sub-flag) (S 482).

  Next, the main CPU 101 updates the rank (mode or point) based on the lottery result of S482 (S483). Next, the main CPU 101 determines whether or not the freeze has been won in the lottery in S482 (S484).

  When the main CPU 101 determines that the freeze has been won in S 484 (when the S 484 is determined as YES), the main CPU 101 performs freeze processing for temporarily stopping the progress of the game, and the number of ART sets and the number of CT sets "1" is added to (S485). Further, in this processing, the main CPU 101 determines and sets the ART level with reference to the ART level determination table (see FIG. 48A). When a freeze occurs, “ART level 2” is determined as the ART level.

  Next, the main CPU 101 sets the ART preparation state to the gaming state of the next game (S486). Then, after the process of S486, the main CPU 101 ends the CZ1 (CZ2) in-process processing and also ends the CZ in-start process (see FIG. 90).

  Here again, returning to the processing of S484, when the main CPU 101 determines that the freeze has not been won in S484 (when the determination of S484 is NO), the main CPU 101 determines the value of the CZ game number counter (first half) Is decremented by 1 (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half) is “0” (S488).

  In S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is not “0” (when S488 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), The CZ start process (see FIG. 90) also ends.

  On the other hand, when the main CPU 101 determines in S488 that the value of the CZ game number counter (first half) is “0” (if YES in S488), the main CPU 101 enters CZ1 or the next gaming state. The second half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing during CZ start (see FIG. 90).

  Here, returning to the process of S481, if the determination of S481 is NO, the main CPU 101 determines whether the current game is the first game of the second half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game in the second half of CZ1 or CZ2 (when S490 is NO), the main CPU 101 performs the processing of S495 described later.

  On the other hand, when the main CPU 101 determines that the current game is the first game in the second half of CZ1 or CZ2 in S490 (when S490 is YES determination), the main CPU 101 selects the CZ ART lottery table (FIG. 44A and 44B) and performs ART lottery processing based on the first half rank (mode or point) (S491).

  Next, the main CPU 101 determines whether or not ART lottery has been won (S492). When the main CPU 101 determines that the ART lottery has not been won in S492 (when the determination in S492 is NO), the main CPU 101 performs the processing of S494 described later.

  On the other hand, when the main CPU 101 determines that the ART lottery has been won in S492 (in the case of YES determination in S492), the main CPU 101 adds “1” to the number of ART sets, and the ART level determination table (see FIG. 48A) ) And perform ART level lottery, and set the lottery result (S493).

  After the processing of S493 or when the determination of S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half part) (S494). In the process of S494, for example, when winning the ART lottery, “4” is set in the CZ game number counter (second half), and when the ART lottery is not won, the CZ game number "3" is set to the counter (second half).

  After the processing of S494 or when the determination of S490 is NO, the main CPU 101 performs ART lottery processing based on the internal winning combination (sub-flag) with reference to the ART lottery table in CZ (see FIG. 44C) (S495).

  Next, the main CPU 101 determines whether or not ART lottery has been won (S 496). When the main CPU 101 determines that the ART lottery has not been won in S 496 (when the determination in S 496 is NO), the main CPU 101 performs the processing of S 498 described later.

  On the other hand, when the main CPU 101 determines that the ART lottery has been won in S 496 (when the S 496 is determined as YES), the main CPU 101 adds “1” to the number of ART sets, and the ART level determination table (see FIG. 48A) Make a ART level lottery with reference to), and set the lottery result (S 497).

  After the processing of S497 or when S496 is NO, the main CPU 101 subtracts one from the value of the CZ game number counter (second half part) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is “0” (S499).

  In S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is not “0” (when S499 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and The CZ start process (see FIG. 90) also ends.

  On the other hand, when the main CPU 101 determines that the value of the CZ game number counter (second half) is “0” in S 499 (when the determination in S 499 is YES), the main CPU 101 determines that the number of ART sets is “1” or more. It is determined whether or not (S500).

  In S500, when the main CPU 101 determines that the ART set number is “1” or more (when S500 is determined as YES), the main CPU 101 sets the ART preparation state as the gaming state of the next game (S501). Then, after the processing of S501, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing during CZ start (see FIG. 90).

  On the other hand, when the main CPU 101 determines in S500 that the ART set number is not 1 or more (S500 is NO determination), the main CPU 101 sets the state at the time of CZ failure to the next game's gaming state ( S502). Then, after the processing of S502, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing during CZ start (see FIG. 90).

[Process in CZ3]
Next, with reference to FIG. 93, the CZ3 middle processing performed in S475 in the CZ middle start processing (see FIG. 90) will be described. FIG. 93 is a flowchart showing the procedure of the CZ3 middle process.

  First, the main CPU 101 executes ART lottery processing based on the internal winning combination (sub flag) with reference to the CZ ART lottery table (see FIG. 45) (S511).

  Next, the main CPU 101 determines whether or not ART lottery has been won (S512). When the main CPU 101 determines in S512 that the ART lottery has not been won (when the determination in S512 is NO), the main CPU 101 performs the processing of S518 described later.

  On the other hand, when the main CPU 101 determines that the ART lottery has been won in S512 (when the determination in S512 is YES), the main CPU 101 adds "1" to the number of ART sets, and "1" to the number of CT sets. It adds (S513). Next, the main CPU 101 determines whether or not a freeze has been won in the ART lottery of S512 (S514).

  When the main CPU 101 determines in step S514 that freezing has not been won (when the determination in step S514 is NO), the main CPU 101 performs the processing of step S516 described below. On the other hand, when the main CPU 101 determines that the freeze has been won in S514 (if YES in S514), the main CPU 101 performs a freeze process to temporarily stop the progress of the game (S515).

  After the processing of S515 or when S514 is NO, the main CPU 101 performs ART level lottery processing with reference to the ART level determination table (see FIG. 48A), and sets the lottery result (ART level) (S516) . Next, the main CPU 101 sets the ART preparation state to the gaming state of the next game (S517). Then, after the processing of S517, the main CPU 101 ends the processing during CZ3 and also ends the processing during CZ start (see FIG. 90).

  Here, returning to the processing of S512, if the determination of S512 is NO, the main CPU 101 subtracts one from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether the value of the CZ game number counter is “0” (S519).

  In S519, when the main CPU 101 determines that the value of the CZ game number counter is not “0” (when the determination in S519 is NO), the main CPU 101 ends the CZ3 in-process and the CZ-in-start process (FIG. See also 90).

  On the other hand, when the main CPU 101 determines in S519 that the value of the CZ game number counter is “0” (when the determination in S519 is YES), the main CPU 101 adds “1” to the number of ART sets. ART level lottery is performed with reference to the level determination table (see FIG. 48A), and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state to the gaming state of the next game (S521). Then, after the processing of S521, the main CPU 101 ends the processing during CZ3 and also ends the processing during start during CZ (see FIG. 90).

[Process during start during normal ART]
Next, with reference to FIG. 94, the start processing during normal ART performed in S411 in the state-dependent control processing (see FIG. 85) will be described. FIG. 94 is a flowchart of the normal-ART start process.

  First, the main CPU 101 adds “1” to the value of the ART continuing game number counter (S531). The ART continuation game number counter is a counter that counts the number of games continued by the ART (the number of digested games). Further, in the present embodiment, in addition to the ART continuation game number counter, an ART end game number counter is also provided which counts the number of games that can normally be ART. Then, in the pachislot 1 of the present embodiment, the value of the ART continuation game number counter and the value of the ART end game number counter are compared, and when the value of the ART continuation game number counter reaches the value of the ART end game number counter, ART The gaming state ends.

  Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 50) and performs CT lottery processing based on the current CT lottery state and the internal winning combination (sub-flag) (S532). Next, the main CPU 101 determines whether or not CT lottery has been won (S533). In S533, when the main CPU 101 determines that CT lottery has not been won (when S533 is NO), the main CPU 101 performs the processing of S536 described later.

  On the other hand, when the main CPU 101 determines that the CT lottery has been won in S533 (when the S533 is determined as YES), the main CPU 101 adds “1” to the CT set number and “CT game number counter value 8 "is set (S534). Next, the main CPU 101 sets the CT of the type that has won the gaming state of the next game (S535).

  After the processing of S535 or when S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48B), extracts ART level based on the value of the ART continuing game number counter, and sets the extraction result. (S536). Next, the main CPU 101 refers to the normal ART medium-to-high probability lottery table (see FIG. 49), and based on the current CT lottery status and the internal winning combination (subflag), extracts the migration destination CT lottery status, and the lottery result Is set (S537).

  Next, the main CPU 101 refers to the ART in-game addition lottery table (see FIG. 51), and performs the addition lottery process of the number of ART games based on the internal winning combination (sub flag) (S538). Next, the main CPU 101 determines whether or not the winning lot has been won (S539).

  In S539, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S539 is NO), the main CPU 101 performs the processing of S541 described later. On the other hand, when the main CPU 101 determines that the additional lottery has been won in S539 (if the determination in S539 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S540).

  After the processing of S540 or when the determination of S539 is NO, the main CPU 101 determines whether the value of the ART continuing game number counter has reached the value of the ART ending game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continuing game number counter has not reached the value of the ART ending game number counter (when the determination of S 541 is NO), the main CPU 101 performs normal ART start processing And the state-specific control process (see FIG. 85) is also ended.

  On the other hand, when the main CPU 101 determines in S541 that the value of the ART continuing game number counter has reached the value of the ART ending game number counter (when the determination of S541 is YES), the main CPU 101 selects one ART set number. The subtraction is performed (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 ends the start processing during the normal ART, and also ends the state-specific control processing (see FIG. 85).

[Process during start during CT]
Next, with reference to FIG. 95, start processing during CT performed in S413 in the state-dependent control processing (see FIG. 85) will be described. FIG. 95 is a flowchart showing a procedure of start processing during CT.

  First, the main CPU 101 refers to the CT middle added lottery table (see FIG. 55) and performs the additional lottery of the number of ART games based on the internal winning combination (sub flag) (S551). Next, the main CPU 101 determines whether or not the additional lottery has been won (S552).

  In S552, when the main CPU 101 determines that the additional lottery has not been won (when the determination of S552 is NO), the main CPU 101 performs the processing of S556 described later. On the other hand, when the main CPU 101 determines that the additional lottery has been won in S552 (when the determination in S552 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S553). As described above, in the pachislot 1 according to the present embodiment, the number of times the subflag "triple chili lip (triple chili lip A or tril chiri lip B)" is won during the same CT increases as per lottery. The amount of additional will increase.

  After the processing of S553, the main CPU 101 determines whether or not the internal winning combination is a combination corresponding to the sub flag EX "three consecutive chills" (or "decision winning combination"), that is, the internal winning combination "F_finalize lip" or "F_1. It is determined whether or not the flag conversion lottery processing at S444 in FIG. 88 is performed (S554).

  When the main CPU 101 determines in S 554 that the internal winning combination is not a combination corresponding to the sub flag EX “three consecutive chills” (S 554 is NO), the main CPU 101 ends the start processing during CT, The state-based control process (see FIG. 85) also ends.

  On the other hand, when the main CPU 101 determines in S 554 that the internal winning combination is the combination corresponding to the sub flag EX “three consecutive chills” (YES in S 554), the main CPU 101 sets the value of the CT game number counter to "1" is added (S555). Then, after the processing of S555, the main CPU 101 ends the processing during start during CT, and also ends the state-specific control processing (see FIG. 85).

  Here, returning to the processing of S552 again, if the determination of S552 is NO, the main CPU 101 conducts CT lottery processing during CT (S556). In this process, the main CPU 101 mainly performs the CT set number addition lottery. The details of the CT lottery process during CT will be described later with reference to FIG. 96 described later.

  Next, the main CPU 101 subtracts one from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether the value of the CT game number counter is “0” (S558).

  In S558, when the main CPU 101 determines that the value of the CT game number counter is not “0” (when the determination in S 558 is NO), the main CPU 101 ends the processing during start during CT, and the state-specific control processing ( Also see FIG. 85). On the other hand, when the main CPU 101 determines in S558 that the value of the CT game number counter is "0" (when the determination in S558 is YES), the main CPU 101 determines whether the CT set number is "1" or more. It is determined whether or not (S559).

  When the main CPU 101 determines in S559 that the number of CT sets is “1” or more (when the determination in S559 is YES), the main CPU 101 subtracts one from the number of CT sets (S560). Next, the main CPU 101 sets “8” to the value of the CT game number counter (S561). Then, after the processing of S 561, the main CPU 101 ends the processing during start during CT, and also ends the state-specific control processing (see FIG. 85).

  On the other hand, when the main CPU 101 determines in S559 that the CT set number is not “1” or more (S559 is NO), the main CPU 101 sets the normal ART to the gaming state of the next game (S562). Then, after the processing of S562, the main CPU 101 ends the processing during start during CT, and also ends the state-specific control processing (see FIG. 85).

[CT during CT lottery processing]
Next, with reference to FIG. 96, CT during CT CT lottery processing performed in S556 in the CT during start processing (see FIG. 95) will be described. FIG. 96 is a flowchart showing the procedure of CT lottery processing during CT.

  First, the main CPU 101 sets a CT extraction table in CT (S571). Here, the CT-in-CT CT lottery table to be set is a CT-in-CT number-of-sets-plus-lottery table schematically shown in FIG.

  Next, the main CPU 101 performs table data acquisition processing (S572). In this process, the main CPU 101 acquires the address of the lottery table to be referred to in the CT during CT lottery process. The details of the table data acquisition process will be described later with reference to FIG. 97 described later.

  Next, the main CPU 101 performs 1-byte lottery processing (S573). In this process, the main CPU 101 carries out a lottery on the CT set. The details of the 1-byte random determination process will be described later with reference to FIG. 98 described later.

  Next, the main CPU 101 determines whether or not the 1-byte lottery process has been won (S574). When the main CPU 101 determines that the one-byte lottery processing has not been won in S 574 (when the determination in S 574 is NO), the main CPU 101 ends the CT lottery processing during CT, and the processing during CT start processing (FIG. Move to S557 of 95).

  On the other hand, when the main CPU 101 determines that the one-byte lottery process has been won in S574 (if YES in S574), the main CPU 101 adds “1” to the number of CT sets (S575). Then, after the processing of S575, the main CPU 101 ends the CT during CT lottery processing, and shifts the processing to S557 of the CT during start processing (see FIG. 95).

[Table data acquisition process]
Next, with reference to FIG. 97, description will be given of the table data acquisition process performed in S572 in the CT lottery process during CT (see FIG. 96). FIG. 97 is a flowchart of the table data acquisition process.

  In the present embodiment, when acquiring the lottery value to be referred to in the CT during the CT lottery process, the lottery value is stored after the two-step address calculation process (first and second stage table data acquisition process). Calculate the address you are First, in the first stage table data acquisition processing (processing of S 582 and S 583 described later), “selected value (1 byte)” associated with the internal winning combination (actually the sub flag D) is acquired. The selection value is provided for each type of internal winning combination, and it can be determined whether or not the internal winning combination is a lottery target, and can specify the arrangement destination of the lottery table associated with the internal winning combination. Value (relative value) is defined. Further, in the present embodiment, a selection value “0” is defined in advance for internal winning combinations (in fact, sub-flag D) in which the lottery result of CT CT lottery processing during CT is not winning, and those internal winning combinations are 1 It is treated as "missing" at the time of stage table data acquisition processing. Then, in the second stage table data acquisition processing (processing of S 585 to S 587 described later), an address storing a lottery value of an internal winning combination in which a selection value other than “0” is defined is calculated (lottery table The address obtained by adding the relative value (selected value) is calculated from the reference address (2 bytes) of

  First, the main CPU 101 refers to the CT in-CT CT lottery selection table (not shown) and calculates the address of the first and second stage addition selection data for calculating the CT in-CT CT lottery table address, and CT The number of lotteries (in the present embodiment, twice) is acquired (S581). Next, the main CPU 101 adds the address of the first stage addition selection data to the address of the CT extraction table in CT to calculate the first stage selection address (S582).

  Next, the main CPU 101 acquires the selection value stored in the calculated first stage selection address (S583). Next, the main CPU 101 determines whether the selection value is "0" (S584).

  When the main CPU 101 determines in S584 that the selection value is “0” (YES in S584), the main CPU 101 ends the table data acquisition process, and the CT lottery process during CT (FIG. 96). Move to S573 of reference).

  On the other hand, when the main CPU 101 determines in S584 that the selection value is not “0” (when the determination in S584 is NO), the main CPU 101 adds the selection value to the selection address, and selects the second selection address. Calculate (S585). Next, the main CPU 101 adds the address of the addition selection data of the second step to the selection address of the second step to calculate the selection address (S586).

  Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates an address to be referred to in the CT extraction table during CT (S587) . Then, after the processing of S587, the main CPU 101 ends the table data acquisition processing, and shifts the processing to S573 of the CT during CT lottery processing (see FIG. 96).

[1 byte lottery process]
Next, with reference to FIG. 98, the 1-byte lottery process performed in S573 in the CT lottery process during CT (see FIG. 96) will be described. FIG. 98 is a flow chart showing a procedure of 1-byte lottery processing.

  First, the main CPU 101 selects a 1-byte random number value (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110) for CT lottery in CT stored in a random number storage area (not shown) in the main RAM 103. Set (S591). Next, the main CPU 101 acquires lottery determination data from the CT during CT lottery table based on the address calculated in S587 during table data acquisition processing (S592). Further, in this process, the main CPU 101 sets the number of determination bits “8” as an initial value of the number of lotteries.

  Next, the main CPU 101 determines whether the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to the bit data in the determination bit associated with the current number of lotteries, and determines that it is the lottery target if the bit data is “1”. Note that, in the present embodiment, bit 0 to bit 7 in the determination bit are associated with the number of lotteries “8” to “1”, respectively.

  In S593, when the main CPU 101 determines that the lottery determination data is not a lottery target (in the case of NO determination in S593), the main CPU 101 performs the processing of S599 described later. On the other hand, when the main CPU 101 determines in S593 that the lottery determination data is a lottery target (if YES in S593), the main CPU 101 acquires a lottery value from the CT during CT lottery table (S594).

  Next, the main CPU 101 determines whether the lottery value is “0” (winning determination data) (S595).

  In S595, when the main CPU 101 determines that the lottery value is “0” (when the determination in S595 is “YES”), the main CPU 101 ends the 1-byte lottery process, and the CT lottery process during CT (FIG. 96) Move to S574 of reference). On the other hand, when the main CPU 101 determines in S595 that the lottery value is not “0” (NO in S595), the main CPU 101 performs CT lottery (CT set number addition lottery) processing (S596). Specifically, the main CPU 101 subtracts the lottery value from the random number value (1-byte random number value), and sets the subtraction result as a random number value.

  Next, the main CPU 101 determines whether or not the CT lottery in S596 has been won (S597). In the CT lottery in S596, the main CPU 101 determines that the winning is achieved when the result of subtraction in S596 is less than or equal to “0” (when so-called “weighing” occurs).

  In S597, when the main CPU 101 determines that CT lottery has been won (in the case of YES determination in S597), the main CPU 101 ends the 1-byte lottery process, and the process is performed during CT CT lottery process (see FIG. 96). Move to S574. On the other hand, when the main CPU 101 determines in S597 that the CT lottery has not been won (when the determination in S597 is NO), the main CPU 101 stores the lottery value storage address (lottery address) in the CT during CT lottery table. Is updated to the next lottery address (S598).

  After the processing of S598 or when the determination of S593 is NO, the main CPU 101 subtracts one from the number of lotteries (S599). Next, the main CPU 101 determines whether the number of lotteries is “0” (S600).

  In S600, when the main CPU 101 determines that the number of times of lottery is not “0” (S600: NO), the main CPU 101 returns the process to S593, and repeats the process of S593 and subsequent steps. On the other hand, when the main CPU 101 determines in S600 that the number of times of lottery is “0” (when the determination in S600 is YES), the main CPU 101 ends the 1-byte lottery process and performs CT lottery process during CT ( Move to S574 of FIG.

[Process during start during BB]
Next, with reference to FIG. 99, the during-BB start process performed in S415 in the state-dependent control process (see FIG. 85) will be described. FIG. 99 is a flowchart showing a procedure of start processing during BB.

  First, the main CPU 101 refers to the ART game number addition lottery table (see FIG. 59) during the bonus, and performs an addition lottery process of the ART game number based on the internal winning combination (S611). Next, the main CPU 101 determines whether or not the winning lot has been won (S612).

  When the main CPU 101 determines in S612 that the additional lottery has not been won (when S612 is NO), the main CPU 101 ends the BB start process and also performs the state-specific control process (see FIG. 85). finish. On the other hand, when the main CPU 101 determines that the winning lottery has been won in S612 (if YES in S612), the main CPU 101 adds the winning result (the number of added games) to the ART finished game number counter (S613). .

  Next, the main CPU 101 determines whether the ART set number is “0” (S614). When the main CPU 101 determines in S614 that the ART set number is not “0” (when S614 is NO), the main CPU 101 ends the BB start process and performs state-based control processing (see FIG. 85). ) Also ends.

  On the other hand, when the main CPU 101 determines in S614 that the ART set number is “0” (YES in S614), the main CPU 101 adds “1” to the ART set number (S615). Then, after the processing of step S615, the main CPU 101 ends the processing during start during BB and also ends the state-specific control processing (see FIG. 85).

[Import priority storage process]
Next, with reference to FIG. 100, the drawing priority priority storage processing performed in S212 in the main flow (see FIG. 74) will be described. FIG. 100 is a flow chart showing the procedure of the retraction priority storage process.

  First, the main CPU 101 sets "3" as the number of search reels (S621). Next, the main CPU 101 performs pull-in priority order table selection processing (S 622). In this process, the drawing priority order table (see FIG. 27) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 performs a drawing priority storage area selection process (S623). In this process, the pull-in priority data storage area of the search target reel is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs symbol code acquisition processing (S625). In this process, the symbol code is acquired with reference to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 101 described later.

  Next, the main CPU 101 performs an AND operation process (S626). In this process, the main CPU 101 performs a process of generating winning operation flag data. Details of the logical product operation processing will be described later with reference to FIG. 102 described later.

  Next, the main CPU 101 performs pull-in priority order acquisition processing (S627). In this process, the main CPU 101 sets the bit to "1" in the winning operation flag (winning combination) storing area (see FIGS. 28 to 30), and the bit is "1" in the hit request flag storing area. With regard to the role set to “1”, pull-in priority data is acquired with reference to the pull-in priority table (see FIG. 27). The details of the pull-in priority order acquisition process will be described later with reference to FIGS. 103 and 104 described later.

  Next, the main CPU 101 stores the acquired drawing priority data in a drawing priority data storage area (not shown) in the main RAM 103 (S628). At this time, the drawing priority order data is stored in the drawing priority order data storage area so that the value of each priority order corresponds to the bit of the storage area.

  In the drawing priority order data storage area, a storage area of priority order data is provided for each type of main reel. In each drawing priority order data storage area, drawing priority order data determined according to each symbol position “0” to “19” of the corresponding main reel is stored. In the present embodiment, by referring to the pull-in priority data storage area, it is searched whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols determined based on the stop table.

  The content of the priority attraction-in data stored in the attraction priority data storage area differs depending on the type of the attraction priority table number in the attraction priority table referenced when determining the attraction priority data. Further, the higher the value of the attraction priority data, the higher the priority. By referring to the draw-in priority order data, it is possible to relatively evaluate the priorities among the symbols arranged on the circumferential surface of the main reel. That is, the symbol for which the largest value is determined as the attraction priority data is the symbol with the highest priority. Therefore, it can be said that the drawing priority order data indicates the order between the symbols arranged on the circumferential surface of the main reel. In addition, when two or more symbols with the same value of a drawing-in priority order data exist, one pattern is determined according to the priority order which a priority order table prescribes | regulates.

  Next, the main CPU 101 performs update processing of the lead-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts one from the number of symbol checks (S630). Next, the main CPU 101 determines whether the symbol check number is "0" (S631).

  In S631, when the main CPU 101 determines that the symbol check number is not “0” (when S631 is NO), the main CPU 101 returns the processing to the processing of S625, and repeats the processing of S625 and subsequent steps. On the other hand, when the main CPU 101 determines in S631 that the symbol check number is “0” (when the determination in S631 is “YES”), the main CPU 101 performs change processing of the search target reel (S632).

  Next, the main CPU 101 subtracts one from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the series of processes described above have been performed for all the main reels (S634).

  When the main CPU 101 determines in S634 that the number of search reels is not “0” (when the determination in S634 is “NO”), the main CPU 101 returns the process to the process of S622, and repeats the processes after S622. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (when the determination in S634 is “YES”), the main CPU 101 ends the drawing priority storing process and the process is a main flow (FIG. 74)).

[Symbol code acquisition processing]
Next, with reference to FIG. 101, the symbol code acquisition processing performed in S625 in the retraction priority storage processing (see FIG. 100) will be described. FIG. 101 is a flowchart of the symbol code acquisition process.

  First, the main CPU 101 clears the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all the storage areas in the winning operation flag storage area (see FIGS. 28 to 30). Next, the main CPU 101 sets a first reel symbol arrangement table (not shown) (S642).

  Next, the main CPU 101 determines whether it is time to stop the first reel (left reel 3L) (S643).

  In S643, when the main CPU 101 determines that the first reel (the left reel 3L) is stopped (when the determination is YES in S643), the main CPU 101 performs the processing of S647 described later. On the other hand, when the main CPU 101 determines that the first reel (the left reel 3L) is not stopped at S643 (when S643 is NO), the main CPU 101 sets the second reel symbol arrangement table (not shown). (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten with the second reel symbol arrangement table.

  Next, the main CPU 101 determines whether it is time to stop the second reel (middle reel 3C) (S645).

  In S645, when the main CPU 101 determines that the second reel (the middle reel 3C) is stopped (when the determination in S645 is YES), the main CPU 101 performs the processing of S647 described later. On the other hand, when the main CPU 101 determines that the second reel (the middle reel 3C) is not stopped at S645 (when S645 is NO), the main CPU 101 sets the third reel symbol arrangement table (not shown). (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten with the third reel symbol arrangement table.

  After the processing of S646, or when S643 or S645 is determined as YES, the main CPU 101 performs symbol check processing at the time of execution of the stop operation on the reel of the stop control target, and corresponds to the symbol corresponding to the symbol acquired by the symbol check processing. A winning operation table (not shown) is obtained (S647). The symbol corresponding prize operation table is a table for making it possible to identify the type of a winning combination (symbol combination) which can be a prize if the corresponding symbol is stopped on the activated line in the stop control target reel.

  Next, the main CPU 101 sets a winning operation flag storage area (S648). Next, the main CPU 101 performs the compressed data storage processing described in FIG. 84 (S649). In this process, the main CPU 101 mainly carries out a process of transferring (expanding) the possible-to-win prize operation flag data stored in the symbol-corresponding prize actuation table to the corresponding storage area in the prize operation flag storage area.

  For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line at the time of the stop operation is "white 7", the symbol combinations that can be won are shown in FIG. As shown in 30, the combination names "C_2nd_A_01", "C_2nd_A_01" and "C_SP1_01" defined in the second storage area, the combination names "C_9 sheets C_01" to "C_9 sheets C_03" defined in the third storage area, "C_9 sheets C_07" to "C_9 sheets C_09" and "C_9 sheets E_01", the combination name "C_RB role A_01" defined in the fourth storage area, "C_RB role A_02", "C_RB role B_01" to "C_RB role B_04 , “C_RB role C_01” and “C_RB role C_02”, the sixth storage area Combination names “C_reach eyes Lip C_01” to “C_reach eyes Lip C_03”, “C_reach eyes Lip D_01”, “C_reach eyes Lip D_02” and “C_reach eyes Lip E_01”, and the 10th storage area It is the combination name "C_BB1" prescribed by.

  After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and the data length of the winning operation flag storage area (12 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and shifts the processing to S626 of the drawing priority storage processing (see FIG. 100).

Logical product operation processing
Next, with reference to FIG. 102, for example, the logical product operation process performed in S626 in the pull-in priority order storage process (see FIG. 100) will be described. FIG. 102 is a flowchart showing the procedure of logical product operation processing. The logical product operation process shown in FIG. 102 is performed not only at S626 in the pull-in priority order storage process (see FIG. 100) but also at S687 in the pull-in priority order acquisition process described later (see FIG. 103 and FIG. 104). Is also performed.

  In the AND operation process executed in S626 in the draw-in priority order storage process (see FIG. 100), the two data to be AND-operated is stored in the winning operation flag set in S650 during the symbol code acquisition process described above. It is data of an area and data of a symbol code storage area. The former data corresponds to "logical AND destination data" described later, and the latter data corresponds to "logical AND source data" described later. Further, in this case, the number of bytes "12" of the data length (12 bytes) set in S650 during the symbol code acquisition processing described above corresponds to the "number of logical multiplications" described later.

  On the other hand, in the AND operation process executed in S687 in the pull-in priority order acquisition process (see FIG. 103 and FIG. 104 described later), the two data to be ANDed is the hit (pull-in) request flag storage area And data of the winning operation flag storage area. The former data corresponds to "logical AND destination data" described later, and the latter data corresponds to "logical AND source data" described later. Further, in this case, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag described later corresponds to “the number of logical multiplications” described later.

  First, the main CPU 101 acquires logical multiplication source data (for example, data of a symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, data of the winning operation flag storage area), and stores the calculation result as logical product destination data (S662).

  Next, the main CPU 101 adds one to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 adds one to the address of the logical multiplication destination data to be referred to (S664).

  Next, the main CPU 101 subtracts one from the number of logical products (S665). Next, the main CPU 101 determines whether the number of logical multiplications is “0” (S666).

  In S666, when the main CPU 101 determines that the number of logical multiplications is not “0” (when S666 is NO), the main CPU 101 returns the processing to the processing of S661, and repeats the processing of S661 and subsequent steps. On the other hand, when the main CPU 101 determines in S666 that the number of logical multiplications is “0” (when the determination in S666 is YES), the main CPU 101 ends the logical multiplication processing and stores the processing, for example, in the drawing priority storage. Move to S627 in the process (see FIG. 100).

[Import priority acquisition process]
Next, with reference to FIG. 103 and FIG. 104, a drawing-in priority acquisition process performed in S627 in the drawing-in priority storage process (see FIG. 100) will be described. FIG. 103 and FIG. 104 are flowcharts showing the procedure of the pull-in priority order acquisition process.

  First, the main CPU 101 determines whether it is time to check the right reel 3R (specific display row) (S671).

  When the main CPU 101 determines in S671 that it is not at the time of checking the right reel 3R (when the determination in S671 is NO), the main CPU 101 performs the processing of S674 described later. On the other hand, when the main CPU 101 determines in S671 that the right reel 3R is checked (when S671 is determined as YES), the main CPU 101 selects "ANY combination" in the symbol combination (winning combination) relating to the internal winning combination. It is determined whether (a predetermined combination of symbols) is included (S672). The term "ANY combination" as used herein refers to a combination in which winning is determined regardless of at least the stop symbol of the right reel 3R (a winning combination in which at least the stop symbol of the right reel 3R is an arbitrary symbol).

  When the main CPU 101 determines in S672 that the symbol combination relating to the internal winning combination does not include the "ANY combination" (when the determination of S672 is NO), the main CPU 101 performs the processing of S674 described later. On the other hand, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes the symbol "ANY combination" in S672 (when the determination of S672 is YES), the main CPU 101 selects "ANY in the prize operation flag storage area. The storage area corresponding to "combination" is masked (S673). Specifically, the main CPU 101 sets “1” to a bit corresponding to “ANY combination” in the winning operation flag storage area. In the case where the "ANY combination" is not defined in the symbol combination (winning combination) relating to the internal winning combination, the processing of S671 to S673 may be unnecessary. Also, when "ANY role" defines the stop symbol of the left reel 3L or the middle reel 3C as an arbitrary symbol, the processing of S672 and S673 is also performed when checking the left reel 3L or the middle reel 3C. It may be performed (the same applies to the processing of S681 to S683 described later).

  After the processing of S673 or when S671 or S672 is NO, the main CPU 101 selects “1” as the address of the last storage area as the address of the winning operation flag storage area (see FIGS. 28 to 30). The added address is set, the stop prohibition data is set, and the winning operation flag data length (data length of the winning operation flag storage area: 12 bytes in the present embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which the stop operation has been detected. Further, the stop button operation state is obtained by referring to the operation stop button storage area (see FIG. 33).

  Next, the main CPU 101 subtracts one from the address of the winning operation flag storage area that has been set (-1 update) (S676). Next, the main CPU 101 generates hit request flag data from the winning operation flag storage area set and the corresponding hit request flag storage area (see FIGS. 28 to 30), and the generated hit request flag data The prohibited winning operation position is generated based on (S677).

  Next, the main CPU 101 determines whether the stop operation position is the prohibited winning operation position (S678).

  When the main CPU 101 determines in S678 that the stop operation position is not the prohibited winning operation position (when the determination in S678 is NO), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (when the determination in S678 is YES), the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop. It is determined whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when the determination of S679 is YES), the main CPU 101 performs the processing of S705 described later. On the other hand, when the main CPU 101 determines in S679 that the value of the stop button operation counter is not the value of the third stop (when S679 is NO), the main CPU 101 determines that the value of the stop button operation counter is the second stop. It is determined whether it is a value (S680).

  When the main CPU 101 determines in S680 that the value of the stop button operation counter is not the value of the second stop (when the determination in S680 is NO), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines that the value of the stop button operation counter is the value of the second stop in S 680 (when the determination in S 680 is YES), the main CPU 101 determines whether or not the right reel 3 R is stopped. It is determined (S681).

  When the main CPU 101 determines that the right reel 3R has been stopped in S681 (when the determination in S681 is YES), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines that the right reel 3R is not stopped in S681 (when the determination in S681 is NO), the main CPU 101 is a flag that may receive an interference of the hit request flag "ANY role". Whether or not (whether or not "ANY combination" is included in the symbol combination (winning combination) according to the internal winning combination) is determined (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may receive an interference of "ANY combination" (if S682 is YES), the main CPU 101 performs the processing of S684 described later. On the other hand, when the main CPU 101 determines in S682 that the hit request flag is a flag that may receive an interference of "ANY combination" (S682: NO), the main CPU 101 determines that the current check is "ANY". It is judged whether it is at the time of the check of the hit request flag including the "combination" (S683).

  When the main CPU 101 determines in S683 that the current check is a check on the hit request flag including the "ANY combination" (when the determination in S683 is YES), the main CPU 101 performs the processing of S705 described later.

  On the other hand, when the main CPU 101 determines in S683 that the current check does not include a check on the hit request flag including "ANY combination" (S683 is NO), S678 or S680 is NO or S681. Alternatively, if the determination in S682 is YES, the main CPU 101 subtracts one from the winning operation flag data length (S684). Next, the main CPU 101 determines whether the winning operation flag data length is "0" (S685).

  In S685, when the main CPU 101 determines that the winning operation flag data length is not "0" (when the determination in S685 is NO), the main CPU 101 returns the process to the process of S676, and repeats the processes after S676.

  On the other hand, when the main CPU 101 determines that the winning operation flag data length is "0" in S685 (when S685 is YES), the main CPU 101 performs stop control pull-in request flag setting processing (S686) . In this process, for example, the main CPU 101 performs the logical product operation process described with reference to FIG. In the logical AND operation process executed in the process of S686, as described above, the data of the hit (pull-in) request flag storage area is set to the "logical AND destination data", and the data of the winning operation flag storage area is It is set in “conjunction source data”, and the number of bytes “1” of the data length (1 byte) of the RT operation combination indication flag is set in “the number of conjunctions”. The RT operation combination display flag is a storage area in which a symbol combination relating to RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 11 as shown in FIGS. 28 to 30. Become.

  Next, the main CPU 101 refers to the drawing priority order table address storage area to acquire a drawing priority order table (S687). In this process, the initial value "1 (001H)" of the pull-in priority data is set to the currently set address, and any of the pull-in priority table numbers "00" to "05" described in FIG. Pull-in priority table is acquired.

  Next, the main CPU 101 determines whether or not the data of the lead-in priority order table stored at the currently set address is the end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data of the pull-in priority order table stored at the currently set address is an end code (YES in S688), the main CPU 101 performs S705 described later. Perform the processing of On the other hand, when the main CPU 101 determines in S688 that the data in the pull-in priority order table stored at the currently set address is not an end code (S688: NO), the main CPU 101 performs a winning operation. The flag storage area is set (S689).

  Next, the main CPU 101 acquires retraction priority data based on the retraction priority table stored at the currently set address (S690). Next, the main CPU 101 sets a block counter of the pull-in priority order table (S691). In this embodiment, in this process, the main CPU 101 sets “2” to the value of the block counter in the pull-in priority order table.

  Next, the main CPU 101 sets the number of checks in the lead-in priority order table, and adds 1 to the address of the lead-in priority order table to be referenced (+1 update) (S692). In this embodiment, in this process, the main CPU 101 sets “8” as the number of checks in the pull-in priority order table.

  Next, the main CPU 101 acquires check data based on the updated address of the lead-in priority order table, and extracts check bits from the check data (S693). In the present embodiment, the check bit extracted here corresponds to bit 0 of the check data. For example, in the process of S690, when the retraction priority data "03EH" is acquired from the retraction priority table with the retraction priority table number "00" described in FIG. 27, "10001000B" as check data in the processing of S693. Is acquired and “0” is extracted as the value of the check bit.

  Next, the main CPU 101 determines whether the value of the extracted check bit is “1” (S694).

  When the main CPU 101 determines in S694 that the value of the extracted check bit is not “1” (when the determination in S694 is NO), the main CPU 101 performs the processing of S699 described later. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is “1” (when the determination in S694 is YES), the main CPU 101 adds 1 to the address of the lead-in priority table to be referred. The determination data is acquired from the lead-in priority order table based on the address after the update (S695).

  Next, based on the determination data acquired in S695, the main CPU 101 determines whether the currently-acquired winning operation flag data is a determination target (S696). In this process, the main CPU 101 compares the currently acquired winning operation flag data with the determination data, and determines whether the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently-acquired winning operation flag data is the determination target.

  When the main CPU 101 determines in S696 that the winning operation flag data is not a determination target (when the determination in S696 is NO), the main CPU 101 performs the processing of S699 described later. On the other hand, when the main CPU 101 determines that the winning operation flag data is the determination target in S 696 (when the determination in S 696 is YES), the main CPU 101 performs a drawing priority update data update process (S 697). In this process, the main CPU 101 updates (overwrites) the currently set attraction priority data with the attraction priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 performs check data update processing (S698). In this process, the main CPU 101 shifts the check data to the right (in the direction from bit 7 to bit 0) by one bit. In this process, "0" is set to bit 7 of the check data after shift.

  After the process of S698, or when S694 or S696 is NO, the main CPU 101 determines whether or not there is a bit to be checked (a bit for which “1” is set) in the check data (S699).

  When the main CPU 101 determines in S699 that there is no check target bit in the check data (when the determination in S699 is NO), the main CPU 101 performs the processing of S702 described later. On the other hand, when the main CPU 101 determines in S699 that there is a check target bit in the check data (if S699 is a YES determination), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update) And decrement the number of checks by one (S700).

  Next, the main CPU 101 determines whether the number of checks is “0” (S701). In S701, when the main CPU 101 determines that the number of checks is not “0” (when S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes of S698 and subsequent steps.

  On the other hand, when the main CPU 101 determines in S701 that the number of checks is "0" (when the determination in S701 is YES), the main CPU 101 checks the address of the prize operation flag storage area currently referred to. The initial value "8" is added to update the address of the winning operation flag storage area, and the value of the block counter is decremented by 1 (S702). Next, the main CPU 101 determines whether the value of the block counter is “0” (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (when the determination in S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes of S692 and subsequent steps.

  On the other hand, when the main CPU 101 determines that the value of the block counter is “0” in S703 (when the determination in S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred (+1 update) ) (S704). For example, in the case where the pull-in priority table currently referred to is the pull-in priority table of pull-in priority table number “00” described in FIG. 27, the pull-up priority table to be referred by this processing is shown in FIG. It is changed to the drawing priority table of drawing priority table number “01” described. Then, after the processing of S704, the main CPU 101 returns the processing to the processing of S688, and repeats the processing after S688.

  Here, returning to the processing of S679, S683 or S688 again, if S679, S683 or S688 is determined as YES, the main CPU 101 sets the retraction priority data set at this time as the final retraction priority data. It sets (S705). When the determination in S679 or S683 is YES, the main CPU 101 sets “0 (00H)” as the final lead-in priority data. In this case, since the end code is assigned to the loading priority data "0 (00H)", no loading data (stop prohibition) is set. Then, after the processing of S705, the main CPU 101 ends the drawing priority acquisition process, and shifts the processing to S628 of the drawing priority storing process (see FIG. 100).

[Reel stop control processing]
Next, with reference to FIG. 105, the reel stop control process performed in S213 in the main flow (see FIG. 74) will be described. FIG. 105 is a flowchart showing the procedure of the reel stop control process.

  First, the main CPU 101 performs a reel stop enable signal OFF process (S711). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal OFF data. Also, this process is performed using the non-specified work area of the main RAM 103.

  Next, the main CPU 101 determines whether or not the rotational speeds of all the reels have reached a predetermined constant speed (whether or not the "constant speed" has been reached) (S712). When the main CPU 101 determines in S712 that the rotational speeds of all the reels are not "constant speed" (when the determination in S712 is NO), the main CPU 101 repeats the processing of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotational speeds of all the reels have become "constant speed" (when the determination in S712 is YES), the main CPU 101 performs reel stop enable signal ON processing (S713). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal ON data. Also, this process is performed using the non-specified work area of the main RAM 103.

  Next, the main CPU 101 determines whether a valid stop button has been pressed (S714).

  When the main CPU 101 determines that the effective stop button has not been pressed in S714 (when the determination in S714 is NO), the main CPU 101 returns the process to the process of S713, and repeats the processes after S713. On the other hand, when the main CPU 101 determines that the effective stop button has been pressed in S714 (when the determination in S 714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 33). The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines a search target reel from the operation stop button (S716). Further, in this process, an address (head address) setting process of the spinning drum control data storage area in which the reel control management information of the search target reel is stored is also performed.

  Next, the main CPU 101 performs reel stop enable signal OFF processing (S717). This process is performed using the non-specified work area of the main RAM 103 as in the above-described S711. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 performs reel stop selection processing (S719). Although the detailed description is omitted, in this process, the main CPU 101 performs a process of selecting the number of sliding symbols.

  Next, the main CPU 101 determines a planned stop position based on the stop start position and the number of sliding symbols determined in S719, and stores the determined planned stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding symbols to the stop start position, and sets the result of the addition as the planned stop position.

  Next, the main CPU 101 executes symbol code storage processing (S721). In this process, the symbol code corresponding to the planned stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether the reel to be controlled is the final stop (third stop) reel (S722). In this processing, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button inactivity counter, and the value of the stop button inactivity counter is When it is "0", it is determined that the reel to be controlled is the reel of the final stop.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stop reel (when the determination in S722 is NO), the main CPU 101 performs control change processing (S723). In this process, the stop information group used to stop the reel is updated when it is at the specific stop position. Next, the main CPU 101 performs the retraction priority storage process described with reference to FIG. 100 (S724).

  Next, the main CPU 101 performs stop interval remaining time standby processing (S725). In this process, the main CPU 101 performs a standby process until a predetermined predetermined reel stop interval time has elapsed. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing of S711 and thereafter.

  Here again, returning to the processing of S722, when the main CPU 101 determines that the reel to be controlled is the final stop reel in S722 (when the determination of S722 is YES), the main CPU 101 excites all the reels. It is determined whether or not is in the stop state (S726). When the main CPU 101 determines in S726 that the excitation of all the reels is not in the stop state (when the determination in S726 is NO), the main CPU 101 repeats the processing of S726.

  On the other hand, when the main CPU 101 determines in S726 that the excitation of all the reels is in the stop state (when the determination in S726 is YES), the main CPU 101 keeps the stop button subjected to the third stop operation in the on state. It is determined whether (the stop button has not been released) (S727). In S727, when the main CPU 101 determines that the stop button subjected to the third stop operation remains in the on state (when the determination in S 727 is YES), the main CPU 101 repeats the process of S 727. On the other hand, when the main CPU 101 determines in S727 that the stop button subjected to the third stop operation is not in the on state (when S727 is NO), the main CPU 101 ends the reel stop control processing and performs processing. Move to S214 in the main flow (see FIG. 74).

[Paid search process]
Next, with reference to FIG. 106, the prize winning search process performed in S214 in the main flow (see FIG. 74) will be described. FIG. 106 is a flowchart showing the procedure of the winning search process.

  First, main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 35) in the corresponding storage area of the winning operation flag storage area (see FIGS. 28 to 30). (S761). At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets an address of a payout number data table (not shown) that defines the payout number (see FIGS. 28 to 30) of the winning combination (symbol combination) in the HL register (S762). Next, the main CPU 101 sets the number-of-payouts table number (for example, “5” in the present embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

  Next, based on the address set in the HL register, the main CPU 101 sets data of the number of paid-out medals (in the present embodiment, one, two, three, or nine sheets) in the C register. Then, the judgment target data is set in the A register, and "2" is added (+2 updated) to the address set in the HL register (S764). In the payout number data table, data on the payout number of medals is defined as, for example, “the number of payouts (1, 2, 3 or 9) * 2 + 0”. Also, in the following, data "0" in the data "the number of payouts (1, 2, 3 or 9) * 2 + 0" of the number of paid-out medals set in the C register is referred to as "determination bit". This determination bit is information indicating whether or not it is a determination target block of a winning search.

  Next, the main CPU 101 extracts the value of the determination bit from the data of the number of paid-out medals set in the C register (S765). Next, the main CPU 101 determines whether or not the block is a determination target block based on the value of the extracted determination bit (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is “1”. In the present embodiment, regardless of the number of medals paid out, the value of the determination bit is always defined as “0”, so the process of S766 always determines NO.

  In S766, when the main CPU 101 determines that the block is not a determination target block (in the case of NO determination in S766), the main CPU 101 performs the process of S768 described later. On the other hand, when the main CPU 101 determines in S766 that the block is a determination target block (when S766 is a YES determination), the main CPU 101 subtracts one from the address of the winning operation flag storage area set in the DE register (- 1) to update (S767).

  After the processing of S767 or when the determination of S766 is NO, the main CPU 101 extracts data of the storage area designated by the address of the winning operation flag storage area set in the DE register as determination data (S768).

  Next, the main CPU 101 determines whether or not the determination result is a winning based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, when the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a winning.

  In S769, when the main CPU 101 determines that the determination result is not a winning (in the case of NO determination in S769), the main CPU 101 performs the processing of S776 described later. On the other hand, when the main CPU 101 determines in S769 that the result of the determination is a winning (when the determination in S769 is YES), the main CPU 101 plays three games (the number of medal bets is three) It is determined whether or not (S 770).

  In S770, when the main CPU 101 determines that the current game is a three-card game (when the determination in S 770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, when the main CPU 101 determines in S770 that the current game is not a three-game game (when S770 is NO), the main CPU 101 pays out a two-card game (a game in which the number of medals bet is two). The number (two sheets) is set in the C register (S771).

  After the process of S771 or when the determination of S770 is YES, the main CPU 101 performs an update process of the number of dispensed sheets (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current value of the winning number counter, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether the value of the payout number is less than the maximum payout number “10” (S773).

  When the main CPU 101 determines in S773 that the value of the number of payouts is less than the maximum number of payouts “10” (when the determination in S773 is YES), the main CPU 101 performs the processing of S775 described later. On the other hand, when the main CPU 101 determines in S773 that the value of the number of payouts is not less than the maximum number of payouts “10” (when the determination of S773 is NO), the main CPU 101 sets the maximum number of payouts “10” as the number of payouts. (S774).

  After the processing of S774 or when the determination of S773 is YES, the main CPU 101 stores the number of payouts in the winning number counter (S775).

  After the processing of S775 or when S769 is NO, the main CPU 101 determines whether or not there is another winning (S776). In S776, when the main CPU 101 determines that there is another winning (if YES in S776), the main CPU 101 returns the process to S769, and repeats the processes of S769 and subsequent steps.

  On the other hand, when the main CPU 101 determines that there is no other winning in S776 (if NO in S776), the main CPU 101 subtracts 1 from the value of the winning search counter (-1 update) (S777). Note that, as in the present embodiment, when there is one valid line, a plurality of small winning combinations do not win in duplicate, so the determination processing in S776 is always determined as NO.

  Next, the main CPU 101 determines whether or not the value of the winning search counter is "0" (S778).

  In S778, when the main CPU 101 determines that the value of the winning search counter is not “0” (when the determination in S778 is NO), the main CPU 101 returns the process to the process of S764 and repeats the processes after S764. On the other hand, when the main CPU 101 determines in S778 that the value of the winning search counter is "0" (when the determination in S778 is YES), the main CPU 101 ends the winning search processing, and the main flow of processing (FIG. And the process of S215 in (see 74).

[Illegal hit check process]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 74) will be described with reference to FIG. FIG. 107 is a flowchart of the illegal hit check process. It should be noted that an illegal hit is a prize winning number and a minor winning number (internal winning combination) which are extracted in the internal lottery process (see FIG. 82) and stored in the symbol number storing area in the symbol setting process (see FIG. 83). Based on this, it is a term indicating that the left reel 3L, the middle reel 3C and the right reel 3R are stopped on the effective line (symbol combination failure) by a combination of symbols that can not be established.

  First, the main CPU 101 sets the address of the winning operation flag storage area (see FIGS. 28 to 30) (S781). Next, the main CPU 101 sets the size of the winning operation flag storage area (the number of bytes, “12” in the present embodiment) to the value of the check counter (S 782).

  Next, based on the address of the winning action flag storage area currently set, the main CPU 101 stores the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storing area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 combines data of the winning combination (winning operation flag data) stored in the address of the currently set winning operation flag storage area and data of the internal winning combination (hit request flag data) (see FIG. S784).

  In the combining process, first, the main CPU 101 obtains an exclusive OR of data of winning combination (winning operation flag data) and data of internal winning combination (hit request flag data). Next, the main CPU 101 obtains the logical product of the calculated exclusive OR calculation result and the winning combination data (prize operation flag data), and sets the logical calculation result as the synthesis result. When no illegal hit error has occurred, the value of the synthesis result is “0”.

  Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the combining process of S784 (S785).

  When the main CPU 101 determines in S785 that an illegal hit error has not occurred (when the determination in S785 is NO), the main CPU 101 updates the address of the winning operation flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts one from the value of the check counter (S787). Next, the main CPU 101 determines whether the value of the check counter is “0” (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (when the determination in S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes of S783 and subsequent steps. On the other hand, when the main CPU 101 determines that the value of the check counter is “0” in S 788 (when the determination in S 788 is YES), the main CPU 101 ends the illegal hit check processing, and the main flow of FIG. And the process of S216 in 74).

  Here, returning to the processing of S 785 again, when the main CPU 101 determines that an illegal hit error has occurred in S 785 (when the determination in S 785 is YES), the main CPU 101 performs the error processing described in FIG. 80. (S 789). As a result of this processing, a two-character "EE" indicating the occurrence of an illegal hit error is displayed as error information on the 2-digit 7-segment LED (for both display of the number of payouts and error display) included in the information display 6. Error display data is output. The state of occurrence of an illegal hit error (error state) is canceled by pressing the reset switch 76 (see FIG. 6).

  Next, the main CPU 101 clears the value of the winning number counter and the data of the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 74).

  In the present embodiment, as shown in FIGS. 28 to 30, since the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area), The winning request flag storage area and the winning operation flag storage area, which are arranged in the main RAM 103 at the time of combining the combination of the winning combination flag storage area and the internal winning combination, can be configured identically. Therefore, the calculation result (combining result of the data of the winning combination and the data of the internal winning combination) in the illegal hit check process of the present embodiment is simply the logical product of the data of the winning combination and the data of the internal winning combination. (E.g., execute with an "AND" instruction). As a result, in the present embodiment, the illegal hit check process can be streamlined and simplified, the free space of the main control program can be secured (increased), and the playability can be increased using the increased free space. It becomes possible to raise.

[Paid check / medal payout process]
Next, with reference to FIG. 108, the winning a prize check and medal payout process performed in S216 in the main flow (see FIG. 74) will be described. FIG. 108 is a flowchart showing the procedure of the winning check and medal payout processing.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub control circuit 200. The winning operation command includes parameters for specifying a winning operation flag (display combination) and the like.

  Next, the main CPU 101 performs the communication data storage process described in FIG. 68 (S802). By this processing, the winning operation command data is stored in the communication data storage area provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is “0” (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (in the case of YES determination in S803), the main CPU 101 ends the winning check and medal payout processing, and the main flow ( Proceed to the processing of S217 in FIG.

  On the other hand, when the main CPU 101 determines in S803 that the value of the winning number counter is not "0" (in the case of NO determination in S803), the main CPU 101 determines that the credit number of medals (stored number) is the upper limit number In the embodiment, it is determined whether the number is 50 or more) (S804).

  In S804, when the main CPU 101 determines that the credit number of medals is not the upper limit or more (when S804 is NO), the main CPU 101 adds 1 to the value of the credit counter (+1 update) S 805). The added value of the credit counter is displayed by a 2-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs medal payout number check processing (S806). The details of the medal payout number check process will be described later with reference to FIG. 109 described later.

  Next, the main CPU 101 determines whether or not the payout of medals is completed (S807). In S807, when the main CPU 101 determines that the payout of medals is completed (S807: YES), the main CPU 101 ends the winning check and medal payout processing, and the processing is in the main flow (see FIG. 74). Transfer to the process of S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not been completed (S807: NO), the main CPU 101 performs payout interval standby processing (S808). In this process, the main CPU 101 continues until a preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt process (1.1172 msec cycle) described later in FIG. 114) elapses. To wait. Then, after the processing of step S808, the main CPU 101 returns the processing to the processing of step S803, and repeats the processing of step S803 and subsequent steps.

  Here, returning to the processing of S804 again, when the main CPU 101 determines that the credit number of medals is equal to or more than the upper limit number (50) in S804 (in the case of YES determination in S804), the main CPU 101 A payout process of medals is performed (S809). As a result of this processing, medals which have not been stored as the number of credits are paid out. Also in the process of S809, the process of S806 to 806 may be repeated each time one medal is paid out, until the payout of the medal is completed. Then, after the processing of S809, the main CPU 101 ends the winning check and medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 74).

[Medal payout number check process]
Next, with reference to FIG. 109, the medal payout number check process performed in S806 in the winning check and medal payout process (see FIG. 108) will be described. FIG. 109 is a flowchart showing the procedure of the medal payout number check process.

  First, the main CPU 101 adds “1” (+1 update) to the value of the medal OUT counter (S811). The medal OUT counter is a counter for counting the number of medals paid out. Next, the main CPU 101 adds “1” (+1 update) to the value of the payout number counter (S812). The payout number counter is a counter for counting the payout number of medals.

  Next, the main CPU 101 performs a payout number 7SEG display process (S813). In this processing, the main CPU 101 performs control processing to display the value of the payout number counter using a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

  Next, the main CPU 101 performs update processing of the winning combination end number counter (S814). In the bonus run end number counter, the bonus combination is won (the symbol combination of the combination “C_BB1” or “C_BB2” is aligned), so that the number of payouts that can be paid out in the bonus game when the bonus game starts is The counter is for counting (see FIG. 110 described later), counting the remaining number of medals paid out during the bonus game, and determining the end of the bonus game (refer to S822 in FIG. 110 described later). In this process, the main CPU 101 compares the value of the combination ending number counter with its lower limit "0", and if the value of the combination ending number counter is larger than the lower limit "0", the combination ending number The value of the counter is decremented by 1 (-1 update), and when the value of the combination ending sheet number counter is less than the lower limit value "0", the value of the combination ending sheet number counter is held at "0". The number of payouts set in the combination ending number counter does not necessarily become the number actually paid out to the player. For example, 216 combination ending number counters are set, and the combination ending number counter is 215. When the winning combination of nine is won, the actual number of payouts to be paid out is 225. The combination run number counter becomes “0” after 216 sheets are paid out, and thereafter, the lower limit “0” of the value of the combination run number counter is maintained.

  Next, the main CPU 101 subtracts 1 from the value of the winning number counter (-1 update) (S815).

  Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command to be transmitted to the sub control circuit 200. The credit information command is configured to include a parameter for specifying the number of credits of medals.

  Next, the main CPU 101 performs the communication data storage processing described in FIG. 68 (S817). By this processing, credit information command data is stored in the communication data storage area provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing described later with reference to FIG. Then, after the processing of S817, the main CPU 101 ends the medal paid out number check processing, and shifts the processing to the processing of S807 in the prize check and medal payout processing (see FIG. 108).

[BB check processing]
Next, the BB check process performed in S217 in the main flow (see FIG. 74) will be described with reference to FIG. FIG. 110 is a flowchart showing the procedure of the BB check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). When the main CPU 101 determines in S821 that the current gaming state is not the bonus state (when the determination in S821 is NO), the main CPU 101 performs the processing of S831 described later.

  On the other hand, when the main CPU 101 determines in S821 that the current gaming state is the bonus state (when the determination in S821 is YES), the main CPU 101 determines whether the value of the combination ending number counter is "0" or less It is determined whether or not (S822). When the main CPU 101 determines in S822 that the value of the combination ending number counter is not “0” or less (S822 is NO), the main CPU 101 ends the BB check processing, and the main flow of processing (FIG. And the process of S218 in (see 74).

  On the other hand, when the main CPU 101 determines that the value of the combination ending number counter is less than or equal to “0” in S822 (if YES in S822), the main CPU 101 performs bonus end processing (S823). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the on state.

  Next, the main CPU 101 refers to the CT lottery table at the end of bonus (see FIG. 60) and performs CT lottery at the time of bonus end (S824). Next, the main CPU 101 determines whether or not the CT lottery at the end of the bonus is won (S825).

  In S825, when the main CPU 101 determines that CT lottery has not been won (when S825 is NO), the main CPU 101 performs the processing of S827 described later. On the other hand, when the main CPU 101 determines that the CT lottery has been won in S825 (if YES in S825), the main CPU 101 adds “1” to the number of CT sets (S826). When CT lottery is won when the number of ART sets is “0”, “1” is added to the number of CT sets and “1” is also added to the number of ART sets in the process of S 826. .

  After the processing of S826 or when the determination of S825 is NO, the main CPU 101 determines whether the number of ART sets or the number of CT sets is "1" or more (S827).

  In S827, when the main CPU 101 determines that the number of ART sets or the number of CT sets is “1” or more (when S827 is YES), the main CPU 101 sets the ART preparation state to the gaming state of the next game (S828). Then, after the processing of S828, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S827 that the ART set number or the CT set number is not “1” or more (S827: NO), the main CPU 101 sets the normal gaming state to the next gaming state. (S829). Next, the main CPU 101 refers to the normal middle / high probability lottery table (see FIG. 40B), and lottery the lottery state of CZ, and sets the lottery result (S830). Then, after the processing of S830, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 74).

  Here, returning to the processing of S821 again, if S821 is NO, the main CPU 101 determines whether or not the symbol combination (combination of symbols “C_BB1” or “C_BB2”) related to the BB combination is displayed. (S831). When the main CPU 101 determines in S831 that the symbol combination relating to the BB combination is not displayed (S831 is NO), the main CPU 101 ends the BB check processing, and the main flow (see FIG. 74). Transfer to the processing of S218 in the inside.

  On the other hand, when the main CPU 101 determines in S831 that the symbol combination relating to the BB combination is displayed (when S831 is YES determination), the main CPU 101 refers to the bonus type lottery table (see FIG. 58) to read the bonus The type is extracted, and the extraction result is set (S832). Next, the main CPU 101 sets a predetermined value (the number of payouts serving as a bonus termination trigger: “216” in the present embodiment) to the value of the combination run number counter (S833).

  Next, the main CPU 101 performs bonus start processing (S 834). In this process, the main CPU 101 performs various processes necessary to start the bonus operation, such as setting the bonus state to the game state of the next game, for example. Then, after the processing of S834, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 74).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 74) will be described with reference to FIGS. 111 and 112. 111 and 112 are flowcharts showing the procedure of the RT check process.

  First, the main CPU 101 determines whether the RT state is the RT5 state (S841). When the main CPU 101 determines in S841 that the RT state is the RT5 state (when the determination in S841 is YES), the main CPU 101 ends the RT check process, and the process is performed in S219 of the main flow (see FIG. 74). Transfer to the processing of

  On the other hand, when the main CPU 101 determines that the RT state is not the RT5 state in S841 (when the determination in S841 is NO), the main CPU 101 determines whether the RT state is the RT0 state (S842). When the main CPU 101 determines in step S842 that the RT state is not the RT0 state (when the determination in step S842 is NO), the main CPU 101 performs the processing of step S845 described below.

  On the other hand, when the main CPU 101 determines that the RT state is the RT0 state in S842 (when the S842 is a YES determination), the main CPU 101 displays the symbol combination of “Bell spilled eyes” (see FIG. 28). It is determined whether or not it is (S843). When the main CPU 101 determines in S843 that the symbol combination "abbreviated" has not been displayed (S843 returns NO), the main CPU 101 ends the RT check process, and the main flow (FIG. And the process of S219 in 74).

  On the other hand, when the main CPU 101 determines in S843 that the symbol combination of the abbreviation "bell spilled eyes" is displayed (when the S843 is determined as YES), the main CPU 101 sets the RT2 status flag to the on state (S844). . By this process, the RT state shifts from the RT0 state to the RT2 state. Then, after the processing of S844, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  Here, returning to the process of S842 again, if S842 is NO, the main CPU 101 determines whether the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (when S845 is NO), the main CPU 101 performs the processing of S850 described later.

  On the other hand, when the main CPU 101 determines in S845 that the RT state is the RT1 state (when the S845 is a YES determination), the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eyes" is displayed. (S846).

  When the main CPU 101 determines in S846 that the symbol combination of "bell spilled eyes" is displayed (when S846 is a YES determination), the main CPU 101 sets the RT1 status flag to the OFF state, and the RT2 status flag. Is set to the on state (S847). By this process, the RT state shifts from the RT1 state to the RT2 state. Then, after the processing of S847, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S846 that the symbol combination of “Bell spilled eyes” is not displayed (when S846 is NO), the main CPU 101 determines whether 20 games in the RT1 state have passed. It is determined (S848).

  In S848, when the main CPU 101 determines that 20 games in the RT1 state have not elapsed (when the determination in S848 is NO), the main CPU 101 ends the RT check process, and the main flow (see FIG. 74). Move to the processing of S219 in). On the other hand, when the main CPU 101 determines that 20 games in the RT1 state have passed in S848 (if YES in S848), the main CPU 101 sets the RT1 state flag to the OFF state (S849). By this process, the RT state shifts from the RT1 state to the RT0 state. Then, after the processing of S849, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  Here, the process returns to S845 again, and if S845 is NO, the main CPU 101 determines whether the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (when the determination in S850 is NO), the main CPU 101 performs the process of S853 described later.

  On the other hand, when the main CPU 101 determines in S850 that the RT state is the RT2 state (when S850 is a YES determination), the main CPU 101 displays symbol combinations (see FIG. 28) of the abbreviation "RT3 transition lip". It is determined whether or not it is (S851). In S851, when the main CPU 101 determines that the symbol combination of “RT3 transition rep” is not displayed (S851 is NO determination), the main CPU 101 ends the RT check processing, and the main flow (FIG. And the process of S219 in 74).

  On the other hand, when the main CPU 101 determines in S851 that the symbol combination of “RT3 transition ripple” is displayed (when S51 is YES), the main CPU 101 sets the RT2 status flag to the OFF state, and RT3. The status flag is set to the on state (S852). By this process, the RT state shifts from the RT2 state to the RT3 state. After the processing of S852, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  Here, returning to the processing of S850, if the determination of S850 is NO, the main CPU 101 determines whether the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (in the case of NO determination in S853), the main CPU 101 performs the processing of S862 described later.

  On the other hand, when the main CPU 101 determines in S853 that the RT state is the RT3 state (when the determination in S853 is YES), the main CPU 101 displays the symbol combination of “Bell spilled eye” or “RT2 transition lip”. It is determined whether it has been done (S854).

  When the main CPU 101 determines in S 854 that the symbol combination of “bell spilled eyes” or “RT2 transition ripple” is displayed (when S 854 is YES determination), the main CPU 101 sets the RT3 status flag to the OFF state. At the same time, the RT2 state flag is set to the on state (S855). By this process, the RT state shifts from the RT3 state to the RT2 state. Then, after the processing of S855, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S 854 that the symbol combination of “bell spilled eyes” or “RT2 transition lip” is not displayed (when S 854 is NO), the main CPU 101 executes the abbreviation “RT 4 transition”. It is determined whether or not the symbol combination of the "rip" (see FIG. 28) is displayed (S856).

  In S856, when the main CPU 101 determines that the symbol combination “RT4 transition ripple” is not displayed (S856 returns NO), the main CPU 101 ends the RT check process, and the main flow of the process ( Proceed to the processing of S219 in FIG. On the other hand, when the main CPU 101 determines that the symbol combination of “RT4 transition ripple” is displayed in S 856 (when the S 856 is a YES determination), the main CPU 101 sets the RT3 status flag to the OFF state and RT4. The status flag is set to on (S857). By this process, the RT state shifts from the RT3 state to the RT4 state.

  After the processing of S857, the main CPU 101 determines whether the gaming state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the gaming state is not the ART preparation state (when S858 is NO), the main CPU 101 ends the RT check processing, and the processing in the main flow (see FIG. 74) is performed. Transfer to the processing of

  On the other hand, when the main CPU 101 determines that the gaming state is the ART preparation state in S858 (when S858 is YES determination), the main CPU 101 determines whether or not the number of CT sets is "1" or more. (S859).

  In S859, when the main CPU 101 determines that the number of CT sets is “1” or more (when S859 is YES), the main CPU 101 sets the CT to the gaming state of the next game and sets the CT game number counter "8" is set (S860). Then, after the processing of S860, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S859 that the number of CT sets is not "1" or more (S859 is NO), the main CPU 101 sets the normal ART to the gaming state of the next game, and the ART end game A predetermined value is set to the number counter (S861). Then, after the processing of S861, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

  Here again, returning to the processing of S853, if the determination of S853 is NO, the main CPU 101 determines whether or not the symbol combination of “Bell spilled eyes” or “RT2 transition lip” is displayed (S862). When the main CPU 101 determines in S862 that the symbol combination of the abbreviation “bell spilled eyes” or “RT2 transition ripple” is not displayed (when the determination of S862 is NO), the main CPU 101 ends the RT check process. Then, the processing is shifted to the processing of S219 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S862 that the symbol combination of “Bell spilled eyes” or “RT2 transition lip” is displayed (S622 is YES determination), the main CPU 101 turns off the RT4 status flag. And the RT2 status flag is set to ON (S863). By this process, the RT state shifts from the RT4 state to the RT2 state. Then, after the processing of S863, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 74).

[Process at the time of CZ · ART end]
Next, with reference to FIG. 113, CZ · ART end processing performed in S219 in the main flow (see FIG. 74) will be described. FIG. 113 is a flowchart of the CZ · ART termination process.

  First, the main CPU 101 determines whether the current gaming state is either CZ failure or ART termination (S871). When the main CPU 101 determines in S871 that the current gaming state is not one of CZ failure and ART termination (when S871 is NO), the main CPU 101 terminates the CZ · ART termination processing, The processing is shifted to the processing of S201 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S871 that the current gaming state is either CZ failure time or ART termination time (when S871 is YES), the main CPU 101 checks the CZ lottery table (see FIG. 41B). ) And CZ pull-back lottery is performed (S872). Next, the main CPU 101 determines whether or not the CZ pullback lottery has been won (S873).

  In S873, when the main CPU 101 determines that the CZ pull-back lottery has been won (if S873 is YES), the main CPU 101 sets the CZ of the type that has won the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type CZ in the CZ game number counter (S875). Then, after the processing of S875, the main CPU 101 ends the CZ · ART end processing, and shifts the processing to the processing of S201 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S873 that the CZ pullback lottery has not been won (S873 is NO), the main CPU 101 sets the normal gaming state to the next gaming state (S876). Next, the main CPU 101 refers to the normal middle / high probability extraction table (see FIG. 40B), extracts the extraction state of CZ, and sets the extraction result (S877). Then, after the processing of S877, the main CPU 101 ends the CZ · ART end processing, and shifts the processing to the processing of S201 in the main flow (see FIG. 74).

[Interrupt process under control of main CPU (1.1172 msec)]
Next, with reference to FIG. 114, the interrupt processing performed by the main CPU 101 will be described in a cycle of 1.172 msec. FIG. 114 is a flowchart of the interrupt process. The interrupt process repeatedly executed in a cycle of 1.1172 msec occurs based on the output timing of the time-out signal of the timer circuit 113 set in the initialization process (see S2 in FIG. 64) of the timer circuit 113 (PTC). This processing is executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs register save processing (S901). Next, the main CPU 101 performs input port check processing (S902). In this process, various switches such as a start switch 79 and a stop switch connected via the external bus interface 104, index sensors (not shown) provided on the left reel 3L, the middle reel 3C and the right reel 3R, etc. The signals input from the various sensors are checked. In this embodiment, through the cabinet side relay board 44, the door relay terminal board 68, the reel relay terminal board 74, etc., these various switches and various sensors are connected to the input port IC (not shown) through the external bus interface 104. It is connected to the input terminal of the input IC connected to the output terminal of FIG. Further, in the main RAM 103, an input port storage area (not shown) for storing the state of the input port IC (in this embodiment, simply referred to as “input port”) connected to the external bus interface 104 by the main CPU 101. ) Is assigned. Here, the input port storage area includes, for example, an input port storage area 1 for storing the current state of the input port, and an input port storage area 2 for storing the state before one interrupt processing of the input port. It consists of Then, in this processing, the main CPU 101 first stores various information stored in the input port storage area 1 in the input port storage area 2 and then stores various information read from the input port in the input port storage area 1 Do. The connection configuration of the various switches and sensors and the configuration of the input port storage area are not limited to those described above. That is, the main CPU 101 only needs to be able to recognize the on / off states of various switches and various sensors.

  Next, the main CPU 101 performs reel control processing (S903). In this process, the main CPU 101 starts the rotation of the left reel 3L, the middle reel 3C and the right reel 3R when the start of rotation of all the reels is requested, and thereafter the respective reels rotate at a constant speed. Drive control of three stepping motors. When the number of sliding symbols is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the effective line of the display window), and for the corresponding reel. The drive control of the corresponding stepping motor is performed so that the rotation is decelerated and stopped.

  Next, the main CPU 101 performs communication data transmission processing (S904). In this process, various commands stored in the communication data storage area are mainly transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 8) of the main control circuit 90. The details of the communication data transmission process will be described later with reference to FIG. 115 described later.

  Next, the main CPU 101 performs an inserted medal passage check process (S905). In this process, the main CPU 101 performs a process of checking whether the inserted medal has passed the selector 66 based on the detection result (the medal sensor input state) of each medal sensor (see FIG. 5).

  Next, the main CPU 101 performs 7-segment LED drive processing (S906). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6, and displays, for example, the number of medals paid out, the number of credits, the pressing order data of the stop button, and the like. The details of the 7-segment LED driving process will be described later with reference to FIG. 117 described later.

  Next, the main CPU 101 performs timer update processing (S907). In this processing, the main CPU 101 performs count (subtraction) processing of the set various timers. The details of the timer update process will be described later with reference to FIG. 119 described later.

  Next, the main CPU 101 performs an error detection process (S908). Next, the main CPU 101 performs door open / close check processing (S909). In the door open / close check process, the main CPU 101 checks the open / close state of the front door 2b (see FIG. 2) by checking the on (door closed) / off (door open) state of the door open / close monitoring switch 67.

  Next, the main CPU 101 performs a shot test signal control process (S910). In this processing, control processing is performed when outputting various test signals to the tester via the second interface board or the like. Also, this process is performed using the extra-defined work area (see FIG. 11C) of the main RAM 103. In the present embodiment, this process is performed also at the time other than at the time of the trial shot test (after the pachislot 1 is installed in the game arcade), but at this time, the main control board 71 is via the second interface boat or the like. Since various test signals are generated, they are not output because they are not connected to the tester.

  Next, the main CPU 101 performs register restoration processing (S911). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[Communication data transmission process]
Next, with reference to FIG. 115, communication data transmission processing performed in S904 in the interrupt processing (see FIG. 114) will be described. FIG. 115 is a flowchart of the communication data transmission process.

  First, the main CPU 101 performs WDT setting processing (S961). In this processing, the main CPU 101 performs processing such as restarting the WDT in the reset controller 106. The details of the WDT setting process will be described later with reference to FIG. 116 described later.

  Next, the main CPU 101 determines whether the command transmission start timer has counted up (S962). That is, the main CPU 101 determines whether or not transmission of communication data is being delayed. When the main CPU 101 determines in S 962 that the command transmission start timer has not counted up (S 962 is NO), the main CPU 101 ends the communication data transmission processing, and interrupts the processing (FIG. 114). Move to the processing of S 905 in).

  On the other hand, when the main CPU 101 determines that the command transmission start timer has counted up in S 962 (when the determination in S 962 is YES), the main CPU 101 determines whether transmission of communication data is completed (S 963) . Specifically, the main CPU 101 refers to the data stored in the command status register (not shown) of the first serial communication circuit 114 (SCU1), and if the data indicating the transmission completion is stored, the communication data When it is determined that transmission has been completed, and data indicating transmission completion has not been stored, it is determined that transmission of communication data has not been completed.

  When the main CPU 101 determines in S963 that transmission of communication data has not been completed (S963 is NO), the main CPU 101 ends the communication data transmission processing and interrupts the processing (see FIG. 114). Move to the processing of S 905 in. On the other hand, when the main CPU 101 determines in S963 that transmission of communication data has been completed (when the determination in S963 is YES), the main CPU 101 performs communication data acquisition processing (S964). In this process, the main CPU 101 performs a process of acquiring communication data (command data) from the communication data storage area of the main RAM 103.

  Next, the main CPU 101 determines whether or not there is unsent data in the acquired communication data (S965). When the main CPU 101 determines in S965 that there is unsent data in the acquired communication data (when the determination in S965 is YES), the main CPU 101 performs the processing of S969 described later.

  On the other hand, when the main CPU 101 determines in S965 that there is no unsent data in the acquired communication data (S965 returns no), the main CPU 101 sets non-operation command data in each register (S966). ). The non-operation command data is information (for example, these operations have been performed) related to a player's game operation (for example, an insertion operation, a start operation, and a stop operation as an operation for advancing a game). The respective parameters are set so as not to include information indicating... Or information indicating an internal winning combination determined based on the start operation, for example. For each parameter of the non-operation command data, for example, a parameter indicating the on / off state of each switch in pachislot 1 or a parameter indicating the on / off state of each sensor (for example, input port storage area 1) And the information stored in the input port storage area 2 may be set. As a result, the sub control circuit 200 may determine the possibility of malfunction or failure of these switches and sensors.

  Next, the main CPU 101 performs communication data storage processing (see FIG. 68) (S967). That is, the main CPU 101 performs processing for storing the non-operation command data generated in S966 in the communication data storage area of the main RAM 103. Next, the main CPU 101 performs communication data acquisition processing (S968). That is, the main CPU 101 performs processing to acquire the non-operation command data stored in the communication data storage area in S967.

  As described above, in the present embodiment, even when there is no communication data to be transmitted from the main control circuit 90 to the sub control circuit 200, at least a non-operation command is transmitted for each interrupt process (see FIG. 114). It is supposed to be. Therefore, it is possible to prevent transmission of unauthorized communication data from the outside due to the absence of communication data to be transmitted from the main control circuit 90 to the sub control circuit 200. From such a point of view, although the non-operation command data does not include information related to the player's game operation, the content of each parameter to be set is not limited to this, and can be appropriately changed. It is.

  After the processing of S968 or when the determination of S965 is YES, the main CPU 101 sets the buffer size of one packet in the transmission counter (S969). In the present embodiment, since one packet of transmission data is 8 bytes, the buffer size of one packet is similarly configured of 8 bytes. Further, in the present embodiment, when a plurality of communication data (command data) are stored in the communication data storage area, they are transmitted in the order of storage (FIFO format). .

  Next, the main CPU 101 acquires transmission data from the communication buffer and sets it in the transmission data register (S970). Specifically, the main CPU 101 sets transmission data in units of 1 byte in a transmission data register (not shown) of the first serial communication circuit 114 (SCU1). As a result, the set transmission data is transferred to the transmission shift register (not shown) of the first serial communication circuit 114 (SCU1) and is transmitted one packet at a time.

  Next, the main CPU 101 updates (+1) the address of the communication buffer by “1” (S971). Next, the main CPU 101 subtracts “1” from the transmission counter (S972). Next, the main CPU 101 determines whether the transmission counter is "0" (S973). That is, the main CPU 101 determines whether transmission of transmission data for one packet has been completed. In S973, when the main CPU 101 determines that the transmission counter is not “0” (when the determination in S973 is NO), the main CPU 101 returns the process to the process of S970, and repeats the processes after S970.

  On the other hand, when the main CPU 101 determines in S973 that the transmission counter is “0” (YES in S973), the main CPU 101 performs communication data pointer update processing (see, eg, FIG. 69) (S974). ). Then, after the processing of S974, the main CPU 101 ends the communication data transmission processing, and shifts the processing to the processing of S905 in the interrupt processing (see FIG. 114).

[WDT setting process]
Next, with reference to FIG. 116, the WDT setting process performed in S961 in the communication data transmission process (see FIG. 115) will be described. FIG. 116 is a flowchart showing the procedure of the WDT setting process.

  First, the main CPU 101 sets the address of the WDT clear register (not shown) in the WDT in the reset controller 106 (S981). Next, the main CPU 101 sets clear data (for example, “55H”) to the set address (S982). Next, the main CPU 101 sets restart data (for example, “AAH”) at the set address (S983).

  Next, the main CPU 101 compares the command transmission start timer with its lower limit "0", and subtracts 1 from the command transmission start timer (-1 update) if the command transmission start timer is larger than the lower limit "0". If the command transmission start timer is less than or equal to the lower limit "0", the command transmission start timer is held at "0" (S984). Then, after the processing of S984, the main CPU 101 ends the WDT setting processing, and shifts the processing to the processing of S962 of the communication data transmission processing (see FIG. 115).

  As described above, in the present embodiment, the reset setting and management information of WDT (permission / prohibition of WDT, reference clock, timeout time (for example, 419.4 ms), etc.) is stored in the program management area. By performing the process of S983, the set timeout time is remeasured. When the reset signal is output due to time-out and the main CPU 101 is restarted, the restart processing is performed without power-off (external) processing (see FIG. 70) being performed, so checksum generation processing (FIG. 71) is not stored in the main RAM 103 (sum value storage area). Therefore, in this case, the result of the sum check determination in the power-on process (see S11 in FIG. 64) is not normal (that is, it is determined as "RAM abnormal"), and an error occurs in the information display 6 (7 segment LED display). The character string "88" meaning occurrence is displayed.

[7 segment LED drive processing]
Next, with reference to FIG. 117, the 7-segment LED driving process performed in S906 in the interrupt process (see FIG. 114) will be described. FIG. 117 is a flowchart of the 7-segment LED driving process.

  First, the main CPU 101 adds “1” (+1 update) to the value of the interruption counter (S921). Next, the main CPU 101 determines whether the value of the interrupt counter is an odd number (S922).

  If the main CPU 101 determines in S922 that the value of the interrupt counter is not an odd number (if S922 is NO), the main CPU 101 ends the 7-segment LED drive processing and interrupts the processing (see FIG. 114). Move to the process of S907 in). That is, in the present embodiment, the 7-segment LED driving process is performed every two interruption cycles. In the present embodiment, an example in which the 7-segment LED driving process is executed when the value of the interrupt counter is even is described, but the present invention is not limited to this. The 7-segment LED driving process is performed when the value of the interrupt counter is odd. The LED drive processing may be executed, or the execution timing of the 7-segment LED drive processing may be determined using the quotient or remainder obtained by dividing the value of the interrupt counter by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in step S922 that the value of the interruption counter is an odd number (when the determination in step S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets an address of a pressing order display data storage area for storing pressing order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 118 described later.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets an address of a credit display data storage area for storing credit display data to be output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs 7-segment display data generation processing (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 118 described later.

  Next, the main CPU 101 sets an address of a 7-segment common counter storage area for storing a value of a 7-segment common counter described later (S929). Next, the main CPU 101 adds “1” (+1 update) to the value of the 7-segment common counter (S930). In this process, when the value of the 7-segment common counter after updating becomes “8”, the main CPU 101 sets “0” to the value of the 7-segment common counter. In this embodiment, in order to perform dynamic control of the 7-segment LED, the value of the 7-segment common counter is updated in a cycle of eight times.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and the address of the target cathode data storage area (target storage area in push order display data storage area or credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed to temporarily turn off the 7-segment LED to eliminate the influence of an afterimage.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED driving processing, and shifts the processing to the processing of S907 in the interrupt processing (see FIG. 114).

[7 segment display data generation process]
Next, with reference to FIG. 118, 7-segment display data generation processing performed in S925 and S928 in the 7-segment LED driving processing (see FIG. 117) will be described. FIG. 118 is a flowchart of the 7-segment display data generation process.

  Note that “display data” described later generated in the 7-segment display data generation processing performed in S925 during the 7-segment LED driving processing (see FIG. 117) corresponds to the pressing order display data, and the 7-segment LED driving processing ( The “display data” described later, which is generated in the 7-segment display data generation process performed in S928 in “see 117” corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, acquires the value of the quotient of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and performs division The remaining value of the result is acquired as display data of lower digits (S941). Next, the main CPU 101 determines whether to display the upper digit based on the acquired display data of the upper digit (S942).

  In S942, when the main CPU 101 determines that the upper digit display is to be performed (when the determination in S942 is YES), the main CPU 101 performs the processing of S944 described later. On the other hand, when the main CPU 101 determines in S942 that the upper digit display is not to be performed (S942 is NO), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when the determination of S942 is YES, the main CPU 101 refers to the 7-segment cathode table (not shown) and acquires display data of the upper digit (S944). Next, the main CPU 101 stores the display data of the upper digit acquired in the display data storage area (not shown) of the upper digit (S945).

  Next, the main CPU 101 acquires display data of lower digits with reference to a 7-segment cathode table (not shown) (S946). Next, the main CPU 101 stores the acquired lower digit display data in the lower digit display data storage area (not shown) (S947).

  Then, after the process of S947, the main CPU 101 ends the 7-segment display data generation process. At this time, if the executed 7-segment display data generation process is the process of S925 in the 7-segment LED drive process (see FIG. 117), the main CPU 101 proceeds to the process of S926 in the 7-segment LED drive process. Move. On the other hand, if the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 117), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. .

[Timer update processing]
Next, with reference to FIG. 119, the timer update process performed in S907 in the interrupt process (see FIG. 114) will be described. FIG. 119 is a flowchart of the timer update process.

  First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the 2-byte timer number in the B register (S951). The 2-byte timer storage area is used to manage time of 286 ms (256 × 1.1172 ms) or more (that is, a timer value exceeding 1 byte).

  Next, the main CPU 101 compares the 2-byte timer number with its lower limit "0", and subtracts "1" from the 2-byte timer number if the 2-byte timer number is greater than the lower limit "0". If the 2-byte timer number is less than or equal to the lower limit "0", the 2-byte timer number is held at "0" (S952). Furthermore, in the process of S952, the main CPU 101 subtracts 2 from the update start address of the 2-byte timer storage area set in the HL register (-2 update). Note that, for example, since the command transmission start timer is also a 2-byte timer, the update may be performed in this process (see FIG. 116).

  Next, the main CPU 101 subtracts one from the number of 2-byte timers set in the B register (update by -1) (S953). Next, the main CPU 101 determines whether the number of 2-byte timers set in the B register is “0” (S954).

  When the main CPU 101 determines in S954 that the number of 2-byte timers set in the B register is not “0” (S954 is NO), the main CPU 101 returns the processing to the processing of S952, and Repeat the process.

  On the other hand, when the main CPU 101 determines that the number of 2-byte timers set in the B register is "0" in S954 (when the determination in S954 is YES), the main CPU 101 stores the 1-byte timer storage area in the HL register. The update start address of is set, and the 1-byte timer number is set in the B register (S 955). The 1-byte timer storage area is used to manage time less than 286 ms (i.e., a timer value not exceeding 1 byte). For example, the medal monitoring timer is updated as a 1-byte timer.

  Next, the main CPU 101 compares the number of 1-byte timers with the lower limit “0”, and subtracts 1 from the number of 1-byte timers if the number of 1-byte timers is larger than the lower limit “0” (−1 updated) If the number of 1-byte timers is equal to or less than the lower limit value "0", the number of 1-byte timers is held at "0" (S956). Furthermore, in the process of S956, the main CPU 101 subtracts one from the update start address of the 1-byte timer storage area set in the HL register (−1 update).

  Next, the main CPU 101 subtracts one from the number of one-byte timers set in the B register (−1 update) (S957). Next, the main CPU 101 determines whether the number of 1-byte timers set in the B register is “0” (S958).

  In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not “0” (when the determination in S958 is NO), the main CPU 101 returns the processing to the processing of S956. Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is “0” (YES in S958), the main CPU 101 performs an electromagnetic counter control process (S959). ). In this process, an output control process at the time of outputting a signal indicating IN / OUT of the medal to the external concentrated terminal plate 47 is performed. Then, after the processing of S959, the main CPU 101 ends the timer update processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 114).

<Description of operation at power on>
Next, with reference to FIG. 120, an operation at the time of powering on of the pachislot according to the embodiment of the present invention will be described. FIG. 120 is a timing chart showing an example of the operation when the Pachi-slot 1 is powered on.

  In FIG. 120, "Main CPU" indicates the main CPU 101 (main control circuit 90), and "Sub CPU" indicates the sub CPU 201 (sub control circuit 200).

  Further, in FIG. 120, the operation state "security mode" of "Main CPU" shows the state in the security mode described above, and the operation state "start delay period" of "Main CPU" mentioned above after the end of the security mode. Indicates the period until the command transmission start timer is set and the set command transmission start timer becomes “0” (that is, the period during which the setting change is possible but the transmission of communication data is delayed), The operation state “normal operation period” of the “Main CPU” indicates a state in which the transmission of communication data is completed and communication data can be transmitted to the sub CPU 201 (sub control circuit 200).

  Further, in FIG. 120, the operation state “initialization” of “SubCPU” is the initialization (activation) processing (hard activation time, BIOS (driver) initialization, etc.) at power-on of the sub CPU 201 (sub control circuit 200). (OS) Indicates a state in which activation is in progress (that is, a state in which reception of communication data transmitted from the main CPU 101 (main control circuit 90) is not possible), and an operation state "normal operation period" of "SubCPU" It shows a state in which the initialization (activation) process at the time of power-on is completed, and the reception of communication data transmitted from the main CPU 101 (main control circuit 90) becomes possible.

  Also, in FIG. 120, “setting operation A” starts setting change in the “startup delay period” (for example, the power of the pachi slot 1 is turned on with the setting key type switch 54 turned on), and then “normal "Transmission mode A" indicates the operation when setting change is completed in the "operation period", and the setting change command (setting change / setting check start) (COM1) in the case of "setting operation A", and setting change The transmission timing of the command (setting change / setting confirmation end) (COM2) is shown. In "Main CPU setting change processing" under "Transmission mode A", the setting change command indicates the communication of the main RAM 103 in the setting change confirmation process (see FIG. 66) by the main CPU 101 in the case of "Transmission mode A". This shows the timing of storage (registration) in the data storage area (see also the setting change command generation and storage process of FIG. 67 and the communication data storage process of FIG. 68).

  Further, in FIG. 120, “setting operation B” starts setting change in the “startup delay period” (for example, the power of the pachi slot 1 is turned on with the setting key type switch 54 turned on), and thereafter, "Transmission mode B" indicates the operation when setting change is ended in the start delay period ", and the setting change command (setting change / setting check start) (COM1) in the case of" setting operation B "(COM1), and setting The transmission timing of the change command (setting change / setting confirmation end) (COM2) is shown. In "Main CPU setting change processing" under "Transmission mode B", the setting change command indicates the communication of the main RAM 103 in the setting change confirmation process (see FIG. 66) by the main CPU 101 in the case of "Transmission mode B". This shows the timing of storage (registration) in the data storage area (see also the setting change command generation and storage process of FIG. 67 and the communication data storage process of FIG. 68).

  When the power of the pachi slot 1 is turned on and a reset signal is input, the security unit (not shown) of the microprocessor 91 is controlled to the operation state of the security mode. In the security mode, activation of the main CPU 101 is delayed for a period corresponding to the setting stored in the security setting area. When the security mode ends, the main CPU 101 delays transmission of communication data for a predetermined period. Note that the main CPU 101 can change the setting even when the transmission of communication data is delayed.

  Here, as shown in “setting operation A”, when the setting change is started during the delay of transmission of communication data and the setting change is ended after the delay of transmission of communication data is ended, the main CPU 101 performs communication The setting change command (setting change / setting check start) (COM1) is sent to the sub control circuit 200 when the delay of data transmission ends, and the setting change command (setting Change / setting confirmation end) (COM 2) is sent to the sub control circuit 200.

  On the other hand, as shown in “setting operation B”, when the setting change is started during the delay of transmission of communication data and the setting change is ended during the delay of the transmission of communication data, the main CPU 101 When the delay of transmission ends, the setting change command (setting change / setting confirmation start) (COM1) and the setting change command (setting change / setting confirmation end) (COM2) are sequentially transmitted to the sub control circuit 200. . That is, when the delay of transmission of communication data ends, the setting change command (setting change / setting check start) (COM1) and the setting change command (setting change / setting check end) (COM2) are stored in the communication data storage area. If registered, these communication data are transmitted in the order of registration.

  As described above, according to the pachi slot 1 of the present embodiment, the main control circuit 90 can be stably started by delaying the start of the main CPU 101 when the pachi slot 1 is powered on. By delaying the transmission of communication data after the delay is completed, it is possible to secure the time required for activating the sub control circuit 200 and stably activate the sub control circuit 200.

  Then, after the delay of the activation of the main CPU 101 is finished, the setting can be changed even before the delay of transmission of communication data is ended. For example, when opening a store in a game arcade, When the power supply of 1 is turned on (that is, when the reset signal is input in connection with this), the setting change can be made in advance without waiting for the completion of activation of the sub control circuit 200. Work efficiency can be improved.

  Furthermore, when the setting change is performed before the delay of transmission of communication data ends, communication data indicating these is registered at the start of the setting change or at the end of the setting change, and the delay of the communication data transmission is Since these communication data are transmitted in the order in which they were registered when they are completed, even if the setting change is made in advance without waiting for the completion of activation of the sub control circuit 200, As a result, it is possible to prevent the occurrence of wrinkles in the information held between the main control circuit 90 and the sub control circuit 200. In addition, for example, even in the case where the sub control circuit 200 is configured to perform the determination of an unauthorized action or an error according to the order of the communication data transmitted from the main control circuit 90, the result of such determination It is possible to make an accurate determination without affecting the

  Further, according to the pachislot 1 of the present embodiment, at least the non-operation command data is transmitted even when the communication data is not registered when the communication data transmission process is performed. For example, it becomes possible to prevent transmission of communication data from the outside by an illegal means such as illegally accessing a connection line between the main control circuit 90 and the sub control circuit 200. In addition, since the registration / transmission of the non-operation command data is not performed before the delay of transmission of communication data is completed, it is possible to reduce the control load when the pachislot 1 is powered on. It should be noted that the non-operation command data may be configured so as not to include information related to the game operation of the player, from the viewpoint of mainly aiming at preventing fraudulent acts.

  Further, according to the pachi slot 1 of the present embodiment, the delay period of activation of the main CPU 101 is configured of a fixed period and a variable period, and these periods (or their ranges) can be appropriately selected and set. Thus, according to the specifications of the main control circuit 90 and the sub control circuit 200, it is possible to set an appropriate delay time. In addition, from the viewpoint of shortening the period until the setting change becomes possible, it is possible to set a range of a predetermined period (for example, “no setting” in the random extension period) in which 0 is necessarily determined as the variable period. In this case, the range of the predetermined period may be set.

  In this embodiment, an example in which setting operation (setting change operation) can be performed during a period in which transmission of communication data is delayed after the end of the security mode ("start delay period") will be described. However, the operation that can be performed in the period in which the transmission of communication data is delayed ("start delay period") is not limited to this. For example, the power of the pachi slot 1 is turned on with the setting key type switch 54 in the off state, and the setting key type switch 54 is in the on state during a period in which transmission of communication data is delayed ("start delay period"). In this case, the confirmation operation (setting confirmation operation) of the setting value may be enabled during the period. Thus, for example, when opening a store, the setting change is not performed, but even if it is desired to check the current set value, etc., the setting confirmation is made without waiting for the start of the sub control circuit 200 to complete. Since it can carry out, it becomes possible to improve the work efficiency at the time of power activation.

<Operation explanation at the time of medal insertion>
Next, with reference to FIG. 121, an operation at the time of medal insertion of the pachislot according to the embodiment of the present invention will be described. FIG. 121 is a timing chart showing an example of the operation of the pachi-slot 1 at the time of medal insertion.

  In FIG. 121, “start switch” indicates the start switch 79, and “medal sensor” indicates the detection state of the upstream medal sensor (first medal sensor) 806 and the downstream medal sensor (second medal sensor) 807. (Medal sensor input state) is shown, and the “medal acceptance signal” indicates that the on state (“ON”) is the state where medal acceptance is permitted (the medal acceptance permission), and the off state (“OFF”) is the medal The state in which the reception of the key is prohibited (the medal reception prohibition) is shown (see FIGS. 75 and 76).

  Further, in FIG. 121, “solenoid” indicates the solenoid of the selector 66 (drive source for shifting the select plate 804 to the guide position or the discharge position), and “monitoring timer” indicates the medal monitoring timer (FIGS. 75 and FIG. 76), “Operation state” is a state (“in game”) that allows the progress of the game after the start operation in the pachislot 1 (“playing in progress”) and a state that does not allow the progress of the game after the start operation ") And.

  When the number of medals for which the game start is possible (three in the present embodiment) is inserted, the main CPU 101 can accept the start operation to the start lever 16. As shown in FIG. 121, in this state, if medals can be stored as the number of credits (if the number of credits is less than 50), the start operation to the start lever 16 is performed (started by the start switch 79) Until the operation is detected), the state in which the reception of the medal is permitted (the state in which the medal reception signal is “ON”) continues. Although illustration is omitted, in this state, if it is not possible to store medals as the number of credits (if there are 50 credits), a state where reception of medals is prohibited (the medal acceptance signal is “OFF” State).

  In the state where the main CPU 101 is inserted with medals for the number of games that can be started (three in this embodiment) and can store medals as the number of credits, the start operation is performed by the start switch 79 (the first start on the left in FIG. 121) When an operation (transition from "OFF" to "ON" of start switch 79) is set to "start operation A", a state where reception of medals is permitted (a medal reception signal is "ON") It shifts from a certain state to a state where medal acceptance is prohibited (the medal acceptance signal is "OFF"), and starts to shift the solenoid of the selector 66 to the demagnetized state, and monitoring by the medal monitoring timer ( Start measurement). At this time, the above-described start lever ON flag is turned on.

  The main CPU 101 checks whether medals have been input (in other words, before the solenoid of the selector 66 has been completely shifted from the excited state to the de-energized state) during monitoring (measurement) by the medal monitoring timer (medal sensor input for each medal sensor) In the case where it is determined based on the state that the medal has been inserted), the inserted medal is counted by changing the solenoid of the selector 66 which has been in transition from the excitation state to the demagnetization state to the excitation state again It is guided in the hopper device 51. Further, in this case, although the "start operation A" is detected by the start switch 79, in the state ("in game") which enables the progress of the game after the operation start operation based on the detection Do not shift. At this time, the above-described start lever ON flag is turned off. That is, in this case, the "start operation A" is invalidated.

  When the main CPU 101 is monitoring (measuring) by the medal monitoring timer (that is, before the solenoid of the selector 66 becomes the transition from the excitation state to the demagnetization state), the medal is inserted (the medal of each medal sensor) In the case where it is determined that the medal has been inserted based on the sensor input state), the reception of the medal is further permitted from the state in which the reception of the medal is prohibited (the state in which the medal reception signal is "OFF") It may be made to shift to a state (a state in which the medal acceptance signal is “ON”).

  After that, the main CPU 101 starts the start operation again by the start switch 79 (in FIG. 121, the second start operation on the right (transition from “OFF” to “ON” of the start switch 79) is “start operation B”) When is detected, the solenoid of the selector 66 is again changed from the energized state to the de-energized state, and monitoring (measurement) by the medal monitoring timer is started again. At this time, the above-described start lever ON flag is turned on again.

  Then, when the main CPU 101 monitors (measures) by the medal monitoring timer (that is, before the solenoid of the selector 66 becomes the transition from the excitation state to the demagnetization state), the medal is not inserted (for each medal sensor) In the case where it is not determined that the medal has been inserted based on the medal sensor input state), the operation state is performed after monitoring (measurement) by the medal monitoring timer ends (that is, after the solenoid of the selector 66 completes transition from the excitation state to the demagnetization state) Is changed to a state ("in game") which enables the progress of the game after the start operation and enables the progress of the game (that is, after medal acceptance / start check processing (see FIG. 75 and FIG. 76) Processing can be performed).

  Although illustration is omitted, the main CPU 101 detects medals “start operation A” by the start switch 79 and allows medal acceptance from the state where the medal acceptance is permitted (state where the medal acceptance signal is “ON”). Changed to a state where the acceptance of the medal is prohibited (the state that the medal acceptance signal is "OFF"), started to shift the solenoid of the selector 66 to the demagnetized state, and started monitoring (measurement) by the medal monitoring timer After that, during the monitoring (measurement) by the medal monitoring timer (that is, before the solenoid of the selector 66 becomes complete transition from the excitation state to the demagnetization state), when the medal is not inserted (the medal sensor input state of each medal sensor) Same as when start operation B is detected by start switch 79). A state that enables the progress of the game after the start operation of the operation state ("in game") after the monitoring (measurement) by the medal monitoring timer is completed (that is, after the solenoid of the selector 66 has been changed from the excitation state to the demagnetization state) To allow the game to proceed (that is, processing after the medal acceptance / start check processing (see FIGS. 75 and 76) can be executed).

  As described above, according to the pachislot 1 of the present embodiment, when the game is started along with the player's start operation, for example, the medal monitoring timer for preventing the occurrence of the medal "snipping" etc. Is set. The medal monitoring timer causes the selector 66 to discharge the inserted medal to the outside of the gaming machine from a state where the inserted medal is stored inside the gaming machine (a state in which the select plate 804 is at the guide position due to the solenoid being excited). The time until the state physically shifts to the state (the state in which the select plate 804 is in the discharge position due to the demagnetization of the solenoid) is secured.

  When the medal is inserted during monitoring (measurement) by the medal monitoring timer, the start operation as the origin is invalidated, and the inserted medal is inserted into the gaming machine in the selector 66. It returns to the state of being stored. Therefore, it is possible to appropriately process the inserted medals by preventing the occurrence of the "snipping" of the medals and the like.

  Further, according to the pachislot 1 of the present embodiment, even when a medal is inserted during monitoring (measurement) by the medal monitoring timer, the medal is counted, so The omission of counting can be prevented, and the inserted medals can be processed more appropriately.

  Further, according to the pachislot 1 of the present embodiment, the timer value (for example, "72") of the medal monitoring timer is changed from the state where the inserted medal is stored inside the gaming machine to the state where it is discharged outside the gaming machine Since it is set to a period (for example, “72” × 1.1172 ms) or more (for example, 80 ms) before physical transition, generation of “slow-in” and the like of medals is reliably prevented. Therefore, it is possible to more appropriately process the inserted medals. In the case where the drive unit is a solenoid as in the present embodiment, such an effect is more remarkable.

<Various modifications>
The configuration and operation of the gaming machine of the invention according to the present embodiment have been described above including the effects and advantages thereof. However, the invention according to the present embodiment is not limited to the above-described embodiment, and various other embodiments and modifications are included without departing from the scope of the invention according to the present embodiment.

[Another example of awarding benefits]
In the pachislot 1 of the above embodiment, the notification content is controlled based on the result of the flag conversion lottery performed on the main side, so the symbol combination displayed is different when the stop operation is performed according to the notification. That is, although the said embodiment demonstrated the example which determines whether a privilege is provided based on the result of the flag conversion lottery performed by the main side, this invention is not limited to this. For example, on the main side (main control board 71), a benefit may be provided based on the symbol combination actually displayed.

  In this case, when the predetermined symbol combination is displayed according to the notification performed according to the result of the flag conversion lottery, the main control board 71 (main CPU 101) gives a privilege and does not follow the notification. Even if a predetermined symbol combination is displayed, a benefit may not be given. In the pachislot 1 of the above embodiment, the symbol combinations displayed in accordance with the pressing order are different, but even when the player ignores the notification and performs the stop operation, the symbol combination relating to the “triple chiri lip” is abbreviated. Etc. Special symbol combinations such as may be displayed. Therefore, in this example, even if the special symbol combination is displayed ignoring the notification, the privilege is given only when the special symbol combination is displayed according to the notification without giving the benefit. May be

[Another example of normal ART or CT end condition]
The termination condition of the normal ART or CT is not limited to the example described in the above embodiment, and any termination condition can be adopted. For example, the number of medals awarded during normal ART or CT, the number of unit game digests during normal ART or CT, the number of notification of information advantageous to the player during normal ART or CT. A termination condition such as the number of sets when the predetermined number of games (for example, 50 games) is one set, and a continuation rate at the end of one set can be adopted.

  Also, as a method of counting the number of medals awarded during normal ART or CT, for example, a method of counting the number of medals paid out in a unit game may be adopted, or payout in a unit game is made. A method may be employed in which the difference number (net increase number) is calculated by subtracting the bet number of the medal used in the unit game from the number of medals obtained. In addition, as a method of counting the number of medals awarded during normal ART or CT, a method of calculating based on the actually increased medals (calculation by actual value) may be adopted, or is it actually increased? A method (calculation based on an ideal value) may be employed which calculates based on the number of medals scheduled to be increased in accordance with the notification regardless of whether or not the notification is made.

  In addition, a configuration may be adopted in which the number of medals awarded is not increased according to the type of internal winning combination, that is, not counted as the number of medals or the number of difference medals serving as the termination condition of the number of medals awarded. . For example, even if the part combination (rare combination) with a low probability of being determined as the internal combination, or the combination of display / non-display of the symbol combination being switched according to the timing of the stop operation is determined as the internal combination. The number of medals may not be increased or decreased (counted).

[Others]
The content of the notification performed during the normal ART or during the CT is not limited to the above-described example, and is arbitrary. For example, the order (pushing order) of stop operation in which a special symbol combination that is advantageous to the player is displayed may be notified, or the timing of the stop operation necessary to display the symbol combination It is also possible to notify of a symbol to be aimed.

  A state advantageous to the player is that the probability of winning of the internal winning combination relating to replay does not change (or changes within a range that does not affect the playability), but the mode of stop operation advantageous to the player The notification function may be a gaming state in which the AT function operates. Further, as a state advantageous to the player, a state of high play probability (replay time) in which the probability of winning of the internal winning combination relating to the re-play becomes high is activated, and a mode of stop operation advantageous to the player is notified. A function may be activated, that is, a gaming state in which the ART function is activated.

  Further, in the above embodiment and various modifications, the pachislot machine has been described as an example of the gaming machine, but the gaming machine to which the invention according to the present embodiment can be applied is not limited to this. For example, features other than pachislo-specific features, such as features relating to reel stop control based on stop operation, are also applicable to gaming machines called "pachinko", and similar effects can be obtained.

[Scalability of gaming machine according to the other embodiment]
In the pachislot 1 of the present embodiment, the player's medal insertion operation (i.e., an operation of inserting a hand-held medal into the medal insertion slot 14 or a credited medal is the MAX bet button 15a or 1 bet button 15b). When the game is started by the operation to insert and the operation is inserted, and there is a payout of the medal when the game is over, the hopper device 51 is driven and the medal is paid out from the medal payout opening 24, or the credit Although the embodiment has been described, the present invention is not limited to this.

  For example, the game medium necessary for the game is inserted by the player, the game is performed based thereon, and the present invention is applied to all the modes in which a privilege is given (for example, medals are paid out) based on the result of the game. be able to. That is, the game control medium 90 (main control board 71) itself is a game medium owned by the player as well as a mode in which the game medium is inserted (hanged) by the operation of the physical player and the game medium is paid out. May be electromagnetically managed to enable games without medals. In addition, the game medium management device installed in (connected to) the main control circuit 90 (main control board 71) to manage game media held by the player electromagnetically may be a game medium management device that manages game media. .

  In this case, the gaming medium management device is a device provided in the gaming machine, having ROM and RWM (or RAM), and bi-directional communication with an external gaming medium handling device (not shown) via a predetermined interface. It is possible to be connected, and the lending operation of gaming media (that is, the operation of providing the necessary gaming media when the player performs the operation of inserting the gaming media) or the prize for winning the role related to the payout of gaming media ( The game media payout operation when the role is established (that is, the operation of acquiring the necessary game media when the player is paid out the game media), or the game media to be used for the game It is sufficient that the operation of recording electromagnetically can be performed. In addition, the gaming media management device displays the number of gaming media held on the front of the pachislot 1 based on not only management of the actual number of gaming media but also, for example, management results of the number of gaming media. A number display device (not shown) may be provided to manage the number of game media displayed on the stored game media number display device. That is, the gaming media management device may be capable of recording and displaying the total number of gaming media that the player can use for gaming by an electromagnetic method.

  Also, in this case, the gaming media management device has the capability of allowing the player to freely transmit a signal indicating the number of gaming media recorded to the external gaming media handling device, and the player In addition to the case of direct operation, the number of recorded game media can not be reduced, and when an external connection terminal board (not shown) is provided between an external game medium handling device It is desirable that the player can not transmit a signal indicating the recorded number of game media without using the external connection terminal board.

  In addition to the above, the gaming machine is provided with a lending operation means operable by the player, a return (settlement) operation means, and an external connection terminal board, and the gaming medium handling device is a slot for inserting valuable values such as bills, a recording medium (For example, an IC card) insertion slot, a non-contact communication antenna for receiving electronic money etc. from a portable terminal, etc., other operation means such as lending operation means, return operation means, game medium handling device side external connection terminal board It may be provided (all not shown).

  As the flow of the game at that time, for example, the player deposits a valuable value to the game medium handling device by any method, and subtracts a predetermined number of valuable values based on the operation of any one of the lending operation means described above. The game media corresponding to the valuable value subtracted from the game media handling device to the game media management device is increased. Then, the player plays a game, and when the game medium is required, the above operation is repeated. Thereafter, a predetermined number of game media are obtained as a result of the game, and the game media management device transmits the number of game media from the game media management device to the game media handling device by operating any return operation means when ending the game. The medium handling device ejects a recording medium recording the number of game media. The gaming media management device clears the number of gaming media stored by itself when transmitting the number of gaming media. The player brings the discharged recording medium to a prize counter or the like to exchange prizes, or moves the game platform to play a game based on the game medium recorded on another platform.

  In the above example, all gaming media are transmitted to the gaming media handling apparatus, but the gaming machine or gaming media handling apparatus transmits only the number of gaming media desired by the player and the gaming media possessed by the player It may be divided and processed. In addition to discharging the recording medium, cash or cash equivalents may be discharged, or may be stored in a portable terminal or the like. Further, the gaming medium handling device may insert a member recording medium of the game arcade, and store the member recording medium in the member recording medium so as to be able to play again later.

  Further, in the gaming machine or game medium handling apparatus, it is possible to execute the lock operation for locking the data communication of the game medium or the valuable value to the game medium handling apparatus or the game medium management apparatus by operating the predetermined operation means (not shown). It is also good. At that time, the player may be stored by setting information which can be known only to the player such as a one-time password, or by an imaging means provided in the gaming machine or the gaming medium handling apparatus.

  In addition, as described above, this gaming media management device may be capable of playing a game only without medals, or gaming media may be inserted (hanged) by the action of a physical player. It may be possible to play the game in a form in which money is paid out, and a form in which the game can be made without medals, or in both forms. In this case, the game medium management device may adopt a method of directly controlling the selector 66 and the hopper device 51 described above, which are controlled by the main control circuit 90 (main control board 71), Adopting a method that enables control to perform control to record and display the total number of game media that the player can use for gaming based on the transmission of the control result by an electromagnetic method. You can also.

  Further, although the above describes the case of applying the gaming media management device to the pachislot 1, the gaming media management device is similarly provided in the slot machine and the enclosed type gaming machine using the gaming ball described above, and the player Game media can be controlled.

  As described above, by providing the above-described gaming medium management device, it is possible to reduce the number of selectors 66 and the hopper device 51 inside the gaming machine compared to the case where the gaming medium is physically provided for gaming. Not only can reduce the cost and production cost of the game, but also prevent the player from directly contacting the game media, and the game environment can be improved, noise can be reduced, and the number of devices has been reduced. It also reduces the power consumption of In addition, it is possible to prevent fraudulent acts through the insertion slot and the payout opening of the game media and the game media. That is, it is possible to provide a gaming machine capable of improving various environments surrounding the gaming machine.

<Supplementary Note (Summary of the Invention)>
[The game machine of the 1st-3rd composition]
In the conventional gaming machine, it is known that the degree of advantage (setting value) of the player regarding the game can be changed by turning on the power with the setting key switch provided in the gaming control device ON. (See, for example, JP-A-2006-055444).

  In the conventional gaming machine, the effect control device reliably receives a command transmitted from the game control device by delaying the activation of the game control device more than the activation of the effect control device (subordinate control device). What was made to be able to do it is known (for example, refer to JP, 2012-205,773A).

  By the way, in recent years, for the purpose of further improving the interest about the effect, the high definition of the image quality of the effect image to be displayed and the sound quality of the BGM to be output has been advanced. For this reason, since the process at the time of start of the effect control device is also complicated, and the amount of data expanded at the time of start is also increased, there is a reality that the start time of the effect control device is longer than before.

  Under such circumstances, it is possible to change the setting value (setting change) if the game control device is to be started after waiting for the start of the effect control device as in the gaming machine of JP 2012-2055773. For example, when performing a store opening operation in a game arcade, a situation occurs in which the setting can not be easily changed even if the game machine is powered on, resulting in work efficiency. Problems such as lowering the

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of improving the work efficiency at the time of power on.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine having the following first configuration.

A gaming machine (e.g., pachislot 1) including a game control unit (e.g., main control circuit 90) for controlling a game operation and an effect control unit (e.g., sub control circuit 200) for controlling an effect operation
The game control unit
An arithmetic processing unit (for example, the main CPU 101) that executes various processes for controlling the game operation;
A first storage unit (for example, the main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored;
A second storage unit (for example, the main RAM 103) in which information is stored based on execution of various processes by the arithmetic processing unit;
A security unit (eg, microprocessor 91) having a security function;
A serial communication unit (for example, the first serial communication circuit 114) for performing serial communication;
The first storage unit is
A program area (for example, a program area) in which a program for the arithmetic processing unit to execute various processes is stored;
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored;
A management area (for example, a program management area and a security setting area) in which settings and management information of the arithmetic processing unit and the security unit are stored;
The security unit includes startup delay means for delaying startup of the arithmetic processing unit based on the input of a reset signal,
The game control unit
Communication data registration means (for example, communication data storage processing shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit;
Communication data transmission means (for example, communication data transmission processing shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area via the serial communication unit to the effect control unit;
Transmission delay means (for example, a command transmission start timer) for delaying transmission of communication data by the communication data transmission means for a predetermined period;
Setting value setting means (for example, setting key type switch 54) capable of setting setting values (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game;
The activation delay unit delays activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays transmission of communication data by the communication data transmission means after the start delay of the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of the set value even when the transmission delay means delays transmission of communication data.
The communication data registration means may be arranged in the communication data storage area when setting of the setting value by the setting value setting means is started, even when transmission of communication data is delayed by the transmission delay means. The first communication data (for example, setting change command (setting change / setting confirmation start)) can be registered, and when setting of the setting value by the setting value setting unit is completed, the second communication data storage area Enables the registration of the communication data (for example, setting change command (setting change / setting confirmation end)) of
The communication data transmission unit is configured to register the first communication data and the second communication data in the communication data storage area when the transmission delay of the communication data by the transmission delay unit ends. A game machine characterized by transmitting these communication data in the registered order.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide the following gaming machine of the second configuration.

A gaming machine (e.g., pachislot 1) including a game control unit (e.g., main control circuit 90) for controlling a game operation and an effect control unit (e.g., sub control circuit 200) for controlling an effect operation
The game control unit
An arithmetic processing unit (for example, the main CPU 101) that executes various processes for controlling the game operation;
A first storage unit (for example, the main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored;
A second storage unit (for example, the main RAM 103) in which information is stored based on execution of various processes by the arithmetic processing unit;
A security unit (eg, microprocessor 91) having a security function;
A serial communication unit (for example, the first serial communication circuit 114) for performing serial communication;
The first storage unit is
A program area (for example, a program area) in which a program for the arithmetic processing unit to execute various processes is stored;
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored;
A management area (for example, a program management area and a security setting area) in which settings and management information of the arithmetic processing unit and the security unit are stored;
The security unit includes startup delay means for delaying startup of the arithmetic processing unit based on the input of a reset signal,
The game control unit
Communication data registration means (for example, communication data storage processing shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit;
Communication data transmission means (for example, communication data transmission processing shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area via the serial communication unit to the effect control unit;
Transmission delay means (for example, a command transmission start timer) for delaying transmission of communication data by the communication data transmission means for a predetermined period;
Setting value setting means (for example, setting key type switch 54) capable of setting setting values (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game;
The activation delay unit delays activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays transmission of communication data by the communication data transmission means after the start delay of the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of the set value even when the transmission delay means delays transmission of communication data.
The communication data registration means may be arranged in the communication data storage area when setting of the setting value by the setting value setting means is started, even when transmission of communication data is delayed by the transmission delay means. The first communication data (for example, setting change command (setting change / setting confirmation start)) can be registered, and when setting of the setting value by the setting value setting unit is completed, the second communication data storage area Enables the registration of the communication data (for example, setting change command (setting change / setting confirmation end)) of
The communication data transmission means is for transmitting communication data registered in the communication data storage area at regular intervals,
When the first communication data and the second communication data are registered in the communication data storage area when the delay of transmission of communication data by the transmission delay means is completed, these communication data are used. Send in the registered order,
In the case where transmission of communication data is not delayed by the transmission delay means, and when communication data is not registered in the communication data storage area, the communication data registration area is placed in the communication data storage area by the communication data registration area. A game machine characterized by registering communication data (for example, no operation command) and transmitting the registered third communication data.

  Further, in the gaming machine of the second configuration, the third communication data does not include information related to the game operation of the player by the effect control unit.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following third configuration.

A gaming machine (e.g., pachislot 1) including a game control unit (e.g., main control circuit 90) for controlling a game operation and an effect control unit (e.g., sub control circuit 200) for controlling an effect operation
The game control unit
An arithmetic processing unit (for example, the main CPU 101) that executes various processes for controlling the game operation;
A first storage unit (for example, the main ROM 102) in which information necessary for the arithmetic processing unit to execute various processes is stored;
A second storage unit (for example, the main RAM 103) in which information is stored based on execution of various processes by the arithmetic processing unit;
A security unit (eg, microprocessor 91) having a security function;
A serial communication unit (for example, the first serial communication circuit 114) for performing serial communication;
The first storage unit is
A program area (for example, a program area) in which a program for the arithmetic processing unit to execute various processes is stored;
A data area (for example, a data area) in which data for the arithmetic processing unit to execute various processes is stored;
A management area (for example, a program management area and a security setting area) in which settings and management information of the arithmetic processing unit and the security unit are stored;
The security unit includes startup delay means for delaying startup of the arithmetic processing unit based on the input of a reset signal,
The game control unit
Communication data registration means (for example, communication data storage processing shown in FIG. 68) for registering communication data in the communication data storage area of the second storage unit;
Communication data transmission means (for example, communication data transmission processing shown in FIG. 115) capable of transmitting communication data registered in the communication data storage area via the serial communication unit to the effect control unit;
Transmission delay means (for example, a command transmission start timer) for delaying transmission of communication data by the communication data transmission means for a predetermined period;
Setting value setting means (for example, setting key type switch 54) capable of setting setting values (for example, settings 1 to 6) indicating the degree of advantage of the player regarding the game;
The activation delay unit delays activation of the arithmetic processing unit for a period corresponding to the setting stored in the management area.
The transmission delay means delays transmission of communication data by the communication data transmission means after the start delay of the arithmetic processing unit by the activation delay means is completed.
The set value setting means enables setting of the set value even when the transmission delay means delays transmission of communication data.
The communication data registration means may be arranged in the communication data storage area when setting of the setting value by the setting value setting means is started, even when transmission of communication data is delayed by the transmission delay means. The first communication data (for example, setting change command (setting change / setting confirmation start)) can be registered, and when setting of the setting value by the setting value setting unit is completed, the second communication data storage area Enables the registration of the communication data (for example, setting change command (setting change / setting confirmation end)) of
The communication data transmission unit is configured to register the first communication data and the second communication data in the communication data storage area when the transmission delay of the communication data by the transmission delay unit ends. Sends these communication data in the registered order,
A fixed period and a variable period can be set as a delay period of activation of the arithmetic processing unit by the activation delay means,
The fixed period can set one period out of a plurality of periods, and the variable period can set a range of one period out of a plurality of periods. Machine.

In the gaming machine of the third configuration, the variable period is at least at least a range of a first period in which 0 is always determined as the variable period, and the variable period is random within a range from 0 to a predetermined period. The range of the second period to be determined can be set,
A game machine characterized in that a range of the first period is set as the variable period.

  According to the gaming machine of the first to third configurations, the security unit can start the game control unit stably by delaying the activation of the operation processing unit, and the delay of the activation of the operation processing unit By delaying the transmission of the communication data after completion of the process, it is possible to secure the time required for activating the effect control unit and stably activate the effect control unit.

  Then, after the delay of the activation of the arithmetic processing unit is finished, the setting change can be made even before the delay of transmission of communication data is finished. For example, when opening a store in a game arcade, When the power of the gaming machine is turned on (that is, when the reset signal is input in connection with this), the setting can be changed in advance without waiting for the activation control unit to complete activation. Work efficiency can be improved.

  Furthermore, when the setting change is performed before the delay of transmission of communication data ends, communication data indicating these is registered at the start of the setting change or at the end of the setting change, and the delay of the communication data transmission is Since these communication data are transmitted in the order in which they were registered when the process ends, even if the setting change is made in advance without waiting for the start of the effect control unit to complete, Thus, it is possible to prevent the occurrence of wrinkles in information held between the game control unit and the effect control unit. In addition, for example, even in the case where the effect control unit is configured to determine the injustice or error according to the order of the communication data transmitted from the game control unit, the effect of such determination is affected. It is possible to make an accurate determination without exerting

  Further, according to the gaming machine of the second configuration, at least the predetermined communication data (third communication data) is transmitted even when the communication data is not registered when the transmission process of the communication data is performed. Is transmitted, for example, illegal access to the connection between the game control device and the effect control device, etc. to prevent communication data from being transmitted from the outside by unauthorized means, etc. It becomes possible. Further, since the registration and transmission of the predetermined communication data are not performed before the delay of the transmission of the communication data is completed, it is possible to reduce the control burden when the gaming machine is powered on. Note that from the viewpoint of mainly preventing fraudulent acts, the predetermined communication data may not include information related to the game operation of the player.

  Further, according to the gaming machine of the third configuration, the delay period of activation of the arithmetic processing unit is constituted by the fixed period and the variable period, and these periods (or the range thereof) can be appropriately selected and set. Thus, it is possible to set an appropriate delay time according to the specifications of the game control device and the effect control device. If it is possible to set the range of the predetermined period (the range of the first period) in which 0 is necessarily determined as the variable period, from the viewpoint of shortening the period until the setting change becomes possible, The range of the predetermined period may be set.

[The game machine of the 4th-6th composition]
In the conventional gaming machine, when the medals can be accepted and the inserted medals are appropriate medals, the inserted medals are counted by the medal sensor and stored inside the gaming machine, and If the inserted medal is not a proper medal even if it is not in a state where medals can be received or medals can be received, the inserted medals are not counted by the medal sensor, and are outside the gaming machine. There is known one provided with a medal sorting device (selector) for being discharged (see, for example, Japanese Patent Application Laid-Open No. 2006-130213).

  In the medal sorting device (selector) shown in JP 2006-130213 A, when the member (regulating guide plate) whose position is shifted by the drive of the solenoid (regulation guide plate) is in a state where it is possible to receive medals, the inserted medals Is guided in the first direction stored inside the gaming machine by passing the medal sensor, and if the medals can not be received, the inserted medal is not guided in the first direction, and the gaming machine is not It is guided in a second direction discharged to the outside.

  By the way, since the solenoid utilizes magnetic force, it takes some time for excitation and demagnetization. Therefore, depending on the insertion timing of the medal, for example, the inserted medal is counted by the medal sensor because the switching of the guiding direction of the medal is not completed although the medal acceptance is not possible. There is a case where the game is stored inside the gaming machine (that is, the medal "spit-in" occurs).

  If such a situation occurs, not only will the player be given a loss, but also the reliability of the game will be reduced. Therefore, it is desirable to provide a gaming machine capable of properly processing the inserted medals by preventing the generation of the medals such as "spit-in".

  The present invention has been made in view of these points, and it is an object of the present invention to provide a gaming machine capable of properly processing inserted gaming media.

  In order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the fourth configuration as described below.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, And state switching means (for example, medal acceptance / start check processing shown in FIGS. 75 and 76) for switching the control state from the receivable state to the unacceptable state when the game start detection unit detects the start operation. ,
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following fifth configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
Gaming medium counting means (for example, a credit counter) for counting gaming media when the detection unit detects gaming media;
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, A state switching means for switching the control state from the acceptable state to the unacceptable state when the predetermined number (for example, three) of gaming media is inserted and the gaming start detection unit detects the start operation For example, medal reception / start check processing shown in FIGS. 75 and 76),
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
The gaming medium counting means enables counting of gaming media even when the detection unit detects gaming media during the standby process.
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

  Further, in order to achieve the above object, according to the gaming machine of the present embodiment, it is possible to provide a gaming machine of the following sixth configuration.

A game control unit (for example, the main control circuit 90) for controlling a game operation, a game medium detection unit (for example, the selector 66) for detecting insertion of game media, and a game start detection unit (for example, , And a start switch 79), for example, a pachislot 1),
The gaming medium detection unit
A distribution unit (for example, select plate 804) capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game machine outside ,
A drive unit (for example, a solenoid) for electromagnetically driving the distribution unit;
A detection unit (for example, a medal sensor) for detecting inserted game media;
The game control unit
It is possible to switch the control state between a reception enable state (for example, medal reception permission) enabling reception of game media and a reception impossible state (for example, medal reception prohibition) for not enabling reception of game media, And state switching means (for example, medal acceptance / start check processing shown in FIGS. 75 and 76) for switching the control state from the receivable state to the unacceptable state when the game start detection unit detects the start operation. ,
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit and the distributing unit guide the game medium in the first direction (for example, the first driving state (for example, the first driving state) Drive control means (for example, the main CPU 101) for shifting from the excitation state) to the second drive state (for example, the demagnetization state) in which the distribution unit guides the game medium in the second direction;
Standby processing means (for example, a medal monitoring timer) that performs standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
Start operation invalidation processing means (for example, medal insertion shown in FIGS. 78 and 79) for invalidating the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process. Check 2 process) and,
The drive unit control means shifts the drive unit from the second drive state to the first drive state when the detection unit detects a game medium during the standby process.
In the predetermined period, the distributing unit guides the game medium in the first direction in response to the drive unit controlling means shifting from the first drive state to the second drive state by the drive unit control means. A game machine characterized by being set to a period equal to or longer than a period from the position until the distribution unit moves to the position for guiding the game medium in the second direction.

  In the gaming machine of the sixth configuration, the drive unit is a solenoid, the first drive state is a state in which the solenoid is excited, and the second drive state is a demagnetization of the solenoid. A gaming machine characterized by being in a state.

  According to the gaming machines of the fourth to sixth configurations, when the game is started along with the player's start operation, for example, the waiting period for preventing the occurrence of the medal "snipping" etc. It is set. By this waiting period, the game medium detection unit secures a time until the inserted medal is physically stored in the gaming machine from being physically discharged to the outside of the gaming machine.

  When the medal is inserted during the standby period, the original start operation is invalidated, and in the gaming medium detection unit, the inserted medal is stored inside the gaming machine. Return to Therefore, it is possible to appropriately process the inserted medals by preventing the occurrence of the "snipping" of the medals and the like.

  Further, according to the gaming machine of the fifth configuration, even when medals are inserted during the standby period, the medals are counted, thereby preventing the counting omission of the inserted medals. It is possible to process the inserted medals more appropriately.

  Further, according to the gaming machine of the sixth configuration, the standby period is equal to or longer than the period of physical transition of the inserted medal from being stored inside the gaming machine to being discharged outside the gaming machine. Since it is set to the period of (1), it becomes possible to prevent the occurrence of "spit-in" etc. of the medals reliably and to process the inserted medals more appropriately. In addition, when a drive part is a solenoid, such an effect becomes more remarkable.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information indicator, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72: secondary control board, 90: main control circuit, 91: microprocessor, 101: main CPU, 102: main ROM, 103: main RAM, 107: arithmetic circuit, 114: first serial communication circuit, 115: second serial Communication circuit, 200: secondary control circuit, 201: secondary CPU 201, 301: first interface board, 302: second interface board

Claims (1)

A gaming machine having a gaming control unit for controlling a gaming operation, a gaming medium detection unit for detecting insertion of gaming media, and a gaming start detection unit for detecting a game start operation,
The gaming medium detection unit
A distribution unit capable of distributing and guiding the inserted game media in a first direction for storing the game medium inside or in a second direction for discharging the game medium to the outside;
A drive unit for electromagnetically driving the distribution unit;
A detection unit for detecting inserted game media;
The game control unit
It is possible to switch the control state between a receivable state enabling reception of gaming media and a non-acceptable status not permitting reception of gaming media, and the gaming start detection unit detects a start operation. State switching means for switching the control state from the receivable state to the unacceptable state;
When the state switching unit switches the control state from the receivable state to the unacceptable state, the driving unit is guided by the distributing unit from the first driving state in which the game medium is guided in the first direction. Drive unit control means for shifting to the second drive state in which the distribution unit guides the game medium in the second direction;
Standby processing means for performing standby processing for a predetermined period when the state switching means switches the control state from the receivable state to the unacceptable state;
And a start operation invalidation processing unit that invalidates the start operation detected by the game start detection unit when the detection unit detects a game medium during the standby process.
When the detection unit detects a game medium during the standby process, the drive unit control means shifts the drive unit from the second drive state to the first drive state. Machine.

Images