JP2019057512A - Organic electroluminescent device and electronic equipment - Google Patents

Abstract

To provide a pixel structure for a high-density pixel, in which layers above a gate electrode are effectively utilized.SOLUTION: A power line layer is connected to one current end of a drive transistor Tdr; a capacitive element C is connected between a gate layer Gdr of the drive transistor Tdr and the power line layer; one current end of a selection transistor Tsl is connected to the gate layer Gdr of the drive transistor Tdr; a pixel electrode is connected to the other current end of the drive transistor Tdr; and a first control line is connected to a gate layer Gsl of the selection transistor Tsl. The capacitive element C includes a first electrode connected to the gate layer Gdr of the drive transistor Tdr and disposed in a layer above the gate layer Gdr, and a dielectric film between the first electrode and the power line layer. The power line layer is disposed above the first electrode; and the first control line is formed in the same layer as the power line layer.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an organic electroluminescence (hereinafter also referred to as organic EL) device using a light emitting material of an organic electroluminescence material.

  For example, a light-emitting device in which light-emitting elements using an organic EL material are arranged in a plane on a substrate has been conventionally proposed as a display device for various electronic devices. Patent Document 1 discloses a technique for forming a capacitor electrode constituting a capacitor element in a layer for forming a scanning line, a gate electrode, or the like.

JP 2007-226184 A

However, when the capacitor electrode is formed in the layer for forming the scan line, the gate electrode, etc. as in Patent Document 1, the capacitor electrode must be formed while avoiding the control line, such as the scan line, and the gate electrode, It was difficult to secure the capacity of the capacitive element.
In view of the above circumstances, an object of the present invention is to provide an organic electroluminescence device and an electronic apparatus that can secure the capacity of a capacitive element even in a high-density pixel.

  In order to solve the above problems, a first transistor according to a preferred aspect of the present invention, an organic electroluminescence element that emits light with a luminance corresponding to the magnitude of a current supplied through the first transistor, A capacitive element having a first electrode connected to the gate of the first transistor, a second electrode, and a dielectric film provided between the first electrode and the second electrode; One electrode is formed in the same layer as the second electrode, and is disposed at a position apart from the second electrode with the dielectric film interposed therebetween. In the above configuration, the first electrode and the second electrode are formed in the same layer, and are arranged at positions apart from each other in the planar direction, so that the capacitive element is formed in the planar direction. Accordingly, a capacitor element can be formed without securing a multilayer and a capacitance can be secured, so that an organic electroluminescence device free from variations in luminance is provided.

  In a preferred aspect of the present invention, the power supply line layer is connected to one current terminal of the first transistor, the first electrode is connected to the gate of the first transistor, and the second electrode is The first electrode is disposed so as to be surrounded by the second electrode in plan view, connected to a power supply line layer connected to the first transistor. In this configuration, since the first electrode is connected to the gate of the first transistor and the second electrode is connected to the power supply line layer connected to the first transistor, the capacitance formed by the first electrode and the second electrode. The element functions as a storage capacitor that holds the potential of one current end and the gate of the first transistor. In addition, since the first electrode of the capacitive element is disposed so as to be surrounded by the second electrode, capacitance is ensured not only in one direction on the plane but also in all directions. In addition, since the first electrode which is the gate potential portion of the first transistor is surrounded by the second electrode connected to the power supply line layer, the gate potential of the first transistor can be stabilized and the first transistor can be stabilized. Coupling between the gate potential portion and other members is suppressed.

  In a preferred aspect of the present invention, the capacitive element includes a third electrode, and the third electrode is connected to the power supply line layer and is disposed so as to be surrounded by the first electrode in plan view. . In this configuration, since the capacitive element is formed by the first electrode and the third electrode, it is possible to further secure the capacitance without increasing the number of layers.

  In a preferred aspect of the present invention, the power supply line layer is provided on an upper layer of the second electrode and the third electrode, and the second electrode is connected to the power supply line layer via a first conduction part. The third electrode is connected to the power supply line layer via a second conduction portion. In this configuration, the power supply line layer can be connected to the second electrode and the third electrode with lower resistance than the case where the power supply line layer is directly extended to the lower layer and the second electrode and the third electrode are connected. it can.

  In a preferred aspect of the present invention, the semiconductor device further includes an electrode connected to the gate of the first transistor, and the electrode is disposed below the third electrode, and is at least one of the third electrode in plan view. It is arrange | positioned in the position which overlaps with a part. In this configuration, since the capacitive element is formed between the third electrode and the electrode connected to the gate of the first transistor, the capacitance can be secured by effectively utilizing the upper layer of the gate.

  In a preferred aspect of the present invention, the semiconductor device further includes an electrode connected to the gate of the first transistor, the electrode being disposed below the second electrode, and at least one of the second electrodes in plan view. In this configuration, which is disposed at a position overlapping with the portion, a capacitive element is formed between the second electrode and the electrode connected to the gate of the first transistor. Can be secured.

  In a preferred aspect of the present invention, an active layer is formed under the electrode connected to the gate of the first transistor, and an impurity is implanted into the active layer. According to this configuration, since the capacitive element by the MOS capacitor is formed between the electrode connected to the gate of the first transistor and the active layer, it is possible to secure the capacitance while enabling high density of pixels. it can.

  In a preferred aspect of the present invention, the power line layer is formed in an upper layer of the first electrode, and is disposed at a position overlapping the first electrode in plan view. In this configuration, since the first electrode is shielded by the power supply line layer, the coupling between the first electrode and the signal line formed above the power supply line layer is suppressed.

  In a preferred aspect of the present invention, the capacitive element and the first transistor are arranged so as to overlap in a plan view. Therefore, the capacitance of the capacitive element is ensured in the first direction, and the density of the pixels can be increased.

In order to solve the above problems, an organic electroluminescence device according to a preferred aspect of the present invention includes a scanning line, a signal line, and a pixel circuit connected to the scanning line and the signal line, The pixel circuit includes a first transistor having one current end connected to the power line layer,
An organic electroluminescence element having a pixel electrode and emitting light with a luminance corresponding to a magnitude of a current supplied through the first transistor; a first electrode connected to a gate of the first transistor; A capacitive element having an electrode and a dielectric film provided between the first electrode and the second electrode, wherein the first electrode is formed in the same layer as the second electrode, and the dielectric The body membrane is disposed at a position away from the second electrode. Accordingly, a capacitor element can be formed without securing a multilayer and a capacitance can be secured, so that an organic electroluminescence device free from variations in luminance is provided.

  In a preferred aspect of the present invention, a power line layer is disposed between the first electrode and the signal line. Therefore, the coupling between the signal line and the capacitor electrode is suppressed by the shielding effect of the power supply line layer.

  In a preferred aspect of the present invention, a power supply line layer is disposed between the first electrode, the scanning line, and the signal line. Therefore, the coupling between the scanning line and the signal line and the capacitor electrode is suppressed by the shielding effect of the power supply line layer.

  In a preferred aspect of the present invention, a power supply line layer is disposed between the first electrode and the pixel electrode. Therefore, the coupling between the pixel electrode and the capacitor electrode is suppressed by the shielding effect of the power supply line layer.

  In a preferred aspect of the present invention, a plurality of conduction holes penetrating each layer from the layer forming the current end of the first transistor to the layer on which the pixel electrode is formed, and connected to each of the plurality of conduction holes The other current end of the first transistor and the pixel electrode are connected by the plurality of conduction holes and the plurality of relay electrodes. Therefore, it is possible to achieve conduction between the first transistor and the pixel electrode with a lower resistance than when the pixel electrode is extended to the layer where the other current end of the first transistor is formed to achieve conduction.

  In a preferred aspect of the present invention, the capacitive element and the first transistor are arranged so as to overlap in a plan view in the first direction. Therefore, the capacitance of the capacitive element is ensured in the first direction, and the density of the pixels can be increased.

  In a preferred aspect of the present invention, the semiconductor device further includes a second transistor having one current terminal connected to the gate of the first transistor and the other current terminal connected to the signal line, the signal line and the second transistor Are arranged so as to overlap in plan view in the first direction. Therefore, it is possible to increase the density of the pixels, reduce the conduction distance between the signal line and the second transistor, and achieve conduction with a low resistance. As a result, the writing capability of the signal line to the second transistor is improved.

  In a preferred aspect of the present invention, a second transistor having one current terminal connected to the gate of the first transistor and the other current terminal connected to the signal line, and the other current of the first transistor. A third transistor having one end connected to one end and the other end connected to the other end of the second transistor; and the signal line and the third transistor Are arranged so as to overlap in a plan view in the first direction. Accordingly, it is possible to increase the density of the pixels, reduce the conduction distance between the signal line and the third transistor, and achieve conduction with a low resistance. As a result, the writing ability to the third transistor by the signal line is improved.

  In a preferred aspect of the present invention, the signal line includes: a fourth transistor in which one current terminal is connected to the other current terminal of the first transistor and the other current terminal is connected to the pixel electrode. And the fourth transistor are arranged so as to overlap in plan view in the first direction. Therefore, the pixel density can be increased.

  The organic electroluminescence device according to each of the above aspects is used for various electronic devices as a display device, for example. Specifically, a head-mounted display device, an electronic viewfinder of an imaging device, and the like can be exemplified as preferred examples of the electronic apparatus of the present invention, but the scope of application of the present invention is not limited to the above examples.

It is a top view of the light-emitting device of 1st Embodiment of this invention. It is a circuit diagram of a pixel. It is sectional drawing of a light-emitting device. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on the board | substrate in the modification of 1st Embodiment. It is explanatory drawing of each element formed on the board | substrate in the modification of 1st Embodiment. It is explanatory drawing of each element formed on the board | substrate in the modification of 1st Embodiment. It is a circuit diagram of the pixel used for the light-emitting device in 2nd Embodiment of this invention. It is a circuit diagram of a pixel for explaining driving by a current programming method. It is sectional drawing of a light-emitting device. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of the light-emitting device in 3rd Embodiment of this invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of the light-emitting device in 3rd Embodiment of this invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of the light-emitting device in 4th Embodiment of this invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is a schematic diagram of a head-mounted display device as an example of an electronic device.

<First Embodiment>
FIG. 1 is a plan view of an organic electroluminescence device 100 according to the first embodiment of the present invention. The organic electroluminescence device 100 of the first embodiment is an organic EL device in which a light emitting element using an organic EL material is formed on the surface of the substrate 10. The substrate 10 is a plate-like member (semiconductor substrate) formed of a semiconductor material such as silicon (silicon), and is used as a base (base) on which a plurality of light emitting elements are formed. As illustrated in FIG. 1, the surface of the substrate 10 is divided into a first region 12 and a second region 14. The first area 12 is a rectangular area, and the second area 14 is a rectangular frame area surrounding the first area 12.

  A plurality of scanning lines 22 extending in the X direction and a plurality of signal lines 26 extending in the Y direction intersecting the X direction are formed in the first region 12. A pixel P (Pd, Pe) is formed corresponding to each intersection of the plurality of scanning lines 22 and the plurality of signal lines 26. Accordingly, the plurality of pixels P are arranged in a matrix over the X direction and the Y direction.

  In the second region 14, a drive circuit 30, a plurality of mounting terminals 36, and a guard ring 38 are installed. The drive circuit 30 is a circuit that drives each pixel P, and extends in the X direction among the two scanning line drive circuits 32 installed at each position sandwiching the first region 12 in the X direction and the second region 14. And a signal line driving circuit 34 installed in the existing area. The plurality of mounting terminals 36 are formed in a region opposite to the first region 12 with the signal line driving circuit 34 interposed therebetween, and are controlled via a flexible wiring substrate (not shown) joined to the substrate 10. It is electrically connected to an external circuit (for example, an electronic circuit mounted on a wiring board) such as a circuit or a power supply circuit.

  In the organic electroluminescence device 100 according to the first embodiment, a plurality of the organic electroluminescence devices 100 are collectively formed by cutting (scribing) an original substrate having a size corresponding to the plurality of substrates 10. The guard ring 38 in FIG. 1 prevents the influence of the impact and static electricity at the time of cutting the original substrate from spreading on the drive circuit 30 or each pixel P and the intrusion of moisture from the end face (cut surface of the original substrate) of each substrate 10. To prevent. As illustrated in FIG. 1, the guard ring 38 is formed in an annular shape (rectangular frame shape) surrounding the drive circuit 30, the plurality of mounting terminals 36, and the first region 12.

  The first region 12 in FIG. 1 is divided into a display region 16 and a peripheral region 18. The display area 16 is an area where an image is actually displayed by driving each pixel P. The peripheral region 18 is a rectangular frame-like region surrounding the display region 16, and the pixel P (hereinafter referred to as “dummy pixel Pd”) that is similar in structure to each pixel P in the display region 16 but does not actually contribute to image display. ") Is arranged. From the viewpoint of clarifying the distinction in notation with the dummy pixel Pd in the peripheral region 18, in the following description, the pixel P in the display region 16 may be referred to as “display pixel Pe” for convenience. The display pixel Pe is an element that is a minimum unit of light emission.

  FIG. 2 is a circuit diagram of each display pixel Pe located in the display area 16. As illustrated in FIG. 2, the display pixel Pe includes a light emitting element 45, a driving transistor Tdr, a selection transistor Tsl, and a capacitive element C. In the first embodiment, each transistor T (Tdr, Tsl) of the display pixel Pe is a P-channel type, but an N-channel transistor can also be used.

  The light emitting element 45 is an electro-optical element in which a light emitting functional layer 46 including a light emitting layer of an organic EL material is interposed between a first electrode (anode) E1 and a second electrode (cathode) E2. The first electrode E1 is individually formed for each display pixel Pe, and the second electrode E2 is continuous over a plurality of pixels P. As understood from FIG. 2, the light emitting element 45 is disposed on a path connecting the first power supply conductor 41 and the second power supply conductor 42. The first power supply conductor 41 is a power supply wiring to which a higher power supply potential Vel is supplied, and the second power supply conductor 42 is a power supply wiring to which a lower power supply potential (for example, ground potential) Vct is supplied. .

  The driving transistor Tdr is disposed in series with the light emitting element 45 on a path connecting the first power supply conductor 41 and the second power supply conductor 42. Specifically, one (source or drain) of the pair of current ends of the driving transistor Tdr is connected to the first power supply conductor 41. The drive transistor Tdr generates a drive current having a current amount corresponding to the voltage between its gate and source or between its gate and drain.

  The selection transistor Tsl in FIG. 2 functions as a switch that controls the conduction state (conduction / non-conduction) between the signal line 26 and the gate of the drive transistor Tdr. The gate of the selection transistor Tsl is connected to the scanning line 22. The capacitive element C is a capacitance in which a dielectric is interposed between the first electrode C1 and the second electrode C2. The first electrode C1 is connected to the gate of the driving transistor Tdr, and the second electrode C2 is connected to the first power supply conductor 41 (the source of the driving transistor Tdr). Accordingly, the capacitive element C holds a voltage between the gate and the source or between the gate and the drain of the driving transistor Tdr.

  The signal line driving circuit 34 supplies a plurality of signal lines for each writing period (horizontal scanning period) with a gradation potential (data signal) corresponding to the gradation specified by the image signal supplied from the external circuit for each display pixel Pe. 26 in parallel. On the other hand, each scanning line drive circuit 32 supplies a scanning signal to each scanning line 22 to sequentially select each of the plurality of scanning lines 22 for each writing period. The selection transistor Tsl of each display pixel Pe corresponding to the scanning line 22 selected by the scanning line driving circuit 32 is turned on. Therefore, the gradation potential is supplied to the gate of the driving transistor Tdr of each display pixel Pe via the signal line 26 and the selection transistor Tsl, and the voltage corresponding to the gradation potential is held in the capacitor C. Accordingly, a driving current corresponding to the gradation potential is supplied from the driving transistor Tdr to the light emitting element 45. As described above, each light emitting element 45 emits light at a luminance corresponding to the gradation potential, whereby an arbitrary image designated by the image signal is displayed in the display area 16. In addition, even after the writing period ends, a driving current corresponding to the voltage held in the capacitor C is supplied from the driving transistor Tdr to the light emitting element 45, so that each light emitting element 45 corresponds to the gradation potential. Maintains light emission at brightness.

  A specific structure of the organic electroluminescence device 100 of the first embodiment will be described in detail below. In the drawings referred to in the following description, the dimensions and scales of the elements are different from those of the actual organic electroluminescence device 100 for convenience of description. FIG. 3 is a cross-sectional view of the organic electroluminescence device 100, and FIGS. 4 to 11 show the state of the surface of the substrate 10 at each stage of forming each element of the organic electroluminescence device 100 as one display pixel Pe. It is the top view illustrated paying attention to minute. 12 to 14 are plan views illustrating the surface of the substrate 10 by paying attention to four display pixels Pe. A cross-sectional view corresponding to the cross section including the line I-I ′ in FIGS. 4 to 11 corresponds to FIG. 3. 4 to 14 are plan views, but from the viewpoint of facilitating visual grasp of each element, hatching in the same manner as FIG. 3 is added for convenience to each element common to FIG. Yes.

  As understood from FIGS. 3 and 4, the active region 10A (source / drain region) of each transistor T (Tdr, Tsl) of the display pixel Pe is formed on the surface of the substrate 10 formed of a semiconductor material such as silicon. It is formed. Ions are implanted into the active region 10A. An active layer of each transistor T (Tdr, Tsl) of the display pixel Pe exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted. It is described in one piece. In the present embodiment, an active region 10A is also formed in a region constituting the capacitive element C, and impurities are implanted into the active region 10A and connected to a power source. Then, a so-called MOS capacitor is formed in which the active region 10A is used as one electrode and the capacitor electrode formed via the insulating layer is used as the other electrode. Further, the active region 10A in the region constituting the capacitive element C also functions as a power supply potential portion. Details of the MOS capacitor and the power supply potential section will be described later. As understood from FIGS. 3 and 5, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate layer G (Gdr, Gsl) of each transistor T is an insulating film. It is formed on the surface of L0. The gate layer G of each transistor T faces the active layer with the insulating film L0 interposed therebetween. Further, as illustrated in FIG. 5, the gate layer Gdr of the drive transistor Tdr is formed to extend to the active region 10A formed in the region constituting the capacitive element C, and constitutes the lower capacitive electrode layer CA1.

  As understood from FIG. 3, on the surface of the insulating film L0 on which the gate layer G and the lower capacitor electrode layer CA1 of each transistor T are formed, a plurality of insulating layers L (LA to LD) and a plurality of conductive layers ( A multilayer wiring layer is formed by alternately stacking wiring layers). Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate G of each transistor T is formed. As understood from FIGS. 3 and 6, the upper capacitor electrode layers CA2, CA3, CA4 and a plurality of relay electrodes QB (QB1, QB2, QB3) are formed from the same layer on the surface of the insulating layer LA. The As understood from FIGS. 3 and 6, the upper capacitor electrode layer CA2 is an active region 10A that forms a source region or a drain region of the driving transistor Tdr through a conduction hole HA5 that penetrates the insulating layer LA and the insulating film L0. Conducted to. In the upper capacitor electrode layer CA2, an opening 50 is formed so as to surround a region where a part of the gate layer Gdr of the drive transistor Tdr and the lower capacitor electrode layer CA1 are formed in a plan view. In addition, the upper capacitor electrode layer CA2 has a drain region or a source region of the driving transistor Tdr that constitutes the pixel conduction portion and a part of the gate layer Gsl and a part of the drain region or the source region of the selection transistor Tsl in plan view. An opening 51 is formed so as to surround.

  In the opening 50, an upper capacitive electrode layer CA3 and an upper capacitive electrode layer CA4 are formed in the same layer as the upper capacitive electrode layer CA2. An opening 52 is formed in the upper capacitor electrode layer CA3, and the upper capacitor electrode layer CA4 is formed in the opening 52. That is, the upper capacitor electrode layer CA2, the upper capacitor electrode layer CA3, and the upper capacitor electrode layer CA4 are formed apart from each other and electrically insulated. That is, the upper capacitive electrode layer CA3 is surrounded by the upper capacitive electrode layer CA2. The upper capacitive electrode layer CA4 is surrounded by the upper capacitive electrode layer CA3. The upper capacitor electrode layer CA3 also functions as a wiring layer that connects the gate layer Gdr of the driving transistor Tdr and the active region 10A that forms the drain region or the source region of the selection transistor Tsl. That is, as understood from FIGS. 3, 5, and 6, the upper capacitor electrode layer CA3 is electrically connected to the active region 10A of the selection transistor Tsl through the conduction hole HA2 that penetrates the insulating layer LA and the insulating film L0. At the same time, it is conducted to the gate Gdr of the drive transistor Tdr through the conduction hole HB2 of the insulating layer LA.

  In the opening 51, the relay electrode QB1, the relay electrode QB2, and the relay electrode QB3 are formed in the same layer as the upper capacitor electrode layer CA2. That is, the relay electrode QB1, the relay electrode QB2, and the relay electrode QB3 are surrounded by the upper capacitor electrode layer CA2. As understood from FIGS. 3, 5, and 6, the relay electrode QB <b> 1 is electrically connected to the active region 10 </ b> A that forms the drain region of the drive transistor Tdr through the conduction hole HA <b> 6 that penetrates the insulating layer LA and the insulating film L <b> 0. To do. The relay electrode QB2 is electrically connected to the gate layer Gsl of the selection transistor Tsl through a conduction hole HB1 that penetrates the insulating layer LA. The relay electrode QB3 is electrically connected to the active region 10A that forms the source region of the drive transistor Tdr through the conduction hole HA1 that penetrates the insulating layer LA and the insulating film L0. As is understood from FIG. 6, each of the selection transistor Tsl and the driving transistor Tdr is formed so that the channel length is along the Y direction. The region constituting the capacitive element C is disposed at a position shifted in the X direction (the positive side in the X direction in FIG. 6) with respect to the drive transistor Tdr. Further, the conduction point between the gate layer Gsl of the selection transistor Tsl and the relay electrode QB2 is arranged at a position shifted in the X direction (the negative side in the X direction in FIG. 6) with respect to the selection transistor Tsl.

  The insulating layer LB is formed on the surface of the insulating layer LA on which the upper capacitive electrode layer CA2, the upper capacitive electrode layer CA3, the upper capacitive electrode layer CA4, and the plurality of relay electrodes QB (QB1, QB2, QB3) are formed. . As understood from FIGS. 3 and 7, on the surface of the insulating layer LB, the power supply line layer 41 as the first power supply conductor, the scanning line 22, and a plurality of relay electrodes QC (QC1, QC2) are provided. It is formed from the same layer. The power supply line layer 41 is electrically connected to the mounting terminal 36 to which the higher power supply potential Vel is supplied via wiring (not shown) in the multilayer wiring layer. The power supply line layer 41 is formed in the display area 16 of the first area 12 shown in FIG. Although not shown, another power line layer is also formed in the peripheral region 18 of the first region 12. This power supply line layer is electrically connected to the mounting terminal 36 to which the lower power supply potential Vct is supplied via wiring (not shown) in the multilayer wiring layer. The power supply line layer 41 and the power supply line layer to which the lower power supply potential Vct is supplied are formed of a conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm.

  As described above, the power supply line layer 41 is a power supply line to which the higher power supply potential Vel is supplied. As understood from FIG. 13, the opening 50 of the upper capacitive electrode layer CA2 and the upper capacitive electrode layer CA2 around it. Is a strip-like pattern that covers each pixel and is continuously continuous with no gap between adjacent pixels in the X direction.

  As understood from FIGS. 3 and 7, the power supply line layer 41 formed in the display region 16 is electrically connected to the upper capacitor electrode layer CA2 through the conduction hole HC3 formed in the insulating layer LB for each display pixel Pe. To do. The power supply line layer 41 is electrically connected to the upper capacitor electrode layer CA2 through the conduction holes HC5, HC6, and HC7 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 3, 5 to 7, the power supply line layer 41 includes the conduction holes HC5 and HC6 penetrating the insulating layer LB, the upper capacitor electrode layer CA2, the insulating film L0 and the insulating layer LA. Conduction is conducted to the active region 10A formed in the region constituting the capacitive element C through the through holes HA3 and HA4 penetrating therethrough. Furthermore, as understood from FIGS. 3 and 7, the power supply line layer 41 is electrically connected to the upper capacitor electrode layer CA2 through the conduction hole HC7 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 3, 5 to 7, the power supply line layer 41 penetrates the conduction hole HC7 that penetrates the insulating layer LB, the upper capacitor electrode layer CA2, the insulating film L0, and the insulating layer LA. Through the conduction hole HA5, conduction is made to the active region 10A that forms the source region or drain region of the drive transistor Tdr. That is, the upper capacitor electrode layer CA2 also functions as a wiring layer that connects the source region or the drain region of the drive transistor Tdr and the power supply line layer 41. As understood from FIG. 12, the upper capacitor electrode layer CA2 that also functions as a wiring layer for the source region or the drain region of the drive transistor Tdr covers the periphery of the opening 50 and the opening 51 in one pixel, and X This is a pattern that is continuous without a gap between adjacent pixels in the direction and the Y direction. The power supply line layer 41 is electrically insulated from the upper capacitor electrode layer CA3 by the insulating layer LB. Further, as understood from FIGS. 3 and 7, the power supply line layer 41 is electrically connected to the upper capacitor electrode layer CA4 through the conduction holes HC4 and HC8 formed in the insulating layer LB for each display pixel Pe.

  As understood from FIG. 7, the scanning line 22 is electrically connected to the relay electrode QB2 through the conduction hole HC2 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 5 to 7, the scanning line 22 is connected to the selection transistor Tsl via the conduction hole HC2 penetrating the insulating layer LB, the relay electrode QB2, and the conduction hole HB1 penetrating the insulating layer LA. Conductive to the gate layer Gsl. As understood from FIG. 13, the scanning line 22 extends linearly in the X direction over the plurality of display pixels Pe, and is electrically insulated from the upper capacitor electrode layer CA2 and the relay electrode QB1 by the insulating layer LB. .

  As understood from FIG. 7, the relay electrode QC1 is electrically connected to the relay electrode QB3 through the conduction hole HC1 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 5 to 7, the relay electrode QC1 is connected to the relay hole HC1 penetrating the insulating layer LB, the relay electrode QB3, and the conductive hole HA1 penetrating the insulating film L0 and the insulating layer LA. Conduction to the active region 10A of the selection transistor Tsl.

  As understood from FIG. 7, the relay electrode QC2 is electrically connected to the relay electrode QB1 through the conduction hole HC9 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 5 to 7, the relay electrode QC2 is connected via the conduction hole HC9 that penetrates the insulating layer LB, the relay electrode QB1, and the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA. It is electrically connected to the active region 10A that forms the drain region or source region of the driving transistor Tdr.

  The insulating layer LC is formed on the surface of the insulating layer LB on which the power line layer 41, the scanning line 22, and the relay electrodes QC1 and QC2 are formed. As understood from FIGS. 3 and 8, the signal line 26 and the relay electrode QD1 are formed from the same layer on the surface of the insulating layer LC. The signal line 26 extends linearly in the Y direction over the plurality of pixels P, and is electrically insulated from the scanning line 22 and the power supply line layer 41 by the insulating layer LC. Specifically, as understood from FIGS. 7 and 8, the signal line 26 is electrically connected to the relay electrode QC1 through the conduction hole HD1 formed in the insulating layer LC for each display pixel Pe. Therefore, as understood from FIGS. 5 to 8, the signal line 26 is electrically connected to the conduction hole HD1, which penetrates the insulating layer LC, the relay electrode QC1, the relay electrode QB3, and the insulating film L0 and the insulating layer LA. It is electrically connected to the active region 10A of the selection transistor Tsl through the hole HA1. The signal line 26 is formed so as to pass through the position of the relay electrode QC1, the scanning line 22, and the upper layer of the power supply line layer 41, and extends along the channel length direction (Y direction) of the selection transistor Tsl. To do. The signal line 26 overlaps the selection transistor Tsl via the scanning line 22 and the power supply line layer 41 in plan view. Further, as understood from FIG. 14, the signal line 26 extends linearly in the Y direction over the plurality of display pixels Pe, and is electrically insulated from the scanning line 22 and the power supply line layer 41 by the insulating layer LC. The

  As understood from FIG. 7, the relay electrode QC2 is electrically connected to the relay electrode QB1 through the conduction hole HC9 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 5 to 7, the relay electrode QC2 is connected via the conduction hole HC9 that penetrates the insulating layer LB, the relay electrode QB1, and the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA. It is electrically connected to the active region 10A that forms the drain region or source region of the driving transistor Tdr.

  As illustrated in FIG. 3, the insulating layer LD is formed on the surface of the insulating layer LC on which the signal line 26 and the relay electrode QD1 are formed. In the above description, the display pixel Pe is focused. However, the structure of each element from the surface of the substrate 10 to the insulating layer LD is common to the dummy pixel Pd in the peripheral region 18.

  A planarization process is performed on the surface of the insulating layer LD. For the planarization treatment, a known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily employed. As illustrated in FIGS. 3 and 9, the reflective layer 55 is a light-reflective conductive material containing, for example, silver or aluminum on the surface of the insulating layer LD that is highly planarized by the planarization process. The film thickness is formed. The reflection layer 55 is formed of a light-reflective conductive material, and is disposed so as to cover each transistor T, each wiring, and each relay electrode as shown in FIG. Accordingly, there is an advantage that intrusion of external light is prevented by the reflective layer 55, and current leakage of each transistor T due to light irradiation can be prevented.

  As understood from FIGS. 3 and 9, the reflective layer 55 is electrically connected to the relay electrode QD1 through the conductive hole HE1 formed in the insulating layer LD for each display pixel Pe. Therefore, as understood from FIGS. 5 to 9, the reflective layer 55 includes the conduction hole HE1 that penetrates the insulating layer LD, the relay electrode QD1, the conduction hole HD2 that penetrates the insulating layer LC, and the relay electrode QC2. The conductive hole HC9 that penetrates the insulating layer LB, the relay electrode QB1, and the conductive hole HA6 that penetrates the insulating film L0 and the insulating layer LA are electrically connected to the active region 10A that forms the drain region or the source region of the driving transistor Tdr. .

  As illustrated in FIG. 3, the optical path adjustment layer 60 is formed on the surface of the insulating layer LD on which the reflective layer 55 is formed. The optical path adjustment layer 60 is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each display pixel Pe. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different.

  As illustrated in FIGS. 3 and 10, the first electrode E <b> 1 for each display pixel Pe in the display region 16 is formed on the surface of the optical path adjustment layer 60. The first electrode E1 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above with reference to FIG. 2, the first electrode E <b> 1 is a substantially rectangular electrode (pixel electrode) that functions as an anode of the light emitting element 45. The first electrode E1 is electrically connected to the reflective layer 55 via a conduction hole HF1 formed in the optical path adjustment layer 60 for each display pixel Pe. Therefore, as understood from FIGS. 5 to 10, the first electrode E1 includes the conduction hole HF1 that penetrates the optical path adjustment layer 60, the reflection layer 55, the conduction hole HE1 that penetrates the insulating layer LD, and the relay electrode QD1. Through the conduction hole HD2 that penetrates the insulating layer LC, the relay electrode QC2, the conduction hole HC9 that penetrates the insulating layer LB, the relay electrode QB1, and the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA. It is electrically connected to the active region 10A that forms the drain region or source region of the driving transistor Tdr.

  On the surface of the optical path adjustment layer 60 on which the first electrode E1 is formed, the pixel definition layer 65 is formed over the entire area of the substrate 10 as illustrated in FIGS. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from FIG. 11, the pixel definition layer 65 is formed with openings 65 </ b> A corresponding to the first electrodes E <b> 1 in the display region 16. A region in the pixel definition layer 65 near the inner periphery of the opening 65A overlaps the periphery of the first electrode E1. That is, the inner peripheral edge of the opening 65A is located inside the peripheral edge of the first electrode E1 in plan view. Each opening 65A has a common planar shape (rectangular shape) and size, and is arranged in a matrix at a common pitch in each of the X direction and the Y direction. As understood from the above description, the pixel definition layer 65 is formed in a lattice shape in plan view. The planar shape and size of the opening 65A are the same as long as the display color is the same, and may be different when the display color is different. Also, the pitch of the openings 65A may be the same between openings having the same display color, and may be different between openings having different display colors.

  In addition, although detailed description is omitted, the light emitting functional layer 46, the second electrode E2, and the sealing body 47 are laminated on the upper layer of the first electrode E1, and the substrate 10 on which the above elements are formed. A sealing substrate (not shown) is bonded to the surface of the substrate with, for example, an adhesive. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. It is also possible to form a color filter for each display pixel Pe on the surface of the sealing substrate or the surface of the sealing body 47.

  As described above, in the first embodiment, the capacitive element and at least a part of the drive transistor Tdr are arranged so as to be aligned in the stacking direction of the layers (the Z direction shown in FIG. 3) which is the third direction. In addition, the power supply portion (power supply potential portion), at least a part of the capacitive element, and the selection transistor Tsl are in the first direction (the X direction shown in FIG. 6) and the plane direction of each layer in the second direction. They are arranged so as to be lined up (in the Y direction shown in FIG. 6). As understood from FIGS. 3, 6 and 7, the upper capacitor electrode layer CA2 is electrically connected to the power line layer 41 as the first power conductor, and the second electrode C2 of the capacitor C shown in FIG. Function as. A gate layer Gdr which is at least a part of the drive transistor Tdr as the first transistor is disposed below the upper capacitor electrode layer CA2 in the stacking direction via the insulating layer LA. Therefore, when the gate layer Gdr itself is considered as the first electrode C1 of the capacitive element C connected to the gate of the driving transistor Tdr shown in FIG. 2, the upper capacitive electrode layer CA2, the insulating layer LA, and the gate layer Gdr are composed of the capacitive element C. The capacitor element C and the gate layer Gdr that is at least a part of the drive transistor Tdr are arranged so as to be aligned in the stacking direction.

  The upper capacitor electrode layer CA3 is electrically connected to the gate layer Gdr that is at least a part of the drive transistor Tdr. Therefore, the upper capacitive electrode layer CA3 functions as the first electrode C1 of the capacitive element C. In the stacking direction, a power supply line layer 41 as a first power supply conductor is disposed above the upper capacitor electrode layer CA3 via an insulating layer LB. Therefore, when the power supply line layer 41 is considered as the second electrode C2 of the capacitor C, the upper capacitor electrode layer CA3, the insulating layer LB, and the power supply line layer 41 constitute the capacitor C. The gate layer Gdr that is at least a part of the drive transistor Tdr is arranged so as to be aligned in the stacking direction.

  The upper capacitor electrode layer CA4 is electrically connected to the power supply line layer 41 as the first power supply conductor. Therefore, the upper capacitive electrode layer CA4 functions as the second electrode C2 of the capacitive element C. In the stacking direction, the lower capacitor electrode layer CA1 is disposed below the upper capacitor electrode layer CA4 via the insulating layer LA. The lower capacitor electrode layer CA1 is an electrode formed integrally with the gate layer Gdr that is at least part of the drive transistor Tdr, and the lower capacitor electrode layer CA1 is electrically connected to the gate layer Gdr that is at least part of the drive transistor Tdr. Functions as the first electrode C1 of the capacitive element C to be operated. Therefore, the upper capacitive electrode layer CA4, the insulating layer LA, and the lower capacitive electrode layer CA1 constitute a capacitive element C, and the capacitive element C and the gate layer Gdr that is at least a part of the driving transistor Tdr include They are arranged in the stacking direction. Further, an active region 10A into which impurities are implanted is disposed below the lower capacitor electrode layer CA1 through the insulating film L0. Since the active region 10A is electrically connected to the power supply line layer 41, it functions as the second electrode C2, and the active region 10A, the insulating film L0, and the lower capacitor electrode layer CA1 constitute a so-called MOS capacitor in the stacking direction. .

  As described above, in the first embodiment, the capacitive element and at least a part of the drive transistor Tdr are arranged so as to be aligned in the stacking direction of the layers (the Z direction shown in FIG. 3) which is the first direction. .

  Next, regarding the Y direction which is the channel length direction of the selection transistor Tsl, as understood from FIGS. 3, 6 and 7, the upper capacitor electrode layer CA2 is electrically connected to the insulating film L0 and the insulating layer LA. The power supply line layer 41 is electrically connected through the holes HA3 and HA4 and the conductive holes HC5 and HA6 penetrating the insulating layer LB. Therefore, the upper capacitor electrode layer CA2 functions as a power supply site (power supply potential portion) and also functions as the second electrode C2 of the capacitor C. The upper capacitor electrode layer CA3 is disposed at a position that is formed in the same layer as the upper capacitor electrode layer CA2 and is separated from the insulating layer LB in the Y direction. The upper capacitive electrode layer CA3 is electrically connected to the gate layer Gdr of the driving transistor Tdr and functions as the first electrode C1 of the capacitive element C. Therefore, the upper capacitive electrode layer CA2, the insulating layer LB, and the upper capacitive electrode layer CA3 constitute the capacitive element C also in the Y direction. Similarly, with respect to the upper capacitor electrode layer CA3 functioning as the first electrode C1, the upper capacitor electrode layer CA4 arranged away from the Y direction via the insulating layer LB is electrically connected to the power supply line layer 41, and the second electrode Functions as C2. Therefore, the upper capacitive electrode layer CA3, the insulating layer LB, and the upper capacitive electrode layer CA4 constitute the capacitive element C also in the Y direction.

  Thus, from the position of the conductive holes HA3, HA4 that penetrate the insulating film L0 and the insulating layer LA where the upper capacitor electrode layer CA2 is electrically connected to the power supply line layer 41, and the conductive holes HC5, HA6 that penetrate the insulating layer LB, In the Y direction up to the position where the selection transistor Tsl is arranged, a capacitive element C constituted by the upper capacitive electrode layer CA2 and the upper capacitive electrode layer CA3, and a capacitance constituted by the upper capacitive electrode layer CA3 and the upper capacitive electrode layer CA4. The element C, the capacitive element C constituted by the upper capacitive electrode layer CA4 and the upper capacitive electrode layer CA3, the capacitive element C constituted by the upper capacitive electrode layer CA3 and the upper capacitive electrode layer CA2, and the selection transistor Tsl are arranged. become. Therefore, considering that the upper capacitor electrode layer CA2 and the upper capacitor electrode layer CA4 also function as power supply portions (power supply potential portions), in the present embodiment, the power supply portions (power supply potential portions) and the capacitor elements At least a portion and the selection transistor Tsl are arranged so as to be arranged in the plane direction of each layer (Y direction shown in FIG. 6) which is the second direction.

As understood from FIGS. 3, 6, and 7, the upper capacitor electrode layer CA2, the upper capacitor electrode layer CA3, and the upper capacitor electrode layer CA4 are not only in the Y direction but also in the X direction, and further, oblique in the XY plane Similarly, the capacitive element C is formed through the insulating layer LB in the direction of. This is because the upper capacitive electrode layer CA3 that is electrically connected to the gate layer Gdr of the driving transistor Tdr and functions as the first electrode C1, and the upper capacitive electrode layer CA2 that is electrically connected to the power supply line layer 41 and functions as the second electrode C2 are the same. This is because the upper capacitor electrode layer CA3 is disposed so as to be surrounded by the upper capacitor electrode layer CA2 in a plan view. Further, when the upper capacitor electrode layer CA4 that is electrically connected to the power supply line layer 41 is considered as the third electrode, the upper capacitor electrode layer CA4 that is the third electrode is disposed so as to be surrounded by the upper capacitor electrode layer CA3 that is the first electrode. Therefore, the upper capacitor electrode layer CA2, the upper capacitor electrode layer CA3, and the upper capacitor electrode layer CA4 are disposed not only in the Y direction but also in the X direction and further in the oblique direction on the XY plane via the insulating layer LB. A capacitive element C is formed.
As described above, in the present embodiment, at least a part of the drive transistor Tdr and the capacitive element C formed between the active region 10A and the lower capacitive electrode layer CA1 are arranged in the first direction (X direction). The power supply site where the conduction holes HA5, HA4, HA3, etc. are arranged, at least a part of the capacitive element C formed between the active region 10A and the lower capacitive electrode layer CA1, and the selection transistor Tsl Are arranged in the direction (in the Y direction). By adopting such an arrangement configuration, the driving transistor Tdr and the capacitor C can be arranged near the power supply site, and the scanning line and the like can be kept away. Therefore, the gate potential portion of the driving transistor Tdr can be stabilized without being affected by the scanning line or the like.
The capacity element C of this embodiment is summarized as follows. In the present embodiment, the capacitive element C includes the following five types.
(Lamination direction)
i) Between the active region 10A and the lower capacitor electrode layer CA1 The lower region formed on the substrate 10 with the power supply potential Vel supplied as one electrode and the gate potential supplied by sandwiching the insulating film L0. The capacitive element C is configured with the electrode layer CA1 as the other electrode.
ii) Between the upper capacitor electrode layer CA2 and the gate layer Gdr and between the upper capacitor electrode layer CA4 and the lower capacitor electrode layer CA1 The gate layer Gdr to which the gate potential is supplied is used as one electrode, and the power supply potential is formed with the insulating layer LA interposed therebetween. The capacitive element C is configured with the upper capacitive electrode layer CA2 supplied with Vel as the other electrode. The capacitive element C has the lower capacitive electrode layer CA1 formed integrally with the gate layer Gdr as one electrode, and the upper capacitive electrode layer CA4 formed with the insulating layer LA interposed therebetween and supplied with the power supply potential Vel as the other electrode. Is configured.
iii) Between the upper capacitor electrode layer CA3 and the power supply line layer 41, the upper capacitor electrode layer CA3 to which the gate potential is supplied is used as one electrode, and the insulating layer LB
The capacitor element C is configured with the power supply line layer 41 formed with the power supply potential Vel supplied therebetween as the other electrode.
The capacitive element C in i) and the capacitive element C in ii) are configured to overlap in a plan view. Further, the capacitive element C of i) and the capacitive element C of iii), and the capacitive element C of ii) and the capacitive element C of iii) are configured to overlap in a plan view.
(Plane direction)
iv) Between the upper capacitive electrode layer CA2 and the upper capacitive electrode layer CA3 The upper capacitive electrode layer CA2 to which the power supply potential Vel is supplied is used as one electrode, and the upper capacitive electrode layer to which the gate potential is supplied with the insulating layer LB interposed therebetween. A capacitive element C is configured with CA3 as the other electrode.
v) Between the upper capacitive electrode layer CA4 and the upper capacitive electrode layer CA3 The upper capacitive electrode layer CA4 to which the power supply potential Vel is supplied is used as one electrode, and the upper capacitive electrode layer to which the gate potential is supplied with the insulating layer LB interposed therebetween. A capacitive element C is configured with CA3 as the other electrode.

  In the present invention, as described above, the capacitive element C is formed in a layer above the gate layer Gdr of the driving transistor Tdr, and is formed in the same layer as the upper layer, that is, in the plane direction in the upper layer. Since the capacitive element C is formed, it is possible to ensure the capacity of the capacitive element by effectively utilizing the layer above the gate layer Gdr. In addition, since the capacitive element C is formed in the same layer as the layer above the gate layer Gdr, it is possible to simplify the manufacturing process. Further, a part of the capacitive element C formed in the same layer is arranged so as to be arranged in the plane direction between the power supply site and the selection transistor Tsl, so that the shield of the gate layer Gdr of the driving transistor Tdr is shielded. There is an advantage that it is easy. Further, since the capacitive element formed by each of the drive transistor Tdr and the upper capacitive electrode layers CA2, CA3, and CA4 is arranged so as to overlap in a plan view, the capacitance of the capacitive element is secured while securing the capacitance. Densification can be realized.

  In the present embodiment, a MOS capacitor having the active region 10A into which the impurity is implanted as one electrode and the lower capacitor electrode layer CA1 as the other electrode through the insulating film L0 is also used as the capacitor element C. It is possible to achieve high density of pixels while securing the capacitance of the element.

  In the case of an organic electroluminescence device, since a high voltage such as 15 V is used, if variation occurs in the gate potential of the drive transistor, the influence of the variation on the light emission luminance of the light emitting element increases. It is important to improve the retention of the gate potential. According to the present embodiment, since the capacitance of the capacitive element is ensured as described above, it is possible to improve the retention of the gate potential of the driving transistor, and provide a high-quality image with no variation in light emission luminance. Can do.

  As described above, the upper capacitor electrode layer CA2 also functions as a source wiring or a drain wiring of the driving transistor Tdr. Therefore, the process can be simplified as compared with the case where the source wiring or drain wiring of the driving transistor Tdr and the capacitor electrode are formed separately. In addition, the upper capacitor electrode layer CA2 also functions as a light shielding portion in relation to the reflective layer 55. As shown in FIG. 9, the reflective layer 55 is not formed in a continuous pattern without a gap between adjacent pixels, but is formed separately for each pixel. Accordingly, a gap between the reflective layers 55 is generated between adjacent pixels. However, as understood from FIGS. 6 and 12, the upper capacitor electrode layer CA2 formed below the reflective layer 55 has the opening 50 and the opening 51, and the gate potential portion of the driving transistor Tdr, The pixel conductive portion, the conductive portion of the selection transistor Tsl, and other conductive portions are disposed so as to surround the pixel conductive portion, and are continuously formed without a gap between adjacent pixels. Therefore, even if there is a gap between the reflective layers 55 between adjacent pixels, the light traveling to the drive transistor Tdr and the selection transistor Tsl is blocked by the upper capacitor electrode layer CA2. Therefore, the upper capacitor electrode layer CA2 also functions as a light shielding part. Since the power supply line layer 41 is also a pattern that is continuously formed without a gap between adjacent pixels, it functions as a light-shielding portion for the gate potential portion of the drive transistor Tdr and the surrounding conductive portions. In other words, since the end portion of the reflective layer 55 is arranged so as to overlap the upper capacitive electrode layer CA2 or the power supply line layer 41, the light transmitted between the adjacent reflective layers 55 is transmitted to the upper capacitive electrode layer CA2 or the power supply line. It is blocked by the line layer 41. Therefore, the structure is such that light does not easily reach each transistor T.

  Regarding the conduction between the capacitor electrode and the power supply line layer, the upper capacitor electrode layer CA2 functioning as the second electrode C2 has a conduction hole HC3 as a first conduction portion penetrating the insulating layer LB, as understood from FIG. Conduction with the power line layer 41 through HC5, HC6, and HC7. Further, as is understood from FIG. 7, the upper capacitor electrode layer CA4 of the third electrode is electrically connected to the power supply line layer 41 through the conduction hole HC4 and the conduction hole HC7 as the second conduction part penetrating the insulating layer LB. . Therefore, the capacitor electrode and the power supply line layer 41 can be connected with a low resistance as compared with the case where the power supply line layer 41 is extended to the lower layer to achieve conduction. Further, as understood from FIGS. 12 and 13, the power supply line layers 41 adjacent to each other across the scanning line 22 are connected via the conduction holes HC3, HC5, HC6, HC7 and the upper capacitive electrode layer CA2 as the first conduction part. And conduct. Therefore, as compared with the case of only the power supply line layer 41, the power supply line layer 41 and the upper capacitor electrode layer CA2 can be conducted in a lattice shape. Therefore, with this configuration, the higher power supply potential Vel can be stably supplied to the display pixel Pe.

  As is understood from FIGS. 3 to 7, the conductive portion connecting the driving transistor Tdr and the power supply line layer 41 is formed from the conductive hole HA5 that penetrates the insulating film L0 and the insulating layer LA and the conductive hole HC7 that penetrates the insulating layer LB. It is configured. This conduction portion functions as a source wiring or a drain wiring of the driving transistor Tdr. By configuring in this way, the drive transistor Tdr and the power supply line layer 41 can be connected with low resistance as compared with the case where the power supply line layer 41 is extended to the lower layer to achieve conduction.

  The conductive part that connects the gate layer Gdr of the drive transistor Tdr and the upper capacitive electrode layer CA3 is configured by a conductive hole HB2 that penetrates the insulating layer LA, as can be understood from FIGS. This conduction portion is a source wiring or a drain wiring of the selection transistor Tsl, and is provided through the layer in which the gate layer Gdr is formed. Therefore, the driving transistor Tdr and the power supply line layer 41 can be connected with a lower resistance than in the case where the capacitive electrode layer CA3 is extended to the lower layer to achieve conduction.

In the present invention, as understood from FIGS. 3 and 6 to 8, the power supply line layer 41 is disposed between the upper capacitive electrode layers CA 2, CA 3 and CA 4 constituting the capacitive element C and the signal line 26. To do. As illustrated in FIG. 13 and FIG. 14, the power supply line layer 41 not only covers the upper capacitor electrode layers CA2, CA3, CA4 in each pixel, but also is a continuous belt-like pattern with no gap between adjacent pixels. Therefore, a good shielding effect is exerted on the upper capacitor electrode layers CA2, CA3, CA4. Therefore, the power supply line layer 41 suppresses the coupling between the signal line 26 and the upper capacitor electrode layers CA2, CA3, CA4. In particular, the upper capacitor electrode layer CA3 that is conductive to the gate layer Gdr of the drive transistor Tdr is covered with the power supply line layer 41 to which the higher power supply potential Vel is supplied, and the higher power supply potential Vel is supplied. Arranged so as to be surrounded by upper capacitive electrode layers CA2 and CA4. As described above, the upper capacitor electrode layer CA3 is surrounded by the power supply potential Vel that is a fixed potential in the XY plane, and is disposed so as to be covered in the stacking direction by the power supply potential Vel that is the fixed potential. And the upper capacitor electrode layer CA3 are further suppressed from coupling. Further, as illustrated in FIGS. 8 and 14, the signal line 26 and the selection transistor Tsl are arranged to extend in the Y direction. Since the signal line 26 is arranged so as to overlap with the selection transistor Tsl in plan view, it is possible to realize pixel miniaturization. Furthermore, since the signal line 26 and the selection transistor Tsl overlap in plan view, the connection between the signal line 26 and the selection transistor Tsl is performed through the conduction holes HA1, HC2, and HD1 that penetrate the respective insulating layers. The signal line 26 and the selection transistor Tsl are connected with a low resistance. As a result, the writing capability of the signal line 26 with respect to the selection transistor Tsl is improved. The conductive portion connecting the signal line 26 and the selection transistor Tsl includes the conductive hole HA1 that penetrates the insulating film L0 and the insulating layer LA, the relay electrode QB3, the conductive hole HC1 that penetrates the insulating layer LB, the relay electrode QC1, and the insulating layer LC. It is constituted by a through hole HD1 that penetrates. This conduction portion is a source wiring or a drain wiring of the selection transistor Tsl, and is provided through the capacitive electrode layer in which the upper capacitive electrode layer CA2 and the like are formed. Therefore, the selection transistor Tsl and the signal line 26 can be connected with low resistance as compared with the case where the signal line 26 is extended to the lower layer to achieve conduction. In addition, the conducting portion between the signal line 26 and the selection transistor Tsl is disposed avoiding the pixel conducting portion. Furthermore, as understood from FIG. 6, between the relay electrode QB1 and the conduction hole HC9 which are pixel conduction parts, and the relay electrode QB3 and the conduction hole HC1 which are conduction parts of the signal line 26 and the selection transistor Tsl, A protruding portion CA2a is formed in the upper capacitor electrode layer CA2, and separates the pixel conduction portion, the conduction portion between the signal line 26 and the selection transistor Tsl. Therefore, the influence of the signal line 26 on the pixel conduction portion can be reduced.
The upper capacitor electrode layer CA2 is configured to be disposed between the gate potential portion of the driving transistor Tdr and the scanning line 22. Further, the power supply line layer 41 is configured to be disposed between the gate potential portion of the driving transistor Tdr and the scanning line 22. Therefore, coupling between the gate potential portion of the driving transistor Tdr and the scanning line 22 is suppressed.
The upper capacitor electrode layer CA2 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the driving transistor Tdr. Further, the power supply line layer 41 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the drive transistor Tdr. Therefore, the coupling between the conductive portion connecting the signal line 26 and the selection transistor Tsl and the gate potential portion of the driving transistor Tdr is suppressed.

  The conductive portion connecting the upper capacitor electrode layers CA1, CA2, CA3 and the power supply line layer 41, the conductive portion connecting the drive transistor Tdr and the power supply line layer 41, and the conductive portion connecting the gate layer Gdr of the drive transistor Tdr and the upper capacitive electrode layer CA3. All the parts are arranged avoiding the pixel conduction part. Therefore, the coupling between these conduction parts and the pixel conduction part is suppressed.

  In the present invention, as understood from FIGS. 3, 6, 7 and 10, the space between the upper capacitive electrode layers CA2, CA3 and CA4 constituting the capacitive element C and the first electrode E1 which is a pixel electrode. Further, the power supply line layer 41 is disposed. As illustrated in FIG. 13 and FIG. 14, the power supply line layer 41 not only covers the upper capacitor electrode layers CA2, CA3, CA4 in each pixel, but also is a continuous belt-like pattern with no gap between adjacent pixels. Therefore, a good shielding effect is exerted on the upper capacitor electrode layers CA2, CA3, CA4. Therefore, the power supply line layer 41 suppresses coupling between the first electrode E1 and the upper capacitor electrode layers CA2, CA3, CA4. Further, as understood from FIGS. 3 to 10, the conducting portion between the first electrode E1 and the source region or drain region of the driving transistor Tdr is a conducting hole HA6 penetrating the insulating film L0 and the insulating layer LA, and the relay electrode QB1. , A conduction hole HC9 penetrating the insulating layer LB, a relay electrode QC2, a conduction hole HD2 penetrating the insulating layer LC, a relay electrode QD1, an HE1 penetrating the insulating layer LD, and a conduction hole HF1 penetrating the optical path adjustment layer 60. Has been. These function as a source wiring or a drain wiring of the driving transistor Tdr. That is, the conduction portion between the first electrode E1 and the source region or drain region of the driving transistor Tdr is provided through the layer in which the upper capacitor electrode layer CA2 and the like are formed and the layer in which the power supply line layer 41 and the like are formed. The driving transistor Tdr is configured by a source wiring or a drain wiring. Accordingly, the source electrode or drain region of the driving transistor Tdr and the first electrode E1, which is a pixel electrode, have a low resistance compared to the case where the pixel electrode is extended to the source region or drain region layer of the driving transistor Tdr to achieve conduction. Can be connected.

  In the present invention, as understood from FIGS. 3 and 7, the scanning line 22 that is a control line of the selection transistor Tsl is formed in the same layer as the power supply line layer 41. Therefore, the process can be simplified. Further, as understood from FIGS. 3, 6 to 7, each capacitor electrode is lower than the signal line 26 and the scanning line 22, and the power supply line layer 41 is formed in the same layer as the scanning line 22. . Therefore, the influence of the signal line 26 and the scanning line 22 on the capacitor electrode and the transistor can be reduced without increasing the number of layers. The conducting portion between the scanning line 22 and the gate layer Gsl of the selection transistor Tsl is arranged to be shifted from the gate of the selection transistor Tsl in the lateral direction (negative direction in the X direction in FIG. 6) so as not to cross the signal line 26. Has been placed. It is possible to reduce the influence of the signal line 26 on the conduction portion between the selection transistor Tsl and the gate layer Gsl. Note that the conducting portion between the scanning line 22 and the gate layer Gsl of the selection transistor Tsl may be disposed directly above the active region 10A of the selection transistor Tsl, and the position of the conducting portion between the selection transistor Tsl and the signal line 26 may be shifted. .

  A reflective layer 55 is connected to the first electrode E1, which is a pixel electrode. Since the potential of the first electrode E1, that is, the drain or source potential of the drive transistor Tdr is set according to the potential of the drive transistor Tdr and the light emitting element 45, the potential of the first electrode E1 and the reflective layer 55 is Insensitive to the potential of the line 26.

  Note that the electrode constituting the capacitor element is formed using the power supply line layer 41, but may be provided in a layer different from the power supply line layer 41 or may be an electrode suspended from the power supply line layer 41. As compared with the case where the source wiring or the drain wiring itself of the driving transistor Tdr is used as a capacitor electrode, the capacitor dielectric film can be made thinner and the capacitance can be increased. Or the freedom degree of arrangement | positioning of a capacitive element can be increased. Further, as shown in FIG. 15, the upper capacitor electrode layer CA3 connected to the gate layer Gdr of the drive transistor Tdr may not be provided with an opening, and the upper capacitor electrode layer CA4 arranged in the opening may be omitted. . Further, as shown in FIG. 16, the corner portion 50a of the opening 50 of the upper capacitor electrode layer CA2 may be chamfered. Furthermore, as shown in FIG. 17, the corner 52a of the opening 52 of the upper capacitor electrode layer CA3 may be chamfered. In the corner portion, the interval between the upper capacitive electrodes is wider than that in other portions, and therefore there is a possibility that the corner portion may not function effectively. On the other hand, by smoothing the surface, it can function as a capacitor.

Second Embodiment
A second embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as that of 1st Embodiment in each form illustrated below, the reference | standard referred by description of 1st Embodiment is diverted, and each detailed description is abbreviate | omitted suitably.

  FIG. 18 is a circuit diagram of each display pixel Pe in the present embodiment. As illustrated in FIG. 18, the display pixel Pe according to the present embodiment includes a light emission control transistor Tel and a compensation transistor Tcmp in addition to the light emitting element 45, the drive transistor Tdr, the selection transistor Tsl, and the capacitive element C. The In this embodiment, each transistor T (Tdr, Tel, Tsl, Tcmp) of the display pixel Pe is a P-channel type, but an N-channel type transistor can also be used. The circuit of the display pixel Pe according to the present embodiment can be driven by any of a so-called coupling drive method and a so-called current programming method. First, driving by the coupling driving method will be described.

  The light emission control transistor Tel functions as a switch that controls the conduction state (conduction / non-conduction) between the other (drain or source) of the pair of current ends of the drive transistor Tdr and the first electrode E1 of the light emitting element 45. The drive transistor Tdr generates a drive current having a current amount corresponding to the voltage between its gate and source. In a state where the light emission control transistor Tel is controlled to be in an on state, the drive current is supplied from the drive transistor Tdr to the light emitting element 45 via the light emission control transistor Tel, so that the light emitting element 45 corresponds to the amount of current of the drive current. In a state where light is emitted with luminance and the light emission control transistor Tel is controlled to be in an off state, the light emitting element 45 is turned off by interrupting the supply of drive current to the light emitting element 45. The gate of the light emission control transistor Tel is connected to the control line 28.

  The compensation transistor Tcmp has a function of compensating for fluctuations in the threshold voltage of the drive transistor Tdr. When the light-emission control transistor Tel is in the off state and the selection transistor Tsl and the driving transistor Tdr are controlled in the on state, when the compensation transistor Tcmp is controlled in the on state, the gate potential and the drain or source potential of the driving transistor Tdr are The driving transistor Tdr becomes a diode connection. For this reason, the current flowing through the driving transistor Tdr charges the gate node and the signal line 26. Specifically, the current flows through a path of the power supply line layer 41 → the driving transistor Tdr → the compensation transistor Tcmp → the signal line 26. For this reason, when the driving transistor Tdr is controlled to be in the ON state, the signal line 26 and the gate node that are connected to each other rise from the potential in the initial state. However, if the threshold voltage of the driving transistor Tdr is | Vth |, the current flowing through the path becomes difficult to flow as the gate node approaches the potential (Vel− | Vth |), so that the compensation transistor Tcmp is turned off. By the end of the compensation period, the signal line 26 and the gate node are saturated with the potential (Vel− | Vth |). Therefore, the capacitive element C holds the threshold voltage | Vth | of the drive transistor Tdr until the end of the compensation period in which the compensation transistor Tcmp is turned off.

  In the present embodiment, the horizontal scanning period has a compensation period and a writing period, and each scanning line drive circuit 32 supplies each scanning line 22 with a scanning signal, thereby allowing each of the plurality of scanning lines 22 to be detected. Selection is performed sequentially for each horizontal scanning period. The selection transistor Tsl of each display pixel Pe corresponding to the scanning line 22 selected by the scanning line driving circuit 32 is turned on. Therefore, the drive transistor Tdr of each display pixel Pe is also turned on. Further, each scanning line driving circuit 32 sequentially selects each of the plurality of control lines 27 for each compensation period by supplying a control signal to each control line 27. The compensation transistor Tcmp of each display pixel Pe corresponding to the control line 27 selected by the scanning line driving circuit 32 is turned on. The capacitive element C holds the threshold voltage | Vth | of the drive transistor Tdr until the end of the compensation period in which the compensation transistor Tcmp is turned off. When each scanning line driving circuit 32 supplies a control signal to each control line 27 to control the compensation transistor Tcmp of each display pixel Pe to an off state, the path from the signal line 26 to the gate node of the driving transistor Tdr is as follows. Although it is in a floating state, it is maintained at (Vel− | Vth |) by the capacitor C. Next, the signal line driving circuit 34 applies a gradation potential (data signal) corresponding to the gradation specified by the image signal supplied from the external circuit for each display pixel Pe to the capacitor Cref for each writing period. Supply in parallel. The level of the grayscale potential is shifted using the capacitive element Cref, and the potential is supplied to the gate of the driving transistor Tdr of each display pixel Pe via the signal line 26 and the selection transistor Tsl. The capacitor C holds a voltage corresponding to the gradation potential while compensating for the threshold voltage | Vth | of the driving transistor Tdr. On the other hand, when the selection of the scanning line 22 in the writing period is completed, each scanning line driving circuit 32 supplies the control signal to each control line 28 to thereby control the light emission of each display pixel Pe corresponding to the control line 28. The transistor Tel is controlled to be on. Therefore, a driving current corresponding to the voltage held in the capacitor C in the immediately preceding writing period is supplied from the driving transistor Tdr to the light emitting element 45 via the light emission control transistor Tel. As described above, each light emitting element 45 emits light at a luminance corresponding to the gradation potential, whereby an arbitrary image designated by the image signal is displayed in the display area 16. Since the drive current supplied from the drive transistor Tdr to the light emitting element 45 is offset by the influence of the threshold voltage, even if the threshold voltage of the drive transistor Tdr varies for each display pixel Pe, the variation is compensated. Since the current corresponding to the gradation level is supplied to the light emitting element 45, the occurrence of display unevenness that impairs the uniformity of the display screen can be suppressed. As a result, high-quality display is possible.

  Next, driving by the current programming method will be described with reference to FIG. When the scanning signal of the scanning line 22 becomes L level, the selection transistor Tsl is turned on. Further, when the control signal of the control line 27 becomes L level, the compensation transistor Tcmp is turned on. Therefore, the drive transistor Tdr has a gate potential equal to the source potential or drain potential on the connection side with the light emission control transistor Tel, and functions as a diode. When the data signal of the signal line 26 becomes L level, the current Idata flows through the path of the power supply line layer 41 → the drive transistor Tdr → the compensation transistor Tcmp → the signal line 26. At that time, charges corresponding to the potential of the gate node of the driving transistor Tdr are accumulated in the capacitor C.

When the control signal of the control line 27 becomes H level, the compensation transistor Tcmp is turned off. At this time, the voltage at both ends of the capacitive element C is held at the voltage when the current Idata flows. When the control signal of the control line 28 becomes L level, the light emission control transistor Tel is turned on, and a current Ioled corresponding to the gate voltage flows between the source and drain of the drive transistor Tdr. Specifically, this current flows through a path of the power supply line layer 41 → the drive transistor Tdr → the light emission control transistor Tel → the light emitting element 45.

  Here, the current Ioled flowing through the light emitting element 45 is determined by the voltage between the gate node of the driving transistor Tdr and the drain node or the source node on the connection side with the power supply line layer 41, and the voltage is L level. This is the voltage held by the capacitive element C when the current Idata flows through the signal line 26 by the scanning signal. For this reason, when the control signal of the control line 28 becomes L level, the current Ioled that flows through the light emitting element 45 substantially matches the current Idata that flows immediately before. As described above, in the case of driving by the current programming method, the light emission luminance is defined by the current Idata. Although the scanning line 22 is a wiring different from the control line 27, the scanning line 22 and the control line 27 may be a single wiring.

  A specific structure of the organic electroluminescence device 100 of the second embodiment will be described in detail below. In the drawings referred to in the following description, the dimensions and scales of the elements are different from those of the actual organic electroluminescence device 100 for convenience of description. FIG. 20 is a cross-sectional view of the organic electroluminescent device 100, and FIGS. 21 to 28 show the state of the surface of the substrate 10 at each stage of forming each element of the organic electroluminescent device 100 as one display pixel Pe. It is the top view illustrated paying attention to minute. FIGS. 29 to 31 are plan views illustrating the surface of the substrate 10 by paying attention to four display pixels Pe. A cross-sectional view corresponding to the cross-section including the line II-II 'in FIGS. 21 to 28 corresponds to FIG. 21 to 31 are plan views, but from the viewpoint of facilitating visual grasp of each element, hatching in the same manner as FIG. 20 is added to each element common to FIG. 20 for convenience. Yes.

  20 and 21, an active region 10A (source / source) of each transistor T (Tdr, Tsl, Tel, Tcmp) of the display pixel Pe is formed on the surface of the substrate 10 made of a semiconductor material such as silicon. Drain region) is formed. Ions are implanted into the active region 10A. The active layer of each transistor T (Tdr, Tsl, Tel, Tcmp) of the display pixel Pe exists between the source region and the drain region, and ions different from the active region 10A are implanted. It is described integrally with the active region 10A. Also in the present embodiment, the active region 10A is formed in the region constituting the capacitive element C, and impurities are implanted into the active region 10A and connected to the power source. Then, a so-called MOS capacitor is formed in which the active region 10A is used as one electrode and the capacitor electrode formed via the insulating layer is used as the other electrode. Further, the active region 10A in the region constituting the capacitive element C also functions as a power supply potential portion. As understood from FIG. 21, the active region 10A of the compensation transistor Tcmp is connected to the active region 10A of the selection transistor Tsl in the portion where the conduction hole HA1 is provided. Therefore, the current end of the compensation transistor Tcmp also functions as the current end of the selection transistor Tsl. 20 and 22, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the gate layer G (Gdr, Gsl, Gel, Gcmp) of each transistor T. ) Is formed on the surface of the insulating film L0. The gate layer G of each transistor T faces the active layer with the insulating film L0 interposed therebetween. Further, as illustrated in FIG. 22, the gate layer Gdr of the drive transistor Tdr is formed to extend to the active region 10 </ b> A formed in the region constituting the capacitive element C, and constitutes the lower capacitive electrode layer CA <b> 1.

  As understood from FIG. 20, on the surface of the insulating film L0 on which the gate layer G and the lower capacitor electrode layer CA1 of each transistor T are formed, a plurality of insulating layers L (LA to LD) and a plurality of conductive layers ( A multilayer wiring layer is formed by alternately stacking wiring layers). Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate G of each transistor T is formed. 20 and 23, on the surface of the insulating layer LA, the upper capacitive electrode layers CA2, CA3, CA4, a plurality of relay electrodes QB (QB2, QB3, QB4, QB5, QB6), and light emission The control line 28 of the control transistor Tel is formed from the same layer. As understood from FIGS. 20 and 23, the upper capacitor electrode layer CA2 is an active region 10A that forms a source region or a drain region of the driving transistor Tdr through a conduction hole HA5 that penetrates the insulating layer LA and the insulating film L0. Conducted to. In the upper capacitor electrode layer CA2, an opening 50 is formed so as to surround a region where a part of the gate layer Gdr of the drive transistor Tdr and the lower capacitor electrode layer CA1 are formed in a plan view.

  In the opening 50, an upper capacitive electrode layer CA3 and an upper capacitive electrode layer CA4 are formed in the same layer as the upper capacitive electrode layer CA2. An opening 52 is formed in the upper capacitor electrode layer CA3, and the upper capacitor electrode layer CA4 is formed in the opening 52. That is, the upper capacitive electrode layer CA2 and the upper capacitive electrode layer CA3 are formed and electrically insulated from each other, and the upper capacitive electrode layer CA3 and the upper capacitive electrode layer CA4 are formed separated from each other and electrically insulated. Has been. The upper capacitor electrode layer CA3 also functions as a wiring layer that connects the gate layer Gdr of the drive transistor Tdr and the drain region or source region of the selection transistor Tsl. That is, as understood from FIGS. 20, 22 and 23, the conductive layer HA2 is electrically connected to the active region 10A of the selection transistor Tsl through the conductive hole HA2 penetrating the insulating layer LA and the insulating film L0. It is electrically connected to the gate Gdr of the drive transistor Tdr through the hole HB2.

  Conductive part of the drive transistor Tdr, the compensation transistor Tcmp and the light emission control transistor Tel, a conductive part of the compensation transistor Tcmp and the selection transistor Tsl, a conductive part of the gate layer Gcmp of the compensation transistor Tcmp, a conductive part of the gate layer Gsl of the selection transistor Tsl In addition, the relay electrode QB4, the relay electrode QB3, the relay electrode QB5, the relay electrode QB2, and the relay electrode QB6 are connected to the upper capacitor electrode layer CA2 in each of the conduction parts between the light emission control transistor Tel and the first electrode E1 as the pixel electrode. It is formed in the same layer. Further, the control line 28 is formed in the same layer as the upper capacitor electrode layer CA2 in the conduction portion of the gate layer Gel of the light emission control transistor Tel. As understood from FIGS. 20, 22 and 23, the relay electrode QB4 is an active region that forms the drain region or the source region of the drive transistor Tdr through the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA. Conducts to 10A. The relay electrode QB4 is electrically connected to the active region 10A that forms the drain region or the source region of the compensation transistor Tcmp through the conduction hole HA7 that penetrates the insulating film L0 and the insulating layer LA. Further, the relay electrode QB4 is electrically connected to an active region 10A that forms a drain region or a source region of the light emission control transistor Tel through a conduction hole HA8 that penetrates the insulating film L0 and the insulating layer LA. The relay electrode QB2 is electrically connected to the gate layer Gsl of the selection transistor Tsl through a conduction hole HB1 that penetrates the insulating layer LA. The relay electrode QB3 forms a source region or a drain region of the selection transistor Tsl through a conduction hole HA1 that penetrates the insulating layer LA and the insulating film L0, and an active region that forms a source region or a drain region of the compensation transistor Tcmp. Conducts to 10A. The relay electrode QB5 is electrically connected to the gate layer Gcmp of the compensation transistor Tcmp through a conduction hole HB3 that penetrates the insulating layer LA. The relay electrode QB6 is electrically connected to an active region 10A that forms a drain region or a source region of the light emission control transistor Tel through a conduction hole HA9 that penetrates the insulating film L0 and the insulating layer LA.

  The control line 28 of the light emission control transistor Tel is electrically connected to the gate layer Gel of the light emission control transistor Tel through a conduction hole HB4 formed in the insulating layer LA. As understood from FIG. 29, the control line 28 extends linearly in the X direction across the plurality of display pixels Pe, and is electrically insulated from the gate layer Gcmp of the compensation transistor Tcmp by the insulating layer LA. As understood from FIG. 23, each of the selection transistor Tsl, the drive transistor Tdr, and the light emission control transistor Tel is formed so that the channel length is along the Y direction. The region constituting the capacitive element C is disposed at a position shifted in the X direction (the positive side in the X direction in FIG. 6) with respect to the drive transistor Tdr. Further, the conduction point between the gate layer Gsl of the selection transistor Tsl and the relay electrode QB2 is arranged at a position shifted in the X direction (the negative side in the X direction in FIG. 6) with respect to the selection transistor Tsl. The conduction point between the gate layer Gcmp of the compensation transistor Tcmp and the relay electrode QB5 is arranged at a position shifted in the Y direction (the positive side in the Y direction in FIG. 23) with respect to the compensation transistor Tcmp.

  The insulating layer LB includes an upper capacitive electrode layer CA2, an upper capacitive electrode layer CA3, an upper capacitive electrode layer CA4, a plurality of relay electrodes QB (QB2, QB3, QB4, QB5, QB6), and a control line 28. It is formed on the surface of the insulating layer LA. As understood from FIGS. 20 and 24, on the surface of the insulating layer LB, the power supply line layer 41 as the first power supply conductor, the scanning line 22, the control line 27 of the compensation transistor Tcmp, and a plurality of relays The electrodes QC (QC1, QC3) are formed from the same layer. The power supply line layer 41 is electrically connected to the mounting terminal 36 to which the higher power supply potential Vel is supplied via wiring (not shown) in the multilayer wiring layer. The power supply line layer 41 is formed in the display area 16 of the first area 12 shown in FIG. Although not shown, another power line layer is also formed in the peripheral region 18 of the first region 12. This power supply line layer is electrically connected to the mounting terminal 36 to which the lower power supply potential Vct is supplied via wiring (not shown) in the multilayer wiring layer. The power supply line layer 41 and the power supply line layer to which the lower power supply potential Vct is supplied are formed of a conductive material containing, for example, silver or aluminum and have a thickness of, for example, about 100 nm.

  The power supply line layer 41 is a power supply line to which the higher power supply potential Vel is supplied as described above, and as understood from FIGS. 24 and 30, the opening 50 of the upper capacitor electrode layer CA2 and the upper capacitor around it. The electrode layer CA2 is covered in each pixel. The power supply line layer 41 is further extended to a position that covers the control line 28 of the light emission control transistor Tel of the display pixel Pe adjacent in the Y direction, and an opening is formed in a continuous portion with the adjacent display pixel Pe. 53 is formed and is disposed so as to surround the pixel electrode conducting portion (the conducting portion of the light emission control transistor Tel and the relay electrode QC3). The power supply line layer 41 is a pattern formed continuously without a gap between the display pixels Pe adjacent in the X direction.

  As understood from FIGS. 20 and 24, the power supply line layer 41 formed in the display region 16 is electrically connected to the upper capacitor electrode layer CA2 through the conduction hole HC3 formed in the insulating layer LB for each display pixel Pe. To do. The power supply line layer 41 is electrically connected to the upper capacitor electrode layer CA2 through the conduction holes HC5 and HC6 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 20, 22 to 24, the power supply line layer 41 has a capacitance via the upper capacitive electrode layer CA2 and the conduction holes HA3 and HA4 penetrating the insulating film L0 and the insulating layer LA. It conducts to the active region 10A formed in the region constituting the element C. Furthermore, as understood from FIGS. 20 and 24, the power supply line layer 41 is electrically connected to the upper capacitor electrode layer CA2 through the conduction hole HC7 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 20, 22 to 24, the power supply line layer 41 includes the upper capacitor electrode layer CA <b> 2 and the driving transistor Tdr through the conduction hole HC <b> 7 penetrating the insulating film L <b> 0 and the insulating layer LA. It conducts to an active region 10A that forms a source region or a drain region. That is, the upper capacitor electrode layer CA2 also functions as a wiring layer that connects the source region or the drain region of the drive transistor Tdr and the power supply line layer 41. As understood from FIGS. 20 and 24, the power supply line layer 41 is electrically connected to the upper capacitor electrode layer CA4 through the conduction holes HC4 and HC8 formed in the insulating layer LB for each display pixel Pe.

  As understood from FIG. 24, the scanning line 22 is electrically connected to the relay electrode QB2 through the conduction hole HC2 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 22 to 24, the scanning line 22 is electrically connected to the gate layer Gsl of the selection transistor Tsl via the relay electrode QB2 and the conduction hole HB1 penetrating the insulating layer LA. As understood from FIG. 30, the scanning line 22 extends linearly in the X direction over the plurality of display pixels Pe, and is electrically insulated from the upper capacitor electrode layer CA2 and the relay electrode QB4 by the insulating layer LB. .

  As understood from FIG. 24, the control line 27 is electrically connected to the relay electrode QB5 through the conduction hole HC10 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 22 to 24, the control line 27 is conducted to the gate layer Gcmp of the compensation transistor Tcmp via the relay electrode QB5 and the conduction hole HB3 penetrating the insulating layer LA. As understood from FIG. 30, the control line 27 extends linearly in the X direction over the plurality of display pixels Pe, and is electrically insulated from the upper capacitor electrode layer CA2 and the relay electrode QB4 by the insulating layer LB. .

  As understood from FIG. 23, the relay electrode QC3 is electrically connected to the relay electrode QB6 through the conduction hole HC11 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 21 to 23, the relay electrode QC3 is electrically connected to the active region 10A of the light emission control transistor Tel via the relay electrode QB6 and the conduction hole HA9 penetrating the insulating film L0 and the insulating layer LA. .

  As understood from FIG. 24, the relay electrode QC1 is electrically connected to the relay electrode QB3 through the conduction hole HC1 formed in the insulating layer LB for each display pixel Pe. Therefore, as understood from FIGS. 22 to 24, the relay electrode QC1 is connected to the drain region of the selection transistor Tsl and the compensation transistor Tcmp via the relay electrode QB3 and the conduction hole HA1 penetrating the insulating film L0 and the insulating layer LA. It conducts to the active region 10A forming the source region.

  The insulating layer LC is formed on the surface of the insulating layer LB on which the power line layer 41, the scanning line 22, the control line 27, and the relay electrodes QC1 and QC3 are formed. As understood from FIGS. 20 and 25, the signal line 26 and the relay electrode QD2 are formed from the same layer on the surface of the insulating layer LC. The signal line 26 extends linearly in the Y direction over the plurality of pixels P, and is electrically insulated from the scanning line 22, the control line 27, and the power supply line layer 41 by the insulating layer LC. Specifically, as understood from FIGS. 24 and 25, the signal line 26 is electrically connected to the relay electrode QC1 through the conduction hole HD1 formed in the insulating layer LC for each display pixel Pe. Therefore, as understood from FIGS. 22 to 25, the signal line 26 is connected to the relay electrode QC1, the conduction hole HC1 that penetrates the insulating film LB, the relay electrode QB3, and the conduction that penetrates the insulating film L0 and the insulating layer LA. The active region 10A is connected to the selection transistor Tsl and the compensation transistor Tcmp through the hole HA1. The signal line 26 is formed so as to pass through the upper layer position of the relay electrode QC1, the scanning line 22, the control line 27, and the power supply line layer 41, and the channel length direction (Y direction) of the selection transistor Tsl. ) And overlaps with the selection transistor Tsl through the scanning line 22, the control line 27, and the power supply line layer 41 in plan view.

  As understood from FIG. 25, the relay electrode QD2 is electrically connected to the relay electrode QC3 through the conduction hole HD3 formed in the insulating layer LC for each display pixel Pe. Therefore, as understood from FIGS. 22 to 25, the relay electrode QD2 includes the conduction hole HD3 formed in the insulating layer LC, the relay electrode QC3, the conduction hole HC11 formed in the insulating layer LB, and the relay electrode QB6. Then, it is electrically connected to the active region 10A forming the drain region or the source region of the light emission control transistor Tel through the conduction hole HA9 penetrating the insulating film L0 and the insulating layer LA.

  As illustrated in FIG. 20, the insulating layer LD is formed on the surface of the insulating layer LC on which the signal line 26 and the relay electrode QD2 are formed. In the above description, the display pixel Pe is focused. However, the structure of each element from the surface of the substrate 10 to the insulating layer LD is common to the dummy pixel Pd in the peripheral region 18.

  A planarization process is performed on the surface of the insulating layer LD. For the planarization treatment, a known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily employed. As illustrated in FIGS. 20 and 26, the reflective layer 55 is formed on the surface of the insulating layer LD that has been highly planarized by the planarization process. The reflective layer 55 is a light-reflective conductive material containing, for example, silver or aluminum and is formed to a thickness of, for example, about 100 nm. The reflection layer 55 is formed of a light-reflective conductive material, and is disposed so as to cover each transistor T, each wiring, and each relay electrode as shown in FIG. Accordingly, there is an advantage that intrusion of external light is prevented by the reflective layer 55, and current leakage of each transistor T due to light irradiation can be prevented.

  As understood from FIGS. 20 and 26, the reflective layer 55 is electrically connected to the relay electrode QD2 through the conductive hole HE2 formed in the insulating layer LD for each display pixel Pe. Therefore, as understood from FIGS. 22 to 26, the reflective layer 55 includes the conduction hole HE2 that penetrates the insulating layer LD, the relay electrode QD2, the conduction hole HD3 that penetrates the insulating layer LC, and the relay electrode QC3. Conduction to the active region 10A forming the drain region or the source region of the light emission control transistor Tel through the conduction hole HC11 penetrating the insulating layer LB, the relay electrode QB6, and the conduction hole HA9 penetrating the insulating film L0 and the insulating layer LA. To do.

  As illustrated in FIG. 20, the optical path adjustment layer 60 is formed on the surface of the insulating layer LD on which the reflective layer 55 is formed. The optical path adjustment layer 60 is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each display pixel Pe. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different.

  As illustrated in FIGS. 20 and 27, the first electrode E <b> 1 for each display pixel Pe in the display region 16 is formed on the surface of the optical path adjustment layer 60. The first electrode E1 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above with reference to FIG. 2, the first electrode E <b> 1 is a substantially rectangular electrode (pixel electrode) that functions as an anode of the light emitting element 45. The first electrode E1 is electrically connected to the reflective layer 55 through a conduction hole HF2 formed in the optical path adjustment layer 60 for each display pixel Pe. Therefore, as understood from FIGS. 22 to 27, the first electrode E1 includes the conduction hole HF2 that penetrates the optical path adjustment layer 60, the reflection layer 55, the conduction hole HE2 that penetrates the insulating layer LD, and the relay electrode QD2. And through a conduction hole HD3 that penetrates the insulating layer LC, a relay electrode QC3, a conduction hole HC11 that penetrates the insulating layer LB, a relay electrode QB6, and a conduction hole HA9 that penetrates the insulating film L0 and the insulating layer LA. The light-emission control transistor Tel is electrically connected to the active region 10A that forms the drain region or the source region.

  On the surface of the optical path adjustment layer 60 on which the first electrode E1 is formed, a pixel definition layer 65 is formed over the entire area of the substrate 10 as illustrated in FIGS. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from FIG. 28, the pixel definition layer 65 has openings 65 </ b> A corresponding to the first electrodes E <b> 1 in the display region 16. A region in the pixel definition layer 65 near the inner periphery of the opening 65A overlaps the periphery of the first electrode E1. That is, the inner peripheral edge of the opening 65A is located inside the peripheral edge of the first electrode E1 in plan view. Each opening 65A has a common planar shape (rectangular shape) and size, and is arranged in a matrix at a common pitch in each of the X direction and the Y direction. As understood from the above description, the pixel definition layer 65 is formed in a lattice shape in plan view. The planar shape and size of the opening 65A are the same as long as the display color is the same, and may be different when the display color is different. Also, the pitch of the openings 65A may be the same between openings having the same display color, and may be different between openings having different display colors.

  In addition, although detailed description is omitted, the light emitting functional layer 46, the second electrode E2, and the sealing body 47 are laminated on the upper layer of the first electrode E1, and the substrate 10 on which the above elements are formed. A sealing substrate (not shown) is bonded to the surface of the substrate with, for example, an adhesive. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. It is also possible to form a color filter for each display pixel Pe on the surface of the sealing substrate or the surface of the sealing body 47.

  As described above, in the second embodiment, the light emission control transistor Tel as the fourth transistor for controlling the connection state between the drive transistor Tdr as the first transistor and the light emitting element 45, and the third control line as The control line 28 of the light emission control transistor Tel is provided. The control line 28 was formed between the power supply line layer 41 and the gate layer Gel. Therefore, due to the shielding effect of the power supply line layer 41, the influence on the control line 28 and the gate layer Gel by the signal line 26 and the like disposed above the power supply line layer 41 can be suppressed. In addition, the influence of the control line 28 and the gate layer Gel on the signal line 26 can be suppressed by the shielding effect of the power supply line layer 41. 29 and 30, the power supply line layer 41 covers the control line 28 and the gate layer Gel with a continuous pattern with no gap in the X direction, thereby blocking light to the light emission control transistor Tel. It also functions as a light shielding part. Further, as understood from FIG. 25, the signal line 26 is arranged so as to overlap with the selection transistor Tsl in a plan view, so that there is an advantage that the pixel can be miniaturized.

  Furthermore, in the second embodiment, as understood from FIG. 30, the power supply line layer 41 extends to a position covering the light emission control transistor Tel of the display pixel Pe and the light emission control transistor Tel adjacent to each other in the Y direction. Formed and arranged so as to surround the pixel conduction portion by the opening 53. Therefore, a high shielding effect for the pixel conduction portion is exhibited, and a good light shielding effect for the driving transistor Tdr and the light emission control transistor Tel is exhibited.

  In the second embodiment, the compensation transistor Tcmp as a third transistor for controlling the connection state between the active region 10A forming the source region or the drain region which is the second current end of the driving transistor Tdr and the gate, The control line 27 of the compensation transistor Tcmp as the second control line is provided, and the control line 27 is formed in the same layer as the power supply line layer 41. Therefore, the process can be simplified.

  As understood from FIGS. 20 to 27, the conductive portion between the first electrode E1 which is a pixel electrode and the source region or drain region of the light emission control transistor Tel, that is, the pixel conductive portion includes the insulating film L0 and the insulating layer LA. Conducting hole HA9, relay electrode QB6, conducting hole HC11 penetrating insulating layer LB, relay electrode QC3, conducting hole HD3 penetrating insulating layer LC, relay electrode QD2, HE2 penetrating insulating layer LD, and optical path adjusting layer It is constituted by a conduction hole HF2 that penetrates through 60. These function as the source wiring or drain wiring of the light emission control transistor Tel. That is, the conduction portion between the first electrode E1 and the source region or drain region of the light emission control transistor Tel passes through the layer in which the upper capacitor electrode layer CA2 or the like is formed and the layer in which the power supply line layer 41 or the like is formed. The light emission control transistor Tel is provided by a source wiring or a drain wiring. Therefore, compared with the case where the pixel electrode is extended to the source region or drain region layer of the light emission control transistor Tel to achieve conduction, the first electrode which is the pixel electrode and the source region or drain region of the light emission control transistor Tel with low resistance. E1 can be connected.

  As understood from FIGS. 23 and 24, the conduction portion between the gate of the compensation transistor Tcmp and the control line 27 is arranged so as to be shifted in the Y direction with respect to the gate of the compensation transistor Tcmp. Therefore, the signal line 26 can be arranged in a layer immediately above the layer in which the control line 27 is formed without stacking an extra layer. The conductive portion between the gate of the compensation transistor Tcmp and the control line 27 is arranged so as to overlap the compensation transistor Tcmp in plan view, and the conductive portion between the selection transistor Tsl, the compensation transistor Tcmp and the signal line 26 is compensated in plan view. The direction of the channel length of the transistor Tcmp may be shifted.

As understood from FIG. 25, since the signal line 26 is arranged so as to overlap with the compensation transistor Tcmp in a plan view, there is an advantage that the pixel can be miniaturized. In addition, since the conductive portion between the signal line 26 and the compensation transistor Tcmp can be disposed directly below the signal line 26, the signal line 26 and the compensation transistor Tcmp can be formed with low resistance by a conduction hole or a relay electrode penetrating the insulating layer. Can be conducted. As a result, the writing capability of the signal line 26 to the compensation transistor Tcmp is improved.
The upper capacitor electrode layer CA2 is configured to be disposed between the scanning line 22 or the control line 27 and the gate potential portion of the driving transistor Tdr. Further, the power supply line layer 41 is configured to be disposed between the scanning line 22 or the control line 27 and the gate potential portion of the driving transistor Tdr. Therefore, coupling between the scanning line 22 or the control line 27 and the gate potential portion of the driving transistor Tdr is suppressed.
The upper capacitor electrode layer CA2 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the driving transistor Tdr. Further, the power supply line layer 41 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the drive transistor Tdr. Therefore, the coupling between the conductive portion connecting the signal line 26 and the selection transistor Tsl and the gate potential portion of the driving transistor Tdr is suppressed.

  In addition, with respect to the configuration common to the first embodiment, the same effects as those in the first embodiment described above can be achieved. Also in the second embodiment, a modification similar to the modification described in the first embodiment can be applied, such as an electrode formed in a layer different from the power supply line layer 41 as an electrode constituting the capacitive element. It is.

<Third Embodiment>
A third embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as 1st Embodiment and 2nd Embodiment in each form illustrated below, the code | symbol referred by description of 1st Embodiment and 2nd Embodiment is diverted, respectively. The detailed description of is omitted as appropriate.

  The circuit of each display pixel Pe of the third embodiment is the same as the circuit of the second embodiment, and includes a compensation transistor Tcmp and a light emission control transistor Tel. The specific structure of the organic electroluminescence device 100 of the third embodiment is substantially the same as the specific structure of the organic electroluminescence device 100 of the second embodiment. Hereinafter, for the sake of simplification, only different portions will be described.

  FIG. 32 is a cross-sectional view of the organic electroluminescent device 100, and FIGS. 33 to 40 show the state of the surface of the substrate 10 at each stage of forming each element of the organic electroluminescent device 100 as one display pixel Pe. It is the top view illustrated paying attention to minute. 41 to 43 are plan views illustrating the surface of the substrate 10 by paying attention to four display pixels Pe. A cross-sectional view corresponding to the cross section including the line III-III 'in FIGS. 33 to 40 corresponds to FIG. 33 to 43 are plan views. From the viewpoint of facilitating visual grasp of each element, hatching in the same manner as FIG. 32 is added to each element common to FIG. 32 for convenience. Yes.

  In the third embodiment, as can be understood from FIGS. 35 and 41, the upper capacitor electrode layer CA2 surrounds a part of the gate conduction part of the drive transistor Tdr and a part of the capacitor element C by the opening 50. Not only the selection transistor Tsl, the compensation transistor Tcmp, the light emission control transistor Tel, the conduction portion of the drive transistor Tdr, the compensation transistor Tcmp and the light emission control transistor Tel, and the source region or the drain region of the light emission control transistor Tel. The pixel conduction portion is disposed so as to be surrounded by the opening 54. As understood from FIG. 41, the upper capacitor electrode layer CA2 has a pattern that is continuous without a gap between the display pixels Pe adjacent in the X direction and the Y direction. Unlike the second embodiment, the upper capacitor electrode layer CA2 is electrically connected to the power supply line layer 41 not only by the conduction hole HC3 penetrating the insulating layer LB but also by the conduction hole HC13 penetrating the insulating layer LB. Yes. Therefore, as compared with the case of only the power supply line layer 41, the power supply line layer 41 and the upper capacitor electrode layer CA2 can be conducted in a lattice shape. Therefore, with this configuration, the higher power supply potential Vel can be stably supplied to the display pixel Pe. In addition, due to the shielding effect of the upper capacitor electrode layer CA2, it is possible to reduce the influence between the display pixels Pe adjacent in the X direction and the Y direction on each transistor and the pixel conduction portion. The upper capacitor electrode layer CA2 is disposed at a position overlapping the gap between the reflective layers 55 of the display pixels Pe adjacent in the X direction and the Y direction in plan view. Therefore, the light shielding property for each transistor is improved. In other words, since the end portion of the reflective layer 55 is arranged so as to overlap the upper capacitive electrode layer CA2 or the power supply line layer 41, the light transmitted between the adjacent reflective layers 55 is transmitted to the upper capacitive electrode layer CA2 or the power supply line. It is blocked by the line layer 41. Therefore, the structure is such that light does not easily reach each transistor T.

As understood from FIG. 36, in the third embodiment, the control line 28 of the light emission control transistor Tel is formed in the same layer as the control line 27 of the compensation transistor Tcmp, the scanning line 22, and the power supply line layer 41. . Therefore, the process can be simplified as compared with the second embodiment. As understood from FIGS. 33 to 37, the control line 28 of the light emission control transistor Tel is connected to the light emission control transistor through the conduction hole HB4 formed in the insulating layer LA, the conduction portion QB7, and the HC12 formed in the insulating layer LB. Conduction to the Tel gate layer Gel. As is understood from FIG. 41, the power supply line layer 41 continues without a gap between the display pixels Pe adjacent in the Y direction as in the second embodiment, and surrounds the pixel conduction portion in the display pixels Pe adjacent in the Y direction. It extends to the position. However, unlike the second embodiment, it does not surround the four sides of the pixel conducting portion, but the control line 28 side of the light emission control transistor Tel is open. Also in the third embodiment, a high shielding effect by the power supply line layer 41 is exhibited.
The upper capacitor electrode layer CA2 is configured to be disposed between any one of the scanning line 22 and the control lines 27 and 28 and the gate potential portion of the driving transistor Tdr. Furthermore, the power supply line layer 41 is configured to be disposed between any one of the scanning line 22 and the control lines 27 and 28 and the gate potential portion of the driving transistor Tdr. Therefore, coupling between any one of the scanning line 22 and the control lines 27 and 28 and the gate potential portion of the driving transistor Tdr is suppressed.
The upper capacitor electrode layer CA2 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the driving transistor Tdr. Further, the power supply line layer 41 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the drive transistor Tdr. Therefore, the coupling between the conductive portion connecting the signal line 26 and the selection transistor Tsl and the gate potential portion of the driving transistor Tdr is suppressed.

  In addition, with respect to the configuration common to the second embodiment, the same effects as those of the second embodiment described above can be achieved. Also in the third embodiment, a modification similar to the modification described in the first embodiment can be applied, such as an electrode formed in a layer different from the power supply line layer 41 as an electrode constituting the capacitive element. It is.

<Fourth embodiment>
A fourth embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as 1st Embodiment and 2nd Embodiment in each form illustrated below, the code | symbol referred by description of 1st Embodiment and 2nd Embodiment is diverted, respectively. The detailed description of is omitted as appropriate.

  The circuit of each display pixel Pe of the fourth embodiment is the same as the circuit of the second embodiment, and includes a compensation transistor Tcmp and a light emission control transistor Tel. The specific structure of the organic electroluminescent device 100 of the fourth embodiment is substantially the same as the specific structure of the organic electroluminescent device 100 of the second embodiment. Hereinafter, for the sake of simplification, only different portions will be described.

  FIG. 44 is a cross-sectional view of the organic electroluminescence device 100, and FIGS. 45 to 52 show the state of the surface of the substrate 10 at each stage of forming each element of the organic electroluminescence device 100 as one display pixel Pe. It is the top view illustrated paying attention to minute. A cross-sectional view corresponding to the cross section including the IV-IV ′ line in FIGS. 45 to 52 corresponds to FIG. 44. 45 to 52 are plan views, but from the viewpoint of facilitating visual grasp of each element, hatching in the same manner as FIG. 44 is added to each element common to FIG. 44 for convenience. Yes.

  As is understood from FIGS. 45 to 49, the fourth embodiment is different from the second embodiment in that the channel length direction of the light emission control transistor Tel is the X direction (the extending direction of the control line 28). 45 and 49, the shape of the relay electrode QB6 constituting the pixel conducting portion is bent from the source region or the drain region of the light emission control transistor Tel, and the channel length direction of the light emission control transistor Tel Are arranged in parallel with each other. The light emission control transistor Tel is disposed so as to overlap the signal line 26 in plan view. Therefore, there is an advantage that the pixels can be easily miniaturized.

In the fourth embodiment, as understood from FIGS. 45 to 49, the control line 28 of the light emission control transistor Tel is formed in the same layer as the power supply line layer 41. Therefore, the process can be simplified more than in the second embodiment. As understood from FIGS. 45 to 49, the control line 28 of the light emission control transistor Tel is connected to the light emission control transistor through the conduction hole HB4 formed in the insulating layer LA, the conduction portion QB7, and the HC12 formed in the insulating layer LB. Conduction to the Tel gate layer Gel.
The upper capacitor electrode layer CA2 is configured to be disposed between any one of the scanning line 22 and the control lines 27 and 28 and the gate potential portion of the driving transistor Tdr. Furthermore, the power supply line layer 41 is configured to be disposed between any one of the scanning line 22 and the control lines 27 and 28 and the gate potential portion of the driving transistor Tdr. Therefore, coupling between any one of the scanning line 22 and the control lines 27 and 28 and the gate potential portion of the driving transistor Tdr is suppressed.
The upper capacitor electrode layer CA2 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the driving transistor Tdr. Further, the power supply line layer 41 is configured to be disposed between a conduction portion that connects the signal line 26 and the selection transistor Tsl and a gate potential portion of the drive transistor Tdr. Therefore, the coupling between the conductive portion connecting the signal line 26 and the selection transistor Tsl and the gate potential portion of the driving transistor Tdr is suppressed.

  In addition, with respect to the configuration common to the second embodiment, the same effects as those of the second embodiment described above can be achieved. Also in the fourth embodiment, a modification similar to the modification described in the first embodiment can be applied, such as an electrode formed in a layer different from the power supply line layer 41 as an electrode constituting the capacitive element. It is.

<Fifth Embodiment>
A fifth embodiment of the present invention will be described. In addition, about the element which an effect | action and function are the same as that of 1st Embodiment in each form illustrated below, the reference | standard referred by description of 1st Embodiment is diverted, and each detailed description is abbreviate | omitted suitably.

  The circuit of each display pixel Pe of the fifth embodiment is the same as the circuit of the first embodiment, and includes a drive transistor Tdr and a selection transistor Tsl. The specific structure of the organic electroluminescent device 100 of the fifth embodiment is substantially the same as the specific structure of the organic electroluminescent device 100 of the first embodiment. Hereinafter, for the sake of simplification, only different portions will be described.

  53 is a cross-sectional view of the organic electroluminescent device 100, and FIGS. 54 to 62 show the state of the surface of the substrate 10 at each stage of forming each element of the organic electroluminescent device 100 as one display pixel Pe. It is the top view illustrated paying attention to minute. A cross-sectional view corresponding to the cross section including the V-V ′ line in FIGS. 54 to 62 corresponds to FIG. 53. 54 to 62 are plan views. From the viewpoint of facilitating visual grasp of each element, hatching in the same manner as FIG. 53 is added to each element common to FIG. 53 for convenience. Yes.

  As can be understood by comparing FIG. 7 showing the power line layer 41 in the first embodiment and FIG. 57 showing the power line layer 41 in the fifth embodiment, the power line layer 41 in the fifth embodiment is selected. The conductive portion between the transistor Tsl and the scanning line 22, the conductive portion between the selection transistor Tsl and the signal line 26, and the pixel conductive portion are arranged to surround each other. As can be understood from FIG. 57, in the fifth embodiment, since the scanning line 22 is not formed in the same layer as the power supply line layer 41, the relay electrode QC4 is formed in the gate conduction portion of the selection transistor Tsl. . The relay electrode QC4 is electrically connected to the relay electrode QC2 through a conduction hole HC2 penetrating the insulating layer LB. Therefore, the relay electrode QC4 is electrically connected to the gate layer Gsl of the selection transistor Tsl via the conduction hole HC2 penetrating the insulating layer LB, the relay electrode QB2, and the conduction hole HB1 penetrating the insulating layer LA.

  In the fifth embodiment, the insulating layer LC is formed on the surface of the insulating layer LB on which the power line layer 41 and the plurality of relay electrodes QC (QC1, QC2, QC4) are formed. As understood from FIGS. 53 and 58, the scanning line 22 and the plurality of relay electrodes QD (QD1, QD3) are formed on the surface of the insulating layer LC. The scanning line 22 is electrically connected to the relay electrode QC4 through the conduction hole HD4 penetrating the insulating layer LC for each display pixel Pe. Therefore, as understood from FIGS. 54 to 58, the scanning line 22 includes the conduction hole HD4 penetrating the insulating layer LC, the relay electrode QC4, the conduction hole HC2 penetrating the insulating layer LB, the relay electrode QB2, It conducts to the gate layer Gsl of the select transistor Tsl through a conduction hole HB1 that penetrates the insulating layer LA. The scanning line 22 extends linearly in the X direction over the plurality of display pixels Pe, and is electrically insulated from the power supply line layer 41 by the insulating layer LC.

  As understood from FIGS. 53 and 58, the relay electrode QD3 is electrically connected to the relay electrode QC1 through the conduction hole HD1 formed in the insulating layer LC for each display pixel Pe. Therefore, as understood from FIGS. 54 to 58, the relay electrode QD3 includes the conduction hole HD1, which penetrates the insulating layer LC, the relay electrode QC1, the conduction hole HC1 which penetrates the insulating layer LB, and the relay electrode QB3. It conducts to the active region 10A of the select transistor Tsl through the conduction hole HA1 penetrating the insulating film L0 and the insulating layer LA.

  As understood from FIGS. 53 and 58, the relay electrode QD1 is electrically connected to the relay electrode QC2 through the conduction hole HD2 formed in the insulating layer LC for each display pixel Pe. Therefore, as understood from FIGS. 54 to 58, the relay electrode QD1 includes the conduction hole HD2, which penetrates the insulating layer LC, the relay electrode QC2, the conduction hole HC9 which penetrates the insulating layer LB, the relay electrode QB1, It conducts to the active region 10A of the drive transistor Tdr via the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA.

  In the fifth embodiment, the insulating layer LD is formed on the surface of the insulating layer LC on which the scanning lines 22 and the plurality of relay electrodes QD (QD1, QD3) are formed. As understood from FIGS. 53 and 59, the signal line 26 and the relay electrode QE1 are formed on the surface of the insulating layer LD. The signal line 26 is electrically connected to the relay electrode QD3 through a conduction hole HE3 formed in the insulating layer LD for each display pixel Pe. Therefore, as understood from FIGS. 54 to 59, the signal line 26 includes the conduction hole HE3 penetrating the insulating layer LD, the relay electrode QC3, the conduction hole HD1 penetrating the insulating layer LC, the relay electrode QC1, The conductive hole HC1 penetrating the insulating layer LB, the relay electrode QB3, and the conductive hole HA1 penetrating the insulating film L0 and the insulating layer LA are electrically connected to the active region 10A of the selection transistor Tsl. The signal line 26 extends linearly in the Y direction over the plurality of display pixels Pe, and is electrically insulated from the scanning line 22 by the insulating layer LD.

  As understood from FIG. 59, the relay electrode QE1 is electrically connected to the relay electrode QD1 through a conduction hole HE1 formed in the insulating layer LD for each display pixel Pe. Therefore, as understood from FIGS. 54 to 59, the relay electrode QE1 includes the conduction hole HE1 penetrating the insulating layer LD, the relay electrode QD1, the conduction hole HD2 penetrating the insulating layer LC, and the relay electrode QC2. The conductive hole HC9 that penetrates the insulating layer LB and the conductive hole HA6 that penetrates the relay electrode QB1, the insulating film L0, and the insulating layer LA are electrically connected to the active region 10A of the driving transistor Tdr.

  In the fifth embodiment, one more layer is formed than in the first embodiment, and the insulating layer LE is formed. The insulating layer LE is formed on the surface of the insulating layer LD on which the signal line 26 and the relay electrode QE1 are formed. As understood from FIGS. 53 and 60, the reflective layer 55 is formed on the surface of the insulating layer LE.

  A planarization process is performed on the surface of the insulating layer LE. For the planarization treatment, a known surface treatment technique such as chemical mechanical polishing (CMP) is arbitrarily employed. As illustrated in FIGS. 53 and 60, the reflective layer 55 is formed on the surface of the insulating layer LE highly planarized by the planarization process. The reflective layer 55 is a light-reflective conductive material containing, for example, silver or aluminum and is formed to a thickness of, for example, about 100 nm. The reflective layer 55 is formed of a light-reflective conductive material, and is disposed so as to cover each transistor T, each wiring, and each relay electrode as shown in FIG. Accordingly, there is an advantage that intrusion of external light is prevented by the reflective layer 55, and current leakage of each transistor T due to light irradiation can be prevented.

  As understood from FIGS. 53 and 60, the reflection layer 55 is electrically connected to the relay electrode QE1 through the conduction hole HF1 formed in the insulating layer LE for each display pixel Pe. Therefore, as understood from FIGS. 54 to 60, the reflective layer 55 includes the conduction hole HF1 that penetrates the insulating layer LE, the relay electrode QE1, the conduction hole HE1 that penetrates the insulating layer LD, and the relay electrode QD1. Driving through the conduction hole HD2 that penetrates the insulating layer LC, the relay electrode QC2, the conduction hole HC9 that penetrates the insulating layer LB, and the conduction hole HA6 that penetrates the relay electrode QB1, the insulating film L0, and the insulating layer LA Conduction to the active region 10A of the transistor Tdr.

  As illustrated in FIG. 53, the optical path adjustment layer 60 is formed on the surface of the insulating layer LE on which the reflective layer 55 is formed. The optical path adjustment layer 60 is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each display pixel Pe. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different.

  As illustrated in FIGS. 53 and 61, the first electrode E <b> 1 for each display pixel Pe in the display region 16 is formed on the surface of the optical path adjustment layer 60. The first electrode E1 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above with reference to FIG. 2, the first electrode E <b> 1 is a substantially rectangular electrode (pixel electrode) that functions as an anode of the light emitting element 45. The first electrode E1 is electrically connected to the reflective layer 55 through a conduction hole HG1 formed in the optical path adjustment layer 60 for each display pixel Pe. Therefore, as understood from FIGS. 54 to 61, the first electrode E1 includes the conduction hole HG1 formed in the optical path adjustment layer 60, the reflection layer 55, the conduction hole HF1 penetrating the insulating layer LE, and the relay electrode. QE1, conduction hole HE1 penetrating the insulating layer LD, relay electrode QD1, conduction hole HD2 penetrating the insulating layer LC, relay electrode QC2, conduction hole HC9 penetrating the insulating layer LB, relay electrode QB1, It conducts to the active region 10A of the drive transistor Tdr via the conduction hole HA6 that penetrates the insulating film L0 and the insulating layer LA.

  On the surface of the optical path adjustment layer 60 on which the first electrode E1 is formed, as illustrated in FIGS. 53 and 62, the pixel definition layer 65 is formed over the entire area of the substrate 10. The pixel definition layer 65 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from FIG. 62, the pixel definition layer 65 is formed with openings 65 </ b> A corresponding to the first electrodes E <b> 1 in the display region 16. A region in the pixel definition layer 65 near the inner periphery of the opening 65A overlaps the periphery of the first electrode E1. That is, the inner peripheral edge of the opening 65A is located inside the peripheral edge of the first electrode E1 in plan view. Each opening 65A has a common planar shape (rectangular shape) and size, and is arranged in a matrix at a common pitch in each of the X direction and the Y direction. As understood from the above description, the pixel definition layer 65 is formed in a lattice shape in plan view. The planar shape and size of the opening 65A are the same as long as the display color is the same, and may be different when the display color is different. Also, the pitch of the openings 65A may be the same between openings having the same display color, and may be different between openings having different display colors.

  In addition, although detailed description is omitted, the light emitting functional layer 46, the second electrode E2, and the sealing body 47 are laminated on the upper layer of the first electrode E1, and the substrate 10 on which the above elements are formed. A sealing substrate (not shown) is bonded to the surface of the substrate with, for example, an adhesive. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. It is also possible to form a color filter for each display pixel Pe on the surface of the sealing substrate or the surface of the sealing body 47.

  In the fifth embodiment, the power source between the layer in which the signal line 26 and the scanning line 22 are formed and the layer in which the upper capacitor electrode layer CA (CA2, CA3, CA4) is formed are provided. A line layer 41 is provided. As understood from FIGS. 56 and 57, the power supply line layer 41 has a shape that uniformly covers the upper capacitor electrode layers CA (CA2, CA3, CA4) and the transistors T (Tdr, Tsl). Therefore, it is possible to suppress coupling between the signal line 26 and the scanning line 22, the upper capacitor electrode layer CA (CA2, CA3, CA4), and the transistor T (Tdr, Tsl).

In addition, with respect to the configuration common to the first embodiment, the same effects as those in the first embodiment described above can be achieved. Also in the fifth embodiment, a modification similar to the modification described in the first embodiment can be applied, such as an electrode formed in a layer different from the power supply line layer 41 as an electrode constituting the capacitive element. It is.
In the third embodiment and the fourth embodiment, the scanning lines 22 and the control lines 27 and 28 are formed in the same layer as the power supply line layer 41. However, as in the fifth embodiment, the scanning lines 22 and the control lines 27, 28 may be provided in a layer above the power supply line layer 41, and the signal line 26 may be further formed in a layer thereabove. In this case, the power supply line layer 41 may be configured to surround the relay electrodes QB2, QB5, QB7, QC1, and QC3.

<Modification>
The above forms can be variously modified. Specific modifications are exemplified below. Two or more aspects arbitrarily selected from the following examples can be appropriately combined within a range that does not contradict each other.

(1) In each embodiment described above, the potential of the power supply line layer 41 is the Vel potential connected to the driving transistor Tdr, but may be another potential. In this case, a conduction hole for connecting the power supply line layer 41 and the drive transistor Tdr can be omitted. The power supply line layer 41 is electrically connected to the mounting terminal 36 to which another power supply potential Va is supplied, and the drive transistor Tdr and the upper capacitor electrode layer CA2 are electrically connected to the mounting terminal 36 to which the power supply potential Vel is supplied. Also good.

(2) In each of the above-described embodiments, the organic electroluminescence device 100 using the semiconductor substrate as the substrate 10 is illustrated, but the material of the substrate 10 is arbitrary. For example, a plate-like member such as glass or quartz can be used as the substrate 10. In each of the above-described embodiments, the drive circuit 30 is disposed in the second region 14 outside the first region 12 of the substrate 10. However, the drive circuit 30 may be disposed in the peripheral region 18, for example. For example, the drive circuit 30 is disposed between the second power supply conductor 42 and the substrate 10.

(3) The configuration of the light emitting element 45 is not limited to the above examples. For example, in each of the above-described embodiments, the configuration in which the light emitting functional layer 46 that generates white light is continuously formed over the plurality of display pixels Pe is exemplified. However, monochromatic light having a wavelength corresponding to the display color of each display pixel Pe is emitted. It is also possible to individually form the light emitting functional layer 46 for each display pixel Pe. In each of the above-described embodiments, a resonance structure is formed between the reflective layer 55 and the second electrode E2 (semi-transmissive reflective layer). For example, the power supply line layer 41 serving as the first power supply conductor is formed as a reflective conductive layer. It is also possible to form a resonance structure between the power line layer 41 (reflective layer) and the second electrode E2 (semi-transmissive reflective layer) by using a material. It is also possible to form the resonance structure between the first electrode E1 (reflective layer) and the second electrode E2 (semi-transmissive reflective layer) by forming the first electrode E1 with a reflective conductive material. In the configuration using the first electrode E1 as the reflective layer, the optical path adjustment layer 60 is formed between the first electrode E1 and the second electrode E2.

  In each of the above-described embodiments, the resonance wavelength of each display pixel Pe is adjusted by the optical path adjustment layer 60. However, the resonance wavelength of each display pixel Pe may be adjusted according to the film thickness of the first electrode E1 or the light emitting functional layer 46. Is possible.

  The light emitting functional layer 46 may emit light in any of the blue wavelength region, the green wavelength region, and the red wavelength region, or may emit white light. In this case, the light emitting functional layer 46 may be provided across a plurality of pixels in the display area. The light emitting functional layer 46 may be configured to emit different light in each of red, green, and blue pixels.

(4) In each of the above-described embodiments, the light emitting element 45 using the organic EL material is exemplified. However, the present invention similarly applies to a configuration using a light emitting element in which a light emitting layer is formed of an inorganic EL material or a light emitting element such as an LED. Applied. Further, in each of the above-described embodiments, the top emission type organic electroluminescence device 100 that emits light to the side opposite to the substrate 10 is exemplified, but the present invention is also applied to a bottom emission type light emitting device that emits light to the substrate 10 side. The invention applies as well.

(5) In each of the above-described embodiments, the configuration in which the dummy pixel Pd having a structure similar to the display pixel Pe (a structure of a wiring, a transistor, a capacitor, or the like) is disposed in the peripheral region 18 is illustrated. The configuration is not limited to the above examples. For example, a circuit other than the driving circuit 30 (the scanning line driving circuit 32 or the signal line driving circuit 34) or the driving circuit 30 and wirings can be arranged below the second power supply conductor 42 in the peripheral region 18. .

(6) In each of the above-described embodiments, attention is paid to the film thickness of the optical path adjustment layer 60 in order to simplify the description of the resonance wavelength. However, in reality, the reflection layer (for example, the first power supply conductor 41) having the resonance structure is used. The resonant wavelength of the resonant structure is set according to the refractive index of each layer positioned between the semi-transmissive reflective layer (for example, the second electrode E2) and the phase shift on the surfaces of the reflective layer and the semi-transmissive reflective layer.

(7) In each of the above-described embodiments, examples in which the five types of capacitive elements C i) to v) are configured have been described. However, any one of the capacitive elements C i) to v) may be omitted. Good. Further, a transistor other than the transistor described in each embodiment, a capacitor, a wiring, or the like may be added as appropriate. Further, in each embodiment, the scanning line 22, the signal line 26, the control lines 27 and 28, and the power supply line layer 41 are linear and uniform in width, but the present invention is limited to this aspect. Instead, the width of the wiring may be thicker than other portions, or may be formed by bending.

<Electronic equipment>
The organic electroluminescence device 100 exemplified in each of the above embodiments is suitably used as a display device for various electronic devices. In FIG. 63, a head-mounted display device 90 (HMD: Head Mounted Display) using the organic electroluminescence device 100 exemplified in each of the above embodiments is illustrated as an electronic device.

  The display device 90 is an electronic device that can be mounted on the user's head, and includes a transmissive portion (lens) 92L that overlaps the user's left eye, a transmissive portion 92R that overlaps the user's right eye, and a left-eye device. An organic electroluminescence device 100L and a half mirror 94L, and an organic electroluminescence device 100R and a half mirror 94R for the right eye are provided. The organic electroluminescent device 100L and the organic electroluminescent device 100R are arranged such that emitted light travels in opposite directions. The half mirror 94L for the left eye transmits the transmitted light of the transmission part 92L to the left eye side of the user and reflects the emitted light from the organic electroluminescence device 100L to the left eye side of the user. Similarly, the right-eye half mirror 94R transmits the light transmitted through the transmission portion 92R to the right eye side of the user and reflects the emitted light from the organic electroluminescence device 100R to the right eye side of the user. Therefore, the user perceives an image obtained by superimposing an image observed through the transmission unit 92L and the transmission unit 92R and a display image by each organic electroluminescence device 100. In addition, the stereoscopic image of the display image is displayed to the user by causing the organic electroluminescent device 100L and the organic electroluminescent device 100R to display the stereoscopic images (the left-eye image and the right-eye image) to which the parallax is added. Can be perceived.

  Note that the electronic apparatus to which the organic electroluminescence device 100 of each embodiment described above is applied is not limited to the display device 90 of FIG. For example, the organic electroluminescence device 100 of the present invention is also preferably used in an electronic view finder (EVF) used in an imaging device such as a video camera or a still camera. In addition, the light emitting device of the present invention can be used in various electronic devices such as mobile phones, personal digital assistants (smartphones), monitors such as televisions and personal computers, and car navigation devices.

DESCRIPTION OF SYMBOLS 100 ... Organic electroluminescent apparatus, 10 ... Board | substrate, 10A ... Active area | region, 12 ... 1st area | region, 14 ... 2nd area | region, 16 ... Display area, 18 ... Peripheral area | region, 22 ... Scanning line , 26 ... signal line, 27 ... control line, 28 ... control line, 30 ... drive circuit, 32 ... scanning line drive circuit, 34 ... signal line drive circuit, 36 ... mounting terminal, 41 ... 1st power supply conductor (power supply line layer), 42... 2nd power supply conductor, 45... Light emitting element, 46... Light emitting functional layer, 60. Capacitance element, C1... First electrode, C2... First electrode, E1... First electrode, E2... Second electrode, L (L0, LA, LB, LC, LD, LE). Q (QB1, QB2, QB3, QB4, QB5, QB6, QC1, QC2, QC3, QC4, QD1 QD2, QD3, QE1) ...... relay electrode, Tcmp ...... compensation transistor, Tdr ...... driving transistor, Tel ...... emission control transistor, Tsl ...... selection transistor.

Claims (20)

In organic electroluminescence equipment,
A first transistor;
An organic electroluminescence element that emits light with a luminance according to the magnitude of the current supplied through the first transistor;
A capacitive element having a first electrode connected to the gate of the first transistor, a second electrode, and a dielectric film provided between the first electrode and the second electrode;
The first electrode is formed in the same layer as the second electrode, and is disposed at a position away from the second electrode with the dielectric film interposed therebetween.
An organic electroluminescence device characterized by that.
A power line layer connected to one current end of the first transistor;
The second electrode is connected to a power line layer connected to the first transistor, and the first electrode is disposed so as to be surrounded by the second electrode in plan view.
The organic electroluminescent device according to claim 1. The capacitive element includes a third electrode,
The third electrode is connected to the power line layer and is disposed so as to be surrounded by the first electrode in a plan view.
The organic electroluminescence device according to claim 2. The power line layer is provided in an upper layer of the second electrode and the third electrode,
The second electrode is connected to the power supply line layer via a first conduction part, and the third electrode is connected to the power supply line layer via a second conduction part.
The organic electroluminescent device according to claim 3. An electrode connected to the gate of the first transistor;
The electrode is disposed below the third electrode, and is disposed at a position overlapping at least a part of the third electrode in plan view.
The organic electroluminescence device according to claim 4. An active layer is formed under the electrode,
Impurities are implanted into the active layer,
The organic electroluminescent device according to claim 5. An electrode connected to the gate of the first transistor;
The electrode is disposed below the second electrode, and is disposed at a position overlapping at least a part of the second electrode in plan view.
The organic electroluminescence device according to claim 1, wherein the organic electroluminescence device is any one of the above. An active layer is formed under the electrode,
Impurities are implanted into the active layer,
The organic electroluminescent device according to claim 7. The power line layer is formed in an upper layer of the first electrode, and is disposed at a position overlapping the first electrode in plan view.
The organic electroluminescence device according to claim 1, wherein the organic electroluminescence device is an organic electroluminescence device. The capacitive element and the first transistor are arranged so as to overlap in a plan view.
The organic electroluminescence device according to claim 1, wherein the organic electroluminescence device is any one of the above. In organic electroluminescence equipment,
Scanning lines;
A signal line;
A pixel circuit connected to the scanning line and the signal line;
With
The pixel circuit includes:
A first transistor having one current end connected to the power line layer;
An organic electroluminescence element that has a pixel electrode and emits light with a luminance corresponding to the magnitude of a current supplied through the first transistor;
A capacitive element having a first electrode connected to the gate of the first transistor, a second electrode, and a dielectric film provided between the first electrode and the second electrode;
The first electrode is formed in the same layer as the second electrode, and is disposed at a position away from the second electrode with the dielectric film interposed therebetween.
An organic electroluminescence device characterized by that. The power supply line layer is disposed between the first electrode and the signal line.
The organic electroluminescence device according to claim 11. The power supply line layer is disposed between the first electrode, the scanning line, and the signal line.
The organic electroluminescence device according to claim 11. The power supply line layer is disposed between the first electrode and the pixel electrode.
14. The organic electroluminescence device according to claim 11, wherein the organic electroluminescence device is any one of the above. A plurality of conduction holes penetrating each layer from a layer forming a current end of the first transistor to a layer on which the pixel electrode is formed; and a plurality of relay electrodes connected to each of the plurality of conduction holes. The other current end of the first transistor and the pixel electrode are connected by the plurality of conduction holes and the plurality of relay electrodes.
The organic electroluminescence device according to claim 11, wherein the organic electroluminescence device is any one of the above. The capacitive element and the first transistor are arranged so as to overlap in a plan view.
The organic electroluminescence device according to claim 1, wherein the organic electroluminescence device is any one of the above. A second transistor having one current terminal connected to the gate of the first transistor and the other current terminal connected to the signal line;
The signal line and the second transistor are arranged so as to overlap in a plan view.
The organic electroluminescence device according to any one of claims 11 to 16, wherein the organic electroluminescence device is any one of the above. A second transistor having one end connected to the gate of the first transistor and the other end connected to the signal line;
A third transistor in which one current terminal is connected to the other current terminal of the first transistor and the other current terminal is connected to the other current terminal of the second transistor;
The signal line and the third transistor are arranged so as to overlap in a plan view.
The organic electroluminescence device according to any one of claims 11 to 16, wherein the organic electroluminescence device is any one of the above. A fourth transistor having one current terminal connected to the other current terminal of the first transistor and the other current terminal connected to the pixel electrode;
The signal line and the fourth transistor are arranged so as to overlap in a plan view.
The organic electroluminescence device according to any one of claims 11 to 18, wherein the organic electroluminescence device is any one of the above.   An electronic apparatus comprising the organic electroluminescence device according to any one of claims 1 to 19.

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