JP2019054111A - Printed-wiring board and method for manufacturing printed-wiring board - Google Patents

Abstract

To reduce or avoid generation of a crack and a fracture in a second metal post 52 with a small bottom diameter.SOLUTION: A printed-wiring board 10 comprises a base insulation layer 24, a conductor layer 26 formed on the base insulation layer 24 and including a plurality of conductor pads, and a coating insulation layer 40 formed on the base insulation layer 24 and the conductor layer 26. The coating insulation layer 40 is formed with a first opening 40a and a second opening 40b having a smaller diameter than the first opening 40a. The plurality of conductor pads include a first conductor pad 44 exposed from the first opening 40a and a second conductor pad 46 formed on the same plane as the first conductor pad 44 and exposed from the second opening 40b. The printed-wiring board 10 further includes an intermediate layer 50 formed on the first conductor pad 44, a first metal post 48 formed on the intermediate layer 50 and having a first bottom diameter R1, and a second metal post 52 directly formed on the second conductor pad 46 and having a second bottom diameter R2 smaller than the first bottom diameter R1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a printed wiring board having a metal post and a method for manufacturing a printed wiring board having a metal post.

  Patent Document 1 discloses a substrate body having a conductor pad formed on the surface thereof, an intermediate layer formed on the conductor pad, and a covering insulation disposed on the substrate body and having an opening corresponding to the intermediate layer. A package substrate comprising a layer and a metal post formed on an intermediate layer is disclosed. The metal post is electrically connected to the conductor pad via the intermediate layer.

JP 2000-323613 A

  However, in the conventional package substrate described above, since the metal post and the intermediate layer are formed of different metals, the bonding strength between the metal post and the intermediate layer is weak, and if the metal post is formed with a small diameter, the metal post and the intermediate layer There may be a problem that a crack occurs or a metal post breaks starting from the boundary part.

  The printed wiring board according to the present invention includes a base insulating layer, a conductor layer including a plurality of conductor pads formed on the base insulating layer, and a covering insulation formed on the base insulating layer and the conductor layer. A first opening and a second opening having a smaller diameter than the first opening are formed in the covering insulating layer, and the plurality of conductor pads are formed from the first opening. An exposed first conductor pad and a second conductor pad formed on the same plane as the first conductor pad and exposed from the second opening are included, and are formed on the first conductor pad. An intermediate layer, a first metal post formed on the intermediate layer and having a first bottom diameter, and a second metal formed directly on the second conductor pad and smaller than the first bottom diameter. A second metal post having a bottom diameter of.

  The printed wiring board manufacturing method according to the present invention includes forming a base insulating layer, forming a conductor layer including a plurality of conductor pads on the base insulating layer, and forming the conductor insulating layer on the base insulating layer and the conductor. Forming a covering insulating layer on the layer; forming a first opening in the covering insulating layer to expose the first conductor pad included in the conductor layer; and on the first conductor pad. Forming an intermediate layer on the cover insulating layer, and forming a second opening having a smaller diameter than the first opening in the covering insulating layer, the conductor being located on the same plane as the first conductor pad Exposing a second conductor pad included in the layer; forming a first metal post having a first bottom diameter on the intermediate layer; and forming the first bottom on the second conductor pad. Second metal having a second bottom diameter smaller than the diameter It includes forming a strike directly, the.

Sectional drawing for demonstrating the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. Sectional drawing for demonstrating the modification of the printed wiring board of embodiment shown by FIG. Sectional drawing for demonstrating the printed wiring board of other embodiment of this invention. Sectional drawing for demonstrating the modification of the printed wiring board of embodiment shown by FIG.

  An embodiment of a printed wiring board of the present invention will be described with reference to the drawings. As shown in FIG. 1, the printed wiring board 10 of the present embodiment includes a core substrate 12, a first buildup layer 14 provided on the first surface side of the core substrate 12, and a first surface of the core substrate 12. And a second buildup layer 16 provided on the second surface side opposite to. The core substrate 12 is made of an insulating member. A first conductor circuit layer 18 is formed on the first surface of the core substrate 12. A second conductor circuit layer 20 is formed on the second surface of the core substrate 12. The first conductor circuit layer 18 and the second conductor circuit layer 20 are electrically connected by a through-hole conductor 22 that penetrates the core substrate 12. A resin filler 23 is filled inside the through-hole conductor 22. The first conductor circuit layer 18, the second conductor circuit layer 20, and the through-hole conductor 22 are made of a conductive metal such as copper.

  The first buildup layer 14 has at least one first resin insulating layer 24 and at least one first conductor layer 26 that are alternately stacked. In the illustrated example, six layers of first resin insulation layers 24 and six layers of first conductor layers 26 are provided. The number of layers of the first resin insulation layer 24 and the first conductor layer 26 is not limited to the illustrated example, and may be 5 layers or less or 7 layers or more. The first conductor layer 26 is made of a conductive metal such as copper. The 1st resin insulation layer 24 can be comprised with the resin composition etc. which contain inorganic fillers, such as a silica and an alumina, and an epoxy resin, for example. The first conductor layers 26 may be electrically connected to each other via a first via conductor 28. The first via conductor 28 may be formed of the same metal as the first conductor layer 26.

  Embedded in the first buildup layer 14 is an embedded substrate 32 having fine wiring and conductor pads 30 formed on the surface. The embedded substrate 32 can be formed of silicon, glass material, or organic material. In one example of use shown in the figure, the embedded substrate 32 electrically connects a plurality of semiconductor chips D1 and D2 that can be mounted close to each other on the surface of the printed wiring board 10. One of the semiconductor chips D1 and D2 electrically connected to each other can be a logic chip such as a central processing unit (CPU) or a graphic processing unit (GPU). The other semiconductor chip D2 can be a memory chip such as a dynamic access memory (DRAM), a static random access memory (SRAM), and a nonvolatile memory (NVM). The embedded substrate 32 is disposed at a position partially overlapping with the plurality of semiconductor chips D1 and D2 that are electrically connected to each other when viewed in the stacking direction of the first buildup layer 14.

  The second buildup layer 16 has at least one second resin insulation layer 34 and at least one second conductor layer 36 that are alternately stacked. In the illustrated example, six second resin insulation layers 34 and six second conductor layers 36 are provided. The number of layers of the second resin insulation layer 34 and the second conductor layer 36 is not limited to the illustrated example, and may be 5 layers or less or 7 layers or more. The second conductor layer 36 is made of a conductive metal such as copper. The 2nd resin insulation layer 34 consists of a resin composition containing inorganic fillers, such as a silica and an alumina, and an epoxy resin, for example. The second conductor layers 36 may be electrically connected to each other through a second via conductor 38. The second via conductor 38 may be formed of the same metal as the second conductor layer 36.

  The printed wiring board 10 is a first resin insulating layer (hereinafter referred to as a “first outermost resin insulating layer”) as a base insulating layer located farthest from the core substrate 12 among the plurality of first resin insulating layers 24. ) 24 and a first coating as a coating insulating layer on the first conductor layer 26 (hereinafter referred to as “first outermost conductor layer”) farthest from the core substrate 12 among the plurality of first conductor layers 26. An insulating layer (solder resist layer) 40 is provided. The printed wiring board 10 includes a plurality of second resin insulation layers 34, a second resin insulation layer furthest from the core substrate 12 (hereinafter referred to as “second outermost resin insulation layer”) 34, and a plurality of second conductors. A second covering insulating layer (solder resist layer) 42 is provided on a second conductor layer (hereinafter referred to as “second outermost conductor layer”) 36 farthest from the core substrate 12 among the layers 36.

  The first covering insulating layer 40 includes a first opening 40a that exposes a part of the first outermost conductor layer 26 as a first conductor pad 44, and a first outermost diameter that is smaller than the first opening 40a. A second opening 40 b that exposes another part of the conductor layer 26 as the second conductor pad 46 is formed. The second opening 40 b is formed at a position corresponding to the embedded substrate 32.

  A first metal post 48 having a first bottom diameter R1 is formed on the first conductor pad 44 exposed from the first opening 40a with an intermediate layer 50 interposed therebetween. The first metal post 48 is made of the same or the same metal as the first conductor pad 44 and is made of, for example, copper. In the illustrated example, the pitch of the first metal posts 48 matches the pitch of the relatively large-diameter bumps provided on the semiconductor chips D1 and D2. The first metal post 48 electrically connects the relatively large-diameter bumps of the semiconductor chips D <b> 1 and D <b> 2 and the first conductor pad 44 via the intermediate layer 50.

  The first metal post 48 is electrically connected to the first conductor pad 44 through an intermediate layer 50 formed on the first conductor pad 44. The intermediate layer 50 is made of a metal different from that of the first conductor pad 44. The intermediate layer 50 may include a nickel plating layer. This nickel plating layer may be an electroless nickel plating layer. The intermediate layer 50 can be, for example, a Ni / Pd / Au plating layer in which a nickel layer, a palladium layer, and a gold layer are stacked in this order. This Ni / Pd / Au plating layer can be an electroless Ni / Pd / Au plating layer.

  On the second conductor pad 46 exposed from the second opening 40b, the second metal post 52 having the second bottom diameter R2 smaller than the first bottom diameter R1 does not pass through the intermediate layer 50 described above. Directly formed. The second metal post 52 is made of the same or the same metal as the second conductor pad 46 and is made of, for example, copper. In the illustrated example, the pitch of the second metal posts 52 matches the pitch of the relatively small-diameter bumps provided on the semiconductor chips D1 and D2. The second metal post 52 directly and electrically connects the relatively small-diameter bumps of the semiconductor chips D1 and D2 and the second conductor pads 46.

  The ratio of the second bottom diameter R2 to the first bottom diameter R1 can be 0.2 or more and 0.9 or less. The top surface of the first metal post 48 preferably has a concave shape whose central portion is lower than the outer peripheral portion. The top surface of the second metal post 52 preferably has a convex shape in which the central portion is higher than the outer peripheral portion. The first metal post 48 and the second metal post 52 have a height protruding from the surface of the first covering insulating layer 40. The height of the first metal post 48 (height from the surface of the first covering insulating layer 40) and the height of the second metal post 52 (height from the surface of the first covering insulating layer 40) are substantially the same. It is preferable that

  The second covering insulating layer 42 is formed with a plurality of third openings 56 that exposes a part of the second outermost conductor layer 36 as third conductor pads 54. A covering metal layer 58 made of the same material as that of the intermediate layer 50 is formed on the surface of the third conductor pad 54.

  According to the printed wiring board 10 of the present embodiment, the second metal post 52 having a bottom diameter smaller than that of the first metal post 48 is directly formed on the second conductor pad 46 without the intermediate layer 50 interposed therebetween. Yes. Therefore, the occurrence of cracks and breaks in the second metal post 52 having a small bottom diameter can be reduced or avoided. In particular, when the second metal post 52 and the second conductor pad 46 are made of the same or the same metal, good bonding strength can be obtained between the second metal post 52 and the second conductor pad 46. Therefore, the occurrence of cracks and breaks as described above can be further reduced or avoided.

  An embodiment of a method for manufacturing the printed wiring board 10 shown in FIG. 1 will be described with reference to FIGS. 2A to 2U.

  As shown in FIG. 2A, a substrate 60 is prepared. The substrate 60 is not particularly limited. For example, a glass epoxy substrate, a bismaleimide-triazine (BT) resin substrate, a copper clad laminate, an insulating sheet with copper foil (RCC), or a ceramic such as an aluminum nitride substrate. A substrate, a silicon substrate, etc. are mentioned. 2A shows a double-sided copper-clad laminate in which copper foils 62 are laminated on both sides of an insulating substrate body 60A as the substrate 60. FIG.

  As shown in FIG. 2B, a plurality of through holes 61 penetrating the substrate 60 are formed using a drill. The through hole 61 can be formed using a laser.

  Thereafter, an electroless plating process and an electrolytic plating process are performed, and the through-hole conductor 22 is formed on the side wall of the through-hole 61. At the same time, a conductive film 63 composed of an electroless plating layer and an electrolytic plating layer is formed on the surface of the copper foil 62. In the embodiment, the through hole 61 is not filled with a metal, and the printed wiring board 10 of the embodiment has a through hole conductor through hole 22 a inside the through hole conductor 22.

  A roughened surface is formed on the surface of the through-hole conductor 22 (not shown).

  As shown in FIG. 2C, a resin filler 23 containing inorganic particles such as glass having an average particle diameter of, for example, 3 μm to 5 μm is filled in the through-hole conductor through-hole 22a, and dried and cured.

  Thereafter, a palladium catalyst is applied to the surface of the substrate 60 and electroless copper plating is performed, whereby an electroless copper plating film is formed. And electrolytic copper plating is given and an electrolytic copper plating film is formed. Thereby, a plating film 64 composed of an electroless copper plating film and an electrolytic copper plating film is formed on the conductive film 63. At the same time, the plating film 64 covers the through hose conductor 22 and the resin filler 23.

  A commercially available dry film is attached to the surface of the substrate 60 having the plating film 64. Thereafter, an etching resist (not shown) is formed on the plating film 64 by photolithography. Then, the plating film 64, the conductive film 63, and the copper foil 62 exposed from the etching resist are dissolved and removed by the etching solution. The etching resist is then removed. A first conductor circuit layer 18 and a second conductor circuit layer 20 are formed. And the surface of the 1st conductor circuit layer 18 and the 2nd conductor circuit layer 20 is roughened, and a roughened surface is formed (not shown). The core substrate 12 is completed. The through hole 61 may be filled with metal.

  As shown in FIG. 2F, a build-up insulating resin including an inorganic filler such as silica or alumina and an epoxy resin as the first resin insulating layer 24 on the first conductor circuit layer 18 of the core substrate 12. The film 65 is laminated, and the same build-up insulating resin film 65 is laminated as the second resin insulating layer 34 on the second conductor circuit layer 20 of the core substrate 12. At that time, the portion between the circuit portions in the first conductor circuit layer 18 and the portion between the circuit portions in the second conductor circuit layer 20 are filled with the insulating resin film 65. The insulating resin film 65 is thermoset. The first resin insulation layer 24 is formed on the first surface side of the core substrate 12, and the second resin insulation layer 34 is formed on the second surface side of the core substrate 12.

  As shown in FIG. 2G, the first resin insulation layer 24 and the second resin insulation layer 34 on both sides of the core substrate 12 are irradiated with a carbon dioxide laser, a UV-YAG laser, or the like to form a plurality of via holes 66. The

  An electroless plating process such as an electroless copper plating process is performed, and an electroless plating film (not shown) is formed on the resin insulation layers 24 and 34 on both sides of the core substrate 12 and in the via hole 66. .

  As shown in FIG. 2H, a plating resist 67 having a predetermined pattern is formed on the electroless plating films on the resin insulating layers 24 and 34 on both sides of the core substrate 12.

  As shown in FIG. 2I, an electrolytic plating process is performed, and the plating is filled in the via hole 66 to form the first via conductor 28 and the second via conductor 38. In addition, an electrolytic plating film 69 is formed on portions exposed from the plating resist 67 in the electroless plating films (not shown) on the resin insulating layers 24 and 34 on both sides of the core substrate 12.

  As shown in FIG. 2J, the plating resist 67 is peeled off, the electroless plating film (not shown) below the plating resist is removed, and the remaining electrolytic plating film 69 and electroless plating film are used to A first conductor layer 26 is formed on the first resin insulation layer 24, and a second conductor layer 36 is formed on the second resin insulation layer 34.

  By repeating the steps of FIGS. 2F to 2J, as shown in FIG. 2K, five first resin insulation layers 24 and five first conductor layers 26 are alternately stacked and five layers. The second resin insulation layers 34 and the five second conductor layers 36 are alternately laminated. Of the five first resin insulation layers 24, the first resin insulation layer 24 located farthest from the core substrate 12 has a buried substrate hole 71 larger than the via hole 66 described with reference to FIG. It is formed by a carbon dioxide laser or a UV-YAG laser. A planar conductor pattern which is a part of the first conductor layer 26 is exposed on the bottom surface of the embedded substrate hole 71.

  As shown in FIG. 2L, a buried substrate prepared in advance is embedded in a buried substrate hole 71 formed in the first resin insulating layer 24 located farthest from the core substrate 12 among the five first resin insulating layers 24. A substrate 32 is disposed. On the embedded substrate 32, fine wirings and conductor pads 30 are formed.

  As shown in FIG. 2M, on the first conductor layer 26 located farthest from the core substrate 12 among the five first conductor layers 26, as the first outermost resin insulation layer 24, for example, silica or alumina. A build-up insulating resin film 65 containing an inorganic filler such as an epoxy resin is laminated on the second conductor layer 36 farthest from the core substrate 12 among the five second conductor layers 36. The same build-up insulating resin film 65 is laminated as the second outermost resin insulating layer 34, and is heated and pressed. At that time, between the circuit portion in the first conductor circuit layer 18, between the circuit portion in the second conductor circuit layer 20, the gap between the embedded substrate hole 71 and the embedded substrate 32, and between the conductor pads 30 of the embedded substrate 32. And filled with an insulating resin film 65.

  2G to 2J, as shown in FIG. 2N, the first via conductor 28 and the first outermost conductor are formed on the first conductor layer 26 that is the fifth layer from the core substrate 12 side. The first conductor layer 26 as the conductor layer 26 is formed, and the second via conductor 38 and the second outermost conductor layer 36 are formed on the second conductor layer 36 that is the fifth layer from the core substrate 12 side. A second conductor layer 36 is formed.

  As shown in FIG. 2O, the first covering insulating layer 40 is laminated on the first outermost resin insulating layer 24 and the first outermost conductor layer 26 as the base insulating layer. A second covering insulating layer 42 is laminated on the second outermost resin insulating layer 34 and the second outermost conductor layer 36.

  As shown in FIG. 2P, a first opening 40a that exposes a part of the first outermost conductor layer 26 as a first conductor pad 44 is formed in the first covering insulating layer 40 by exposure and development. . Further, a third opening 56 that exposes a part of the second outermost conductor layer 36 as a third conductor pad 54 is formed in the second covering insulating layer 42 by exposure and development.

  As shown in FIG. 2Q, for example, a nickel layer, a palladium layer, and a gold layer are stacked in this order on the first conductor pad 44 exposed from the first opening 40a of the first covering insulating layer 40, and the intermediate layer 50 is stacked. And a covering metal layer 58 made of the same material as the intermediate layer 50 is formed on the third conductor pad 54 exposed from the third opening 56 of the second covering insulating layer 42. The intermediate layer 50 and the covering metal layer 58 can be formed simultaneously.

  As shown in FIG. 2R, the first covering insulating layer 40 is irradiated with, for example, a carbon dioxide laser or a UV-YAG laser, so that a part of the first outermost conductor layer 26 is smaller in diameter than the first opening 40a. A second opening 40b exposed as the second conductor pad 46 is formed.

  An electroless plating process such as an electroless copper plating process is performed, and an electroless plating film (not shown) is formed on the first covering insulating layer 40, in the first opening 40a, and in the second opening 40b. Is done.

  As shown in FIG. 2S, a predetermined pattern of plating resist 73 is formed on the electroless plating film on the first covering insulating layer 40, and a plating resist 74 is formed on the entire surface of the second covering insulating layer 42. Is done.

  As shown in FIG. 2T, an electrolytic plating process, for example, an electrolytic copper plating process is performed, and the plating is filled in the first opening 40a, so that the first outermost conductor layer 26 has a first conductor pad 44 on it. A first metal post 48 is formed through the intermediate layer 50, and plating is filled into the second opening 40b, and the second metal pad 48 is formed on the second conductor pad 46 of the first outermost conductor layer 26. Metal posts 52 are formed directly. The first metal post 48 has a first bottom diameter R1, and the second post has a second bottom diameter R2 that is smaller than the first bottom diameter R1 (see FIG. 1). The ratio of the second bottom diameter R2 to the first bottom diameter R1 can be 0.2 or more and 0.9 or less. The top surface of the first metal post 48 is preferably formed so that the central portion has a concave shape lower than the outer peripheral portion. On the other hand, the top surface of the second metal post 52 is preferably formed so that the central portion has a convex shape higher than the outer peripheral portion. Both the first and second metal posts 52 preferably have a height that protrudes from the surface of the first covering insulating layer 40. The height of the first metal post 48 (height from the surface of the first covering insulating layer 40) and the height of the second metal post 52 (height from the surface of the first covering insulating layer 40) are approximately. It is preferable to form the same.

  As shown in FIG. 2U, the plating resists 73 and 74 are peeled off, and the electroless plating film (not shown) below the plating resists 73 and 74 is removed. Thus, the printed wiring board 10 is completed.

  According to the method for manufacturing the printed wiring board 10 of the present embodiment, it is possible to easily manufacture the printed wiring board 10 that can reduce or avoid the occurrence of cracks and breaks in the second metal post 52 having a small bottom diameter. it can. In particular, when the second metal post 52 and the second conductor pad 46 are made of the same or the same metal, good bonding strength can be obtained between the second metal post 52 and the second conductor pad 46. Therefore, the occurrence of cracks and breaks as described above can be further reduced or avoided.

  A modification of the printed wiring board 10 shown in FIG. 1 will be described with reference to FIG.

  In the printed wiring board 10 shown in FIG. 1, the second metal post 52 is formed on the second conductor pad 46 of the first outermost conductor layer 26, but the modified example shown in FIG. 3 is printed. In the wiring board 10, the second metal post 52 is directly formed on the conductor pad 30 on the embedded substrate 32. Since the conductor pads 30 on the embedded substrate 32 are on the same plane as the first conductor pads 44 of the first outermost conductor layer 26, they correspond to the “second conductor pads” in the present invention. Since the other structure of the printed wiring board 10 is the same as the printed wiring board 10 shown in FIG. 1, detailed description is abbreviate | omitted. The printed wiring board 10 can be manufactured by a method similar to the manufacturing method described with reference to FIGS. 2A to 2U.

  According to the printed wiring board 10 according to this modification, the second metal post 52 having a bottom diameter smaller than that of the first metal post 48 includes the intermediate layer 50 as in the printed wiring board 10 shown in FIG. It is directly formed on the second conductor pad 30 of the embedded substrate 32 without intervention. Therefore, the occurrence of cracks and breaks in the second metal post 52 having a small bottom diameter can be reduced or avoided. In particular, when the second metal post 52 and the second conductor pad 30 on the embedded substrate 32 are made of the same or the same metal, the second metal post 52 and the second conductor pad 46 are good. Therefore, the occurrence of cracks and breaks as described above can be further reduced or avoided.

  With reference to FIG. 4, the printed wiring board 80 of other embodiment of this invention is demonstrated.

  The printed wiring board 80 shown in FIG. 4 is a printed wiring board having a coreless structure that does not have a core substrate. The printed wiring board 80 includes a plurality of conductor layers 82 and an interlayer resin insulation layer 84 disposed between the conductor layers 82. In the illustrated example, three conductor layers 82 and two interlayer resin insulation layers 84 disposed between the conductor layers 82 are provided, but the number of conductor layers 82 and interlayer resin insulation layers 84 is limited to this. Not. The conductor layer 82 can be formed from a metal such as copper. The interlayer resin insulation layer 84 can be formed from a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin, for example.

  The conductor layers 82 may be connected to each other via via conductors 86. Via conductor 86 may be formed of the same metal as conductor layer 82.

  Embedded in the interlayer resin insulation layer 84 is an embedded substrate 88 with fine wiring and conductor pads formed on the surface. The embedded substrate 88 can be formed of silicon, glass material, or organic material. In the illustrated example, the embedded substrate 88 electrically connects a plurality of semiconductor chips D1, D2 that can be mounted close to each other on the surface of the printed wiring board 80. One of the semiconductor chips D1 and D2 electrically connected to each other can be a logic chip such as a central processing unit (CPU) or a graphic processing unit (GPU). The other semiconductor chip D2 can be a memory chip such as a dynamic access memory (DRAM), a static random access memory (SRAM), and a nonvolatile memory (NVM). The embedded substrate 88 is disposed at a position that partially overlaps the plurality of semiconductor chips D1 and D2 that are electrically connected to each other when viewed in the stacking direction of the conductor layer 82 and the interlayer resin insulating layer 84.

  The printed wiring board 80 is also provided with a coating insulating layer (solder resist layer) 90 on the interlayer resin insulating layer 84 and the conductor layer 82 as the base insulating layer located at the outermost position in the laminating direction.

  The covering insulating layer 90 includes a first opening 90a that exposes a part of the conductor layer 82 as a first conductor pad 82a, and another part of the conductor layer 82 that is smaller in diameter than the first opening 90a. A second opening 90b is formed to be exposed as the second conductor pad 82b. The second opening 90 b is formed at a position corresponding to the embedded substrate 88.

  On the first conductor pad 82a exposed from the first opening 90a, a first metal post 92 having a first bottom diameter R1 is formed via an intermediate layer 94. The first metal post 92 is made of the same or the same metal as the first conductor pad 82a and is made of, for example, copper. In the illustrated example, the pitch of the first metal posts 92 matches the pitch of the relatively large-diameter bumps provided on the semiconductor chips D1 and D2. The first metal post 92 electrically connects the relatively large-diameter bumps of the semiconductor chips D1 and D2 and the first conductor pad 82a via the intermediate layer 94.

  The first metal post 92 is electrically connected to the first conductor pad 82a through an intermediate layer 94 formed on the first conductor pad 82a. The intermediate layer 94 is made of a metal different from that of the first conductor pad 82a. The intermediate layer 94 may include a nickel plating layer. This nickel plating layer may be an electroless nickel plating layer. The intermediate layer 94 can be, for example, a Ni / Pd / Au plating layer in which a nickel layer, a palladium layer, and a gold layer are laminated in this order. This Ni / Pd / Au plating layer can be an electroless Ni / Pd / Au plating layer.

  On the second conductor pad 82b exposed from the second opening 90b, the second metal post 96 having the second bottom diameter R2 smaller than the first bottom diameter R1 does not pass through the intermediate layer 94 described above. Directly formed. The second metal post 96 is made of the same or the same metal as the second conductor pad 82b, and is made of, for example, copper. In the illustrated example, the pitch of the second metal posts 96 matches the pitch of the relatively small-diameter bumps provided on the semiconductor chips D1 and D2. The second metal post 96 directly and electrically connects the relatively small-diameter bumps of the semiconductor chips D1 and D2 and the second conductor pads 82b.

  The ratio of the second bottom diameter R2 to the first bottom diameter R1 can be 0.2 or more and 0.9 or less. The top surface of the first metal post 92 preferably has a concave shape whose central portion is lower than the outer peripheral portion. It is preferable that the top surface of the second metal post 96 has a convex shape in which the central portion is higher than the outer peripheral portion. The first metal post 92 and the second metal post 96 have a height protruding from the surface of the covering insulating layer 90. The height of the first metal post 92 (height from the surface of the insulating cover layer 90) and the height of the second metal post 96 (height from the surface of the insulating cover layer 90) are substantially the same. preferable.

  According to the printed wiring board 80 of the present embodiment, the second metal post 96 having a bottom diameter smaller than that of the first metal post 92 is formed directly on the second conductor pad 82b without the intermediate layer 94 interposed therebetween. Yes. Accordingly, the occurrence of cracks and breaks in the second metal post 96 having a small bottom diameter can be reduced or avoided. In particular, when the second metal post 96 and the second conductor pad 82b are made of the same type or the same metal, good bonding strength can be obtained between the second metal post 96 and the second conductor pad 82b. Therefore, the occurrence of cracks and breaks as described above can be further reduced or avoided.

  The printed wiring board 80 according to the present embodiment is similarly obtained by using a support plate (not shown) instead of the core substrate 12 in the method for manufacturing the printed wiring board 10 described with reference to FIGS. 2A to 2U. Can be manufactured. The conductor layers 82 and the interlayer resin insulation layers 84 can be alternately stacked on the support plate. The printed wiring board 80 manufactured on the support plate or its intermediate body can be finally peeled off from the support plate. For the support plate, for example, a metal plate, a copper-clad laminate, or a double-sided copper-clad laminate can be used.

  A modification of the printed wiring board 80 shown in FIG. 4 will be described with reference to FIG. The same members or elements are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  In the printed wiring board 80 shown in FIG. 4, the second metal post 96 is formed on the second conductor pad 82b of the conductor layer 82. However, in the printed wiring board 80 of the modification shown in FIG. The second metal post 96 is directly formed on the conductor pad 88 a on the embedded substrate 88. Since the conductor pad 88a on the embedded substrate 88 is on the same plane as the first conductor pad 82a of the conductor layer 82, it corresponds to the “second conductor pad” in the present invention. The other configuration of the printed wiring board 80 is the same as that of the printed wiring board 80 shown in FIG.

  According to the printed wiring board 80 according to this modification, like the printed wiring board 80 shown in FIG. 4, the second metal post 96 having a bottom diameter smaller than that of the first metal post 92 includes the intermediate layer 94. It is directly formed on the second conductor pad 88a of the embedded substrate 88 without being interposed. Accordingly, the occurrence of cracks and breaks in the second metal post 96 having a small bottom diameter can be reduced or avoided. In particular, when the second metal post 96 and the second conductor pad 88a on the embedded substrate 88 are made of the same or the same metal, the second metal post 96 and the second conductor pad 88a are good. Therefore, the occurrence of cracks and breaks as described above can be further reduced or avoided.

DESCRIPTION OF SYMBOLS 10,80 Printed wiring board 12 Core board 14 1st buildup layer 16 2nd buildup layer 18 1st conductor circuit layer 20 2nd conductor circuit layer 22 Through-hole conductor 23 Resin filler 24 1st resin insulation layer 26 1st Conductor layer 28 First via conductor 30 Conductor pad 32, 88 Embedded substrate 34 Second resin insulation layer 36 Second conductor layer 38 Second via conductor 40 First covering insulation layer 40a, 90a First opening 40b, 90b Second Opening 42 Second covering insulating layer 44, 82a First conductor pad 46, 82b, 88a Second conductor pad 48, 92 First metal post 50, 94 Intermediate layer 52, 96 Second metal post 54 Third Conductor pad 56 Third opening 58 Covered metal layer 82 Conductor layer 84 Interlayer resin insulation layer 86 Via conductor R1 First bottom diameter R2 Second bottom diameter

Claims (17)

A printed wiring board,
A base insulating layer;
A conductor layer including a plurality of conductor pads formed on the base insulating layer;
A covering insulating layer formed on the base insulating layer and the conductor layer, and
The covering insulating layer is formed with a first opening and a second opening having a smaller diameter than the first opening,
The plurality of conductor pads include a first conductor pad exposed from the first opening, a second conductor pad formed on the same plane as the first conductor pad, and exposed from the second opening; Contains
An intermediate layer formed on the first conductor pad;
A first metal post formed on the intermediate layer and having a first bottom diameter;
And a second metal post formed directly on the second conductor pad and having a second bottom diameter smaller than the first bottom diameter.   2. The printed wiring board according to claim 1, wherein the first metal post, the second metal post, the first conductor pad, and the second conductor pad are made of the same kind of metal.   3. The printed wiring board according to claim 2, wherein the first metal post, the second metal post, the first conductor pad, and the second conductor pad are made of copper.   The printed wiring board according to claim 1, wherein the intermediate layer includes an electroless nickel plating layer.   2. The printed wiring board according to claim 1, wherein a ratio of the second bottom diameter to the first bottom diameter is 0.2 or more and 0.9 or less.   2. The printed wiring board according to claim 1, wherein the top surface of the first metal post has a concave shape whose central portion is lower than the outer peripheral portion.   2. The printed wiring board according to claim 1, wherein the top surface of the second metal post has a convex shape whose central portion is higher than the outer peripheral portion.   The printed wiring board according to claim 1, wherein a height of the first metal post and a height of the second metal post are substantially the same. A method of manufacturing a printed wiring board,
Forming a base insulating layer;
Forming a conductor layer including a plurality of conductor pads on the base insulating layer;
Forming a covering insulating layer on the base insulating layer and the conductor layer;
Forming a first opening in the covering insulating layer to expose a first conductor pad included in the conductor layer;
Forming an intermediate layer on the first conductor pad;
A second conductor pad included in the conductor layer is formed on the same surface as the first conductor pad by forming a second opening having a smaller diameter than the first opening in the covering insulating layer. Exposing
Forming a first metal post having a first bottom diameter on the intermediate layer and having a second bottom diameter smaller than the first bottom diameter on the second conductor pad; Forming the post directly.   10. The method for manufacturing a printed wiring board according to claim 9, wherein the first metal post, the second metal post, the first conductor pad, and the second conductor pad are made of the same kind of metal. .   11. The method for manufacturing a printed wiring board according to claim 10, wherein the first metal post, the second metal post, the first conductor pad, and the second conductor pad are made of copper.   The method for manufacturing a printed wiring board according to claim 9, wherein the intermediate layer includes an electroless nickel plating layer.   10. The method for manufacturing a printed wiring board according to claim 9, wherein a ratio of the second bottom diameter to the first bottom diameter is 0.2 or more and 0.9 or less.   10. The method for manufacturing a printed wiring board according to claim 9, wherein a top surface of the first metal post has a concave shape in which a central portion is lower than an outer peripheral portion.   10. The method for manufacturing a printed wiring board according to claim 9, wherein the top surface of the second metal post has a convex shape in which a central portion is higher than an outer peripheral portion.   The method for manufacturing a printed wiring board according to claim 9, wherein a height of the first metal post and a height of the second metal post are substantially the same.   10. The method for manufacturing a printed wiring board according to claim 9, wherein the first opening is formed by exposure / development, and then the second opening is formed by laser irradiation.

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