JP2019051249A5

JP2019051249A5 -

Info

Publication number: JP2019051249A5
Application number: JP2017179222A
Authority: JP
Filing date: 2017-09-19
Publication date: 2020-09-03
Anticipated expiration: 2037-09-19

Description

また、従来、上記構成の遊技機において、ソフトウエアによるタイマー減算処理で制御される遊技機が知られている（例えば、特許文献１参照）。 Further, conventionally, in a gaming machine having the above configuration, a gaming machine controlled by a timer subtraction process by software is known (see, for example, Patent Document 1) .

特開２００４−０４１２６１号公報Japanese Unexamined Patent Publication No. 2004-041261

ところで、従来、上述した遊技機特有の制限として、主制御回路のプログラム容量が、規則により小容量に制限されている。さらに、近年、遊技性の複雑化により主制御回路のＲＯＭの容量が圧迫されており、主制御回路で管理する処理プログラムやテーブルなどの容量削減が求められている。 By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit .

本発明は、上記課題を解決するためになされたものであり、本発明の目的は、主制御回路で管理する処理プログラムやテーブルなどの容量を削減して主制御回路のＲＯＭの空き容量を増やし、該増えた容量分のＲＯＭの空き領域を利用して遊技性を高めることが可能な遊技機を提供することである。 The present invention has been made to solve the above problems, and an object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to increase the free space of the ROM of the main control circuit. The present invention is to provide a gaming machine capable of enhancing game playability by utilizing the free area of the ROM corresponding to the increased capacity .

遊技動作を制御するための演算処理を行う演算処理手段（例えば、後述のメインＣＰＵ１０１）と、
前記演算処理手段による前記演算処理の実行に必要な情報が記憶された第１記憶手段（例えば、後述のメインＲＯＭ１０２）と、
前記演算処理手段による前記演算処理の実行に必要な情報が記憶される第２記憶手段（例えば、後述のメインＲＡＭ１０３）と、
前記演算処理手段により制御され、役に応じた操作手順を示す特定の指示情報を報知する第１報知手段（例えば、後述の指示モニタ）と、
前記演算処理手段から送信された前記特定の指示情報を受信可能な演出制御手段（例えば、後述の副制御回路２００）と、
前記演出制御手段により制御され、前記特定の指示情報に応じた演出を行う第２報知手段（例えば、後述の表示装置１１）と、を備え、
前記演算処理手段は、
２バイトのソフトタイマーのタイマー値の計数処理（例えば、後述のタイマー更新処理）において、
更新命令、下限判定命令及び判断分岐命令を一つの命令で実行可能な所定の更新命令（例えば、後述の「ＤＣＰＷＬＤ」命令）を実行することにより、現在の前記ソフトタイマーのタイマー値と前記タイマー値の下限値とを比較するとともに、現在の前記ソフトタイマーのタイマー値が前記下限値より大きければ、前記ソフトタイマーのタイマー値を減算更新し、現在の前記ソフトタイマーのタイマー値が前記下限値以下であれば、前記ソフトタイマーのタイマー値を前記下限値に保持し、
その後、前記第２記憶手段内の前記ソフトタイマーの更新開始アドレスを２バイト分更新し、
前記第１記憶手段には、第１の記憶領域（例えば、後述の遊技用ＲＯＭ領域）及び第２の記憶領域（例えば、後述の規定外ＲＯＭ領域）が設けられ、
前記第１の記憶領域には、前記計数処理を実行するためのプログラムが記憶され、
前記第２の記憶領域には、試験に用いられる信号を制御するためのプログラム（例えば、後述の特賞信号制御処理）、及び、再遊技中であるか否かを示す信号を制御する条件装置信号制御処理を実行するためのプログラムが記憶される
ことを特徴とする遊技機。 An arithmetic processing means (for example, the main CPU 101 described later) that performs arithmetic processing for controlling game operations, and
A first storage means (for example, a main ROM 102 described later) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, the main RAM 103 described later) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A first notification means (for example, an instruction monitor described later) that is controlled by the arithmetic processing means and notifies specific instruction information indicating an operation procedure according to a combination, and
An effect control means (for example, a sub-control circuit 200 described later) capable of receiving the specific instruction information transmitted from the arithmetic processing means, and
A second notification means (for example, a display device 11 described later) , which is controlled by the effect control means and performs an effect according to the specific instruction information , is provided.
The arithmetic processing means
In the timer value counting process of a 2-byte soft timer (for example, the timer update process described later),
By executing a predetermined update instruction (for example, the "DCPWLD" instruction described later) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer value of the soft timer and the timer value If the current timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and the current timer value of the soft timer is equal to or less than the lower limit value. If there is, the timer value of the soft timer is held at the lower limit value,
After that, the update start address of the soft timer in the second storage means is updated by 2 bytes.
The first storage means is provided with a first storage area (for example, a gaming ROM area described later) and a second storage area (for example, a non-standard ROM area described later).
A program for executing the counting process is stored in the first storage area.
In the second storage area, a program for controlling the signal used in the test (for example, a special prize signal control process described later) and a condition device signal for controlling a signal indicating whether or not the game is being replayed A gaming machine characterized in that a program for executing a control process is stored .

上記構成の本発明の遊技機によれば、主制御回路で管理する処理プログラムやテーブルなどの容量を削減して主制御回路のＲＯＭ（第１記憶手段）の空き容量を増やし、該増えた容量分のＲＯＭの空き領域を利用して遊技性を高めることができる。 According to the gaming machine of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute .

次いで、メインＣＰＵ１０１は、２バイトタイマー値とその下限値「０」とを比較し、２バイトタイマー値が下限値「０」より大きい場合には、２バイトタイマー値を１減算（−１更新）し、２バイトタイマー値が下限値「０」以下である場合には、２バイトタイマー値を「０」に保持する（Ｓ９５２）。さらに、Ｓ９５２の処理では、メインＣＰＵ１０１は、ＨＬレジスタにセットされている２バイトタイマー格納領域の更新開始アドレスを２減算（−２更新）する。 Then, the main CPU101 compares the 2-byte timer value and the lower limit value "0", if 2-byte timer value lower limit value greater than "0", 1 subtracts 2 byte timer value (-1 updated) When the 2-byte timer value is equal to or less than the lower limit value "0", the 2-byte timer value is held at "0" (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 updates) the update start address of the 2-byte timer storage area set in the HL register.

次いで、メインＣＰＵ１０１は、１バイトタイマー値とその下限値「０」とを比較し、１バイトタイマー値が下限値「０」より大きい場合には、１バイトタイマー値を１減算（−１更新）し、１バイトタイマー値が下限値「０」以下である場合には、１バイトタイマー値を「０」に保持する（Ｓ９５６）。さらに、Ｓ９５６の処理では、メインＣＰＵ１０１は、ＨＬレジスタにセットされている１バイトタイマー格納領域の更新開始アドレスを１減算（−１更新）する。 Then, the main CPU101 compares the 1 byte timer value and the lower limit value "0", 1 byte timer value lower limit value is larger than "0", 1 is subtracted (-1 updated) one byte timer value When the 1-byte timer value is equal to or less than the lower limit value “0”, the 1-byte timer value is held at “0” (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

それゆえ、図１６５中のソースコード「ＤＣＰＷＬＤ（ＨＬ），０」では、ＨＬレジスタで指定されたアドレスから２バイト分のメモリの内容（２バイトタイマー値）と整数「０」（下限値）とが比較され、２バイト分のメモリの内容が整数「０」より大きい場合には、２バイト分のメモリの内容が１減算され、２バイト分のメモリの内容が整数「０」以下である場合には、２バイト分のメモリの内容に「０」がセットされる。すなわち、現時点の２バイトタイマー値が「０」より大きい場合には、２バイトタイマーの更新処理が行われ、現時点の２バイトタイマー値が「０」以下であれば、２バイトタイマー値が「０」に保持される。 Therefore, in the source code "DCPWLD (HL), 0" in FIG. 165, the contents of the memory for 2 bytes (2-byte timer value ) and the integer "0" (lower limit value) from the address specified by the HL register. When the contents of the memory for 2 bytes are larger than the integer "0", the contents of the memory for 2 bytes are subtracted by 1, and the contents of the memory for 2 bytes are equal to or less than the integer "0". Is set to "0" in the contents of the memory for 2 bytes. That is, if the current 2-byte timer value is larger than "0", the 2-byte timer is updated, and if the current 2-byte timer value is "0" or less, the 2-byte timer value is "0". Is held in.

上述のように、本実施形態のタイマー更新処理では、メインＣＰＵ１０１専用命令コードである「ＤＣＰＷＬＤ」命令により、タイマー値の更新（減算）処理及びタイマー値を「０」に保持する処理の両方を実行することができる。この場合、両処理を別個に実行するための命令コードを設ける必要がなくなる。また、タイマー値が「０」であるか否かを判別するための判断分岐命令コードも省略することができる。それゆえ、本実施形態では、ソースプログラムの容量（メインＲＯＭ１０２の使用容量）を低減することができ、メインＲＯＭ１０２において、空き容量を確保する（増大させる）ことができ、増えた空き容量を活用して、遊技性を高めることが可能になる。なお、本実施形態では、２バイトタイマーの更新処理においてのみ「ＤＣＰＷＬＤ」命令を使用する例を説明したが、本発明はこれに限定されず、１バイトタイマーの更新処理においても「ＤＣＰＷＬＤ」命令を使用してもよい。 As described above, in the timer update process of the present embodiment, both the timer value update (subtraction) process and the timer value holding process are executed by the "DCPWLD" instruction, which is the main CPU 101 dedicated instruction code. can do. In this case, it is not necessary to provide an instruction code for executing both processes separately. Further, the determination branch instruction code for determining whether or not the timer value is "0" can be omitted. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. In the present embodiment, an example in which the "DCPWLD" instruction is used only in the update process of the 2-byte timer has been described, but the present invention is not limited to this, and the "DCWPLD" instruction is also used in the update process of the 1-byte timer. You may use it.

タイマー更新処理において、「ＤＣＰＷＬＤ」命令を実行した場合、上述のように、タイマー値（２バイトタイマー値）の更新（減算）処理及びタイマー値を「０」に保持する処理の両方を実行することができる。この場合、両処理を別個に実行するための命令コードを設ける必要がなくなる。それゆえ、本実施形態では、ソースプログラムの容量（メインＲＯＭ１０２の使用容量）を低減することができ、メインＲＯＭ１０２において、空き容量を確保する（増大させる）ことができ、増えた空き容量を活用して、遊技性を高めることができる。 When the "DCPWLD" command is executed in the timer update process, both the update (subtraction) process of the timer value (2-byte timer value ) and the process of holding the timer value at "0" are executed as described above. Can be done. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

遊技動作を制御するための演算処理を行う演算処理手段（例えば、メインＣＰＵ１０１）と、
前記演算処理手段による前記演算処理の実行に必要な情報が記憶された第１記憶手段（例えば、メインＲＯＭ１０２）と、
前記演算処理手段による前記演算処理の実行に必要な情報が記憶される第２記憶手段（例えば、メインＲＡＭ１０３）と、を備え、
前記演算処理手段は、
ソフトタイマーのタイマー値の計数処理（例えば、タイマー更新処理）において、
更新命令、下限判定命令及び判断分岐命令を一つの命令で実行可能な所定の更新命令（例えば、「ＤＣＰＷＬＤ」命令）を実行することにより、現在の前記ソフトタイマーのタイマー値と前記タイマー値の下限値とを比較するとともに、現在の前記ソフトタイマーのタイマー値が前記下限値より大きければ、前記ソフトタイマーのタイマー値を減算更新し、現在の前記ソフトタイマーのタイマー値が前記下限値以下であれば、前記ソフトタイマーのタイマー値を前記下限値に保持する
ことを特徴とする遊技機。 Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the calculation process by the calculation processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
In the timer value counting process of the soft timer (for example, timer update process)
By executing a predetermined update instruction (for example, "DCPWLD" instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer value of the soft timer and the lower limit of the timer value are executed. as well as with the value, if the timer value of the current of the soft timer is greater than the lower limit, the timer value of the soft timer is subtracted update, if the timer value of the current of the soft timer is less than the lower limit value , A gaming machine characterized in that the timer value of the soft timer is held at the lower limit value.

また、前記本発明の第１０の遊技機では、前記演算処理手段は、一定の周期で処理を行う定周期処理手段（例えば、１．１１７２ｍｓｅｃ周期で繰り返し実行される割込処理）を有し、
前記ソフトタイマーによる前記タイマー値の計数処理は、前記定周期処理手段により実行され、
前記定周期処理手段が処理を行う周期と前記タイマー値とに基づいて、前記ソフトタイマーの経過時間が決定されるようにしてもよい。 Further, in the tenth gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle.
The timer value counting process by the soft timer is executed by the fixed cycle processing means.
The elapsed time of the soft timer may be determined based on the cycle in which the constant cycle processing means performs processing and the timer value .

Claims

Arithmetic processing means that performs arithmetic processing to control game operations,
A first storage means in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means for storing information necessary for executing the arithmetic processing by the arithmetic processing means, and
A first notifying means, which is controlled by the arithmetic processing means and notifies specific instruction information indicating an operation procedure according to a combination,
An effect control means capable of receiving the specific instruction information transmitted from the arithmetic processing means, and
A second notification means , which is controlled by the effect control means and performs an effect according to the specific instruction information , is provided.
The arithmetic processing means
In the timer value counting process of the 2-byte soft timer
By executing a predetermined update instruction that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer value of the soft timer is compared with the lower limit value of the timer value, and the present If the timer value of the soft timer is larger than the lower limit value, the timer value of the soft timer is subtracted and updated, and if the current timer value of the soft timer is equal to or less than the lower limit value, the timer value of the soft timer is set. Hold at the lower limit and
After that, the update start address of the soft timer in the second storage means is updated by 2 bytes.
The first storage means is provided with a first storage area and a second storage area.
A program for executing the counting process is stored in the first storage area.
In the second storage area, a program for controlling the signal used for the test and a program for executing the condition device signal control process for controlling the signal indicating whether or not the game is being replayed are stored. gaming machine characterized in that it is.