JP2019050062A - Image processing apparatus and method for controlling the same, and program - Google Patents

Abstract

To solve the problem in which: in an image processing apparatus including a plurality of image processing circuits, a dedicated memory belonging to an image processing circuit temporarily stopped according to an operation mode cannot be used from the other operating image processing circuits.SOLUTION: An image processing apparatus comprises: a plurality of image processing means that each processes image data stored in an external storage of the image processing apparatus for every partial image data; an interface with the external storage; a common memory that is shared by the plurality of image processing means, holds data processed by the image processing means through the interface, and constituted by a plurality of SRAMs included inside the image processing apparatus; and a memory control circuit that allocates, to the common memory, an input buffer area that temporarily holds the partial image data input to the image processing means from the external storage, the partial image data before being processed by the image processing means, and an output buffer area that temporarily holds the partial image data after being processed by the image processing means output to the external storage from the image processing means.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an image processing apparatus, a control method therefor, and a program.

  In recent years, scanners, video cameras and the like have become widespread as input devices. In addition, various color printers using an inkjet, dye thermal sublimation type or electrophotographic system as an output device are in widespread use. In general, typical image processing used in these color input / output devices include "color space conversion" and "spatial filtering".

  The “color space conversion” is a process of converting the color space of the input device into the color space of the output device in order to solve the problem relating to the color reproducibility between the input / output devices with respect to a color image or the like. Specifically, it may refer to the entire series of image processing such as input γ correction, luminance density conversion, masking, black generation, UCR, output γ correction, etc., and it may refer to only certain processing among them.

  Also, "spatial filtering" refers to local (near-by) image processing that performs some operation using all the pixels included in the spatial filter area including the pixel to be processed (hereinafter referred to as a processing pixel). is there. For example, it refers to processing such as edge enhancement processing and blurring processing.

  The image processing circuit for realizing such image processing temporarily stores reference data required by various operation circuits in addition to various operation circuits, and temporarily stores the pixel value of the processing pixel of the color image. It often comes with a memory to The memories used in these image processing circuits will be described in detail by way of specific examples.

  In the above color space conversion, the three-color digital image signal of the input device is often referred to simultaneously to be converted to the three-color or four-color digital image signal of the output device. Here, the three colors of the input device indicate, for example, three colors of red, blue, and green (hereinafter, abbreviated as “RGB”). Further, the three colors of the output device refer to, for example, three colors of cyan, magenta and yellow (hereinafter abbreviated as "CMY"). Further, the four colors of the output device indicate, for example, four colors of cyan, magenta, yellow, and black (hereinafter, abbreviated as "CMYK"). In the case of an electrophotographic copying machine, the engine characteristics of the printer change with the operating time, so periodic calibration is required. In such a case, conversion from four colors (for example, "CMYK") of the output device to four colors (for example, "C'M'Y'K '") of the output device is also required.

  As a means for realizing the above color space conversion, the conversion result is stored in advance as a look-up table (hereinafter abbreviated as "LUT") in a memory, and the conversion result is converted from the LUT to the input digital image signal. There is a way to output.

  In the color space conversion method using this LUT, the LUT used for digital image signals of three-color input is called a three-dimensional look-up table (hereinafter abbreviated as "3D-LUT"). Also, the LUT used for digital image signals of four-color input is called a four-dimensional look-up table (hereinafter abbreviated as "4D-LUT").

  Here, in the case of dividing into 16 in each axial direction of the color space (RGB space) of the three-dimensional input, the 3D-LUT needs a memory having the number of entries of the cube of 16 (see Patent Document 1). Therefore, a memory of a capacity of 16 Kbytes is implemented as a dedicated memory (part of the same circuit) of the color space conversion circuit if the data amount is 4 bytes per entry to convert RGB space to CMYK space.

  In addition, when divided into 16 in each axis direction of color space (CMYK space) of four-dimensional input, 4D-LUT needs memory with the entry number of 16 4 (16 times the size of 3D-LUT) It becomes. That is, in order to convert the CMYK space into the C'M'Y'K 'space, if the amount of data is 4 bytes per entry, a memory with a capacity of 256 Kbytes is a dedicated memory of the color space conversion circuit (part of the same circuit) Implemented as

  In the case of the above-mentioned spatial filter processing, image processing is performed pixel by pixel from the upper left end pixel of the digital image data in the main scanning direction, and image processing is performed up to the right end pixel. Then, it advances by one pixel in the sub scanning direction, and image processing is performed again from the pixel at the left end to the right end by one pixel along the main scanning direction. This series of image processing is repeatedly executed until image processing on the pixel at the lower right of the digital image data is completed, and desired image processing is performed.

  Such a technique requires a large memory capacity as the width in the main scanning direction of digital image data increases. For example, when an A4 size image is read by a scanner having a resolution of 600 dpi and converted into digital image data, the width of the digital image data is 4953 pixels. Further, when one pixel is constituted by the aforementioned RGB, and RGB has a data amount of 3 bytes, a delay memory for 2 lines is required for the 3 × 3 spatial filter area. A memory having a capacity of about 29 Kbytes (4953 pixels × 2 lines × 3 bytes) is implemented as a dedicated memory (part of the same circuit) of the spatial filter circuit.

  Further, it is assumed that one pixel is constituted by the above-mentioned CMYK, and the CMYK has a data amount of 4 bytes. In this case, a memory having a capacity of about 39 Kbytes (4953 pixels × 2 lines × 4 bytes) is mounted as a dedicated memory (part of the same circuit) of the space filter circuit for the 3 × 3 space filter area. Be done.

  2. Description of the Related Art In recent years, various image processing circuits are required for an image processing apparatus in order to improve the image quality and enhance functions of products. However, the image processing circuit can not change the contents of processing if programs are exchanged like a CPU. Therefore, by changing the operation mode of various products, one image processing circuit is operated among the various image processing circuits of the image processing apparatus, and another image processing circuit is temporarily stopped because it is unnecessary. A situation occurs in which

  At this time, the dedicated memory attached to the image processing circuit in the stopped state is also stopped at the same time, and can not be used from other image processing circuits in operation. As described in the above description, the memory capacity connected as a dedicated memory to the image processing circuit is very large, and the circuit scale of the dedicated memory occupies a large proportion of the entire image processing LSI. These memories are temporarily wasted, and hardware resources are not effectively used (the activation rate of the entire image processing LSI is not improved).

JP 2007-67956 A

  As described above, in the image processing apparatus including a plurality of image processing circuits, there is a problem that the dedicated memory attached to the image processing circuit temporarily stopped due to the operation mode can not be used from other image processing circuits in operation.

  The present invention has been made in view of the problems described above, and by sharing the dedicated memories of a plurality of image processing circuits with each other, the image processing circuits in other operations may be operated even when some of the image processing circuits do not operate. To provide technology that can be used by

An image processing apparatus according to the present invention for solving the above problems is:
A plurality of image processing means for processing image data held in an external storage outside the image processing apparatus for each partial image data;
An interface with the external storage, and a plurality of SRAMs internally included in the image processing apparatus, which share the plurality of image processing units and hold data to be processed by the image processing units through the interface Shared memory,
An input buffer area for temporarily holding the partial image data that is the partial image data input from the external storage to the image processing means from the external storage in the shared memory and before the image processing means processes the image; And a memory control circuit for assigning an output buffer area for temporarily holding the partial image data processed by the image processing means which is output from the processing means to the external storage.

  According to the present invention, by sharing the dedicated memories of a plurality of image processing circuits with one another, even if some of the image processing circuits do not operate, the area for the circuit is allocated to the other image processing circuits in operation. be able to. Thereby, the activation rate of the memory used for image processing can always be improved.

FIG. 1 is a block diagram showing an example of the overall configuration of an image processing apparatus 10. FIG. 3 is a block diagram showing an example of a circuit configuration of an image processing unit 150. FIG. 16 is a diagram for explaining an example of a shared memory control circuit 270. It is a figure explaining an example of the address map of shared memory 280. FIG. FIG. 6 is a diagram illustrating an example of a circuit configuration of an image processing unit in a state in which a clock of an unused memory can be stopped and an example of an address map of a shared memory. 5 is a flowchart illustrating an example of shared memory control processing; It is a figure explaining an example of operation of band processing corresponding to a 4th embodiment of the invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment
FIG. 1 is a block diagram showing an example of the entire configuration of an image processing apparatus 10 according to the first embodiment. In FIG. 1, the image reading unit 120 includes a lens 124, a CCD sensor 126, an A / D conversion unit 127, and the like. In the image reading unit 120, image information of the document 110 formed on the CCD sensor 126 via the lens 124 is converted by the CCD sensor 126 into analog electric signals of R (Red), G (Green) and B (Blue). Ru. The image information converted into the analog electrical signal is input to the A / D conversion unit 127, corrected and the like for each of the R, G, and B colors, and then analog / digital converted (A / D conversion). Thus, a digitized full color signal (referred to as a digital image signal) is generated. A digital image signal composed of one set of R, G, B represents one pixel of the image.

  The CPU 102 controls a write DMAC (Direct Memory Access Controller) 192 and stores the generated digital image signal as image data in the RAM 106 of the CPU circuit unit 100 via the shared bus 190. Next, the CPU 102 controls the read DMAC 194 to read out the image data stored in the RAM 106 and input the image data to the image processing unit 150.

  The image processing unit 150 performs, for example, correction of individual differences of the reading elements of the sensor or device such as a scanner and color correction such as input gamma correction on the input digital image signal, normalizes the read image, Create image data. The digital image signal subjected to these processes is stored again in the RAM 106 by the write DMAC 196 in accordance with the control of the CPU 102.

  The image processing unit 150 can also print the input digital image signal by performing input color correction processing, spatial filter processing, color space conversion, density correction processing, and image processing as preprocessing for printing. Image data can also be created. Also in this case, the write DMAC 196 causes the RAM 106 to store the same as described above.

  Finally, the CPU 102 controls the read DMAC 198 to read out the image-processed image data stored in the RAM 106, performs halftone processing, and outputs the processed image data to the image printing (printer) unit 170. The image printing (printer) unit 170 includes, for example, a print output unit (not shown) such as a raster plotter using an ink jet head or a thermal head, and the image is printed on paper by the input digital image signal. Record.

  The CPU circuit unit 100 further includes a CPU 102 for arithmetic control, a ROM 104 for storing fixed data and programs, a RAM 106 for temporarily storing data and loading a program, and an external storage device 108. The CPU circuit unit 100 controls the image reading unit 120, the image processing unit 150, the image printing (printer) unit 170, and the like, and controls the overall sequence of the image processing apparatus 10 of the present embodiment.

  The external storage device 108 is a storage medium such as a disk that stores parameters, programs, and correction data used by the image processing apparatus 10 according to the present embodiment. Data, programs, and the like of the RAM 106 are loaded from the external storage device 108 It does not matter as a structure.

  Next, the image processing unit 150 of FIG. 1 will be described in detail. FIG. 2 is a block diagram showing an example of the circuit configuration of the image processing unit 150 of the present embodiment.

  The digital image signal is input to the image processing unit 150, and the image processing described below is performed. The image processing unit 150 includes an image processing input circuit 210, a spatial filter processing circuit (1) 220, a spatial filter processing circuit (2) 230, a color space conversion circuit 240, an output γ correction circuit 250, and an image processing output circuit 260. Is configured.

  The image processing input circuit 210, the spatial filter processing circuit (1) 220, the spatial filter processing circuit (2) 230, the color space conversion circuit 240, the output γ correction circuit 250, and the image processing output circuit 260 will be described in detail below.

[Image processing input circuit 210]
A digital image signal 205 is input via a readout DMAC 194 external to the image processing unit 150. The digital image signal 205 is composed of R, G and B luminance signals. The image processing input circuit 210 can control the memory of the double buffer configuration and temporarily store it in the buffer while receiving the digital image signal 205. On the other hand, the digital image signal stored in the previous buffer is read out and output as a digital image signal 215.

[Spatial filter processing circuit (1) 220 / Spatial filter processing circuit (2) 230]
The digital image signal 215 output from the image processing input circuit 210 is input to the spatial filter processing circuit (1) 220. The spatial filter processing circuit (1) 220 can control a delay memory for performing filter processing, and performs smoothing or an edge based on the digital image signal already accumulated in the delay memory and the input digital image signal 215. Perform local (near-by) image processing such as enhancement. The processing result is output as a digital image signal 225. Among the digital image signals already accumulated in the delay memory, unnecessary digital image signals are replaced with the input digital image signals 215 simultaneously with processing.

  The spatial filter processing circuit (2) 230 also receives the input of the digital image signal 225, performs the same processing as the spatial filter processing circuit (1) 220, and outputs it as a digital image signal 235.

[Color space conversion circuit 240]
The digital image signal 235 output from the spatial filter processing circuit (2) 230 is input to the color space conversion circuit 240. The color space conversion circuit 240 can control a memory that holds a 3D-LUT or 4D-LUT for color conversion. The color space conversion circuit 240 acquires reference data from the 3D-LUT and performs interpolation operation, and the luminance signals R, G, B of the input digital image signal 235 are converted into luminance signals R ', G', of another color space. It is converted into B ', density signals C, M, Y and density signals C, M, Y, K. The conversion result is output as a digital image signal 245. When the input digital image signal 235 has four components of density signals C, M, Y, and K, the color space conversion circuit 240 acquires reference data from the 4D-LUT and performs interpolation. The density signals C, M, Y, K of the digital image signal 235 are converted into other density signals C ′, M ′, Y ′, K ′ and output as digital image signals 245.

[Output γ correction circuit 250]
The digital image signals (luminance signals R ′, G ′, B ′, density signals C, M, Y, etc.) 245 output from the color space conversion circuit 240 are input into the output γ correction circuit 250. The output γ correction circuit 250 can control a memory holding a 1D-LUT for performing color correction specific to the output device. The output γ correction circuit 250 acquires reference data from the 1D-LUT, performs interpolation operation, corrects the input digital image signal 245, and outputs it as a digital image signal 255.

[Image processing output circuit 260]
The image processing output circuit 260 can control the memory of the double buffer configuration and temporarily store it in the buffer while receiving the digital image signal 255. On the other hand, the digital image signal stored in the previous buffer is read, and the digital image signal 265 is output to the RAM 106 via the write DMAC 196 outside the image processing unit 150.

  The plurality of image processing circuits 210 to 260 constituting the image processing unit 150 all control the memory to perform image processing. Each processing circuit operates the shared memory control circuit 270 via the control port 272 for this memory control. Each of the image processing circuits sends a memory access method designation signal 274 to the shared memory control circuit 270, receives a memory access end signal 276 from the shared memory control circuit 270, and synchronizes with the shared memory control circuit 270. To realize. When the memory control from each of the image processing circuits is data writing, each of the image processing circuits has a shared memory control circuit simultaneously or sequentially with the sending of the memory access method designation signal 274. Send to 270

  When the memory control from each of the image processing circuits is data read (read), each of the image processing circuits receives read data from the shared memory control circuit 270. When the memory control is data read (read), each of the image processing circuits can determine the completion of the memory control by receiving the read (read) data. Therefore, the memory access end signal 276 may be omitted, or the memory access end signal 276 may be received simultaneously with, prior to, or at the end of receiving the read data.

  The shared memory control circuit 270 is connected to the shared memory 280, the read DMAC 290, and the write DMAC 294. However, if all of the image processing circuits do not support the read cache mode described later, the shared memory control circuit 270 need not be connected to the read DMAC 290. In addition, when all of the image processing circuits do not support the write cache mode described later, the shared memory control circuit 270 need not be connected to the write DMAC 294. The read DMAC 290 and the write DMAC 294 may be outside the image processing unit 150 even if any of the image processing circuits support the read cache mode or the write cache mode. At this time, the shared memory control circuit 270 may be connected to a control port for controlling the read DMAC 290 or the write DMAC 294.

  The shared memory 280 according to the present embodiment includes one or more memories (shown as memories 280-1 to 280-N), and configures the shared memory in consideration of the processing performance of the image processing circuits 210 to 260. The number of memories to be determined is determined. At this time, the shared memory 280 is a virtual memory formed by integrating a plurality of memories (entities).

  Further, in the LSI mounting, the circuit scale is increased if the memory having a certain capacity is divided into a plurality of sub memories having a smaller capacity than in a single case. This is because one memory needs an area for securing a power supply and an area for connecting a test circuit for testing the memory. However, when the memory is divided into a plurality of sub memories, the amount of data that can be read and written in parallel increases, so the processing performance per cycle can be easily improved. The image processing circuits 210 to 260 require a total of eight control ports 272.

  For example, in a consumer printer image processing apparatus, if the processing performance of the image processing circuits 210 to 260 may be 1/10 [pixel / cycle], each of the image processing circuits performs memory control at a rate of once every 10 clocks. It will be good. In this case, the shared memory 280 may be realized by only the memory (1) 280-1.

  On the other hand, if the processing performance of the image processing circuits 210 to 260 is 1/1 [pixel / cycle] in a printer image processing apparatus for office equipment, at least 10 shared memories 280 (1) to (N) ) (N = 10). When it is assumed that the space filter processing circuit requires two memory controls of reading and writing of data, the above approximation is obtained.

  The shared memory control circuit 270 also controls a chip select signal (cs), a read / write identification signal (rw), and an address signal (address) for controlling the memory (1) 280-1 to the memory (N) 280-N. , Write data (write_data). Also, read data (read_data) is received from the memory (1) 280-1 to the memory (N) 280-N (these signals are generically called a memory control signal 284).

  Allocation of the use area of the shared memory 280 according to the operation mode of the present embodiment will be described with reference to FIG. First, the address map described in Case 1 corresponding to the first operation mode shows the case where all of the image processing circuits shown in FIG. 2 are used.

  The double buffer used in the image processing input circuit 210 is realized by switching and using the input buffer 410 and the input buffer 412. The spatial filter processing circuit (1) 220 uses a delay memory (1) 420, and the spatial filter processing circuit (2) 230 uses a delay memory (2) 430. The color space conversion circuit 240 uses a three-dimensional LUT 440, and the output γ correction circuit 250 uses a one-dimensional LUT (1) 450. The double buffer used in the image processing output circuit 260 is realized by switching between the output buffer 460 and the output buffer 462.

  Case 2 and case 3 shown in FIG. 4 show an example of the address map in the second and third operation modes different from the first operation mode and a configuration example of the image processing circuit. In case 2, the space filter processing circuit (1) 220 of case 1 is stopped, and the unused area of shared memory 280 is used by input buffers 410 and 412 of case 1, delay memory (2) 430, and output buffers 460 and 462 . More specific processing content will be described in the fourth embodiment. In case 2, for the three-dimensional LUT 440 and the one-dimensional LUT (1) 450, the case 1 and the top address on the shared memory 280 are different but the capacity is the same.

  In case 3, the space filter processing circuit (1) 220 and the space filter processing circuit (2) 230 in case 1 are stopped, and unused areas are allocated to the color space conversion circuit 240 and the output γ correction circuit 250. There is. In one example of case 3, the input digital image signal has four colors of C, M, Y and K, and the color space conversion circuit 240 performs color space conversion using four-dimensional tetrahedron interpolation method C ', M' and Y '. , K 'are output. Since the 4D-LUT required at this time requires 256 K bytes as described above, cache data is expanded in the four-dimensional LUT data cache 440 of the shared memory 280 in the illustrated example. The output γ correction circuit 250 is also assigned a one-dimensional LUT 450 for digital image signals of four colors.

  As described above, depending on the operation mode of the image processing apparatus 10, the use area of the shared memory 280 used by the image processing circuit being stopped is used to improve the efficiency (processing performance) of the image processing, if any. Other image processing circuits can be used. At other times, another image processing circuit in operation can be used to improve the function including high image quality.

  By the process of the flowchart shown in FIG. 6, the use area of the shared memory 280 used by the image processing circuit in suspension is appropriately allocated to another image processing circuit in operation. First, in step S601, the CPU circuit unit 100 determines an operation mode of image processing. Next, in step S602, the CPU circuit unit 100 functions as a processing circuit control unit based on the determined operation mode of image processing, and selects an image processing circuit to be used. Further, in step S603, the image processing unit 150 calculates the buffer capacity for inputting / outputting digital image data from another related domain from the transfer amounts of the read DMAC 194 and the write DMAC 196. In step S604 and subsequent steps, the memory capacity required for each of the image processing circuits selected in the operation mode is calculated according to the content of the image processing.

  First, in step S604, it is determined whether color space conversion using the color space conversion circuit 240 is to be performed. If color space conversion is to be performed ("YES" in step S604), the process moves to step S605. On the other hand, when color space conversion is not performed ("NO" in step S604), the process proceeds to step S606.

  In step S605, the LUT capacity for color space conversion is calculated. In color space conversion, since a three-dimensional LUT or a four-dimensional LUT is used, the capacity corresponding to the LUT to be used is calculated. As described above, for example, in the case of 3D-LUT, it is 16 Kbytes and in the case of 4D-LUT, it is 256 Kbytes. Then, it transfers to step S606.

  Next, in step S606, it is determined whether the output γ correction by the output γ correction circuit 250 is to be performed. If the output γ correction is to be performed (“YES” in step S606), the process proceeds to step S607. On the other hand, when the output γ correction is not performed (“NO” in step S606), the process proceeds to step S608. In step S 607, the capacity of the one-dimensional LUT 450 for the four-color digital image signal used for the output γ correction is calculated.

  In the following step S608, it is determined whether or not the spatial filter processing circuit (1) 220 is to be used. If the spatial filter processing circuit (1) 220 is used ("YES" in step S608), the process proceeds to step S609. In step S609, the delay memory capacity is calculated, and the process proceeds to step S610. If necessary at this time, the band height is calculated. The calculation of the band height will be described later in detail in the fourth embodiment. On the other hand, when the spatial filter processing circuit (1) 220 is not used ("NO" in step S608), the process proceeds to step S610.

  In the following step S610, it is determined whether or not the spatial filter processing circuit (2) 230 is to be used. If the spatial filter processing circuit (2) 230 is used ("YES" in step S610), the process proceeds to step S611. In step S611, the delay memory capacity is calculated. If necessary at this time, the band height is calculated. On the other hand, when the spatial filter processing circuit (2) 230 is not used (“NO” in step S610), the process proceeds to step S612.

  In the subsequent step S612, the allocation of the used area of the shared memory 280 is determined. In the following step S613, it is determined whether there is an unused memory, and if there is an unused memory ("YES" in step S613), the process proceeds to step S614. On the other hand, when there is no unused memory ("NO" in step S613), the process proceeds to step S615.

  In step S614, the clock supply to the unused memory is stopped, and the process proceeds to step S615. In step S615, a predetermined value is set in advance in the conversion table of the shared memory control circuit in accordance with the determined assignment of shared memory 280. In step S616, image processing in the operation mode determined in step S601 is performed.

  Hereinafter, the operation of the shared memory control circuit and the cooperation with the image processing circuit will be described in more detail with reference to FIG.

  The block diagram shown in FIG. 3 shows details of the shared memory control circuit 270. Each of the image processing circuits inputs the aforementioned memory access method designation signal to the instruction queue 314 via the control port 272 connected to the shared memory control circuit 270.

  In the control port 272, one port 311 is disposed for each image processing circuit. The port 311 has an instruction queue 314 and an instruction completion queue 316. In the instruction queue 314, a memory access method designation signal to the shared memory 280 from each image processing circuit is written. In addition, a memory control end signal for notifying the end of control to the memory or read (read) data from the shared memory 280 is written in the instruction completion queue 316.

  The memory access arbitration circuit 310 takes out the memory access method designation signal of the instruction queue 314 of the control port input from each of the image processing circuits in accordance with the prioritization and sends it to the conversion table 370.

  The memory access method designation signal comprises an ID (tag) for identifying a memory access method and a relative start address (pointer) for specifying a memory access position. Also, the table value of one entry constituting the conversion table 370 is configured by the start address and capacity (number of words) on the address map of the shared memory, the number of memory control times to be executed by one instruction, and the memory access method.

  There are five memory access methods in this embodiment: write, read, write after read (Read & Write), read cache, and write cache. Each of these memory access methods is assigned an ID (tag). From the conversion table 370, a table value for realizing memory access for image processing registered in advance according to the ID (tag) is acquired.

  The operation of each memory access method will be briefly described below.

[Write]
When the memory access method of the table value is write, write data is written to the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address.

[Read]
When the memory access method of the table value is read (Read), read (read) data is read from the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address.

[Write after read (Read & Write)]
When the memory access method of the table value is write after read (Read & Write), read (read) data is read from the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address. Thereafter, write data is written to the same address of the shared memory.

[Write cache]
When the memory access method of the table value is the write cache, the relative start address (pointer) is regarded as the cache tag number, and the cache hit / miss hit is determined. If it is a hit, write data is written to the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address.

  In the case of a mishit, the write DMAC controller 360 controls the write DMAC for data of a predetermined address of the shared memory continuously for the number of times of memory control from the addition result of the relative start address (pointer) and the start address. At the same time, writing to the RAM 106 is performed. Thereafter, write data is written to a predetermined address of the shared memory.

[Read Cache]
If the table value memory access method is a read cache, the relative start address (pointer) is regarded as a cache tag number to determine a cache hit / miss hit. If it is a hit, from the result of adding the relative start address (pointer) and the start address, read data is read from the shared memory continuously for the number of times of memory control. In the case of a mishit, the read DMAC controller 350 controls the read DMAC continuously for the number of times of memory control based on the addition result of the relative start address (pointer) and the start address. Then, read (read) data is reacquired from the RAM 106, and (read) data is written to a predetermined address of the shared memory, and at the same time read (read) data is read.

  Control for each memory access method is performed by the control circuit 380. The control circuit 380 is a cache tag determination circuit that determines cache hit / mishit, a FIFO pointer circuit, a read circuit (READ), a write circuit (WRITE), and a selector that controls input / output to each circuit. sel).

  From the control circuit 380, a predetermined address defining the access destination to the shared memory 280 and the number of times of memory control are sent to the memory control circuit 330. The memory control circuit 330 determines which of the memory (1) to the memory (N) the memory control is based on the predetermined address and the number of times of memory control. The memory control circuit 330 generates a memory control signal and performs reading and writing from the memory (1) to the memory (N).

  A sequencer 345 is mounted on each of the SRAM controllers 340-1 to 340-N, the read DMAC controller 350, and the write DMAC controller 360 in order to perform memory control continuously for the number of times of memory control.

  The SRAM controllers 340-1 to 340 -N, the read DMAC controller 350, and the write DMAC controller 360 send a memory control end signal to the read data acquisition circuit 320 in the case of writing. In the case of read, read data or a memory control end signal is sent to the read data acquisition circuit 320. The memory control end signal is input to the instruction completion queue 316 in the control port 272 of each of the image processing circuits, and each of the image processing circuits obtains a memory control end signal or read data.

  Hereinafter, a memory access method in each image processing circuit will be described.

  The image processing input circuit 210 needs to realize a double buffer configuration, and writes the input digital image data from the read DMAC 194 to the shared memory by designating “Write” as the memory access method as needed. When digital image data stored in the previous buffer is to be sent to the subsequent image processing circuit, digital image data is read from the shared memory by designating "Read" as the memory access method.

  The spatial filter processing circuit (1) 220 and the spatial filter processing circuit (2) 230 control the delay memory. In the case of delay memory control, the memory access method is specified as "write after read (Read & Write)" to simultaneously read and write the shared memory.

  The color space conversion circuit 240 and the output γ correction circuit 250 control the LUT. In the case of LUT control, digital image data is read out from the shared memory by designating "Read" as the memory access method.

  If the color space conversion circuit 240 can not store all the LUTs in the shared memory when reading out read data from the four-dimensional LUT, the memory access method is designated as “read cache”. Thereby, a cache function is added at the time of LUT reference from shared memory.

  The image processing output circuit 260 needs to realize the double buffer configuration, and writes the output digital image data from the image processing circuit to the shared memory by designating “Write” as the memory access method as needed. When the digital image data stored in the previous buffer is sent to the RAM 106 via the DMAC (Write), the output digital image data is read from the shared memory by designating "Read" as the memory access method.

  The control method for sharing the memory in the plurality of image processing circuits has been described above, but the above content is an example. Therefore, the ID (tag) and relative start address (pointer) of the memory access method designation signal may not necessarily come out as described above. In addition, the start address and capacity (number of words) on the address map of the shared memory, the number of memory control times to be executed by one instruction, and the memory access method, which are table values of one entry constituting the conversion table 370 It does not matter if it does not have a circuit configuration like this. For example, the conversion table 370 may not be implemented, and all the information for performing the memory control may be included in the memory access method designation signal.

Second Embodiment
In the first embodiment, the memory access method is defined by general memory control requirements, and the image processing circuit combines them to realize read / write to the shared memory.

  Specifically, the image processing input circuit 210 combines two memory access methods [Write] and [Read]. Actually, four memory access methods ([Write] and [Read] to the input buffer [A] 410, [Write] to the input buffer [B] 412, [Read] is registered. Then, the image processing input circuit 210 selects two of the four conversion table values to realize a double buffer.

  On the other hand, in the second embodiment, the memory access method is defined by the requirements specific to the image processing circuit. That is, for the image processing input circuit 210 described above, a double buffer mode is defined as a memory access method. Then, the input memory [A] 410 and the input buffer [B] 412 are automatically switched on the shared memory control circuit side according to the specification of the relative start address (pointer) of the memory access method specification signal.

  Further, with respect to the memory access method of the spatial filter processing circuits (1) 220 and (2) 230, the above-mentioned [write (read & write) after reading] is defined as a delay buffer (FIFO) mode. At this time, the length of the ring FIFO may be registered in the conversion table separately from the delay buffer capacity. Further, for the memory access method of the color space conversion circuit 240 and the output γ correction circuit 250, the above [Read] is defined as the look-up table mode. At this time, shared memory control is to continuously read out the vertexes necessary for tetrahedron interpolation described in Japanese Patent Application Laid-Open No. 2007-67956, instead of reading out the LUT reading method continuously from the predetermined address of the shared memory in the conversion table. The mounting method may be performed automatically on the circuit side.

  Further, the ID (tag) of the memory access method designation signal may not be the entry number of the conversion table as in the first embodiment, but may be a unique number indicating the image processing content.

Third Embodiment
FIG. 5 shows the present embodiment and is a view for explaining an example of the circuit configuration of the image processing unit in a state in which the clock of the unused memory can be stopped and an example of the address map of the shared memory. In the circuit configuration of FIG. 5, the shared memory includes four memories of the same capacity: memory (1) 280-1, memory (2) 280-2, memory (3) 280-3, and memory (4) 280-4. It is configured. Also, as shown in FIG. 5, it is assumed that the same capacity is allocated to the address map in the order of the memory (1), the memory (2), the memory (3) and the memory (4).

  As in the circuit configuration of FIG. 5, among the image processing circuits of the image processing apparatus 10, only the image processing input circuit 210, the spatial filter processing circuit (1) 220, and the image processing output circuit 260 are selected depending on the operation mode. Assume that it works and the rest is stopped. At this time, as in the memory map shown in FIG. 5, the designated area of the shared memory 280 is allocated so as to fit in the area of the memory (1) 280-1 constituting the shared memory. Alternatively, the allocation is adjusted such that there is a memory to which no area is allocated, as much as possible so that the used areas are not dispersed among a plurality of memories.

  As a result, in the case of FIG. 5, the memory (2) 280-2 to the memory (4) 280-4 become unused and are not used for image processing. Then, the surplus memory clock can be stopped to reduce the power consumption of the image processing circuit. Even in the case other than that, the clock can be stopped for the memory to which no area is allocated to reduce the power consumption.

  When each of the image processing circuits is connected to the dedicated memory, it is possible to suppress the power consumption by stopping the clock for the unused image processing circuit and the dedicated memory in the operation mode. On the other hand, in the present invention, power consumption can be suppressed by operating the designated area of the shared memory according to the operation mode.

Fourth Embodiment
As described in Japanese Patent Application Laid-Open No. 2006-139606, it is possible to reduce the delay memory capacity required for the spatial filter processing circuit of local (nearby) image processing such as edge enhancement processing and blurring processing. For example, local image processing such as edge enhancement processing and blurring processing is performed on the digital image data 700 in FIG. 7. At this time, digital image data is divided into areas, and local image processing is performed for each of the areas. In general, in such a technology, as shown in (a) to (d) of FIG. 7, the entire digital image data of one sheet is divided into strips (stripes), and various image processing is sequentially performed for each area. It takes place.

  The divided elongated area is called a band area, the storage area in which the band area is expanded is called a band memory, and the action of dividing the image is called a band division. The band memory is not necessarily reserved as a storage area in the main memory, but may be secured in any storage area on the system, but here, in order to simplify the explanation, the band memory is mainly used. The case of securing in the memory will be described as an example.

  Further, as shown in FIG. 7E, the coordinate system (main scanning direction-sub scanning direction) of the digital image data defines a new coordinate system (band area coordinate system) in the length direction and the height direction. And express the band area by length × height. The band area is set such that either the length or the height always has a width in the main scanning direction of the digital image data or a height in the sub-scanning direction. For example, when the length of the band area is adjusted to the width in the main scanning direction of the digital image data, the height of the band is an arbitrary value. On the other hand, when the height of the band area is adjusted to the height of the digital image data in the sub-scanning direction, the length of the band is an arbitrary value.

  The band processing will be described in detail. First, the first band area 701 shown in (a) of FIG. 7 is developed in a band memory on the main memory and image processing is performed. Next, the second band area 702 shown in (b) of FIG. 7 is overwritten and expanded in the band memory in which the first band area 701 is expanded, and image processing is performed. Further, the third band area 703 shown in (c) of FIG. 7 is overwritten and expanded in the band memory in which the second band area 702 is expanded, and image processing is performed. Finally, the fourth band area 704 shown in (d) of FIG. 7 is overwritten and expanded in the band memory in which the third band area 703 is expanded, and image processing is performed.

  As apparent from (a) to (d) of FIG. 7, the band regions 701 to 704 have the same length but the height does not have to be the same. In FIG. 7, banded regions 701-703 have the same height, and banded region 704 has a lower height. Therefore, the height of the band memory which is the storage area secured in the main memory is determined by the band area having the largest size in the height direction (the first to third band areas 701 to 703 in FIG. 7). It is determined.

  In this technique, in order to perform local image processing without gaps between the band regions, it is devised that the respective band regions overlap with each other at the boundaries with the respective adjacent regions. Further, in Japanese Patent Application Laid-Open No. 2006-139606, a pixel is scanned one pixel at a time in the same direction as the height of each band area, and the capacity of the delay memory holding processing pixels necessary for local image processing is the height of each band area. It defines by the size of. Thus, the memory saving of the delay memory is realized.

  In general, in order to perform the local image processing described in the example, a delay memory having a capacity equal to an integer (the number of taps of spatial filtering minus one) times the number of pixels in the horizontal width of the paper surface is required. In such a technique, the delay memory capacity is determined by the size of the paper and can not be changed. However, in Japanese Patent Application Laid-Open No. 2006-139606, the delay memory capacity is an integer (divided by the number of taps of spatial filtering processing) times the divided band height, but any band height can be specified according to the number of divided bands. Therefore, the delay memory capacity can be changed.

  In this embodiment, the feature that the delay memory capacity can be changed is used. That is, the band height is calculated according to the following equation 1 according to the free space of the shared memory (delayed memory capacity which can be secured on the shared memory) and the number of taps of the space filtering process.

Band height = Delay memory capacity that can be secured on shared memory / (Number of taps-1) / (Data amount of one pixel) ... (Equation 1)
According to the present invention, even when a part of the image processing circuit of the image processing apparatus 10 does not operate, the image processing circuit in operation can always use the memory, and the memory mounted for image processing can be effectively used. The memory activation rate of the entire LSI can be improved. In addition, since each image processing circuit does not need to be aware that the memory of the connection destination is shared, the memory control method is easy for each image processing circuit, and the design of each image processing circuit is also easy.

  Also, conventionally, the dedicated memory attached to each image processing circuit has various sizes according to the contents of each processing, and has been unevenly distributed. On the other hand, since the present invention integrates memories of a certain size (in many cases, the same capacity is desirable) into one virtual shared memory, it is easy to arrange and route circuits during LSI development. Become.

  Furthermore, among the plural image processing circuits, the capacity of the shared memory may be larger than the total amount of memories of the image processing circuits operated by the designation of the operation mode, so that the total amount of all memories of plural image processing circuits is LSI as in the prior art. There is no need to implement it. Therefore, the circuit scale of the memory mounted as a total decreases.

  Further, in the method of performing image processing sequentially by band division, the capacity of the delay memory used for local image processing such as a spatial filter circuit depends on the number of taps of the spatial filter and the band height. In such image processing, the ratio of the number of spatial filter taps to the band height changes the number of redundantly retransmitted pixels, and the larger the band height, the better the image processing efficiency. More flexible image processing can be realized by combining the shared memory of the present invention and band division and sequentially combining image processing. Specifically, when there are a large number of image processing circuits operated with an operation mode with emphasis on functions, the free capacity of the shared memory naturally decreases. At this time, an executable band height is calculated from the space area of the shared memory and the number of taps of the spatial filter, and although the efficiency is lowered, sequential image processing for each predetermined band height is performed. Conversely, when there are very few image processing circuits that operate in the operation mode, the free space of the shared memory naturally increases, and efficient image processing can be performed by setting the band height as large as possible. That is, the band height can be adjusted according to the free space of the shared memory, and the function and efficiency of the image processing can be traded off to realize flexible image processing.

  In the above embodiments, the present invention has been described as an image processing apparatus having a plurality of image processing circuits, but the embodiments of the invention are not limited to the image processing apparatus. That is, in the information processing apparatus including a plurality of processing circuits, the present invention is provided to solve the problem that the dedicated memory attached to the processing circuit temporarily stopped in the operation mode can not be used from other processing circuits in operation. can do. In such an information processing apparatus, by sharing the dedicated memories of a plurality of processing circuits with one another, even if some of the processing circuits do not operate, an area for the circuit is allocated to the processing circuit in another operation. be able to.

Other Embodiments
Even if the present invention is applied to a system constituted by a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus consisting of one device (for example, a copying machine, a facsimile machine, etc.) It may apply to

  The object of the present invention is also achieved by supplying a storage medium storing computer program code for realizing the functions described above to a system, and the system reads out and executes the computer program code. In this case, the code itself of the computer program read from the storage medium implements the functions of the above-described embodiments, and the storage medium storing the code of the computer program constitutes the present invention. In addition, an operating system (OS) or the like operating on a computer performs part or all of the actual processing based on the instruction of the code of the program, and the above-described functions are realized by the processing. .

  Furthermore, it may be realized in the following form. That is, the computer program code read out from the storage medium is written in a memory provided in a function expansion card inserted in the computer or a function expansion unit connected to the computer. Then, based on the instruction of the code of the computer program, the CPU included in the function expansion card or the function expansion unit may execute part or all of the actual processing to realize the above-described function.

  When the present invention is applied to the storage medium, the storage medium stores the code of the computer program corresponding to the flowchart described above.

10: Image processing apparatus 10, 100: CPU circuit unit, 150: image processing unit, 280: shared memory

Claims (13)

An image processing apparatus,
A plurality of image processing means for processing image data held in an external storage outside the image processing apparatus for each partial image data;
An interface with the external storage,
A shared memory composed of a plurality of SRAMs internally included in the image processing apparatus, which is shared by the plurality of image processing units and holds data processed by the image processing unit through the interface ;
An input buffer area for temporarily holding the partial image data that is the partial image data input from the external storage to the image processing means from the external storage in the shared memory and before the image processing means processes the image; an output buffer area for temporarily storing the partial image data after the image processing unit outputted from the processing unit to the external storage has processed, a memory control circuit for assigning a,
An image processing apparatus comprising: The memory control circuit further allocates a storage area of reference data for the image processing means to process the partial image data, and the reference data is cached data used by the image processing means. The image processing apparatus according to claim 1, characterized in that The memory control circuit is further characterized in that the image processing means allocates a storage area of reference data for processing the partial image data, and the reference data is a look-up table used by the image processing means. The image processing apparatus according to claim 1, wherein Further, in the memory control circuit, the image processing means allocates a storage area of reference data for processing the partial image data, and the image processing means used by the image processing mode of the image processing apparatus makes the shared memory 2. The image processing apparatus according to claim 1, wherein types of reference data to be stored in the storage area of the reference data to be allocated are made different.   The image processing apparatus according to claim 1, wherein the input buffer area is allocated based on a DMA transfer amount.   The image processing apparatus according to claim 1, wherein the output buffer area is allocated based on a DMA transfer amount.   2. The image processing apparatus according to claim 1, wherein said partial image data before being processed by said image processing means is input by DMA transfer from said external storage to said input buffer area.   2. The image processing apparatus according to claim 1, wherein a storage area capable of double buffering is secured in the input buffer area.   2. The image processing apparatus according to claim 1, wherein a storage area capable of double buffering is secured in the output buffer area. The data amount of the partial image data before processing by the image processing means and the data amount of the partial image data after processing by the image processing means are predetermined, and the memory control circuit The image processing means allocates at least a part of the remaining storage area allocated the input buffer area and the output buffer area to a memory as a storage area of reference data for processing the partial image data. The image processing apparatus according to claim 1.   11. The image according to claim 10, wherein the memory control circuit stops the clock supply to the shared memory of the remaining area to which the input buffer area, the output buffer area, and the storage area of the reference data are allocated. Processing unit. A plurality of image processing means for processing image data held in external storage external to the image processing apparatus for each partial image data;
An interface with the external storage,
A shared memory composed of a plurality of SRAMs internally included in the image processing apparatus, which is shared by the plurality of image processing units and holds data processed by the image processing unit through the interface ;
A control method of an image processing apparatus having
An input buffer area for temporarily holding the partial image data that is the partial image data input from the external storage to the image processing means from the external storage in the shared memory and before the image processing means processes the image; It said image processing means to be output from the processing means to the external memory has a memory control step of assigning and an output buffer area temporarily retaining the partial image data after the process, a method for controlling the image processing apparatus. Computer,
A plurality of image processing means for processing image data held in external storage external to the image processing apparatus for each partial image data;
An interface with the external storage,
The image processing means is shared by a plurality of SRAMs internally included in the image processing apparatus, which shares the plurality of image processing means and holds data processed by the image processing means through the interface. An input buffer area for temporarily holding the partial image data which is the partial image data input from the external storage and before being processed by the image processing means, and is outputted from the image processing means to the external storage program for functioning as the image processing unit memory control means for assigning the output buffer area, the temporarily holding the partial image data after being processed that.

Images