JP2019047725A - Step-up circuit, semiconductor device, and method for controlling step-up circuit - Google Patents

Abstract

To provide a step-up circuit capable of suppressing an activation trouble of a step-up unit, a semiconductor device, and a method for controlling the step-up circuit.SOLUTION: A method for controlling a step-up circuit comprises the steps of: generating a first potential by a reference voltage generation circuit and supplying the generated potential to a first potential line; starting the step-up control unit connected to a second potential line on the basis of the first potential and controlling the step-up unit by the step-up control unit; supplying the second potential stepped up from the first potential by the step-up unit to the second potential line; and controlling the switch connected to the first potential line and the second potential line by the control circuit on the basis of a potential difference between the first potential and the second potential.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a booster circuit, a semiconductor device, and a control method of the booster circuit.

  In general, a booster circuit is known which boosts and outputs a predetermined voltage such as a reference voltage. In the booster circuit, boosting of a predetermined voltage is performed based on a control signal (for example, a clock signal or the like) supplied by the boost control circuit. Some boost control circuits use a boosted voltage boosted by a boost circuit as a power supply.

  In such a step-up control circuit, when the step-up circuit is powered on, it may not be able to properly start up.

  For example, immediately after the start of the operation when the power is supplied to the boosting circuit, the boosting voltage is 0 V because the boosting is not yet performed. Therefore, the power supply of the boost control circuit also becomes 0 V and can not start up. Since the boost control circuit does not start, the boost circuit does not perform boosting.

  In a booster circuit, techniques for avoiding such a state are known. For example, Patent Document 1 describes a technique of supplying a constant potential from a start-up circuit at the start of oscillation of an oscillation circuit that uses a voltage boosted by a booster circuit as a power supply and supplies a clock signal to the booster circuit.

  For example, there is known a booster circuit in which a reference voltage line to which a reference voltage is supplied and a boosted voltage line for supplying a boosted voltage as a power supply voltage to a booster circuit control unit which is a boost control circuit are connected by a diode FIG. 8: refer to the booster circuit 100). In the booster circuit 100, when the power is turned on, the reference voltage supplied to the reference voltage line is supplied as the power supply voltage to the booster circuit control unit via the boosted voltage line, and the booster circuit is based on the supplied power supply voltage. The controller starts up.

Japanese Patent Application Publication No. 08-185240

  However, in the above-described conventional booster circuit 100, since the reference voltage is supplied to the boosted voltage line through the diode, the voltage of the power supply voltage supplied to the boosted voltage line is dropped by the diode and the reference voltage is generated. The potential drops from the potential of the voltage to the forward voltage drop VF of the diode. The occurrence of the voltage drop may cause a problem in boosting by the booster. For example, when the reference voltage is a low voltage, the potential of the supplied power supply voltage falls below the voltage necessary for starting the booster circuit controller due to the voltage drop, and the booster circuit controller does not start, so the booster may not start. Will occur.

  The present invention has been proposed to solve the above-described problems, and it is an object of the present invention to provide a booster circuit, a semiconductor device, and a control method of the booster circuit that can suppress a failure in activation of the booster unit. I assume.

  In order to achieve the above object, a booster circuit according to the present invention generates a first potential and supplies a reference voltage generation circuit to supply to a first potential line, and a second potential obtained by boosting the first potential. A boosting unit for supplying a second potential line, a boosting control unit connected to the second potential line and controlling the boosting unit based on the second potential, the first potential line, and the first potential line And a control circuit configured to control the switch based on a potential difference between the first potential and the second potential.

  Further, the semiconductor device of the present invention outputs the second potential boosted by the booster as a drive potential, and the display circuit causes the liquid crystal display device to display the drive potential. And a drive circuit for supplying each pixel of the liquid crystal display device.

  Further, in the control method of the booster circuit according to the present invention, the reference voltage generation circuit generates a first potential and supplies the first potential to a first potential line, and the booster unit boosts the first potential. A step of supplying a second potential to the second potential line; a step of controlling the booster based on the second potential connected to the second potential line by the boost control section; and a control circuit Controlling a switch connected to the first potential line and the second potential line based on a potential difference between the first potential and the second potential.

  According to the present invention, it is possible to suppress the failure of the activation of the booster unit.

It is a schematic block diagram which shows an example of the booster circuit of 1st Embodiment. It is a circuit diagram showing an example of a comparator of a 1st embodiment. FIG. 8 is an explanatory diagram for explaining a relationship among a reference voltage VL1, a boosted voltage VL2, a threshold voltage of a comparator, and on / off of a switch element in the booster circuit of the first embodiment. FIG. 16 is a time chart showing a temporal change of a waveform of the potential of the boosted voltage line 27 at the time of power application of the booster circuit 10 when the potential of the reference voltage VL1 is 1.0 V. (1) shows the waveform of the potential of the boosted voltage line in the conventional booster circuit. (2) shows the waveform of the potential of the boosted voltage line in the booster circuit of the present embodiment. It is a circuit diagram showing an example of a comparator of a 2nd embodiment. It is a schematic block diagram which shows an example of the booster circuit of 3rd Embodiment. It is a schematic block diagram for demonstrating the case where the booster circuit of this invention is applied to a LCD driver. It is a schematic block diagram which shows an example of the conventional booster circuit.

First Embodiment
Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic configuration diagram of an example of the booster circuit of the present embodiment.

  As shown in FIG. 1, the booster circuit 10 of the present embodiment includes a booster circuit control unit 12, a comparator 14, a battery 18, a reference voltage generation source 20, and a booster unit 22.

  The high potential side of the battery 18 is connected to the reference voltage generation source 20, and the low potential side is connected to the ground line 23 which provides the ground potential. The battery voltage supplied from the battery 18 is used as a power supply (power supply voltage VDD) of the reference voltage generation source 20.

  The reference voltage generation source 20 has a function of generating the reference voltage VL1 based on the power supply voltage VDD and supplying it to the reference voltage line 25. The reference voltage VL1 supplied to the reference voltage line 25 by the reference voltage generation source 20 of the present embodiment is not affected by the step-up state of the booster 22 and is changed by the influence of the power supply voltage VDD.

  The boosting circuit control unit 12 has a function of controlling the boosting operation of the boosting unit 22 by generating a clock signal and outputting the clock signal to the boosting unit 22. The booster circuit control unit 12 is connected to the boosted voltage line 27, and operates using the voltage (boosted voltage VL2) supplied to the boosted voltage line 27 as a power supply voltage.

  The switch element 16 has a function of controlling the voltage supplied to the boosted voltage line 27 (details will be described later). In the booster circuit 10 of the present embodiment, a PMOS transistor is used as the switch element 16. One main terminal of switch element 16 is connected to boosted voltage line 27, and the other main terminal is connected to reference voltage line 25.

  Comparator 14 is connected to reference voltage line 25 and boosted voltage line 27 and is a voltage difference (potential difference) between reference voltage VL1 supplied to reference voltage line 25 and boosted voltage VL2 supplied to boosted voltage line 27. And a function to control the on / off of the switch element 16 based on the above (details will be described later).

  The booster 22 includes capacitive elements C1, C2, and C3 and switch elements SW1, SW2, SW3, and SW4. The boosting unit 22 has a function of supplying a boosted voltage line 27 with a boosted voltage VL2 obtained by doubling the reference voltage VL1 supplied to the reference voltage line 25. As a specific example, when the reference voltage VL1 is 1.2 V, the booster 22 supplies the boosted voltage VL2 boosted to 2.4 V to the boosted voltage line 27. The boosted voltage VL2 thus boosted is output from the OUT terminal to the outside of the booster circuit 10.

  One end of the capacitive element C1 is connected to the reference voltage line 25 via the switch element SW1, and is connected to the boosted voltage line 27 via the switch element SW3. The other end of the capacitive element C1 is connected to the ground line 23 via the switch element SW2, and is connected to the reference voltage line 25 via the switch element SW4. One end of the capacitive element C 2 is connected to the reference voltage line 25, and the other end is connected to the ground line 23. One end of the capacitive element C3 is connected to the boosted voltage line 27, and the other end is connected to the ground line 23.

  The boosting operation of the booster circuit 10 will be described.

  First, in response to the clock signal supplied from the booster circuit control unit 12, the switch elements SW1 and SW2 of the booster unit 22 are turned on, and the switch elements SW3 and SW4 are turned off. One end of the capacitive element C1 is connected to the reference voltage line 25, and the other end is connected to the ground line 23. Since the capacitive elements C1 and C2 are connected in parallel, the reference voltage VL1 is stored in the capacitive elements C1 and C2, respectively.

  Next, in response to the clock signal supplied from the booster circuit control unit 12, the switch elements SW1 and SW2 of the booster 22 are turned off, and the switch elements SW3 and SW4 are turned on. One end of the capacitive element C1 is connected to the boosted voltage line 27, and the other end is connected to the reference voltage line 25. Since the capacitive elements C1 and C2 are connected in series, the reference voltage VL1 + the reference voltage VL1 is supplied to the boosted voltage line 27 and output from the OUT terminal.

  The booster 22 repeatedly outputs the boosted voltage VL2 obtained by twice boosting the reference voltage VL1 from the OUT terminal to the outside by repeating charging and discharging of the capacitive elements C1 and C2.

  As described above, the boosting operation of the boosting unit 22 is performed based on the clock signal supplied from the boosting circuit control unit 12. In order for the booster circuit control unit 12 to generate a clock signal, the power supply voltage (boosted voltage VL2) supplied by the boosted voltage line 27 needs to be equal to or higher than the voltage necessary for starting up the booster circuit control unit 12.

  However, when the power of the booster circuit 10 is turned on (when switched from off to on), the booster 22 has not yet started operation, and the boosted voltage VL2 is 0V. Further, even after the start-up of the booster 22 is started, it takes a predetermined time for the boosted voltage VL2 to reach twice the potential of the reference voltage VL1. Therefore, the boosted voltage VL2 may fall below the reference voltage VL1.

  In this case, in the booster circuit 10 according to the present embodiment, the switch element 16 supplies the reference voltage VL1 to the boosted voltage line 27, thereby supplying a voltage necessary for starting up the booster circuit control unit 12. The on / off of the switch element 16 is controlled by the comparator 14.

  In FIG. 2, the circuit diagram of an example of the comparator 14 of this Embodiment is shown.

  The comparator 14 includes PMOS transistors 30, 32, 34, 36, 38, 40 and NMOS transistors 42, 44, 46, 48.

  One main terminal of the PMOS transistor 30 is connected to the reference voltage line 25, the other main terminal is connected to the NMOS transistor 42, and the control terminal is connected to the other main terminal. One main terminal of the PMOS transistor 32 is connected to the boosted voltage line 27, the other main terminal is connected to the NMOS transistor 44, and the control terminal is connected to the other terminal of the PMOS transistor 30. In the comparator 14 of the present embodiment, the dimension of the PMOS transistor 32 is larger than the dimension of the PMOS transistor 30 (size of transistor: gate width / gate length ratio).

  One main terminal of PMOS transistor 38 is connected to boosted voltage line 27, the other main terminal is connected to NMOS transistor 46, and the control terminal is connected to the other terminal of PMOS transistor 32 and the other terminal of PMOS transistor 36. ing. One main terminal of the PMOS transistor 40 is connected to the boosted voltage line 27, the other main terminal is connected to the NMOS transistor 48, and the control terminal is connected to the other terminal of the PMOS transistor 38.

  Further, one main terminal of the PMOS transistor 34 is connected to the boosted voltage line 27, the other main terminal is connected to the PMOS transistor 36, and the control terminal is connected to the other terminal of the PMOS transistor 38. One main terminal of the PMOS transistor 36 is connected to the other main terminal of the PMOS transistor 34, the other main terminal is connected to the other main terminal of the PMOS transistor 32, and the control terminal is connected to the other terminal of the PMOS transistor 30. It is done.

  One main terminal of the NMOS transistor 42 is connected to the PMOS transistor 30, and the other main terminal is connected to the ground line 23. One main terminal of the NMOS transistor 44 is connected to the PMOS transistor 32, and the other main terminal is connected to the ground line 23. One main terminal of the NMOS transistor 46 is connected to the PMOS transistor 38, and the other main terminal is connected to the ground line 23. One main terminal of the NMOS transistor 48 is connected to the PMOS transistor 40, and the other main terminal is connected to the ground line 23. Control terminals of the NMOS transistors 42, 44, 46, 48 are connected to a bias line 29 to which a bias voltage is supplied. Therefore, a bias voltage is applied to the NMOS transistors 42, 44, 46, 48 as a gate voltage.

  FIG. 3 is an explanatory diagram for explaining the relationship among the reference voltage VL1, the boosted voltage VL2, the threshold voltage of the comparator 14, and the on / off of the switch element 16 in the booster circuit 10.

  The NMOS transistors 42, 44, 46 and 48 are turned on by the bias voltage supplied from the bias line 29, regardless of the potential of the boosted voltage VL2.

  When boosted voltage VL2 is low potential (for example, when power is turned on: 0 V), since reference voltage VL1 is higher potential, boosted voltage VL2 is less than the threshold voltage of comparator 14 as shown in FIG. Become. The comparator 14 supplies an L level electric potential (0 V) to the control terminal of the switch element 16 as a gate voltage, so the switch element 16 is turned on.

  When switch element 16 is in the on state, reference voltage line 25 and boosted voltage line 27 are connected, and reference voltage VL1 is supplied from reference voltage line 25 to boosted voltage line 27. Therefore, the reference voltage VL1 is supplied as the power supply voltage to the booster circuit control unit 12 via the boosted voltage line 27. The booster circuit control unit 12 is started based on the reference voltage VL1. By the activation of the booster circuit control unit 12, the booster unit 22 is activated, and the potential of the boosted voltage VL2 supplied to the boosted voltage line 27 rises. Specifically, the potential of the boosted voltage VL2 rises from 0 V to a potential twice the reference voltage VL1.

  When the potential of the boosted voltage VL2 rises and approaches the potential of the reference voltage VL1, as shown in FIG. 3, the boosted voltage VL2 becomes equal to or higher than the threshold voltage of the comparator 14.

  The L level potential is supplied to the control terminals of the PMOS transistor 32 and the PMOS transistor 36 by the PMOS transistor 30, and the PMOS transistors 32 and 36 are turned on. The control terminal of the PMOS transistor 38 is supplied with an H level potential, and the PMOS transistor 38 is turned off. The control terminal of the PMOS transistors 34 and 40 is supplied with an L level potential, and the PMOS transistors 34 and 40 are turned on.

Therefore, the potential of the H level (reference voltage VL1) is supplied to the control terminal of the switch element 16, and the switch element 16 is turned off. When switch element 16 is turned off, reference voltage line 25 and boosted voltage line 27 are disconnected, and the supply of reference voltage VL1 from reference voltage line 25 to boosted voltage line 27 is stopped. Since the potential of the boosted voltage VL2 supplied to the boosted voltage line 27 by the booster 22 is already high enough, the booster circuit controller 12 operates without any problem.
Second Embodiment
The entire configuration of the booster circuit 10 according to the present embodiment is the same as that of the booster circuit 10 (FIG. 1) according to the first embodiment, and thus the description of the overall configuration of the booster circuit 10 is omitted. In the booster circuit 10 of the present embodiment, the configuration of the comparator is different from that of the first embodiment, so the configuration of the comparator of the present embodiment will be described.

  FIG. 5 shows a circuit diagram of an example of the comparator of this embodiment.

  Unlike the comparator 14 (see FIG. 2) of the first embodiment, the comparator 74 shown in FIG. 5 includes a current control unit 59.

  The current control unit 59 is provided between the NMOS transistors 42, 44, 46, 48 and the ground line 23. The current control unit 59 has a function of disconnecting the NMOS transistors 42, 44, 46, 48 and the ground line 23 based on the start-up signal.

  The current control unit 59 includes NMOS transistors 52, 54, 55, 56, 58. One main terminal of the NMOS transistor 52 is connected to the NMOS transistor 42, and the other main terminal is connected to the ground line 23. One main terminal of the NMOS transistor 54 is connected to the NMOS transistor 44, and the other main terminal is connected to the ground line 23. One main terminal of the NMOS transistor 56 is connected to the NMOS transistor 46, and the other main terminal is connected to the ground line 23. One main terminal of the NMOS transistor 58 is connected to the NMOS transistor 48, and the other main terminal is connected to the ground line 23. Control terminals of the NMOS transistors 52, 54, 56, 58 are connected to a start-up line 51 to which a start-up signal is supplied. Therefore, the potential of the start-up signal is applied to the NMOS transistors 52, 54, 56, 58 as the gate voltage. In addition, the NMOS transistor 55 has one main terminal connected to the control terminals of the PMOS transistor 34 and the PMOS transistor 40 and the other main terminal connected to the ground line 23. An inverted signal of Therefore, on / off of the NMOS transistors 52, 54, 56, 58 and the NMOS transistor 55 is reversed.

  Further, the comparator 74 of the present embodiment includes the PMOS transistor 50 having one main terminal connected to the boosted voltage line 27 and the other main terminal connected to the control terminal of the PMOS transistor 38. The control terminal of the PMOS transistor 50 is supplied with a start-up signal.

  The start-up signal indicates that the potential of the boosted voltage VL2 becomes equal to or higher than the reference voltage VL1 or the potential of the boosted voltage VL2 is equal to or higher than the threshold of the comparator 74 when the booster circuit 10 is activated. It is a signal which becomes H level during a period until it becomes (hereinafter referred to as start-up period) and becomes L level during the other periods. The start-up signal is a signal supplied from the outside of the comparator 74 (or the outside of the booster circuit 10) (not shown).

  In the start-up period in which the start-up signal is at the H level, the NMOS transistors 52, 54, 56, 58 are turned on, and the NMOS transistor 55 is turned off. Also, during the other period of the L level of the start-up signal, the NMOS transistors 52, 54, 56, 58 are turned off, and the NMOS transistor 55 is turned on.

  That is, in the other period, the current control unit 59 disconnects the NMOS transistors 42, 44, 46, 48, that is, the PMOS transistors 30, 32, 38, 40 from the ground line 23.

  Further, in the comparator 74 of the present embodiment, the PMOS transistor 50 is turned off during the startup period, and is turned on during the other periods. In the other periods, the boosted voltage VL2 at the H level is supplied to the control terminal of the PMOS transistor 38, so the PMOS transistor 38 is turned off. Also, in the other period, the control terminals of the PMOS transistor 34 and the PMOS transistor 40 are connected to the ground line 23 by the NMOS transistor 55 of the current control unit 59. As described above, in the comparator 74 according to the present embodiment, the potential supplied to the control terminal of the PMOS transistor 40 is controlled based on the start-up signal.

Therefore, in the comparator 74 of the present embodiment, a current flows in the comparator 74 to operate in the startup period, and in the other periods, the current path in the comparator 74 is disconnected and the operation is stopped. Therefore, in the comparator 14 of the present embodiment, current consumption can be suppressed in other periods.
Third Embodiment
FIG. 6 shows a schematic configuration diagram of an example of the booster circuit of the present embodiment.

  As shown in FIG. 6, the booster circuit 10 of this embodiment includes a switch element between the switch element 16 and the reference voltage line 25 of the booster circuit 10 (FIG. 1) of the first embodiment. It is the same configuration as that of the first embodiment. The comparator 14 has the same configuration (see FIG. 5) as the comparator 14 of the second embodiment.

  One main terminal of the switch element 60 is connected to the switch element 16, and the other main terminal is connected to the reference voltage line 25. The control terminal of the switch element 60 is supplied with an inverted signal of the start-up signal. In the booster circuit 10 of the present embodiment, the start-up signal supplied to the control terminal of the switch element 60 is the same as the start-up signal in the second embodiment.

  Therefore, the switch element 60 is turned on in the start-up period. In the other periods, the switch element 60 is in the off state.

  Thereby, reference voltage line 25 and boosted voltage line 27 can be disconnected from each other in the other period.

  For example, when the potential of the reference voltage VL1 is higher than the potential of the boosted voltage VL2 outside the startup period, a voltage higher than the convergence voltage of the booster circuit 10 (booster 22) is supplied to the reference voltage line 25 by the switch element 16. Can be suppressed. Further, when the booster circuit 10 is stopped, the switch element 16 can suppress the supply of the reference voltage VL1 from the reference voltage line 25 to the boosted voltage line 27.

  As described above, in the booster circuit 10 of each of the above embodiments, the switch element 16 is provided between the reference voltage line 25 and the boosted voltage line 27, and the control terminal of the switch element 16 is an output of the comparator 14. It is connected to the. The comparator 14 controls the on / off of the switch element 16 in accordance with the potential difference between the potential of the reference voltage VL1 supplied to the reference voltage line 25 and the potential of the boosted voltage VL2 supplied to the boosted voltage line 27. In the booster circuit 10, when the power of the booster circuit 10 is turned on or the like, the boosted voltage VL2 is lower than the reference voltage VL1 and is less than the threshold voltage of the comparator 14, the switch element 16 is turned on to reference voltage VL1. Is supplied to the boosted voltage line 27. On the other hand, in the booster circuit 10, when the potential of the boosted voltage VL2 is equal to or higher than the potential of the reference voltage VL1 and higher than the threshold voltage of the comparator 14, the switch element 16 is turned off and the boosted voltage VL2 to the boosted voltage line 27 Supply is stopped.

  Further, in the comparator 14 of each of the above embodiments, the dimension of the PMOS transistor 32 is made larger than the dimension of the PMOS transistor 30 (size of the transistor: gate width / gate length ratio). Thereby, the switch element 16 can be turned off before the potential of the boosted voltage VL2 exceeds the potential of the reference voltage VL1. That is, as shown in FIG. 3, the threshold voltage of the comparator 14 can be made lower than the reference voltage VL1. Therefore, according to the comparator 14, the backflow from the boosted voltage line 27 to the reference voltage line 25 can be suppressed.

  In each of the above embodiments, the threshold of the comparator 14 when the potential of the boosted voltage VL2 rises is affected by the PMOS transistor 36, and the threshold of the comparator 14 when the potential of the boosted voltage VL2 decreases. The threshold is influenced by the PMOS transistor 34. Therefore, as shown in FIG. 3, the threshold of the comparator 14 when the potential of the boosted voltage VL2 is rising is higher, and the comparator 14 has the hysteresis width shown in FIG. Therefore, chattering of the comparator 14 can be suppressed. In addition, the comparator 14 has hysteresis so that it is quick when the switch element 16 is turned off and is delayed when the switch element 16 is turned on. Thereby, it is possible to suppress the backflow from boosted voltage line 27 to reference voltage line 25.

  Further, since the switch element 16 is connected in bulk to the boosted voltage line 27, it can be considered that a diode from the reference voltage line 25 to the boosted voltage line 27 is formed. Therefore, current can be supplied even if the boosted voltage VL2 is low and in an unstable state.

  Further, in the above embodiments, the bias voltage supplied to the NMOS transistors 42, 44, 46, 48 by the bias line 29 is supplied from a stable power supply. Thereby, even if boosted voltage VL2 is at a low potential, NMOS transistor 48 is stably in the ON state, and therefore the potential supplied to the control terminal of switch element 16 can be forced to L level. , And the switch element 16 can be turned on.

  A conventional booster circuit 100 will be described as a comparative example. FIG. 8 shows a schematic configuration diagram of an example of a conventional booster circuit 100. As shown in FIG. In the conventional booster circuit 100, as shown in FIG. 8, a diode 115 is provided instead of the comparator 14 and the switch element 16 in the booster circuit 10 of each of the above embodiments. The diode 115 has an anode connected to the reference voltage line 25 and a cathode connected to the boosted voltage line 27. Thus, when the potential of reference voltage VL1 supplied to reference voltage line 25 is higher than the potential of boosted voltage VL2 supplied to boosted voltage line 27, reference voltage VL1 is boosted voltage line 27 via diode 115. Supplied to At this time, due to the forward voltage drop VF of the diode 115, the potential actually supplied to the boosted voltage line 27 becomes the potential-forward voltage drop VF of the reference voltage VL1.

  On the other hand, in the booster circuit 10 of each of the above embodiments, since the reference voltage VL1 is supplied from the reference voltage line 25 to the boosted voltage line 27 via the switch element 16, the voltage drop is as shown in the booster circuit 100 of the comparative example. The potential itself of the reference voltage VL1 is directly supplied to the boosted voltage line 27 without being generated.

  As a specific example, FIG. 4 shows the temporal change of the waveform of the potential of the boosted voltage line 27 when the power of the booster circuit 10 is turned on when the potential of the reference voltage VL1 is 1.0V. FIG. 4 (1) shows the waveform of the potential of the boosted voltage line 27 in the conventional booster circuit 100, and FIG. 4 (2) shows the potential of the boosted voltage line 27 in the booster circuit 10 of each of the above embodiments. The waveform is shown. As shown in FIG. 4 (1), in the conventional booster circuit 100, the potential of the boosted voltage line 27 rises only to 0.65 V due to the forward voltage drop of the diode 115. On the other hand, as shown in FIG. 4 (2), in the booster circuit 10 of each of the above embodiments, the potential of the boosted voltage line 27 rapidly rises to approximately 1.0V.

  For example, when the battery 18 is a single battery and the voltage is as low as about 1.5 V as a specific example, if the battery 18 is degraded and becomes so-called, the power supply voltage VDD is as low as about 1.0 V The potential drops. In such a case, in the conventional booster circuit 100, as shown in FIG. 4 (1), the potential of the boosted voltage line 27 becomes low, which may cause the booster circuit control unit 12 not to be properly activated. Therefore, problems may occur in the activation of the booster 22.

  On the other hand, in the booster circuit 10 of each of the above-described embodiments, as shown in FIG. 4 (2), the potential itself of the reference voltage VL1 is directly supplied to the booster voltage line 27. Launch to Therefore, the malfunction of starting of the booster 22 can be suppressed.

  Although the boosted voltage VL2 boosted by the booster circuit 10 of each of the above embodiments is supplied to a load circuit outside the booster circuit 10, the load circuit is not particularly limited. For example, the present invention can be applied to an LCD (Liquid Crystal Display) driver of a liquid crystal display device. FIG. 7 shows a schematic configuration diagram for explaining the case where the booster circuit 10 of each of the above embodiments is applied to an LCD driver. By applying a drive voltage to each pixel of the liquid crystal display 84 by the LCD driver 80 based on the display data, the liquid crystal display 84 displays an image according to the display data. The LCD driver 80 includes the booster circuit 10 and drive circuits 86 and 87. The booster circuit 10 boosts the reference voltage VL1 to generate a drive voltage based on an instruction of the controller 82, and supplies the drive voltage to the drive circuits 86 and 88. The drive circuits 86 and 88 apply a drive voltage to the corresponding pixels of the liquid crystal display 84 based on the instruction of the controller 82. Needless to say, the application example of the booster circuit 10 is not limited to the LCD driver.

  Moreover, in each said embodiment, although the comparator 14 and the switch element 16 were connected to the reference voltage line 25, you may be connected to another signal line. In this case, an initial voltage for activating the booster circuit control unit 12 may be supplied to the other new combination.

  In the comparator 14 of each of the above-described embodiments, the PMOS transistors 34 and 36 are provided. However, the comparators 14 and 36 may not be provided. As described above, since the comparator 14 has hysteresis by providing the PMOS transistors 34 and 36, it is preferable to include the PMOS transistors 34 and 36 as in the comparator 14 of each of the above embodiments.

  In the booster circuit 10 of each of the above embodiments, the two-step booster circuit that doubles the potential of the reference voltage VL1 has been described. However, the present invention is not limited thereto. Good. In such a case, the number of capacitive elements may be increased each time the boosting step is increased to vertically stack the capacitive elements C1. At this time, the boosted voltage VL2 supplied to the boosted voltage line 27 has the highest potential.

  Further, the configurations and operations of the booster circuit 10, the comparator 14, the switch element 16 and the like described in the other embodiments above are merely examples, and can be changed according to the situation without departing from the scope of the present invention. It goes without saying that

10 Step-up circuit 12 Step-up circuit control unit (step-up control unit)
22 Booster 14 Comparator (Control circuit)
16 switch element (switch)
23 Ground line (third potential line)
25 Reference voltage line (first potential line)
27 Boost voltage line (second potential line)
30 PMOS transistor (first PMOS transistor)
32 PMOS transistor (second PMOS transistor)
34 PMOS transistor (fifth PMOS transistor)
36 PMOS transistor (sixth PMOS transistor)
38 PMOS transistor (third PMOS transistor)
40 PMOS transistor (fourth PMOS transistor)
42 NMOS transistor (first NMOS transistor)
44 NMOS transistor (second NMOS transistor)
46 NMOS transistor (third NMOS transistor)
48 NMOS transistor (fourth NMOS transistor)
59 Current control unit (switching unit)
60 switch element (control switch)
80 LCD driver (semiconductor device)
86, 88 drive circuit

Claims (1)

Generating a first potential by a reference voltage generation circuit and supplying the first potential to the first potential line;
The step-up control unit connected to the second potential line is activated based on the first potential to control the step-up unit;
Supplying a second potential obtained by boosting the first potential by the booster to the second potential line;
Controlling a switch connected to the first potential line and the second potential line based on a potential difference between the first potential and the second potential by the control circuit;
Control method of the booster circuit provided with