JP2019047046A - Integrated circuit, computer, and electronic equipment - Google Patents

Abstract

To provide a novel integrated circuit.SOLUTION: An integrated circuit comprises a plurality of arithmetic circuits equivalent to a hidden layer and an output layer of a neural network. The arithmetic circuit comprises a product-sum arithmetic circuit and a hierarchy output circuit. The arithmetic circuit has a function to output third data corresponding to product-sum arithmetic results of first data and second data. The hierarchy output circuit has a function to convert the third data on the basis of an activation function and output analog data or multivalued digital data. The analog data or the multivalued digital data is input to a product-sum arithmetic circuit of the next arithmetic circuit without being converted into binary digital data. Variations in transistor characteristics constituting a memory cell can be reduced by unifying channel length directions of transistors of the memory cell between a plurality of product-sum arithmetic circuits.SELECTED DRAWING: Figure 3

Description

One embodiment of the present invention relates to an integrated circuit, a computer, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention disclosed in this specification and the like includes a semiconductor device, an imaging device, a display device, a light emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, and an input / output. An apparatus, a method of driving them, or a method of manufacturing them can be mentioned as an example.

Further, in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, and the like are one embodiment of a semiconductor device. In addition, a display device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may include a semiconductor device.

With the development of information technology such as Internet of Things (IoT) and Artificial Intelligence (AI), the amount of data handled tends to increase. In order for electronic devices to use information technologies such as IoT and AI, semiconductor devices capable of storing a large amount of data are required. Furthermore, in order to use the electronic device comfortably, there is a demand for a semiconductor device that can be treated at high speed.

Patent Document 1 discloses a configuration of a product-sum operation circuit whose circuit scale is reduced by a method of using a memory in a digital circuit that performs product-sum operation.

JP, 1997-319730, A

An object of one embodiment of the present invention is to provide a novel integrated circuit or semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide an integrated circuit or a semiconductor device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide an integrated circuit or a semiconductor device which can operate at high speed. Alternatively, it is an object of one embodiment of the present invention to provide an integrated circuit or a semiconductor device with a small area. Alternatively, it is an object of one embodiment of the present invention to provide a highly reliable integrated circuit or semiconductor device.

Note that one aspect of the present invention does not necessarily have to solve all the problems described above, as long as at least one problem can be solved. In addition, the above description of the problems does not disturb the existence of other problems. Problems other than these are naturally apparent from the description of the specification, claims, drawings, and the like, and the extraction of problems other than these is apparent from the descriptions of the specification, claims, drawings, and the like. Is possible.

One embodiment of the present invention includes a first arithmetic circuit and a second arithmetic circuit, and the first arithmetic circuit includes a first product-sum arithmetic circuit having a first transistor; And a second arithmetic circuit includes a second product-sum operation circuit having a second transistor, and a second hierarchical output circuit, and the channel length of the first transistor The direction and the channel length direction of the second transistor are parallel, and the first product-sum operation circuit and the second product-sum operation circuit correspond to the result of the product-sum operation of the first data and the second data. The first hierarchical output circuit and the second hierarchical output circuit convert the third data based on the activation function, and outputs analog data or multilevel digital data. The second product-sum operation circuit has a function of outputting data, and the first product output circuit An integrated circuit that forces the analog data or multilevel digital data is input.

In the above, the channel width direction of the first transistor and the channel width direction of the second transistor are preferably parallel.

In the above, it is preferable that the first transistor and the second transistor include a metal oxide in the channel formation region.

Another embodiment of the present invention is a computer including an operation unit including the above integrated circuit, a processing unit, and a storage unit.

Another embodiment of the present invention is an electronic device including the above integrated circuit or computer.

According to one aspect of the present invention, a novel integrated circuit or semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an integrated circuit or semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, an integrated circuit or a semiconductor device which can operate at high speed can be provided. Alternatively, according to one embodiment of the present invention, an integrated circuit or a semiconductor device with a small area can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable integrated circuit or semiconductor device can be provided.

Note that the description of these effects does not disturb the existence of other effects. In addition, one aspect of the present invention does not necessarily have to have all of these effects. The effects other than these are naturally apparent from the description of the specification, claims, drawings, and the like, and the effects other than these are extracted from the descriptions of the specification, claims, drawings, and the like. Is possible.

FIG. 2 shows an example of the configuration of an integrated circuit. The figure which shows the structural example of a neural network. FIG. 2 shows an example of the configuration of an integrated circuit. FIG. 2 shows an example of the configuration of an integrated circuit. FIG. 2 shows an example of the configuration of an integrated circuit. FIG. 2 shows an example of the configuration of a circuit. FIG. 2 shows an example of the configuration of a memory cell. Timing chart. FIG. 2 is a diagram showing an example of the configuration of a drive circuit. FIG. 2 shows an example of the configuration of an integrated circuit. The figure which shows the structural example of a computer. FIG. 7 shows a structural example of a semiconductor device. FIG. 7 shows a structural example of a transistor. FIG. 2 is a diagram showing an example of the configuration of an electronic device and a system. The figure which shows the structural example of a parallel computer, a computer, and a PC card. A figure showing an example of composition of a system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and it is easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Be done. Therefore, the present invention should not be construed as being limited to the following description of the embodiments.

In the present specification and the like, metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like. For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case where the metal oxide has at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be called a metal oxide semiconductor, which is abbreviated as OS. Hereinafter, a transistor including a metal oxide in a channel formation region is also referred to as an OS transistor.

In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride. Details of the metal oxide will be described later.

Further, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected, and X and Y function. It is assumed that the case where they are connected as well as the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, the present invention is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or a sentence, and anything other than the connection relationship shown in a figure or a sentence is also described in the figure or the sentence. Here, X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).

As an example in the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) capable of electrically connecting X and Y An element (e.g., a switch, a transistor, a capacitive element, an inductor) that enables an electrical connection between X and Y when the element, the light emitting element, the load, etc. is not connected between X and Y , X, and Y are connected without interposing a resistance element, a diode, a display element, a light emitting element, a load, and the like.

As an example when X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) which enables electrical connection of X and Y One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on and off. That is, the switch is turned on or off and has a function of controlling whether current flows or not. Alternatively, the switch has a function of selecting and switching a path through which current flows. In addition, when X and Y are electrically connected, the case where X and Y are directly connected shall be included.

As an example when X and Y are functionally connected, a circuit (for example, a logic circuit (for example, an inverter, a NAND circuit, a NOR circuit, etc.) that enables functional connection of X and Y, signal conversion Circuits (DA converter circuit, AD converter circuit, gamma correction circuit, etc.), potential level converter circuits (power supply circuits (boost circuit, step-down circuit etc.), level shifter circuits for changing the potential level of signals, etc.) voltage source, current source, switching A circuit, an amplifier circuit (a circuit capable of increasing the signal amplitude or current amount, etc., an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc. It is possible to connect one or more in between. As an example, even if another circuit is interposed between X and Y, X and Y are functionally connected if the signal output from X is transmitted to Y. Do. Note that when X and Y are functionally connected, the case where X and Y are directly connected and the case where X and Y are electrically connected are included.

In addition, when it is explicitly stated that X and Y are electrically connected, X and Y are electrically connected (ie, between X and Y). When X and Y are functionally connected (that is, functionally connected with another circuit between X and Y). And X and Y are directly connected (that is, when X and Y are connected without sandwiching another element or another circuit), the present specification. Shall be disclosed in the That is, in the case where it is explicitly stated that it is electrically connected, the same contents as in the case where it is only explicitly stated that it is connected are disclosed in the present specification etc. It shall be done.

Further, even in the case in which independent components are illustrated as being electrically connected in the drawings, one component may have the functions of a plurality of components in combination. is there. For example, in the case where part of the wiring also functions as an electrode, one conductive film combines the function of the wiring and the function of both components of the function of the electrode. Therefore, the term "electrically connected" in this specification also falls under the category of one such conductive film, even when it has the function of a plurality of components.

Further, in the present specification and the like, multivalued digital data refers to digital data of three or more values.

Further, in this specification and the like, the channel length of a transistor refers to the shortest distance between the source electrode and the drain electrode of the transistor. Further, that the channel length directions of different transistors are parallel means that the difference between the channel length directions of different transistors is within 2.5 °, and they do not necessarily have to be strictly parallel. Similarly, the channel width of the transistor refers to the length of the portion where the source electrode and the drain electrode are opposed to each other in the region in contact with the semiconductor. Further, that the channel width directions of the different transistors are parallel means that the difference in the channel width directions of the different transistors is within 2.5 °, and they do not necessarily have to be strictly parallel.

Embodiment 1
In this embodiment, an integrated circuit according to one embodiment of the present invention will be described. An integrated circuit according to an aspect of the present invention has a function of performing artificial intelligence calculations.

In addition, artificial intelligence is a generic term of the computer which imitated human intelligence. As used herein, artificial intelligence includes artificial neural networks (ANN). An artificial neural network is a circuit that simulates a neural network composed of neurons and synapses. The term "neural network" as used herein refers particularly to artificial neural networks.

<Configuration Example 1 of Integrated Circuit>
FIG. 1 shows a configuration example of the integrated circuit 10. The integrated circuit 10 has a function of performing operations of a neural network, and has a plurality of operation circuits AC corresponding to a hidden layer and an output layer. FIG. 1 shows an example of a configuration in which the integrated circuit 10 includes N (N is an integer of 2 or more) arithmetic circuits AC [1] to [N].

The integrated circuit 10 can be configured by a semiconductor device. Therefore, the integrated circuit 10 can also be called a semiconductor device.

The arithmetic circuit AC has a current source circuit CM, an offset absorption circuit OFS, a cell array CA, and a hierarchy output circuit OU. The current source circuit CM has a reference current source circuit CMREF. The cell array CA also has a memory cell MU and a reference memory cell MUREF.

The current source circuit CM, the offset absorption circuit OFS, and the cell array CA can function as a product-sum operation circuit MAC. The hierarchical output circuit OU can function as an activation function circuit. The hierarchical output circuit OU may have a function as an amplifier circuit.

The arithmetic circuit AC can perform neural network arithmetic using the product-sum operation circuit MAC and the hierarchical output circuit OU. FIG. 2 shows an example of neural network operation.

As shown in FIG. 2A, the neural network NN can be configured by an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. Each of the input layer IL, the output layer OL, and the intermediate layer HL has one or more neurons (units). The intermediate layer HL may be a single layer or two or more layers. A neural network having two or more intermediate layers HL can be called DNN (deep neural network), and learning using a deep neural network can also be called deep learning.

Input data is input to each neuron in the input layer IL, an output signal of a neuron in the anterior or posterior layer is input to each neuron in the intermediate layer HL, and an output from a neuron in the anterior layer is input to each neuron in the output layer OL A signal is input. Each neuron may be connected to all neurons in the previous and subsequent layers (total connection) or may be connected to some neurons.

FIG. 2 (B) shows an example of operation by a neuron. Here, a neuron N and two neurons in the front layer outputting signals to the neuron N are shown. The output x ₁ of the anterior layer neuron and the output x ₂ of the anterior layer neuron are input to the neuron N. Then, in the neuron N, the sum (x ₁ w ₁ + x) of the multiplication result (x ₁ w ₁ ) of the output x ₁ and the weight w ₁ and the multiplication result (x ₂ w ₂ ) of the output x ₂ and the weight w _{2 After 2} w ₂ ) is calculated, the bias b is added as necessary to obtain the value a = x ₁ w ₁ + x ₂ w ₂ + b. Then, the value a is converted by the activation function h, and the neuron N outputs an output signal y = h (a).

Thus, the operation by the neuron includes an operation of adding the product of the input data and the weight, that is, a product-sum operation. This product-sum operation can be performed by a product-sum operation circuit MAC having the current source circuit CM, the offset absorption circuit OFS, and the cell array CA shown in FIG. The signal conversion by the activation function h can be performed by the hierarchical output circuit OU shown in FIG. That is, the arithmetic circuit AC can perform the operation of the intermediate layer HL or the output layer OL.

The cell array CA of the product-sum operation circuit is constituted by a plurality of memory cells MU arranged in a matrix.

The memory cell MU has a function of storing first data. The first data is data corresponding to weights between neurons in the neural network. In addition, the memory cell MU has a function of performing multiplication of the first data and the second data input from the outside of the cell array CA. That is, the memory cell MU has a function as a memory circuit and a function as a multiplier circuit.

When the first data is analog data, the memory cell MU has a function as an analog memory. When the first data is multilevel data, the memory cell MU has a function as a multilevel memory.

Then, the results of multiplication by memory cells MU belonging to the same column are added. Thereby, a product-sum operation of the first data and the second data is performed. Then, the result of the operation by the cell array CA is output to the hierarchy output circuit OU as third data. The details of the product-sum operation by the cell array CA will be described later.

The hierarchical output circuit OU has a function of converting the third data output from the cell array CA according to a predetermined activation function. The analog signal or multi-value digital signal output from the hierarchical output circuit OU corresponds to the output data of the intermediate layer or output layer in the neural network NN.

As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function or the like can be used. The signal converted by the hierarchical output circuit OU is output as analog data or multilevel digital data (data D _analog ).

Thus, one arithmetic circuit AC can realize any one operation of the intermediate layer HL or the output layer OL of the neural network NN. The product-sum operation circuit MAC and the hierarchy output circuit OU possessed by the arithmetic circuit AC [k] (k is an integer of 1 or more and N or less) are the product-sum operation circuit MAC [k] and the hierarchy output circuit OU [k], respectively. write. Also, analog data or multi-value digital data output from the arithmetic circuit AC [k] will be denoted as data D _analog [k].

Here, the integrated circuit 10 according to an aspect of the present invention includes a plurality of arithmetic circuits AC. Then, analog data or multi-value digital data output from the first arithmetic circuit AC is supplied to the second arithmetic circuit AC as second data. Then, the second arithmetic circuit AC performs an operation using the first data stored in the memory cell MU and the second data input from the first arithmetic circuit AC. Thereby, the integrated circuit 10 can perform the operation of the neural network constituted by a plurality of layers.

Further, analog data or multilevel digital data output from one arithmetic circuit AC is input to another arithmetic circuit AC without being converted into binary digital data. Therefore, analog-digital (AD) conversion and digital-analog (DA) conversion can be omitted, and power consumption can be reduced or calculation speed can be improved.

Furthermore, analog data or multi-value digital data output from one arithmetic circuit AC is input to another arithmetic circuit AC without passing through a memory. Therefore, access to the memory when transferring data between the arithmetic circuits AC can be omitted, and power consumption can be reduced or arithmetic speed can be improved.

When the N arithmetic circuits AC [1] to [N] are mounted on the integrated circuit 10 as shown in FIG. 1, the weight W is stored in the cell array CA of the arithmetic circuits AC [1] to [N]. Be done. Also, data X is input to the arithmetic circuit [1].

The product-sum operation circuit MAC [1] performs product-sum operation of the weight W (first data) stored in the cell array CA and the data X (second data), and the result is output as the third data hierarchically Output to the circuit OU [1]. Then, the hierarchy output circuit OU [1] converts the third data based on the activation function. Analog data or multi-value digital data obtained by this conversion is output to the arithmetic circuit AC [2] as data D _analog [1].

The product-sum operation circuit MAC [2] performs product-sum operation on the weight W (first data) stored in the cell array CA and the data D _analog [1] (second data), and the result is calculated as the third The data is output as data to the hierarchy output circuit OU [2]. Then, the hierarchy output circuit OU [2] converts the third data based on the activation function. The analog data or multilevel digital data obtained by this conversion is output to the arithmetic circuit AC [3] as data D _analog [2].

Similar operations are performed in the arithmetic circuits AC [3] to [N]. Then, the data D _analog [N] output from the arithmetic circuit AC [N] becomes output data of the integrated circuit 10 and is output as data Y to the outside.

The calculations by the calculation circuits AC [1] to [N−1] correspond to the calculations of the first to (N−1) th intermediate layers HL, and the calculation of the calculation circuit AC [N] is calculation of the output layer OL. It corresponds to In the input layer IL, product-sum operation of input data and weights is not performed. Therefore, the input layer IL can be realized by a circuit that appropriately performs data processing (such as DA conversion) on data input from the outside of the integrated circuit 10 and outputs the data to the arithmetic circuit AC [1]. By providing such a circuit in the integrated circuit 10, the function of the input layer IL can be added to the integrated circuit 10.

Thus, by mounting the N arithmetic circuits AC in the integrated circuit 10, a neural network of N + 1 layers is constructed, which is configured of the input layer IL, the intermediate layer HL of the N-1 layers, and the output layer OL. be able to.

<Configuration Example 2 of Integrated Circuit>
Next, a more specific configuration example of the integrated circuit 10 will be described using FIGS. 3 to 6. FIG. 3 shows portions of the arithmetic circuit AC [1] and the arithmetic circuit AC [2] of the integrated circuit 10 having a plurality of arithmetic circuits AC. Further, FIG. 4 is an enlarged view of the arithmetic circuit AC [1] shown in FIG. 3 to explain the electrical connection in more detail. It is FIG. 5 which expanded the arithmetic circuit AC [2] shown in FIG. 3, and explained electric connection in more detail. An example of a specific configuration of each circuit shown in FIGS. 3 to 5 is shown in FIG.

The arithmetic circuit AC [1] and the arithmetic circuit AC [2] each include a current source CM, an offset absorption circuit OFS, a cell array CA, and a hierarchy output circuit OU.

The integrated circuit 10 further includes a source driver 11, a gate driver 12, and an input buffer 13 in addition to the arithmetic circuit AC.

The gate driver 12 has a function of supplying a signal (hereinafter, selection signal) for selecting a memory cell MU. The gate driver 12 is connected to the cell array CA via the wiring WW. When storing the first data in the cell array CA, a selection signal is supplied from the gate driver 12 to the memory cell MU via the wiring WW. The gate driver 12 has a function of supplying a selection signal to both the memory cell MU of the arithmetic circuit AC [1] and the memory cell MU of the arithmetic circuit AC [2].

The source driver 11 has a function of supplying the first data to the cell array CA. The source driver 11 is connected to the cell array CA via the wiring WD. When storing the first data in the cell array CA, a potential (hereinafter, also referred to as a write potential) corresponding to the first data is supplied to the memory cell MU through the source driver 11 wiring WD. The source driver 11 has a function of supplying a write potential to both the memory cell MC of the arithmetic circuit AC [1] and the memory cell MU of the arithmetic circuit AC [2]. The write potential is supplied from the source driver 11 to the memory cell MU selected by the gate driver 12, whereby the weight W is stored in the memory cell MU.

The weight W is input to the source driver 11 from the outside. Then, the weight W input to the source driver 11 is appropriately subjected to signal processing by the source driver, and is supplied to the cell array CA as first data. Note that when digital data is input as the weight W, the source driver has a function of performing DA conversion.

The input buffer 13 has a function of appropriately performing signal processing on the data X input from the outside and outputting the data X to the cell array CA of the arithmetic circuit AC [1]. The data X corresponds to the second data used for the product-sum operation by the arithmetic circuit AC [1]. When digital data is input as data X, the input buffer 13 has a function of performing DA conversion.

FIG. 6A shows an example of the configuration of the current source circuit CM. The current source circuit CM has a third transistor Tr3. The third transistor preferably includes silicon in a channel formation region. The gate electrode of the third transistor is electrically connected to the wiring CMG, one of the source electrode or the drain electrode is electrically connected to the high power supply potential, and the other of the source electrode or the drain electrode is electrically connected to the wiring CMD Be done.

FIG. 6B shows an example of the configuration of the offset absorption circuit OFS. The offset absorbing circuit OFS includes a fourth transistor Tr4, a fifth transistor Tr5, a sixth transistor Tr6, a seventh transistor Tr7, an eighth transistor Tr8, a ninth transistor Tr9, a second capacitive element C2, a fifth There are three capacitive elements C3.

The fourth transistor Tr4 and the seventh transistor Tr7 preferably include silicon in a channel formation region. The fifth transistor Tr5, the sixth transistor Tr6, the eighth transistor Tr8, and the ninth transistor Tr9 preferably include a metal oxide in a channel formation region.

The gate electrode of the fourth transistor Tr4 is electrically connected to one of the second capacitive element C2, one of the source electrode or drain electrode of the fifth transistor Tr5, and one of the source electrode and drain electrode of the sixth transistor. Ru. One of the source electrode and the drain electrode of the fourth transistor Tr4 is electrically connected to the other of the second capacitive element C2 and the high power supply potential. The other of the source electrode and the drain electrode of the fourth transistor Tr4 is the other of the source electrode or the drain electrode of the fifth transistor Tr5, the wiring WX, one of the source electrode or the drain electrode of the seventh transistor Tr, and the eighth It is electrically connected to one of the source electrode and the drain electrode of the transistor Tr8.

The gate electrode of the fifth transistor Tr5 is electrically connected to the wiring OSM. The gate electrode of the sixth transistor Tr6 is electrically connected to the wiring ORM.

The gate electrode of the seventh transistor Tr7 is electrically connected to one of the third capacitive element C3, the other of the source electrode or drain electrode of the eighth transistor Tr8, and one of the source electrode or drain electrode of the ninth transistor Tr9. Be done. The other of the source electrode and the drain electrode of the seventh transistor Tr7 is electrically connected to the other of the third capacitive element C3 and the other of the ninth transistor Tr9, and is grounded.

The gate electrode of the eighth transistor Tr8 is electrically connected to the wiring OSP. The gate electrode of the ninth transistor Tr9 is electrically connected to the wiring ORP.

FIG. 6B shows an example of the configuration of the memory cell MU. The memory cell MU includes a first transistor Tr1, a second transistor Tr2, and a first capacitive element C1. The first transistor Tr1 preferably includes a metal oxide in a channel formation region. The second transistor Tr2 preferably includes silicon in a channel formation region.

The gate electrode of the first transistor Tr1 is electrically connected to the wiring WW, one of the source electrode or the drain electrode is electrically connected to the wiring WD, and the other of the source electrode or the drain electrode is one of the capacitive elements C1 and the first It is electrically connected to the gate electrode of the second transistor Tr2.

One of the source electrode or the drain electrode of the second transistor Tr2 is electrically connected to the wiring WX, and the other of the source electrode or the drain electrode is grounded.

The other of the first capacitive element C1 is electrically connected to the wiring RW.

In the arithmetic circuit AC according to one embodiment of the present invention which performs arithmetic operation using analog data or multilevel digital data, the reliability of the memory cell MU largely affects the accuracy of the arithmetic operation. Therefore, it is necessary to reduce the variation in characteristics of memory cells MU included in different arithmetic circuits AC as well as reducing the variation in characteristics of memory cells MU in the same arithmetic circuit AC. In order to reduce the variation in the characteristics of the memory cell MU, it is necessary to reduce the variation in the characteristics of the transistor of the memory cell MU. This is true for both the transistor preferably having silicon in the channel formation region and the transistor preferably having metal oxide in the channel formation region of the memory cell MU.

In order to reduce variations in transistor characteristics, it is effective to make the conditions not different depending on the place in the process of forming the transistor. For that purpose, it is effective to align the direction of the transistors when arranging the memory cells on the substrate. To align the direction of the transistor means, for example, to make the channel length direction of the transistor parallel. Alternatively, it refers to making the channel width directions of the transistors parallel.

By parallelizing the channel length directions of the transistors in the memory cells of different arithmetic circuits AC as described above, more accurate arithmetic operations can be performed.

In other words, for example, the channel length direction of the first transistor Tr1 of the memory cell MU of the arithmetic circuit AC [1] and the first transistor Tr1 of the memory cell MU of the arithmetic circuit AC [2]. It is preferable to make the channel length directions of Alternatively, the channel width direction of the first transistor Tr1 of the memory cell MU of the arithmetic circuit AC [1] is parallel to the channel width direction of the first transistor Tr1 of the memory cell MU of the arithmetic circuit AC [2]. It is preferable to

FIG. 6C shows an example of the configuration of the hierarchy output circuit OU. In the hierarchical output circuit OU shown in FIG. 6C, the ReLU function is implemented as the activation function.

The hierarchical output circuit OU includes a tenth transistor Tr10, an eleventh transistor Tr11, a twelfth transistor Tr12, a thirteenth transistor Tr13, a second capacitive element C2, a first resistive element R1, and a first switch S1. Have.

The gate electrode of the tenth transistor Tr10 is electrically connected to the wiring RST. One of the source electrode and the drain electrode of the tenth transistor Tr10 is electrically connected to the wiring OPR. The other of the source electrode and the drain electrode of the tenth transistor Tr10 is electrically connected to one of the second capacitive elements C2 and the gate electrode of the twelfth transistor Tr12.

The gate electrode of the eleventh transistor Tr11 is electrically connected to the wiring OBS. One of the source electrode and the drain electrode of the eleventh transistor Tr11 is electrically connected to the high power supply potential. The other of the source electrode or drain electrode of the eleventh transistor Tr11 is electrically connected to the other of the source electrode or drain electrode of the twelfth transistor Tr12, to one of the source electrode or drain electrode of the thirteenth transistor Tr13, and to the wiring OUT. .

The gate electrode of the twelfth transistor Tr12 is electrically connected to the high power supply potential. The gate electrode of the thirteenth transistor Tr13 is electrically connected to the wiring NB, and the other of the source electrode and the drain electrode is grounded.

The other of the second capacitive element C2 is electrically connected to the wiring IN and the other of the first switch S1.

One of the first resistance elements R1 is electrically connected to the wiring OREF, and the other is electrically connected to one of the first switches S1.

The signal supplied from the wiring ER controls the on / off of the first switch S1.

FIG. 7A shows an example of the configuration of the source driver 11. The source driver 11 includes a shift register SL1, a latch circuit LAT1, and a DA conversion circuit DAC1. The start pulse SP1 and the clock signal CLK1 are input to the shift register SL1, and the weight W (digital data) is input to the latch circuit LAT1.

The shift register SL1 has a function of generating a sampling pulse using the start pulse SP1 and the clock signal CLK1. The sampling pulse generated by the shift register SL1 is output to the latch circuit LAT1.

The latch circuit LAT1 has a function of storing the weight W at a predetermined timing according to the sampling pulse input from the shift register SL1. The weight W stored in the latch circuit LAT1 is output to the DA conversion circuit DAC1.

The DA conversion circuit DAC1 has a function of converting the weight W input from the latch circuit LAT1 into an analog signal and outputting the analog signal to the wiring WD. The potential output from the DA conversion circuit DAC1 to the wiring WD corresponds to the write potential.

FIG. 7B shows an example of the configuration of the input buffer 13. The input buffer 13 has a shift register SL2, a latch circuit LAT2, and a DA conversion circuit DAC2. The start pulse SP2 and the clock signal CLK2 are input to the shift register SL2, and the data X (digital data) is input to the latch circuit LAT2.

The shift register SL2, the latch circuit LAT2, and the DA conversion circuit DAC2 have the same functions as the shift register SL1, the latch circuit LAT1, and the DA conversion circuit DAC1, respectively. Then, the potential supplied from the DA conversion circuit DAC2 to the wiring RW corresponds to the second data input to the arithmetic circuit AC [1].

<Operation Example of Arithmetic Circuit>
The product-sum operation of the first data and the second data can be performed using the above-described arithmetic circuit AC. Hereinafter, an operation example of the arithmetic circuit AC when performing the product-sum operation will be described using the example of the cell array shown in FIG.

FIG. 9 shows a timing chart of an operation example of the arithmetic circuit AC. In FIG. 9, the wiring WW [1], the wiring WW [2], the wiring WD [1], the wiring WDref, the node NM [1,1], the node NM [2,1], and the node NMref [1] in FIG. , node Nmref [2], wiring RW [1], and changes in potentials of the wiring RW [2], the current _{I WX [1] -I α [} 1], and shows a transition of the value of the current _{I WXref} . The current I _WX [1] -I _α [1] corresponds to the sum of the currents flowing from the wiring WX [1] to the memory cells MU [1, 1] and [2, 1].

Here, the operation will be described focusing on the memory cells MU [1, 1], [2, 1] and the memory cells MUref [1], [2] shown in FIG. 8 as a representative example, but other memory cells MU and memory cell MUref can be similarly operated.

[First data storage]
First, the time at T01-T02, the potential of the wiring WW [1] becomes high level, the _V PR _{-V W [1,1]} greater potential the potential of the wiring WD [1] is higher than the ground potential (GND), wiring potential of WDref becomes the _{V PR} greater potential than the ground potential. Further, the potentials of the wiring RW [1] and the wiring RW [2] become a reference potential (REFP). The potential V _{W [1, 1]} is a potential corresponding to the first data stored in the memory cell MU [1, 1]. Further, the potential _VPR is a potential corresponding to reference data. Thus, the memory cell MU [1,1] and the transistor Tr11 having a memory cell MUref [1] is turned on, the node NM potential of [1,1] is _V PR _{-V W [1,1],} the node NMref The potential of [1] becomes _VPR .

At this time, the current I _{MU [1, 1], 0} flowing from the wiring WX [1] to the transistor Tr12 of the memory cell MU [1, 1] can be expressed by the following equation. Here, k is a constant determined by the channel length, channel width, mobility, and the capacity of the gate insulating film of the transistor Tr12. Further, V _th is a threshold voltage of the transistor Tr12.

_{I MU [1,1], 0 =} k (V PR -V W [1,1] -V th) 2 (E1)

Further, the current I _{MUref [1], 0} flowing from the wiring WXref to the transistor Tr12 of the memory cell MUref [1] can be expressed by the following equation.

_{I MUref [1], 0 =} k (V PR -V th) 2 (E2)

Next, at time T02 to T03, the potential of the wiring WW [1] becomes low. Accordingly, the transistor Tr11 included in the memory cell MU [1,1] and the memory cell MUref [1] is turned off, and the potentials of the node NM [1,1] and the node NMref [1] are held.

As described above, it is preferable to use an OS transistor as the transistor Tr11. Thus, the leak current of the transistor Tr11 can be suppressed, and the potentials of the node NM [1,1] and the node NMref [1] can be accurately held.

Then, at time T03-T04, the potential of the wiring WW [2] becomes the high level, the potential of the wiring WD [1] becomes _V PR _{-V W [2,1]} greater potential than the ground potential, of the wiring WDref potential becomes the V _PR greater potential than the ground potential. The potential V _{W [2, 1]} is a potential corresponding to the first data stored in the memory cell MU [2, 1]. Thus, the memory cell MU [2,1] and the transistor Tr11 having a memory cell MUref [2] are turned on, the node NM potential of [1,1] is _V PR _{-V W [2,1],} the node NMref The potential of [1] becomes _VPR .

At this time, the current I _{MU [2, 1], 0} flowing from the wiring WX [1] to the transistor Tr12 of the memory cell MU [2, 1] can be expressed by the following equation.

_{I MU [2,1], 0 =} k (V PR -V W [2,1] -V th) 2 (E3)

Further, the current I _{MUref [2], 0} flowing from the wiring WXref to the transistor Tr12 of the memory cell MUref [2] can be expressed by the following equation.

_{I MUref [2], 0 =} k (V PR -V th) 2 (E4)

Next, at time T04 to T05, the potential of the wiring WW [2] becomes low. Accordingly, the transistor Tr11 included in the memory cell MU [2,1] and the memory cell MUref [2] is turned off, and the potentials of the node NM [2,1] and the node NMref [2] are held.

By the above operation, the first data is stored in the memory cells MU [1, 1], [2, 1], and the reference data is stored in the memory cells MUref [1], [2].

Here, consider the current flowing through the wiring WX [1] and the wiring WXref at time T04 to T05. The current from the current source circuit CS is supplied to the wiring WXref. Further, the current flowing through the wiring WXref is discharged to the current mirror circuit CM and the memory cells MUref [1] and [2]. Assuming that the current supplied from the current source circuit CS to the wiring WXref is I _Cref , and the current discharged from the wiring WXref to the current mirror circuit CM is I _{CM, 0} , the following equation is established.

I _Cref −I _{CM, 0} = I _{MUref [1], 0} + I _{MUref [2], 0} (E5)

The current from the current source circuit CS is supplied to the wiring WX [1]. Further, the current flowing through the wiring WX [1] is discharged to the current mirror circuit CM and the memory cells MU [1,1] and [2,1]. In addition, a current flows from the wiring WX [1] to the offset circuit OFST. Assuming that the current supplied from the current source circuit CS to the wiring WX [1] is I _{C, 0} and the current flowing from the wiring WX [1] to the offset circuit OFST is I _{α, 0} , the following equation is established.

I _{C −} I _{CM, 0} = I _{MU [1, 1], 0} + I _{MU [2, 1], 0} + I _{α, 0} (E6)

[Product-Sum operation of first data and second data]
Next, at time T05 to T06, the potential of the wiring RW [1] is higher than the reference potential by V _{X [1]} . At this time, the potential V _{X [1]} is supplied to the capacitive element C11 of each of the memory cell MU [1,1] and the memory cell MUref [1], and the potential of the gate of the transistor Tr12 rises due to capacitive coupling. The potential V _{x [1]} is a potential corresponding to the second data supplied to the memory cell MU [1, 1] and the memory cell MU ref [1].

The amount of change in the potential of the gate of the transistor Tr12 is a value obtained by multiplying the amount of change in the potential of the wiring RW by the capacitive coupling coefficient determined by the configuration of the memory cell. The capacitive coupling coefficient is calculated by the capacitance of the capacitive element C11, the gate capacitance of the transistor Tr12, the parasitic capacitance, and the like. Hereinafter, for convenience, it is assumed that the amount of change in the potential of the wiring RW and the amount of change in the potential of the gate of the transistor Tr12 are the same, that is, the capacitive coupling coefficient is 1. In practice, the potential V _x may be determined in consideration of the capacitive coupling coefficient.

When potential V _{X [1]} is supplied to capacitive element C11 of memory cell MU [1] and memory cell MUref [1], the potentials of node NN [1] and node NMref [1] are V _{X [1],} respectively _. To rise.

Here, the current I _{MU [1, 1], 1} flowing from the wiring WX [1] to the transistor Tr12 of the memory cell MU [1, 1] at time T05 to T06 can be expressed by the following equation.

_{I MU [1,1], 1 =} k (V PR -V W [1,1] + V X [1] -V th) 2 (E7)

That is, by supplying the potential V _{X [1]} to the wiring RW [1], the current flowing from the wiring WX [1] to the transistor Tr12 of the memory cell MU [1,1] is ΔI _{MU [1,1]} = I _{MU [1,1], 1-} I _{MU [1,1], 0} increase.

Further, at time T05-T06, the current I _{MUref [1], 1} flowing from the wiring WXref to the transistor Tr12 of the memory cell MUref [1] can be expressed by the following equation.

_{I MUref [1], 1 =} k (V PR + V X [1] -V th) 2 (E8)

That is, by supplying the potential V _{X [1]} to the wiring RW [1], the current flowing from the wiring WXref to the transistor Tr12 of the memory cell MUref [1] is ΔI _{MUref [1]} = I _{MUref [1], 1} -I _{MUref [1],} increases by ₀ .

Further, the current flowing to the wiring WX [1] and the wiring WXref will be considered. The current I _Cref is supplied from the current source circuit CS to the wiring WXref. Further, the current flowing through the wiring WXref is discharged to the current mirror circuit CM and the memory cells MUref [1] and [2]. Assuming that the current discharged from the wiring WXref to the current mirror circuit CM is I _{CM, 1} , the following equation holds.

I _Cref −I _{CM, 1} = I _{MUref [1], 1} + I _{MUref [2], 0} (E9)

The current I _C is supplied from the current source circuit CS to the wiring WX [1]. Further, the current flowing through the wiring WX [1] is discharged to the current mirror circuit CM and the memory cells MU [1,1] and [2,1]. Furthermore, current flows from the wiring WX [1] to the offset circuit OFST. Assuming that the current flowing from the wiring WX [1] to the offset circuit OFST is I _{α, 1} , the following equation is established.

I _C −I _{CM, 1} = I _{MU [1,1], 1} + I _{MU [2,1], 1} + I _{α, 1} (E10)

Then, the difference between the current I _{α, 0} and the current I _{α, 1} (difference current ΔI _α ) can be expressed by the following equation from the equations (E1) to (E10).

ΔI _α = I _{α, 0} −I _{α, 1} = 2 kV _{W [1,1]} V _{X [1]} (E11)

Thus, the differential current ΔI _α takes a value corresponding to the product of the potentials V _{W [1, 1]} and V _{X [1]} .

After that, at time T06-T07, the potential of the wiring RW [1] becomes the ground potential, and the potentials of the node NM [1,1] and the node NMref [1] become similar to those at time T04-T05.

Next, at time T07 to T08, the potential of the wiring RW [1] becomes V _{X [1]} larger than the reference potential, and the potential of the wiring RW [2] is V _{X [2]} larger than the reference potential Supplied. Thereby, potential V _{X [1]} is supplied to each capacitive element C11 of memory cell MU [1, 1] and memory cell MUref [1], and node NM [1, 1] and node NMref [ The potential of _1] rises by V _{X [1]} . In addition, potential V _{X [2]} is supplied to capacitive element C11 of each of memory cell MU [2, 1] and memory cell MUref [2], and node NM [2, 1] and node NMref [2 Each of the potentials of V _{] [2]} rises.

Here, the current I _{MU [2, 1], 1} flowing from the wiring WX [1] to the transistor Tr12 of the memory cell MU [2, 1] at time T07-T08 can be expressed by the following equation.

_{I MU [2,1], 1 =} k (V PR -V W [2,1] + V X [2] -V th) 2 (E12)

That is, by supplying the potential V _{X [2]} to the wiring RW [2], the current flowing from the wiring WX [1] to the transistor Tr12 of the memory cell MU [2, 1] is ΔI _{MU [2, 1]} = I _{MU [2, 1], 1-} I _{MU [2, 1], 0} increases.

Further, at time T05-T06, the current I _{MUref [2], 1} flowing from the wiring WXref to the transistor Tr12 of the memory cell MUref [2] can be expressed by the following equation.

_{I MUref [2], 1 =} k (V PR + V X [2] -V th) 2 (E13)

That is, by supplying the potential V _{X [2]} to the wiring RW [2], the current flowing from the wiring WXref to the transistor Tr12 of the memory cell MUref [2] is ΔI _{MUref [2]} = I _{MUref [2], 1} -I _{MUref [2],} increases by ₀ .

Further, the current flowing to the wiring WX [1] and the wiring WXref will be considered. The current I _Cref is supplied from the current source circuit CS to the wiring WXref. Further, the current flowing through the wiring WXref is discharged to the current mirror circuit CM and the memory cells MUref [1] and [2]. Assuming that the current discharged from the wiring WXref to the current mirror circuit CM is I _{CM, 2} , the following equation holds.

I _Cref −I _{CM, 2} = I _{MUref [1], 1} + I _{MUref [2], 1} (E14)

The current I _C is supplied from the current source circuit CS to the wiring WX [1]. Further, the current flowing through the wiring WX [1] is discharged to the current mirror circuit CM and the memory cells MU [1,1] and [2,1]. Furthermore, current flows from the wiring WX [1] to the offset circuit OFST. Assuming that the current flowing from the wiring WX [1] to the offset circuit OFST is I _{α, 2} , the following equation is established.

I _{C −} I _{CM, 2} = I _{MU [1, 1], 1} + I _{MU [2, 1], 1} + I _{α, 2} (E15)

Then, the difference between the current I _{α, 0} and the current I _{α, 2} (difference current ΔI _α ) is expressed by the following equation from the equations (E1) to (E8) and the equations (E12) to (E15) be able to.

ΔI _α = I _{α, 0} −I _{α, 2} = 2 k (V _{W [1, 1]} V _{X [1]} + V _{W [2, 1]} V _{X [2]} ) (E16)

Thus, the difference current ΔI _α is obtained by adding the product of the potential V _{W [1, 1]} and the potential V _{X [1] and} the product of the potential V _{W [2, 1]} and the potential V _{X [2].} It becomes a value according to the combined result.

After that, at time T08-T09, the potentials of the wirings RW [1] and [2] become the ground potential, and the potentials of the nodes NM [1,1] and [2,1] and the nodes NMref [1] and [2] become It becomes the same as time T04-T05.

As shown in the equation (E9) and the equation (E16), the differential current ΔI _α input to the offset circuit OFST is the potential V _X corresponding to the first data (weight) and the second data (input data And the value corresponding to the result of adding the product of the potential V _W corresponding to. That is, by measuring the difference current ΔI _α with the offset circuit OFST, it is possible to obtain the result of the product-sum operation of the first data and the second data.

Although the above description focuses on the memory cells MU [1, 1], [2, 1] and the memory cells MUref [1], [2], the number of memory cells MU and memory cells MUref may be set arbitrarily. Can. The differential current ΔIα when the number m of rows of the memory cell MU and the memory cell MUref is an arbitrary number can be expressed by the following equation.

ΔI _α = 2 k _{i i} V _{W [i, 1]} V _{X [i]} (E17)

Further, by increasing the number n of columns of the memory cell MU and the memory cell MUref, the number of product-sum operations to be executed in parallel can be increased.

As described above, by using the arithmetic circuit AC, the product-sum operation of the first data and the second data can be performed.

When the arithmetic circuit AC is used for arithmetic in a neural network, the number m of rows of memory cells MU corresponds to the number of input data supplied to one neuron, and the number n of columns of memory cells MU corresponds to the number of neurons Can. For example, it is assumed that the product-sum operation is performed using the arithmetic circuit AC in the intermediate layer HL shown in FIG. At this time, the number m of rows of the memory cell MU is set to the number of input data supplied from the input layer IL (the number of neurons in the input layer IL), and the number n of columns of the memory cell MU is a neuron of the intermediate layer HL It can be set to the number of

The structure of the neural network to which the arithmetic circuit AC is applied is not particularly limited. For example, the arithmetic circuit AC can be used for a convolutional neural network (CNN), a recursive neural network (RNN), an auto encoder, a Boltzmann machine (including a restricted Boltzmann machine), and the like.

<Configuration Example 3 of Integrated Circuit>
Although FIG. 3 illustrates the configuration example in which the integrated circuit 10 includes the arithmetic circuits AC [1] and [2], the number of the arithmetic circuits AC is not limited to this and can be freely set. FIG. 10 shows a configuration example of an integrated circuit 10 having six arithmetic circuits AC.

The integrated circuit 10 performs operation of a seven-layer neural network composed of the input layer IL, the five intermediate layers HL, and the output layer OL using the arithmetic circuits AC [1] to [6]. it can. The arithmetic circuits AC [1] to AC [5] have a function of calculating the intermediate layer HL, and the arithmetic circuit [6] has a function of calculating the output layer OL.

Further, as shown in FIG. 10, by providing the amplifier circuits [1] to [5] at positions adjacent to the hierarchical output circuit OU and the cell array CA, the arithmetic circuit AC for performing data transmission / reception is brought close and wiring Arrangement can be simplified.

In the integrated circuit 10, the source driver and the gate driver are shared. Specifically, the source driver has a function of supplying a selection signal to the cell array CA of the arithmetic circuits AC [1] to [6] through the wiring WD. Further, the gate driver has a function of supplying a write potential to the cell array CA of the arithmetic circuits AC [1] to [6] through the wiring WW.

As described above, the integrated circuit 10 according to one aspect of the present invention has a configuration in which analog data or multi-value digital data output from one arithmetic circuit AC is input to another arithmetic circuit AC. Network operations can be performed with low power consumption or high speed.

This embodiment can be combined with the description of the other embodiments as appropriate.

Second Embodiment
In this embodiment mode, application examples of the integrated circuit described in the above embodiment modes will be described.

The integrated circuit 10 described in the above embodiment can be used in a computer. A configuration example of the computer 50 is shown in FIG. The computer 50 includes a processing unit 51, a storage unit 52, an arithmetic unit 53, an input unit 54, and an output unit 55. The processing unit 51, the storage unit 52, the operation unit 53, the input unit 54, and the output unit 55 are connected to the transmission path 56, and transmission and reception of information between them can be performed via the transmission path 56. .

The processing unit 51 has a function of performing an operation using the information supplied from the storage unit 52, the operation unit 53, the input unit 54 or the like. The result of the calculation by the processing unit 51 is supplied to the storage unit 52, the calculation unit 53, the output unit 55, or the like. The processing unit 51 can perform various data processing and program control by executing the program stored in the storage unit 52.

The processing unit 51 can be configured by, for example, a central processing unit (CPU). The processing unit 103 can also be configured by a microprocessor such as a digital signal processor (DSP) or a graphics processing unit (GPU). The microprocessor may be configured by a PLD (Programmable Logic Device) such as a Field Programmable Gate Array (FPGA) or a Field Programmable Analog Array (FPAA).

The storage unit 52 has a function of storing data used for calculation by the processing unit 51, a program executed by the processing unit 51, and the like. The storage unit 52 can be configured by a storage device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

Arithmetic unit 53 has a function of performing a predetermined operation. The processing unit 51 can cause the computing unit 53 to execute predetermined processing. That is, the computing unit 53 can execute part of the processing performed by the processing unit 51 instead of the processing unit 51. The result of the calculation by the calculation unit 53 is supplied to the processing unit 51, the storage unit 52, the output unit 55, or the like.

The arithmetic unit 53 can be provided with the integrated circuit 10 described in the above embodiment. As a result, the operation unit 53 can be equipped with the function of performing an operation using a neural network.

The input unit 54 has a function of supplying information input from the outside of the computer 50 to the processing unit 51, the storage unit 52, the computing unit 53, and the like. The output unit 55 has a function of outputting the information stored in the storage unit 52 as a result of processing by the processing unit 51, the result of the calculation by the calculation unit 53, and the like to the outside of the computer 50.

As described above, by mounting the integrated circuit 10 on the computer 50, it is possible to configure a computer capable of neural network operation.

Although an example in which the integrated circuit 10 is built in a computer has been described here, an application example of the integrated circuit 10 is not limited to this. For example, by using the integrated circuit 10 in an image processing circuit of a display device, image processing using a neural network can be performed.

This embodiment can be combined with the description of the other embodiments as appropriate.

Third Embodiment

In this embodiment, a semiconductor device which can be used for the integrated circuit described in the above embodiment and a structural example of an ox transistor which can be used for the semiconductor device will be described.

<Configuration Example of Semiconductor Device>
The semiconductor device illustrated in FIG. 12 includes a transistor 300, a transistor 200, and a capacitor 100. 13A is a cross-sectional view of the transistor 200 in the channel length direction, FIG. 13B is a cross-sectional view of the transistor 200 in the channel width direction, and FIG. 13C is a cross section of the transistor 300 in the channel width direction. FIG.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has low off-state current, stored data can be held for a long time by using the transistor 200 for a semiconductor device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the semiconductor device can be sufficiently reduced.

In the semiconductor device illustrated in FIG. 12, the wiring 1001 is connected to one of the source and the drain of the transistor 300, and the wiring 1002 is connected to the other of the source and the drain of the transistor 300. The wiring 1003 is connected to one of the source and the drain of the transistor 200, the wiring 1004 is connected to the top gate of the transistor 200, and the wiring 1006 is connected to the bottom gate of the transistor 200. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are connected to one of the electrodes of the capacitor 100, and the wiring 1005 is connected to the other of the electrodes of the capacitor 100.

Here, in the case where the semiconductor device described in this embodiment is used for the ox memory described in Embodiment 2, the transistor M3 corresponds to the transistor 300, the transistor M2 corresponds to the transistor 200, and the capacitor CB corresponds to the capacitor 100. The wiring SL corresponds to the wiring 1001, the wiring RWX to the wiring 1002, the wiring WBL to the wiring 1003, the wiring WOL to the wiring 1004, the wiring CAL to the wiring 1005, and the wiring BGL to the wiring 1006 Do.

In the case where the semiconductor device described in this embodiment is used for the arithmetic circuit described in Embodiment 3, the transistor Tr12 corresponds to the transistor 300, the transistor Tr11 corresponds to the transistor 200, and the capacitive element CP corresponds to the capacitive element 100. The wiring VR 0 corresponds to the wiring 1001, the wiring WX to the wiring 1002, the wiring WD to the wiring 1003, the wiring WW to the wiring 1004, and the wiring CL to the wiring 1005.

When the semiconductor device described in this embodiment is used for both the ox memory and the arithmetic circuit, the transistors M3 and Tr12, the transistors M2 and Tr11, and the capacitors CB and CP are formed in the same step. be able to. Thereby, the manufacturing process can be simplified and the cost can be reduced.

The semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. Have.

As illustrated in FIG. 13C, in the transistor 300, the top surface of the semiconductor region 313 and the side surface in the channel width direction are covered with the conductor 316 with the insulator 315 interposed therebetween. As described above, by setting the transistor 300 to a Fin type, the on-characteristic of the transistor 300 can be improved by increasing the effective channel width. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor.

A semiconductor such as a silicon-based semiconductor is preferably included in a region where the channel of the semiconductor region 313 is to be formed, a region in the vicinity thereof, a low resistance region 314a to be a source or drain region, a low resistance region 314b, and the like. Preferably, crystalline silicon is included. Alternatively, it may be formed using a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide) or the like. It is also possible to use silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.

The low-resistance region 314a and the low-resistance region 314b impart p-type conductivity such as an element imparting n-type conductivity such as arsenic or phosphorus or p-type conductivity such as boron in addition to the semiconductor material applied to the semiconductor region 313 Containing elements.

The conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, an alloy Materials or conductive materials such as metal oxide materials can be used.

Note that the Vth of the transistor can be adjusted by defining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

Note that the transistor 300 illustrated in FIG. 12 is an example and is not limited to the structure, and an appropriate transistor may be used in accordance with the circuit configuration and the driving method. For example, as in the transistor 200, the transistor 300 may be formed using an oxide semiconductor.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked over the transistor 300.

For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used as the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Just do it.

The insulator 322 may have a function as a planarization film which planarizes a step difference generated by the transistor 300 and the like provided below the insulator. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance the planarity.

For the insulator 324, a film having a barrier property to prevent diffusion of hydrogen or an impurity from the substrate 311, the transistor 300, or the like to the region where the transistor 200 is provided is preferably used.

As an example of a film having a barrier property to hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 200 or the like, the characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to use a film which suppresses diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of desorption of hydrogen.

The desorption amount of hydrogen can be analyzed, for example, using a thermal desorption gas analysis method (TDS) or the like. For example, in the TDS analysis, the desorption amount of hydrogen in the insulator 324 is 10 × 10 5 in the range of 50 ° C. to 500 ° C. when the desorption amount in terms of hydrogen atoms is converted per area of the insulator 324. ¹⁵ atom / cm ² or less, and may be preferably 5 × ¹⁰ 15 atom / cm ² or less.

Note that the insulator 326 preferably has a dielectric constant lower than that of the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the dielectric constant of the insulator 324 is preferably 0.7 times or less of the dielectric constant of the insulator 326, and more preferably 0.6 times or less. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, the conductor 328 connected to the capacitor 100 or the transistor 200, the conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 have a function as a plug or a wiring. Moreover, the conductor which has a function as a plug or wiring may put several structure together, and may provide the same code | symbol. In the present specification and the like, the wiring and the plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As a material of each plug and a wiring (conductor 328 and conductor 330 and the like), a single layer or a stack of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material It can be used. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 12, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug connected to the transistor 300 or a wiring. Note that the conductor 356 can be provided using a material similar to the conductor 328 and the conductor 330.

Note that, for example, for the insulator 350, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 350 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

As a conductor having a barrier property to hydrogen, for example, tantalum nitride or the like may be used. Further, by stacking tantalum nitride and tungsten with high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, the tantalum nitride layer having a barrier property to hydrogen preferably has a structure in contact with the insulator 350 having a barrier property to hydrogen.

A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 12, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked and provided. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

Note that, for example, for the insulator 360, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 360 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 12, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed over the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to the conductor 328 and the conductor 330.

Note that, for example, for the insulator 370, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening portion of the insulator 370 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 12, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to the conductor 328 and the conductor 330.

Note that for example, for the insulator 380, as in the case of the insulator 324, it is preferable to use an insulator having a barrier property to hydrogen. The conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 380 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described above, the semiconductor device according to this embodiment It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. For any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, a material having a barrier property to oxygen or hydrogen is preferably used.

For example, for the insulator 210 and the insulator 214, for example, a film having a barrier property to prevent diffusion of hydrogen and impurities from the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 200 is provided Is preferred. Therefore, the same material as the insulator 324 can be used.

As an example of a film having a barrier property to hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 200 or the like, the characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to use a film which suppresses diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of desorption of hydrogen.

Further, as the film having a barrier property to hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

In particular, aluminum oxide has a high blocking effect of preventing permeation of the film against both oxygen and impurities such as hydrogen and moisture which cause fluctuation of the electrical characteristics of the transistor. Thus, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed in the transistor 200 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide of the transistor 200 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 200.

For example, for the insulator 212 and the insulator 216, the same material as the insulator 320 can be used. In addition, by using a material having a relatively low dielectric constant as the interlayer film for the insulating film, parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212 and the insulator 216.

In the insulator 210, the insulator 212, the insulator 214, and the insulator 216, the conductor 218, a conductor (conductor 203) included in the transistor 200, and the like are embedded. Note that the conductor 218 has a function as a plug connected to the capacitor 100 or the transistor 300, or a wiring. The conductor 218 can be provided using a material similar to the conductor 328 and the conductor 330.

In particular, the conductor 218 in a region in contact with the insulator 210 and the insulator 214 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. According to this structure, the transistor 300 and the transistor 200 can be completely separated in a layer having a barrier property to oxygen, hydrogen, and water, and can suppress diffusion of hydrogen from the transistor 300 to the transistor 200. .

The transistor 200 is provided above the insulator 216.

As shown in FIGS. 13A and 13B, the transistor 200 is disposed over the conductor 203 disposed so as to be embedded in the insulator 214 and the insulator 216, and the insulator 216 and the conductor 203. Insulator 220, an insulator 222 disposed on the insulator 220, an insulator 224 disposed on the insulator 222, an oxide 230a disposed on the insulator 224, and an oxide An oxide 230b disposed on 230a, a conductor 242a and a conductor 242b spaced apart from each other on oxide 230b, and a conductor 242a and a conductor 242b An insulator 280 in which an opening is formed overlapping the conductor 242b, a conductor 260 disposed in the opening, an oxide 230b, a conductor 242a, a conductor 242b, and An insulator 250 disposed between the insulator 280 and the conductor 260, an oxide 230b, the conductor 242a, the conductor 242b, the insulator 280, and the insulator 250 And an oxide 230c. Further, as shown in FIGS. 13A and 13B, an insulator 244 is preferably provided between the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b, and the insulator 280. . As shown in FIGS. 13A and 13B, the conductor 260 is a conductor provided inside the insulator 250 and a conductor provided so as to be embedded inside the conductor 260a. It is preferable to have 260b. Further, as shown in FIGS. 13A and 13B, the insulator 274 is preferably provided over the insulator 280, the conductor 260, and the insulator 250.

Note that in the following, the oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as the oxide 230. Further, the conductor 242 a and the conductor 242 b may be collectively referred to as a conductor 242.

Note that in the transistor 200, a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in the region where a channel is formed and in the vicinity thereof is illustrated; It is not a thing. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. In the transistor 200, the conductor 260 is illustrated as a stacked-layer structure of two layers, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. The transistor 200 illustrated in FIGS. 12 and 13A and 13B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

Here, the conductor 260 functions as a gate electrode of the transistor, and the conductor 242a and the conductor 242b function as a source electrode or a drain electrode, respectively. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and the region sandwiched between the conductor 242 a and the conductor 242 b. The arrangement of the conductor 260, the conductor 242a and the conductor 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 200, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Thus, the conductor 260 can be formed without providing a positioning margin, so that the area occupied by the transistor 200 can be reduced. Thus, the semiconductor device can be miniaturized and highly integrated.

Further, since the conductor 260 is formed in a self-aligned manner in the region between the conductor 242a and the conductor 242b, the conductor 260 does not have a region overlapping with the conductor 242a or the conductor 242b. Thus, parasitic capacitance formed between the conductor 260 and the conductor 242a and the conductor 242b can be reduced. Thus, the switching speed of the transistor 200 can be improved and high frequency characteristics can be provided.

The conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 203 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 203 independently and not in conjunction with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 203, Vth of the transistor 200 can be larger than 0 V, and off current can be reduced. Therefore, when a negative potential is applied to the conductor 203, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.

The conductor 203 is placed so as to overlap with the oxide 230 and the conductor 260. Thus, when a potential is applied to the conductor 260 and the conductor 203, the electric field generated from the conductor 260 and the electric field generated from the conductor 203 are connected to cover the channel formation region formed in the oxide 230. Can. In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

The conductor 203 has the same configuration as the conductor 218. The conductor 203a is formed in contact with the inner wall of the opening of the insulator 214 and the insulator 216, and the conductor 203b is formed inside the conductor 203a.

The insulator 220, the insulator 222, the insulator 224, and the insulator 250 have a function as a gate insulator.

Here, the insulator 224 in contact with the oxide 230 is preferably an insulator that contains oxygen at a higher proportion than the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing the insulator including such excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide from which oxygen is released by heating is a desorption amount of oxygen of at least 1.0 × 10 ¹⁸ atoms / cm ³ , preferably 1 in terms of oxygen atom in TDS (thermal desorption spectroscopy) analysis. It is an oxide film having a density of not less than 0 × 10 ¹⁹ atoms / cm ³ , more preferably not less than 2.0 × 10 ¹⁹ atoms / cm ³ , or not less than 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

Further, in the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing at least one diffusion of oxygen (eg, oxygen atom, oxygen molecule, and the like) (the above-described oxygen is difficult to transmit). Is preferred.

Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, oxygen included in the oxide 230 is preferably not diffused to the insulator 220 side. In addition, the conductor 203 can be inhibited from reacting with the insulator 224 and oxygen in the oxide 230.

The insulator 222 is, for example, a so-called high material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator containing a -k material in a single layer or a stack. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential at the time of transistor operation while maintaining the physical thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium which is an insulating material having a function of suppressing diffusion of impurities, oxygen, and the like (the above oxygen is difficult to transmit). As an insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 suppresses the release of oxygen from the oxide 230 and the entry of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Act as a layer.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

Further, the insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a combination of an insulator with a high-k material and an insulator 220 provides a stacked structure with high thermal stability and high dielectric constant. Can.

Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.

In the transistor 200, a metal oxide which functions as an oxide semiconductor is preferably used for the oxide 230 including a channel formation region. For example, In-M-Zn oxide as the oxide 230 (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium It is preferable to use a metal oxide such as one or more selected from hafnium, tantalum, tungsten, or magnesium. In addition, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used.

The metal oxide which functions as a channel formation region in the oxide 230 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide with a large band gap, the off-state current of the transistor can be reduced.

The oxide 230 includes the oxide 230a under the oxide 230b, so that diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, by including the oxide 230c over the oxide 230b, diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

Note that the oxide 230 preferably has a stacked-layer structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is larger than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. Is preferred. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide which can be used for the oxide 230a or the oxide 230b can be used.

Further, it is preferable that the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c be higher than the energy at the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.

Here, at the junction of the oxide 230 a, the oxide 230 b, and the oxide 230 c, the energy level at the lower end of the conduction band changes gently. In other words, the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c can be said to be continuously changed or connected continuously. In order to do this, the density of defect states in the mixed layer formed at the interface between the oxide 230 a and the oxide 230 b and at the interface between the oxide 230 b and the oxide 230 c may be lowered.

Specifically, the oxide layer 230a and the oxide layer 230b, and the oxide layer 230b and the oxide layer 230c have a common element other than oxygen (which is a main component), whereby a mixed layer with low defect state density is formed. can do. For example, in the case where the oxide 230b is an In-Ga-Zn oxide, an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like may be used as the oxide 230a and the oxide 230c.

At this time, the main route of the carrier is the oxide 230b. With the oxide 230 a and the oxide 230 c described above, the density of defect states in the interface between the oxide 230 a and the oxide 230 b and the interface between the oxide 230 b and the oxide 230 c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-state current.

A conductor 242 (a conductor 242 a and a conductor 242 b) functioning as a source electrode and a drain electrode is provided over the oxide 230 b. As the conductor 242, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material which maintains conductivity even by absorbing oxygen.

Further, as shown in FIG. 13A, there is a case where a region 243 (a region 243 a and a region 243 b) is formed as a low resistance region at and in the vicinity of the interface of the oxide 230 with the conductor 242. is there. At this time, the region 243a functions as one of a source region or a drain region, and the region 243b functions as the other of the source region or the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 243a and the region 243b.

By providing the conductor 242 in contact with the oxide 230, the oxygen concentration in the region 243 may be reduced. In addition, a metal compound layer containing a metal contained in the conductor 242 and a component of the oxide 230 may be formed in the region 243. In such a case, the carrier density of the region 243 is increased, and the region 243 becomes a low resistance region.

The insulator 244 is provided to cover the conductor 242 and suppresses oxidation of the conductor 242. At this time, the insulator 244 may be provided to cover the side surface of the oxide 230 and to be in contact with the insulator 224.

As the insulator 244, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium may be used. it can.

In particular, as the insulator 244, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like which is an insulator containing one or both oxides of aluminum and hafnium is preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in a later step. Note that the insulator 244 is not an essential component in the case where the conductivity is not significantly reduced even if the conductor 242 has oxidation resistance or absorbs oxygen. It may be appropriately designed according to the transistor characteristics to be obtained.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the inner side (upper surface and side surface) of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in temperature-programmed desorption gas analysis (TDS analysis), the desorption amount of oxygen in terms of molecular oxygen is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ^19. It is an oxide film which is atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ or 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

By providing an insulator from which oxygen is released by heating in contact with the top surface of the oxide 230c as the insulator 250, oxygen can be effectively applied to the channel formation region of the oxide 230b from the insulator 250 through the oxide 230c. Can be supplied. Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

In addition, a metal oxide may be provided between the insulator 250 and the conductor 260 in order to efficiently supply the oxide 230 with excess oxygen of the insulator 250. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing the metal oxide which suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, the decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, the oxidation of the conductor 260 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 244 may be used.

The conductor 260 functioning as the first gate electrode is illustrated as a two-layer structure in FIGS. 13A and 13B, but may be a single-layer structure or a stacked structure of three or more layers. .

The conductor 260a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ etc.), copper atoms, etc. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (eg, oxygen atom, oxygen molecule, and the like). Since the conductor 260a has a function of suppressing the diffusion of oxygen, the oxygen contained in the insulator 250 can suppress the oxidation of the conductor 260b and the decrease in conductivity. As a conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

The conductor 260 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In addition, since the conductor 260b also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a stacked structure, for example, a stacked structure of titanium and titanium nitride and the above conductive material.

The insulator 280 is provided on the conductor 242 via the insulator 244. The insulator 280 preferably has an excess oxygen region. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having voids It is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having holes are preferable because an excess oxygen region can be easily formed in a later step.

The insulator 280 preferably has an excess oxygen region. By providing the insulator 280 from which oxygen is released by heating in contact with the oxide 230c, oxygen in the insulator 280 can be efficiently supplied to the region 234 of the oxide 230 through the oxide 230c. . Note that the concentration of impurities such as water or hydrogen in the insulator 280 is preferably reduced.

The opening of the insulator 280 is formed to overlap with the region between the conductor 242a and the conductor 242b. Thus, the conductor 260 is formed to be embedded in the opening of the insulator 280 and in the region between the conductor 242 a and the conductor 242 b.

In order to miniaturize the semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 260 from being lowered. Therefore, when the film thickness of the conductor 260 is increased, the conductor 260 can have a shape with a high aspect ratio. In this embodiment mode, since the conductor 260 is provided so as to be embedded in the opening of the insulator 280, even if the conductor 260 has a shape with a high aspect ratio, the conductor 260 is formed without collapsing in the process. Can.

The insulator 274 is preferably provided in contact with the top surface of the insulator 280, the top surface of the conductor 260, and the top surface of the insulator 250. By depositing the insulator 274 by a sputtering method, an excess oxygen region can be provided for the insulator 250 and the insulator 280. Thus, oxygen can be supplied to the oxide 230 from the excess oxygen region.

For example, as the insulator 274, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. Can.

In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even if it is a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide film formed by the sputtering method can have not only an oxygen supply source but also a function as a barrier film of an impurity such as hydrogen.

Further, an insulator 281 which functions as an interlayer film is preferably provided over the insulator 274. The insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the film, similarly to the insulator 224 and the like.

Further, the conductor 240 a and the conductor 240 b are provided in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 244. The conductor 240 a and the conductor 240 b are provided opposite to each other with the conductor 260 interposed therebetween. The conductor 240 a and the conductor 240 b have the same configuration as the conductor 246 and the conductor 248 described later.

An insulator 282 is provided on the insulator 281. For the insulator 282, a substance having a barrier property to oxygen or hydrogen is preferably used. Therefore, the same material as the insulator 214 can be used for the insulator 282. For example, for the insulator 282, metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

In particular, aluminum oxide has a high blocking effect of preventing permeation of the film against both oxygen and impurities such as hydrogen and moisture which cause fluctuation of the electrical characteristics of the transistor. Thus, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed in the transistor 200 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide of the transistor 200 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 200.

In addition, an insulator 286 is provided over the insulator 282. The insulator 286 can be made of the same material as the insulator 320. In addition, by using a material having a relatively low dielectric constant as the interlayer film for the insulating film, parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 286.

For the insulator 220, the insulator 222, the insulator 224, the insulator 244, the insulator 280, the insulator 274, the insulator 281, the insulator 282, and the insulator 286, the conductor 246, the conductor 248, and the like Is embedded.

The conductor 246 and the conductor 248 function as a plug or a wiring connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

Subsequently, a capacitor 100 is provided above the transistor 200. The capacitive element 100 includes a conductor 110, a conductor 120, and an insulator 130.

The conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 has a function as a plug connected to the transistor 200 or a wiring. The conductor 110 has a function as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

For the conductor 112 and the conductor 110, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or a metal nitride film containing the above-described element as a component (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide can also be applied.

Although the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 12, the structure is not limited to this structure, and a stacked structure of two or more layers may be used. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor having high adhesion to a conductor having a barrier property and a conductor having high conductivity may be formed.

The conductor 120 is provided to overlap with the conductor 110 through the insulator 130. Note that as the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper) or Al (aluminum) or the like which is a low resistance metal material may be used.

An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Moreover, the insulator 150 may function as a planarizing film which covers the uneven shape below it.

With this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, in a semiconductor device using a transistor including an oxide semiconductor, miniaturization or high integration can be achieved.

<Electrical characteristics of transistor>
Next, the electrical characteristics of the ox transistor will be described. Hereinafter, a transistor having a first gate and a second gate will be described as an example. The transistor having the first gate and the second gate can control the threshold voltage by applying different potentials to the first gate and the second gate. For example, by applying a negative potential to the second gate, the threshold voltage of the transistor can be higher than 0 V and off current can be reduced. That is, by applying a negative potential to the second gate, the drain current when the potential applied to the first electrode is 0 V can be reduced.

In addition, in the oxide semiconductor, when an impurity such as hydrogen is added, the carrier density may increase. For example, when hydrogen is added, an oxide semiconductor may react with oxygen which is bonded to a metal atom to be water and form oxygen vacancies. Carrier density is increased by the entry of hydrogen into the oxygen vacancies. In addition, a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. That is, an oxide semiconductor to which an impurity such as hydrogen is added has n-type conductivity, and thus has low resistance.

Therefore, the resistance of the oxide semiconductor can be selectively reduced. That is, providing an oxide semiconductor with a region having low carrier density and functioning as a channel formation region and a low-resistance region having high carrier density and functioning as a source region or a drain region it can.

Embodiment 4
In this embodiment mode, a structure of a metal oxide which can be used for the ox transistor described in the above embodiment mode will be described.

<Structure of Metal Oxide>
In the specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a structure of a material.

The CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor throughout the material. Note that in the case where CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is electrons serving as carriers. Is a function that does not A function of switching (function of turning on / off) can be imparted to the CAC-OS or the CAC-metal oxide by causing the conductive function and the insulating function to be complementary to each other. By separating the functions of CAC-OS or CAC-metal oxide, both functions can be maximized.

In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed as connected in a cloud shape with a blurred periphery.

In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from the insulating region and a component having a narrow gap resulting from the conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above-described CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on current, and high field effect mobility can be obtained in the on state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite (matrix composite) or a metal matrix composite (metal matrix composite).

<Structure of metal oxide>
Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As the non-single crystal oxide semiconductor, for example, c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), pseudo amorphous oxide semiconductor (a-like) OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

The CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure. Note that distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

The nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon. In the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) can not be confirmed near the strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is thought that it is for.

In addition, a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as a (In, M, Zn) layer. In addition, when indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, CAAC-OS can not confirm clear crystal grain boundaries, so that it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, generation of defects, or the like, so that the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, the oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable also to a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when a CAAC-OS is used for the ox transistor, the degree of freedom of the manufacturing process can be expanded.

The nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<Transistor with Oxide Semiconductor>
Subsequently, a case where the above oxide semiconductor is used for a transistor will be described.

Note that by using the above oxide semiconductor for the transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, an oxide semiconductor with low carrier density is preferably used for the transistor. In the case of reducing the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In the present specification and the like, the low impurity concentration and the low density of defect level states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. It should be cm ³ or more.

In addition, since the high purity intrinsic or the substantially high purity intrinsic oxide semiconductor film has a low density of defect states, the density of trap states may also be low.

In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave like fixed charge. Therefore, the transistor in which the channel formation region is formed in the oxide semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

<Impurity>
Here, the influence of each impurity in the oxide semiconductor is described.

In the oxide semiconductor, when silicon or carbon which is one of the group 14 elements is contained, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × ¹⁰ 18 atoms / cm ³ or less, preferably 2 × ¹⁰ 17 atoms / cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state may be formed and a carrier may be generated. Therefore, a transistor including an oxide semiconductor which contains an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in an oxide semiconductor, electrons which are carriers are generated, carrier density is increased, and n-type is easily formed. As a result, a transistor in which an oxide semiconductor containing nitrogen is used as a semiconductor is likely to be normally on. Therefore, in the oxide semiconductor, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ^{18 in} SIMS. atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. In addition, a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Thus, a transistor including an oxide semiconductor which contains hydrogen is likely to be normally on. Thus, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. ^{It is} less than ³ and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced for the channel formation region of the transistor, stable electrical characteristics can be provided.

This embodiment can be combined with the description of the other embodiments as appropriate.

Fifth Embodiment
In this embodiment mode, electronic devices to which the integrated circuit described in the above embodiment modes can be applied are described.

<Electronic equipment / system>
A GPU or a computer according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc. In addition to electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. may be mentioned. In addition, by providing the integrated circuit or the computer according to one embodiment of the present invention to an electronic device, artificial intelligence can be mounted on the electronic device.

The electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow, humidity, inclination, vibration, odor or infrared.

The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided. FIG. 14 shows an example of the electronic device.

[mobile phone]

FIG. 14A shows a mobile phone (smart phone) which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511. A touch panel is provided in the display portion 5511 as an input interface, and a button is provided in the housing 5510.

The information terminal 5500 can execute an application using artificial intelligence by applying the computer of one embodiment of the present invention. As an application using artificial intelligence, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5511, recognizes characters, figures, and the like input by the user with respect to a touch panel included in the display unit 5511; An application displayed on the display portion 5511, an application for performing biometric authentication such as fingerprint or voiceprint, and the like can be given.

[Information terminal 1]
A desktop information terminal 5300 is illustrated in FIG. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

The desktop information terminal 5300 can execute an application using artificial intelligence by applying the computer of one embodiment of the present invention, as in the case of the information terminal 5500 described above. Examples of applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. In addition, by using the desktop information terminal 5300, new artificial intelligence can be developed.

In the above description, although the smartphone and the desktop information terminal are illustrated as examples of the electronic device in FIGS. 14A and 14B, an information terminal other than the smartphone and the desktop information terminal may be applied. it can. As an information terminal other than a smart phone and a desktop information terminal, for example, a PDA (Personal Digital Assistant), a notebook information terminal, a work station, etc. may be mentioned.

[Electronics]
FIG. 14C illustrates an electric refrigerator-freezer 5800 which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803 and the like.

By applying the computer of one embodiment of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 is automatically stored in the electric refrigerator-freezer 5800, which automatically generates a menu based on the food stored in the electric refrigerator-freezer 5800, the expiration date of the food, etc. It can have a function of automatically adjusting to the temperature according to the food.

In this example, the electric refrigerator-freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner. Appliances, washing machines, dryers, audiovisual equipment etc. may be mentioned.

[game machine]

FIG. 14D illustrates a portable game console 5200 which is an example of the game console. The portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.

By applying the GPU or the computer of one embodiment of the present invention to the portable game device 5200, a low-power consumption portable game device 5200 can be realized. Further, since low power consumption can reduce heat generation from the circuit, it is possible to reduce the influence of heat generation on the circuit itself, peripheral circuits, and modules.

Furthermore, by applying the GPU or the computer of one embodiment of the present invention to the portable game device 5200, a portable game device 5200 having artificial intelligence can be realized.

Originally, expressions such as the progress of the game, the behavior and behavior of creatures appearing on the game, and the phenomena occurring on the game are determined by the program possessed by the game, but by applying artificial intelligence to the portable game machine 5200 The expression which is not limited to the program of the game becomes possible. For example, it is possible to express that the contents asked by the player, the progress of the game, the time, and the behavior of the person appearing on the game change.

In addition, when playing a game that requires a plurality of players in the portable game machine 5200, since the game player can be artificially constructed by artificial intelligence, even by using an opponent as a game player by artificial intelligence, even one person can play a game. I can play the game.

Although FIG. 14D illustrates a portable game machine as an example of the game machine, a game machine to which the GPU or the computer of one embodiment of the present invention is applied is not limited thereto. As a game machine to which the GPU or computer of one aspect of the present invention is applied, for example, a home-use stationary game machine, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a sports facility Pitching machines for batting practice.

[Mobile body]
The GPU or computer of one embodiment of the present invention can be applied to an automobile that is a mobile body and around the driver's seat of the automobile.

FIG. 14 (E1) shows a car 5700 which is an example of a moving body, and FIG. 14 (E2) shows a periphery of a windshield in a room of the car. FIG. 14E1 illustrates the display panel 5704 attached to the pillar, in addition to the display panel 5701 attached to the dashboard, the display panel 5702, and the display panel 5703.

The display panel 5701 to the display panel 5703 can provide various other information such as a speedometer, a tachometer, a travel distance, a refueling amount, a gear state, setting of an air conditioner, and the like. In addition, display items, layouts, and the like displayed on the display panel can be appropriately changed in accordance with the user's preference, and design can be enhanced. The display panels 5701 to 5703 can also be used as lighting devices.

By projecting an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, it is possible to complement the view (dead angle) blocked by the pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated to enhance safety. In addition, by displaying an image that complements the invisible part, it is possible to check the safety more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

Since the GPU or computer of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the computer can be used for an autonomous driving system of a car 5700. Further, the computer can be used for a system that performs road guidance, danger prediction, and the like. Information such as road guidance and danger prediction may be displayed on the display panel 5701 to the display panel 5704.

In addition, although the motor vehicle is demonstrated as an example of a mobile body in the above-mentioned, a mobile body is not limited to a motor vehicle. For example, the moving object may also be a train, a monorail, a ship, a flying object (helicopter, unmanned aircraft (drone), airplane, rocket) or the like, and the computer of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be provided.

[Broadcasting system]
The GPU or computer of one embodiment of the present invention can be applied to a broadcast system.

FIG. 14F schematically shows data transmission in the broadcast system. Specifically, FIG. 14F shows a path until the radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches the television receiver (TV) 5600 of each home. The TV 5600 includes a receiver (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 through the receiver.

In FIG. 14F, the antenna 5650 is a UHF (Ultra High Frequency) antenna. However, as the antenna 5650, a BS · 110 ° CS antenna, a CS antenna, or the like can be used.

The radio wave 5675A and the radio wave 5675B are broadcast signals for ground wave broadcasting, and the radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. Each household can view terrestrial TV broadcast on the TV 5600 by receiving the radio wave 5675 B by the antenna 5650. The broadcast system is not limited to the terrestrial broadcast shown in FIG. 14F, and may be satellite broadcast using an artificial satellite, data broadcast by an optical circuit, or the like.

The broadcast system described above may be a broadcast system using artificial intelligence by applying the computer of one embodiment of the present invention. When broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each home, compression of the broadcast data is performed by the encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving apparatus included in the TV 5600 Restoration is performed. By utilizing artificial intelligence, for example, in motion compensation prediction which is one of compression methods of an encoder, it is possible to recognize a display pattern included in a display image. In addition, intra-frame prediction using artificial intelligence can also be performed. In addition, for example, when broadcast data with low resolution is received and the broadcast data is displayed by the TV 5600 with high resolution, image interpolation processing such as up conversion can be performed in restoration of broadcast data by the decoder.

The above-described broadcast system using artificial intelligence is suitable for ultra high definition television (UHDTV: 4K, 8K) broadcast where the amount of broadcast data is increased.

In addition, as an application of artificial intelligence on the TV 5600 side, for example, the TV 5600 may be provided with a recording device having artificial intelligence. With such a configuration, it is possible to automatically record a program according to the user's preference by making the recording device learn the user's preference to the artificial intelligence.

<Parallel computer>
A parallel computer can be configured by clustering a plurality of computers of one embodiment of the present invention.

A large parallel computer 5400 is illustrated in FIG. In the parallel computer 5400, a plurality of rack mount computers 5420 are stored in the rack 5410.

The calculator 5420 can have, for example, a configuration of a perspective view shown in FIG. In FIG. 15B, a calculator 5420 has a mother board 5430, and the mother board has a plurality of slots 5431, a plurality of connection terminals 5432, and a plurality of connection terminals 5433. The PC card 5421 is inserted in the slot 5431. In addition, the PC card 5421 has a connection terminal 5423, a connection terminal 5424, and a connection terminal 5425, which are connected to the mother board 5430, respectively.

The PC card 5421 is the processing board provided with the CPU, the GPU, the storage device, and the like described in the first embodiment. For example, in FIG. 15C, the PC card 5421 has a board 5422, and the board 5422 includes a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, a chip 5426, a chip 5427, a connection terminal 5428, Shows a configuration having Note that FIG. 15C illustrates a chip other than the chip 5426 and the chip 5427, but the description of the chips 5426 and 5427 described below is referred to for those chips.

The connection terminal 5428 has a shape that can be inserted into the slot 5431 of the motherboard 5430, and the connection terminal 5428 functions as an interface for connecting the PC card 5421 and the motherboard 5430. Examples of the standard of the connection terminal 5428 include PCIe and the like.

The connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 can be, for example, an interface for supplying power, inputting a signal, or the like to the PC card 5421. Also, for example, an interface for outputting a signal calculated by the PC card 5421 can be used. Examples of the respective standards of the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). Further, in the case of outputting a video signal from the connection terminal 5423, the connection terminal 5424, and the connection terminal 5425, examples of the respective standards include HDMI (registered trademark).

The chip 5426 has a terminal (not shown) for inputting and outputting signals, and the chip 5426 and the PC card 5421 can be inserted by inserting the terminal into a socket (not shown) of the PC card 5421. Can be connected electrically. The chip 5426 can be, for example, the GPU described in the above embodiment.

The chip 5427 has a plurality of terminals, and the terminals are electrically connected to the PC card 5421 by, for example, performing reflow soldering to the wiring of the PC card 5421. can do. As the chip 5427, for example, a memory device, a field programmable gate array (FPGA), a CPU, or the like can be given.

By applying the computer of one embodiment of the present invention to the computer 5420 of the parallel computer 5400 illustrated in FIG. 15A, large-scale calculations necessary for, for example, learning and reasoning of artificial intelligence can be performed.

<Server and System Including Server>
The computer of one embodiment of the present invention can be applied to, for example, a server that functions over a network. Moreover, thereby, the system containing the said server can be comprised.

FIG. 16A schematically shows, as an example, communication between server 5100 to which the computer of one embodiment of the present invention is applied, and information terminal 5500 and desktop information terminal 5300 described above. Is shown. In FIG. 16A, the communication 5110 is illustrated as the communication is performed.

By configuring such a form, the user can access the server 5100 from the information terminal 5500, the desktop information terminal 5300, and the like. Then, the user can receive the service provided by the administrator of the server 5100 through the communication 5110 via the Internet. Such services include, for example, electronic mail, social networking services (SNS), online software, cloud storage, navigation systems, translation systems, internet games, online shopping, financial transactions such as stocks / forex / credits, public facilities / commercial facilities・ Reservation of accommodation facilities and hospitals, watching of videos such as Internet programs, lectures and lectures, etc.

In particular, by applying the computer of one embodiment of the present invention to the server 5100, artificial intelligence may be able to be used in the above-described service. For example, by introducing artificial intelligence to a navigation system, the system may be able to adaptively guide to a destination according to the congestion of roads, train operation information, and the like. Also, for example, by introducing artificial intelligence into a translation system, the system may be able to appropriately translate unique expressions such as dialects and slang. In addition, for example, by using artificial intelligence for a reservation system such as a hospital, the system may be able to introduce an appropriate hospital, a doctor's office, etc. judging from the user's symptoms and degree of injury etc. is there.

When the user wants to develop artificial intelligence, the server 5100 can be accessed via the Internet, and the development can be performed on the server 5100. This is suitable when, for example, the information terminal 5500 and the desktop information terminal 5300 at hand of the user do not have sufficient processing capability, and the development terminal can not be constructed with the information terminal 5500 and the desktop information terminal 5300.

16A shows an example of a system including an information terminal and a server 5100 as a system including a server, but as another example, the system includes an electronic device other than the information terminal and the server 5100 System may be used. That is, the electronic device may be connected to the Internet in the form of Internet of Things (IoT).

16B schematically shows, as an example, communication between the electronic device (electric refrigerator-freezer 5800, portable game machine 5200, car 5700, TV 5600) described in FIG. 14 and the server 5100. There is. In FIG. 16B, the communication 5110 is illustrated as the communication is performed.

When artificial intelligence is applied to each of the electronic devices described with reference to FIG. 14, as shown in FIG. 16B, the server 5100 can execute calculations required to operate the artificial intelligence. For example, input data required for calculation is transmitted from one of the electronic devices to the server 5100 by the communication 5110, and artificial intelligence of the server 5100 is used to calculate output data based on the input data. The output data is transmitted from the server 5100 to one of the electronic devices by the communication 5110. Thus, one of the electronic devices can perform an operation based on the data output from the artificial intelligence.

The electronic device illustrated in FIG. 16B is an example, and an electronic device not illustrated in FIG. 16B may be connected to the server 5100 to perform communication with each other as described above.

The electronic device described in this embodiment, the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be combined with the description of other electronic devices as appropriate.

This embodiment can be combined with the description of the other embodiments as appropriate.

DESCRIPTION OF REFERENCE NUMERALS 10 integrated circuit 11 source driver 12 gate driver 13 input buffer 50 computer 51 processing unit 52 storage unit 53 computing unit 54 input unit 55 output unit 56 transmission path 100 capacitive element 103 processing unit 110 conductor 112 conductor 120 conductor 130 insulator 130 insulator 150 insulator 200 transistor 203 conductor 203a conductor 203b conductor 210 insulator 212 insulator 214 insulator 216 insulator 218 conductor 220 insulator 222 insulator 224 insulator 230 oxide 230a oxide 230b oxide 230c oxide 234 region 240 a conductor 240 b conductor 242 conductor 242 a conductor 242 b conductor 243 region 243 a region 243 b region 244 insulator 246 conductor 248 conductor 250 insulator 260 conductor 260 a conductor 260 b Conductor 274 insulator 280 insulator 281 insulator 282 insulator 286 insulator 300 transistor 311 substrate 313 semiconductor region 314 a low resistance region 314 b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 350 insulator 352 insulator 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 376 insulator 380 conductor 382 insulator 382 insulator 384 insulator Body 386 Conductor 1001 Wiring 1002 Wiring 1003 Wiring 1005 Wiring 1005 Wiring 1005 Wiring 5100 Server 5110 Communication 5200 Mobile game machine 5201 Housing 5202 Display 5203 Button 5300 Desktop information terminal 5301 Main unit 5302 display 5303 keyboard 5400 parallel computer 5410 rack 5420 computer 5421 PC card 5422 connection terminal 5424 connection terminal 5425 connection terminal 5426 chip 5427 chip 5428 connection terminal 5430 motherboard 5431 slot 5432 connection terminal 5433 connection terminal 5500 information terminal 5510 housing 5511 display Part 5600 TV
5650 antenna 5670 radio wave tower 5675A radio wave 5675B radio wave 5680 broadcasting station 5700 display panel 5702 display panel 5703 display panel 5704 display panel 5800 electric refrigerator-freezer 5801 housing 5802 refrigerator compartment door 5803 refrigerator compartment door

Claims (5)

A first arithmetic circuit and a second arithmetic circuit,
The first arithmetic circuit includes a first product-sum arithmetic circuit having a first transistor, and a first hierarchical output circuit.
The second arithmetic circuit includes a second product-sum arithmetic circuit having a second transistor, and a second hierarchical output circuit.
The channel length direction of the first transistor and the channel length direction of the second transistor are parallel,
The first product-sum operation circuit and the second product-sum operation circuit have a function of outputting third data corresponding to the result of the product-sum operation of the first data and the second data,
The first hierarchical output circuit and the second hierarchical output circuit have a function of converting the third data based on an activation function and outputting analog data or multilevel digital data.
An integrated circuit to which analog data or multilevel digital data output from the first layer output circuit is input to the second product-sum operation circuit. In claim 1,
The integrated circuit in which the channel width direction of the first transistor and the channel width direction of the second transistor are parallel. In claim 1 or claim 2,
An integrated circuit in which the first transistor and the second transistor include a metal oxide in a channel formation region.   A computer comprising: an operation unit having the integrated circuit according to any one of claims 1 to 3; a processing unit; and a storage unit.   An electronic device comprising the integrated circuit according to any one of claims 1 to 4 or the computer according to claim 4.

Images