JP2019046199A5 - - Google Patents

Claims (8)

It is a processor having a chip provided with a CPU and a GPU.
Each of the CPU and the GPU has one or more power domains capable of power gating.
The CPU is provided with a flip-flop to which a backup circuit is electrically connected.
The GPU is provided with a plurality of multipliers arranged in a matrix.
The multiplier comprises a first transistor, a second transistor, a capacitive element and a holding node.
The gate of the second transistor and the terminal of the capacitive element are electrically connected to the holding node, respectively.
The first transistor has a function of controlling writing of data to the holding node.
It said transistor backup circuits, in each of the first transistor of the multiplier, that the channel formation region have a metal oxide processor. In claim 1,
It said backup circuit may include a processor that is laminated to the flip-flop. In claim 1 or 2,
The data to be written to the hold node multipliers Oh Ru processor in analog data. In any one of claims 1 to 3,
The CPU is further provided with a first memory device.
In the memory cell of the first memory device, a processor in which a channel forming region of a writing transistor is formed of a metal oxide. In any one of claims 1 to 4,
The CPU is further provided with a second memory device.
A backup circuit is provided in the memory cell of the second memory device.
In the transistor of the backup circuit , the channel forming region is a processor having a metal oxide. In any one of claims 1 to 5,
Further, a third memory device is provided on the chip.
The third memory device is accessible to the CPU or the GPU.
In the memory cell of the third memory device, the channel formation region of the write transistor is a processor formed of a metal oxide. In any one of claims 1 to 6,
The CPU is a processor having a plurality of CPU cores. An electronic device incorporating the processor according to any one of claims 1 to 7.