JP2019045613A - Display device and electronic apparatus - Google Patents

Abstract

To provide a display device capable of performing image processing.SOLUTION: Pixel units each including two pixels are provided in a matrix, and each pixel is provided with a memory circuit, and the memory circuit holds a desired correction signal. The correction signal is calculated by an external apparatus and written into each pixel. The correction signal is added to an image signal by capacitive coupling and supplied to a display element. Therefore, the display element can display a corrected image. By the correction, it is possible to perform up conversion of the image and correction of image quality due to characteristic variation of a transistor of the pixel.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a display device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the present specification and the like relates to an object, a method, or a method of manufacturing. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in the present specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light emitting device, a lighting device, a power storage device, a storage device, an imaging device, and the like. A driving method or a method of manufacturing them can be mentioned as an example.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, the memory device, the display device, the imaging device, and the electronic device may include a semiconductor device.

A technique for forming a transistor using a metal oxide formed on a substrate has attracted attention. For example, Patent Document 1 and Patent Document 2 disclose a technique in which a transistor using zinc oxide or an In—Ga—Zn-based oxide is used as a switching element of a pixel of a display device or the like.

Further, Patent Document 3 discloses a memory device having a configuration in which a transistor with extremely low off-state current is used for a memory cell.

Further, Patent Document 4 discloses a display panel having a reflective liquid crystal element and an organic EL element as display elements and capable of performing high-visibility display with both display elements or one display element according to the environment. It is done.

Unexamined-Japanese-Patent No. 2007-123861 JP 2007-96055 A JP 2011-119674 A JP, 2017-037288, A

In a display device, the resolution has been increased, and hardware capable of performing display at 8K4K (number of pixels: 7680 × 4320) resolution or higher has been developed. On the other hand, since high-resolution image sources are enormous, peripheral technologies such as imaging devices, storage devices, communication devices, etc. need to be prepared in order to be widely used.

Upconversion is another technique for generating high resolution image sources. By performing up-conversion, it is possible to convert a low resolution image into a high resolution image in a pseudo manner. Since up-conversion is performed on the peripheral device of the display device, conventional techniques can be used for devices that handle the image source before up-conversion.

However, in an apparatus that performs up-conversion, a large image signal is analyzed to generate a new image signal, so that there is a problem that the circuit size and the power consumption increase. In addition, processing in real time may not catch up and display delay may occur.

Upconversion has such a problem, but, for example, there may be a possibility of alleviating problems such as power consumption and delay by distributing the function related to the upconversion to a plurality of devices.

In addition, in a display device including an EL element or the like, variation in characteristics of transistors included in a pixel is a factor of deterioration in display quality. As means for correcting the characteristic variation of the transistor, there are an internal correction that corrects an image signal by a circuit incorporated in the pixel, and an external correction that acquires a correction value for each pixel and supplies the corrected image signal to the pixel.

Although internal correction can be performed on a frame-by-frame basis, a high resolution display device shortens the horizontal selection period, making it difficult to secure the correction period. Further, although external correction is effective for a high resolution display device, since it is necessary to correct all image signals, the burden on external devices becomes large. Ideally, it is preferable to operate without correction, but since it is extremely difficult to suppress transistor characteristic variations, new correction means are desired.

In addition, in display devices included in electronic devices, a transmissive liquid crystal element using a backlight as a light source, a self-emitting organic EL element, and the like are often used. Although these display elements have good visibility indoors, external light is strongly reflected on the display surface under strong light such as outdoors under fine weather, so that light (display) visible from the inside of the display device is visible Sex is reduced.

On the contrary, since the reflective display element is not sufficient in the indoor visibility where the external light intensity is weak, it is suitable to be used according to the environmental change by using a transmissive liquid crystal element, a self-luminous organic EL element and the like in combination. It is preferable to perform display with a display element.

Therefore, one object of one embodiment of the present invention is to provide a display device capable of performing image processing. Another object is to provide a display device capable of performing an up-conversion operation. Another object is to provide a display device capable of correcting an image signal. Another object is to provide a display device with high visibility even under strong light.

Another object is to provide a display device with low power consumption. Alternatively, it is an object to provide a highly reliable display device. Another object is to provide a novel display device or the like. Another object is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. In addition, problems other than these are naturally apparent from the description of the specification, drawings, claims and the like, and it is possible to extract the problems other than these from the description of the specification, drawings, claims and the like. It is.

One embodiment of the present invention relates to a display device capable of performing image processing. Alternatively, the present invention relates to a display device capable of correcting an image signal.

One embodiment of the present invention is a display device including a pixel in which a first display element, a second display element, a first memory circuit, and a second memory circuit are provided. The memory circuit has a function of storing a first correction signal, the second memory circuit has a function of storing a second correction signal, and the first memory circuit has a function of storing the first correction signal. Is added to the first image signal to generate the third image signal, and the second memory circuit adds the second correction signal to the second image signal to generate the fourth image signal. And the first display element has a function to perform display based on the third image signal, and the second display element has a function to perform display based on the fourth image signal. A display device having

A reflective liquid crystal element can be used for the first display element. In addition, an organic EL element can be used for the second display element.

It has a function of displaying an image by one or both of the first light reflected by the first display element and the second light emitted by the second display element.

The pixel configuration includes a first transistor, a second transistor, and a first capacitance element, and one of the source and the drain of the first transistor is one electrode of the first capacitance element. And one electrode of the first capacitive element is electrically connected to the first display element, and one of the source and drain of the second transistor is the other of the first capacitive element. The other electrode of the first capacitor element is electrically connected to the electrode and can be electrically connected to the first memory circuit.

The first memory circuit includes a third transistor, a fourth transistor, and a second capacitor, and a gate of the third transistor is electrically connected to one of the source and the drain of the fourth transistor. Connected, one of the source or the drain of the fourth transistor is electrically connected to one electrode of the second capacitive element, and one of the source or the drain of the third transistor is a first capacitive element Can be electrically connected to the other electrode of the

At least a fourth transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd Or Hf) is preferable.

In addition, the other of the source or the drain of the second transistor is electrically connected to the low potential power supply line, and the other of the source or the drain of the third transistor is electrically connected to the high potential power supply line Is preferred.

And a fifth transistor and a sixth transistor, wherein one of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the first transistor; The other of the source and the drain of the transistor is electrically connected to the display element, and one of the source or the drain of the sixth transistor is electrically connected to the other of the source or the drain of the fifth transistor; The other of the source and the drain of the transistor may be electrically connected to the low potential power supply line.

In the pixel configuration, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the third capacitance element, and the fourth capacitance element And one of the source or drain of the seventh transistor is electrically connected to one of the electrodes of the third capacitive element, and one of the electrodes of the third capacitive element is the one of the eighth transistor. One of the source and drain electrically connected, the other of the source and drain of the eighth transistor is electrically connected to one of the source and drain of the ninth transistor, and the source or drain of the ninth transistor is electrically connected One is electrically connected to one electrode of the fourth capacitive element, and the other of the source and the drain of the ninth transistor is electrically connected to the low potential power supply line. And one electrode of the fourth capacitive element is electrically connected to the gate of the tenth transistor, and one of the source or drain of the tenth transistor is electrically connected to the other electrode of the fourth capacitive element. And the other electrode of the fourth capacitive element is electrically connected to one of the electrodes of the second display element, and one of the source and the drain of the eleventh transistor is the other of the third capacitive element. The other electrode of the third capacitor element may be electrically connected to the second memory circuit.

The second memory circuit includes a twelfth transistor, a thirteenth transistor, and a fifth capacitance element, and a gate of the twelfth transistor is electrically connected to one of a source and a drain of the thirteenth transistor. Connected, one of the source or the drain of the thirteenth transistor is electrically connected to one electrode of the fifth capacitive element, and one of the source or the drain of the twelfth transistor is a third capacitive element Can be electrically connected to the other electrode of the

At least a thirteenth transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd Or Hf) is preferable.

By using one embodiment of the present invention, a display device capable of performing image processing can be provided. Alternatively, a display device which can perform up-conversion operation can be provided. Alternatively, a display device capable of correcting an image signal can be provided. Alternatively, a display device with high visibility even in strong light can be provided.

Alternatively, a display device with low power consumption can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device or the like can be provided. Alternatively, a method of driving the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

FIG. 6 illustrates a pixel circuit. 5 is a timing chart illustrating operation of a pixel circuit. The figure explaining up conversion. 7A and 7B illustrate a pixel circuit and a timing chart illustrating operation of the pixel circuit. FIG. 6 illustrates a pixel circuit. FIG. 6 illustrates a pixel circuit. FIG. 6 illustrates a pixel circuit. FIG. 18 is a block diagram illustrating a display device. FIG. 6 illustrates a pixel circuit. FIG. FIG. FIG. 10 is a top view of a pixel of a display device. FIG. 8 illustrates a display device. FIG. 8 illustrates a display device. FIG. 6 is a diagram for explaining an example of an operation mode of a display device. The figure explaining the structural example of a neural network. 5A and 5B illustrate a configuration example of a semiconductor device. 5A to 5C illustrate an example of a configuration of a memory cell. The figure explaining the structural example of an offset circuit. 7 is a timing chart illustrating operation of a semiconductor device. 5A to 5C illustrate electronic devices.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof may not be repeated. Note that hatching of the same elements that make up a drawing may be omitted or changed as appropriate between different drawings.

Embodiment 1
In this embodiment, a display device which is an embodiment of the present invention will be described with reference to the drawings.

One embodiment of the present invention is a display device having a structure in which pixel units each having two pixels are provided in a matrix and having a function for adding a correction signal to an image signal. Each pixel is provided with a display element and a memory circuit, and the memory circuit holds a desired correction signal. The correction signal is generated by an external device and written to each pixel.

The correction signal is added to the image signal by capacitive coupling and supplied to the display element. Therefore, the display device can display the corrected image. By the correction, it is possible to perform image upconversion or correction of the image quality which is deteriorated due to the characteristic variation of the transistor included in the pixel.

FIG. 1 is a diagram for explaining a pixel unit 11e that can be used for the display device of one embodiment of the present invention. The pixel unit 11 e has a first pixel 17 provided with a first display element and a second pixel 18 provided with a second display element.

The first display element has a function of reflecting visible light, and the second display element has a function of emitting visible light. Therefore, display with good visibility can be performed with low power consumption, such as operating the first display element under strong light and operating the second display element under weak light.

For example, a reflective liquid crystal element can be used as the first display element. For example, a light emitting element can be used as the second display element. A reflective liquid crystal element consumes less power and can provide a highly visible display even under sunlight when it is fine. The light-emitting element can perform display with high visibility in indoor light or outdoors in cloudy weather.

The first pixel 17 includes a transistor 101L, a transistor 102L, a transistor 106L, a transistor 107L, a transistor 115L, a transistor 116L, a capacitor 103L, a capacitor 104L, a capacitor 117L, and a first display. A liquid crystal element 105L is provided as an element.

One of the source and the drain of the transistor 101L is electrically connected to one electrode of the capacitor 103L. One electrode of the capacitor 103L is electrically connected to one of the source and the drain of the transistor 106L. The other of the source and the drain of the transistor 106L is electrically connected to one of the source and the drain of the transistor 107L. One of the source and the drain of the transistor 107L is electrically connected to one electrode of the capacitor 104L. One electrode of the capacitor 104L is electrically connected to the liquid crystal element 105L. One of the source and the drain of the transistor 102L is electrically connected to the other electrode of the capacitor 103L. The other electrode of the capacitor 103L is electrically connected to one of the source and the drain of the transistor 116L. The gate of the transistor 116L is electrically connected to one of the source and the drain of the transistor 115L. One of the source and the drain of the transistor 115L is electrically connected to one electrode of the capacitor 117L.

Here, a wiring to which one of the source and the drain of the transistor 101L, one of the electrodes of the capacitor 103L, and one of the source and the drain of the transistor 106L are connected is a node NAL. A wiring to which the other of the source and the drain of the transistor 106L, one of the electrodes of the capacitor 104L, and one of the electrodes of the liquid crystal element 105L are connected is a node NBL. Further, a wiring to which the other electrode of the capacitor 103L, one of the source or the drain of the transistor 102L, and one of the source or the drain of the transistor 116L is connected is a node NRL. A wiring to which the gate of the transistor 116L, one of the source and the drain of the transistor 115L, and one electrode of the capacitor 117L are connected is a node NML.

The gate of the transistor 101L and the gate of the transistor 106L are electrically connected to the wiring 123L. The gate of the transistor 102L is electrically connected to the wiring 123L. The gate of the transistor 107L and the other electrode of the capacitor 117L are electrically connected to the wiring 121L. The gate of the transistor 115L is electrically connected to the wiring 122L. The other of the source and the drain of the transistor 115L is electrically connected to the wiring 124L.

The other of the source and the drain of the transistor 116L is electrically connected to the power supply line (high potential). The other of the source and the drain of the transistor 102L is electrically connected to the power supply line (low potential). The other of the source and the drain of the transistor 107L is electrically connected to the power supply line (low potential). The other electrode of the capacitor 104L is electrically connected to the common wiring 127L. The other electrode of the liquid crystal element 105L is electrically connected to the common wiring 128L. Note that any potential can be supplied to the common wires 127L and 128L, and both may be electrically connected.

The wirings 122L, 123L, and 126L can have a function as signal lines for controlling the operation of the transistors. The wiring 125L can have a function as a signal line for supplying an image signal. The wiring 121L and the wiring 124L can have a function as signal lines for operating the memory circuit MEML described below.

The transistor 115L, the transistor 116L, and the capacitor 117L form a memory circuit MEML. The node NML is a storage node, and the signal supplied to the wiring 124L can be written to the node NML by turning on the transistor 115L. By using a transistor with extremely low off-state current as the transistor 115L, the potential of the node NML can be held for a long time. For example, a transistor in which a metal oxide is used for a channel formation region (hereinafter referred to as an OS transistor) can be used as the transistor.

Note that the OS transistor may be applied not only to the transistor 115L but also to other transistors included in the pixel. Further, a transistor having Si in a channel formation region (hereinafter, a Si transistor) may be applied to the transistor 115L. Alternatively, both an OS transistor and a Si transistor may be used. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low temperature polysilicon), a transistor having single crystal silicon, and the like.

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium, or the like can be used, for example, the following CAAC-OS or CAC-OS can be used. In the CAAC-OS, atoms constituting a crystal are stable and suitable for a transistor or the like in which reliability is important. Further, since CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like which performs high-speed driving.

An OS transistor exhibits extremely low off-current characteristics because of its large energy gap. In addition, the OS transistor has characteristics different from that of the Si transistor, such as no impact ionization, avalanche breakdown, short channel effect, and the like, and can form a highly reliable circuit.

The semiconductor layer included in the OS transistor is, for example, an In-M-Zn-based oxide containing indium, zinc and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). The film can be represented by

In the case where the oxide semiconductor forming the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. The atomic ratio of the metal elements of such a sputtering target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3: In: M: Zn = 4: 2: 4: In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.

For the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3 ³ or less, more preferably less than 1 × ^{10 10} / cm ^3, it is possible to use an oxide semiconductor of 1 × ¹⁰ -9 / cm ³ or more carrier density. Such an oxide semiconductor is referred to as a high purity intrinsic or substantially high purity intrinsic oxide semiconductor. Accordingly, the impurity concentration is low and the density of defect states is low, so that the oxide semiconductor can be said to be an oxide semiconductor having stable characteristics.

Note that the composition is not limited to those described above, and a composition having an appropriate composition may be used in accordance with the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, and the like) of the required transistor. In addition, in order to obtain semiconductor characteristics of a required transistor, it is preferable to make appropriate the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like in the semiconductor layer. .

When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor forming the semiconductor layer, oxygen vacancies increase and n-type conductivity is obtained. Therefore, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, a carrier may be generated, which may increase the off-state current of the transistor. Therefore, the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less Make it

In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons which are carriers are generated, carrier density is increased, and n-type is easily formed. As a result, a transistor including an oxide semiconductor which contains nitrogen is likely to be normally on. Therefore, the nitrogen concentration (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure is, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor, or a C-Axis Aligned and AB-plane Anchored Crystalline Oxide Semiconductor) having a crystal oriented in the c-axis, a polycrystalline structure, A microcrystalline structure or an amorphous structure is included. In the non-single crystal structure, the amorphous structure has the highest density of defect states, and CAAC-OS has the lowest density of defect states.

The oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystalline component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.

Note that the semiconductor layer may be a mixed film having two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having a CAAC-OS, and a region having a single crystal structure. Good. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

Hereinafter, a structure of a Cloud-Aligned Composite (CAC) -OS which is one embodiment of a non-single-crystal semiconductor layer is described.

The CAC-OS is, for example, a configuration of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that in the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less The state of mixing in is also called mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium etc. One or more selected from the above may be included.

For example, CAC-OS in the In-Ga-Zn oxide (an In-Ga-Zn oxide among the CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium Oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)), or gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That is, the CAC-OS is a complex oxide semiconductor having a structure in which a region in which GaO _X3 is a main component and a region in which In _{X 2} Zn _{Y 2} O _{Z 2} or InO _{X 1} is a main component are mixed. Note that in this specification, for example, the ratio of the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, It is assumed that the concentration of In is higher than that in the region 2.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are _represented by InGaO 3 _(ZnO) m1 (m1 is a natural number), or _{In (1 + x0) Ga (} 1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

On the other hand, CAC-OS relates to the material configuration of an oxide semiconductor. The CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material configuration including In, Ga, Zn, and O, and nanoparticles composed mainly of In in some components. The area | region observed in shape says the structure currently disperse | distributed to mosaic shape at random, respectively. Therefore, in CAC-OS, the crystal structure is a secondary element.

Note that CAC-OS does not include a stacked structure of two or more types of films different in composition. For example, a structure including two layers of a film containing In as a main component and a film containing Ga as a main component is not included.

In some cases, a clear boundary can not be observed between the region in which GaO _X3 is the main component and the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component.

In addition, it is selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium instead of gallium. In the case where one or a plurality of types are contained, the CAC-OS may be a region observed in the form of nanoparticles mainly composed of the metal element, and a nano mainly composed of In as a main component. The area | region observed in particle form says the structure currently each disperse | distributed to mosaic form at random.

The CAC-OS can be formed by, for example, a sputtering method under conditions in which the substrate is not intentionally heated. In addition, in the case where the CAC-OS is formed by a sputtering method, one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas at the time of film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less .

CAC-OS has a feature that a clear peak is not observed when it is measured using a θ / 2θ scan by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be understood from X-ray diffraction that the orientation in the a-b plane direction and the c-axis direction of the measurement region is not seen.

Further, in an electron beam diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm, the CAC-OS has a ring-like high luminance region and a plurality of ring regions. A bright spot is observed. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and in the cross-sectional direction.

In addition, for example, in the case of CAC-OS in In-Ga-Zn oxide, GaO _X3 is a main component by EDX mapping acquired using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) It can be confirmed that the region and the region containing In _{X 2} Zn _{Y 2} O _{Z 2} or In O _{X 1} as the main component have a structure in which the regions are localized and mixed.

The CAC-OS has a structure different from the IGZO compound in which the metal element is uniformly distributed, and has different properties from the IGZO compound. That is, CAC-OS is phase-separated into a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component, and a region in which each element is a main component Has a mosaic-like structure.

Here, the region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 is a region whose conductivity is higher than the region whose main component is GaO _X3 or the like. That is, when carriers flow in a region mainly containing In _X2 Zn _Y2 O _Z2 or InO _X1 , conductivity as an oxide semiconductor is exhibited. Therefore, high field-effect mobility (μ) can be realized by cloud-like distribution in a region of the oxide semiconductor of a region containing In _{X 2} Zn _{Y 2} O _{Z 2} or InO _{X 1} as a main component.

On the other hand, the region in which GaO _X3 or the like is a main component is a region in which the insulating property is higher than the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component. That is, by distributing a region containing GaO _{X 3} or the like as a main component in the oxide semiconductor, leakage current can be suppressed and favorable switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _{X 2} Zn _{Y 2} O _{Z 2} or InO _{X 1} act complementarily to achieve high results. On current (I _on ) and high field effect mobility (μ) can be realized.

In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material of various semiconductor devices.

In the pixel 11 unit e, the signal written to the node NML can be read out to the node NRL by supplying an appropriate potential to the wiring 121L. The potential can be, for example, a potential corresponding to the threshold voltage of the transistor 116L. If an image signal is written to the node NAL before this operation, a signal potential obtained by adding the potential of the node NRL to the image signal is applied to the liquid crystal element 105L by capacitive coupling of the capacitor 103L.

That is, when a desired correction signal is stored in the node NML, the correction signal can be added to the supplied image signal. Since the correction signal may be attenuated by an element on the transmission path, it is preferable to generate the correction signal in consideration of the attenuation.

The above is the description of the configuration of the first pixel 17.

The second pixel 18 includes a transistor 101E, a transistor 102E, a transistor 106E, a transistor 107E, a transistor 108E, a transistor 115E, a transistor 116E, a capacitor 103E, a capacitor 109E, and a capacitor 117E. An EL element 110E is provided as a second display element.

One of the source and the drain of the transistor 101E is electrically connected to one electrode of the capacitor 103E. One electrode of the capacitor 103E is electrically connected to one of the source and the drain of the transistor 106E. The other of the source and the drain of the transistor 106E is electrically connected to one of the source and the drain of the transistor 107E. One of the source and the drain of the transistor 107E is electrically connected to one electrode of the capacitor 109E. One electrode of the capacitor 100E is electrically connected to the gate of the transistor 108E. One of the source and the drain of the transistor 108E is electrically connected to the other electrode of the capacitor 109E. The other electrode of the capacitor 109E is electrically connected to one electrode of the EL element 110E.

Here, a wiring to which one of the source and the drain of the transistor 101E, one of the electrodes of the capacitor 103E, and one of the source and the drain of the transistor 106E is connected is a node NAE. A wiring to which the other of the source and the drain of the transistor 106E, one of the electrodes of the capacitor 109E, one of the source and the drain of the transistor 107E, and the gate of the transistor 108E is connected is a node NBE. Further, a wiring to which the other electrode of the capacitor 103E, one of the source or the drain of the transistor 102E, and one of the source or the drain of the transistor 116E is connected is a node NRE. A wiring to which the gate of the transistor 116E, one of the source and the drain of the transistor 115E, and one electrode of the capacitor 117E are connected is a node NME.

The gate of the transistor 101E and the gate of the transistor 106E are electrically connected to the wiring 123E. The gate of the transistor 102E is electrically connected to the wiring 123E. The gate of the transistor 107E and the other electrode of the capacitor 117E are electrically connected to the wiring 121L. The gate of the transistor 115E is electrically connected to the wiring 122E. The other of the source and the drain of the transistor 115E is electrically connected to the wiring 124E.

The other of the source and the drain of the transistor 116E is electrically connected to the power supply line (high potential). The other of the source and the drain of the transistor 102E is electrically connected to the power supply line (low potential). The other of the source and the drain of the transistor 107E is electrically connected to the power supply line (low potential). The other electrode of the EL element 110E is electrically connected to the common wiring 129E. Note that an arbitrary potential can be supplied to the common wiring 129E.

The wirings 122E, 123E, and 126E can have a function as signal lines for controlling the operation of the transistors. The wiring 125E can have a function as a signal line for supplying an image signal. The wiring 121E and the wiring 124E can have a function as signal lines for operating the memory circuit MEME described below.

The transistor 115E, the transistor 116E, and the capacitor 117E form a memory circuit MEME. The node NME is a storage node, and the signal supplied to the wiring 124E can be written to the node NME by turning on the transistor 115E. By using a transistor with extremely low off-state current as the transistor 115E, the potential of the node NME can be held for a long time. For example, a transistor in which a metal oxide is used for a channel formation region (hereinafter referred to as an OS transistor) can be used as the transistor.

Note that the OS transistor may be applied not only to the transistor 115E but also to other transistors included in the pixel. Further, a transistor having Si in a channel formation region (hereinafter, a Si transistor) may be applied to the transistor 115E. Alternatively, both an OS transistor and a Si transistor may be used. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low temperature polysilicon), a transistor having single crystal silicon, and the like.

The operation of the pixel unit 11e will be described in detail using the timing chart shown in FIG. Although the operation in the first pixel 17 will be described below, the second pixel 18 can also operate in the same procedure. The first pixel 17 and the second pixel 18 may be operated simultaneously, or only one of them may be operated.

Further, at a desired timing, the correction signal (Vp) is supplied to the wiring 124L, and the image signal (Vs) is supplied to the wiring 125L. In the following description, the high potential is represented by "H" and the low potential is represented by "L".

When the potential of the wiring 121L is “L”, the potential of the wiring 122L is “H”, and the potential of the wiring 123L is “L” in the period T1, the transistor 115L is turned on and the correction signal (Vp) is written to the node NML. Note that the potential of the wiring 126L is inherited from the operation of the previous frame and is “H” in the period T1.

When the potential of the wiring 121L is “L”, the potential of the wiring 122L is “L”, the potential of the wiring 123L is “H”, and the potential of the wiring 126L is “L” in the period T2, the transistor 102L is turned on and the node NRL It is reset to "L". In addition, the transistor 101L is turned on, and the image signal (Vs) is written to the node NAL. Further, since the transistor 106L is turned off, the potential of the node NBL is maintained and display is continued.

Assuming that the potential of the wiring 121L is “H”, the potential of the wiring 122L is “L”, the potential of the wiring 123L is “L”, and the potential of the wiring 126L is “L” in period T3, the node NML is capacitively coupled by the capacitive element 117L. The potential of the wiring 121L is added to the potential of At this time, assuming that the potential of the wiring 121L is a threshold voltage (V _th ) of the transistor 116L, the potential of the node NML is Vp + _Vth . Then, the transistor 116L is turned on, and the node NRL becomes a potential lower than the gate potential of the transistor 116L by the threshold voltage (V _th ), that is, a potential corresponding to the correction signal (Vp).

Then, by capacitive coupling of the capacitive element 103L, a potential (Vp ') corresponding to the capacitance ratio between the node NRL and the node NAL is added to the image signal (Vs). That is, the potential of the node NAL is Vs + Vp ′. The transistor 107L is turned on to reset the potential of the node NBL to "L".

Assuming that the potential of the wiring 121L is “L”, the potential of the wiring 122L is “L”, the potential of the wiring 123L is “L”, and the potential of the wiring 126L is “H” in period T4, the potential of the node NAL is distributed to the node NBL The potential of the node NBL is (Vs + Vp ′) ′.

Thus, the potential derived from the correction signal can be added to the image signal, and the display can be corrected.

The configuration and operation of the pixel unit 11e are useful for up-converting an image. Up-conversion using the pixel unit 11 e will be described with reference to FIGS. 3 (A) and 3 (B).

For example, the number of pixels of the 8K4K display device is four times the number of pixels (3840 × 2160) of the 4K2K display device. That is, if an image signal to be displayed by one pixel of the 4K2K display device is to be simply displayed by the 8K4K display device, the same image signal is displayed by four pixels.

FIG. 3A is a diagram for explaining an image displayed on four pixel units in the horizontal and vertical directions assuming the above. One pixel unit has a first pixel on which the display of the image signal S1L is performed and a second pixel on which the display of the image signal S1E is performed. Although display may be performed in any one of the first pixel and the second pixel, the case in which display is performed in both will be described here.

As shown in FIG. 3A, all the four pixel units are displayed as the image signal S1L and the image signal S1E before the up conversion, but after the up conversion, the image signals S0L to S2L are applied to the respective pixel units. And the image signals S0E to S2E can be applied to improve the resolution.

FIG. 3B is a diagram for explaining the up conversion operation in the pixel unit 11 e. In the pixel unit 11e, the image signal is corrected in the direction of increasing the potential in order to correct the image signal by the method described above. Therefore, the original image signals S1L and S1E are processed by the external device into image signals S0L and S0E with small signal potentials, and are supplied to the pixel unit 11e. In addition, since the generation operation of the image signals S0L and S0E is simple, the load on the external device is small.

Further, W1L to W3L and W1E to W3E are supplied to the respective pixels as correction signals. Here, the method of generating W1L to W3L and W1E to W3E is not limited. The correction signal may be generated in real time using an external device, or the correction signal stored in the recording medium may be read and synchronized with the image signals S0L and S0E.

Then, by performing the operation of the pixel unit 11e described above, each correction signal is added to each image signal, and new image signals S0L to S2L and S0E to S2E are generated. Therefore, up-converted display can be performed.

In conventional upconversion by external correction, the load on the external device is large because a new image signal itself is generated. On the other hand, in one aspect of the present invention described above, the image signal supplied does not change significantly, and a new image signal is generated by the pixel to which the correction signal is supplied, so that the load on the external device can be reduced. In addition, an operation for generating a new image signal by a pixel can be performed in few steps, and a display device with a large number of pixels and a short horizontal period can also be supported.

Note that the first pixel 17 in which the liquid crystal element 105L is used as a display element may have a circuit configuration illustrated in FIG. The circuit configuration illustrated in FIG. 4A is a configuration in which the transistors 106L and 107L and the wiring 126L are omitted from the circuit configuration illustrated in FIG. In this structure, a wiring to which one of the source and the drain of the transistor 101L, one of the electrodes of the capacitor 103L, one of the electrodes of the capacitor 104L, and one of the electrodes of the liquid crystal element 105L are connected is a node NAL.

The operation of the first pixel 17 will be described in detail with reference to a timing chart shown in FIG. In this configuration, the correction signal is added after the original image signal is supplied to the liquid crystal element 105L. However, the operation speed of the liquid crystal element 105L is relatively slow, so the influence on the display is minor.

When the potential of the wiring 121L is “L”, the potential of the wiring 122L is “H”, and the potential of the wiring 123L is “L” in the period T1, the transistor 115L is turned on and the correction signal (Vp) is written to the node NM.

When the potential of the wiring 121L is “L”, the potential of the wiring 122L is “L”, and the potential of the wiring 123L is “H” in the period T2, the transistor 102L is turned on and the node NRL is reset to “L”. In addition, the transistor 101L is turned on, and the image signal (Vs) is written to the node NAL.

When the potential of the wiring 121L is “H”, the potential of the wiring 122L is “L”, and the potential of the wiring 123L is “L” in period T3, the potential of the wiring 121L is added to the potential of the node NML by capacitive coupling of the capacitive element 117L. Be done. At this time, assuming that the potential of the wiring 121L is a threshold voltage (V _th ) of the transistor 116L, the potential of the node NML is Vp + _Vth . Then, the transistor 116L is turned on, and the node NRL becomes a potential lower than the gate potential of the transistor 116L by the threshold voltage (V _th ), that is, a potential corresponding to the correction signal (Vp).

Then, by capacitive coupling of the capacitive element 103, a potential (Vp ′) corresponding to the capacitance ratio between the node NRL and the node NAL is added to the image signal (Vs). That is, the potential of the node NAL is Vs + Vp ′.

Thus, the potential derived from the correction signal can be added to the image signal, and the display can be corrected.

Although FIG. 1 shows a configuration in which a memory circuit is connected to each display element in a pixel, a configuration in which a memory circuit is connected to only one of the display elements may be employed.

For example, as illustrated in FIG. 5, a memory circuit may be provided only in the first pixel 17 in which the liquid crystal element 105L is used as a display element. In this case, up-conversion can be performed only for the first pixel 17. Alternatively, as shown in FIG. 6, a memory circuit may be provided only in the second pixel 18 using the EL element 110E as a display element. In this case, up-conversion can be performed only for the second pixel 18.

Further, as shown in FIG. 7, a part of signal lines may be shared by the first pixel 17 and the second pixel 18. Since only one of the first pixel 17 and the second pixel 18 may be operated for display, it is preferable that the signal line for controlling the supply of the image signal is not shared. On the other hand, signal lines for controlling the supply of correction signals can be shared because they do not directly relate to the display operation. Therefore, as shown in FIG. 7, the gate of the transistor 115L and the gate of the transistor 115E may be connected to the wiring 122LE, and the other electrode of the capacitor 117L and the other electrode of the capacitor 117E may be connected to the wiring 121LE.

FIG. 8 is an example of a block diagram of a display device of one embodiment of the present invention. The display device includes a pixel array in which pixel units 11 e are provided in a matrix, row drivers 21 and 22, column drivers 23 and 24, and a circuit 25. The row driver 21 and the column driver 23 are peripheral circuits for driving the first pixel 17 having the liquid crystal element 105L. The row driver 22 and the column driver 24 are peripheral circuits for driving the second pixel 18 having the EL element 110E.

For example, shift register circuits can be used as the row drivers 21 and 22 and the column drivers 23 and 24. The circuit 25 has a function of generating an image signal and a correction signal. The circuit 25 can also be referred to as an external device for generating the correction signal described above.

For example, the image signals S1L and S1E in the description of FIGS. 3A and 3B are input to the circuit 25, and the image signals S0L and S0E and the correction signals W1L to W3L and W1E to W3E are generated, and the column driver 23 is generated. , 24 output. Different circuits may have the function of generating the image signals S0L and S0E and the function of generating the correction signals W1L to W3L and W1E to W3E.

The circuit 25 may also have a neural network. For example, the correction signal W with high accuracy can be generated by using a deep neural network in which a large number of images are learned as teacher data.

Up to this point, the upconversion operation in a pixel having a memory circuit has been mainly described. However, in the pixel, an operation of correcting variation in characteristics of transistors can also be performed. In a pixel using an EL element, variation in threshold voltage of a drive transistor for supplying current to the EL element has a great influence on display quality. Display quality can be improved by holding a signal for correcting the threshold voltage of the drive transistor in the memory circuit MEME and adding the signal to the image signal.

FIG. 9A is a diagram showing a configuration of the second pixel 18 capable of performing an operation of correcting the threshold voltage (V _th ) of the transistor 108E corresponding to the drive transistor. In FIG. 9A, the transistor 111E and the wiring 130E are added to the second pixel 18 illustrated in FIG. Note that the above-described up-conversion operation may be performed using the pixel circuit having the above configuration. Also, both threshold voltage correction and up conversion may be performed.

One of the source and the drain of the transistor 111E is electrically connected to one of the source and the drain of the transistor 108E. The other of the source and the drain of the transistor 111E is electrically connected to the wiring 130E. The gate of the transistor 111E is electrically connected to the wiring 123E.

The wiring 130E functions as a monitor line for obtaining the electrical characteristics of the transistor 108E with an external device. In addition, the writing of the image signal can be stabilized by supplying a specific potential to the one electrode of the capacitor 109E from the wiring 130E through the transistor 111E.

In this configuration, an external correction operation is performed as an initial operation, but the generated correction signal is stored in the memory circuit MEME. Therefore, after the correction signal is held in the memory circuit MEME, it operates like an internal correction.

When threshold voltage correction is performed using the above circuit, the configuration of the block diagram shown in FIG. 9B can be used. In FIG. 9B, a column driver 26 and a circuit 27 are added to the configuration shown in FIG. The column driver 26 is electrically connected to the wiring 130E, and the output value thereof can be input to the circuit 27.

First, the transistors 101E and 106E are turned on, and the standard potential at which the transistor 108E is turned on is written to the node NB. The current output from the transistor 108E is taken into the circuit 27 via the transistor 111E. The operation is performed on all the pixels, and a current value output from the transistor 112 when a standard potential is applied to the gate is obtained.

The circuit 27 reads and analyzes the current value, and generates a correction signal W _Vth stored in each pixel with reference to the transistor with the highest current value. The correction signal W _Vth is input to the circuit 25 and added to another correction signal generated by the circuit 25. For example, the circuit 25 outputs W1E 'to W3E' including the correction signal of the threshold voltage to the column driver 24, and is stored in the memory circuit MEME of each pixel. Note that the circuit 27 has a function of reading a current value, and the other circuit may have a function of generating the correction signal W _Vth .

After that, the display operation in which the correction signal is added to the image signal is performed as in the up conversion operation. Although the threshold voltage of the transistor may largely fluctuate over a long period, the fluctuation in a short period is extremely small. Therefore, when only the threshold voltage correction operation is performed, the generation of the correction signal and the storage operation to the memory circuit MEM do not need to be performed for each frame or the like, and may be performed at the time of power on or end. Alternatively, the operation time of the display device may be recorded, and the operation may be performed at regular intervals of day, week, month, year, and the like.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

Second Embodiment
In this embodiment, the display device of one embodiment of the present invention and a driving method of the display device will be described.

The display device of one embodiment of the present invention is a hybrid display. A hybrid display can provide a hybrid display.

The hybrid display is a method of displaying characters or an image by complementing each other with color tone or light intensity by using reflected light and self-emission together in one panel. Alternatively, the hybrid display is a method of displaying characters and / or images by using respective lights from a plurality of display elements in the same pixel or the same sub-pixel. However, when a hybrid display performing hybrid display is viewed locally, it is displayed using a pixel or a sub-pixel displayed using any one of a plurality of display elements and two or more of a plurality of display elements And may have pixels or sub-pixels.

In the present specification and the like, a device that satisfies any one or more of the above configurations is referred to as a hybrid display.

In addition, the hybrid display has a plurality of display elements in the same pixel or the same sub-pixel. In addition, as a some display element, the reflection type element which reflects light, and the self-light-emitting element which inject | emits light are mentioned, for example. Note that the reflective element and the self light emitting element can be controlled independently. The hybrid display has a function of displaying characters and / or images in the display unit using reflected light and / or self-emission.

The display device of one embodiment of the present invention can include a pixel provided with a first display element which reflects visible light. Alternatively, it can include a pixel provided with a second display element which emits visible light. Alternatively, it can have a pixel provided with a first display element and a second display element.

In this embodiment mode, a display device including a first display element which reflects visible light and a second display element which emits visible light will be described.

The display device has a function of displaying an image by one or both of the first light reflected by the first display element and the second light emitted by the second display element. Alternatively, the display device has a function of expressing gradation by controlling the light amount of the first light reflected by the first display element and the light amount of the second light emitted by the second display element. Have.

In addition, the display device controls the gray level by controlling the amount of light emitted from the second pixel and the first pixel that expresses the gray level by controlling the amount of light reflected by the first display element. It is preferable to have a configuration having a second pixel to be expressed. For example, a plurality of first pixels and second pixels are arranged in a matrix, respectively, to constitute a display portion.

In addition, it is preferable that the first pixel and the second pixel be arranged in the display area with the same number and the same pitch. At this time, the adjacent first and second pixels can be collectively referred to as a pixel unit. Thus, as described later, both an image displayed with only a plurality of first pixels, an image displayed with only a plurality of second pixels, and both a plurality of first pixels and a plurality of second pixels Each of the images displayed in can be displayed in the same display area.

For the first display element included in the first pixel, an element which reflects ambient light to be displayed can be used. Such an element does not have a light source, which makes it possible to extremely reduce the power consumption at the time of display.

A reflective liquid crystal element can be typically used for the first display element. Alternatively, as a first display element, a shutter type MEMS (Micro Electro Mechanical System) element, an optical interference type MEMS element, a microcapsule type, an electrophoresis type, an electrowetting type, an electronic powder fluid (registered trademark) An element or the like to which a method or the like is applied can be used.

The second display element included in the second pixel includes a light source, and an element which performs display using light from the light source can be used. In particular, it is preferable to use an electroluminescent element which can extract light emission from a light-emitting substance by applying an electric field. The light emitted from such a pixel has high color reproducibility (wide color gamut) and high contrast, that is, vivid display since the luminance and chromaticity thereof are not influenced by external light. be able to.

For the second display element, for example, a self-luminous light emitting element such as an organic light emitting diode (OLED), a light emitting diode (LED), a quantum-dot light emitting diode (QLED), or a semiconductor laser can be used. Alternatively, as a display element included in the second pixel, a combination of a backlight which is a light source and a transmissive liquid crystal element which controls the light amount of the transmitted light of the light from the backlight may be used.

The first pixel may be configured to have, for example, a sub-pixel exhibiting white (W), or a sub-pixel presenting three-color light of, for example, red (R), green (G) and blue (B). . Similarly, the second pixel also has a sub-pixel that exhibits white (W), for example, or a sub-pixel that exhibits light of three colors, for example, red (R), green (G), and blue (B). can do. Note that the subpixels of the first pixel and the second pixel may have four or more colors. As the number of types of sub-pixels is increased, power consumption can be reduced and color reproducibility can be improved.

One embodiment of the present invention displays a first mode in which an image is displayed by a first pixel, a second mode in which an image is displayed by a second pixel, and an image in first and second pixels. The third mode can be switched. Further, as described in Embodiment 1, different image signals can be input to each of the first pixel and the second pixel to display a composite image.

The first mode is a mode in which an image is displayed using light reflected by the first display element. The first mode is an extremely low power consumption drive mode because no light source is required. For example, it is effective when the illuminance of outside light is sufficiently high and the outside light is white light or light in the vicinity thereof. The first mode is a display mode suitable for displaying, for example, character information such as a book or a document. In addition, since the reflected light is used, the display can be gentle on the eyes, and the eyes are less tired.

The second mode is a mode in which an image is displayed using light emission by the second display element. Therefore, an extremely vivid display (high contrast and high color reproducibility) can be performed regardless of the illuminance and the chromaticity of the external light. For example, it is effective when the illuminance of external light is extremely low, such as at night or in a dark room. When the ambient light is dark, the user may feel dazzling if a bright display is performed. In order to prevent this, it is preferable to perform display with reduced luminance in the second mode. Moreover, in addition to suppressing glare, power consumption can also be reduced. The second mode is a mode suitable for displaying a bright image, a smooth moving image, and the like.

The third mode is a mode in which display is performed using both the reflected light by the first display element and light emission by the second display element. Specifically, driving is performed so as to express one color by mixing the light exhibited by the first pixel and the light exhibited by the second pixel adjacent to the first pixel. It is possible to reduce power consumption more than the second mode while displaying brighter than the first mode. For example, it is effective in the case where the illuminance of outside light is relatively low, such as under indoor lighting, or in the morning or the evening, or when the chromaticity of the outside light is not white.

Hereinafter, more specific examples of one embodiment of the present invention will be described with reference to the drawings.

[Configuration Example of Display Device]

FIG. 10 is a diagram illustrating the pixel array 40 included in the display device of one embodiment of the present invention. The pixel array 40 has a plurality of pixel units 45 arranged in a matrix. The pixel unit 45 includes a pixel 46 and a pixel 47.

FIG. 10 shows an example in which the pixel 46 and the pixel 47 have display elements corresponding to three colors of red (R), green (G), and blue (B), respectively.

The pixel 46 includes a display element 46R corresponding to red (R), a display element 46G corresponding to green (G), and a display element 46B corresponding to blue (B). Each of the display elements 46R, 46G, and 46B is a second display element using light of a light source.

The pixel 47 includes a display element 47R corresponding to red (R), a display element 47G corresponding to green (G), and a display element 47B corresponding to blue (B). Each of the display elements 47R, 47G, and 47B is a first display element using reflection of external light.

The above is the description of the configuration example of the display device.

[Configuration example of pixel unit]
Subsequently, the pixel unit 45 will be described using FIGS. 11 (A), (B), and (C). FIGS. 11A, 11 B, and 11 C are schematic views showing an example of the configuration of the pixel unit 45.

The pixel 46 includes a display element 46R, a display element 46G, and a display element 46B. The display element 46R has a light source, and emits red light R2 of luminance according to the gradation value corresponding to red contained in the second gradation value input to the pixel 46 to the display surface side. Similarly, the display element 46G and the display element 46B respectively emit green light G2 or blue light B2 to the display surface side.

The pixel 47 includes a display element 47R, a display element 47G, and a display element 47B. The display element 47R reflects external light, and emits red light R1 of luminance according to the gradation value corresponding to red contained in the first gradation value input to the pixel 47 to the display surface side . Similarly, the display element 47G and the display element 47B respectively emit green light G1 or blue light B1 to the display surface side.

[First mode]
FIG. 11A illustrates an example of an operation mode in which an image is displayed by driving the display element 47R that reflects external light, the display element 47G, and the display element 47B. As shown in FIG. 11A, the pixel unit 45 does not drive the pixel 46, for example, when the illuminance of the external light is sufficiently high, and the light from the pixel 47 (light R1, light G1, and light By mixing only B1), light 55 of a predetermined color can also be emitted to the display surface side. Thus, driving with extremely low power consumption can be performed.

[Second mode]
FIG. 11B illustrates an example of an operation mode in which an image is displayed by driving the display element 46R, the display element 46G, and the display element 46B. As shown in FIG. 11B, the pixel unit 45 does not drive the pixel 47, for example, when the illuminance of external light is extremely low, and so on, the light from the pixel 46 (light R2, light G2, and light B2 The light 55 of a predetermined color can also be emitted to the display surface side by mixing only the colors. This makes it possible to display vividly. In addition, by reducing the luminance when the illuminance of external light is low, it is possible to suppress glare that the user feels and to reduce power consumption.

[Third mode]
FIG. 11C shows an operation of displaying an image by driving both the display element 47R that reflects external light, the display element 47G, the display element 47B, the display element 46R that emits light, the display element 46G, and the display element 46B. An example of the mode is shown. As shown in FIG. 11C, the pixel unit 45 mixes six colors of light R1, light G1, light B1, light R2, light G2 and light B2 to form light 55 of a predetermined color. It can be ejected on the display surface side.

The above is the description of the configuration example of the pixel unit 45.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

Third Embodiment
Hereinafter, an example of a display panel which is one embodiment of the present invention will be described. The display panel exemplified below is a display panel that has both a reflective liquid crystal element and an EL element and can perform display in both transmissive mode and reflective mode.

[Example of pixel configuration]
FIG. 12A illustrates a configuration example of the conductive layer 311 b included in the pixel 410. The conductive layer 311 b functions as a reflective electrode of the liquid crystal element in the pixel 410. Further, an opening 451 is provided in the conductive layer 311 b.

In FIG. 12A, an EL element 360 located in a region overlapping with the conductive layer 311 b is indicated by a broken line. The EL element 360 is disposed so as to overlap with the opening 451 included in the conductive layer 311 b. Thus, the light emitted from the EL element 360 is emitted to the display surface side through the opening 451.

In FIG. 12A, the pixel 410 adjacent in the direction R is a pixel corresponding to a different color. At this time, as shown in FIG. 12A, in two pixels adjacent in the direction R, the openings 451 are preferably provided at different positions of the conductive layer 311 b so as not to be arranged in a line. Accordingly, the two EL elements 360 can be separated, and a phenomenon (also referred to as crosstalk) in which light emitted from the EL elements 360 is incident on the colored layer of the adjacent pixel 410 can be suppressed. In addition, since two adjacent EL elements 360 can be arranged separately, a display device with high definition can be realized even when the EL layer of the EL element 360 is separately formed using a shadow mask or the like.

Alternatively, the arrangement may be as shown in FIG.

If the ratio of the total area of the openings 451 to the total area of the non-openings is too large, the display using the liquid crystal element will be dark. If the ratio of the total area of the openings 451 to the total area of the non-openings is too small, the display using the EL element 360 will be dark.

In addition, when the area of the opening 451 provided in the conductive layer 311 b functioning as a reflective electrode is too small, the efficiency of light which can be extracted from the light emitted from the EL element 360 is reduced.

The shape of the opening 451 may be, for example, a polygon, a square, an oval, a circle, a cross, or the like. In addition, it may be in the shape of an elongated streak, a slit, or a checkered pattern. Alternatively, the openings 451 may be arranged close to adjacent pixels. Preferably, the openings 451 are arranged close to other pixels displaying the same color. This can suppress crosstalk.

[Display panel configuration example]
FIG. 13 is a schematic perspective view of a display panel 300 according to one embodiment of the present invention. The display panel 300 has a configuration in which a substrate 351 and a substrate 361 are bonded to each other. In FIG. 13, the substrate 361 is clearly indicated by a broken line.

The display panel 300 includes a display portion 362, a circuit 364, a wiring 365, and the like. The substrate 351 is provided with, for example, a circuit 364, a wiring 365, a conductive layer 311 b functioning as a pixel electrode, and the like. Further, FIG. 13 shows an example in which the IC 373 and the FPC 372 are mounted on the substrate 351. Therefore, the structure illustrated in FIG. 13 can also be referred to as a display module including the display panel 300, the FPC 372, and the IC 373.

The circuit 364 can use, for example, a circuit functioning as a scan line driver circuit (row driver).

The wiring 365 has a function of supplying a signal or power to the display portion or the circuit 364. The signal and the power are input to the wiring 365 from the outside or the IC 373 through the FPC 372.

Further, FIG. 13 illustrates an example in which the IC 373 is provided on the substrate 351 by a COG (Chip On Glass) method or the like. As the IC 373, for example, an IC having a function as a scan line driver circuit or a signal line driver circuit can be applied. Note that in the case where the display panel 300 includes a circuit functioning as a scan line driver circuit and a signal line driver circuit (column driver), a circuit functioning as a scan line driver circuit or a signal line driver circuit is provided outside, and display is performed through the FPC 372 In the case where a signal for driving the panel 300 is input or the like, the IC 373 may not be provided. Alternatively, the IC 373 may be mounted on the FPC 372 by a COF (Chip On Film) method or the like.

FIG. 13 shows an enlarged view of a part of the display unit 362. In the display portion 362, conductive layers 311b included in a plurality of display elements are arranged in matrix. The conductive layer 311 b has a function of reflecting visible light, and functions as a reflective electrode of a liquid crystal element 340 described later.

Further, as shown in FIG. 13, the conductive layer 311 b has an opening. Further, an EL element 360 is provided closer to the substrate 351 than the conductive layer 311 b. Light from the EL element 360 is emitted to the substrate 361 side through the opening of the conductive layer 311 b.

In addition, an input device 366 can be provided over the substrate 361. For example, a sheet-like capacitive touch sensor may be provided over the display portion 362. Alternatively, a touch sensor may be provided between the substrate 361 and the substrate 351. In the case where a touch sensor is provided between the substrate 361 and the substrate 351, an optical touch sensor using a photoelectric conversion element may be applied in addition to a capacitive touch sensor.

[Example of section configuration]
14 is a cross section of the display panel illustrated in FIG. 13 when part of the region including the FPC 372, part of the region including the circuit 364, part of the region including the display portion 362, and the input device 366 are cut. An example is shown.

The display panel includes an insulating layer 220 between the substrate 351 and the substrate 361. Further, an EL element 360, a transistor 201, a transistor 205, a transistor 206, a coloring layer 134, and the like are provided between the substrate 351 and the insulating layer 220. In addition, a liquid crystal element 340, a coloring layer 131, and the like are provided between the insulating layer 220 and the substrate 361. The substrate 361 and the insulating layer 220 are bonded to each other through the adhesive layer 141, and the substrate 351 and the insulating layer 220 are bonded to each other through the adhesive layer 142.

The transistor 206 is electrically connected to the liquid crystal element 340, and the transistor 205 is electrically connected to the EL element 360. Since both the transistor 205 and the transistor 206 are formed on the surface of the insulating layer 220 on the substrate 351 side, these can be manufactured using the same process.

The substrate 361 is provided with a coloring layer 131, a light shielding layer 132, an insulating layer 121, a conductive layer 313 functioning as a common electrode of the liquid crystal element 340, an alignment film 133b, an insulating layer 117, and the like. The insulating layer 117 functions as a spacer for holding the cell gap of the liquid crystal element 340.

On the substrate 351 side of the insulating layer 220, insulating layers such as the insulating layer 211, the insulating layer 212, the insulating layer 213, the insulating layer 214, the insulating layer 215, and the like are provided. A part of the insulating layer 211 functions as a gate insulating layer of each transistor. The insulating layer 212, the insulating layer 213, and the insulating layer 214 are provided to cover the transistors. In addition, an insulating layer 215 is provided to cover the insulating layer 214. The insulating layer 214 and the insulating layer 215 have a function as a planarization layer. Note that although the case where three layers of the insulating layer 212, the insulating layer 213, and the insulating layer 214 are provided as an insulating layer covering a transistor and the like is shown here, the present invention is not limited to this. It may be a layer or two layers. Further, the insulating layer 214 which functions as a planarization layer may not be provided if unnecessary.

The transistor 201, the transistor 205, and the transistor 206 each have a conductive layer 221 whose portion functions as a gate, a conductive layer 222 whose portion functions as a source or drain, and a semiconductor layer 231. Here, the same hatching pattern is given to a plurality of layers obtained by processing the same conductive film.

The liquid crystal element 340 is a reflective liquid crystal element. The liquid crystal element 340 has a stacked structure in which the conductive layer 311 a, the liquid crystal 312, and the conductive layer 313 are stacked. In addition, a conductive layer 311 b that reflects visible light is provided in contact with the substrate 351 side of the conductive layer 311 a. The conductive layer 311 b has an opening 251. The conductive layer 311 a and the conductive layer 313 each include a material which transmits visible light. Further, an alignment film 133 a is provided between the liquid crystal 312 and the conductive layer 311 a, and an alignment film 133 b is provided between the liquid crystal 312 and the conductive layer 313. In addition, on the outer surface of the substrate 361, a polarizing plate 130 is provided.

In the liquid crystal element 340, the conductive layer 311b has a function of reflecting visible light, and the conductive layer 313 has a function of transmitting visible light. The light incident from the substrate 361 side is polarized by the polarizing plate 130, passes through the conductive layer 313 and the liquid crystal 312, and is reflected by the conductive layer 311 b. Then, the light passes through the liquid crystal 312 and the conductive layer 313 again, and reaches the polarizing plate 130. At this time, alignment of liquid crystal can be controlled by a voltage applied between the conductive layer 311 b and the conductive layer 313, and optical modulation of light can be controlled. That is, the intensity of light emitted through the polarizing plate 130 can be controlled. Further, light is absorbed by the colored layer 131 by light outside the specific wavelength range, and thus the light to be extracted becomes light exhibiting, for example, red.

The EL element 360 is a bottom emission light emitting element. The EL element 360 has a stacked structure in which a conductive layer 191, an EL layer 192, and a conductive layer 193b are stacked in this order from the insulating layer 220 side. A conductive layer 193a is provided to cover the conductive layer 193b. The conductive layer 193 b includes a material that reflects visible light, and the conductive layer 191 and the conductive layer 193 a include a material that transmits visible light. Light emitted from the EL element 360 is emitted to the substrate 361 side through the coloring layer 134, the insulating layer 220, the opening 251, the conductive layer 313, and the like.

Here, as shown in FIG. 14, the opening 251 is preferably provided with a conductive layer 311 a that transmits visible light. Accordingly, the liquid crystal 312 is also oriented in the area overlapping with the opening 251 in the same manner as in the other areas, so that the alignment failure of the liquid crystal occurs at the boundary between these areas, and unintended light leakage can be suppressed.

The light diffusing plate 129 and the polarizing plate 130 are disposed on the outer surface of the substrate 361. A linear polarizer may be used as the polarizer 130, but a circular polarizer may also be used. As a circularly-polarizing plate, what laminated | stacked the linear-polarizing plate and the 1/4 wavelength phase difference plate can be used, for example. Thereby, external light reflection can be suppressed. In addition, a light diffusion plate may be provided to suppress external light reflection. In addition, a desired contrast may be realized by adjusting a cell gap, an alignment, a driving voltage, and the like of a liquid crystal element used for the liquid crystal element 340 in accordance with the type of polarizing plate.

An insulating layer 217 is provided over the insulating layer 216 covering the end portion of the conductive layer 191. The insulating layer 217 has a function as a spacer which prevents the insulating layer 220 and the substrate 351 from approaching each other more than necessary. In the case where the EL layer 192 and the conductive layer 193a are formed using a shielding mask (a metal mask), the EL layer 192 and the conductive layer 193a may have a function for suppressing the contact of the shielding mask with the formation surface. Note that the insulating layer 217 may not be provided if it is unnecessary.

One of the source and the drain of the transistor 205 is electrically connected to the conductive layer 191 of the EL element 360 through the conductive layer 224.

One of the source and the drain of the transistor 206 is electrically connected to the conductive layer 311 b through the connection portion 207. The conductive layer 311 b and the conductive layer 311 a are provided in contact with each other, and these are electrically connected. Here, the connection portion 207 is a portion that connects conductive layers provided on both surfaces of the insulating layer 220 through an opening provided in the insulating layer 220.

A connection portion 204 is provided in a region where the substrate 351 and the substrate 361 do not overlap. The connection portion 204 is electrically connected to the FPC 372 through the connection layer 242. The connection unit 204 has the same configuration as the connection unit 207. The conductive layer obtained by processing the same conductive film as the conductive layer 311 a is exposed on the top surface of the connection portion 204. Thus, the connection portion 204 and the FPC 372 can be electrically connected to each other through the connection layer 242.

A connection portion 252 is provided in a partial region where the adhesive layer 141 is provided. In the connection portion 252, a conductive layer obtained by processing the same conductive film as the conductive layer 311 a and a part of the conductive layer 313 are electrically connected by the connection body 243. Therefore, a signal or potential input from the FPC 372 connected to the substrate 351 can be supplied to the conductive layer 313 formed on the substrate 361 through the connection portion 252.

For example, conductive particles can be used as the connection body 243. As the conductive particles, those in which the surface of particles of organic resin or silica is coated with a metal material can be used. It is preferable to use nickel or gold as the metal material because contact resistance can be reduced. In addition, it is preferable to use particles in which two or more types of metal materials are coated in layers, such as further coating nickel with gold. Further, as the connection body 243, it is preferable to use a material which is elastically or plastically deformed. At this time, as shown in FIG. 14, the connection body 243 which is conductive particles may have a shape which is crushed in the vertical direction. By doing this, the contact area between the connection member 243 and the conductive layer electrically connected to the connection member 243 can be increased, the contact resistance can be reduced, and the occurrence of problems such as connection failure can be suppressed.

The connector 243 is preferably disposed so as to be covered by the adhesive layer 141. For example, the connector 243 may be dispersed in the adhesive layer 141 before curing.

Further, the input device 366 provided on the first surface of the substrate 560 is bonded to the polarizing plate 130 via the adhesive layer 141.

FIG. 14 illustrates an example in which the transistor 201 is provided as an example of the circuit 364.

In FIG. 14, as an example of the transistor 201 and the transistor 205, a structure in which a semiconductor layer 231 in which a channel is formed is sandwiched between two gates is applied. One gate is formed of a conductive layer 221, and the other gate is formed of a conductive layer 223 overlapping the semiconductor layer 231 with the insulating layer 212 interposed therebetween. With such a structure, the threshold voltage of the transistor can be controlled. At this time, the transistor may be driven by connecting two gates and supplying the same signal thereto. Such a transistor can increase field-effect mobility as compared to other transistors, and can increase on current. As a result, a circuit capable of high speed driving can be manufactured. Furthermore, the area occupied by the circuit portion can be reduced. By applying a transistor having a large on current, signal delay in each wiring can be reduced even if the number of wirings increases when the display panel is enlarged or the resolution is increased, and display unevenness is suppressed. can do.

Note that the transistor included in the circuit 364 and the transistor included in the display portion 362 may have the same structure. Further, the plurality of transistors included in the circuit 364 may have the same structure or may be combined with transistors having different structures. In addition, the plurality of transistors included in the display portion 362 may have the same structure, or transistors with different structures may be used in combination.

For at least one of the insulating layer 212 and the insulating layer 213 covering the transistors, a material in which an impurity such as water or hydrogen does not easily diffuse is preferably used. That is, the insulating layer 212 or the insulating layer 213 can function as a barrier film. With such a structure, diffusion of impurities from the outside to the transistor can be effectively suppressed, and a highly reliable display panel can be realized.

An insulating layer 121 is provided on the substrate 361 side so as to cover the colored layer 131 and the light shielding layer 132. The insulating layer 121 may have a function as a planarization layer. Since the surface of the conductive layer 313 can be roughly planarized by the insulating layer 121, the alignment state of the liquid crystal 312 can be uniform.

[About each component]
Below, each component shown above is demonstrated.

〔substrate〕
For the substrate of the display panel, a material having a flat surface can be used. For a substrate from which light from the display element is extracted, a material that transmits the light is used. For example, materials such as glass, quartz, ceramic, sapphire, and organic resin can be used.

By using a thin substrate, weight and thickness of the display panel can be reduced. Furthermore, a flexible display panel can be realized by using a flexible substrate having a thickness.

In addition, since the substrate on the side from which light is not emitted does not have to be light-transmitting, a metal substrate or the like can be used in addition to the substrates listed above. A metal substrate has high thermal conductivity and can easily conduct heat to the entire substrate, which can suppress local temperature increase of the display panel, which is preferable. In order to obtain flexibility and bendability, the thickness of the metal substrate is preferably 10 μm or more and 200 μm or less, and more preferably 20 μm or more and 50 μm or less.

The material constituting the metal substrate is not particularly limited, but for example, metals such as aluminum, copper and nickel, or alloys such as aluminum alloys or stainless steel can be suitably used.

Alternatively, a substrate that has been subjected to an insulating process by oxidizing the surface of the metal substrate or forming an insulating film on the surface may be used. For example, the insulating film may be formed using a coating method such as spin coating or dipping, an electrodeposition method, a vapor deposition method, a sputtering method, or the like. An oxide film may be formed on the surface of the substrate by means of, for example.

Examples of materials having flexibility and transparency to visible light include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyether sulfone (PES) resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamide imide resin, polyvinyl chloride resin, polytetrafluoroethylene (PTFE) resin, and the like. In particular, it is preferable to use a material having a low thermal expansion coefficient, and for example, a polyamideimide resin, a polyimide resin, PET, or the like having a thermal expansion coefficient of 30 × 10 ⁻⁶ / K or less can be suitably used. Alternatively, a substrate in which glass fiber is impregnated with an organic resin, or a substrate in which an inorganic filler is mixed with an organic resin to reduce the thermal expansion coefficient can be used. A substrate using such a material is light in weight, so that a display panel using the substrate can also be lightweight.

When a fibrous body is contained in the above material, the fibrous body is a high strength fiber of an organic compound or an inorganic compound. The high-strength fiber specifically refers to a fiber having a high tensile modulus or Young's modulus, and representative examples include polyvinyl alcohol fibers, polyester fibers, polyamide fibers, polyethylene fibers, aramid fibers, Polyparaphenylene benzobisoxazole fibers, glass fibers, or carbon fibers can be mentioned. As glass fiber, glass fiber using E glass, S glass, D glass, Q glass etc. is mentioned. These may be used in the form of a woven or non-woven fabric, and a structure obtained by impregnating the fiber body with a resin and curing the resin may be used as a flexible substrate. It is preferable to use a structure composed of a fiber body and a resin as the flexible substrate because the reliability against breakage due to bending or local pressure is improved.

Alternatively, glass, metal, or the like which is thin enough to have flexibility can be used for the substrate. Alternatively, a composite material in which glass and a resin material are bonded by an adhesive layer may be used.

A flexible substrate, a hard coat layer (eg, silicon nitride, aluminum oxide, etc.) that protects the surface of the display panel from scratches, a layer of a material that can disperse pressure (eg, aramid resin, etc.), etc. It may be laminated. Further, in order to suppress a decrease in the lifetime of the display element due to moisture or the like, an insulating film with low water permeability may be stacked over a flexible substrate. For example, an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, or aluminum nitride can be used.

The substrate can also be used by stacking a plurality of layers. In particular, when the glass layer is provided, the barrier property against water and oxygen can be improved, and a display panel with high reliability can be obtained.

[Transistor]
The transistor includes a conductive layer functioning as a gate electrode, a semiconductor layer, a conductive layer functioning as a source electrode, a conductive layer functioning as a drain electrode, and an insulating layer functioning as a gate insulating layer. The above shows the case where a bottom gate transistor is applied.

Note that the structure of the transistor included in the display device of one embodiment of the present invention is not particularly limited. For example, a planar transistor, a staggered transistor, or an inverted staggered transistor may be used. In addition, any top gate type or bottom gate type transistor structure may be employed. Alternatively, gate electrodes may be provided above and below the channel.

The crystallinity of the semiconductor material used for the transistor is not particularly limited either, and any of an amorphous semiconductor and a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having a crystalline region in part) May be used. The use of a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

As a semiconductor material used for the transistor, a metal oxide with an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium or the like can be used, for example, the above-described CAAC-OS, CAC-OS, or the like can be used.

[Conductive layer]
Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, and the like can be used for conductive layers of the wirings, electrodes, and the like in the display device, in addition to the gate, the source, and the drain of the transistor. Examples thereof include metals such as tantalum and tungsten, and alloys containing this as a main component. In addition, a film containing these materials can be used as a single layer or as a stacked structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked on a titanium film, a two-layer structure in which an aluminum film is stacked on a tungsten film, a copper film on a copper-magnesium-aluminum alloy film Two-layer structure to be laminated, two-layer structure in which a copper film is laminated on a titanium film, two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film And a three-layer structure in which a titanium film or a titanium nitride film is formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film stacked thereon, and further a molybdenum film or There is a three-layer structure or the like for forming a molybdenum nitride film. Note that an oxide such as indium oxide, tin oxide or zinc oxide may be used. Further, it is preferable to use copper containing manganese because controllability of the shape by etching is enhanced.

Further, as the light-transmitting conductive material, conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, or graphene can be used. Alternatively, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material can be used. Alternatively, a nitride of the metal material (eg, titanium nitride) or the like may be used. Note that in the case of using a metal material or an alloy material (or a nitride thereof), it may be thin enough to have translucency. In addition, a stacked film of the above materials can be used as the conductive layer. For example, the use of a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because the conductivity can be increased. These can also be used for conductive layers such as various wirings and electrodes included in a display device, and conductive layers (conductive layers functioning as pixel electrodes and common electrodes) included in a display element.

[Insulating layer]
As an insulating material which can be used for each insulating layer, for example, resin such as acrylic resin and epoxy resin, resin having a siloxane bond, inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride and aluminum oxide Materials can also be used.

In addition, the light emitting element is preferably provided between the pair of low water permeability insulating films. Thereby, it can suppress that impurities, such as water, penetrate | invade into a light emitting element, and can suppress decline in the reliability of an apparatus.

As the insulating film having low water permeability, a film containing nitrogen and silicon such as a silicon nitride film or a silicon nitride oxide film, a film containing nitrogen and aluminum such as an aluminum nitride film, and the like can be given. Alternatively, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.

For example, the water vapor transmission rate of a low permeability insulating film is 1 × 10 ⁻⁵ [g / (m ² · day)] or less, preferably 1 × 10 ⁻⁶ [g / (m ² · day)] or less, It is more preferably 1 × 10 ⁻⁷ [g / (m ² · day)] or less, still more preferably 1 × 10 ⁻⁸ [g / (m ² · day)] or less.

[Liquid crystal element]
As the liquid crystal element, for example, a liquid crystal element to which a vertical alignment (VA: Vertical Alignment) mode is applied can be used. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Pattered Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

Further, liquid crystal elements to which various modes are applied can be used as the liquid crystal element. For example, in addition to VA mode, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetrically Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode A liquid crystal element to which an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, or the like is applied can be used.

A liquid crystal element is an element that controls transmission or non-transmission of light by an optical modulation action of liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including an electric field in the lateral direction, an electric field in the longitudinal direction, or an electric field in the oblique direction). As liquid crystals used for liquid crystal elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. may be used. Can. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

Further, as the liquid crystal material, either a positive type liquid crystal or a negative type liquid crystal may be used, and an optimum liquid crystal material may be used according to the applied mode or design.

In addition, in order to control the alignment of the liquid crystal, an alignment film can be provided. Note that in the case of employing the in-plane switching mode, liquid crystal exhibiting a blue phase for which an alignment film is not used may be used. The blue phase is one of the liquid crystal phases, and is a phase which appears immediately before the cholesteric liquid phase is changed to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight% or more of a chiral agent is mixed is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic. In addition, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. In addition, since it is not necessary to provide an alignment film, rubbing processing is also unnecessary, so electrostatic breakdown caused by rubbing processing can be prevented, and defects and breakage of the liquid crystal display device in the manufacturing process can be reduced. .

As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, or the like can be used.

In one embodiment of the present invention, in particular, a reflective liquid crystal element can be used.

In the case of using a transmissive or semi-transmissive liquid crystal element, two polarizing plates are provided so as to sandwich the pair of substrates. In addition, a backlight is provided outside the polarizing plate. The backlight may be a direct type backlight or an edge light type backlight. It is preferable to use a direct-type backlight provided with an LED (Light Emitting Diode) because local dimming becomes easy and contrast can be enhanced. In addition, it is preferable to use an edge light type backlight because the thickness of a module including the backlight can be reduced.
Preferred.

In the case of using a reflective liquid crystal element, a polarizing plate is provided on the display surface side. Further, separately from this, it is preferable to dispose a light diffusion plate on the display surface side because visibility can be improved.

In the case of using a reflective or semi-transmissive liquid crystal element, a front light may be provided outside the polarizing plate. It is preferable to use an edge light type front light as the front light. It is preferable to use a front light including an LED (Light Emitting Diode) because power consumption can be reduced.

[Light-emitting element]
As a light-emitting element, an element capable of self-emission can be used, and an element whose luminance is controlled by current or voltage is included in its category. For example, an LED, an organic EL element, an inorganic EL element, or the like can be used.

The light emitting element includes a top emission type, a bottom emission type, a dual emission type, and the like. A conductive film transmitting visible light is used for the electrode on the side from which light is extracted. In addition, it is preferable to use a conductive film that reflects visible light for the electrode on the side where light is not extracted.

The EL layer has at least a light emitting layer. As the EL layer, as a layer other than the light emitting layer, a substance having a high hole injecting property, a substance having a high hole transporting property, a hole blocking material, a substance having a high electron transporting property, a substance having a high electron injecting property, or a bipolar property It may further have a layer containing a substance (a substance having a high electron transporting property and a hole transporting property) or the like.

Either a low molecular weight compound or a high molecular weight compound can be used in the EL layer, and an inorganic compound may be contained. The layers constituting the EL layer can be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

When a voltage higher than the threshold voltage of the light emitting element is applied between the cathode and the anode, holes are injected into the EL layer from the anode side, and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light-emitting substance contained in the EL layer emits light.

In the case of applying a white light emitting element as the light emitting element, it is preferable that the EL layer include two or more kinds of light emitting substances. For example, white light emission can be obtained by selecting a light emitting substance so that the light emission of each of two or more light emitting substances is in a complementary color relationship. For example, light-emitting substances that emit light such as R (red), G (green), B (blue), Y (yellow), O (orange), etc., or spectral components of two or more of R, G, B It is preferable to contain 2 or more among the light-emitting substances which emit light including. In addition, it is preferable to apply a light emitting element in which the spectrum of light emitted from the light emitting element has two or more peaks in the wavelength range of visible light (for example, 350 nm to 750 nm). The emission spectrum of the material having a peak in the yellow wavelength region is preferably a material having spectral components in the green and red wavelength regions.

The EL layer preferably has a structure in which a light emitting layer containing a light emitting material emitting light of one color and a light emitting layer containing a light emitting material emitting light of another color are laminated. For example, the plurality of light emitting layers in the EL layer may be stacked in contact with each other, or may be stacked via a region which does not include any light emitting material. For example, as a structure in which a region including the same material (eg, host material or assist material) as the fluorescent light emitting layer or the phosphorescent light emitting layer is included between the fluorescent light emitting layer and the phosphorescent light emitting layer and which does not contain any light emitting material It is also good. This facilitates the manufacture of the light emitting element and reduces the driving voltage.

The light emitting element may be a single element having one EL layer, or may be a tandem element in which a plurality of EL layers are stacked via a charge generation layer.

The conductive film which transmits visible light can be formed using, for example, indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide to which gallium is added, or the like. In addition, metallic materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, alloys containing these metallic materials, or nitrides of these metallic materials (for example, Titanium nitride or the like can also be used as thin as it has translucency. In addition, a stacked film of the above materials can be used as the conductive layer. For example, the use of a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because the conductivity can be increased. Alternatively, graphene or the like may be used.

The conductive film that reflects visible light uses, for example, a metal material such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy containing these metal materials. Can. In addition, lanthanum, neodymium, germanium, or the like may be added to the above-described metal material or alloy. Alternatively, an alloy (aluminum alloy) containing titanium, nickel, or neodymium and aluminum may be used. Alternatively, an alloy containing copper, palladium, magnesium and silver may be used. An alloy containing silver and copper is preferable because of its high heat resistance. Further, by laminating a metal film or a metal oxide film in contact with an aluminum film or an aluminum alloy film, oxidation can be suppressed. Examples of materials of such metal films and metal oxide films include titanium and titanium oxide. Alternatively, the conductive film that transmits visible light and a film made of a metal material may be stacked. For example, a stacked film of silver and indium tin oxide, a stacked film of an alloy of silver and magnesium, and indium tin oxide can be used.

The electrodes may be formed by vapor deposition or sputtering, respectively. In addition, it can be formed using a discharge method such as an inkjet method, a printing method such as a screen printing method, or a plating method.

Note that the above-described layers include a light-emitting layer, a substance with a high hole-injection property, a substance with a high hole-transport property, a substance with a high electron-transport property, a substance with a high electron-injection property, a bipolar substance, etc. Each may have an inorganic compound such as a quantum dot or a high molecular compound (eg, an oligomer, a dendrimer, or a polymer). For example, by using a quantum dot for the light-emitting layer, it can also function as a light-emitting material.

As the quantum dot material, a colloidal quantum dot material, an alloy quantum dot material, a core / shell quantum dot material, a core quantum dot material, or the like can be used. Alternatively, a material containing group 12 and group 16, group 13 and group 15, or group 14 and group 16 may be used. Alternatively, a quantum dot material containing an element such as cadmium, selenium, zinc, sulfur, phosphorus, indium, tellurium, lead, gallium, arsenic, aluminum or the like may be used.

[Adhesive layer]
As the adhesive layer, various curable adhesives such as an ultraviolet curable photocurable adhesive, a reaction curable adhesive, a thermosetting adhesive, an anaerobic adhesive and the like can be used. Examples of the adhesive include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin and the like. In particular, materials having low moisture permeability such as epoxy resins are preferable. Also, a two-component mixed resin may be used. In addition, an adhesive sheet or the like may be used.

Further, the resin may contain a desiccant. For example, a substance that adsorbs water by chemical adsorption can be used, such as an alkaline earth metal oxide (such as calcium oxide or barium oxide). Alternatively, a substance that adsorbs water by physical adsorption may be used, such as zeolite or silica gel. The inclusion of the desiccant is preferable because it can suppress the entry of impurities such as moisture into the element and the reliability of the display panel can be improved.

Moreover, light extraction efficiency can be improved by mixing the filler and light-scattering member with a high refractive index to the said resin. For example, titanium oxide, barium oxide, zeolite, zirconium or the like can be used.

[Connection layer]
As the connection layer, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used.

[Colored layer]
Materials usable for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like.

[Light-shielding layer]
Examples of the material that can be used as the light shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing a solid solution of a plurality of metal oxides. The light shielding layer may be a film containing a resin material or a thin film of an inorganic material such as metal. In addition, a stacked film of films including a material of a colored layer can also be used for the light shielding layer. For example, a layered structure of a film containing a material used for a colored layer transmitting light of a certain color and a film containing a material used for a colored layer transmitting light of another color can be used. It is preferable to use a common material for the colored layer and the light shielding layer, as it is possible to share the device and simplify the process.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

Embodiment 4
In this embodiment, operation modes that can be performed by the display device of one embodiment of the present invention will be described with reference to FIGS.

In the following, a normal operation mode (Normal mode) operating at a normal frame frequency (typically 60 Hz to 240 Hz) and an idling stop (IDS) driving mode operating at a low frame frequency are exemplified. To explain.

Note that the IDS drive mode refers to a drive method for stopping the rewriting of image data after executing the process of writing the image data. By writing the image data once and then extending the interval until the next writing of the image data, it is possible to reduce the power consumption for writing the image data in the meantime. The IDS drive mode can be, for example, a frame frequency of about 1/100 to 1/10 of the normal operation mode. Still pictures have the same video signal between successive frames. Therefore, the IDS drive mode is particularly effective when displaying a still image. By displaying an image using IDS drive, power consumption is reduced, flickering of the screen is suppressed, and eyestrain can also be reduced.

FIGS. 15A to 15C are timing charts for explaining the pixel circuit and the normal drive mode and the IDS drive mode. A pixel circuit 502 illustrated in FIG. 15A is a pixel of a general liquid crystal display device, and includes a signal line SL, a gate line GL, a transistor M1 connected to the signal line SL and the gate line GL, and a transistor M1. The capacitor Cs _LC and the liquid crystal element 501 are connected to each other. The IDS drive mode can be applied not only to the liquid crystal display device but also to an EL display device.

Here, the transistor M1 corresponds to the transistor 101 of the pixel 11a described in Embodiment 1 or the transistor 106 of the pixels 11b to 11c.

Transistor M1 may become a leak path data _{D 1.} Therefore, the smaller the off-state current of the transistor M1, the better. It is preferable to use an OS transistor as the transistor M1. The OS transistor is characterized in that the leakage current (off current) in the nonconductive state is extremely lower than that of a transistor using polycrystalline silicon or the like. By using an OS transistor for the transistor M1, charge supplied to the node ND1 can be held for a long time.

Further, in the circuit diagram shown in FIG. 15 (A), also a liquid crystal element 501 becomes a leak path data _{D 1.} Therefore, in order to perform IDS driving appropriately, the resistivity of the liquid crystal element 501 is preferably 1.0 × 10 ¹⁴ Ω · cm or more.

Note that, for example, an In—Ga—Zn oxide, an In—Zn oxide, or the like can be preferably used for the channel region of the OS transistor.

FIG. 15B is a timing chart showing waveforms of signals given to the signal line SL and the gate line GL in the normal drive mode. The normal drive mode operates at a normal frame frequency (eg, 60 Hz). It expressed one frame period from the period T ₁ to T _3, given a scan signal to the gate line GL in each frame period, an operation for writing from the signal line SL and data D ₁ to the node ND1. This behavior, when writing same data D ₁ in a period T ₁ to T _3, or the same in the case of writing different data.

FIG. 15C is a timing chart showing waveforms of signals given to the signal line SL and the gate line GL in the IDS drive mode. The IDS drive operates at a low frame frequency (for example, 1 Hz). One frame period is represented by a period T ₁ , in which a data write period is represented by a period T _W , and a data retention period is represented by a period T _RET . IDS drive mode gives a scanning signal to the gate line GL in a period _{T W,} write data _{D 1} of the signal line SL, and a gate line GL is fixed to the low level of the voltage in the period _{T RET,} nonconductive transistor M1 It performs an operation of holding temporarily the data D ₁ written as. The low-speed frame frequency may be, for example, 0.1 Hz or more and less than 60 Hz.

Therefore, the power consumption of the display device can be reduced by using the IDS drive mode.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

Fifth Embodiment
In this embodiment, a structural example of a semiconductor device which functions as a neural network which can be used for the circuit 25 or the like described in Embodiment 1 will be described.

As shown in FIG. 16A, the neural network NN can be configured by an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. Each of the input layer IL, the output layer OL, and the intermediate layer HL has one or more neurons (units). The intermediate layer HL may be a single layer or two or more layers. A neural network having two or more intermediate layers HL can be called DNN (deep neural network), and learning using a deep neural network can also be called deep learning.

Input data is input to each neuron in the input layer IL, an output signal of a neuron in the front or rear layer is input to each neuron in the intermediate layer HL, and an output from a neuron in the front layer is input to each neuron in the output layer OL A signal is input. Each neuron may be connected to all neurons in the previous and subsequent layers (total connection) or may be connected to some neurons.

FIG. 16 (B) shows an example of operation by a neuron. Here, a neuron N and two neurons in the front layer outputting signals to the neuron N are shown. The output x ₁ of the anterior layer neuron and the output x ₂ of the anterior layer neuron are input to the neuron N. Then, the neurons N, the output _{x 1} and the sum _x 1 _w 1 ₊ x 2 _{w 2} weight _{w 1} of the multiplication result _(x 1 _{w 1)} and the output _{x 2} and the weight _{w 2} of the multiplication result _(x 2 _{w 2)} After being calculated, the bias b is added as needed to obtain the value a = x ₁ w ₁ + x ₂ w ₂ + b. Then, the value a is converted by the activation function h, and the neuron N outputs an output signal y = h (a).

Thus, the operation by the neuron includes the operation of adding the product of the output of the anterior layer neuron and the weight, that is, the product-sum operation (x ₁ w ₁ + x ₂ w _{2 above} ). This product-sum operation may be performed on software using a program or may be performed by hardware. When the product-sum operation is performed by hardware, a product-sum operation circuit can be used. A digital circuit or an analog circuit may be used as this product-sum operation circuit.

In one embodiment of the present invention, an analog circuit is used for the product-sum operation circuit. Therefore, the processing speed can be improved and the power consumption can be reduced by reducing the circuit scale of the product-sum operation circuit or reducing the number of accesses to the memory.

The product-sum operation circuit may be configured by a Si transistor or may be configured by an OS transistor. In particular, since the OS transistor has extremely small off-state current, the OS transistor is suitable as a transistor forming an analog memory of a product-sum operation circuit. Note that the product-sum operation circuit may be configured using both a Si transistor and an OS transistor. Hereinafter, a configuration example of a semiconductor device having the function of a product-sum operation circuit will be described.

<Configuration Example of Semiconductor Device>
FIG. 17 shows a configuration example of a semiconductor device MAC having a function of performing computation of a neural network. The semiconductor device MAC has a function of performing a product-sum operation of first data corresponding to coupling strength (weight) between neurons and second data corresponding to input data. Note that each of the first data and the second data can be analog data or multivalued data (discrete data). In addition, the semiconductor device MAC has a function of converting data obtained by the product-sum operation using an activation function.

The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.

Cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref. In FIG. 17, a memory cell MC (MC [1,1] to [m, n]) of m rows and n columns (m, n is an integer of 1 or more) and m memory cells MCref (MCref) are shown. An example of a configuration having [1] to [m] is shown. Memory cell MC has a function of storing first data. The memory cell MCref has a function of storing reference data used for product-sum operation. The reference data can be analog data or multivalued data.

The memory cell MC [i, j] (i is an integer of 1 to m and j is an integer of 1 to n) includes the wiring WL [i], the wiring RW [i], the wiring WD [j], and the wiring BL Connected with [j]. The memory cell MCref [i] is connected to the wiring WL [i], the wiring RW [i], the wiring WDref, and the wiring BLref. Here, the memory cell MC [i, j] to the wiring BL [j] the current flowing between denoted as _{I MC [i, j],} the current flowing between the memory cell MCref [i] and the wiring BLref _{I MCref [ i]} .

A specific configuration example of the memory cell MC and the memory cell MCref is shown in FIG. FIG. 18 shows memory cells MC [1,1], [2,1] and memory cells MCref [1], [2] as representative examples, but the same applies to other memory cells MC and memory cells MCref. The configuration of can be used. Each of the memory cell MC and the memory cell MCref includes transistors Tr11 and Tr12 and a capacitive element C11. Here, the case where the transistors Tr11 and Tr12 are n-channel transistors is described.

In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source or drain is connected to the gate of the transistor Tr12 and the first electrode of the capacitive element C11, and the other is connected to the wiring WD It is done. One of the source and the drain of the transistor Tr12 is connected to the wiring BL, and the other of the source and the drain is connected to the wiring VR. The second electrode of the capacitive element C11 is connected to the wiring RW. The wiring VR is a wiring having a function of supplying a predetermined potential. Here, as an example, the case where a low power supply potential (such as a ground potential) is supplied from the wiring VR will be described.

A node connected to one of the source and the drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitor C11 is a node NM. The nodes NM of the memory cells MC [1,1] and [2,1] are denoted as nodes NM [1,1] and [2,1], respectively.

Memory cell MCref also has a configuration similar to that of memory cell MC. However, the memory cell MCref is connected to the wiring WDref instead of the wiring WD, and is connected to the wiring BLref instead of the wiring BL. In memory cells MCref [1] and [2], one of the source and the drain of transistor Tr11, the gate of transistor Tr12, and the node connected to the first electrode of capacitive element C11 are node NMref [1], respectively. And [2].

The node NM and the node NMref function as holding nodes of the memory cell MC and the memory cell MCref, respectively. The node NM holds the first data, and the node NMref holds reference data. Further, currents I _{MC [1} , _1] and I _{MC [2, 1]} flow from the wiring BL [1] to the transistors Tr 12 of the memory cells MC [1, 1] and [2, 1], respectively. Further, currents I _{MCref [1]} and I _{MCref [2]} flow from the wiring BLref to the transistors Tr12 of the memory cells MCref [1] and [2], respectively.

Since the transistor Tr11 has a function of holding the potential of the node NM or the node NMref, the off-state current of the transistor Tr11 is preferably small. Therefore, it is preferable to use an OS transistor with extremely small off-state current as the transistor Tr11. Accordingly, fluctuation of the potential of the node NM or the node NMref can be suppressed, and the calculation accuracy can be improved. Further, the frequency of the operation of refreshing the potential of the node NM or the node NMref can be suppressed low, and power consumption can be reduced.

The transistor Tr12 is not particularly limited, and, for example, a Si transistor or an OS transistor can be used. When an OS transistor is used as the transistor Tr12, the transistor Tr12 can be manufactured using the same manufacturing apparatus as the transistor Tr11, and the manufacturing cost can be suppressed. The transistor Tr12 may be an n-channel type or a p-channel type.

The current source circuit CS is connected to the wirings BL [1] to [n] and the wiring BLref. The current source circuit CS has a function of supplying current to the wirings BL [1] to [n] and the wiring BLref. Note that the current values supplied to the wirings BL [1] to [n] may be different from the current values supplied to the wiring BLref. Here, the current supplied from the current source circuit CS to the wirings BL [1] to [n] is denoted as I _C , and the current supplied from the current source circuit CS to the wiring BLref is denoted as I _Cref .

The current mirror circuit CM includes interconnects IL [1] to [n] and an interconnect ILref. The wirings IL [1] to [n] are connected to the wirings BL [1] to [n], respectively, and the wiring ILref is connected to the wiring BLref. Here, connection points of the wirings IL [1] to [n] and the wirings BL [1] to [n] are denoted as nodes NP [1] to [n]. Further, a connection point between the wiring ILref and the wiring BLref is denoted as a node NPref.

The current mirror circuit CM has a function of causing a current I _CM according to the potential of the node NPref to flow through the wiring ILref, and a function of flowing this current I _{CM also} into the wirings IL [1] to [n]. Figure 17 is discharged current _{I CM} from the wiring BLref to the wiring ILref, wiring BL [1] to the wiring from the [n] IL [1] to [n] to the current _{I CM} is an example to be discharged . Further, currents flowing from the current mirror circuit CM to the cell array CA through the wirings BL [1] to [n] are denoted as I _B [1] to [n]. Further, the current flowing from the current mirror circuit CM to the cell array CA via the wiring _BLref is denoted as I _Bref .

The circuit WDD is connected to the wirings WD [1] to [n] and the wiring WDref. The circuit WDD has a function of supplying a potential corresponding to the first data stored in the memory cell MC to the wirings WD [1] to [n]. The circuit WDD has a function of supplying a potential corresponding to reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD is connected to the wirings WL [1] to [m]. The circuit WLD has a function of supplying a signal for selecting a memory cell MC or a memory cell MCref to which data is written, to the wirings WL [1] to [m]. The circuit CLD is connected to the wirings RW [1] to [m]. The circuit CLD has a function of supplying a potential corresponding to the second data to the wirings RW [1] to [m].

The offset circuit OFST is connected to the wirings BL [1] to [n] and the wirings OL [1] to [n]. The offset circuit OFST detects the amount of current flowing from the wirings BL [1] to [n] to the offset circuit OFST and / or the amount of change in current flowing from the wirings BL [1] to [n] to the offset circuit OFST Have. The offset circuit OFST also has a function of outputting the detection result to the wirings OL [1] to [n]. The offset circuit OFST may output a current corresponding to the detection result to the line OL, or may convert a current corresponding to the detection result to a voltage and output the voltage to the line OL. The currents flowing between the cell array CA and the offset circuit OFST are denoted by I _α [1] to [n].

A configuration example of the offset circuit OFST is shown in FIG. The offset circuit OFST shown in FIG. 19 includes circuits OC [1] to [n]. The circuits OC [1] to [n] each include a transistor Tr21, a transistor Tr22, a transistor Tr23, a capacitive element C21, and a resistive element R1. The connection relationship of each element is as shown in FIG. A node connected to the first electrode of the capacitive element C21 and the first terminal of the resistive element R1 is referred to as a node Na. A node connected to the second electrode of the capacitive element C21, one of the source and the drain of the transistor Tr21, and the gate of the transistor Tr22 is referred to as a node Nb.

The wiring VrefL has a function of supplying a potential Vref, the wiring VaL has a function of supplying a potential Va, and the wiring VbL has a function of supplying a potential Vb. The wiring VDDL has a function of supplying a potential VDD, and the wiring VSSL has a function of supplying a potential VSS. Here, the case where the potential VDD is a high power supply potential and the potential VSS is a low power supply potential will be described. The wiring RST has a function of supplying a potential for controlling the conductive state of the transistor Tr21. A source follower circuit is configured by the transistor Tr22, the transistor Tr23, the wiring VDDL, the wiring VSSL, and the wiring VbL.

Next, an operation example of the circuits OC [1] to [n] will be described. Although an operation example of the circuit OC [1] will be described here as a representative example, the circuits OC [2] to [n] can be operated similarly. First, when the first current flows through the wiring BL [1], the potential of the node Na becomes a potential corresponding to the first current and the resistance value of the resistor element R1. At this time, the transistor Tr21 is in the on state, and the potential Va is supplied to the node Nb. Thereafter, the transistor Tr21 is turned off.

Next, when a second current flows through the wiring BL [1], the potential of the node Na changes to a potential corresponding to the second current and the resistance value of the resistor element R1. At this time, since the transistor Tr21 is in the off state and the node Nb is in the floating state, the potential of the node Nb changes due to capacitive coupling with the change of the potential of the node Na. Here, assuming that the change in the potential of the node Na is ΔV _Na and the capacitive coupling coefficient is 1, the potential of the node Nb is Va + ΔV _Na . Then, assuming that the threshold voltage of the transistor Tr22 is V _th , the potential Va + ΔV _Na −V _th is output from the wiring OL [1]. Here, by setting Va = V _th , the potential ΔV _Na can be output from the wiring OL [1].

Potential ΔV _Na is determined according to the amount of change from the first current to the second current, resistance element R1, and potential Vref. Here, since the resistance element R1 and the potential Vref are known, the amount of change in current flowing from the potential ΔV _Na to the wiring BL can be obtained.

As described above, a signal corresponding to the amount of current detected by the offset circuit OFST and / or the amount of change in current is input to the activation function circuit ACTV through the wirings OL [1] to [n].

The activation function circuit ACTV is connected to the wirings OL [1] to [n] and the wirings NIL [1] to [n]. The activation function circuit ACTV has a function of performing an operation for converting a signal input from the offset circuit OFST in accordance with a previously defined activation function. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function or the like can be used. The signals converted by the activation function circuit ACTV are output to the wirings NIL [1] to [n] as output data.

<Operation Example of Semiconductor Device>
The product-sum operation of the first data and the second data can be performed using the above-described semiconductor device MAC. Hereinafter, an operation example of the semiconductor device MAC when performing a product-sum operation will be described.

FIG. 20 shows a timing chart of an operation example of the semiconductor device MAC. In FIG. 20, the wiring WL [1], the wiring WL [2], the wiring WD [1], the wiring WDref, the node NM [1,1], the node NM [2,1], and the node NMref [1] in FIG. , The transition of the potential of the node NMref [2], the wiring RW [1], and the wiring RW [2], and the transition of the values of the current I _B [1] -I _α [1] and the current I _Bref . The current I _B [1] -I _α [1] corresponds to the sum of the currents flowing from the wiring BL [1] to the memory cells MC [1, 1] and [2, 1].

Here, the operation will be described focusing on memory cells MC [1,1], [2,1] and memory cells MCref [1], [2] shown in FIG. 18 as a representative example, but other memory cells are described. MC and memory cell MCref can be operated similarly.

[First data storage]
First, the time at T01-T02, the potential of the wiring WL [1] becomes high level, the _V PR _{-V W [1,1]} greater potential the potential of the wiring WD [1] is higher than the ground potential (GND), wiring potential of WDref becomes the _{V PR} greater potential than the ground potential. Further, the potentials of the wiring RW [1] and the wiring RW [2] become a reference potential (REFP). The potential V _{W [1, 1]} is a potential corresponding to the first data stored in the memory cell MC [1, 1]. Further, the potential _VPR is a potential corresponding to reference data. Thus, the memory cell MC [1,1] and the transistor Tr11 having a memory cell MCref [1] is is turned on and node NM potential of [1,1] is _V PR _{-V W [1,1],} the node NMref The potential of [1] becomes _VPR .

At this time, the current I _{MC [1, 1], 0} flowing from the wiring BL [1] to the transistor Tr12 of the memory cell MC [1, 1] can be expressed by the following equation. Here, k is a constant determined by the channel length, channel width, mobility, and the capacity of the gate insulating film of the transistor Tr12. Further, V _th is a threshold voltage of the transistor Tr12.

_{I MC [1,1], 0 =} k (V PR -V W [1,1] -V th) 2 (E1)

Further, the current I _{MCref [1], 0} flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref [1] can be expressed by the following equation.

_{I MCref [1], 0 =} k (V PR -V th) 2 (E2)

Next, at time T02 to T03, the potential of the wiring WL [1] becomes low. Accordingly, the transistor Tr11 included in the memory cell MC [1,1] and the memory cell MCref [1] is turned off, and the potentials of the node NM [1,1] and the node NMref [1] are held.

As described above, it is preferable to use an OS transistor as the transistor Tr11. Thus, the leak current of the transistor Tr11 can be suppressed, and the potentials of the node NM [1,1] and the node NMref [1] can be accurately held.

Then, at time T03-T04, the potential of the wiring WL [2] becomes the high level, the potential of the wiring WD [1] becomes _V PR _{-V W [2,1]} greater potential than the ground potential, of the wiring WDref potential becomes the V _PR greater potential than the ground potential. The potential V _{W [2, 1]} is a potential corresponding to the first data stored in the memory cell MC [2, 1]. Thus, the memory cell MC [2,1] and the transistor Tr11 having a memory cell MCref [2] are turned on, the node NM potential of [1,1] is _V PR _{-V W [2,1],} the node NMref The potential of [1] becomes _VPR .

At this time, the current I _{MC [2, 1], 0} flowing from the wiring BL [1] to the transistor Tr12 of the memory cell MC [2, 1] can be expressed by the following equation.

_{I MC [2,1], 0 =} k (V PR -V W [2,1] -V th) 2 (E3)

Further, the current I _{MCref [2], 0} flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref [2] can be expressed by the following equation.

_{I MCref [2], 0 =} k (V PR -V th) 2 (E4)

Next, at time T04 to T05, the potential of the wiring WL [2] becomes low. Accordingly, the transistor Tr11 included in the memory cell MC [2,1] and the memory cell MCref [2] is turned off, and the potentials of the node NM [2,1] and the node NMref [2] are held.

By the above operation, the first data is stored in the memory cells MC [1,1], [2,1], and the reference data is stored in the memory cells MCref [1], [2].

Here, consider the current flowing to the wiring BL [1] and the wiring BLref at time T04 to T05. A current is supplied from the current source circuit CS to the wiring BLref. Further, the current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref [1] and [2]. Assuming that the current supplied from the current source circuit CS to the wiring BLref is I _Cref and the current discharged from the wiring BLref to the current mirror circuit CM is I _{CM, 0} , the following equation is established.

I _Cref −I _{CM, 0} = I _{MCref [1], 0} + I _{MCref [2], 0} (E5)

The current from the current source circuit CS is supplied to the wiring BL [1]. Further, the current flowing through the wiring BL [1] is discharged to the current mirror circuit CM and the memory cells MC [1,1] and [2,1]. In addition, a current flows from the wiring BL [1] to the offset circuit OFST. Assuming that the current supplied from the current source circuit CS to the wiring BL [1] is I _{C, 0} and the current flowing from the wiring BL [1] to the offset circuit OFST is I _{α, 0} , the following equation is established.

I _C −I _{CM, 0} = I _{MC [1,1], 0} + I _{MC [2,1], 0} + I _{α, 0} (E6)

[Product-Sum operation of first data and second data]
Next, at time T05 to T06, the potential of the wiring RW [1] is higher than the reference potential by V _{X [1]} . At this time, the potential V _{X [1]} is supplied to the capacitive element C11 of each of the memory cell MC [1,1] and the memory cell MCref [1], and the potential of the gate of the transistor Tr12 rises due to capacitive coupling. The potential V _{x [1]} is a potential corresponding to the second data supplied to the memory cell MC [1, 1] and the memory cell MCref [1].

The amount of change in the potential of the gate of the transistor Tr12 is a value obtained by multiplying the amount of change in the potential of the wiring RW by the capacitive coupling coefficient determined by the configuration of the memory cell. The capacitive coupling coefficient is calculated by the capacitance of the capacitive element C11, the gate capacitance of the transistor Tr12, the parasitic capacitance, and the like. Hereinafter, for convenience, it is assumed that the amount of change in the potential of the wiring RW and the amount of change in the potential of the gate of the transistor Tr12 are the same, that is, the capacitive coupling coefficient is 1. In practice, the potential V _x may be determined in consideration of the capacitive coupling coefficient.

When potential V _{X [1]} is supplied to capacitive element C11 of memory cell MC [1] and memory cell MCref [1], the potentials of nodes NN [1] and NMref [1] are V _{X [1],} respectively _. To rise.

Here, the current I _{MC [1, 1], 1} that flows from the wiring BL [1] to the transistor Tr12 of the memory cell MC [1, 1] at time T05 to T06 can be expressed by the following equation.

_{I MC [1,1], 1 =} k (V PR -V W [1,1] + V X [1] -V th) 2 (E7)

That is, by supplying the potential V _{X [1]} to the wiring RW [1], the current flowing from the wiring BL [1] to the transistor Tr12 of the memory cell MC [1,1] is ΔI _{MC [1,1]} = I _{MC [1,1], 1-} I _{MC [1,1], 0} increase.

At time T05 to T06, current I _{MCref [1], 1} flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref [1] can be expressed by the following equation.

_{I MCref [1], 1 =} k (V PR + V X [1] -V th) 2 (E8)

That is, by supplying potential V _{X [1]} to the wiring RW [1], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref [1] is ΔI _{MCref [1]} = I _{MCref [1], 1} -I _{MCref [1],} increases by ₀ .

Further, the current flowing to the wiring BL [1] and the wiring BLref will be considered. The current I _Cref is supplied from the current source circuit CS to the wiring BLref. Further, the current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref [1] and [2]. Assuming that the current discharged from the wiring BLref to the current mirror circuit CM is I _{CM, 1} , the following equation is established.

I _Cref −I _{CM, 1} = I _{MCref [1], 1} + I _{MCref [2], 1} (E9)

The current I _C is supplied from the current source circuit CS to the wiring BL [1]. Further, the current flowing through the wiring BL [1] is discharged to the current mirror circuit CM and the memory cells MC [1,1] and [2,1]. Further, current flows from the wiring BL [1] to the offset circuit OFST. Assuming that the current flowing from the wiring BL [1] to the offset circuit OFST is I _{α, 1} , the following equation is established.

I _C −I _{CM, 1} = I _{MC [1,1], 1} + I _{MC [2,1], 1} + I _{α, 1} (E10)

Then, the difference between the current I _{α, 0} and the current I _{α, 1} (difference current ΔI _α ) can be expressed by the following equation from the equations (E1) to (E10).

ΔI _α = I _{α, 1} −I _{α, 0} = 2 kV _{W [1,1]} V _{X [1]} (E11)

Thus, the differential current ΔI _α takes a value corresponding to the product of the potentials V _{W [1, 1]} and V _{X [1]} .

After that, at time T06 to T07, the potential of the wiring RW [1] becomes the ground potential, and the potentials of the node NM [1,1] and the node NMref [1] become similar to those at time T04 to T05.

Next, at time T07 to T08, the potential of the wiring RW [1] becomes V _{X [1]} larger than the reference potential, and the potential of the wiring RW [2] is V _{X [2]} larger than the reference potential Supplied. Thereby, potential V _{X [1]} is supplied to capacitive element C11 of each of memory cell MC [1, 1] and memory cell MCref [1], and node NM [1, 1] and node NMref [ The potential of _1] rises by V _{X [1]} . In addition, potential V _{X [2]} is supplied to capacitive element C11 of each of memory cell MC [2, 1] and memory cell MCref [2], and node NM [2, 1] and node NMref [2 Each of the potentials of V _{] [2]} rises.

Here, the current I _{MC [2, 1], 1} flowing from the wiring BL [1] to the transistor Tr12 of the memory cell MC [2, 1] at time T07 to T08 can be expressed by the following equation.

_{I MC [2,1], 1 =} k (V PR -V W [2,1] + V X [2] -V th) 2 (E12)

That is, by supplying the potential V _{X [2]} to the wiring RW [2], the current flowing from the wiring BL [1] to the transistor Tr12 of the memory cell MC [2, 1] is ΔI _{MC [2, 1]} = I _{MC [2, 1], 1-} I _{MC [2, 1],} increases by ₀ .

Further, at time T05 to T06, the current I _{MCref [2], 1} flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref [2] can be expressed by the following equation.

_{I MCref [2], 1 =} k (V PR + V X [2] -V th) 2 (E13)

That is, by supplying potential V _{X [2]} to the wiring RW [2], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref [2] is ΔI _{MCref [2]} = I _{MCref [2], 1} -I _{MCref [2],} increases by ₀ .

Further, the current flowing to the wiring BL [1] and the wiring BLref will be considered. The current I _Cref is supplied from the current source circuit CS to the wiring BLref. Further, the current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref [1] and [2]. Assuming that the current discharged from the wiring BLref to the current mirror circuit CM is I _{CM, 2} , the following equation holds.

I _Cref −I _{CM, 2} = I _{MCref [1], 1} + I _{MCref [2], 1} (E14)

The current I _C is supplied from the current source circuit CS to the wiring BL [1]. Further, the current flowing through the wiring BL [1] is discharged to the current mirror circuit CM and the memory cells MC [1,1] and [2,1]. Further, current flows from the wiring BL [1] to the offset circuit OFST. Assuming that the current flowing from the wiring BL [1] to the offset circuit OFST is I _{α, 2} , the following equation is established.

I _C −I _{CM, 2} = I _{MC [1,1], 1} + I _{MC [2,1], 1} + I _{α, 2} (E15)

Then, the difference between the current I _{α, 0} and the current I _{α, 2} (difference current ΔI _α ) is expressed by the following equation from the equations (E1) to (E8) and the equations (E12) to (E15) be able to.

ΔI _α = I _{α, 2} −I _{α, 0} = 2 k (V _{W [1, 1]} V _{X [1]} + V _{W [2, 1]} V _{X [2]} ) (E16)

Thus, the difference current ΔI _α is obtained by adding the product of the potential V _{W [1, 1]} and the potential V _{X [1] and} the product of the potential V _{W [2, 1]} and the potential V _{X [2].} It becomes a value according to the combined result.

After that, at time T08-T09, the potentials of the wirings RW [1] and [2] become the ground potential, and the potentials of the nodes NM [1,1] and [2,1] and the nodes NMref [1] and [2] become It becomes the same as time T04-T05.

As shown in the equation (E9) and the equation (E16), the differential current ΔI _α input to the offset circuit OFST has the potential V _X corresponding to the first data (weight) and the second data (input data And the value corresponding to the result of adding the product of the potential V _W corresponding to. That is, by measuring the difference current ΔI _α with the offset circuit OFST, it is possible to obtain the result of the product-sum operation of the first data and the second data.

Although the above description focuses on the memory cells MC [1,1], [2,1] and the memory cells MCref [1], [2], the number of memory cells MC and memory cells MCref may be set arbitrarily. Can. The differential current ΔIα when the number m of rows of the memory cell MC and the memory cell MCref is an arbitrary number can be expressed by the following equation.

ΔI _α = 2 k _{i i} V _{W [i, 1]} V _{X [i]} (E17)

Further, by increasing the number n of columns of the memory cell MC and the memory cell MCref, the number of product-sum operations to be executed in parallel can be increased.

As described above, by using the semiconductor device MAC, product-sum operation of the first data and the second data can be performed. By using the configuration shown in FIG. 14 as memory cell MC and memory cell MCref, a product-sum operation circuit can be configured with a small number of transistors. Therefore, the circuit scale of the semiconductor device MAC can be reduced.

When the semiconductor device MAC is used for computation in a neural network, the number m of rows of memory cells MC corresponds to the number of input data supplied to one neuron, and the number n of columns of memory cells MC corresponds to the number of neurons Can. For example, it is assumed that a product-sum operation is performed using semiconductor device MAC in intermediate layer HL shown in FIG. At this time, the number m of rows of memory cells MC is set to the number of input data supplied from the input layer IL (the number of neurons in the input layer IL), and the number n of columns of memory cells MC is the neurons in the intermediate layer HL It can be set to the number of

The structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC can also be used for a convolutional neural network (CNN), a recursive neural network (RNN), an auto encoder, a Boltzmann machine (including a restricted Boltzmann machine), and the like.

As described above, by using the semiconductor device MAC, product-sum operations of neural networks can be performed. Furthermore, by using the memory cell MC and the memory cell MCref shown in FIG. 18 for the cell array CA, it is possible to provide an integrated circuit IC capable of improving calculation accuracy, reducing power consumption, or reducing circuit scale. it can.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

Sixth Embodiment
As an electronic device that can use the display device according to one aspect of the present invention, a display device, a personal computer, an image storage device or an image reproduction device provided with a recording medium, a mobile phone, a game machine including a mobile type, a mobile data terminal , E-book reader, video camera, camera such as digital still camera, goggle type display (head mounted display), navigation system, sound reproduction device (car audio, digital audio player etc), copier, facsimile, printer, printer complex machine , Automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIG.

21A illustrates a television, which includes a housing 971, a display portion 973, operation keys 974, speakers 975, a communication connection terminal 976, an optical sensor 977, and the like. The display portion 973 is provided with a touch sensor and can also perform input operation. By using the display device of one embodiment of the present invention for the display portion 973, display with high display quality can be performed.

FIG. 21B illustrates an information processing terminal, which includes a housing 901, a display portion 902, a display portion 903, a sensor 904, and the like. The display portion 902 and the display portion 903 are formed of one display panel and have flexibility. In addition, the housing 901 also has flexibility and can be used by being bent as illustrated, or can be used in a flat plate shape like a tablet terminal. The sensor 904 can sense the shape of the housing 901, and can switch the display of the display portion 902 and the display portion 903 when the housing is bent, for example. With the use of the display device of one embodiment of the present invention for the display portion 902 and the display portion 903, display with high display quality can be performed.

FIG. 21C illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display portion 965, an operation key 966, a zoom lever 968, a lens 969, and the like. With the display device of one embodiment of the present invention for the display portion 965, display with high display quality can be performed.

FIG. 21D shows digital signage, which has a configuration in which a large display portion 922 is attached to the side surface of a pillar 921. FIG. By using the display device of one embodiment of the present invention for the display portion 922, display with high display quality can be performed.

FIG. 21E illustrates an example of a mobile phone, which includes a housing 951, a display portion 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, and the like. The mobile phone includes the touch sensor in the display portion 952. All operations such as making a call and inputting characters can be performed by touching the display portion 952 with a finger, a stylus, or the like. In addition, the housing 901 and the display portion 952 have flexibility and can be used by being bent as illustrated. With the use of the display device of one embodiment of the present invention for the display portion 952, display with high display quality can be performed.

FIG. 21F illustrates a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, and the like. Information can be input / output by the touch panel function of the display portion 912. With the use of the display device of one embodiment of the present invention for the display portion 912, display with high display quality can be performed.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.

11 pixel 11a pixel 11b pixel 11c pixel 11e pixel unit 17 pixel 18 pixel 21 row driver 22 row driver 23 column driver 24 column driver 25 circuit 26 column driver 27 circuit 40 pixel array 45 pixel unit 46 pixel 46B display element 46G display element 46R display Element 47 Pixel 47 B Display element 47 G Display element 47 R Display element 55 Light 100 E Capacitance element 101 Transistor 101 E Transistor 101 L Transistor 102 E Transistor 102 L Transistor 103 L Capacitance element 103 L Capacitance element 103 L Capacitance element 104 L Capacitance element 104 L Capacitance element 105 L Liquid crystal element 106 107L transistor 108E transistor 109E capacitive element 1 10E EL element 111E transistor 112 transistor 115E transistor 116L transistor 116L transistor 117 insulating layer 117E capacitor element 117L capacitor element 121 insulating layer 121E wiring 121L wiring 121LE wiring 122E wiring 122L wiring 122LE wiring 123E wiring 123L wiring 124E wiring 124L wiring 125E wiring 125L Wiring 126E Wiring 126L Wiring 127L Common Wiring 128L Common Wiring 129 Light Diffusing Plate 129E Common Wiring 130 Polarizing Plate 130E Wiring 131 Colored Layer 132 Light Shielding Layer 133a Alignment Film 133b Alignment Film 134 Colored Layer 141 Adhesive Layer 142 Adhesive Layer 191 Conductive Layer 192 EL Layer 193a conductive layer 193b conductive layer 201 transistor 204 connection portion 205 transistor 2 6 Transistor 207 Connection portion 211 Insulating layer 212 Insulating layer 213 Insulating layer 214 Insulating layer 215 Insulating layer 216 Insulating layer 217 Insulating layer 220 Insulating layer 221 Insulating layer 221 Conductive layer 223 Conductive layer 224 Conductive layer 231 Semiconductor layer 242 Connection layer 243 Connection body 251 opening 252 connection portion 300 display panel 311 a conductive layer 311 b conductive layer 312 liquid crystal 313 conductive layer 340 liquid crystal element 351 substrate 360 EL element 361 substrate 362 display portion 364 circuit 365 wiring 366 input device 372 FPC
373 IC
Reference numeral 410 pixel 451 opening 501 liquid crystal element 502 pixel circuit 560 substrate 901 housing 902 display area 904 display area 904 sensor 911 housing 912 camera area 919 pillar 921 pillar 922 display area 951 housing 952 display area 953 operation button 954 external connection port 955 Speaker 956 Microphone 957 Camera 961 Housing 962 Shutter button 963 Microphone 965 Display 966 Operation key 967 Speaker 968 Zoom lever 969 Lens 971 Housing 973 Display 974 Operation key 975 Speaker 976 Communication connection terminal 977 Optical sensor

Claims (13)

A display device including a pixel in which a first display element, a second display element, a first memory circuit, and a second memory circuit are provided,
The first memory circuit has a function of storing a first correction signal.
The second memory circuit has a function of storing a second correction signal.
The first memory circuit has a function of adding the first correction signal to a first image signal to generate a third image signal.
The second memory circuit has a function of adding the second correction signal to a second image signal to generate a fourth image signal.
The first display element has a function of performing display based on the third image signal,
The display device having a function of performing display based on the fourth image signal. In claim 1,
The display device in which the first display element is a reflective liquid crystal element. In claim 1 or 2,
The display device in which the second display element is a light emitting element. In any one of claims 1 to 3,
A display device having a function of displaying an image by one or both of the first light reflected by the first display element and the second light emitted by the second display element. In any one of claims 1 to 4,
A first transistor, a second transistor, and a first capacitive element;
One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitive element,
One electrode of the first capacitive element is electrically connected to the first display element,
One of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitive element,
The display device in which the other electrode of the first capacitive element is electrically connected to the first memory circuit. In claim 5,
The first memory circuit includes a third transistor, a fourth transistor, and a second capacitor.
The gate of the third transistor is electrically connected to one of the source and the drain of the fourth transistor,
One of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitive element,
One of a source and a drain of the third transistor is electrically connected to the other electrode of the first capacitor element. In claim 6,
At least a fourth transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, And Nd or Hf). In claim 6 or 7,
The other of the source and the drain of the second transistor is electrically connected to a low potential power supply line,
A display device in which the other of the source and the drain of the third transistor is electrically connected to a high potential power supply line. In any one of claims 5 to 8,
And a fifth transistor and a sixth transistor,
One of the source or the drain of the fifth transistor is electrically connected to one of the source or the drain of the first transistor,
The other of the source and the drain of the fifth transistor is electrically connected to the first display element,
One of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor,
The display device in which the other of the source and the drain of the sixth transistor is electrically connected to a low potential power supply line. In any one of claims 1 to 9,
A seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a third capacitive element, and a fourth capacitive element;
One of the source and the drain of the seventh transistor is electrically connected to one electrode of the third capacitive element,
One electrode of the third capacitive element is electrically connected to one of the source and the drain of the eighth transistor,
The other of the source and the drain of the eighth transistor is electrically connected to one of the source and the drain of the ninth transistor,
One of the source and the drain of the ninth transistor is electrically connected to one electrode of the fourth capacitive element,
The other of the source and the drain of the ninth transistor is electrically connected to a low potential power supply line,
One electrode of the fourth capacitive element is electrically connected to the gate of the tenth transistor,
One of the source and the drain of the tenth transistor is electrically connected to the other electrode of the fourth capacitive element,
The other electrode of the fourth capacitive element is electrically connected to one electrode of the second display element;
One of the source and the drain of the eleventh transistor is electrically connected to the other electrode of the third capacitive element,
The display device in which the other electrode of the third capacitive element is electrically connected to the second memory circuit. In claim 10,
The second memory circuit includes a twelfth transistor, a thirteenth transistor, and a fifth capacitance element.
The gate of the twelfth transistor is electrically connected to one of the source and the drain of the thirteenth transistor,
One of the source and the drain of the thirteenth transistor is electrically connected to one electrode of the fifth capacitive element,
One of a source and a drain of the twelfth transistor is electrically connected to the other electrode of the third capacitive element. In claim 11,
At least a thirteenth transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, And Nd or Hf). An electronic device comprising the display device according to any one of claims 1 to 12 and a camera.

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