JP2019041063A5 - - Google Patents
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- JP2019041063A5 JP2019041063A5 JP2017163772A JP2017163772A JP2019041063A5 JP 2019041063 A5 JP2019041063 A5 JP 2019041063A5 JP 2017163772 A JP2017163772 A JP 2017163772A JP 2017163772 A JP2017163772 A JP 2017163772A JP 2019041063 A5 JP2019041063 A5 JP 2019041063A5
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- JP
- Japan
- Prior art keywords
- conductive substrate
- resist mask
- opening
- forming
- terminals
- Prior art date
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- 239000000758 substrate Substances 0.000 claims description 29
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000000875 corresponding Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 1
Description
また、本発明による半導体素子搭載用基板の製造方法は、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から剥離除去可能な導電性基板の一方の側の面に、面全体を覆う第１のレジストマスクを形成するとともに、前記導電性基板の他方の側の面に、所定間隔をあけて配列される複数の所定位置を開口する第１のレジストマスクを形成する工程と、前記第１のレジストマスクの開口から前記導電性基板にハーフエッチング加工を施し、該導電性基板の他方の側の面に、所定間隔をあけて配列される複数の凹部を形成する工程と、前記導電性基板の両面に形成した前記第１のレジストマスクを除去する工程と、前記導電性基板の一方の側の面に、端子に対応する複数の所定位置を開口する第２のレジストマスクを形成するとともに、該導電性基板の他方の側の面に、面全体を覆う第２のレジストマスクを形成する工程と、前記第２のレジストマスクの開口から前記導電性基板にめっき加工を施し、複数の端子を形成する工程と、前記導電性基板の面に形成したレジストマスクを除去する工程と、を有することを特徴としている。 Further, the method for manufacturing a semiconductor element mounting substrate according to the present invention, a surface of one side of a conductive substrate that can be peeled off from a resin sealing body in which a semiconductor element mounting region is sealed with a sealing resin, Forming a first resist mask covering the entire surface, and forming a first resist mask that opens a plurality of predetermined positions arranged at predetermined intervals on the other surface of the conductive substrate. And half-etching the conductive substrate through the opening of the first resist mask to form a plurality of recesses on the other surface of the conductive substrate at predetermined intervals. A step of removing the first resist mask formed on both surfaces of the conductive substrate, and a second resist mask for opening a plurality of predetermined positions corresponding to terminals on the surface on one side of the conductive substrate. To form , On the other side surface of the conductive substrate, and forming a second resist mask covering the entire surface, the plating on the conductive substrate from the opening of the second resist mask applied, a plurality of terminals And a step of removing the resist mask formed on the surface of the conductive substrate.
そして、このような本発明の半導体素子搭載用基板は、半導体素子が搭載された領域を封止樹脂で封止した樹脂封止体から剥離除去可能な導電性基板の一方の側の面に、面全体を覆う第１のレジストマスクを形成するとともに、導電性基板の他方の側の面に、所定間隔をあけて配列される複数の所定位置を開口する第１のレジストマスクを形成する工程と、第１のレジストマスクの開口から導電性基板にハーフエッチング加工を施し、導電性基板の他方の側の面に、所定間隔をあけて配列される複数の凹部を形成する工程と、導電性基板の両面に形成した第１のレジストマスクを除去する工程と、導電性基板の一方の側の面に、端子に対応する複数の所定位置を開口する第２のレジストマスクを形成するとともに、導電性基板の他方の側の面に、面全体を覆う第２のレジストマスクを形成する工程と、第２のレジストマスクの開口から導電性基板にめっき加工を施し、複数の端子を形成する工程と、導電性基板の面に形成したレジストマスクを除去する工程と、を有することによって製造可能である。 Then, such a semiconductor element mounting substrate of the present invention, on the surface of one side of the conductive substrate that can be peeled and removed from the resin encapsulant that seals the region in which the semiconductor element is mounted with a sealing resin, Forming a first resist mask that covers the entire surface, and forming a first resist mask that opens a plurality of predetermined positions arranged at predetermined intervals on the other surface of the conductive substrate; A step of performing a half-etching process on the conductive substrate from the opening of the first resist mask to form a plurality of recesses arranged at predetermined intervals on the other surface of the conductive substrate; And removing the first resist mask formed on both surfaces of the conductive substrate, and forming a second resist mask for opening a plurality of predetermined positions corresponding to the terminals on the surface on one side of the conductive substrate, and The other side of the board And forming a second resist mask covering the entire surface is subjected to plating the conductive substrate through the opening of the second resist mask to form a plurality of terminals, formed on the surface of the conductive substrate And a step of removing the resist mask.
Claims (1)
前記第１のレジストマスクの開口から前記導電性基板にハーフエッチング加工を施し、該導電性基板の他方の側の面に、所定間隔をあけて配列される複数の凹部を形成する工程と、
前記導電性基板の両面に形成した前記第１のレジストマスクを除去する工程と、
前記導電性基板の一方の側の面に、端子に対応する複数の所定位置を開口する第２のレジストマスクを形成するとともに、該導電性基板の他方の側の面に、面全体を覆う第２のレジストマスクを形成する工程と、
前記第２のレジストマスクの開口から前記導電性基板にめっき加工を施し、複数の端子を形成する工程と、
前記導電性基板の面に形成したレジストマスクを除去する工程と、
を有することを特徴とする半導体素子搭載用基板の製造方法。 A first resist mask that covers the entire surface is formed on the surface on one side of the conductive substrate that can be peeled off from the resin encapsulant in which the region on which the semiconductor element is mounted is encapsulated with an encapsulating resin, and Forming a first resist mask on the other surface of the conductive substrate at a plurality of predetermined positions arranged at predetermined intervals;
Half-etching the conductive substrate through the opening of the first resist mask to form a plurality of recesses arranged on the other surface of the conductive substrate at predetermined intervals;
Removing the first resist mask formed on both sides of the conductive substrate;
A second resist mask for opening a plurality of predetermined positions corresponding to the terminals is formed on the surface on one side of the conductive substrate, and a second resist mask covering the entire surface is formed on the surface on the other side of the conductive substrate. A step of forming a second resist mask,
Plating the conductive substrate from the opening of the second resist mask to form a plurality of terminals;
Removing the resist mask formed on the surface of the conductive substrate,
A method of manufacturing a semiconductor element mounting substrate, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017163772A JP6901201B2 (en) | 2017-08-28 | 2017-08-28 | Substrate for mounting semiconductor elements and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017163772A JP6901201B2 (en) | 2017-08-28 | 2017-08-28 | Substrate for mounting semiconductor elements and its manufacturing method |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019041063A JP2019041063A (en) | 2019-03-14 |
| JP2019041063A5 true JP2019041063A5 (en) | 2020-04-16 |
| JP6901201B2 JP6901201B2 (en) | 2021-07-14 |
Family
ID=65725919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017163772A Active JP6901201B2 (en) | 2017-08-28 | 2017-08-28 | Substrate for mounting semiconductor elements and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6901201B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3921880B2 (en) * | 1999-07-09 | 2007-05-30 | 松下電器産業株式会社 | Manufacturing method of resin-encapsulated semiconductor device |
| JP2011204826A (en) * | 2010-03-25 | 2011-10-13 | Renesas Electronics Corp | Masking tape and method of manufacturing semiconductor device |
| JP2017208516A (en) * | 2016-05-20 | 2017-11-24 | Ｓｈマテリアル株式会社 | Wiring member for multi-row type semiconductor device, and method of manufacturing the same |
-
2017
- 2017-08-28 JP JP2017163772A patent/JP6901201B2/en active Active
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