JP2019021816A - Multilayer ceramic capacitor and method for manufacturing the same - Google Patents

Abstract

To provide a multilayer ceramic capacitor which enables an increase in reliability, and a method for manufacturing the multilayer ceramic capacitor.SOLUTION: A multilayer ceramic capacitor comprises a laminate structure having a generally rectangular parallelepiped shape, in which dielectric layers including a ceramic as a primary component and internal electrode layers are laminated to alternate, and the laminated internal electrode layers are alternately exposed from opposing two end faces. In at least one of end margin areas where the internal electrode layers laminated in the laminate structure and exposed from the same end face are opposed to each other in a state in which the internal electrode layers exposed from the other end face are located therebetween, and side-margin areas provided so as to cover respective ends of the internal electrode layers laminated in the laminate structure and extending to two side faces other than the two opposing end faces, the concentration of a donor element to the primary component ceramic is lower than the concentration of a donor element to the primary component ceramic in the dielectric layers of the laminate structure.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

  In recent years, along with miniaturization of electronic devices such as smartphones and mobile phones, miniaturization of electronic components to be mounted is rapidly progressing. For example, in a multilayer ceramic capacitor, the dielectric layer and the internal electrode layer have been made thinner in order to reduce the chip size while ensuring predetermined characteristics.

  As the dielectric layer is made thinner, the voltage applied to one dielectric layer increases, and the lifetime of the dielectric layer is shortened. As a result, the reliability of the multilayer ceramic capacitor may be reduced. Therefore, a technique for adding a donor element such as Mo (molybdenum), Nb (niobium), Ta (tantalum), or W (tungsten) to the dielectric layer is disclosed (for example, see Patent Documents 1 to 4).

JP 2016-127120 A JP-A-2006-139720 JP 2017-028224 A JP 2017-028225 A

  However, if the donor element concentration in the end margin region or side margin region is high, structural defects may occur due to sintering delay, abnormal grain growth on the chip surface, etc., and as a result, the reliability of the multilayer ceramic capacitor may be reduced. There is.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor that can improve reliability and a method for manufacturing the same.

  In the multilayer ceramic capacitor according to the present invention, dielectric layers mainly composed of ceramic and internal electrode layers are alternately stacked to have a substantially rectangular parallelepiped shape, and the plurality of stacked internal electrode layers are alternately stacked. An end margin region having a laminated structure formed so as to be exposed at two opposing end faces, wherein the internal electrode layers exposed at the same end face in the laminated structure are opposed to each other without the internal electrode layers exposed at different end faces; and The donor for the main component ceramic in at least one of the side margin regions provided so that the plurality of internal electrode layers stacked in the stacked structure cover the end portions extending on the two side surfaces other than the two end surfaces The element concentration is lower than a donor element concentration with respect to a main component ceramic in the dielectric layer of the laminated structure.

  In the multilayer ceramic capacitor, the main component ceramic in the margin region and the main component ceramic in the dielectric layer of the multilayer structure may be barium titanate.

  In the multilayer ceramic capacitor, the donor element may be Mo.

  The method for manufacturing a multilayer ceramic capacitor according to the present invention includes a first step of arranging a first pattern of a metal conductive paste on a green sheet containing main component ceramic particles, and a peripheral region of the metal conductive paste on the green sheet. In addition, a second step of arranging the second pattern including the main component ceramic particles and a stack unit obtained by the second step are obtained by laminating a plurality of layers so that the arrangement positions of the first pattern are alternately shifted. A third step of firing the ceramic laminate, wherein the concentration of the donor element relative to the main component ceramic in the second pattern is lower than the concentration of the donor element relative to the main component ceramic in the green sheet. To do.

  In the method for manufacturing a multilayer ceramic capacitor, the donor element may be Mo.

  In the method for manufacturing a multilayer ceramic capacitor, the Mo concentration with respect to the main component ceramic in the second pattern may be less than 0.2 atm%.

  In the method for manufacturing a multilayer ceramic capacitor, the main component ceramic of the green sheet and the second pattern may be barium titanate.

  According to the present invention, the reliability of the multilayer ceramic capacitor can be improved.

It is a partial section perspective view of a multilayer ceramic capacitor. It is the sectional view on the AA line of FIG. It is the BB sectional view taken on the line of FIG. (A) is an enlarged view of a cross section of a side margin region, and (b) is an enlarged view of a cross section of an end margin region. It is a figure which illustrates the flow of the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows a measurement result.

  Hereinafter, embodiments will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. 2 is a cross-sectional view taken along line AA in FIG. 3 is a cross-sectional view taken along line BB in FIG. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a rectangular parallelepiped shape and external electrodes 20 a and 20 b provided on two opposing end faces of the multilayer chip 10. Of the four surfaces other than the two end surfaces of the multilayer chip 10, two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The external electrodes 20 a and 20 b extend on the upper surface, the lower surface, and the two side surfaces of the multilayer chip 10 in the stacking direction. However, the external electrodes 20a and 20b are separated from each other.

  The multilayer chip 10 has a configuration in which dielectric layers 11 including a ceramic material functioning as a dielectric and internal electrode layers 12 including a base metal material are alternately stacked. The edge of each internal electrode layer 12 is alternately exposed on the end surface of the multilayer chip 10 where the external electrode 20a is provided and the end surface where the external electrode 20b is provided. Thereby, each internal electrode layer 12 is alternately conducted to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are stacked via the internal electrode layer 12. In the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is disposed as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered with the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layer 11 and the ceramic material.

  The size of the multilayer ceramic capacitor 100 is, for example, a length of 0.2 mm, a width of 0.125 mm, and a height of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, a height of 0.2 mm, or a length. 0.6 mm, width 0.3 mm, height 0.3 mm, or length 1.0 mm, width 0.5 mm, height 0.5 mm, or length 3.2 mm, width 1.6 mm, height The length is 1.6 mm, or the length is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm, but is not limited to these sizes.

The internal electrode layer 12 is mainly composed of a base metal such as Ni (nickel), Cu (copper), or Sn (tin). As the internal electrode layer 12, a noble metal such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or an alloy containing these may be used. The dielectric layer 11 includes, for example, a ceramic material having a perovskite structure represented by the general formula ABO ₃ as a main component. Note that the perovskite structure includes ABO _3-α deviating from the stoichiometric composition. For example, as the ceramic material, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), Ba _1-xy which forms a perovskite structure. _{Ca x Sr y Ti 1-z} Zr z O 3 (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) , or the like can be used.

  As illustrated in FIG. 2, a region where the internal electrode layer 12 connected to the external electrode 20 a and the internal electrode layer 12 connected to the external electrode 20 b face each other is a region in which electric capacity is generated in the multilayer ceramic capacitor 100. . Therefore, this area is referred to as a capacity area 14. That is, the capacitance region 14 is a region where two adjacent internal electrode layers 12 connected to different external electrodes face each other.

  A region where the internal electrode layers 12 connected to the external electrode 20a are opposed to each other without the internal electrode layer 12 connected to the external electrode 20b is referred to as an end margin region 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without the internal electrode layer 12 connected to the external electrode 20a is also the end margin region 15. That is, the end margin region 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without the internal electrode layers 12 connected to different external electrodes. The end margin area 15 is an area where no capacity is generated.

  As illustrated in FIG. 3, in the multilayer chip 10, an area from the two side surfaces of the multilayer chip 10 to the internal electrode layer 12 is referred to as a side margin area 16. That is, the side margin region 16 is a region provided so as to cover the end portions of the plurality of internal electrode layers 12 stacked in the stacked structure extending to the two side surfaces. The side margin region 16 is also a region where no capacitance is generated.

  FIG. 4A is an enlarged view of a cross section of the side margin region 16. The side margin region 16 has a structure in which the dielectric layers 11 and the reverse pattern layers 17 are alternately stacked in the stacking direction of the dielectric layers 11 and the internal electrode layers 12 in the capacitor region 14. Each dielectric layer 11 in the capacitance region 14 and each dielectric layer 11 in the side margin region 16 are continuous layers. According to this configuration, a step between the capacitance region 14 and the side margin region 16 is suppressed.

  FIG. 4B is an enlarged view of a cross section of the end margin region 15. In comparison with the side margin region 16, in the end margin region 15, the internal electrode layers 12 extend to the end surface of the end margin region 15 every other one of the plurality of stacked internal electrode layers 12. Further, the reverse pattern layer 17 is not laminated in the layer in which the internal electrode layer 12 extends to the end face of the end margin region 15. Each dielectric layer 11 in the capacitance region 14 and each dielectric layer 11 in the end margin region 15 are continuous layers. According to this configuration, a step between the capacitance region 14 and the end margin region 15 is suppressed.

The dielectric layer 11 is obtained, for example, by firing a raw material powder of a main component ceramic having a perovskite structure. Since the raw material powder is exposed to a reducing atmosphere during firing, oxygen defects occur in the main component ceramic. Therefore, it is conceivable to replace the B site of the perovskite structure represented by ABO ₃ and add Mo, Nb, Ta, W or the like that functions as a donor to the dielectric layer 11. By adding the donor element to the dielectric layer 11, the generation of oxygen defects in the main component ceramic is suppressed. As a result, the lifetime characteristics of the dielectric layer 11 are improved, reliability is improved, a high dielectric constant is obtained, and good bias characteristics are obtained. However, when a large amount of donor element is also added to the reverse pattern layer 17, abnormal grain growth on the surface of the multilayer chip 10 due to promotion of grain growth of the main component ceramic, and densification are hindered by the influence thereof. Structural defects resulting from the sintering delay occur. Alternatively, when a large amount of donor element is also added to the reverse pattern layer 17, grain growth of the reverse pattern layer 17 is promoted, resulting in structural defects due to the spheroidization of the internal electrode layer 12 in the vicinity of the reverse pattern layer 17. As a result, the reliability of the multilayer ceramic capacitor 100 may be reduced. For example, moisture resistance becomes insufficient due to the inhibition of the densification. Due to the structural defects resulting from the spheroidization, problems such as an increase in the short-circuit rate, a decrease in life, and a decrease in withstand voltage (BDV) are caused.

  Therefore, in the present embodiment, the donor element concentration with respect to the main component ceramic in the reverse pattern layer 17 is set lower than the Mo concentration with respect to the main component ceramic in the dielectric layer 11. In this configuration, abnormal grain growth and sintering delay on the surface of the multilayer chip 10 are suppressed, and structural defects are suppressed. As a result, the reliability of the multilayer ceramic capacitor 100 is improved.

  Note that the concentration of the donor element relative to the main component ceramic in the entire end margin region 15 and side margin region 16 (hereinafter sometimes referred to as a margin region) due to the diffusion of the donor element during firing is such that the dielectric of the capacitor region 14 It becomes lower than the donor element concentration with respect to the main component ceramic in the layer 11.

If the amount of the donor element in the reverse pattern layer 17 is too large, abnormal grain growth and sintering delay on the surface of the multilayer chip 10 may not be sufficiently suppressed. Therefore, it is preferable to set an upper limit on the donor element concentration in the reverse pattern layer 17. In the present embodiment, as an example, when Mo is used as the donor element, the Mo concentration with respect to the main component ceramic in the reverse pattern layer 17 is preferably less than 0.2 atm%, and is preferably 0.1 atm% or less. More preferred. The concentration (atm%) is a concentration when the B site of the main component ceramic having a perovskite structure represented by the general formula ABO ₃ is 100 atm%. The same shall apply hereinafter.

  In the present embodiment, the donor element concentration relative to the main component ceramic in both the end margin region 15 and the side margin region 16 is lower than the donor element concentration relative to the main component ceramic in the dielectric layer 11 in the capacitor region 14. Yes, but not limited to that. For example, the donor element concentration with respect to the main component ceramic in any one of the margin regions may be lower than the donor element concentration with respect to the main component ceramic in the dielectric layer 11 in the capacitor region 14.

  Then, the manufacturing method of the multilayer ceramic capacitor 100 is demonstrated. FIG. 5 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A site element and the B site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO ₃ particles. For example, BaTiO ₃ is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO ₃ can be generally obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. As a method for synthesizing the ceramic constituting the dielectric layer 11, various methods are conventionally known, and for example, a solid phase method, a sol-gel method, a hydrothermal method, and the like are known. Any of these may be employed in the present embodiment.

  A predetermined additive compound is added to the obtained ceramic powder according to the purpose. As additive compounds, Mo, Nb, Ta, W, Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium) , Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), and Co (cobalt), Ni, Li (lithium), B (Boron), Na (sodium), K (potassium) and Si (silicon) oxide or glass. In the present embodiment, at least one of the donor elements is added to the obtained ceramic powder.

  In the present embodiment, preferably, first, the ceramic particles constituting the dielectric layer 11 are mixed with a compound containing an additive compound and calcined at 820 to 1150 ° C. Subsequently, the obtained ceramic particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic powder. For example, the average particle diameter of the ceramic powder is preferably 50 to 300 nm from the viewpoint of thinning the dielectric layer 11. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification treatment to adjust the particle size.

  Next, a reverse pattern material for forming the end margin region 15 and the side margin region 16 is prepared. Depending on the purpose, a predetermined additive compound is added to the barium titanate ceramic powder obtained by the same process as that for producing the dielectric material. Examples of the additive compound include Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Na, Examples include K and Si oxides or glasses. In the present embodiment, the donor element is not added or the amount of the donor element added is reduced as compared with the dielectric material.

  In the present embodiment, preferably, a compound containing an additive compound is first mixed with ceramic particles constituting the end margin region 15 and the side margin region 16 and calcined at 820 to 1150 ° C. Subsequently, the obtained ceramic particles are wet-mixed with an additive compound, dried and pulverized to prepare a ceramic powder. For example, the average particle size of the ceramic powder is preferably 50 to 300 nm in accordance with the dielectric material. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification treatment to adjust the particle size.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer such as dioctyl phthalate (DOP) are added to the obtained dielectric material and wet mixed. Using the obtained slurry, for example, a band-shaped dielectric green sheet having a thickness of 0.8 μm or less is applied on a substrate by, for example, a die coater method or a doctor blade method and dried.

Next, internal electrodes that are alternately drawn out to a pair of external electrodes having different polarities by printing a metal conductive paste containing an organic binder on the surface of the dielectric green sheet by screen printing, gravure printing, or the like. A layer pattern (first pattern) is arranged. Ceramic particles are added as a co-material to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. For example, BaTiO ₃ having an average particle diameter of 50 nm or less may be uniformly dispersed.

  Next, an ethyl cellulose-based binder and a terpineol-based organic solvent were added to the reverse pattern material and kneaded by a roll mill to obtain a reverse pattern paste. On the dielectric green sheet, a reverse pattern (second pattern) is arranged by printing a reverse pattern paste in a peripheral region where the internal electrode layer pattern is not printed, thereby filling a step with the internal electrode layer pattern.

  Thereafter, the dielectric green sheet on which the internal electrode layer pattern and the reverse pattern are printed is punched to a predetermined size, and the punched dielectric green sheet is peeled off from the internal electrode layer 12 and the dielectric. The internal electrode layers 12 are alternately drawn out to a pair of external electrodes 20a and 20b having different polarities so that the edges of the internal electrode layers 12 are alternately exposed at both end surfaces in the length direction of the dielectric layer 11 so that the layers 11 are alternated. As described above, a predetermined number of layers (for example, 100 to 500 layers) are stacked. A cover sheet to be the cover layer 13 is pressure-bonded to the upper and lower sides of the laminated dielectric green sheets, cut into a predetermined chip size (for example, 1.0 mm × 0.5 mm), and then a metal conductive paste to be the external electrodes 20a and 20b is applied. Then, it is applied to both sides of the cut laminate by a dip method and dried. Thereby, a molded body of the multilayer ceramic capacitor 100 is obtained.

(Baking process)
The molded body thus obtained was subjected to binder removal treatment in an N ₂ atmosphere at 250 to 500 ° C., and then at 1100 to 1300 ° C. for 10 minutes in a reducing atmosphere having an oxygen partial pressure of 10 ⁻⁵ to 10 ⁻⁸ atm. By firing for 2 hours, each compound sinters and grows. In this way, the multilayer ceramic capacitor 100 is obtained.

(Reoxidation process)
It may then be subjected to re-oxidizing treatment at 600 ° C. to 1000 ° C. in _{an N 2} gas atmosphere.
(Plating process)
Thereafter, a metal coating such as Cu, Ni, or Sn may be applied to the external electrodes 20a and 20b by plating.

  According to the manufacturing method according to the present embodiment, the donor element concentration with respect to the main component ceramic in the reverse pattern material is lower than the donor element concentration with respect to the main component ceramic in the dielectric material. In this case, in the firing step, abnormal grain growth and sintering delay on the surface of the multilayer chip 10 are suppressed, and structural defects are suppressed. As a result, the reliability of the multilayer ceramic capacitor 100 is improved.

  If the amount of the donor element in the reverse pattern material is too large, there is a possibility that abnormal grain growth and sintering delay on the surface of the laminated chip 10 are not sufficiently suppressed. Therefore, it is preferable to set an upper limit on the donor element concentration in the reverse pattern material. In the present embodiment, as an example, when Mo is used as the donor element, the Mo concentration with respect to the main component ceramic in the reverse pattern material is preferably less than 0.2 atm%, more preferably 0.1 atm% or less. Preferably, it is more preferably zero.

  Hereinafter, the multilayer ceramic capacitor according to the embodiment was produced, and the characteristics were examined.

(Examples 1 and 2)
(Production of dielectric material)
For barium titanate powder (average particle size 0.15 μm) 100 atm%, Ho concentration is 0.4 atm%, Mn concentration is 0.2 atm%, V concentration is 0.1 atm%, Si concentration is 0.6 atm%, Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₅ , SiO ₂ , and MoO ₃ were weighed so that the Mo concentration was 0.2 atm%, and sufficiently wet mixed and pulverized with a ball mill to obtain a dielectric material.

(Production of reverse pattern material)
In Example 1, the Ho concentration is 0.4 atm%, the Mn concentration is 2 atm%, the V concentration is 0.1 atm%, and the Si concentration is 2 atm% with respect to 100 atm% of the barium titanate powder (average particle size 0.15 μm). , Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₅ , SiO ₂ , and B ₂ O ₃ were weighed so that the B concentration was 0.3 atm%. In Example 2, MoO ₃ was weighed so that the Mo concentration was 0.1 atm%. Thereafter, the mixture was sufficiently wet-mixed and pulverized with a ball mill to obtain a reverse pattern material.

(Preparation of reverse pattern paste)
The reverse pattern paste was obtained by adding ethyl cellulose type as an organic binder and terpineol type as a solvent to the reverse pattern material and kneading with a roll mill.

(Production of multilayer ceramic capacitor)
A green sheet was prepared by adding butyral as an organic binder and toluene and ethyl alcohol as solvents to the dielectric material, so that the thickness of the dielectric layer 11 after sintering was 0.8 μm by a doctor blade method. An internal electrode forming paste was screen-printed on the obtained sheet to form an internal electrode, and a reverse pattern paste was screen-printed on a portion without the internal electrode to fill the steps of the internal electrode. 250 printed sheets were stacked, and 30 μm of cover sheets were stacked on the top and bottom. Then, the laminated body was obtained by thermocompression bonding and cut into a predetermined shape. A Ni external electrode is formed on the obtained laminate by a dip method, and after a binder removal treatment in an N ₂ atmosphere, firing is performed at 1250 ° C. in a reducing atmosphere (O ₂ partial pressure: 10 ⁻⁵ to 10 ⁻⁸ atm). Thus, a sintered body was obtained. The shape dimensions were 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height. The sintered body was subjected to a re-oxidation treatment under a N ₂ atmosphere at 800 ° C., and then plated, and the surface of the external electrode terminal was coated with Cu, Ni, and Sn to obtain a multilayer ceramic capacitor. Note that, after firing, the thickness of the Ni internal electrode was 1.0 μm.

(Comparative Example 1)
In Comparative Example 1, in the process of producing the reverse pattern material, the Ho concentration is 0.4 atm%, the Mn concentration is 2 atm%, and the V concentration is 0 with respect to 100 atm% of the barium titanate powder (average particle diameter 0.15 μm). 0.1 atm%, Si concentration at 2 atm%, B concentration at 0.3 atm%, and Mo concentration at 0.2 atm%, Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₅ , SiO ₂ , B ₂ O ₃ And MoO ₃ were weighed. Other conditions were the same as in Example 1.

(Comparative Example 2)
In Comparative Example 2, in the step of manufacturing the dielectric material, the Ho concentration is 0.4 atm%, the Mn concentration is 0.2 atm%, and V is 100 atm% of the barium titanate powder (average particle diameter 0.15 μm). Ho ₂ O ₃ , MnCO ₃ , V ₂ O ₅ and SiO ₂ were weighed so that the concentration was 0.1 atm% and the Si concentration was 0.6 atm%, and no Mo source was added. Other conditions were the same as in Example 1.

(analysis)
HALT (Highly Accelerated Limit Test) defect rate and capacity acquisition rate were measured for Examples 1 and 2 and Comparative Examples 1 and 2. In the measurement of the HALT defect rate, 125 ° C-12Vdc-120min-100 HALT tests are performed, a short defect rate of less than 5% is accepted (◯), 5% or more and less than 10% is △, and 10% or more. Was rejected (x). In measuring the capacity acquisition rate, the capacity was measured with an LCR meter. This measured value and the dielectric constant of the dielectric material (preparing a disk-shaped sintered body of φ = 10 mm × T = 1 mm using only the dielectric material and measuring the capacitance to calculate the dielectric constant) The design values calculated from the crossing area, the dielectric ceramic layer thickness, and the number of laminated layers were compared, and those having a capacity acquisition rate (measured value / design value × 100) of 95% to 105% were determined to be acceptable (◯).

  FIG. 6 is a diagram showing the measurement results. In FIG. 6, the “margin” column shows the average value of the dielectric material and the reverse pattern material because the dielectric material and the reverse pattern material are alternately laminated in the margin region. In Comparative Example 1, the HALT defect rate increased to 31%. This is presumably because structural defects occurred due to abnormal grain growth on the surface of the multilayer chip 10 and sintering delay due to the addition of a large amount of Mo to the reverse pattern material. Next, also in Comparative Example 2, the HALT defect rate increased to 50%. This is presumably because the lifetime of the dielectric layer 11 could not be increased because Mo was not added to the dielectric material. In contrast, in both Examples 1 and 2, the HALT defect rate was less than 10%. This is because the Mo concentration with respect to the main component ceramic in the reverse pattern material is made lower than the Mo concentration with respect to the main component ceramic in the dielectric material, so that the lifetime of the dielectric layer 11 becomes longer and abnormalities on the surface of the multilayer chip 10 occur. This is probably because grain growth and sintering delay were suppressed and structural defects were suppressed. The Mo concentration relative to the main component ceramic in the entire margin region after firing was lower than the Mo concentration relative to the main component ceramic in the dielectric layer 11 in the capacitor region 14.

  Next, the HALT defect rate of Example 1 was lower than that of Example 2. This is presumably because the Mo concentration with respect to the main component ceramic in the margin region became lower because Mo was not added to the reverse pattern material in Example 1.

  In Comparative Examples 1 and 2, the capacity acquisition rate varied compared to Examples 1 and 2. In Comparative Example 1, the capacity acquisition rate was low. This is considered to be because Mo growth promoted grain growth in the vicinity of the side margin, and Ni at the end of the internal electrode was spheroidized (continuity decreased), resulting in a decrease in capacity acquisition rate. In Comparative Example 2, the capacity acquisition rate was high. This is presumably because Mo for promoting grain growth was not added in Comparative Example 2, and the relative dielectric constant slightly increased due to the decrease in the total amount of additives.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Multilayer chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitance area | region 15 End margin area | region 16 Side margin area | region 17 Reverse pattern layer 20a, 20b External electrode 100 Multilayer ceramic capacitor

Claims (7)

Dielectric layers mainly composed of ceramics and internal electrode layers are alternately stacked so as to have a substantially rectangular parallelepiped shape, and the plurality of stacked internal electrode layers are exposed on two opposing end surfaces. With a formed laminated structure,
In the laminated structure, the internal electrode layers exposed at the same end face are opposed to each other without the internal electrode layers exposed at different end faces, and the plurality of internal electrode layers laminated in the laminated structure are the two end faces. Among the side margin regions provided so as to cover the end portions extending to the other two side surfaces, the donor element concentration with respect to the main component ceramic in at least one margin region is set to the main component ceramic in the dielectric layer of the multilayer structure. A multilayer ceramic capacitor having a lower concentration than a donor element.   2. The multilayer ceramic capacitor according to claim 1, wherein the main component ceramic of the margin region and the main component ceramic of the dielectric layer of the multilayer structure are barium titanate.   The multilayer ceramic capacitor according to claim 1, wherein the donor element is Mo. A first step of disposing a first pattern of a metal conductive paste on a green sheet containing main component ceramic particles;
A second step of disposing a second pattern containing main component ceramic particles in a peripheral region of the metal conductive paste on the green sheet;
A third step of firing a ceramic laminate obtained by laminating a plurality of lamination units obtained in the second step so that the arrangement positions of the first patterns are alternately shifted, and
A method for manufacturing a multilayer ceramic capacitor, wherein a concentration of a donor element with respect to a main component ceramic in the second pattern is lower than a concentration of a donor element with respect to the main component ceramic in the green sheet.   The method for producing a multilayer ceramic capacitor according to claim 4, wherein the donor element is Mo.   The method for manufacturing a multilayer ceramic capacitor according to claim 5, wherein the Mo concentration in the second pattern with respect to the main component ceramic is less than 0.2 atm%.   The method for producing a multilayer ceramic capacitor according to claim 4, wherein the green sheet and the main ceramic component of the second pattern are barium titanate.

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