JP2019021798A - Photoelectric conversion device, manufacturing method of photoelectric conversion device, imaging system, and moving body - Google Patents

Abstract

To provide a photoelectric conversion device with more reduced noise.SOLUTION: A photoelectric conversion device includes a pixel for generating a signal by photoelectric conversion, a capacitive element having a first terminal and a second terminal and holding a signal output from the pixel, and a transistor having a gate electrode connected to the first terminal or a source or a drain connected to the first terminal, and a silicide spaced apart from at least a part of its outer edge is provided on one of a first semiconductor region constituting the first terminal, a gate electrode of the transistor, and a second semiconductor region constituting the source or the drain.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a photoelectric conversion device, a method for manufacturing a photoelectric conversion device, an imaging system, and a moving body.

  Patent Document 1 discloses a structure of a MOS (Metal-Oxide-Semiconductor) transistor used as an electrostatic protection element. The MOS transistor has a source / drain region, a gate electrode formed above the source / drain region, and a sidewall formed on a side surface of the gate electrode. A first silicide film formed at a predetermined distance from the sidewall is formed on the upper surface of the source / drain region, and a predetermined distance from the sidewall is formed on the upper surface of the gate electrode. The formed second silicide film is formed. According to Patent Document 1, it is described that this configuration improves resistance against electrostatic breakdown due to diffusion resistance of the source / drain regions.

JP 2011-222955 A

  Patent Document 1 does not disclose that the MOS transistor is applied to uses other than the electrostatic protection element. In a MOS transistor or the like in which a silicide film is formed on an impurity diffusion region or on an electrode, the potential barrier of the insulating layer is lowered due to thermal diffusion of silicide, and a leak current due to a tunnel effect can occur. When such a leakage current is generated in the output circuit of the photoelectric conversion device, noise such as vertical shading may be a problem. In view of the above, an object of the present invention is to provide a photoelectric conversion device, a method for manufacturing the photoelectric conversion device, an imaging system, and a moving body with further reduced noise.

  According to one aspect of the present invention, a pixel that generates a signal by photoelectric conversion, a capacitor that has a first terminal and a second terminal, and holds a signal output from the pixel; and the first A gate electrode connected to a terminal, or a transistor having a source or a drain connected to the first terminal, and a first semiconductor region constituting the first terminal, a gate electrode of the transistor, And a photoelectric conversion device comprising: a silicide disposed on at least one of the second semiconductor regions constituting the source or the drain and spaced apart from at least a part of an outer edge thereof. The

  According to another aspect of the present invention, there is provided a step of forming a pixel that generates a signal by photoelectric conversion, and a capacitive element that has a first terminal and a second terminal and holds a signal output from the pixel Forming a gate electrode connected to the first terminal, or forming a transistor having a source or a drain connected to the first terminal, the first terminal being Silicide disposed on at least one of the first semiconductor region constituting the transistor, the gate electrode of the transistor, and the second semiconductor region constituting the source or the drain and spaced apart from at least a part of the outer edge thereof A method for manufacturing a photoelectric conversion device is provided.

  It is possible to provide a photoelectric conversion device in which noise is further reduced, a method for manufacturing the photoelectric conversion device, an imaging system, and a moving body.

1 is a block diagram of a solid-state imaging device according to a first embodiment of the present invention. 1 is a circuit diagram of an output circuit according to a first embodiment of the present invention. 1 is a schematic plan view of an output circuit according to a first embodiment of the present invention. It is a cross-sectional schematic diagram of the output circuit which concerns on 1st Embodiment of this invention. It is a plane schematic diagram of the output circuit which concerns on 2nd Embodiment of this invention. It is a cross-sectional schematic diagram of the output circuit which concerns on 2nd Embodiment of this invention. It is a plane schematic diagram of the output circuit which concerns on 3rd Embodiment of this invention. It is a cross-sectional schematic diagram of the output circuit which concerns on 3rd Embodiment of this invention. It is a plane schematic diagram of the output circuit which concerns on 4th Embodiment of this invention. It is a cross-sectional schematic diagram of the output circuit which concerns on 4th Embodiment of this invention. It is a plane schematic diagram of the output circuit which concerns on 5th Embodiment of this invention. It is a cross-sectional schematic diagram of the output circuit which concerns on 5th Embodiment of this invention. It is a block diagram of the imaging system concerning a 6th embodiment of the present invention. It is a figure which shows the structural example of the imaging system and moving body which concern on 7th Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Corresponding elements are denoted by common reference numerals throughout the drawings, and the description thereof may be omitted or simplified.

[First Embodiment]
FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device 1 according to the present embodiment. A solid-state imaging device 1 shown in FIG. 1 is a kind of photoelectric conversion device that converts incident light into an electrical signal by photoelectric conversion, and is, for example, a CMOS (Complementary-MOS) image sensor. The solid-state imaging device 1 includes a plurality of pixels 10, a vertical scanning circuit 13, a control circuit 14, a column circuit 15, a horizontal transfer circuit 18, a horizontal scanning circuit 19, and an output circuit 20.

  The plurality of pixels 10 are arranged to form a plurality of rows and a plurality of columns. Each of the pixels 10 outputs a signal corresponding to incident light by photoelectric conversion. In each row of the plurality of pixels 10, a control signal line 11 extending in the row direction (lateral direction in FIG. 1) is arranged. The control signal lines 11 are respectively connected to the pixels 10 arranged in the row direction, and form a common signal line for these pixels 10. Further, a vertical output line 12 extending in the column direction (vertical direction in FIG. 1) is arranged in each column of the plurality of pixels 10. The vertical output lines 12 are respectively connected to the pixels 10 arranged in the column direction, and form a common signal line for these pixels 10.

  The control signal line 11 of each row is connected to the vertical scanning circuit 13. The vertical scanning circuit 13 is a circuit unit that supplies a control signal for driving a circuit in the pixel 10 to the pixel 10 via the control signal line 11 when a pixel signal is read from the pixel 10. One end of the vertical output line 12 of each column is connected to the column circuit 15. The column circuit 15 includes a column amplifier circuit 16 and a column holding circuit 17 provided for each column of the plurality of pixels 10. The pixel signal read from the pixel 10 is input to the column amplifier circuit 16 via the vertical output line 12. The column amplifier circuit 16 is a circuit unit that performs signal processing such as amplification processing on the pixel signal read from the pixel 10. The column holding circuit 17 holds the signal output from the column amplifier circuit 16. The column holding circuit 17 may include a sample hold circuit and the like.

  The horizontal transfer circuit 18 is a circuit unit that sequentially transfers the pixel signals held in the column holding circuit 17 to the output circuit 20 for each column. The horizontal scanning circuit 19 is a circuit unit that outputs a control signal for controlling the transfer operation of the horizontal transfer circuit 18. The control circuit 14 is a circuit unit for supplying control signals for controlling operations and timings of the vertical scanning circuit 13, the column circuit 15, the horizontal scanning circuit 19, the output circuit 20, and the like. The output circuit 20 is a circuit unit for outputting the pixel signal output from the horizontal transfer circuit 18 to a signal processing unit outside the solid-state imaging device 1.

  FIG. 2 is a block diagram showing a schematic configuration of the output circuit 20 according to the present embodiment. The output circuit 20 includes MOS transistors 24, 27 and 29, current sources 25 and 26, and a clamp capacitor 28. The pixel signal output from the horizontal transfer circuit 18 is input to the input terminal 21 that is the gate node of the MOS transistor 24.

  The power supply voltage VDD is input to the drain of the MOS transistor 24. The source of the MOS transistor 24 is a node N1, and one end of a current source 25 and a clamp capacitor 28 is connected to the node N1. This node is called a node N1. The other end of the clamp capacitor 28 is connected to the source of the MOS transistor 29 and the gate of the MOS transistor 27. A control signal output from the control circuit 14 is input to the gate of the MOS transistor 29 via the control terminal 22. The clamp voltage Vc is input to the drain of the MOS transistor 29. When the MOS transistor 29 is turned on, the potential of the node N2 between the clamp capacitor 28, the source of the MOS transistor 29, and the gate of the MOS transistor 27 is initialized to a voltage based on the clamp voltage Vc.

  The power supply voltage VDD is input to the drain of the MOS transistor 27, and the current source 26 is connected to the source of the MOS transistor 27. The source node of the MOS transistor 27 forms the output terminal 23 and is connected to the output terminal OUT of the solid-state imaging device 1.

  A signal input to the input terminal 21 of the output circuit 20 is amplified by the MOS transistor 24 and the current source 25 functioning as a source follower, and input to one end of the clamp capacitor 28. At this time, the clamp capacitor 28 holds a signal corresponding to the voltage between the node N1 and the node N2. The signal held in the clamp capacitor 28 is amplified by the MOS transistor 27 and the current source 26 that function as a source follower, and is output from the output terminal 23. Here, since the MOS transistor 29 operates so as to be turned on once per frame period, the potential of the node N2 is held for a maximum of one frame period.

  FIG. 3 is a schematic plan view of a circuit corresponding to the region 30 shown in FIG. 2 in the output circuit 20. 4 is a schematic cross-sectional view taken along line AB of FIG. The element structure of the output circuit 20 according to the present embodiment will be described along the manufacturing process with reference to FIGS. 3 and 4.

  A P-type well region 402 is formed on the N-type semiconductor substrate 401 by ion implantation. Capacitance elements and MOS transistors 27 and 29 constituting the clamp capacitor 28 shown in FIG. 2 are formed on the P-type well region 402. The active regions 102 forming these elements are electrically isolated by element isolation regions 403 and 404. The element isolation regions 403 and 404 can be, for example, STI (Shallow Trench Isolation) formed of silicon oxide or the like.

  An N-type impurity diffusion region 111 that functions as a first terminal of the clamp capacitor 28 is formed in the well region 402 by performing ion implantation of N-type impurities. An insulating film 108 that functions as a dielectric layer of the clamp capacitor 28 is formed on the impurity diffusion region 111. At the same time, insulating films 210 and 308 functioning as gate insulating films for forming the MOS transistors 29 and 27 are formed on the well region 402. Polysilicon electrodes 101, 201, and 301 are formed on the insulating films 108, 210, and 308, respectively. The electrode 101 functions as a second terminal of the clamp capacitor 28. The electrodes 201 and 301 function as gate electrodes of the MOS transistors 29 and 27, respectively.

  Impurity diffusion regions 103, 207, 202, and 302 are formed by ion implantation of N-type impurities at a low concentration after the electrodes 101, 201, and 301 are formed. The impurity diffusion regions 207 and 202 are main electrodes of the MOS transistor 29 and function as drains and sources. The impurity diffusion region 302 is a main electrode of the MOS transistor 27 and functions as a drain or a source.

  The pattern of the impurity diffusion regions 103, 207, 202, 302 is defined by self-alignment with the pattern of the electrodes 101, 201, 301 and element isolation regions 403, 404. Thereafter, by etching back the silicon oxide film deposited by CVD (Chemical Vapor Deposition) or the like, sidewalls 109, 208, 211, and 306 are formed on the side surfaces of the electrodes. Thereafter, N-type impurity ions are implanted again into the impurity diffusion regions 103, 207, 202, and 302. As described above, the outer edges of the impurity diffusion regions 103, 207, 202, and 302 are defined by the boundaries between the impurity diffusion regions 103, 207, 202, and 302 and the element isolation regions 403 and 404 or the sidewalls 109, 208, 211, and 306. At least a portion thereof is defined. The outer edges of the electrodes 101, 201, 301 are at least partially defined by the boundaries with the sidewalls 109, 208, 211, 306.

  Next, a silicide film is formed on the impurity diffusion regions 103, 207, 202, and 302. First, silicide blocks 105, 204, and 304 shown in FIG. 3 are formed. The silicide blocks 105, 204, and 304 are, for example, silicon oxide films. In FIG. 4, the silicide block 105 is formed in the regions 105a and 105b, the silicide block 204 is formed in the regions 204a and 204b, and the silicide block 304 is formed in the region 304a. In FIG. 4, the silicide blocks 105, 204, and 304 are not shown.

  After the formation of the silicide blocks 105, 204, and 304, a metal film is deposited, and heat treatment is performed to form silicide films 110, 206, and a combination of silicon and metal films on the impurity diffusion regions 103, 207, 202, and 302. 212 and 305 are formed. Further, silicide films 107, 209, and 307 are formed on the electrodes 101, 201, and 301, respectively. At this time, the metal film on the silicide blocks 105, 204, and 304 is not silicided. Therefore, by performing a process such as wet etching to selectively remove the non-silicided metal film, the silicide films 110, 206, 212, 305, 107, 209, and 307 are only in regions where the silicide blocks 105, 204, 304 are not present. Is formed. The metal film used in this process is, for example, cobalt, and in this case, the above-described silicide film is cobalt silicide.

  Thereafter, contacts 104, 205, 203, and 303 made of tungsten or the like as a main material are formed on the silicide films 110, 206, 212, and 305, respectively. The contacts 104, 205, 203, and 303 electrically connect the silicide films 110, 206, 212, and 305 and the wiring layer. Note that contacts are similarly formed on the silicide films 107, 209, and 307. Similarly, contacts are formed on the electrodes 101, 201, and 301. The contact 106 on the electrode 101 is electrically connected to the node N1.

  When thermal diffusion of silicide occurs at the interface between a semiconductor such as silicon and an insulator such as silicon oxide, the potential barrier is lowered, and a leakage current due to the tunnel effect may occur. If a leak current is generated at a node holding charge such as the node N2 of the output circuit 20, it may cause noise such as vertical shading. On the other hand, the silicide film 110 formed on the impurity diffusion region 103 (first semiconductor region) constituting the first terminal of the clamp capacitor 28 has an element isolation region 403 (first region) adjacent to the impurity diffusion region 103. 1 element isolation region). Therefore, thermal diffusion of silicide hardly occurs at the interface between the impurity diffusion region 103 and the element isolation region 403, and the leakage current of the path from the impurity diffusion region 103 to the element isolation region 403 is reduced. Therefore, according to the present embodiment, noise of a photoelectric conversion device such as a solid-state imaging device can be further reduced.

  Further, the silicide film 110 formed on the impurity diffusion region 103 is also separated from the sidewall 109 (first sidewall) formed on the side surface of the electrode 101 as shown in FIG. Therefore, the leakage current of the path from the impurity diffusion region 103 to the sidewall 109 is also reduced.

  Further, the silicide film 107 formed on the electrode 101 is separated from the sidewall 109 as shown in FIG. Therefore, the leakage current of the path from the electrode 101 to the sidewall 109 is also reduced.

  As shown in FIG. 3, the silicide block 105 for forming the gap is arranged so as to surround the contact 104 in a plan view with respect to the surface of the semiconductor substrate 401. As a result, the leakage current can be reduced more reliably.

  Further, as shown in FIG. 4, the silicide film 212 formed on the impurity diffusion region 202 (second semiconductor region) has an element isolation region 404 (second element) adjacent to the impurity diffusion region 202. Separated from the separation region). The silicide film 212 is also separated from the sidewall 211 (second sidewall) formed on the side surface of the electrode 201. Therefore, the leakage current of the path from the impurity diffusion region 202 to the element isolation region 404 and the sidewall 211 is also reduced.

  Further, the silicide film 209 formed on the electrode 201 which is a control terminal is separated from the sidewall 211 as shown in FIG. Therefore, the leakage current of the path from the electrode 201 to the sidewall 211 is also reduced.

  As shown in FIG. 3, the silicide block 204 for forming a gap is arranged so as to surround the contact 203 in a plan view with respect to the surface of the semiconductor substrate 401. As a result, the leakage current can be reduced more reliably.

  Further, the silicide film 305 formed on the impurity diffusion region 302 is separated from the sidewall 306 as shown in FIG. Therefore, the leakage current of the path from the impurity diffusion region 302 to the sidewall 306 is also reduced.

  Further, the silicide film 307 formed on the electrode 301 is separated from the sidewall 306 (third sidewall) as shown in FIG. Therefore, the leakage current of the path from the electrode 301 to the sidewall 306 is also reduced.

  As described above, in this embodiment, at least the node N2 of the output circuit 20 blocks the leakage current path so that no silicide film is formed at the interface between the semiconductor (silicon) or the electrode (polysilicon) and the insulator. It has a configuration. Thereby, the amount of leakage current generated from node N2 can be less than 1 picoampere. In this case, the level of vertical shading caused by the charge flowing out from the node N2 can be set to 1 LSB (Least Significant Bit) or less within one frame period.

[Second Embodiment]
FIG. 5 is a schematic plan view of a circuit corresponding to the region 30 shown in FIG. 2 in the output circuit 20. FIG. 6 is a schematic cross-sectional view taken along line CD in FIG. 3 and 4 of the first embodiment is that the silicide blocks 204 and 304 are not provided.

  As shown in FIG. 6, since the silicide block 204 is not provided, the space between the silicide film 212 and the sidewall 211, the space between the silicide film 212 and the element isolation region 404, and the space between the silicide film 209 and the sidewall 211 are shown. The structure is not separated. Further, since the silicide block 304 is not provided, there is a structure in which neither the silicide film 305 and the sidewall 306 nor the silicide film 307 and the sidewall 306 are separated from each other.

  In the present embodiment, by not forming the silicide blocks 204 and 304, the element area can be reduced as compared with the first embodiment. Compared with the first embodiment, the number of paths in which leakage current occurs increases, but in this embodiment as well, the amount of leakage current generated from the node N2 can be less than 1 picoampere. Therefore, the level of vertical shading caused by the electric charge flowing out from the node N2 can be set to 1 LSB or less within one frame period.

[Third Embodiment]
FIG. 7 is a schematic plan view of a circuit corresponding to the region 30 shown in FIG. 2 in the output circuit 20. FIG. 8 is a schematic cross-sectional view taken along line EF in FIG. 3 and 4 of the first embodiment is that the silicide blocks 105 and 304 are not provided.

  As shown in FIG. 8, since the silicide block 105 is not provided, there is a gap between the silicide film 110 and the sidewall 109, between the silicide film 110 and the element isolation region 403, and between the silicide film 107 and the sidewall 109. The structure is not separated. Further, since the silicide block 304 is not provided, there is a structure in which neither the silicide film 305 and the sidewall 306 nor the silicide film 307 and the sidewall 306 are separated from each other.

  In the present embodiment, by not forming the silicide blocks 105 and 304, the element area can be reduced as compared with the first embodiment. Compared with the first embodiment, the number of paths in which leakage current occurs increases, but in this embodiment as well, the amount of leakage current generated from the node N2 can be less than 1 picoampere. Therefore, the level of vertical shading caused by the electric charge flowing out from the node N2 can be set to 1 LSB or less within one frame period.

[Fourth Embodiment]
FIG. 9 is a schematic plan view of a circuit corresponding to the region 30 shown in FIG. 2 in the output circuit 20. 10 is a schematic cross-sectional view taken along line GH in FIG. 3 and 4 of the first embodiment is that the silicide blocks 105 and 204 are not provided.

  As shown in FIG. 10, since the silicide block 105 is not provided, the silicide film 110 and the side wall 109, the silicide film 110 and the element isolation region 403, and the silicide film 107 and the side wall 109 are separated from each other. It becomes a structure that does not. Further, since the silicide block 204 is not provided, the silicide film 212 and the sidewall 211, the silicide film 212 and the element isolation region 404, and the silicide film 209 and the sidewall 211 are not separated from each other.

  In the present embodiment, by not forming the silicide blocks 105 and 204, the element area can be reduced compared to the first embodiment. Compared with the first embodiment, the number of paths in which leakage current occurs increases, but in this embodiment as well, the amount of leakage current generated from the node N2 can be less than 1 picoampere. Therefore, the level of vertical shading caused by the electric charge flowing out from the node N2 can be set to 1 LSB or less within one frame period.

[Fifth Embodiment]
FIG. 11 is a schematic plan view of a circuit corresponding to the region 30 shown in FIG. 2 in the output circuit 20. 12 is a schematic cross-sectional view taken along the line I-J in FIG. 3 and 4 of the first embodiment is that the shape of the silicide block 105c is different from the corresponding silicide block 105 of the first embodiment.

  In the present embodiment, as shown in FIG. 11, the shape of the silicide block 105c is different from that of the first embodiment. Thus, as shown in FIG. 12, the silicide film 110 and the element isolation region 403 are not separated from each other. Thereby, an element area can be reduced compared with 1st Embodiment. Compared with the first embodiment, the number of paths in which leakage current occurs increases, but in this embodiment as well, the amount of leakage current generated from the node N2 can be less than 1 picoampere. Therefore, the level of vertical shading caused by the electric charge flowing out from the node N2 can be set to 1 LSB or less within one frame period.

[Sixth Embodiment]
An imaging system according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a block diagram illustrating a schematic configuration of the imaging system according to the present embodiment.

  The solid-state imaging device 1 described in the first to fifth embodiments described above can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and the like. A camera module including an optical system such as a lens and the solid-state imaging device 1 is also included in the imaging system. FIG. 13 illustrates a block diagram of a digital still camera as an example of these.

  An imaging system 500 illustrated in FIG. 13 includes a solid-state imaging device 1, a lens 502 that forms an optical image of a subject on the solid-state imaging device 1, a diaphragm 504 that changes the amount of light passing through the lens 502, and protection of the lens 502. A barrier 506 is provided. The lens 502 and the stop 504 are an optical system that focuses light on the solid-state imaging device 1. The solid-state imaging device 1 is the solid-state imaging device 1 described in the first to fifth embodiments, and converts an optical image formed by the lens 502 into image data.

  The imaging system 500 also includes a signal processing unit 508 that processes an output signal output from the solid-state imaging device 1. The signal processing unit 508 performs AD conversion that converts an analog signal output from the solid-state imaging device 1 into a digital signal. In addition, the signal processing unit 508 performs an operation of outputting image data after performing various corrections and compressions as necessary. The AD conversion unit that is a part of the signal processing unit 508 may be formed on a semiconductor substrate on which the solid-state imaging device 1 is provided, or may be formed on a semiconductor substrate different from the solid-state imaging device 1. . Further, the solid-state imaging device 1 and the signal processing unit 508 may be formed on the same semiconductor substrate.

  The imaging system 500 further includes a buffer memory unit 510 for temporarily storing image data, and an external interface unit (external I / F unit) 512 for communicating with an external computer or the like. Further, the imaging system 500 includes a recording medium 514 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 516 for recording or reading to the recording medium 514. Have Note that the recording medium 514 may be built in the imaging system 500 or may be detachable.

  The imaging system 500 further includes an overall control / arithmetic unit 518 that controls various calculations and the entire digital still camera, and a timing generation unit 520 that outputs various timing signals to the solid-state imaging device 1 and the signal processing unit 508. Here, the timing signal or the like may be input from the outside, and the imaging system 500 only needs to include at least the solid-state imaging device 1 and the signal processing unit 508 that processes the output signal output from the solid-state imaging device 1.

  The solid-state imaging device 1 outputs an imaging signal to the signal processing unit 508. The signal processing unit 508 performs predetermined signal processing on the imaging signal output from the solid-state imaging device 1 and outputs image data. The signal processing unit 508 generates an image using the imaging signal.

  By applying the solid-state imaging device 1 according to the first to fifth embodiments, it is possible to realize an imaging system 500 that can acquire a high-quality image.

[Seventh Embodiment]
An imaging system and a moving body according to a seventh embodiment of the present invention will be described with reference to FIGS. 14 (a) and 14 (b). FIG. 14A and FIG. 14B are diagrams illustrating the configuration of the imaging system 600 and the moving body according to the present embodiment.

  FIG. 14A shows an example of an imaging system 600 relating to an in-vehicle camera. The imaging system 600 includes the solid-state imaging device 1. The solid-state imaging device 1 is the solid-state imaging device 1 according to any one of the first to fifth embodiments described above. The imaging system 600 includes an image processing unit 612 that performs image processing on a plurality of image data acquired by the solid-state imaging device 1, and parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 600. A parallax calculation unit 614 that calculates The imaging system 600 also calculates a distance measurement unit 616 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 618 that determines whether there is a collision possibility based on the calculated distance. And having. Here, the parallax calculation unit 614 and the distance measurement unit 616 are an example of a distance information acquisition unit that acquires distance information about an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 618 may determine the possibility of collision using any of these distance information. The distance information acquisition unit may be realized by hardware designed exclusively, or may be realized by a software module. Further, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

  The imaging system 600 is connected to a vehicle information acquisition device 620 and can acquire vehicle information such as a vehicle speed, a yaw rate, and a steering angle. In addition, the imaging system 600 is connected to a control ECU 630 that is a control device that outputs a control signal for generating a braking force for the vehicle based on a determination result in the collision determination unit 618. That is, the control ECU 630 is an example of a moving body control unit that controls the moving body based on the distance information. The imaging system 600 is also connected to an alarm device 640 that issues an alarm to the driver based on the determination result in the collision determination unit 618. For example, when the possibility of a collision is high as a determination result of the collision determination unit 618, the control ECU 630 performs vehicle control to avoid a collision and reduce damage by applying a brake, returning an accelerator, or suppressing an engine output. The alarm device 640 warns the user by sounding an alarm such as a sound, displaying alarm information on a screen of a car navigation system, or applying vibration to the seat belt or steering.

  In the present embodiment, the imaging system 600 images the periphery of the vehicle, for example, the front or rear. FIG. 14B shows an imaging system when imaging the front of the vehicle (imaging range 650). The vehicle information acquisition device 620 sends an instruction to the imaging system 600 or the solid-state imaging device 1 so as to perform a predetermined operation. With such a configuration, the accuracy of distance measurement can be further improved.

  Although an example of controlling so as not to collide with other vehicles has been described, the present invention can also be applied to control for automatically driving following other vehicles, control for automatically driving so as not to protrude from the lane, and the like. Furthermore, the imaging system is not limited to a vehicle such as the host vehicle, but can be applied to a moving body (moving device) such as a ship, an aircraft, or an industrial robot. In addition, the present invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent road traffic systems (ITS).

[Modified Embodiment]
The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

  Further, the location where the configuration of the silicide film of the above-described embodiment can be used is not limited to the output circuit 20. For example, the present invention can be applied to a capacitor element and a MOS transistor provided in the column holding circuit 17 in the column circuit 15 or the like. When the storage capacitor, the reset circuit, and the source follower circuit are formed in the column holding circuit 17, the silicide film of the above-described embodiment is applied to the storage capacitor electrode, the reset circuit MOS transistor, and the input MOS transistor of the source follower circuit. A configuration can be used. As described above, the present invention can be applied to a circuit other than the circuits described in the above embodiments as long as a leakage current from a node connected to the capacitor element can be generated.

  The present invention is applicable not only to a solid-state imaging device but also to any photoelectric conversion device including a focus detection device that does not mainly acquire an image. When the photoelectric conversion device is used for focus detection, noise can be reduced by reducing leakage current, and the effect of improving focus detection accuracy can be obtained.

  The names of the source and drain of the MOS transistor described in the above embodiment may differ depending on the conductivity type of the MOS transistor, the function of interest, etc., and all or part of the above-mentioned source and drain are opposite names. Sometimes called.

  The imaging systems shown in the sixth and seventh embodiments are examples of the configuration of an imaging system to which the solid-state imaging device 1 of the present invention can be applied. Imaging that can be applied to the solid-state imaging device of the present invention. The system is not limited to the configuration shown in FIGS.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 Solid-state imaging device 10 Pixel 27, 29 MOS transistor 28 Clamp capacitance 101, 201, 301 Electrode 103, 202, 302 Impurity diffusion region 110, 212, 307 Silicide film 403, 404 Element isolation region

Claims (10)

A pixel that generates a signal by photoelectric conversion;
A capacitive element having a first terminal and a second terminal and holding a signal output from the pixel;
A gate electrode connected to the first terminal, or a transistor having a source or a drain connected to the first terminal,
On at least one of the first semiconductor region constituting the first terminal, the gate electrode of the transistor, and the second semiconductor region constituting the source or the drain, separated from at least a part of the outer edge thereof. Having silicide arranged
A photoelectric conversion device characterized by that. The silicide disposed on the first semiconductor region constituting the first terminal;
A first element isolation region that is disposed adjacent to the first semiconductor region and electrically isolates the first semiconductor region from other semiconductor regions;
2. The photoelectric conversion device according to claim 1, wherein a boundary between the first semiconductor region and the first element isolation region forms at least a part of an outer edge of the first semiconductor region. The silicide disposed on the first semiconductor region constituting the first terminal;
The capacitive element further includes an electrode constituting the second terminal, and a first sidewall disposed on a side surface of the electrode,
The photoelectric conversion device according to claim 1, wherein a boundary between the first semiconductor region and the first sidewall forms at least a part of an outer edge of the first semiconductor region. The silicide disposed on the second semiconductor region constituting the source or the drain;
A second element isolation region that is disposed adjacent to the second semiconductor region and electrically isolates the second semiconductor region from other semiconductor regions;
4. The boundary according to claim 1, wherein a boundary between the second semiconductor region and the second element isolation region forms at least a part of an outer edge of the second semiconductor region. 5. Photoelectric conversion device. The silicide disposed on the second semiconductor region constituting the source or the drain;
The transistor has a second sidewall disposed on a side surface of the gate electrode;
5. The boundary according to claim 1, wherein a boundary between the second semiconductor region and the second sidewall forms at least a part of an outer edge of the second semiconductor region. Photoelectric conversion device. The silicide disposed on the gate electrode of the transistor;
The transistor further includes a third sidewall disposed on a side surface of the gate electrode,
6. The photoelectric conversion device according to claim 1, wherein a boundary between the gate electrode and the third sidewall forms at least a part of an outer edge of the gate electrode. A contact disposed on the silicide;
7. The photoelectric conversion device according to claim 1, wherein a region for separating the outer edge and the silicide is disposed so as to surround the contact in a plan view. The photoelectric conversion device according to any one of claims 1 to 7,
An image pickup system comprising: a signal processing unit that processes a signal output from the photoelectric conversion device. A moving object,
The photoelectric conversion device according to any one of claims 1 to 7,
Distance information acquisition means for acquiring distance information about an object from a parallax image based on a signal from the photoelectric conversion device;
And a moving body control means for controlling the moving body based on the distance information. Forming a pixel that generates a signal by photoelectric conversion;
Forming a capacitor element having a first terminal and a second terminal and holding a signal output from the pixel;
Forming a gate electrode connected to the first terminal, or a transistor having a source or drain connected to the first terminal, and
On at least one of the first semiconductor region constituting the first terminal, the gate electrode of the transistor, and the second semiconductor region constituting the source or the drain, separated from at least a part of the outer edge thereof. A method for manufacturing a photoelectric conversion device, comprising: a silicide arranged as a first step.

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