JP2019017189A - Power conversion device - Google Patents

Abstract

To accurately detect a current flowing through a semiconductor switching element constituting a 2-in-1 module.SOLUTION: A power conversion device comprises a first semiconductor driving device 30 and a second semiconductor driving device 50. The first semiconductor driving device drives a 2-in-1 configuration semiconductor switching element 11 of a semiconductor power module. The second semiconductor driving device drives a 2-in-1 configuration semiconductor element 21 of the semiconductor power module. The first semiconductor driving device comprises a gate voltage control circuit 32 which supplies a gate driving signal to the semiconductor switching element, a filters 33 which outputs a zero value when the detection voltage detected by an emitter signal terminal is less than a predetermined value and outputs the detection voltage when the detection voltage exceeds the predetermined value, and an integration circuits 34 which outputs an output value obtained by integrating a filter output. The second semiconductor driving device comprises a gate voltage control circuit 52 which supplies a gate driving signal to the semiconductor switching element, a filter 53 which outputs a zero value when the detection voltage detected by the emitter signal terminal is less than the predetermined value and outputs the detection voltage when the detection voltage exceeds the predetermined value, and an integration circuit 54 which outputs an output value obtained by integrating a filter output. The first and second semiconductor driving devices protect an overcurrent on the basis of outputs of the integration circuits.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a power conversion device using a semiconductor drive device equipped with a protection function.

  Power conversion devices such as inverters realize power conversion by switching operation of a semiconductor power module (hereinafter sometimes abbreviated as “module”). As a typical example of the semiconductor switching element in the semiconductor power module, a voltage-driven semiconductor element such as a MOSFET or an IGBT is widely used. In particular, IGBTs capable of high-speed switching and capable of controlling large power are used in a wide range of fields from small capacity inverters for home appliances to large capacity inverters for railways and the like.

  In a semiconductor power module, an antiparallel connection circuit (referred to as an “arm”) of a semiconductor switching element and a diode is generally used. The arm connected between the positive terminal and the AC terminal is called the upper arm, and the arm connected between the AC terminal and the negative terminal is called the lower arm. A pair of upper and lower arms can output AC power for one phase. Therefore, three sets of upper and lower arms are required to output a three-phase alternating current.

  In order to control such a semiconductor switching element, a semiconductor drive device that provides a drive signal to the semiconductor switching element is required. In general, a semiconductor drive device for a voltage-driven semiconductor switching element has a function of controlling the conduction state (ON state) of the semiconductor switching element by applying a voltage to the gate of the semiconductor switching element.

  When a semiconductor switching element is used for an inverter or the like, a short circuit protection function is often provided in order to prevent element damage due to an arm short circuit or a load short circuit. The arm short circuit is a phenomenon in which the semiconductor switching elements of the upper and lower arms are simultaneously turned on, and the positive and negative power supplies are short-circuited. Load short-circuiting is a phenomenon in which a load connected to an inverter or the like is short-circuited, and the positive and negative power supplies are short-circuited via a semiconductor switching element that is turned on. When these short circuits occur, an excessive current flows through the semiconductor switching element, causing the semiconductor switching element to break down.

  Such a short circuit is generally classified into three short-circuit modes of Type I to Type III depending on the conduction state of the semiconductor power module when the short circuit occurs (Non-patent Document 1).

  The Type I short circuit is a short circuit that occurs when the self-arm element is turned on. Considering the upper and lower arms of an inverter as an example, this occurs in a situation where the arm device is broken and remains conductive while the arm is turned off and the arm is turned on in that state. When Type I is short-circuited, the collector current of its own arm increases to the saturation current of the IGBT due to the short-circuit, while the collector-emitter voltage varies with the electromotive voltage generated by the product of the parasitic inductance of the main circuit and the rate of increase of the main current. To do. At this time, a displacement current flows from the collector to the gate via the feedback capacitor. For this reason, the gate voltage temporarily rises to about the power supply voltage.

  In Type II short-circuiting, the IGBT of the own arm is in a gate-on state, and the off-arm element that is turned off may be suddenly destroyed and short-circuited while the collector current is flowing. In this Type II short circuit, since the short circuit occurs in the gate-on state, the current change rate is larger than the Type I short circuit limited by the element characteristics, and is limited by the parasitic inductance of the main circuit.

  As a result, the collector current increases rapidly, resulting in a shorter short circuit than the Type I short circuit. Further, in the Type II short-circuit, the collector-emitter voltage increases rapidly, so that the displacement current flows into the gate via the feedback capacitance, the gate voltage rises, and the saturation current further increases.

  In Type III short-circuiting, as in Type II short-circuiting, it is a mode of short-circuiting when the gate of the IGBT of its own arm is turned on, but the point of short-circuiting when the diode connected in reverse parallel to the IGBT is conducting is Type II. Different from short circuit.

  As an example, there may be a case where the off-arm pair is suddenly broken and short-circuited in a state where the diode of the self-arm carries a reflux current and the gate of the IGBT of the self-arm is on. Also in this case, since the short circuit occurs in the gate-on state, the rate of change in current increases as in the Type II short circuit, resulting in a severe short circuit.

  It is desirable to provide a short circuit protection circuit in the semiconductor drive device in order to protect the self arm element from secondary damage when a short circuit occurs due to destruction or false firing of the anti-arm element. Generally, a short circuit protection circuit observes the current and voltage of a semiconductor switching element, and when they exceed a predetermined value, it takes measures to limit or cut off the current of the semiconductor switching element. It is something to protect.

  In the overcurrent protection circuit, current detection means for detecting the current flowing through the semiconductor switching element in the semiconductor power module is required.

  Generally, when using short-circuit detection means for high-voltage inverters used in electric railways, etc., there is a false detection due to noise, i.e., an event that erroneously detects that the short-circuit is not short-circuited but stops the inverter. May occur. In order to avoid such an event, generally, high-frequency noise that occurs during switching by a low-pass filter and low-frequency noise by a high-pass filter are removed. In addition, in order to avoid erroneous detection due to the recovery current generated when the switching operation is turned on, the overcurrent protection circuit has a filtering time, that is, a function that starts the protection operation by detecting that the short circuit has continued for a certain period of time. have.

  By the way, the power conversion device is installed together with other devices in a limited space under the vehicle floor in an electric railway vehicle, and in a limited space in a hood in an electric vehicle. Is required. When the semiconductor power module is downsized, the main terminals through which the main current flows, the control terminals that connect the semiconductor drive device, the conductors that make up the detection terminals that output voltage signals to detect abnormal conditions such as overcurrent, and the terminals In addition, wiring conductors for connecting these terminals and the semiconductor switching elements are arranged close to each other. Therefore, the magnetic flux generated by the main current flowing through the terminals (conductors) and the wiring conductors affects each terminal and each wiring conductor.

  On the other hand, in Patent Document 1, in order to cope with the influence of the magnetic flux as described above, a current flowing through the semiconductor switching element is detected in consideration of a mutual inductance generated between each terminal and each wiring conductor. Technology is disclosed.

Japanese Patent Application Laid-Open No. 2006-66974

Jorg Schumann, et al. "Influence of the Gate Drive on the Short-Circuit Type II and Type III Behavior of HV-IGBT," PCIM 2010, pp. 709-714

  As described above, there is a module having a so-called 2-in-1 configuration in order to reduce the size of the semiconductor power module. With 2in1, one semiconductor power module has two arms consisting of an anti-parallel circuit of IGBT (or power MOSFET etc.) and a diode, and the two arms are connected in series in the module, and a pair of upper and lower An arm series circuit is configured. According to Patent Document 1, the current flowing through the upper arm can be detected by detecting the voltage generated in the wiring between the emitter signal terminal of the upper arm and the emitter main terminal of the upper arm. Further, the current flowing through the lower arm can be detected by detecting the voltage generated in the wiring between the emitter signal terminal of the lower arm and the emitter main terminal of the lower arm.

  FIG. 1 shows an equivalent circuit diagram of a main circuit of a semiconductor power module using a general 2-in-1 module. In FIG. 1, the mutual inductance which acts between wiring (conductor) in a module is typically represented. As shown in FIG. 1, an upper arm 10 and a lower arm 20 made of an anti-parallel circuit of an IGBT and a diode are connected in series. A gate voltage is supplied to a gate signal terminal G of the upper arm 10 from a semiconductor drive device (not shown), and a gate voltage is supplied to a gate signal terminal G of the lower arm 20 from a semiconductor drive device (not shown).

  The semiconductor power module including the upper arm 10 and the lower arm 20 includes a self-inductance L1 of the wiring conductor between the positive terminal P and the collector of the upper arm 10, an emitter signal terminal S of the upper arm 10, the upper arm 10 and the lower arm 20. The self-inductance L2 of the wiring conductor between the connection midpoints is provided. Further, the self-inductance L3 between the connection midpoint of the upper arm 10 and the lower arm 20 and the collector of the lower arm 20, and the self-inductance L4 of the wiring conductor between the emitter signal terminal S and the negative terminal N of the lower arm 20 are represented. Have. Further, it has a self-inductance L5 of the wiring conductor between the connection midpoint of the upper arm 10 and the lower arm 20 and the AC terminal AC.

In the 2-in-1 module as described above, for example, the voltage generated in the wiring between the negative electrode terminal N and the emitter signal terminal S of the lower arm 20 is L1-L4 mutual inductance M14, L2 in addition to the self-inductance L4 of the wiring conductor. -L4 mutual inductance M24, L3-L4 mutual inductance M34, and L4-L5 mutual inductance M45. Further, when the current change rate dI _H / dt of the upper arm 10, the current change rate dI _L / dt of the lower arm 20, and the current change rate dI _AC / dt of the wiring of the AC terminal AC are generated in the self-inductance L 4. The voltage VL4 can be expressed as VL4 = (M14 + M24) · dI _H / dt + (L4 + M34) · dI _L / dt + M45 · dI _AC / dt.

At the time of a short circuit or when the switching operation is turned on / off, the rate of change is reversed in the upper arm 10 and the lower arm 20, and current changes of the same magnitude (rate of change) occur. DI _AC = 0, dI _H / dt = dI _{Since L} / dt, VL4 = (M14 + M24 + M34 + L4) · dI _H (or dI _L ) / dt. Similarly, the voltage VL2 generated in the emitter-side wiring of the upper arm 10 is VL2 = (M12 + M23 + M24 + L2) · dI _H (or dI _L ) / dt. The effective inductance value generated in the wiring conductor, taking into account the mutual inductance, can be obtained by prior calculations and measurements and treated as a constant. Therefore, in the event of short-circuiting or turn-on / off of the switching operation, the current change rate dI / dt of each arm can be detected by measuring the voltage generated in the wiring, and further by the integration of the detected dI / dt. Current can be detected.

  However, in a conductive state where the current flows only to one arm in the 2 in 1 module, or in a reflux state, the current change rate of the wiring conductor of the AC terminal AC is equal to the current change rate of the arm where the current flows, but no current flows. In the arm, the current change rate dI / dt is zero. As an example, an equivalent circuit of a main circuit and a schematic diagram of a current waveform when double pulse switching is performed by connecting a load inductance in parallel to the upper arm 10 are shown in FIGS.

  FIG. 2 shows an equivalent circuit of the main circuit when a load inductance L6 is connected in parallel to the upper arm 10 of the semiconductor power module. FIG. 3 shows current waveforms of the upper arm 10 and the lower arm 20 in the equivalent circuit of FIG.

  As shown in FIG. 2, a load inductance L6 is connected to the positive terminal P and the AC terminal AC. Further, FIG. 3 shows the time change (1) of the lower arm command, the time change (2) of the lower arm gate voltage, the time change (3) of the upper arm current, and the time change (4) of the lower arm current. . For example, as shown in (1) of FIG. 3, when a turn-on command and a turn-off command are input to the semiconductor drive device to the lower arm 20, a gate voltage as shown in (2) of FIG. G is supplied. It becomes the threshold voltage Vth or more after a predetermined time of the turn-on command, and becomes the threshold voltage Vth or less after the predetermined time of the turn-off command. Here, only the command and gate voltage for the lower arm 20 are described for convenience.

In such a situation, for example, when only the lower arm 20 is conducting or refluxing, the voltage VL4 generated in the emitter-side wiring of the lower arm 20 is VL4 = (L4 + M34 + M45) · dI _L / dt (FIG. 3 ( 4)). When no current is flowing through the lower arm 20 and only the upper arm 10 is conducting or refluxing, VL4 = (M14 + M24 + M45) · dI _H / dt, and a voltage is generated even when no current flows through the own arm. I understand that At this time, I _L / dt and dI _H / dt slightly change in the upper arm 10 and the lower arm 20, respectively ((3) and (4) in FIG. 3). As described above, there are three states: a state where only the own arm is conducting or refluxing (mode 1), a state where only the opposite arm is conducting or refluxing (mode 2), and a short circuit or turn-on / turn-off (mode 3). Effective inductance values acting on the wiring in the operation mode are different.

  In order to accurately detect the current including the current during conduction and recirculation, a current detection circuit corresponding to the effective inductance value of each of the above three operation modes is required. There is a problem that the configuration becomes complicated.

  In addition, in order to eliminate the influence of the current arm or the pair arm during conduction or reflux, a measure to limit the operation period of the current detection circuit only to before and after the gate is turned on can be considered. It is not possible to cope with Type II short-circuit and Type III short-circuit generated due to the destruction of the pair of arms.

  The present invention was devised in view of the above-described situation, and provides a power conversion device using a semiconductor drive device having a short-circuit protection function capable of accurately detecting a current flowing through a semiconductor switching element constituting a 2-in-1 module. For the purpose.

In order to solve the above problems, one aspect of a power conversion device of the present invention includes a semiconductor power module and a semiconductor drive device that drives the semiconductor power module.
The semiconductor power module has a first main terminal and a second main terminal which are a pair of DC terminals, a first main electrode and a second main electrode, and the first main electrode is the first main terminal. A first semiconductor switching element electrically connected to the second main electrode, a third main electrode and a fourth main electrode, wherein the fourth main electrode is electrically connected to the second main terminal. And a semiconductor switching element. The semiconductor power module is electrically connected to a connection point between the second main electrode of the first semiconductor switching element and the third main electrode of the second semiconductor switching element that are electrically connected in series. AC terminal is provided. Further, the semiconductor power module includes a first signal terminal for detecting the potential of the second main electrode, and a second signal terminal for detecting the potential of the connection point between the first semiconductor switching element and the second semiconductor switching element. And a third signal terminal for detecting the potential of the fourth main electrode, and a fourth signal terminal for detecting the potential of the second main terminal.
The semiconductor drive device is composed of a first semiconductor drive device and a second semiconductor drive device. The first semiconductor drive device includes a first gate voltage control circuit for supplying a gate drive signal to the first semiconductor switching element, and a first detection voltage detected at the second signal terminal is less than a predetermined value. A zero value is sometimes output, and a first filter that outputs the first detection voltage when the first detection voltage exceeds a predetermined value and an output value obtained by integrating the output of the first filter are output. And an overcurrent protection of the first semiconductor switching element based on the output of the first integration circuit.
Similarly, the second semiconductor drive device includes a second gate voltage control circuit that supplies a gate drive signal to the second semiconductor switching element, and a second detection voltage detected at the fourth signal terminal is a predetermined value. A second filter that outputs a zero value when the second detection voltage exceeds a predetermined value and an output value obtained by integrating the output of the second filter. A third integrating circuit for outputting, and overcurrent protection of the second semiconductor switching element is performed based on the output of the third integrating circuit.

According to at least one aspect of the present invention, it is possible to accurately detect a short-circuit current and a switching current of a 2-in-1 module, and thus it is possible to reliably interrupt the short-circuit current.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is an equivalent circuit diagram of the main circuit of the semiconductor power module using a general 2 in 1 module. It is an equivalent circuit diagram of the main circuit when a load inductance is connected in parallel to the upper arm of the semiconductor power module. It is explanatory drawing which shows the current waveform of the upper arm and lower arm in the equivalent circuit of FIG. 1 is a block diagram illustrating a basic configuration example of a semiconductor power module and a semiconductor drive device according to a first embodiment of the present invention. It is explanatory drawing which shows the electric current detection signal of a semiconductor power module in case the filter is not provided between the 2nd signal terminal and the 1st integration circuit (conventional example). It is explanatory drawing which shows the electric current detection signal of the semiconductor power module which concerns on the 1st Embodiment of this invention. It is explanatory drawing which shows the electric current detection signal of a semiconductor power module in the case of providing a high pass filter between the 2nd signal terminal and the 1st integration circuit (comparative example). FIG. 3 is an equivalent circuit diagram showing a specific example of the basic configuration of the semiconductor drive device according to the first embodiment of the present invention. FIG. 6 is an equivalent circuit diagram showing a modification of the specific example of the basic configuration of the semiconductor drive device according to the first embodiment of the present invention. It is an equivalent circuit diagram which shows the other specific example of the basic composition of the semiconductor drive device which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the basic structural example of the semiconductor drive device which concerns on the 2nd Embodiment of this invention. It is an equivalent circuit diagram which shows the specific example of the basic composition of the semiconductor drive device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the basic structural example of the semiconductor drive device which concerns on the 3rd Embodiment of this invention. It is an equivalent circuit diagram which shows the specific example of the basic composition of the semiconductor drive device which concerns on the 3rd Embodiment of this invention. It is a schematic waveform diagram which shows the example of the time change of the gate voltage at the time of gate voltage reduction. It is a schematic waveform diagram which shows the example of the time change of the arm current at the time of gate voltage reduction. It is a block diagram which shows the basic structural example of the semiconductor drive device which concerns on the 4th Embodiment of this invention. It is an equivalent circuit diagram which shows the specific example of the basic composition of the semiconductor drive device which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the basic structural example of the power converter device which concerns on the 5th Embodiment of this invention.

Hereinafter, an example of an embodiment for carrying out the present invention will be described with reference to the accompanying drawings. The description will be given in the following order. In the accompanying drawings, components having substantially the same function or configuration are denoted by the same reference numerals, and redundant description is omitted. The attached drawings show specific embodiments and implementation examples based on the principle of the present invention, but these are for understanding the present invention and are not intended to limit the present invention. Not used.
1. 1st Embodiment (example provided with the filter which cuts low level detection voltage)
2. Second Embodiment (Example provided with a gate voltage comparison circuit and a time constant switching circuit)
3. Third embodiment (example including a gate voltage reduction circuit)
4). Fourth embodiment (example using a Zener diode as a gate voltage adjusting circuit)
5. Fifth Embodiment (Example in which a semiconductor drive device is applied to a power converter)

<1. First Embodiment>
[Functional configuration of power converter]
FIG. 4 is a block diagram showing a basic configuration example (for a short circuit protection function) of the semiconductor power module having the 2-in-1 configuration and the semiconductor drive device according to the first embodiment of the present invention. In the first embodiment, an IGBT is described as an example of a semiconductor switching element, but the present invention is not limited to this, and can be applied to other general semiconductor switching elements.

  The semiconductor power module shown in FIG. 4 is composed of upper and lower arms composed of an upper arm 10 and a lower arm 20 connected in series. The upper arm 10 (an example of a power semiconductor element) includes an anti-parallel circuit of an IGBT 11 that is a first semiconductor switching element and a diode 12, and the lower arm 20 (an example of a power semiconductor element) is a second semiconductor switching element. It consists of an antiparallel circuit of an IGBT 21 and a diode 22. The semiconductor power module including the upper arm 10 and the lower arm 20 has a first main terminal 1 as a positive electrode terminal, a second main terminal 2 as a negative electrode terminal, and an AC terminal 3.

  The IGBT 11 has a first main electrode 13 (collector) and a second main electrode 14 (emitter), and the first main electrode 13 is electrically connected to the first main terminal 1. The IGBT 21 has a third main electrode 23 (collector) and a fourth main electrode 24 (emitter), and the fourth main electrode 24 is electrically connected to the second main terminal 2. The IGBT 11 and the IGBT 21 are connected in series by the second main electrode 14 and the third main electrode 23 being electrically connected by a conductor. The AC terminal 3 is electrically connected to the series connection point of the IGBT 11 and the IGBT 21.

  Further, regarding the IGBT 11, the first gate signal terminal 4, the first signal terminal 5 as an emitter signal terminal for detecting the potential of the second main electrode 14, and the change rate of the current flowing through the wiring parasitic inductance and the semiconductor power module. Is provided with a second signal terminal 6 for detecting a first detection voltage (the potential of the AC terminal 3) output in response thereto. Further, regarding the IGBT 21, the second signal signal terminal 7, the third signal terminal 8 as an emitter signal terminal for detecting the potential of the fourth main electrode 24, and the wiring parasitic inductance and the change rate of the current flowing in the semiconductor power module. A fourth signal terminal 9 for detecting the second detection voltage (the potential of the second main terminal 2) output in response is provided. The first signal terminal 5 and the third signal terminal 8 are grounded.

  The semiconductor power module including the upper arm 10 and the lower arm 20 includes a self-inductance L1 of a wiring conductor between the first main terminal 1 and the collector of the upper arm 10, an emitter signal terminal S of the upper arm 10, and the upper arm 10. It has a self-inductance L2 of the wiring conductor between the connection midpoint of the lower arm 20. The self-inductance L3 between the connection midpoint of the upper arm 10 and the lower arm 20 and the collector of the lower arm 20, and the self of the wiring conductor between the emitter signal terminal S of the lower arm 20 and the second main terminal 2 It has an inductance L4. Furthermore, it has a self-inductance L5 of the wiring conductor between the connection midpoint of the upper arm 10 and the lower arm 20 and the AC terminal 3.

  A gate drive signal (gate voltage) is supplied from the first semiconductor drive device 30 to the first gate signal terminal 4 of the upper arm 10, and the second semiconductor drive device 50 is supplied to the second gate signal terminal 7 of the lower arm 20. A gate drive signal (gate voltage) is supplied from.

(First semiconductor driving device)
The first semiconductor drive device 30 includes a first gate drive command unit 31, a first gate voltage control circuit 32, a first filter 33, a first integration circuit 34, a first switch 35, and a first output. A comparison circuit 36, a second integration circuit 37, and a first cutoff command unit 38 are provided.

  The first gate drive command unit 31 outputs a drive command to the first gate voltage control circuit 32 based on the drive command input signal SIN input from the higher-order logic unit.

  The first gate voltage control circuit 32 supplies a gate drive signal (gate voltage) to the IGBT 11 based on the drive command input from the first gate drive command unit 31.

  The first filter 33 is electrically connected to the second signal terminal 6. The first filter 33 filters a first detection voltage having an absolute value smaller than a predetermined value in order to remove a minute signal generated at the second signal terminal 6. That is, the first filter 33 sets the zero value to the first value when the first detection voltage output between the first signal terminal 5 and the second signal terminal 6 is less than the first predetermined value. The first detection voltage is output to the first integration circuit 34 when the first detection voltage is equal to or higher than the first predetermined value. In the present embodiment, the first filter 33 determines whether or not the potential (first detection voltage) detected at the second signal terminal 6 is not less than a predetermined value other than during a short circuit or turn-on / turn-off. .

  The first integration circuit 34 integrates the signal that has passed through the first filter 33 and detects the current flowing between the collector and emitter of the IGBT 11.

  The first switch 35 operates the first integration circuit 34 only during a predetermined period, and resets the output value of the first integration circuit 34 during other periods. For example, the first switch 35 resets the output of the first integrating circuit 34 and keeps it at a zero value except during a short circuit or turn-on / turn-off.

  When the output of the first integration circuit 34 exceeds a predetermined value, the first output comparison circuit 36 determines that the IGBT 11 is in an overcurrent state, and sends a signal according to the determination result to the second integration circuit 37. Output.

  The second integration circuit 37 integrates the signal output from the first output comparison circuit 36 and detects a period in which the IGBT 11 is in an overcurrent state. The second integration circuit 37 outputs the integration result to the first cutoff command unit 38. Although the determination accuracy of the overcurrent state is improved by providing the second integration circuit 37, the overcurrent protection function can be realized without the second integration circuit 37.

  The first cutoff command unit 38 outputs a current cutoff command when the output value of the second integration circuit 37 determines that the IGBT 11 is in a short circuit state.

(Second semiconductor driving device)
The second semiconductor drive device 50 includes a second gate drive command unit 51, a second gate voltage control circuit 52, a second filter 53, a third integration circuit 54, a second switch 55, and a second output. A comparison circuit 56, a fourth integration circuit 57, and a second cutoff command unit 58 are provided. The second gate drive command unit 51, the second gate voltage control circuit 52, the second filter 53, the third integration circuit 54, the second switch 55, the second output comparison circuit 56, and the fourth integration The circuit 57 and the second cutoff command unit 58 have the same functions as the respective units of the first semiconductor drive device 30.

  The second gate drive command unit 51 outputs a drive command to the second gate voltage control circuit 52 based on the drive command input signal SIN input from the higher-order logic unit. The drive command input signal SIN input to the second gate drive command unit 51 is a different signal independent of the drive command input signal SIN of the first gate drive command unit 31.

  The second gate voltage control circuit 52 supplies a gate drive signal (gate voltage) to the IGBT 11 based on the drive command input from the second gate drive command unit 51.

  The second filter 53 is electrically connected to the fourth signal terminal 9. The second filter 53 filters a second detection voltage having an absolute value smaller than a predetermined value in order to remove a minute signal generated at the fourth signal terminal 9. That is, the second filter 53 sets the zero value to the third value when the second detection voltage output between the third signal terminal 8 and the fourth signal terminal 9 is less than the second predetermined value. The second detection voltage is output to the third integration circuit 54 when the second detection voltage is equal to or higher than the second predetermined value. In the present embodiment, the second filter 53 determines whether or not the potential (second detection voltage) detected at the fourth signal terminal 9 is not less than a predetermined value other than during a short circuit or turn-on / turn-off. . The first predetermined value and the second predetermined value may be the same.

  The third integration circuit 54 integrates the signal that has passed through the second filter 53 and detects the current that flows between the collector and emitter of the IGBT 21.

  The second switch 55 operates the third integration circuit 54 only during a predetermined period, and resets the output value of the third integration circuit 54 during other periods. For example, the second switch 55 resets the output of the third integrating circuit 54 and keeps it at a zero value except during a short circuit or turn-on / turn-off. The definition of the reset period of the second switch 55 is the same as that of the first switch 35.

  When the output of the third integration circuit 54 exceeds a predetermined value, the second output comparison circuit 56 determines that the IGBT 21 is in an overcurrent state, and sends a signal corresponding to the determination result to the fourth integration circuit 57. Output.

  The fourth integration circuit 57 integrates the signal output from the second output comparison circuit 56 and detects a period during which the IGBT 21 is in an overcurrent state. The fourth integration circuit 57 outputs the integration result to the second cutoff command unit 58. Similar to the second integration circuit 37, by providing the fourth integration circuit 57, the determination accuracy of the overcurrent state is improved. However, the overcurrent protection function can be realized without the fourth integration circuit 57. It is.

  The second cutoff command unit 58 outputs a current cutoff command when the output value of the fourth integration circuit 57 determines that the IGBT 21 is in a short circuit state.

  Of course, the semiconductor drive device according to the present invention can be applied to a case where there are a large number of IGBTs (semiconductor switching elements) which are basic components in parallel (see FIG. 19 as an example).

[Operation of semiconductor drive device]
Next, operations of the first semiconductor drive device 30 and the second semiconductor drive device 50 will be described. Since the operations of the first semiconductor drive device 30 and the second semiconductor drive device 50 are basically the same, the following description will focus on the operation of the first semiconductor drive device 30.

  When the drive command input signal SIN is input from the higher-order logic unit to the first gate drive command unit 31 of the first semiconductor drive device 30, the first gate drive command unit 31 preferably drives the IGBT 11. Process the signal. Based on the result, the first gate voltage control circuit 32 applies a voltage as a gate drive signal to the first gate signal terminal 4 of the IGBT 11 to control the operation of the semiconductor power module.

  Further, when the drive command input signal SIN is input from the higher-order logic unit to the second gate drive command unit 51 of the second semiconductor drive device 50, the second gate drive command unit 51 preferably drives the IGBT 21. To process the signal. Based on the result, the second gate voltage control circuit 52 applies a voltage as a gate drive signal to the second gate signal terminal 7 of the IGBT 21 to control the operation of the semiconductor power module.

Here, it is assumed that the IGBT 21 is destroyed when the IGBT 11 is on, and a short circuit state (Type II short circuit) occurs. At this time, the arm current I _H (collector current) flowing between the collector and the emitter of the IGBT 11 increases, and the arm current I _H enters an overcurrent state. Further, the first signal terminal 6 has a first inductance depending on the mutual inductance value generated between the self-inductance of the conductor through which the main current of the IGBT 11 flows and the adjacent conductor, and the increase rate of the arm current I _H. A detection voltage is generated.

Since the current increase rate at the time of the short circuit is large and the first detection voltage is sufficiently large, the first detection voltage passes through the first filter 33 and is input to the first integration circuit 34. it is possible to detect the current value of the arm current I _H from the output. The function of the first switch 35 for resetting the output of the first integrating circuit 34 at this time is because in the OFF state, there is no concern that it becomes impossible to detect the arm current I _H.

  Further, the output value of the first integration circuit 34 is input to the first output comparison circuit 36 to determine the overcurrent state. When the overcurrent state is established, the first output comparison circuit 36 outputs the second value. A signal is output to the integrating circuit 37. After that, the output of the first output comparison circuit 36 is integrated by the second integration circuit 37, and the second integration is performed only when the integration value reaches a predetermined value, that is, when the overcurrent state continues for a predetermined period. A signal is output from the circuit 37 to the first shutoff command unit 38. Then, a cutoff command is output from the first cutoff command unit 38 to the first gate voltage control circuit 32.

In this way, since the interruption command is output only when the overcurrent state continues for a predetermined period, the risk of erroneous interruption due to noise or the like is reduced. At this time, the second integration circuit 37 has a function as a time filter. When an overcurrent condition continues for a certain period of time, a command to cut off gently reduce arm current I _H from the first shutoff unit 38 to the first gate voltage control circuit 32 is issued, the first semiconductor driving device 30 Can safely cut off the current.

  Next, the first detection voltage during normal switching operation will be described. As an example, attention is focused on the turn-on operation of the upper arm 10 (IGBT 11).

  During the period when the gate of the own arm (upper arm 10) is off, the current flows back in the opposite arm (lower arm 20), and the return current is gradually decreased due to parasitic resistance or the like. Here, the wiring conductor on the opposite arm side and the wiring conductor on the own arm are close to each other, and the mutual inductance due to the wiring conductor on the opposite arm is so large that it cannot be ignored. Therefore, even in a situation where no current flows through the own arm, the second signal terminal 6 of the IGBT 11 has a minute amount according to the rate of change of the current flowing through the paired arm and the mutual inductance of the wiring conductor on the paired arm side. A detection voltage is generated.

  Next, while the gate of the own arm (upper arm 10) is turned on and turned on, the current change in the same direction and the same magnitude in both the wiring conductor of the own arm and the wiring conductor of the opposite arm (lower arm 20). Because the current change rate is large. Therefore, a large detection voltage is generated at the second signal terminal 6 according to the self-inductance of the wiring conductor and the mutual inductance of the wiring conductor of the own arm and the wiring conductor of the opposite arm.

  Next, when the turn-on of the own arm (upper arm 10) is completed and the own arm becomes conductive, a second signal is generated according to the rate of change of the conduction current, the self inductance of the wiring, and the mutual inductance of the own arm wiring conductor. A minute detection voltage is generated at the terminal 6.

  As described above, at the time of switching, the current flow path is different in the three operation modes, that is, return to arm (mode 2), turn-on / turn-off (mode 3), and self-arm conduction (mode 1). As a result, the mutual inductance acting on the wiring conductor is different. Therefore, if the detection voltages in the three operation modes are integrated with the same constant, the accuracy of current detection decreases. This problem can be avoided by changing the circuit constant of the integration circuit in each operation mode in each operation mode, but there are problems such as a significant increase in the number of parts of the semiconductor drive device and a complicated circuit configuration. The present embodiment can solve the above problems with a simple circuit configuration.

  In the first embodiment described above, paying attention to the fact that the detection voltage signal generated during the self-arm conduction and the anti-arm conduction is minute, the detection signal is output when the absolute value of the detection signal is smaller than a predetermined value. The first filter 33 (and the second filter 53) having a function that does not pass is provided. With such a configuration, the detection signal during conduction of the own arm and the conduction of the arm is not input to the first integration circuit 34 (and the third integration circuit 54), and a large detection signal is output at a large current change rate. Only the detection signal at the time of turn-on, turn-off or short circuit can be detected with high accuracy. In the first embodiment, the first switch 35 (and the second switch 55) causes the output of the first integrating circuit 34 (and the third integrating circuit 54) to be given a gate-on command for its own arm. Since it can be reset when not, the risk of erroneous detection of current can be further reduced.

[Effects of First Embodiment]
In the first embodiment described above, the first filter 33 is provided between the second signal terminal 6 and the first integration circuit 34 in the upper arm 10 to cut a signal having a voltage lower than a predetermined value. Yes. Thereby, only a large voltage signal generated at the second signal terminal 6 during turn-on, turn-off, or short-circuit can be detected, so that the turn-on / turn-off current and the short-circuit current can be detected with high accuracy. Therefore, the current (short-circuit current and switching current) flowing through the IGBT (semiconductor switching element) constituting the 2-in-1 module can be accurately detected without significantly increasing the number of parts of the semiconductor drive device and complicating the circuit configuration. Can do. As a result, the short-circuit current can be reliably interrupted, and therefore the semiconductor power module can be reliably protected from overcurrent. In addition, since the current detection accuracy is improved in this embodiment, it is possible to suppress a short-circuit protection margin.

  5 to 7 show the current (1) at the time of turn-on in the switching of the lower arm 20, the first detection voltage (integration circuit input voltage) (2) generated at the second signal terminal 6, and the current detection value. The time change of the integration circuit output (3) as shown in FIG. 5 to 7, the current of the lower arm 20 is indicated by I.

(Conventional current detection signal)
FIG. 5 shows a current detection signal of the semiconductor power module when no filter is provided between the second signal terminal 6 and the first integration circuit 34 (conventional example). During the return of the upper arm 10 before the turn-on, no current flows through the lower arm 20, but the second signal terminal 6 of the upper arm 10 has a return current of the upper arm 10 as shown in FIG. A low level voltage corresponding to the gradual current change rate and the mutual inductance between the wiring self-inductance and the self-arm wiring conductor is detected. This detected signal is input to the first integration circuit 34 as the first detection voltage V _D1 ((2) in FIG. 5).

  Next, when the lower arm 20 starts a turn-on operation, the current flowing through the lower arm 20 rapidly increases and the return current of the upper arm 10 rapidly decreases ((1) in FIG. 5). At this time, the current change rates of the upper and lower arms are opposite and have the same magnitude. Accordingly, the second signal terminal 6 has a voltage corresponding to the rate of change of current, the mutual inductance between the wiring self-inductance and the self-arm wiring conductor, and the mutual inductance between the wiring self-inductance and the arm wiring conductor. It is detected ((2) in FIG. 5).

  Next, when the turn-on operation is completed and the lower arm 20 is in a conductive state, no current flows through the upper arm 10, so that the second signal terminal 6 has a change rate of the conductive current, a self-inductance of wiring, and a self-arm. A low level voltage corresponding to the mutual inductance with the wiring conductor is detected ((2) in FIG. 5). Therefore, when the voltage generated during the upper arm 10 reflux, the turn-on, and the lower arm 20 conduction is integrated with the same circuit constant, as shown in FIG. The error between the current I of the lower arm 20 and the integration circuit output In increases, and the current detection accuracy decreases. For example, because of the error e1 between the current I of the lower arm 20 during the return of the upper arm 10 and the integration circuit output In, the value of the integration circuit output In during the turn-on decreases, and appears as an error e2.

(Current detection signal according to the first embodiment)
FIG. 6 shows a current detection signal of the semiconductor power module according to the first embodiment. By the first filter 33, the first detection voltage having a small voltage value indicated by a broken line during the reflux of the upper arm 10 and the conduction of the lower arm 20 is cut (set to a zero value) and is not input to the first integration circuit 34. ((2) in FIG. 6). The portion exceeding the predetermined value Dr shown in (2) of FIG. 6 is the operating range of the first integration circuit 34. The portion exceeding the predetermined value Dr is a portion exceeding the absolute value of the predetermined value Dr. In the graph of the turn-on period shown in (2) of FIG. 6, the portion below the predetermined value Dr corresponds. Therefore, the first filter 33 can input only the detection signal (first detection voltage V _LCF ) exceeding the predetermined value Dr during the turn-on to the first integration circuit 34 and detect the turn-on current with high accuracy. .

Thereby, as shown in (3) of FIG. 6, an error between the current I of the lower arm 20 and the integration circuit output In hardly occurs during the return of the upper arm 10 and the turn-on. In addition, even when the lower arm 20 is conducting, a slight error is generated between the current I of the lower arm 20 and the integration circuit output _ILCF with a moderate current change rate of the conducting current of the lower arm 20. . As described above, in the first embodiment, the error between the current I of the lower arm 20 and the integration circuit output _ILCF is small, and the current detection accuracy is improved as compared with the conventional example of FIG.

(Current detection signal when high-pass filter is used)
For comparison, FIG. 7 shows a current detection signal of the semiconductor power module when a high-pass filter is provided between the second signal terminal 6 and the first integration circuit 34 (comparative example). Since the detection signal generated during the return of the upper arm 10 or when the own arm (lower arm 20) is conducted is generally lower in frequency than the detection signal generated during turn-on, turn-off, or short-circuit, the upper arm 10 is returned by the high-pass filter. It can be easily imagined that the detection signal (first detection voltage V _HPF ) while the lower arm 20 is conducting is filtered.

However, in the period during which the upper arm 10 returns from the reflux state to the turn-on (part indicated by a one-dot chain line) and the period during which the lower arm 20 transitions from the turn-on to the lower arm 20 conduction state (part indicated by the one-dot chain line). In addition, a component having a high frequency is included in the detected voltage due to the reflux of the lower arm 20 ((2) in FIG. 7). Since this high-frequency detection voltage is input to the first integration circuit 34 together with the detection signal being turned on, the first detection voltage V _HPF is increased by that much, and the current detection accuracy is reduced ( (3) in FIG. As shown in (3) of FIG. 7, the error e3 between the current I of the lower arm 20 and the integration circuit output I _HPF becomes large. In other words, when the integration target of the integration circuit is at the voltage level, if the frequency discrimination is performed by the high-pass filter, the integration may be performed including noise (lower voltage than desired and higher frequency than the cutoff frequency of the high-pass filter).

[One specific example of the first embodiment]
Next, a specific example of the basic configuration of the semiconductor drive device according to the first embodiment will be described with reference to FIG. Hereinafter, the first semiconductor driving device 30 will be described, but the second semiconductor driving device 50 has the same configuration.

  FIG. 8 is an equivalent circuit diagram showing a specific example of the basic configuration of the semiconductor drive device according to the first embodiment. In the present embodiment, an example in which an n-channel MOSFET 33a is used as the first filter 33 of the first semiconductor drive device 30 is shown as an example. The drain of the MOSFET 33a is connected to the input terminal of the first integrating circuit 34, and the source is connected to the second signal terminal 6 via the resistor R4. Resistors R2, R3, and R4 are connected in series between the first signal terminal 5 and the second signal terminal 6, and the gate of the first filter 33 is connected to the midpoint of connection between the resistors R2 and R3. ing. A diode 33b is connected in the reverse direction between the drain and source of the MOSFET 33a. The gate voltage of the MOSFET 33a is generated by resistance-dividing the first detection voltage obtained between the first signal terminal 5 and the second signal terminal 6. When the first detection voltage becomes larger than a predetermined value, the MOSFET 33 a is turned on, and a signal of the first detection voltage is input to the first integration circuit 34.

  A comparator 36 a is used as the first output comparison circuit 36. The comparator 36a compares the integrated value of the first integrating circuit 34 input to the non-inverting input terminal with the reference voltage Vref input to the inverting input terminal, and the integrated value of the first integrating circuit 34 is the reference voltage Vref. When the value is larger than the value, a signal is output to the second integration circuit 37.

  As the second integrating circuit 37, a filter circuit using passive elements such as a capacitor 37b and a resistor 37a is shown. When the integral value exceeds the voltage Vm, the second integration circuit 37 outputs a signal to the first cutoff command unit 38. The second integration circuit 37 may use a filter circuit using an operational amplifier.

  As an example of the first switch 35, a p-channel MOSFET 35 a that is turned on / off in response to a gate drive command signal output from the first gate drive command unit 31 can be used. The drain of the MOSFET 35 a is connected to the output terminal of the first integrating circuit 34, and the source is connected to the first signal terminal 5. A diode 35b is connected in the reverse direction between the drain and source of the MOSFET 35a. A parallel circuit of a diode 35c and a resistor 35d is connected between the input terminal of the first gate voltage control circuit 32 and the gate of the MOSFET 35a. The power supply voltage Vp is supplied to the input terminal of the first gate voltage control circuit 32 via the resistor R1.

  In the present embodiment, the first switch 35 is configured such that the gate voltage of the IGBT 11 (see FIG. 4) becomes the threshold voltage Vth (after the first semiconductor drive device 30 (first gate drive command unit 31) issues an ON command. The operation of the first integration circuit 34 is started until the time (see (2) in FIG. 3) is reached (the first switch 35 is turned off). The first gate drive command unit 31 issues an off command, and the output value of the first integrating circuit 34 is reset after the gate voltage of the IGBT 11 falls below the threshold voltage Vth (first switch 35 is turned on). During the ON command period of the gate drive command signal, the first switch 35 is turned off and the first integration circuit 34 is turned on, so that a short circuit of Type I to III can be detected.

  Further, in this embodiment, by connecting a resistor 35d and a diode 35c in parallel to the gate wiring of the first switch 35, the operation delay of the first switch 35 has anisotropy with respect to the gate drive command. It is Since the operation delay of the first switch 35 has anisotropy, the operation period of the first integration circuit 34 can be adjusted.

[Modification of Specific Example of First Embodiment]
FIG. 9 is an equivalent circuit diagram showing a modification of the specific example of the basic configuration of the semiconductor drive device according to the first embodiment. As in FIG. 8, the first switch 35 of the first semiconductor drive device 30 ′ is turned on / off according to the gate voltage of the IGBT 11 (see FIG. 4). The first semiconductor drive device 30 ′ is different from the first semiconductor drive device 30 shown in FIG. 8 in that the parallel circuit of the diode 35c and the resistor 35d of the first switch 35 is the first gate voltage control circuit 32. Is connected to the output terminal side. The second semiconductor driving device 50 ′ is configured similarly.

[Another specific example of the first embodiment]
FIG. 10 is an equivalent circuit diagram showing another specific example of the basic configuration of the semiconductor drive device according to the first embodiment. FIG. 10 shows an example in which the first filter 33-1 of the first semiconductor drive device 30-1 is configured by a bidirectional diode in which a diode 33c and a diode 33d are connected in parallel in opposite directions. Since a voltage smaller than the rising voltage of the diodes 33c and 33d is not passed, the first filter 33-1 functions as a voltage cut filter. The threshold value of the voltage to be removed can be adjusted by adjusting the first detection voltage using the resistance voltage division (resistors R3 and R4). The second filter 53-1 of the second semiconductor drive device 50-1 is configured similarly.

<2. Second Embodiment>
[Functional configuration of semiconductor drive device]
Next, a semiconductor drive device according to a second embodiment will be described with reference to FIGS.
FIG. 11 is a block diagram illustrating a basic configuration example of the semiconductor drive device according to the second embodiment. Hereinafter, the first semiconductor drive device 30A will be described, but the second semiconductor drive device 50A has the same configuration.

  The difference between the first semiconductor drive device 30A according to the second embodiment and the first semiconductor drive device 30 shown in FIG. 4 is that the overgate voltage state is monitored and determined to be the overgate voltage state. This is to shorten the time constant of the second integration circuit 37.

  The first semiconductor drive device 30 </ b> A further includes a first gate voltage comparison circuit 40 and a first time constant switching circuit 41 compared to the first semiconductor drive device 30. A series circuit of the first gate voltage comparison circuit 40 and the first time constant switching circuit 41 is connected between the gate of the IGBT 11 and the second integration circuit 37.

  The first gate voltage comparison circuit 40 monitors the overgate voltage state to determine whether or not it is in the overgate voltage state, and outputs the determination result to the first time constant switching circuit 41.

  The first time constant switching circuit 41 performs a process of shortening the time constant of the second integration circuit 37 when the first gate voltage comparison circuit 40 determines that the over gate voltage state is present. The delay until the current interruption command is issued after the state is determined is reduced.

  Similarly to the first semiconductor drive device 30A, the second semiconductor drive device 50A includes a second gate voltage comparison circuit 60 and a second time constant switching circuit 61. Since the functions of the second gate voltage comparison circuit 60 and the second time constant switching circuit 61 are the same as those of the first gate voltage comparison circuit 40 and the first time constant switching circuit 41, detailed description thereof is omitted. .

  The Type II and Type III short circuits are characterized in that current flows into the gate of the IGBT 11 via the feedback capacitance at the start of the short circuit, resulting in an over-gate voltage state. Therefore, the Type II and Type III short circuit is detected by determining the over-gate voltage state by the first gate voltage comparison circuit 40 together with the determination of the over-current state by the first output comparison circuit 36 shown in the first embodiment. can do.

  In general, a short circuit between Type II and Type III is a short circuit compared to a Type I short circuit, and therefore, it is necessary to cut off a current faster than a Type I short circuit. As shown in the second embodiment, if the delay of the current interruption command is reduced by the first time constant switching circuit 41 when it is determined that the over-gate voltage state is present, the current is interrupted at high speed when Type II and Type III are short-circuited. it can. Therefore, even if it is a short circuit of TypeII or TypeIII, an electric current can be interrupt | blocked safely.

[Specific Example of Second Embodiment]
Next, a specific example of the basic configuration of the semiconductor drive device according to the second embodiment will be described with reference to FIG. Hereinafter, the first semiconductor drive device 30A will be described, but the second semiconductor drive device 50A has the same configuration.

  FIG. 12 is an equivalent circuit diagram showing a specific example of the basic configuration of the semiconductor drive device according to the second embodiment. In the present embodiment, a comparator 40a is used as the first gate voltage comparison circuit 40 of the first semiconductor drive device 30A. The comparator 40a compares the gate voltage detected at the first gate signal terminal 4 input to the non-inverting input terminal with the power supply voltage Vp input to the inverting input terminal, and the gate voltage is greater than the power supply voltage Vp. In this case, a drive signal is output to the first time constant switching circuit 41.

  As an example, the first time constant switching circuit 41 uses a p-channel MOSFET 41a. The drain of the MOSFET 41 a is connected between the resistor 37 a of the second integration circuit 37 and the input terminal of the second cutoff command unit 58, and the source is connected to the capacitor 37 c of the second integration circuit 37. The gate of the MOSFET 41 a is connected to the output terminal of the comparator 40 a of the first gate voltage comparison circuit 40. When a drive signal is input from the comparator 40a to the gate of the MOSFET 41a, the MOSFET 41a is turned on. Thus, in the second integration circuit 37, a filter circuit is configured by adding a capacitor 37c to the resistor 37a and the capacitor 37b. As a result, the time constant of the CR circuit of the second integration circuit 37 is reduced, and the delay (integration period) from when the first output comparison circuit 36 determines an overcurrent state to when the current interruption command is issued is reduced. Is done. When the integral value exceeds the voltage Vm, the second integration circuit 37 outputs a signal to the first cutoff command unit 38.

<3. Third Embodiment>
[Functional configuration of semiconductor drive device]
Next, a semiconductor drive device according to a third embodiment will be described with reference to FIGS.
FIG. 13 is a block diagram illustrating a basic configuration example of the semiconductor drive device according to the third embodiment. Hereinafter, the first semiconductor drive device 30B will be described, but the second semiconductor drive device 50B has the same configuration.

  The difference between the first semiconductor drive device 30B according to the third embodiment and the first semiconductor drive device 30 shown in FIG. 4 is that the first output comparison circuit 36 determines that an overcurrent state has occurred. The gate voltage of the IGBT 11 is reduced to such an extent that the arm current (collector current) is not cut off.

  The first semiconductor drive device 30 </ b> B further includes a first gate voltage reduction circuit 42 as compared with the first semiconductor drive device 30. The first gate voltage reduction circuit 42 is connected between the first gate signal terminal 4 of the IGBT 11 and the output terminal of the first output comparison circuit 36.

  In order to perform short circuit protection of a semiconductor switching element having a large saturation current and a short circuit withstand capability, it is generally necessary to reduce the time constant of the second integration circuit 37 and cut off at high speed. However, if the time constant of the second integration circuit 37 is reduced, there is a problem that the risk of erroneously shutting off a system (such as a power converter and a system including the same) including a semiconductor power module due to erroneous detection due to noise increases. There is.

  According to the third embodiment having the above configuration, when the first output comparison circuit 36 determines that the upper arm 10 (IGBT 11) is overcurrent, the gate voltage of the IGBT 11 is reduced to suppress the saturation current. By doing, the short circuit tolerance of IGBT11 improves. Therefore, the current of the upper arm 10 can be safely reduced without reducing the time constant of the second integration circuit 37.

[Specific Example of Third Embodiment]
FIG. 14 is an equivalent circuit diagram showing a specific example of the basic configuration of the semiconductor drive device according to the third embodiment. Hereinafter, the first semiconductor drive device 30B will be described, but the second semiconductor drive device 50B has the same configuration.

  In the present embodiment, the first gate voltage reduction circuit 42 of the first semiconductor drive device 30B is configured using a MOSFET 42a. The drain of the MOSFET 41a is connected to the first gate signal terminal 4 through the resistor 42d, and the source is connected to the power source of the voltage Vm through the resistor 42c. The voltage Vm is smaller than the power supply voltage Vp. The gate of the MOSFET 41a is connected to the output terminal side of the comparator 36a of the first output comparison circuit 36 through a parallel circuit of a diode 42e and a resistor 42f. The diode 42e is connected so as to be in the forward direction from the first output comparison circuit 36 toward the MOSFET 41a.

  By connecting the resistor 42f and the diode 42e in parallel to the gate wiring of the MOSFET 42a, the gate voltage can be quickly reduced when the upper arm 10 is in an overcurrent state. On the other hand, even if the overcurrent state is canceled, the first period is maintained. The gate voltage reduction circuit 42 can be kept on. The gate voltage reduction function in this embodiment can prevent the circuit from oscillating even when the current oscillates temporarily, so that the current can be safely interrupted.

  Note that the second semiconductor drive device 50B includes a second gate voltage reduction circuit 62, similar to the first semiconductor drive device 30B. Since the function of the second gate voltage reduction circuit 62 is the same as that of the first gate voltage reduction circuit 42, detailed description thereof is omitted.

[Oscillation prevention by gate voltage reduction function]
Next, oscillation prevention by the gate voltage reduction function according to the present embodiment will be described with reference to FIGS. FIG. 15 is a schematic waveform diagram showing an example of the temporal change of the gate voltage when the gate voltage is reduced. FIG. 16 is a schematic waveform diagram showing an example of temporal change in arm current when the gate voltage is reduced.

  As shown in FIG. 15, when the gate voltage supplied to the gate of the IGBT 11 is reduced by the first gate voltage reduction circuit 42, the gate voltage fluctuates due to the inductor component of the wiring. When the gate voltage fluctuates, the current of the wiring conductor changes, so that the arm current fluctuates. Depending on the magnitude of the fluctuation of the arm current, the first output comparison circuit 36 determines that the state is an overcurrent state, and a signal is output from the first output comparison circuit 36 to the second integration circuit 37 (the arrow in FIG. 16). The first cutoff command unit 38 outputs a current cutoff signal. When the current is cut off, that is, when the gate voltage is reduced, the arm current may be changed again, and there is a possibility that the oscillation state may be repeated such that the first output comparison circuit 36 is turned on. In this embodiment, the resistor 42f is connected in parallel to the diode 42e, so that the first gate voltage reduction circuit 42 is kept on for a certain period of time, and the circuit oscillates even when the current oscillates temporarily. To prevent.

<4. Fourth Embodiment>
[Functional configuration of semiconductor drive device]
Next, a semiconductor drive device according to a fourth embodiment will be described with reference to FIGS.
FIG. 17 is a block diagram illustrating a basic configuration example of the semiconductor drive device according to the fourth embodiment. The first semiconductor drive device 30C will be described below, but the second semiconductor drive device 50C has the same configuration.

  The difference between the first semiconductor drive device 30C according to the fourth embodiment and the first semiconductor drive device 30 shown in FIG. 4 is that the gate of the IGBT 11 when the first detection voltage is larger than a predetermined value. It is a point to control the voltage

  The first semiconductor drive device 30 </ b> C includes a first gate voltage adjustment circuit 43 as compared with the first semiconductor drive device 30. The first gate voltage adjustment circuit 43 is connected between the first gate signal terminal 4 of the IGBT 11 and the connection point between the resistor R3 and the resistor R4.

  In the type II or type III short circuit, the current increase rate at the start of the short circuit is limited only by the inductance of the main circuit and becomes very large, resulting in a severe short circuit. At that time, a very large voltage is applied to the second signal terminal 6. For example, when the current on the emitter side of the IGBT abruptly increases, a large negative voltage is generated at the second signal terminal 6. On the contrary, when the current on the emitter side of the IGBT abruptly decreases, A large positive voltage is generated at the signal terminal 6.

[Specific Example of Fourth Embodiment]
FIG. 18 is an equivalent circuit diagram showing a specific example of the basic configuration of the semiconductor drive device according to the fourth embodiment. Hereinafter, the first semiconductor drive device 30C will be described, but the second semiconductor drive device 50C has the same configuration.

  In the present embodiment, the first gate voltage adjustment circuit 43 of the first semiconductor drive device 30C uses zener diodes 43a and 43b (constant voltage diodes) as an example. A Zener diode 43a and a Zener diode 43b are connected in series in the opposite direction between the first gate signal terminal 4 of the IGBT 11 and the connection point of the resistor R3 and the resistor R4. As long as the voltage can be clamped, other diodes may be used instead of the Zener diode.

  Note that the second semiconductor drive device 50C includes a second gate voltage adjustment circuit 63, like the first semiconductor drive device 30C. Since the function of the second gate voltage adjustment circuit 63 is the same as that of the first gate voltage adjustment circuit 43, detailed description thereof is omitted.

  According to 4th Embodiment of the said structure, there exist the following effects other than the effect acquired by 1st Embodiment. When the current of the IGBT 11 suddenly increases and a large negative voltage is applied to the second signal terminal 6, the gate voltage is reduced by the clamping operation of the Zener diode 43b, and an increase in current can be suppressed. Conversely, when the current of the IGBT 11 is suddenly decreased and a large positive voltage is applied to the second signal terminal 6, the gate voltage is increased by the clamping operation of the Zener diode 43a, and the current decrease rate is suppressed. Thus, the surge voltage generated when the current decreases can be reduced.

  For example, when the current flows when the voltage across the first gate signal terminal 4 and the second signal terminal 6 reaches 30 V, the potential of the first gate signal terminal 4 is +15 V, and the second signal terminal 6 When the potential becomes -15V, the voltage at both ends becomes 30V, current flows from the first gate signal terminal 4 to the second signal terminal 6 via the Zener diodes 43a and 43b, and the gate voltage is reduced.

<5. Fifth Embodiment>
Next, as a fifth embodiment, a power conversion device using the above-described first to fourth embodiments will be described with reference to FIG.

FIG. 19 is a circuit diagram showing a basic configuration example of a power conversion device according to the fifth embodiment.
A power conversion device 70 shown in FIG. 19 is obtained by applying the semiconductor drive device according to any one of the first to fourth embodiments described above as a drive device for a semiconductor switching element in the power conversion device 70. .

  As illustrated in FIG. 19, the power conversion device 70 includes 2-in-1 semiconductor power modules 74 to 76, semiconductor drive devices 77 to 82, and a drive that is a control signal for switching operation with respect to the semiconductor drive devices 77 to 82. A higher-order logic unit 72 that generates a command signal is provided. Note that the power conversion device 70 according to the fifth embodiment is an inverter device that converts the DC power of the DC power source 73 into AC power.

  In the fifth embodiment, IGBTs are used for the semiconductor power modules 74 to 76, but the present invention is not limited to this, and other semiconductor switching elements such as MOSFETs may be used.

  In the power conversion device 70, three sets of semiconductor power modules including the upper arm 10 and the lower arm 20 connected in series with the polarities of two semiconductor switching elements (IGBTs) aligned are connected between the positive and negative terminals of the DC power source 73. Has been. In addition, diodes that circulate the load current are connected in reverse polarity and in parallel between the emitter and collector of each semiconductor switching element. The connection points of the IGBT 11 (upper arm 10) and the IGBT 21 (lower arm 20) connected in series are AC output terminals (corresponding to the AC terminal 3 in FIG. 4), and are connected to the three-phase AC motor M as a load. Has been.

  The power conversion device 70 controls the switching operation of the semiconductor switching elements by the upper logic unit 72 via the semiconductor drive devices 77 to 82, respectively, and is connected to the AC terminals 3 u, 3 v, 3 w. To supply AC power.

  Here, the power conversion device 70 generates a drive command signal for each semiconductor switching element by the higher-order logic unit 72 and transmits the drive command signal to the gate signal terminal of the semiconductor switching device via the semiconductor drive devices 77 to 82. By doing so, the power conversion operation is performed.

  In the fifth embodiment, as an example in which the semiconductor drive device of the present invention is applied to a power conversion device, an inverter device that converts direct current to alternating current is used. However, the present invention is not limited to this. . The semiconductor drive device of the present invention can also be applied to other power conversion devices such as a DC-DC converter device and an AC-DC converter device.

  Furthermore, the present invention is not limited to the above-described embodiments, and various other application examples and modifications can be taken without departing from the gist of the present invention described in the claims. is there.

  For example, the above-described exemplary embodiments are detailed and specific descriptions of the configuration of the apparatus and the system in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the configurations described above. . Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment. In addition, the configuration of another embodiment can be added to the configuration of a certain embodiment. Moreover, it is also possible to add, delete, and replace other configurations for a part of the configuration of each exemplary embodiment.

  Further, the control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

  DESCRIPTION OF SYMBOLS 1 ... 1st main terminal (positive electrode terminal), 2 ... 2nd main terminal (negative electrode terminal), 3 ... AC terminal, 4 ... 1st gate signal terminal (gate), 5 ... 1st signal terminal (emitter) Signal terminal), 6 ... second signal terminal, 7 ... second gate signal terminal (gate), 8 ... third signal terminal (emitter signal terminal), 9 ... fourth signal terminal, 10 ... upper arm, DESCRIPTION OF SYMBOLS 11 ... IGBT (1st semiconductor switching element), 12 ... Diode, 13 ... 1st main electrode (collector), 14 ... 2nd main electrode (emitter), 20 ... Lower arm, 21 ... IGBT (2nd Semiconductor switching element), 22 ... diode, 23 ... third main electrode (collector), 24 ... fourth main electrode (emitter), 30, 30-1, 30A, 30B, 30C ... first semiconductor drive device, 31 ... First gate drive Motion command unit, 32 ... first gate voltage control circuit, 33, 33-1 ... first filter, 34 ... first integration circuit, 35 ... first switch, 36 ... first output comparison circuit, 37 DESCRIPTION OF SYMBOLS 2nd integration circuit 38 ... 1st interruption | blocking command part 40 ... 1st gate voltage comparison circuit 41 ... 1st time constant switching circuit 42 ... 1st gate voltage reduction circuit 43 ... 1st 50, 50-1, 50A, 50B, 50C ... second semiconductor drive device, 51 ... second gate drive command section, 52 ... second gate voltage control circuit, 53, 53-1. 2nd filter, 54 ... 3rd integration circuit, 55 ... 2nd switch, 56 ... 2nd output comparison circuit, 57 ... 4th integration circuit, 58 ... 2nd cutoff command part, 60 ... 1st 2 gate voltage comparison circuit, 61 ... second time constant Replacement circuit 62 ... Second gate voltage reduction circuit 63 ... Second gate voltage adjustment circuit 70 ... Power conversion device 72 ... Higher-order logic unit 73 ... DC power supply 74-76 Semiconductor power module 77- 82: Semiconductor drive device, SIN: Drive command input signal

Claims (8)

A semiconductor power module, and a semiconductor drive device for driving the semiconductor power module,
The semiconductor power module is
A first main terminal and a second main terminal to be a pair of DC terminals;
A first semiconductor switching element having a first main electrode and a second main electrode, wherein the first main electrode is electrically connected to the first main terminal;
A second semiconductor switching element having a third main electrode and a fourth main electrode, wherein the fourth main electrode is electrically connected to the second main terminal;
An AC terminal electrically connected to a connection point between a second main electrode of the first semiconductor switching element electrically connected in series and a third main electrode of the second semiconductor switching element;
A first signal terminal for detecting a potential of the second main electrode; a second signal terminal for detecting a potential of a connection point between the first semiconductor switching element and the second semiconductor switching element;
A third signal terminal for detecting the potential of the fourth main electrode; and a fourth signal terminal for detecting the potential of the second main terminal;
The semiconductor drive device includes a first semiconductor drive device and a second semiconductor drive device,
The first semiconductor drive device includes:
A first gate voltage control circuit for supplying a gate drive signal to the first semiconductor switching element;
A zero value is output when the first detection voltage detected at the second signal terminal is less than a predetermined value, and the first detection voltage is output when the first detection voltage exceeds the predetermined value. A first filter to output;
A first integration circuit that outputs an output value obtained by integrating the output of the first filter,
Based on the output of the first integration circuit, overcurrent protection of the first semiconductor switching element,
The second semiconductor driving device includes:
A second gate voltage control circuit for supplying a gate drive signal to the second semiconductor switching element;
A zero value is output when the second detection voltage detected at the fourth signal terminal is less than a predetermined value, and the second detection voltage is output when the second detection voltage exceeds the predetermined value. A second filter to output;
A third integration circuit for outputting an output value obtained by integrating the output of the second filter,
A power conversion device that performs overcurrent protection of the second semiconductor switching element based on an output of the third integration circuit. The first semiconductor drive device further includes:
A first output comparison circuit for comparing the output value of the first integration circuit with a predetermined value to determine whether or not an overcurrent state;
A first cutoff command unit that issues a current cutoff command to the first gate voltage control circuit based on a comparison result of the first output comparison circuit;
The second semiconductor drive device further includes:
A second output comparison circuit for comparing the output value of the third integration circuit with a predetermined value to determine whether or not an overcurrent state;
The power conversion device according to claim 1, further comprising: a second cutoff command unit that issues a current cutoff command to the second gate voltage control circuit based on a comparison result of the second output comparison circuit. The first semiconductor drive device further includes a second integration circuit that integrates an output value of the first output comparison circuit and outputs an integration value.
The first cutoff command unit issues the current cutoff command when the integral value of the second integration circuit reaches a predetermined value,
The second semiconductor drive device further includes a fourth integration circuit that integrates an output value of the second output comparison circuit and outputs an integration value.
The power conversion device according to claim 2, wherein the second cutoff command unit issues the current cutoff command when an integrated value of the fourth integration circuit reaches a predetermined value. The first semiconductor drive device further includes:
A first switch that operates the first integration circuit only during a predetermined period and resets the output value of the first integration circuit during the other period;
The second semiconductor drive device further includes:
The power converter according to claim 1, further comprising: a second switch that operates the third integration circuit only during a predetermined period and resets an output value of the third integration circuit during the other period. The first switch controls the operation of the first integration circuit between the time when the first semiconductor driving device issues an ON command and the time when the gate voltage of the first semiconductor switching element reaches a threshold voltage. The first semiconductor drive device issues an off command, and the output value of the first integration circuit is reset after the gate voltage of the first semiconductor switching element falls below a threshold voltage;
The second switch controls the operation of the third integrating circuit between the time when the second semiconductor driving device issues an ON command and the time when the gate voltage of the second semiconductor switching element reaches the threshold voltage. 5. The output of the third integrating circuit is reset after the second semiconductor driving device issues an off command and the gate voltage of the second semiconductor switching element falls below a threshold voltage. The power converter device described in 1. The first semiconductor drive device further includes:
A first gate voltage comparison circuit for determining whether or not the gate voltage of the first semiconductor switching element is in an over gate voltage state exceeding a predetermined value;
A first time constant switching circuit that reduces a time constant of the second integration circuit when the first gate voltage comparison circuit determines that the over gate voltage state is present;
The second semiconductor drive device further includes:
A second gate voltage comparison circuit for determining whether or not the gate voltage of the second semiconductor switching element is in an over gate voltage state exceeding a predetermined value;
4. A second time constant switching circuit that reduces a time constant of the fourth integration circuit when the second gate voltage comparison circuit determines that the over gate voltage state is present. 5. Power converter. The first semiconductor drive device further includes:
When the overcurrent state is determined by the first output comparison circuit, the gate voltage of the first semiconductor switching element flows between the first main electrode and the second main electrode. A first gate voltage reduction circuit that reduces the current to an extent that is not interrupted,
The second semiconductor drive device further includes:
When the second output comparison circuit determines that the overcurrent state is present, the gate voltage of the second semiconductor switching element flows between the third main electrode and the fourth main electrode. The power conversion device according to claim 2, further comprising a second gate voltage reduction circuit that reduces the current to an extent that the current is not interrupted. The first semiconductor drive device further includes:
A first gate voltage adjustment circuit that reduces a gate voltage of the first semiconductor switching element when the first detection voltage exceeds a predetermined value;
The second semiconductor drive device further includes:
The power conversion device according to claim 1, further comprising: a second gate voltage adjustment circuit that reduces a gate voltage of the second semiconductor switching element when the second detection voltage exceeds a predetermined value.

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