JP2019009840A - Current detection circuit - Google Patents

Abstract

To detect current of an inverter by reducing an operation load and a circuit scale that are required for detecting the current.SOLUTION: A current detection circuit 5 comprises a first current detection part 1 for detecting an amount of current flowing a sense terminal T1 of a first switching element 11 constituting an arm 10a of an inverter 10 as a voltage value to output positively and negatively symmetrical first voltage value and first inversion voltage value; a second current detection part 2 for detecting another amount of current flowing another sense terminal T2 of a second switching element 12 as another voltage value to output positively and negatively symmetrical second voltage value and second inversion voltage value; and a third current detection part 3 for providing, to an inverter control device 20 by which the inverter 10 is switching-controlled, a difference between two voltage values after the following addition according to adding the first voltage value and the second inversion voltage value, and adding the first inversion voltage value and the second voltage value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a current detection circuit that detects a current flowing through an arm of an inverter.

  In an inverter that converts electric power between direct current and alternating current, currents flowing through switching elements and inverter arms constituting the inverter are detected for inverter control and fail-safe. Various methods are known as current detection methods. For example, a current sensor is installed in each arm to directly detect the current, and a shunt resistor or the like is arranged in series in each arm and a terminal of the shunt resistor. For example, a current is detected from an inter-voltage, and a current is detected from a voltage across a resistor connected in series to the sense terminal in a switching element having a sense terminal through which a minute current proportional to the element current flows.

  For example, Japanese Patent Laying-Open No. 2006-63675 discloses that an inverter (21) configured using a switching element having a sense terminal (SE, SS) detects a current flowing through the inverter based on a current flowing through the sense terminal. (For example, [0063], FIG. 3, FIG. 5, etc. In the background art, the reference numerals in parentheses are those of the references to be referred to). This inverter (21) has three arms, and each arm has two switching elements. The currents flowing through the sense terminals of a total of six switching elements are detected by six current measurement circuits (CM11, CM12, CM21, CM22, CM31, CM32) corresponding to the respective switching elements. The detection results (FB11, FB12, FB21, FB22, FB31, FB32) of these six current measurement circuits are input to the control circuit (22) that controls the inverter (21).

  When the control circuit (22) is constituted by a microcomputer or the like, for example, six input terminals (ports) are required to receive detection results from the six current measurement circuits. In addition, in order to perform a digital operation using the detection result provided as an analog signal, the control circuit needs to include six or more A / D converters or share less than six A / D converters. is there. In addition, the current value of each arm needs to be calculated based on the detection results of the two switching elements constituting each arm. As described above, when the current of the inverter is detected using the sense terminal provided in each switching element, there is a possibility that the input terminal of the control circuit, the circuit scale, the calculation load, and the like are increased.

Japanese Patent Laid-Open No. 2006-63675

  In view of the above background, it is desirable to provide a technique for appropriately detecting the current of the inverter by reducing the circuit scale and calculation load required for current detection.

In view of the above, the arm in which the first switching element and the second switching element are connected in series is connected between the positive electrode and the negative electrode of the direct current to convert the power between the direct current and the alternating current to the arm of the inverter. A current detection circuit for detecting a flowing current is one aspect,
The first switching element and the second switching element each have one control terminal, two input / output terminals, and a sense terminal through which a minute current proportional to an element current flowing between the input / output terminals flows;
A first current detector that detects a magnitude of a current flowing through the first sense terminal, which is the sense terminal of the first switching element, as a voltage value, and outputs the first voltage value and a first inverted voltage value that are symmetric with respect to positive and negative; ,
A second current detector for detecting the magnitude of the current flowing through the second sense terminal, which is the sense terminal of the second switching element, as a voltage value, and outputting the detected voltage as a positive and negative symmetric second voltage value and a second inverted voltage value; ,
The first voltage value and the second inverted voltage value are added, the first inverted voltage value and the second voltage value are added, and the inverter is subjected to switching control for the difference between the two voltage values after the addition. A third current detector provided to the inverter control device.

  According to this configuration, the current flowing through the first switching element (hereinafter referred to as the first element current) and the current flowing through the second switching element (hereinafter referred to as the second element current) are individually detected and controlled by the inverter. Compared to the case of providing the device, the number of connection terminals between the inverter control device and the current detection circuit can be reduced, and the circuit scale can be reduced. For example, when the inverter is compatible with three-phase alternating current, the number of connection terminals can be reduced by three because there are three arms.

  In many cases, a control device such as an inverter control device is constituted by a digital circuit such as a logical processor. When the current detection circuit is an analog signal, it is converted into a digital value by an A / D converter provided in the inverter control device. When the detection result of the first element current and the detection result of the second element current are separately provided to the inverter control device, the inverter control device requires two A / D converters. Alternatively, the inverter control device needs to selectively use one A / D converter by time sharing or the like, and the control load increases. Like this configuration, the number of A / D converters required is reduced by providing the detection result of the first element current and the detection result of the second element current to the inverter control device as one detection result. As a result, the need for time sharing and the like also decreases. As described above, when the inverter is compatible with three-phase alternating current, the reduction effect of the A / D converter is further increased.

  Further, when the detection result of the first element current and the detection result of the second element current are individually provided to the inverter control device, it is necessary to calculate the current of the entire arm in the inverter control device. By combining the detection result of the first element current and the detection result of the second element current before providing to the control device, it is possible to reduce the calculation load in the inverter control device. Since the inverter is switched using pulse width modulation or the like, switching noise tends to occur when the first element current and the second element current are switched. In this configuration, since the detection result is provided to the inverter control device after taking the difference in the third current detection unit, the switching noise is also appropriately reduced. Thus, according to the present configuration, the circuit scale and calculation load required for current detection can be reduced, and the inverter current can be detected appropriately.

  Further features and advantages of the current detection circuit will become clear from the following description of embodiments described with reference to the drawings.

Circuit block diagram showing configuration example of inverter and current detection circuit Equivalent block diagram of isolation amplifier Output waveform diagram of the first current detection circuit Output waveform diagram of second current detection circuit Output waveform diagram of the third current detection circuit Circuit block diagram showing another configuration example of the current detection circuit Circuit block diagram showing comparative example of current detection circuit Output waveform diagram of third current detection circuit of comparative example Output waveform diagram of third current detection circuit of comparative example

  Hereinafter, embodiments of a current detection circuit will be described with reference to the drawings. Here, the current detection circuit 5 that detects the current flowing through the arm 10a of the inverter 10 for driving the AC rotating electrical machine 80 will be described as an example. The inverter 10 is connected to a DC power source (not shown) and the rotating electrical machine 80, and converts power between DC and AC. In this embodiment, the rotary electric machine 80 is a three-phase AC rotary electric machine, and the inverter 10 also converts electric power between direct current and three-phase alternating current. The inverter 10 is configured such that an arm 10 a in which a first switching element 11 and a second switching element 12 are connected in series is connected between a DC positive electrode P and a negative electrode N. In the present embodiment, three arms 10a (a u-phase arm 10u, a v-phase arm 10v, and a w-phase arm 10w) are provided corresponding to the three-phase stator coil 81 of u, v, and w of the rotating electrical machine 80. ing.

  The inverter 10 is controlled by the inverter control device 20. The inverter control device 20 is constructed with a logical processor such as a microcomputer as a core member. For example, the inverter control device 20 performs current feedback control using a vector control method based on the target torque of the rotating electrical machine 80 provided by another control device (not shown), and rotates the rotating electrical machine 80 via the inverter 10. To control. Since vector control and current feedback control are publicly known, detailed description thereof is omitted here. In the present embodiment, the inverter control device 20 acquires the current value flowing through the stator coil 81 of each phase of the rotating electrical machine 80 via the current detection circuit 5. Moreover, the inverter control apparatus 20 acquires the magnetic pole position and rotational speed at each time of the rotor of the rotating electrical machine 80 from a rotation sensor (not shown) such as a resolver.

  The current detection circuit 5 detects a current flowing through each arm 10 a corresponding to a current flowing through the stator coil 81. Since the configuration of the current detection circuit 5 corresponding to each arm 10a is the same, in the following description, the current detection circuit 5 corresponding to the u-phase arm 10u will be described as a representative. The first switching element 11 is a so-called upper stage side switching element, and is connected to the DC positive electrode P side. The second switching element 12 is a so-called lower-stage switching element, and is connected to the DC negative electrode N side. In the present embodiment, the first switching element 11 and the second switching element 12 are illustrated as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). However, IGBT (Insulated Gate Bipolar Transistor) or SIT (Static Induction Transistor) may be used as the switching element.

The first switching element 11 and the second switching element 12 each have one control terminal (gate terminal G), two input / output terminals (drain terminal D, source terminal S), and input / output terminals (between drain and source). ) And a sense terminal T through which a minute current (sense current) proportional to the device current (drain-source current I _DS ) flows. Further, each of the first switching element 11 and the second switching element 12 includes a switching element body TR and a free wheel diode FD connected in parallel to the switching element body TR with the direction from the negative electrode N to the positive electrode P as a forward direction. And have. When the switching element is a MOS-FET, a diode is formed with the direction from the source terminal S to the drain terminal D as the forward direction due to the structure of the switching element. When the switching element is an IGBT or the like, it is preferable that a freewheel diode FD is separately connected.

  The current detection circuit 5 includes a first current detection unit 1, a second current detection unit 2, and a third current detection unit 3. Although the details will be described later, the first current detector 1 detects the magnitude of the current flowing through the first sense terminal T1, which is the sense terminal T of the first switching element 11, as a voltage value, and a first voltage value that is symmetric between positive and negative. And the first inverted voltage value is output. The second current detection unit 2 detects the magnitude of the current flowing through the second sense terminal T2, which is the sense terminal T of the second switching element 12, as a voltage value, and a positive and negative symmetric second voltage value and second inverted voltage value. Is output. The third current detector 3 adds the first voltage value and the second inverted voltage value, adds the first inverted voltage value and the second voltage value, and takes the difference between these two voltage values after the addition. To the inverter control device 20.

  As shown in FIG. 1, the first current detector 1 includes a first operational amplifier having a first non-inverting output terminal PO1 that outputs a first voltage value and a first inverting output terminal NO1 that outputs a first inverted voltage value. A1. The second current detection unit 2 includes a second operational amplifier A2 having a second non-inverting output terminal PO2 that outputs a second voltage value and a second inverting output terminal NO2 that outputs a second inverted voltage value. Yes. Further, the third current detection unit 3 includes a third operational amplifier A3 (differential amplifier DA) having a first differential input terminal DI1, a second differential input terminal DI2, and a differential output terminal DO.

  As described above, in the third current detection unit 3, the first voltage value and the second inverted voltage value are added, and the first inverted voltage value and the second voltage value are added. Therefore, in the third current detection unit 3, the first non-inverting output terminal PO1 and the second inverting output terminal NO2 are connected to form the first addition node n1, and the first inverting output terminal NO1 and the second non-inverting terminal The output terminal PO2 is connected to form a second addition node n2. The first addition node n1 is connected to the first differential input terminal DI1, the second addition node n2 is connected to the second differential input terminal DI2, and the differential output terminal DO is connected to the inverter control device 20. ing. Since the outputs of the first current detection unit 1 and the second current detection unit 2 are connected to the input terminal of the third operational amplifier A3 that performs differential amplification, the first current detection unit 1 and the second current detection unit 2 are It is preferable that the amplification factor by the first operational amplifier A1 and the amplification factor by the second operational amplifier A2 are the same.

  As shown in FIG. 1, a first resistor R1 is provided between the first non-inverting output terminal PO1 and the first addition node n1. A second resistor R2 is provided between the second inverted output terminal NO2 and the first addition node n1. A third resistor R3 is provided between the first inverting output terminal NO1 and the second addition node n2. A fourth resistor R4 is provided between the second non-inverting output terminal PO2 and the second addition node n2. As described above, since the outputs of the first current detection unit 1 and the second current detection unit 2 are connected to the input terminal of the third operational amplifier A3 that performs differential amplification, there is no variation in weighting in addition. Is preferred. Accordingly, it is preferable that the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 have the same resistance value.

  By the way, when the output is relatively large, such as a rotating electrical machine in which the rotating electrical machine 80 serves as a driving force source for the wheels of the vehicle, the voltage of the DC power source connected to the inverter 10 may also increase (for example, several tens to Hundreds of volts). On the other hand, the inverter control device 20 and the current detection circuit 5 are often electronic circuits whose operating voltage is much lower than that (for example, about 3.3 to 12 volts). For this reason, high voltage tolerance and insulation are required for the first current detection unit 1 and the second current detection unit 2. In the present embodiment, the input side (the inverter 10 side) of the first current detection unit 1 and the second current detection unit 2 and the output side (the inverter control device 20 and the third current detection unit 3 side) are insulated. ing. Specifically, the first operational amplifier A1 and the second operational amplifier A2 are configured using an isolation amplifier IA in which the input side and the output side are insulated.

  FIG. 2 schematically shows the configuration of the isolation amplifier IA. The isolation amplifier IA includes an input side amplifier 6 and an output side amplifier 7, and the input side amplifier 6 and the output side amplifier 7 are electrically insulated. A signal is transmitted from the input side amplifier 6 to the output side amplifier 7 by a photocoupler. The output-side amplifier 7 has a non-inverting output terminal PO that outputs a positive / negative voltage and an inverting output terminal NO.

The outline of the current detection circuit 5 has been described above. Specific configuration examples and operation examples will be described below with reference to FIGS. Although FIGS. 3 to 5 show examples of waveforms, for the sake of convenience, the direction of the current is the direction indicated by the arrow in FIG. The drain of the first switching element 11 - source current _{I DS} of the first element current _{I H,} the drain of the second switching element 12 - the source current _{I DS} and second element current _{I L.} The sense terminal T, the drain - small sense current I _SNS proportional to source current I _DS is flowing. With this ratio as the mirror ratio M of the sense current, “sense current I _SNS = drain-source current I _DS / M”. In general, the sense current I _SNS is 1/1000 or less of the drain-source current I _DS . The sense terminal T, the sense resistor (R11, R12) are connected, the first operational amplifier A1 and a second operational amplifier A2, the voltage across the sense resistor a first element current _{I H} and the second element current _{I L} It is detected as the indicated voltage value.

  The first sense resistor R11 is connected to the first sense terminal T1 of the first switching element 11, and both ends of the first sense resistor R11 are connected to the non-inverting input terminal PI (first non-inverting input terminal) of the first operational amplifier A1. PI1) and the inverting input terminal NI (first inverting input terminal NI1). The second sense resistor R12 is connected to the second sense terminal T2 of the second switching element 12, and both ends of the second sense resistor R12 are connected to the non-inverting input terminal PI (second non-inverting input terminal) of the second operational amplifier A2. PI2) and the inverting input terminal NI (second inverting input terminal NI2). Note that the first sense resistor R11 and the second sense resistor R12 have the same resistance value.

The first operational amplifier A1 and the second operational amplifier A2 output the difference between the voltage at the non-inverting input terminal PI and the voltage at the inverting input terminal NI as a detection value. When the first operational amplifier A1 and the second operational amplifier A2 output the difference, the first operational amplifier A1 and the second operational amplifier A2 output two signals that are symmetric. Note that the voltage on the axis of symmetry is, for example, the voltage of the midpoint (V _DD / 2) of the power supply voltage V _DD of the first operational amplifier A1 and the second operational amplifier A2. Of course, the axis of symmetry is not limited to the midpoint, and may be a voltage offset to the power supply voltage side (V _DD side) or the ground side (zero side). Further, when the first operational amplifier A1 and the second operational amplifier A2 are isolation amplifiers IA as in the present embodiment, the input side amplifier 6 and the output side amplifier 7 have different power sources (electrically isolated and floating). Operated by the power supply). The power supply voltage V _DD that defines the axis of symmetry of the output signal is the power supply voltage of the output side amplifier 7.

Here, the mirror ratio is M, the amplification factor (first amplification factor) of the first operational amplifier A1 is α1, the sense current I _SNS on the upper stage side (first switching element 11) is I _SNSH , and the common mode noise on the upper stage side is N _CMH , where the resistance value of the first sense resistor R11 is R11, the first voltage value V _PO1 that is a voltage value output from the non-inverting output terminal PO (first non-inverting output terminal PO1) of the first operational amplifier A1. The first inverted voltage value V _NO1 that is the voltage value output from the inverted output terminal NO (first inverted output terminal NO1) of the first operational amplifier A1 is expressed by the following equations (1) and (2). FIG. 3 shows a waveform example of the first non-inverting output terminal PO1 and the first inverting output terminal NO1. The first voltage value V _PO1 and the first inverted voltage value V _NO1 output from the first non-inverted output terminal PO1 and the first inverted output terminal _NO1 are alternating current signals, and the voltage (V _DD / 2) also corresponds to the amplitude center of the first voltage value _VPO1 and the first inverted voltage value _VNO1 .

V _PO1 = M ・ R11 ・ α1 ・ I _SNSH + N _CMH (1)
V _NO1 = -M ・ R11 ・ α2 ・ I _SNSH + N _CMH (2)

Similarly, the amplification factor of the second operational amplifier A2 (the second amplification factor) [alpha] 2, the lower side sense current _{I SNS} the _{I SNSL} (second switching element 12), the common mode noise _{N CML} the lower side, the second Assuming that the resistance value of the sense resistor R12 is R12, a second voltage value V _PO2 , which is a voltage value output from the non-inverting output terminal PO (second non-inverting output terminal PO2) of the second operational amplifier A2, a second operational amplifier. A second inversion voltage value _VNO2 that is a voltage value output from the inversion output terminal NO (second inversion output terminal NO2) of A2 is expressed by the following equations (3) and (4). FIG. 4 shows a waveform example of the second non-inverting output terminal PO2 and the second inverting output terminal NO2. Also in this case, the voltage (V _DD / 2) serving as the symmetry axis described above corresponds to the amplitude center of the second voltage value _VPO2 and the second inverted voltage value _VNO2 .

V _PO2 = M ・ R12 ・ α2 ・ I _SNSL + N _CML (3)
V _NO2 = -M ・ R12 ・ α2 ・ I _SNSL + N _CML (4)

The first non-inverting output terminal PO1 is connected to the first addition node n1 via the first resistor R1, the second inverting output terminal NO2 is connected to the first addition node n1 via the second resistor R2, At the 1 addition node n1, the first voltage value _VPO1 and the second inverted voltage value _VNO2 are added. The second non-inverting output terminal PO2 is connected to the second addition node n2 via the third resistor R3, and the first inverting output terminal NO1 is connected to the second addition node n2 via the fourth resistor R4. The second voltage value _VPO2 and the first inverted voltage value _VNO1 are added at the second addition node n2.

The first addition node n1 is connected to the non-inverting input terminal (first differential input terminal DI1) of the third operational amplifier A3 via the fifth resistor R5, and the second addition node n2 is connected to the seventh resistor R7. To the inverting input terminal (second differential input terminal DI2) of the third operational amplifier A3. The third operational amplifier A3 (differential amplifier DA) calculates the difference between the voltage at the first addition node n1 (first addition voltage value) and the voltage at the second addition node n2 (second addition voltage value). As apparent from FIGS. 3 and 4, since the first addition voltage value and the second addition voltage value are also AC signals, the reference voltage Ref corresponding to the amplitude center is set. The reference voltage Ref is, for example, a voltage at the midpoint (V _DD / 2) of the power supply voltage V _DD of the third operational amplifier A3. Of course, the reference voltage Ref is not limited to the middle point, and may be a voltage offset to the power supply voltage side (V _DD side) or the ground side (zero side).

  The first differential input terminal DI1 is further connected to the reference voltage Ref via the sixth resistor R6. The second differential input terminal DI2 is further connected to the output terminal (differential output terminal DO) of the third operational amplifier A3 via the eighth resistor R8. When the resistance values of the first resistor R1, the fifth resistor R5, and the sixth resistor R6 are R1, R5, and R6, respectively, the amplification factor (third amplification) in the third current detector 3 (third operational amplifier A3). (Rate) g is represented by the following formula (5). As described above, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are the same, and here, the resistance of the first resistor R1 is representative. Use the value. In general, in a differential amplifier such as the third operational amplifier A3, the resistance value of the fifth resistor R5 and the resistance value of the seventh resistor R7 are the same, and the resistance value of the sixth resistor R6 is The resistance value of the eighth resistor R8 is the same.

  g = R6 / {(R1 / 2) + R5} = 2 · R6 / (R1 + 2 · R5) (5)

  Using the third amplification factor g, the voltage value (detected output value) VO of the differential output terminal DO, which is the output terminal of the third operational amplifier A3, is expressed by the following equation (6). Note that “Vref” in the equation (6) corresponds to the reference voltage Ref (“Ref” shown in FIG. 1, potential corresponding to the amplitude center in FIGS. 3 and 4). FIG. 5 shows a waveform example of the differential output terminal DO.

VO = g {( _VPO1 + _VNO2 ) / 2}-{( _VPO2 + _VNO1 ) / 2} + Vref (6)

  Here, the first operational amplifier A1 and the second operational amplifier A2 are the same isolation amplifier IA, the first amplification factor α1 and the second amplification factor α2 are the same amplification factor α, and the first sense resistor R11 and Assuming that the second sense resistor R12 has the same resistance value Rs, from the equations (1) to (6), the equation (7) is expressed as follows.

VO = _{g.M.Rs..alpha ..} ( _{I.sub.SNSH- I.sub.SNSL} ) + Vref (7)

  The differential output terminal DO is connected to the inverter control device 20. As apparent from the equation (7) and FIG. 5, the common mode noise is appropriately removed, and a voltage value (detected output value VO) indicating a sinusoidal current flowing through the arm 10 a is provided to the inverter control device 20. The inverter control device 20 converts the detected output value VO into a digital value by the A / D converter 21 and uses it for feedback control of the inverter 10.

  Note that the detection output value VO only needs to be finally output from the third current detection unit 3, so that the first operational amplifier A1 of the first current detection unit 1 and the second operational amplifier A2 of the second current detection unit 2 are used. The connection form of the third current detector 3 to the non-inverting input terminal and the inverting input terminal of the third operational amplifier A3, and the non-inverting output terminal and the inverting output terminal of the first operational amplifier A1 and the second operational amplifier A2 The connection form (connection form to the first addition node n1 and the second addition node n2) is not limited to the form described above with reference to FIG. For example, as illustrated in FIG. 6, the connection of the second operational amplifier A2 to the second non-inverting input terminal PI2 and the second inverting input terminal NI2 is reversed from that in FIG. 1, and the second non-inverting output terminal PO2 The connection from the second inverted output terminal NO2 may be reversed from that in FIG.

As described above, the current flowing through the first switching element 11 (first element current I _H ) and the current flowing through the second switching element (second element current I _L ) are individually detected and transferred to the inverter control device 20. Compared with the case where it provides, the connection terminal of the inverter control apparatus 20 and the electric current detection circuit 5 can be reduced, and a circuit scale can be made small.

FIG. 7 illustrates, as a comparative example, a current detection circuit 50 in a form in which the first element current I _H and the second element current _IL are individually detected and provided to the inverter control device 20. The configurations of the first current detection unit 1 and the second current detection unit 2 are the same as those described above with reference to FIG. The third current detection unit 30 of the comparative example is provided with two systems corresponding to the third current detection unit 3 of the above-described embodiment. The resistors R5a and R5b in the comparative example correspond to the fifth resistor R5 described above, the resistors R6a and R6b correspond to the sixth resistor R6, the resistors R7a and R7b correspond to the seventh resistor R7, Resistors R8a and R8b correspond to the eighth resistor R8. In addition, the operational amplifiers A31 and A32 in the comparative example are differential amplifiers DA corresponding to the third operational amplifier A3. In the comparative example, the current detection circuit 50 outputs two detection output values (first detection output value VO _H , second detection output value VO _L ). Sense current _{I SNS (I SNSH, I SNSL} ) detection output value (first detected output value VO _H, the second detection output value VO _L) The operation of obtaining the embodiments described above with reference to FIG. 1 Detailed description will be omitted.

A first detection output value VO _H corresponding to the first element current I _H and the second detection output value VO _L corresponding to the second element current I _L is provided to individually inverter control device 20 as the comparative examples In this case, the inverter control device 20 requires two A / D converters 21 (21a, 21b) as shown in FIG. Alternatively, the inverter control device 20 needs to selectively use one A / D converter 21 by time sharing or the like, which increases the control load. As described above with reference to FIG. 1, to provide to the inverter control device 20 as the first element current I _H of the detection result and the second element current I _L of the detection result and one detection output value VO combined Therefore, the number of A / D converters 21 required is reduced, and the need for time sharing and the like is also reduced. Moreover, the connection terminal of the inverter control apparatus 20 can also be reduced. When the inverter 10 is compatible with three-phase alternating current, the effect of further reducing the A / D converter 21 and the connection terminals is increased.

8 and 9 show an example of the waveform of the first detection output value VO _H and the second detection output value VO _L. As it is apparent from FIGS. 8 and 9, the first detection output value VO _H and the second detection output value VO _L is varied in accordance with a switching control on the switching elements (11, 12) such as by pulse width modulation , The current of the entire arm 10a is not represented. Therefore, the inverter control unit 20, A / D converter 21 (21a, 21b) a first detection output value VO _H and the second detection output value VO _L by after converting into a digital value, the total current of the arm 10a It is necessary to calculate. However, in the present embodiment, as shown in FIG. 5, the detected output value VO represents the current of the entire arm 10 a, so the calculation load in the inverter control device 20 is reduced.

  As described above, according to the present embodiment, the circuit scale and calculation load required for current detection can be reduced, and the inverter current can be detected appropriately.

[Outline of Embodiment]
The outline of the current detection circuit (5) described above will be briefly described below.

As one aspect, an arm in which the first switching element (11) and the second switching element (12) are connected in series is connected between a positive electrode and a negative electrode of a direct current to convert power between direct current and alternating current. The current detection circuit (5) for detecting the current flowing through the arm of the inverter
Each of the first switching element and the second switching element includes a control terminal (G), two input / output terminals (D, S), and an element current (DS) flowing between the input / output terminals (DS). A sense terminal (T) through which a minute current proportional to I _DS ) flows,
The magnitude of the current flowing through the first sense terminal (T1), which is the sense terminal (T) of the first switching element (11), is detected as a voltage value, and a first voltage value (V _PO1 ) that is positive and negative symmetric and a first voltage value. A first current detector (1) that outputs as one inverted voltage value (V _NO1 );
The magnitude of the current flowing through the second sense terminal (T2), which is the sense terminal (T) of the second switching element (12), is detected as a voltage value, and a positive and negative symmetric second voltage value (V _PO2 ) and A second current detection unit (2) that outputs a value of 2 inversion voltage (V _NO2 );
The first voltage value (V _PO1 ) and the second inverted voltage value (V _NO2 ) are added, and the first inverted voltage value (V _NO1 ) and the second voltage value (V _NO1 ) are added and added. A third current detection unit (3) that provides a difference between the latter two voltage values to an inverter control device (20) that performs switching control of the inverter (10).

According to this configuration, a current flowing through the first switching element (11) (hereinafter referred to as a first element current (I _H )) and a current flowing through the second switching element (12) (hereinafter referred to as a second element current (I) _L )) is detected separately and provided to the inverter control device (20), the number of connection terminals between the inverter control device (20) and the current detection circuit (5) can be reduced. The circuit scale can be reduced. For example, when the inverter (10) is compatible with three-phase alternating current, the number of connection terminals can be reduced by three because there are three arms (10a).

In many cases, the control device such as the inverter control device (20) is configured by a digital circuit such as a logical processor. When the current detection circuit (5) is an analog signal, it is converted into a digital value by an A / D converter (21) provided in the inverter control device (20). When the detection result of the first element current (I _H ) and the detection result of the second element current (I _L ) are individually provided to the inverter control device (20), the inverter control device (20) has two A / A D converter (21) is required. Alternatively, the inverter control device (20) needs to selectively use one A / D converter (21) by time sharing or the like, and the control load becomes high. It becomes necessary by combining the detection result of the first element current (I _H ) and the second element current (I _L ) as one detection result to the inverter control device (20) as in this configuration. The number of A / D converters (21) decreases, and the need for time sharing and the like also decreases. As described above, when the inverter (10) is compatible with three-phase alternating current, the reduction effect of the A / D converter (21) is further increased.

When the detection result of the first element current (I _H ) and the detection result of the second element current (I _L ) are individually provided to the inverter control device (20), the current of the entire arm (10a) Must be calculated in the inverter control device (20), but before being provided to the inverter control device (20), the detection result of the first element current (I _H ) and the detection result of the second element current (I _L ) Can be combined to reduce the computational load on the inverter control device (20). Since the inverter (20) is switched using pulse width modulation or the like, switching noise tends to occur when the first element current (I _H ) and the second element current (I _L ) are switched. In this configuration, since the detection result is provided to the inverter control device (20) after taking the difference in the third current detection unit (3), the switching noise is also appropriately reduced. Thus, according to the present configuration, the circuit scale and calculation load required for current detection can be reduced, and the inverter current can be detected appropriately.

Here, the first current detector (1) is the output of the first non-inverting output terminal (PO1) and the first reversal voltage value output the first voltage value _{(V PO1) (V NO1)} A first operational amplifier (A1) having one inverting output terminal (NO1);
Said second current detector (2), the second inverted output for outputting a second non-inverting output terminal (PO2) and said second inversion voltage value to output the second voltage value _{(V PO2) (V NO2)} A second operational amplifier (A2) having a terminal (NO2);
The third current detector (3) includes a differential amplifier (A3 (DA)) having a first differential input terminal (DI1), a second differential input terminal (DI2), and a differential output terminal (DO). Including
The amplification factor (α) by the first operational amplifier (A1) and the second operational amplifier (A2) is the same,
The first non-inverting output terminal (PO1) and the second inverting output terminal (NO2) are connected to form a first addition node (n1), and the first inverting output terminal (NO1) and the second non-inverting output terminal (NO1). The inverting output terminal (PO2) is connected to form a second addition node (n2),
The first addition node (n1) is connected to the first differential input terminal (DI1), the second addition node (n2) is connected to the second differential input terminal (DI2), and the differential output It is preferable that the terminal (DO) is connected to the inverter control device (20).

When the current flowing through the sense terminal (T) is detected as a voltage value, in order not to affect the current to be detected, the input impedances of the first current detection unit (1) and the second current detection unit (2) are High is preferred. Considering that the first voltage value (V _PO1 ), the first inversion voltage value (V _NO1 ), the second voltage value (V _PO2 ), and the second inversion voltage value (V _NO2 ) are added, the first A first current detector (1) that outputs a voltage value (V _PO1 ) and a first inverted voltage value (V _NO1 ), and a second voltage value (V _PO2 ) and a second inverted voltage value (V _NO2 ) are output. The second current detector (2) that performs the output preferably has a low output impedance. An operational amplifier is a circuit element having a high input impedance (ideally infinite) and a low output impedance (ideally zero). Therefore, it is preferable that the first current detection unit (1) and the second current detection unit (2) include the operational amplifiers (A1, A2).

  In the third current detection unit (3), an addition operation and a differential operation for taking a difference are performed. The addition operation is realized by electrical connection at the first addition node (n1) and the second addition node (n2), but in order not to affect the operation result, the input impedance of the circuit that performs the differential operation Is preferably high. The differential amplifier (A3 (DA)) is a kind of operational amplifier, and is an element having a high input impedance (ideally infinite). Therefore, it is preferable that the third current detection unit (3) includes the differential amplifier (A3 (DA)). Note that a differential amplifier (A3 (DA)), which is a kind of operational amplifier, has a low output impedance (ideally zero), and therefore is not easily affected by the input impedance and wiring of the inverter control device (20). The current detection result can be provided to the inverter control device (20).

  As described above, when the first current detector (1) includes the first operational amplifier (A1) and the second current detector (2) includes the second operational amplifier (A2), The first operational amplifier (A1) and the second operational amplifier (A2) are preferably isolation amplifiers (IA) in which the input side and the output side are insulated.

  When the work of an electric device driven through the inverter (10) is large (for example, a high-torque rotating electrical machine, pump, compressor, etc.), the voltage of the DC power source connected to the inverter (10) may be high. (For example, tens to hundreds of volts). On the other hand, the inverter control device (20) and the current detection circuit (5) are often electronic circuits whose operating voltage is much lower (for example, about 3.3 to 12 volts). In this case, the current detection circuit (5) is required to have high voltage tolerance and insulation. Input side (inverter (10) side) and output side (inverter control device (20) and third current detection circuit (3) side) of the first current detection unit (1) and the second current detection unit (2) ) Are insulated from each other, the current detection circuit (5) after the output side of the first current detection unit (1) and the second current detection unit (2) can be configured as a general electronic circuit. . When the first operational amplifier (A1) included in the first current detector (1) and the second operational amplifier (A2) included in the second current detector (2) are isolation amplifiers (IA), The first current detection unit (1) and the second current detection unit (2) can appropriately ensure insulation and can simply configure the current detection circuit (5).

  In addition, as described above, the amplification factors of the first operational amplifier (A1) and the second operational amplifier (A2) are the same, and the first non-inverting output terminal (PO1) and the second inverting output terminal ( NO2) is connected to form a first addition node (n1), and the first inverting output terminal (NO1) and the second non-inverting output terminal (PO2) are connected to form a second addition node (n2). The first resistor (R1) is provided between the first non-inverting output terminal (PO1) and the first addition node (n1), and the second inverting output terminal (NO2) and the first A second resistor (R2) is provided between the first addition node (n1) and a third resistor (R3) is provided between the first inverted output terminal (NO1) and the second addition node (n2). The second non-inverting output terminal (PO2) and the second addition node (n2) A fourth resistor (R4) between the first resistor (R1), the second resistor (R2), the third resistor (R3), and the fourth resistor (R4). It is preferable that the resistance values are the same.

According to this configuration, signal processing is performed on two systems of signals (a voltage value indicating the first element current (I _H ) and a voltage value indicating the second element current (I _L )) before being differentially amplified under the same conditions. Thus, the difference can be obtained appropriately.

DESCRIPTION OF SYMBOLS 1 1st current detection part 2 2nd current detection part 3 3rd current detection part 5 Current detection circuit 10 Inverter 10a Arm 11 1st switching element 12 2nd switching element 20 Inverter control apparatus 21 A / D converter A1 1st operational amplifier A2 Second operational amplifier A3 Third operational amplifier DA Differential amplifier DI1 First differential input terminal DI2 Second differential input terminal DO Differential output terminal IA Isolation amplifier I _DS Drain-source current (element current)
I _H First element current I _L Second element current I _SNS sense current (a minute current proportional to the element current)
N negative electrode NI1 first inverting input terminal NI2 second inverting input terminal NO1 first inverting output terminal NO2 second inverting output terminal P positive electrode PI1 first non-inverting input terminal PI2 second non-inverting input terminal PO1 first non-inverting output terminal PO2 Second non-inverting output terminal R1 first resistor R2 second resistor R3 third resistor R4 fourth resistor T sense terminal T1 first sense terminal T2 second sense terminal V _NO1 first inversion voltage value V _NO2 second Inversion voltage value VO detection output value V _PO1 first voltage value V _PO2 second voltage value n1 first addition node n2 second addition node α amplification factor α1 first amplification factor α2 second amplification factor

Claims (4)

An arm in which the first switching element and the second switching element are connected in series is connected between a positive electrode and a negative electrode of a direct current to detect a current flowing through the arm of the inverter that converts power between the direct current and the alternating current. A current detection circuit,
Each of the first switching element and the second switching element has one control terminal, two input / output terminals, and a sense terminal through which a minute current proportional to an element current flowing between the input / output terminals flows. ,
A first current detector for detecting a magnitude of a current flowing through the first sense terminal, which is the sense terminal of the first switching element, as a voltage value, and outputting a first voltage value and a first inversion voltage value that are positive and negative symmetric; ,
A second current detector for detecting a magnitude of a current flowing through the second sense terminal, which is the sense terminal of the second switching element, as a voltage value, and outputting a positive and negative symmetric second voltage value and a second inverted voltage value; ,
The first voltage value and the second inverted voltage value are added, the first inverted voltage value and the second voltage value are added, and the inverter is subjected to switching control for the difference between the two voltage values after the addition. A third current detector provided to the inverter control device;
A current detection circuit comprising: The first current detector includes a first operational amplifier having a first non-inverting output terminal that outputs the first voltage value and a first inverting output terminal that outputs the first inverted voltage value.
The second current detection unit includes a second operational amplifier having a second non-inverting output terminal that outputs the second voltage value and a second inverting output terminal that outputs the second inverted voltage value;
The third current detection unit includes a differential amplifier having a first differential input terminal, a second differential input terminal, and a differential output terminal;
The amplification factors of the first operational amplifier and the second operational amplifier are the same,
The first non-inverting output terminal and the second non-inverting output terminal are connected to form a first addition node, and the first inverting output terminal and the second non-inverting output terminal are connected to form a second addition node. Form the
The first addition node is connected to the first differential input terminal, the second addition node is connected to the second differential input terminal, and the differential output terminal is connected to the inverter control device. Item 2. The current detection circuit according to Item 1.   The current detection circuit according to claim 2, wherein the first operational amplifier and the second operational amplifier are isolation amplifiers in which an input side and an output side are insulated. A first resistor provided between the first non-inverting output terminal and the first addition node;
A second resistor provided between the second inverting output terminal and the first addition node;
A third resistor is provided between the first inverting output terminal and the second addition node;
A fourth resistor is provided between the second non-inverting output terminal and the second addition node;
The current detection circuit according to claim 2 or 3, wherein resistance values of the first resistor, the second resistor, the third resistor, and the fourth resistor are the same.

Images